xref: /freebsd/sys/dev/mmc/mmcreg.h (revision 23833df4831a6f41aa39e952fba524edfb8cec6d)
1 /*-
2  * Copyright (c) 2006 M. Warner Losh.  All rights reserved.
3  * Copyright (c) 2017 Marius Strobl <marius@FreeBSD.org>
4  * Copyright (c) 2015-2016 Ilya Bakulin <kibab@FreeBSD.org>
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  *
26  * Portions of this software may have been developed with reference to
27  * the SD Simplified Specification.  The following disclaimer may apply:
28  *
29  * The following conditions apply to the release of the simplified
30  * specification ("Simplified Specification") by the SD Card Association and
31  * the SD Group. The Simplified Specification is a subset of the complete SD
32  * Specification which is owned by the SD Card Association and the SD
33  * Group. This Simplified Specification is provided on a non-confidential
34  * basis subject to the disclaimers below. Any implementation of the
35  * Simplified Specification may require a license from the SD Card
36  * Association, SD Group, SD-3C LLC or other third parties.
37  *
38  * Disclaimers:
39  *
40  * The information contained in the Simplified Specification is presented only
41  * as a standard specification for SD Cards and SD Host/Ancillary products and
42  * is provided "AS-IS" without any representations or warranties of any
43  * kind. No responsibility is assumed by the SD Group, SD-3C LLC or the SD
44  * Card Association for any damages, any infringements of patents or other
45  * right of the SD Group, SD-3C LLC, the SD Card Association or any third
46  * parties, which may result from its use. No license is granted by
47  * implication, estoppel or otherwise under any patent or other rights of the
48  * SD Group, SD-3C LLC, the SD Card Association or any third party. Nothing
49  * herein shall be construed as an obligation by the SD Group, the SD-3C LLC
50  * or the SD Card Association to disclose or distribute any technical
51  * information, know-how or other confidential information to any third party.
52  *
53  * $FreeBSD$
54  */
55 
56 #ifndef DEV_MMC_MMCREG_H
57 #define	DEV_MMC_MMCREG_H
58 
59 /*
60  * This file contains the register definitions for the mmc and sd buses.
61  * They are taken from publicly available sources.
62  */
63 
64 struct mmc_data;
65 struct mmc_request;
66 
67 struct mmc_command {
68 	uint32_t	opcode;
69 	uint32_t	arg;
70 	uint32_t	resp[4];
71 	uint32_t	flags;		/* Expected responses */
72 #define	MMC_RSP_PRESENT	(1ul << 0)	/* Response */
73 #define	MMC_RSP_136	(1ul << 1)	/* 136 bit response */
74 #define	MMC_RSP_CRC	(1ul << 2)	/* Expect valid crc */
75 #define	MMC_RSP_BUSY	(1ul << 3)	/* Card may send busy */
76 #define	MMC_RSP_OPCODE	(1ul << 4)	/* Response include opcode */
77 #define	MMC_RSP_MASK	0x1ful
78 #define	MMC_CMD_AC	(0ul << 5)	/* Addressed Command, no data */
79 #define	MMC_CMD_ADTC	(1ul << 5)	/* Addressed Data transfer cmd */
80 #define	MMC_CMD_BC	(2ul << 5)	/* Broadcast command, no response */
81 #define	MMC_CMD_BCR	(3ul << 5)	/* Broadcast command with response */
82 #define	MMC_CMD_MASK	(3ul << 5)
83 
84 /* Possible response types defined in the standard: */
85 #define	MMC_RSP_NONE	(0)
86 #define	MMC_RSP_R1	(MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
87 #define	MMC_RSP_R1B	(MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | MMC_RSP_BUSY)
88 #define	MMC_RSP_R2	(MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC)
89 #define	MMC_RSP_R3	(MMC_RSP_PRESENT)
90 #define	MMC_RSP_R4	(MMC_RSP_PRESENT)
91 #define	MMC_RSP_R5	(MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
92 #define	MMC_RSP_R5B	(MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | MMC_RSP_BUSY)
93 #define	MMC_RSP_R6	(MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
94 #define	MMC_RSP_R7	(MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
95 #define	MMC_RSP(x)	((x) & MMC_RSP_MASK)
96 	uint32_t	retries;
97 	uint32_t	error;
98 #define	MMC_ERR_NONE	0
99 #define	MMC_ERR_TIMEOUT	1
100 #define	MMC_ERR_BADCRC	2
101 #define	MMC_ERR_FIFO	3
102 #define	MMC_ERR_FAILED	4
103 #define	MMC_ERR_INVALID	5
104 #define	MMC_ERR_NO_MEMORY 6
105 #define	MMC_ERR_MAX	6
106 	struct mmc_data	*data;		/* Data segment with cmd */
107 	struct mmc_request *mrq;	/* backpointer to request */
108 };
109 
110 /*
111  * R1 responses
112  *
113  * Types (per SD 2.0 standard)
114  *	e : error bit
115  *	s : status bit
116  *	r : detected and set for the actual command response
117  *	x : Detected and set during command execution.  The host can get
118  *	    the status by issuing a command with R1 response.
119  *
120  * Clear Condition (per SD 2.0 standard)
121  *	a : according to the card current state.
122  *	b : always related to the previous command.  reception of a valid
123  *	    command will clear it (with a delay of one command).
124  *	c : clear by read
125  */
126 #define	R1_OUT_OF_RANGE (1u << 31)		/* erx, c */
127 #define	R1_ADDRESS_ERROR (1u << 30)		/* erx, c */
128 #define	R1_BLOCK_LEN_ERROR (1u << 29)		/* erx, c */
129 #define	R1_ERASE_SEQ_ERROR (1u << 28)		/* er, c */
130 #define	R1_ERASE_PARAM (1u << 27)		/* erx, c */
131 #define	R1_WP_VIOLATION (1u << 26)		/* erx, c */
132 #define	R1_CARD_IS_LOCKED (1u << 25)		/* sx, a */
133 #define	R1_LOCK_UNLOCK_FAILED (1u << 24)	/* erx, c */
134 #define	R1_COM_CRC_ERROR (1u << 23)		/* er, b */
135 #define	R1_ILLEGAL_COMMAND (1u << 22)		/* er, b */
136 #define	R1_CARD_ECC_FAILED (1u << 21)		/* erx, c */
137 #define	R1_CC_ERROR (1u << 20)			/* erx, c */
138 #define	R1_ERROR (1u << 19)			/* erx, c */
139 #define	R1_CSD_OVERWRITE (1u << 16)		/* erx, c */
140 #define	R1_WP_ERASE_SKIP (1u << 15)		/* erx, c */
141 #define	R1_CARD_ECC_DISABLED (1u << 14)		/* sx, a */
142 #define	R1_ERASE_RESET (1u << 13)		/* sr, c */
143 #define	R1_CURRENT_STATE_MASK (0xfu << 9)	/* sx, b */
144 #define	R1_READY_FOR_DATA (1u << 8)		/* sx, a */
145 #define	R1_SWITCH_ERROR (1u << 7)		/* sx, c */
146 #define	R1_APP_CMD (1u << 5)			/* sr, c */
147 #define	R1_AKE_SEQ_ERROR (1u << 3)		/* er, c */
148 #define	R1_STATUS(x)		((x) & 0xFFFFE000)
149 #define	R1_CURRENT_STATE(x)	(((x) & R1_CURRENT_STATE_MASK) >> 9)
150 #define	R1_STATE_IDLE	0
151 #define	R1_STATE_READY	1
152 #define	R1_STATE_IDENT	2
153 #define	R1_STATE_STBY	3
154 #define	R1_STATE_TRAN	4
155 #define	R1_STATE_DATA	5
156 #define	R1_STATE_RCV	6
157 #define	R1_STATE_PRG	7
158 #define	R1_STATE_DIS	8
159 
160 /* R4 response (SDIO) */
161 #define R4_IO_NUM_FUNCTIONS(ocr)	(((ocr) >> 28) & 0x3)
162 #define R4_IO_MEM_PRESENT		(0x1<<27)
163 #define R4_IO_OCR_MASK			0x00fffff0
164 
165 /*
166  * R5 responses
167  *
168  * Types (per SD 2.0 standard)
169  *e : error bit
170  *s : status bit
171  *r : detected and set for the actual command response
172  *x : Detected and set during command execution.  The host can get
173  *    the status by issuing a command with R1 response.
174  *
175  * Clear Condition (per SD 2.0 standard)
176  *a : according to the card current state.
177  *b : always related to the previous command.  reception of a valid
178  *    command will clear it (with a delay of one command).
179  *c : clear by read
180  */
181 #define R5_COM_CRC_ERROR		(1u << 15)/* er, b */
182 #define R5_ILLEGAL_COMMAND		(1u << 14)/* er, b */
183 #define R5_IO_CURRENT_STATE_MASK	(3u << 12)/* s, b */
184 #define R5_IO_CURRENT_STATE(x) 		(((x) & R5_IO_CURRENT_STATE_MASK) >> 12)
185 #define R5_ERROR			(1u << 11)/* erx, c */
186 #define R5_FUNCTION_NUMBER		(1u << 9)/* er, c */
187 #define R5_OUT_OF_RANGE			(1u << 8)/* er, c */
188 struct mmc_data {
189 	size_t len;		/* size of the data */
190 	size_t xfer_len;
191 	void *data;		/* data buffer */
192 	uint32_t	flags;
193 #define	MMC_DATA_WRITE	(1UL << 0)
194 #define	MMC_DATA_READ	(1UL << 1)
195 #define	MMC_DATA_STREAM	(1UL << 2)
196 #define	MMC_DATA_MULTI	(1UL << 3)
197 	struct mmc_request *mrq;
198 };
199 
200 struct mmc_request {
201 	struct mmc_command *cmd;
202 	struct mmc_command *stop;
203 	void (*done)(struct mmc_request *); /* Completion function */
204 	void *done_data;		/* requestor set data */
205 	uint32_t flags;
206 #define	MMC_REQ_DONE	1
207 #define	MMC_TUNE_DONE	2
208 };
209 
210 /* Command definitions */
211 
212 /* Class 0 and 1: Basic commands & read stream commands */
213 #define	MMC_GO_IDLE_STATE	0
214 #define	MMC_SEND_OP_COND	1
215 #define	MMC_ALL_SEND_CID	2
216 #define	MMC_SET_RELATIVE_ADDR	3
217 #define	SD_SEND_RELATIVE_ADDR	3
218 #define	MMC_SET_DSR		4
219 #define	MMC_SLEEP_AWAKE		5
220 #define IO_SEND_OP_COND		5
221 #define	MMC_SWITCH_FUNC		6
222 #define	 MMC_SWITCH_FUNC_CMDS	 0
223 #define	 MMC_SWITCH_FUNC_SET	 1
224 #define	 MMC_SWITCH_FUNC_CLR	 2
225 #define	 MMC_SWITCH_FUNC_WR	 3
226 #define	MMC_SELECT_CARD		7
227 #define	MMC_DESELECT_CARD	7
228 #define	MMC_SEND_EXT_CSD	8
229 #define	SD_SEND_IF_COND		8
230 #define	MMC_SEND_CSD		9
231 #define	MMC_SEND_CID		10
232 #define	MMC_READ_DAT_UNTIL_STOP	11
233 #define	MMC_STOP_TRANSMISSION	12
234 #define	MMC_SEND_STATUS		13
235 #define	MMC_BUSTEST_R		14
236 #define	MMC_GO_INACTIVE_STATE	15
237 #define	MMC_BUSTEST_W		19
238 
239 /* Class 2: Block oriented read commands */
240 #define	MMC_SET_BLOCKLEN	16
241 #define	MMC_READ_SINGLE_BLOCK	17
242 #define	MMC_READ_MULTIPLE_BLOCK	18
243 #define	MMC_SEND_TUNING_BLOCK	19
244 #define	MMC_SEND_TUNING_BLOCK_HS200 21
245 
246 /* Class 3: Stream write commands */
247 #define	MMC_WRITE_DAT_UNTIL_STOP 20
248 			/* reserved: 22 */
249 
250 /* Class 4: Block oriented write commands */
251 #define	MMC_SET_BLOCK_COUNT	23
252 #define	MMC_WRITE_BLOCK		24
253 #define	MMC_WRITE_MULTIPLE_BLOCK 25
254 #define	MMC_PROGARM_CID		26
255 #define	MMC_PROGRAM_CSD		27
256 
257 /* Class 6: Block oriented write protection commands */
258 #define	MMC_SET_WRITE_PROT	28
259 #define	MMC_CLR_WRITE_PROT	29
260 #define	MMC_SEND_WRITE_PROT	30
261 			/* reserved: 31 */
262 
263 /* Class 5: Erase commands */
264 #define	SD_ERASE_WR_BLK_START	32
265 #define	SD_ERASE_WR_BLK_END	33
266 			/* 34 -- reserved old command */
267 #define	MMC_ERASE_GROUP_START	35
268 #define	MMC_ERASE_GROUP_END	36
269 			/* 37 -- reserved old command */
270 #define	MMC_ERASE		38
271 
272 /* Class 9: I/O mode commands */
273 #define	MMC_FAST_IO		39
274 #define	MMC_GO_IRQ_STATE	40
275 			/* reserved: 41 */
276 
277 /* Class 7: Lock card */
278 #define	MMC_LOCK_UNLOCK		42
279 			/* reserved: 43 */
280 			/* reserved: 44 */
281 			/* reserved: 45 */
282 			/* reserved: 46 */
283 			/* reserved: 47 */
284 			/* reserved: 48 */
285 			/* reserved: 49 */
286 			/* reserved: 50 */
287 			/* reserved: 51 */
288 			/* reserved: 54 */
289 
290 /* Class 8: Application specific commands */
291 #define	MMC_APP_CMD		55
292 #define	MMC_GEN_CMD		56
293 			/* reserved: 57 */
294 			/* reserved: 58 */
295 			/* reserved: 59 */
296 			/* reserved for mfg: 60 */
297 			/* reserved for mfg: 61 */
298 			/* reserved for mfg: 62 */
299 			/* reserved for mfg: 63 */
300 
301 /* Class 9: I/O cards (sd) */
302 #define	SD_IO_RW_DIRECT		52
303 /* CMD52 arguments */
304 #define  SD_ARG_CMD52_READ		(0<<31)
305 #define  SD_ARG_CMD52_WRITE		(1<<31)
306 #define  SD_ARG_CMD52_FUNC_SHIFT		28
307 #define  SD_ARG_CMD52_FUNC_MASK		0x7
308 #define  SD_ARG_CMD52_EXCHANGE		(1<<27)
309 #define  SD_ARG_CMD52_REG_SHIFT		9
310 #define  SD_ARG_CMD52_REG_MASK		0x1ffff
311 #define  SD_ARG_CMD52_DATA_SHIFT		0
312 #define  SD_ARG_CMD52_DATA_MASK		0xff
313 #define  SD_R5_DATA(resp)		((resp)[0] & 0xff)
314 
315 #define	SD_IO_RW_EXTENDED	53
316 /* CMD53 arguments */
317 #define  SD_ARG_CMD53_READ		(0<<31)
318 #define  SD_ARG_CMD53_WRITE		(1<<31)
319 #define  SD_ARG_CMD53_FUNC_SHIFT		28
320 #define  SD_ARG_CMD53_FUNC_MASK		0x7
321 #define  SD_ARG_CMD53_BLOCK_MODE		(1<<27)
322 #define  SD_ARG_CMD53_INCREMENT		(1<<26)
323 #define  SD_ARG_CMD53_REG_SHIFT		9
324 #define  SD_ARG_CMD53_REG_MASK		0x1ffff
325 #define  SD_ARG_CMD53_LENGTH_SHIFT	0
326 #define  SD_ARG_CMD53_LENGTH_MASK	0x1ff
327 #define  SD_ARG_CMD53_LENGTH_MAX		64 /* XXX should be 511? */
328 
329 /* Class 10: Switch function commands */
330 #define	SD_SWITCH_FUNC		6
331 			/* reserved: 34 */
332 			/* reserved: 35 */
333 			/* reserved: 36 */
334 			/* reserved: 37 */
335 			/* reserved: 50 */
336 			/* reserved: 57 */
337 
338 /* Application specific commands for SD */
339 #define	ACMD_SET_BUS_WIDTH	6
340 #define	ACMD_SD_STATUS		13
341 #define	ACMD_SEND_NUM_WR_BLOCKS	22
342 #define	ACMD_SET_WR_BLK_ERASE_COUNT 23
343 #define	ACMD_SD_SEND_OP_COND	41
344 #define	ACMD_SET_CLR_CARD_DETECT 42
345 #define	ACMD_SEND_SCR		51
346 
347 /*
348  * EXT_CSD fields
349  */
350 #define	EXT_CSD_EXT_PART_ATTR	52	/* R/W, 2 bytes */
351 #define	EXT_CSD_ENH_START_ADDR	136	/* R/W, 4 bytes */
352 #define	EXT_CSD_ENH_SIZE_MULT	140	/* R/W, 3 bytes */
353 #define	EXT_CSD_GP_SIZE_MULT	143	/* R/W, 12 bytes */
354 #define	EXT_CSD_PART_SET	155	/* R/W */
355 #define	EXT_CSD_PART_ATTR	156	/* R/W */
356 #define	EXT_CSD_PART_SUPPORT	160	/* RO */
357 #define	EXT_CSD_RPMB_MULT	168	/* RO */
358 #define	EXT_CSD_BOOT_WP_STATUS	174	/* RO */
359 #define	EXT_CSD_ERASE_GRP_DEF	175	/* R/W */
360 #define	EXT_CSD_PART_CONFIG	179	/* R/W */
361 #define	EXT_CSD_BUS_WIDTH	183	/* R/W */
362 #define	EXT_CSD_STROBE_SUPPORT	184	/* RO */
363 #define	EXT_CSD_HS_TIMING	185	/* R/W */
364 #define	EXT_CSD_POWER_CLASS	187	/* R/W */
365 #define	EXT_CSD_CARD_TYPE	196	/* RO */
366 #define	EXT_CSD_DRIVER_STRENGTH	197	/* RO */
367 #define	EXT_CSD_REV		192	/* RO */
368 #define	EXT_CSD_PART_SWITCH_TO	199	/* RO */
369 #define	EXT_CSD_PWR_CL_52_195	200	/* RO */
370 #define	EXT_CSD_PWR_CL_26_195	201	/* RO */
371 #define	EXT_CSD_PWR_CL_52_360	202	/* RO */
372 #define	EXT_CSD_PWR_CL_26_360	203	/* RO */
373 #define	EXT_CSD_SEC_CNT		212	/* RO, 4 bytes */
374 #define	EXT_CSD_HC_WP_GRP_SIZE	221	/* RO */
375 #define	EXT_CSD_ERASE_TO_MULT	223	/* RO */
376 #define	EXT_CSD_ERASE_GRP_SIZE	224	/* RO */
377 #define	EXT_CSD_BOOT_SIZE_MULT	226	/* RO */
378 #define	EXT_CSD_PWR_CL_200_195	236	/* RO */
379 #define	EXT_CSD_PWR_CL_200_360	237	/* RO */
380 #define	EXT_CSD_PWR_CL_52_195_DDR 238	/* RO */
381 #define	EXT_CSD_PWR_CL_52_360_DDR 239	/* RO */
382 #define	EXT_CSD_GEN_CMD6_TIME	248	/* RO */
383 #define	EXT_CSD_PWR_CL_200_360_DDR 253	/* RO */
384 
385 /*
386  * EXT_CSD field definitions
387  */
388 #define	EXT_CSD_EXT_PART_ATTR_DEFAULT		0x0
389 #define	EXT_CSD_EXT_PART_ATTR_SYSTEMCODE	0x1
390 #define	EXT_CSD_EXT_PART_ATTR_NPERSISTENT	0x2
391 
392 #define	EXT_CSD_PART_SET_COMPLETED		0x01
393 
394 #define	EXT_CSD_PART_ATTR_ENH_USR		0x01
395 #define	EXT_CSD_PART_ATTR_ENH_GP0		0x02
396 #define	EXT_CSD_PART_ATTR_ENH_GP1		0x04
397 #define	EXT_CSD_PART_ATTR_ENH_GP2		0x08
398 #define	EXT_CSD_PART_ATTR_ENH_GP3		0x10
399 #define	EXT_CSD_PART_ATTR_ENH_MASK		0x1f
400 
401 #define	EXT_CSD_PART_SUPPORT_EN			0x01
402 #define	EXT_CSD_PART_SUPPORT_ENH_ATTR_EN	0x02
403 #define	EXT_CSD_PART_SUPPORT_EXT_ATTR_EN	0x04
404 
405 #define	EXT_CSD_BOOT_WP_STATUS_BOOT0_PWR	0x01
406 #define	EXT_CSD_BOOT_WP_STATUS_BOOT0_PERM	0x02
407 #define	EXT_CSD_BOOT_WP_STATUS_BOOT0_MASK	0x03
408 #define	EXT_CSD_BOOT_WP_STATUS_BOOT1_PWR	0x04
409 #define	EXT_CSD_BOOT_WP_STATUS_BOOT1_PERM	0x08
410 #define	EXT_CSD_BOOT_WP_STATUS_BOOT1_MASK	0x0c
411 
412 #define	EXT_CSD_ERASE_GRP_DEF_EN	0x01
413 
414 #define	EXT_CSD_PART_CONFIG_ACC_DEFAULT	0x00
415 #define	EXT_CSD_PART_CONFIG_ACC_BOOT0	0x01
416 #define	EXT_CSD_PART_CONFIG_ACC_BOOT1	0x02
417 #define	EXT_CSD_PART_CONFIG_ACC_RPMB	0x03
418 #define	EXT_CSD_PART_CONFIG_ACC_GP0	0x04
419 #define	EXT_CSD_PART_CONFIG_ACC_GP1	0x05
420 #define	EXT_CSD_PART_CONFIG_ACC_GP2	0x06
421 #define	EXT_CSD_PART_CONFIG_ACC_GP3	0x07
422 #define	EXT_CSD_PART_CONFIG_ACC_MASK	0x07
423 #define	EXT_CSD_PART_CONFIG_BOOT0	0x08
424 #define	EXT_CSD_PART_CONFIG_BOOT1	0x10
425 #define	EXT_CSD_PART_CONFIG_BOOT_USR	0x38
426 #define	EXT_CSD_PART_CONFIG_BOOT_MASK	0x38
427 #define	EXT_CSD_PART_CONFIG_BOOT_ACK	0x40
428 
429 #define	EXT_CSD_CMD_SET_NORMAL		1
430 #define	EXT_CSD_CMD_SET_SECURE		2
431 #define	EXT_CSD_CMD_SET_CPSECURE	4
432 
433 #define	EXT_CSD_HS_TIMING_BC		0
434 #define	EXT_CSD_HS_TIMING_HS		1
435 #define	EXT_CSD_HS_TIMING_HS200		2
436 #define	EXT_CSD_HS_TIMING_HS400		3
437 #define	EXT_CSD_HS_TIMING_DRV_STR_SHIFT	4
438 
439 #define	EXT_CSD_POWER_CLASS_8BIT_MASK	0xf0
440 #define	EXT_CSD_POWER_CLASS_8BIT_SHIFT	4
441 #define	EXT_CSD_POWER_CLASS_4BIT_MASK	0x0f
442 #define	EXT_CSD_POWER_CLASS_4BIT_SHIFT	0
443 
444 #define	EXT_CSD_CARD_TYPE_HS_26		0x0001
445 #define	EXT_CSD_CARD_TYPE_HS_52		0x0002
446 #define	EXT_CSD_CARD_TYPE_DDR_52_1_8V	0x0004
447 #define	EXT_CSD_CARD_TYPE_DDR_52_1_2V	0x0008
448 #define	EXT_CSD_CARD_TYPE_HS200_1_8V	0x0010
449 #define	EXT_CSD_CARD_TYPE_HS200_1_2V	0x0020
450 #define	EXT_CSD_CARD_TYPE_HS400_1_8V	0x0040
451 #define	EXT_CSD_CARD_TYPE_HS400_1_2V	0x0080
452 
453 #define	EXT_CSD_BUS_WIDTH_1	0
454 #define	EXT_CSD_BUS_WIDTH_4	1
455 #define	EXT_CSD_BUS_WIDTH_8	2
456 #define	EXT_CSD_BUS_WIDTH_4_DDR	5
457 #define	EXT_CSD_BUS_WIDTH_8_DDR	6
458 #define	EXT_CSD_BUS_WIDTH_ES	0x80
459 
460 #define	EXT_CSD_STROBE_SUPPORT_EN	0x01
461 
462 #define	MMC_TYPE_HS_26_MAX		26000000
463 #define	MMC_TYPE_HS_52_MAX		52000000
464 #define	MMC_TYPE_DDR52_MAX		52000000
465 #define	MMC_TYPE_HS200_HS400ES_MAX	200000000
466 
467 /*
468  * SD bus widths
469  */
470 #define	SD_BUS_WIDTH_1		0
471 #define	SD_BUS_WIDTH_4		2
472 
473 /*
474  * SD Switch
475  */
476 #define	SD_SWITCH_MODE_CHECK	0
477 #define	SD_SWITCH_MODE_SET	1
478 #define	SD_SWITCH_GROUP1	0
479 #define	SD_SWITCH_NORMAL_MODE	0
480 #define	SD_SWITCH_HS_MODE	1
481 #define	SD_SWITCH_SDR50_MODE	2
482 #define	SD_SWITCH_SDR104_MODE	3
483 #define	SD_SWITCH_DDR50		4
484 #define	SD_SWITCH_NOCHANGE	0xF
485 
486 #define	SD_CLR_CARD_DETECT	0
487 #define	SD_SET_CARD_DETECT	1
488 
489 #define	SD_HS_MAX		50000000
490 #define	SD_DDR50_MAX		50000000
491 #define	SD_SDR12_MAX		25000000
492 #define	SD_SDR25_MAX		50000000
493 #define	SD_SDR50_MAX		100000000
494 #define	SD_SDR104_MAX		208000000
495 
496 /* Specifications require 400 kHz max. during ID phase. */
497 #define	SD_MMC_CARD_ID_FREQUENCY	400000
498 
499 /*
500  * SDIO Direct & Extended I/O
501  */
502 #define SD_IO_RW_WR		(1u << 31)
503 #define SD_IO_RW_FUNC(x)	(((x) & 0x7) << 28)
504 #define SD_IO_RW_RAW		(1u << 27)
505 #define SD_IO_RW_INCR		(1u << 26)
506 #define SD_IO_RW_ADR(x)		(((x) & 0x1FFFF) << 9)
507 #define SD_IO_RW_DAT(x)		(((x) & 0xFF) << 0)
508 #define SD_IO_RW_LEN(x)		(((x) & 0xFF) << 0)
509 
510 #define SD_IOE_RW_LEN(x)	(((x) & 0x1FF) << 0)
511 #define SD_IOE_RW_BLK		(1u << 27)
512 
513 /* Card Common Control Registers (CCCR) */
514 #define SD_IO_CCCR_START		0x00000
515 #define SD_IO_CCCR_SIZE			0x100
516 #define SD_IO_CCCR_FN_ENABLE		0x02
517 #define SD_IO_CCCR_FN_READY		0x03
518 #define SD_IO_CCCR_INT_ENABLE		0x04
519 #define SD_IO_CCCR_INT_PENDING		0x05
520 #define SD_IO_CCCR_CTL			0x06
521 #define  CCCR_CTL_RES			(1<<3)
522 #define SD_IO_CCCR_BUS_WIDTH		0x07
523 #define  CCCR_BUS_WIDTH_4		(1<<1)
524 #define  CCCR_BUS_WIDTH_1		(1<<0)
525 #define SD_IO_CCCR_CARDCAP		0x08
526 #define SD_IO_CCCR_CISPTR		0x09 /* XXX 9-10, 10-11, or 9-12 */
527 
528 /* Function Basic Registers (FBR) */
529 #define SD_IO_FBR_START			0x00100
530 #define SD_IO_FBR_SIZE			0x00700
531 
532 /* Card Information Structure (CIS) */
533 #define SD_IO_CIS_START			0x01000
534 #define SD_IO_CIS_SIZE			0x17000
535 
536 /* CIS tuple codes (based on PC Card 16) */
537 #define SD_IO_CISTPL_VERS_1		0x15
538 #define SD_IO_CISTPL_MANFID		0x20
539 #define SD_IO_CISTPL_FUNCID		0x21
540 #define SD_IO_CISTPL_FUNCE		0x22
541 #define SD_IO_CISTPL_END		0xff
542 
543 /* CISTPL_FUNCID codes */
544 /* OpenBSD incorrectly defines 0x0c as FUNCTION_WLAN */
545 /* #define SDMMC_FUNCTION_WLAN		0x0c */
546 
547 /* OCR bits */
548 
549 /*
550  * in SD 2.0 spec, bits 8-14 are now marked reserved
551  * Low voltage in SD2.0 spec is bit 7, TBD voltage
552  * Low voltage in MC 3.31 spec is bit 7, 1.65-1.95V
553  * Specs prior to  MMC 3.31 defined bits 0-7 as voltages down to 1.5V.
554  * 3.31 redefined them to be reserved and also said that cards had to
555  * support the 2.7-3.6V and fixed the OCR to be 0xfff8000 for high voltage
556  * cards.  MMC 4.0 says that a dual voltage card responds with 0xfff8080.
557  * Looks like the fine-grained control of the voltage tolerance ranges
558  * was abandoned.
559  *
560  * The MMC_OCR_CCS appears to be valid for only SD cards.
561  */
562 #define	MMC_OCR_VOLTAGE	0x3fffffffU	/* Vdd Voltage mask */
563 #define	MMC_OCR_LOW_VOLTAGE (1u << 7)	/* Low Voltage Range -- tbd */
564 #define	MMC_OCR_MIN_VOLTAGE_SHIFT	7
565 #define	MMC_OCR_200_210	(1U << 8)	/* Vdd voltage 2.00 ~ 2.10 */
566 #define	MMC_OCR_210_220	(1U << 9)	/* Vdd voltage 2.10 ~ 2.20 */
567 #define	MMC_OCR_220_230	(1U << 10)	/* Vdd voltage 2.20 ~ 2.30 */
568 #define	MMC_OCR_230_240	(1U << 11)	/* Vdd voltage 2.30 ~ 2.40 */
569 #define	MMC_OCR_240_250	(1U << 12)	/* Vdd voltage 2.40 ~ 2.50 */
570 #define	MMC_OCR_250_260	(1U << 13)	/* Vdd voltage 2.50 ~ 2.60 */
571 #define	MMC_OCR_260_270	(1U << 14)	/* Vdd voltage 2.60 ~ 2.70 */
572 #define	MMC_OCR_270_280	(1U << 15)	/* Vdd voltage 2.70 ~ 2.80 */
573 #define	MMC_OCR_280_290	(1U << 16)	/* Vdd voltage 2.80 ~ 2.90 */
574 #define	MMC_OCR_290_300	(1U << 17)	/* Vdd voltage 2.90 ~ 3.00 */
575 #define	MMC_OCR_300_310	(1U << 18)	/* Vdd voltage 3.00 ~ 3.10 */
576 #define	MMC_OCR_310_320	(1U << 19)	/* Vdd voltage 3.10 ~ 3.20 */
577 #define	MMC_OCR_320_330	(1U << 20)	/* Vdd voltage 3.20 ~ 3.30 */
578 #define	MMC_OCR_330_340	(1U << 21)	/* Vdd voltage 3.30 ~ 3.40 */
579 #define	MMC_OCR_340_350	(1U << 22)	/* Vdd voltage 3.40 ~ 3.50 */
580 #define	MMC_OCR_350_360	(1U << 23)	/* Vdd voltage 3.50 ~ 3.60 */
581 #define	MMC_OCR_MAX_VOLTAGE_SHIFT	23
582 #define	MMC_OCR_S18R	(1U << 24)	/* Switching to 1.8 V requested (SD) */
583 #define	MMC_OCR_S18A	MMC_OCR_S18R	/* Switching to 1.8 V accepted (SD) */
584 #define	MMC_OCR_XPC	(1U << 28)	/* SDXC Power Control */
585 #define	MMC_OCR_ACCESS_MODE_BYTE (0U << 29) /* Access Mode Byte (MMC) */
586 #define	MMC_OCR_ACCESS_MODE_SECT (1U << 29) /* Access Mode Sector (MMC) */
587 #define	MMC_OCR_ACCESS_MODE_MASK (3U << 29)
588 #define	MMC_OCR_CCS	(1u << 30)	/* Card Capacity status (SD vs SDHC) */
589 #define	MMC_OCR_CARD_BUSY (1U << 31)	/* Card Power up status */
590 
591 /* CSD -- decoded structure */
592 struct mmc_cid {
593 	uint32_t mid;
594 	char pnm[8];
595 	uint32_t psn;
596 	uint16_t oid;
597 	uint16_t mdt_year;
598 	uint8_t mdt_month;
599 	uint8_t prv;
600 	uint8_t fwrev;
601 };
602 
603 struct mmc_csd
604 {
605 	uint8_t csd_structure;
606 	uint8_t spec_vers;
607 	uint16_t ccc;
608 	uint16_t tacc;
609 	uint32_t nsac;
610 	uint32_t r2w_factor;
611 	uint32_t tran_speed;
612 	uint32_t read_bl_len;
613 	uint32_t write_bl_len;
614 	uint32_t vdd_r_curr_min;
615 	uint32_t vdd_r_curr_max;
616 	uint32_t vdd_w_curr_min;
617 	uint32_t vdd_w_curr_max;
618 	uint32_t wp_grp_size;
619 	uint32_t erase_sector;
620 	uint64_t capacity;
621 	unsigned int read_bl_partial:1,
622 	    read_blk_misalign:1,
623 	    write_bl_partial:1,
624 	    write_blk_misalign:1,
625 	    dsr_imp:1,
626 	    erase_blk_en:1,
627 	    wp_grp_enable:1;
628 };
629 
630 struct mmc_scr
631 {
632 	unsigned char		sda_vsn;
633 	unsigned char		bus_widths;
634 #define	SD_SCR_BUS_WIDTH_1	(1 << 0)
635 #define	SD_SCR_BUS_WIDTH_4	(1 << 2)
636 };
637 
638 struct mmc_sd_status
639 {
640 	uint8_t			bus_width;
641 	uint8_t			secured_mode;
642 	uint16_t		card_type;
643 	uint16_t		prot_area;
644 	uint8_t			speed_class;
645 	uint8_t			perf_move;
646 	uint8_t			au_size;
647 	uint16_t		erase_size;
648 	uint8_t			erase_timeout;
649 	uint8_t			erase_offset;
650 };
651 
652 /*
653  * Various MMC/SD constants
654  */
655 #define	MMC_BOOT_RPMB_BLOCK_SIZE	(128 * 1024)
656 
657 #define	MMC_EXTCSD_SIZE	512
658 
659 #define	MMC_PART_GP_MAX	4
660 #define	MMC_PART_MAX	8
661 
662 #define	MMC_TUNING_MAX		64	/* Maximum tuning iterations */
663 #define	MMC_TUNING_LEN		64	/* Size of tuning data */
664 #define	MMC_TUNING_LEN_HS200	128	/* Size of tuning data in HS200 mode */
665 
666 /*
667  * Older versions of the MMC standard had a variable sector size.  However,
668  * I've been able to find no old MMC or SD cards that have a non 512
669  * byte sector size anywhere, so we assume that such cards are very rare
670  * and only note their existence in passing here...
671  */
672 #define	MMC_SECTOR_SIZE	512
673 
674 #endif /* DEV_MMCREG_H */
675