1 /*- 2 * Copyright (c) 2014-2019 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Synopsys DesignWare Mobile Storage Host Controller 33 * Chapter 14, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22) 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/bus.h> 42 #include <sys/kernel.h> 43 #include <sys/lock.h> 44 #include <sys/module.h> 45 #include <sys/malloc.h> 46 #include <sys/mutex.h> 47 #include <sys/rman.h> 48 #include <sys/queue.h> 49 #include <sys/taskqueue.h> 50 51 #include <dev/mmc/bridge.h> 52 #include <dev/mmc/mmcbrvar.h> 53 54 #include <dev/fdt/fdt_common.h> 55 #include <dev/ofw/openfirm.h> 56 #include <dev/ofw/ofw_bus.h> 57 #include <dev/ofw/ofw_bus_subr.h> 58 59 #include <machine/bus.h> 60 #include <machine/cpu.h> 61 #include <machine/intr.h> 62 63 #ifdef EXT_RESOURCES 64 #include <dev/extres/clk/clk.h> 65 #endif 66 67 #include <dev/mmc/host/dwmmc_reg.h> 68 #include <dev/mmc/host/dwmmc_var.h> 69 70 #include "mmcbr_if.h" 71 72 #define dprintf(x, arg...) 73 74 #define READ4(_sc, _reg) \ 75 bus_read_4((_sc)->res[0], _reg) 76 #define WRITE4(_sc, _reg, _val) \ 77 bus_write_4((_sc)->res[0], _reg, _val) 78 79 #define DIV_ROUND_UP(n, d) howmany(n, d) 80 81 #define DWMMC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 82 #define DWMMC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 83 #define DWMMC_LOCK_INIT(_sc) \ 84 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 85 "dwmmc", MTX_DEF) 86 #define DWMMC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 87 #define DWMMC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 88 #define DWMMC_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 89 90 #define PENDING_CMD 0x01 91 #define PENDING_STOP 0x02 92 #define CARD_INIT_DONE 0x04 93 94 #define DWMMC_DATA_ERR_FLAGS (SDMMC_INTMASK_DRT | SDMMC_INTMASK_DCRC \ 95 |SDMMC_INTMASK_HTO | SDMMC_INTMASK_SBE \ 96 |SDMMC_INTMASK_EBE) 97 #define DWMMC_CMD_ERR_FLAGS (SDMMC_INTMASK_RTO | SDMMC_INTMASK_RCRC \ 98 |SDMMC_INTMASK_RE) 99 #define DWMMC_ERR_FLAGS (DWMMC_DATA_ERR_FLAGS | DWMMC_CMD_ERR_FLAGS \ 100 |SDMMC_INTMASK_HLE) 101 102 #define DES0_DIC (1 << 1) /* Disable Interrupt on Completion */ 103 #define DES0_LD (1 << 2) /* Last Descriptor */ 104 #define DES0_FS (1 << 3) /* First Descriptor */ 105 #define DES0_CH (1 << 4) /* second address CHained */ 106 #define DES0_ER (1 << 5) /* End of Ring */ 107 #define DES0_CES (1 << 30) /* Card Error Summary */ 108 #define DES0_OWN (1 << 31) /* OWN */ 109 110 #define DES1_BS1_MASK 0x1fff 111 112 struct idmac_desc { 113 uint32_t des0; /* control */ 114 uint32_t des1; /* bufsize */ 115 uint32_t des2; /* buf1 phys addr */ 116 uint32_t des3; /* buf2 phys addr or next descr */ 117 }; 118 119 #define IDMAC_DESC_SEGS (PAGE_SIZE / (sizeof(struct idmac_desc))) 120 #define IDMAC_DESC_SIZE (sizeof(struct idmac_desc) * IDMAC_DESC_SEGS) 121 #define DEF_MSIZE 0x2 /* Burst size of multiple transaction */ 122 #define IDMAC_MAX_SIZE 4096 123 124 static void dwmmc_next_operation(struct dwmmc_softc *); 125 static int dwmmc_setup_bus(struct dwmmc_softc *, int); 126 static int dma_done(struct dwmmc_softc *, struct mmc_command *); 127 static int dma_stop(struct dwmmc_softc *); 128 static void pio_read(struct dwmmc_softc *, struct mmc_command *); 129 static void pio_write(struct dwmmc_softc *, struct mmc_command *); 130 static void dwmmc_handle_card_present(struct dwmmc_softc *sc, bool is_present); 131 132 static struct resource_spec dwmmc_spec[] = { 133 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 134 { SYS_RES_IRQ, 0, RF_ACTIVE }, 135 { -1, 0 } 136 }; 137 138 #define HWTYPE_MASK (0x0000ffff) 139 #define HWFLAG_MASK (0xffff << 16) 140 141 static void 142 dwmmc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 143 { 144 145 if (error != 0) 146 return; 147 *(bus_addr_t *)arg = segs[0].ds_addr; 148 } 149 150 static void 151 dwmmc_ring_setup(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 152 { 153 struct dwmmc_softc *sc; 154 int idx; 155 156 if (error != 0) 157 return; 158 159 sc = arg; 160 161 dprintf("nsegs %d seg0len %lu\n", nsegs, segs[0].ds_len); 162 163 for (idx = 0; idx < nsegs; idx++) { 164 sc->desc_ring[idx].des0 = (DES0_OWN | DES0_DIC | DES0_CH); 165 sc->desc_ring[idx].des1 = segs[idx].ds_len & DES1_BS1_MASK; 166 sc->desc_ring[idx].des2 = segs[idx].ds_addr; 167 168 if (idx == 0) 169 sc->desc_ring[idx].des0 |= DES0_FS; 170 171 if (idx == (nsegs - 1)) { 172 sc->desc_ring[idx].des0 &= ~(DES0_DIC | DES0_CH); 173 sc->desc_ring[idx].des0 |= DES0_LD; 174 } 175 } 176 } 177 178 static int 179 dwmmc_ctrl_reset(struct dwmmc_softc *sc, int reset_bits) 180 { 181 int reg; 182 int i; 183 184 reg = READ4(sc, SDMMC_CTRL); 185 reg |= (reset_bits); 186 WRITE4(sc, SDMMC_CTRL, reg); 187 188 /* Wait reset done */ 189 for (i = 0; i < 100; i++) { 190 if (!(READ4(sc, SDMMC_CTRL) & reset_bits)) 191 return (0); 192 DELAY(10); 193 } 194 195 device_printf(sc->dev, "Reset failed\n"); 196 197 return (1); 198 } 199 200 static int 201 dma_setup(struct dwmmc_softc *sc) 202 { 203 int error; 204 int nidx; 205 int idx; 206 207 /* 208 * Set up TX descriptor ring, descriptors, and dma maps. 209 */ 210 error = bus_dma_tag_create( 211 bus_get_dma_tag(sc->dev), /* Parent tag. */ 212 4096, 0, /* alignment, boundary */ 213 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 214 BUS_SPACE_MAXADDR, /* highaddr */ 215 NULL, NULL, /* filter, filterarg */ 216 IDMAC_DESC_SIZE, 1, /* maxsize, nsegments */ 217 IDMAC_DESC_SIZE, /* maxsegsize */ 218 0, /* flags */ 219 NULL, NULL, /* lockfunc, lockarg */ 220 &sc->desc_tag); 221 if (error != 0) { 222 device_printf(sc->dev, 223 "could not create ring DMA tag.\n"); 224 return (1); 225 } 226 227 error = bus_dmamem_alloc(sc->desc_tag, (void**)&sc->desc_ring, 228 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 229 &sc->desc_map); 230 if (error != 0) { 231 device_printf(sc->dev, 232 "could not allocate descriptor ring.\n"); 233 return (1); 234 } 235 236 error = bus_dmamap_load(sc->desc_tag, sc->desc_map, 237 sc->desc_ring, IDMAC_DESC_SIZE, dwmmc_get1paddr, 238 &sc->desc_ring_paddr, 0); 239 if (error != 0) { 240 device_printf(sc->dev, 241 "could not load descriptor ring map.\n"); 242 return (1); 243 } 244 245 for (idx = 0; idx < IDMAC_DESC_SEGS; idx++) { 246 sc->desc_ring[idx].des0 = DES0_CH; 247 sc->desc_ring[idx].des1 = 0; 248 nidx = (idx + 1) % IDMAC_DESC_SEGS; 249 sc->desc_ring[idx].des3 = sc->desc_ring_paddr + \ 250 (nidx * sizeof(struct idmac_desc)); 251 } 252 sc->desc_ring[idx - 1].des3 = sc->desc_ring_paddr; 253 sc->desc_ring[idx - 1].des0 |= DES0_ER; 254 255 error = bus_dma_tag_create( 256 bus_get_dma_tag(sc->dev), /* Parent tag. */ 257 CACHE_LINE_SIZE, 0, /* alignment, boundary */ 258 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 259 BUS_SPACE_MAXADDR, /* highaddr */ 260 NULL, NULL, /* filter, filterarg */ 261 IDMAC_MAX_SIZE * IDMAC_DESC_SEGS, /* maxsize */ 262 IDMAC_DESC_SEGS, /* nsegments */ 263 IDMAC_MAX_SIZE, /* maxsegsize */ 264 0, /* flags */ 265 NULL, NULL, /* lockfunc, lockarg */ 266 &sc->buf_tag); 267 if (error != 0) { 268 device_printf(sc->dev, 269 "could not create ring DMA tag.\n"); 270 return (1); 271 } 272 273 error = bus_dmamap_create(sc->buf_tag, 0, 274 &sc->buf_map); 275 if (error != 0) { 276 device_printf(sc->dev, 277 "could not create TX buffer DMA map.\n"); 278 return (1); 279 } 280 281 return (0); 282 } 283 284 static void 285 dwmmc_cmd_done(struct dwmmc_softc *sc) 286 { 287 struct mmc_command *cmd; 288 289 cmd = sc->curcmd; 290 if (cmd == NULL) 291 return; 292 293 if (cmd->flags & MMC_RSP_PRESENT) { 294 if (cmd->flags & MMC_RSP_136) { 295 cmd->resp[3] = READ4(sc, SDMMC_RESP0); 296 cmd->resp[2] = READ4(sc, SDMMC_RESP1); 297 cmd->resp[1] = READ4(sc, SDMMC_RESP2); 298 cmd->resp[0] = READ4(sc, SDMMC_RESP3); 299 } else { 300 cmd->resp[3] = 0; 301 cmd->resp[2] = 0; 302 cmd->resp[1] = 0; 303 cmd->resp[0] = READ4(sc, SDMMC_RESP0); 304 } 305 } 306 } 307 308 static void 309 dwmmc_tasklet(struct dwmmc_softc *sc) 310 { 311 struct mmc_command *cmd; 312 313 cmd = sc->curcmd; 314 if (cmd == NULL) 315 return; 316 317 if (!sc->cmd_done) 318 return; 319 320 if (cmd->error != MMC_ERR_NONE || !cmd->data) { 321 dwmmc_next_operation(sc); 322 } else if (cmd->data && sc->dto_rcvd) { 323 if ((cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK || 324 cmd->opcode == MMC_READ_MULTIPLE_BLOCK) && 325 sc->use_auto_stop) { 326 if (sc->acd_rcvd) 327 dwmmc_next_operation(sc); 328 } else { 329 dwmmc_next_operation(sc); 330 } 331 } 332 } 333 334 static void 335 dwmmc_intr(void *arg) 336 { 337 struct mmc_command *cmd; 338 struct dwmmc_softc *sc; 339 uint32_t reg; 340 341 sc = arg; 342 343 DWMMC_LOCK(sc); 344 345 cmd = sc->curcmd; 346 347 /* First handle SDMMC controller interrupts */ 348 reg = READ4(sc, SDMMC_MINTSTS); 349 if (reg) { 350 dprintf("%s 0x%08x\n", __func__, reg); 351 352 if (reg & DWMMC_CMD_ERR_FLAGS) { 353 dprintf("cmd err 0x%08x cmd 0x%08x\n", 354 reg, cmd->opcode); 355 cmd->error = MMC_ERR_TIMEOUT; 356 } 357 358 if (reg & DWMMC_DATA_ERR_FLAGS) { 359 dprintf("data err 0x%08x cmd 0x%08x\n", 360 reg, cmd->opcode); 361 cmd->error = MMC_ERR_FAILED; 362 if (!sc->use_pio) { 363 dma_done(sc, cmd); 364 dma_stop(sc); 365 } 366 } 367 368 if (reg & SDMMC_INTMASK_CMD_DONE) { 369 dwmmc_cmd_done(sc); 370 sc->cmd_done = 1; 371 } 372 373 if (reg & SDMMC_INTMASK_ACD) 374 sc->acd_rcvd = 1; 375 376 if (reg & SDMMC_INTMASK_DTO) 377 sc->dto_rcvd = 1; 378 379 if (reg & SDMMC_INTMASK_CD) { 380 dwmmc_handle_card_present(sc, 381 READ4(sc, SDMMC_CDETECT) == 0 ? true : false); 382 } 383 } 384 385 /* Ack interrupts */ 386 WRITE4(sc, SDMMC_RINTSTS, reg); 387 388 if (sc->use_pio) { 389 if (reg & (SDMMC_INTMASK_RXDR|SDMMC_INTMASK_DTO)) { 390 pio_read(sc, cmd); 391 } 392 if (reg & (SDMMC_INTMASK_TXDR|SDMMC_INTMASK_DTO)) { 393 pio_write(sc, cmd); 394 } 395 } else { 396 /* Now handle DMA interrupts */ 397 reg = READ4(sc, SDMMC_IDSTS); 398 if (reg) { 399 dprintf("dma intr 0x%08x\n", reg); 400 if (reg & (SDMMC_IDINTEN_TI | SDMMC_IDINTEN_RI)) { 401 WRITE4(sc, SDMMC_IDSTS, (SDMMC_IDINTEN_TI | 402 SDMMC_IDINTEN_RI)); 403 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_NI); 404 dma_done(sc, cmd); 405 } 406 } 407 } 408 409 dwmmc_tasklet(sc); 410 411 DWMMC_UNLOCK(sc); 412 } 413 414 static void 415 dwmmc_handle_card_present(struct dwmmc_softc *sc, bool is_present) 416 { 417 bool was_present; 418 419 was_present = sc->child != NULL; 420 421 if (!was_present && is_present) { 422 taskqueue_enqueue_timeout(taskqueue_swi_giant, 423 &sc->card_delayed_task, -(hz / 2)); 424 } else if (was_present && !is_present) { 425 taskqueue_enqueue(taskqueue_swi_giant, &sc->card_task); 426 } 427 } 428 429 static void 430 dwmmc_card_task(void *arg, int pending __unused) 431 { 432 struct dwmmc_softc *sc = arg; 433 434 DWMMC_LOCK(sc); 435 436 if (READ4(sc, SDMMC_CDETECT) == 0) { 437 if (sc->child == NULL) { 438 if (bootverbose) 439 device_printf(sc->dev, "Card inserted\n"); 440 441 sc->child = device_add_child(sc->dev, "mmc", -1); 442 DWMMC_UNLOCK(sc); 443 if (sc->child) { 444 device_set_ivars(sc->child, sc); 445 (void)device_probe_and_attach(sc->child); 446 } 447 } else 448 DWMMC_UNLOCK(sc); 449 450 } else { 451 /* Card isn't present, detach if necessary */ 452 if (sc->child != NULL) { 453 if (bootverbose) 454 device_printf(sc->dev, "Card removed\n"); 455 456 DWMMC_UNLOCK(sc); 457 device_delete_child(sc->dev, sc->child); 458 sc->child = NULL; 459 } else 460 DWMMC_UNLOCK(sc); 461 } 462 } 463 464 static int 465 parse_fdt(struct dwmmc_softc *sc) 466 { 467 pcell_t dts_value[3]; 468 phandle_t node; 469 uint32_t bus_hz = 0, bus_width; 470 int len; 471 #ifdef EXT_RESOURCES 472 int error; 473 #endif 474 475 if ((node = ofw_bus_get_node(sc->dev)) == -1) 476 return (ENXIO); 477 478 /* bus-width */ 479 if (OF_getencprop(node, "bus-width", &bus_width, sizeof(uint32_t)) <= 0) 480 bus_width = 4; 481 if (bus_width >= 4) 482 sc->host.caps |= MMC_CAP_4_BIT_DATA; 483 if (bus_width >= 8) 484 sc->host.caps |= MMC_CAP_8_BIT_DATA; 485 486 /* max-frequency */ 487 if (OF_getencprop(node, "max-frequency", &sc->host.f_max, sizeof(uint32_t)) <= 0) 488 sc->host.f_max = 200000000; 489 490 /* fifo-depth */ 491 if ((len = OF_getproplen(node, "fifo-depth")) > 0) { 492 OF_getencprop(node, "fifo-depth", dts_value, len); 493 sc->fifo_depth = dts_value[0]; 494 } 495 496 /* num-slots (Deprecated) */ 497 sc->num_slots = 1; 498 if ((len = OF_getproplen(node, "num-slots")) > 0) { 499 device_printf(sc->dev, "num-slots property is deprecated\n"); 500 OF_getencprop(node, "num-slots", dts_value, len); 501 sc->num_slots = dts_value[0]; 502 } 503 504 /* clock-frequency */ 505 if ((len = OF_getproplen(node, "clock-frequency")) > 0) { 506 OF_getencprop(node, "clock-frequency", dts_value, len); 507 bus_hz = dts_value[0]; 508 } 509 510 #ifdef EXT_RESOURCES 511 512 /* IP block reset is optional */ 513 error = hwreset_get_by_ofw_name(sc->dev, 0, "reset", &sc->hwreset); 514 if (error != 0 && 515 error != ENOENT && 516 error != ENODEV) { 517 device_printf(sc->dev, "Cannot get reset\n"); 518 goto fail; 519 } 520 521 /* vmmc regulator is optional */ 522 error = regulator_get_by_ofw_property(sc->dev, 0, "vmmc-supply", 523 &sc->vmmc); 524 if (error != 0 && 525 error != ENOENT && 526 error != ENODEV) { 527 device_printf(sc->dev, "Cannot get regulator 'vmmc-supply'\n"); 528 goto fail; 529 } 530 531 /* vqmmc regulator is optional */ 532 error = regulator_get_by_ofw_property(sc->dev, 0, "vqmmc-supply", 533 &sc->vqmmc); 534 if (error != 0 && 535 error != ENOENT && 536 error != ENODEV) { 537 device_printf(sc->dev, "Cannot get regulator 'vqmmc-supply'\n"); 538 goto fail; 539 } 540 541 /* Assert reset first */ 542 if (sc->hwreset != NULL) { 543 error = hwreset_assert(sc->hwreset); 544 if (error != 0) { 545 device_printf(sc->dev, "Cannot assert reset\n"); 546 goto fail; 547 } 548 } 549 550 /* BIU (Bus Interface Unit clock) is optional */ 551 error = clk_get_by_ofw_name(sc->dev, 0, "biu", &sc->biu); 552 if (error != 0 && 553 error != ENOENT && 554 error != ENODEV) { 555 device_printf(sc->dev, "Cannot get 'biu' clock\n"); 556 goto fail; 557 } 558 559 if (sc->biu) { 560 error = clk_enable(sc->biu); 561 if (error != 0) { 562 device_printf(sc->dev, "cannot enable biu clock\n"); 563 goto fail; 564 } 565 } 566 567 /* 568 * CIU (Controller Interface Unit clock) is mandatory 569 * if no clock-frequency property is given 570 */ 571 error = clk_get_by_ofw_name(sc->dev, 0, "ciu", &sc->ciu); 572 if (error != 0 && 573 error != ENOENT && 574 error != ENODEV) { 575 device_printf(sc->dev, "Cannot get 'ciu' clock\n"); 576 goto fail; 577 } 578 579 if (sc->ciu) { 580 if (bus_hz != 0) { 581 error = clk_set_freq(sc->ciu, bus_hz, 0); 582 if (error != 0) 583 device_printf(sc->dev, 584 "cannot set ciu clock to %u\n", bus_hz); 585 } 586 error = clk_enable(sc->ciu); 587 if (error != 0) { 588 device_printf(sc->dev, "cannot enable ciu clock\n"); 589 goto fail; 590 } 591 clk_get_freq(sc->ciu, &sc->bus_hz); 592 } 593 594 /* Enable regulators */ 595 if (sc->vmmc != NULL) { 596 error = regulator_enable(sc->vmmc); 597 if (error != 0) { 598 device_printf(sc->dev, "Cannot enable vmmc regulator\n"); 599 goto fail; 600 } 601 } 602 if (sc->vqmmc != NULL) { 603 error = regulator_enable(sc->vqmmc); 604 if (error != 0) { 605 device_printf(sc->dev, "Cannot enable vqmmc regulator\n"); 606 goto fail; 607 } 608 } 609 610 /* Take dwmmc out of reset */ 611 if (sc->hwreset != NULL) { 612 error = hwreset_deassert(sc->hwreset); 613 if (error != 0) { 614 device_printf(sc->dev, "Cannot deassert reset\n"); 615 goto fail; 616 } 617 } 618 #endif /* EXT_RESOURCES */ 619 620 if (sc->bus_hz == 0) { 621 device_printf(sc->dev, "No bus speed provided\n"); 622 goto fail; 623 } 624 625 return (0); 626 627 fail: 628 return (ENXIO); 629 } 630 631 int 632 dwmmc_attach(device_t dev) 633 { 634 struct dwmmc_softc *sc; 635 int error; 636 int slot; 637 638 sc = device_get_softc(dev); 639 640 sc->dev = dev; 641 642 /* Why not to use Auto Stop? It save a hundred of irq per second */ 643 sc->use_auto_stop = 1; 644 645 error = parse_fdt(sc); 646 if (error != 0) { 647 device_printf(dev, "Can't get FDT property.\n"); 648 return (ENXIO); 649 } 650 651 DWMMC_LOCK_INIT(sc); 652 653 if (bus_alloc_resources(dev, dwmmc_spec, sc->res)) { 654 device_printf(dev, "could not allocate resources\n"); 655 return (ENXIO); 656 } 657 658 /* Setup interrupt handler. */ 659 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE, 660 NULL, dwmmc_intr, sc, &sc->intr_cookie); 661 if (error != 0) { 662 device_printf(dev, "could not setup interrupt handler.\n"); 663 return (ENXIO); 664 } 665 666 device_printf(dev, "Hardware version ID is %04x\n", 667 READ4(sc, SDMMC_VERID) & 0xffff); 668 669 /* XXX: we support operation for slot index 0 only */ 670 slot = 0; 671 if (sc->pwren_inverted) { 672 WRITE4(sc, SDMMC_PWREN, (0 << slot)); 673 } else { 674 WRITE4(sc, SDMMC_PWREN, (1 << slot)); 675 } 676 677 /* Reset all */ 678 if (dwmmc_ctrl_reset(sc, (SDMMC_CTRL_RESET | 679 SDMMC_CTRL_FIFO_RESET | 680 SDMMC_CTRL_DMA_RESET))) 681 return (ENXIO); 682 683 dwmmc_setup_bus(sc, sc->host.f_min); 684 685 if (sc->fifo_depth == 0) { 686 sc->fifo_depth = 1 + 687 ((READ4(sc, SDMMC_FIFOTH) >> SDMMC_FIFOTH_RXWMARK_S) & 0xfff); 688 device_printf(dev, "No fifo-depth, using FIFOTH %x\n", 689 sc->fifo_depth); 690 } 691 692 if (!sc->use_pio) { 693 dma_stop(sc); 694 if (dma_setup(sc)) 695 return (ENXIO); 696 697 /* Install desc base */ 698 WRITE4(sc, SDMMC_DBADDR, sc->desc_ring_paddr); 699 700 /* Enable DMA interrupts */ 701 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_MASK); 702 WRITE4(sc, SDMMC_IDINTEN, (SDMMC_IDINTEN_NI | 703 SDMMC_IDINTEN_RI | 704 SDMMC_IDINTEN_TI)); 705 } 706 707 /* Clear and disable interrups for a while */ 708 WRITE4(sc, SDMMC_RINTSTS, 0xffffffff); 709 WRITE4(sc, SDMMC_INTMASK, 0); 710 711 /* Maximum timeout */ 712 WRITE4(sc, SDMMC_TMOUT, 0xffffffff); 713 714 /* Enable interrupts */ 715 WRITE4(sc, SDMMC_RINTSTS, 0xffffffff); 716 WRITE4(sc, SDMMC_INTMASK, (SDMMC_INTMASK_CMD_DONE | 717 SDMMC_INTMASK_DTO | 718 SDMMC_INTMASK_ACD | 719 SDMMC_INTMASK_TXDR | 720 SDMMC_INTMASK_RXDR | 721 DWMMC_ERR_FLAGS | 722 SDMMC_INTMASK_CD)); 723 WRITE4(sc, SDMMC_CTRL, SDMMC_CTRL_INT_ENABLE); 724 725 sc->host.f_min = 400000; 726 sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340; 727 sc->host.caps |= MMC_CAP_HSPEED; 728 sc->host.caps |= MMC_CAP_SIGNALING_330; 729 730 TASK_INIT(&sc->card_task, 0, dwmmc_card_task, sc); 731 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &sc->card_delayed_task, 0, 732 dwmmc_card_task, sc); 733 734 /* 735 * Schedule a card detection as we won't get an interrupt 736 * if the card is inserted when we attach 737 */ 738 dwmmc_card_task(sc, 0); 739 740 return (0); 741 } 742 743 int 744 dwmmc_detach(device_t dev) 745 { 746 struct dwmmc_softc *sc; 747 int ret; 748 749 sc = device_get_softc(dev); 750 751 ret = device_delete_children(dev); 752 if (ret != 0) 753 return (ret); 754 755 taskqueue_drain(taskqueue_swi_giant, &sc->card_task); 756 taskqueue_drain_timeout(taskqueue_swi_giant, &sc->card_delayed_task); 757 758 if (sc->intr_cookie != NULL) { 759 ret = bus_teardown_intr(dev, sc->res[1], sc->intr_cookie); 760 if (ret != 0) 761 return (ret); 762 } 763 bus_release_resources(dev, dwmmc_spec, sc->res); 764 765 DWMMC_LOCK_DESTROY(sc); 766 767 #ifdef EXT_RESOURCES 768 if (sc->hwreset != NULL && hwreset_deassert(sc->hwreset) != 0) 769 device_printf(sc->dev, "cannot deassert reset\n"); 770 if (sc->biu != NULL && clk_disable(sc->biu) != 0) 771 device_printf(sc->dev, "cannot disable biu clock\n"); 772 if (sc->ciu != NULL && clk_disable(sc->ciu) != 0) 773 device_printf(sc->dev, "cannot disable ciu clock\n"); 774 775 if (sc->vmmc && regulator_disable(sc->vmmc) != 0) 776 device_printf(sc->dev, "Cannot disable vmmc regulator\n"); 777 if (sc->vqmmc && regulator_disable(sc->vqmmc) != 0) 778 device_printf(sc->dev, "Cannot disable vqmmc regulator\n"); 779 #endif 780 781 return (0); 782 } 783 784 static int 785 dwmmc_setup_bus(struct dwmmc_softc *sc, int freq) 786 { 787 int tout; 788 int div; 789 790 if (freq == 0) { 791 WRITE4(sc, SDMMC_CLKENA, 0); 792 WRITE4(sc, SDMMC_CMD, (SDMMC_CMD_WAIT_PRVDATA | 793 SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START)); 794 795 tout = 1000; 796 do { 797 if (tout-- < 0) { 798 device_printf(sc->dev, "Failed update clk\n"); 799 return (1); 800 } 801 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START); 802 803 return (0); 804 } 805 806 WRITE4(sc, SDMMC_CLKENA, 0); 807 WRITE4(sc, SDMMC_CLKSRC, 0); 808 809 div = (sc->bus_hz != freq) ? DIV_ROUND_UP(sc->bus_hz, 2 * freq) : 0; 810 811 WRITE4(sc, SDMMC_CLKDIV, div); 812 WRITE4(sc, SDMMC_CMD, (SDMMC_CMD_WAIT_PRVDATA | 813 SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START)); 814 815 tout = 1000; 816 do { 817 if (tout-- < 0) { 818 device_printf(sc->dev, "Failed to update clk"); 819 return (1); 820 } 821 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START); 822 823 WRITE4(sc, SDMMC_CLKENA, (SDMMC_CLKENA_CCLK_EN | SDMMC_CLKENA_LP)); 824 WRITE4(sc, SDMMC_CMD, SDMMC_CMD_WAIT_PRVDATA | 825 SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START); 826 827 tout = 1000; 828 do { 829 if (tout-- < 0) { 830 device_printf(sc->dev, "Failed to enable clk\n"); 831 return (1); 832 } 833 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START); 834 835 return (0); 836 } 837 838 static int 839 dwmmc_update_ios(device_t brdev, device_t reqdev) 840 { 841 struct dwmmc_softc *sc; 842 struct mmc_ios *ios; 843 uint32_t reg; 844 int ret = 0; 845 846 sc = device_get_softc(brdev); 847 ios = &sc->host.ios; 848 849 dprintf("Setting up clk %u bus_width %d\n", 850 ios->clock, ios->bus_width); 851 852 if (ios->bus_width == bus_width_8) 853 WRITE4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT); 854 else if (ios->bus_width == bus_width_4) 855 WRITE4(sc, SDMMC_CTYPE, SDMMC_CTYPE_4BIT); 856 else 857 WRITE4(sc, SDMMC_CTYPE, 0); 858 859 if ((sc->hwtype & HWTYPE_MASK) == HWTYPE_EXYNOS) { 860 /* XXX: take care about DDR or SDR use here */ 861 WRITE4(sc, SDMMC_CLKSEL, sc->sdr_timing); 862 } 863 864 /* Set DDR mode */ 865 reg = READ4(sc, SDMMC_UHS_REG); 866 if (ios->timing == bus_timing_uhs_ddr50 || 867 ios->timing == bus_timing_mmc_ddr52 || 868 ios->timing == bus_timing_mmc_hs400) 869 reg |= (SDMMC_UHS_REG_DDR); 870 else 871 reg &= ~(SDMMC_UHS_REG_DDR); 872 WRITE4(sc, SDMMC_UHS_REG, reg); 873 874 if (sc->update_ios) 875 ret = sc->update_ios(sc, ios); 876 877 dwmmc_setup_bus(sc, ios->clock); 878 879 return (ret); 880 } 881 882 static int 883 dma_done(struct dwmmc_softc *sc, struct mmc_command *cmd) 884 { 885 struct mmc_data *data; 886 887 data = cmd->data; 888 889 if (data->flags & MMC_DATA_WRITE) 890 bus_dmamap_sync(sc->buf_tag, sc->buf_map, 891 BUS_DMASYNC_POSTWRITE); 892 else 893 bus_dmamap_sync(sc->buf_tag, sc->buf_map, 894 BUS_DMASYNC_POSTREAD); 895 896 bus_dmamap_sync(sc->desc_tag, sc->desc_map, 897 BUS_DMASYNC_POSTWRITE); 898 899 bus_dmamap_unload(sc->buf_tag, sc->buf_map); 900 901 return (0); 902 } 903 904 static int 905 dma_stop(struct dwmmc_softc *sc) 906 { 907 int reg; 908 909 reg = READ4(sc, SDMMC_CTRL); 910 reg &= ~(SDMMC_CTRL_USE_IDMAC); 911 reg |= (SDMMC_CTRL_DMA_RESET); 912 WRITE4(sc, SDMMC_CTRL, reg); 913 914 reg = READ4(sc, SDMMC_BMOD); 915 reg &= ~(SDMMC_BMOD_DE | SDMMC_BMOD_FB); 916 reg |= (SDMMC_BMOD_SWR); 917 WRITE4(sc, SDMMC_BMOD, reg); 918 919 return (0); 920 } 921 922 static int 923 dma_prepare(struct dwmmc_softc *sc, struct mmc_command *cmd) 924 { 925 struct mmc_data *data; 926 int err; 927 int reg; 928 929 data = cmd->data; 930 931 reg = READ4(sc, SDMMC_INTMASK); 932 reg &= ~(SDMMC_INTMASK_TXDR | SDMMC_INTMASK_RXDR); 933 WRITE4(sc, SDMMC_INTMASK, reg); 934 935 err = bus_dmamap_load(sc->buf_tag, sc->buf_map, 936 data->data, data->len, dwmmc_ring_setup, 937 sc, BUS_DMA_NOWAIT); 938 if (err != 0) 939 panic("dmamap_load failed\n"); 940 941 /* Ensure the device can see the desc */ 942 bus_dmamap_sync(sc->desc_tag, sc->desc_map, 943 BUS_DMASYNC_PREWRITE); 944 945 if (data->flags & MMC_DATA_WRITE) 946 bus_dmamap_sync(sc->buf_tag, sc->buf_map, 947 BUS_DMASYNC_PREWRITE); 948 else 949 bus_dmamap_sync(sc->buf_tag, sc->buf_map, 950 BUS_DMASYNC_PREREAD); 951 952 reg = (DEF_MSIZE << SDMMC_FIFOTH_MSIZE_S); 953 reg |= ((sc->fifo_depth / 2) - 1) << SDMMC_FIFOTH_RXWMARK_S; 954 reg |= (sc->fifo_depth / 2) << SDMMC_FIFOTH_TXWMARK_S; 955 956 WRITE4(sc, SDMMC_FIFOTH, reg); 957 wmb(); 958 959 reg = READ4(sc, SDMMC_CTRL); 960 reg |= (SDMMC_CTRL_USE_IDMAC | SDMMC_CTRL_DMA_ENABLE); 961 WRITE4(sc, SDMMC_CTRL, reg); 962 wmb(); 963 964 reg = READ4(sc, SDMMC_BMOD); 965 reg |= (SDMMC_BMOD_DE | SDMMC_BMOD_FB); 966 WRITE4(sc, SDMMC_BMOD, reg); 967 968 /* Start */ 969 WRITE4(sc, SDMMC_PLDMND, 1); 970 971 return (0); 972 } 973 974 static int 975 pio_prepare(struct dwmmc_softc *sc, struct mmc_command *cmd) 976 { 977 struct mmc_data *data; 978 int reg; 979 980 data = cmd->data; 981 data->xfer_len = 0; 982 983 reg = (DEF_MSIZE << SDMMC_FIFOTH_MSIZE_S); 984 reg |= ((sc->fifo_depth / 2) - 1) << SDMMC_FIFOTH_RXWMARK_S; 985 reg |= (sc->fifo_depth / 2) << SDMMC_FIFOTH_TXWMARK_S; 986 987 WRITE4(sc, SDMMC_FIFOTH, reg); 988 wmb(); 989 990 return (0); 991 } 992 993 static void 994 pio_read(struct dwmmc_softc *sc, struct mmc_command *cmd) 995 { 996 struct mmc_data *data; 997 uint32_t *p, status; 998 999 if (cmd == NULL || cmd->data == NULL) 1000 return; 1001 1002 data = cmd->data; 1003 if ((data->flags & MMC_DATA_READ) == 0) 1004 return; 1005 1006 KASSERT((data->xfer_len & 3) == 0, ("xfer_len not aligned")); 1007 p = (uint32_t *)data->data + (data->xfer_len >> 2); 1008 1009 while (data->xfer_len < data->len) { 1010 status = READ4(sc, SDMMC_STATUS); 1011 if (status & SDMMC_STATUS_FIFO_EMPTY) 1012 break; 1013 *p++ = READ4(sc, SDMMC_DATA); 1014 data->xfer_len += 4; 1015 } 1016 1017 WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_RXDR); 1018 } 1019 1020 static void 1021 pio_write(struct dwmmc_softc *sc, struct mmc_command *cmd) 1022 { 1023 struct mmc_data *data; 1024 uint32_t *p, status; 1025 1026 if (cmd == NULL || cmd->data == NULL) 1027 return; 1028 1029 data = cmd->data; 1030 if ((data->flags & MMC_DATA_WRITE) == 0) 1031 return; 1032 1033 KASSERT((data->xfer_len & 3) == 0, ("xfer_len not aligned")); 1034 p = (uint32_t *)data->data + (data->xfer_len >> 2); 1035 1036 while (data->xfer_len < data->len) { 1037 status = READ4(sc, SDMMC_STATUS); 1038 if (status & SDMMC_STATUS_FIFO_FULL) 1039 break; 1040 WRITE4(sc, SDMMC_DATA, *p++); 1041 data->xfer_len += 4; 1042 } 1043 1044 WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_TXDR); 1045 } 1046 1047 static void 1048 dwmmc_start_cmd(struct dwmmc_softc *sc, struct mmc_command *cmd) 1049 { 1050 struct mmc_data *data; 1051 uint32_t blksz; 1052 uint32_t cmdr; 1053 1054 sc->curcmd = cmd; 1055 data = cmd->data; 1056 1057 if ((sc->hwtype & HWTYPE_MASK) == HWTYPE_ROCKCHIP) 1058 dwmmc_setup_bus(sc, sc->host.ios.clock); 1059 1060 /* XXX Upper layers don't always set this */ 1061 cmd->mrq = sc->req; 1062 1063 /* Begin setting up command register. */ 1064 1065 cmdr = cmd->opcode; 1066 1067 dprintf("cmd->opcode 0x%08x\n", cmd->opcode); 1068 1069 if (cmd->opcode == MMC_STOP_TRANSMISSION || 1070 cmd->opcode == MMC_GO_IDLE_STATE || 1071 cmd->opcode == MMC_GO_INACTIVE_STATE) 1072 cmdr |= SDMMC_CMD_STOP_ABORT; 1073 else if (cmd->opcode != MMC_SEND_STATUS && data) 1074 cmdr |= SDMMC_CMD_WAIT_PRVDATA; 1075 1076 /* Set up response handling. */ 1077 if (MMC_RSP(cmd->flags) != MMC_RSP_NONE) { 1078 cmdr |= SDMMC_CMD_RESP_EXP; 1079 if (cmd->flags & MMC_RSP_136) 1080 cmdr |= SDMMC_CMD_RESP_LONG; 1081 } 1082 1083 if (cmd->flags & MMC_RSP_CRC) 1084 cmdr |= SDMMC_CMD_RESP_CRC; 1085 1086 /* 1087 * XXX: Not all platforms want this. 1088 */ 1089 cmdr |= SDMMC_CMD_USE_HOLD_REG; 1090 1091 if ((sc->flags & CARD_INIT_DONE) == 0) { 1092 sc->flags |= (CARD_INIT_DONE); 1093 cmdr |= SDMMC_CMD_SEND_INIT; 1094 } 1095 1096 if (data) { 1097 if ((cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK || 1098 cmd->opcode == MMC_READ_MULTIPLE_BLOCK) && 1099 sc->use_auto_stop) 1100 cmdr |= SDMMC_CMD_SEND_ASTOP; 1101 1102 cmdr |= SDMMC_CMD_DATA_EXP; 1103 if (data->flags & MMC_DATA_STREAM) 1104 cmdr |= SDMMC_CMD_MODE_STREAM; 1105 if (data->flags & MMC_DATA_WRITE) 1106 cmdr |= SDMMC_CMD_DATA_WRITE; 1107 1108 WRITE4(sc, SDMMC_TMOUT, 0xffffffff); 1109 WRITE4(sc, SDMMC_BYTCNT, data->len); 1110 blksz = (data->len < MMC_SECTOR_SIZE) ? \ 1111 data->len : MMC_SECTOR_SIZE; 1112 WRITE4(sc, SDMMC_BLKSIZ, blksz); 1113 1114 if (sc->use_pio) { 1115 pio_prepare(sc, cmd); 1116 } else { 1117 dma_prepare(sc, cmd); 1118 } 1119 wmb(); 1120 } 1121 1122 dprintf("cmdr 0x%08x\n", cmdr); 1123 1124 WRITE4(sc, SDMMC_CMDARG, cmd->arg); 1125 wmb(); 1126 WRITE4(sc, SDMMC_CMD, cmdr | SDMMC_CMD_START); 1127 }; 1128 1129 static void 1130 dwmmc_next_operation(struct dwmmc_softc *sc) 1131 { 1132 struct mmc_request *req; 1133 1134 req = sc->req; 1135 if (req == NULL) 1136 return; 1137 1138 sc->acd_rcvd = 0; 1139 sc->dto_rcvd = 0; 1140 sc->cmd_done = 0; 1141 1142 /* 1143 * XXX: Wait until card is still busy. 1144 * We do need this to prevent data timeouts, 1145 * mostly caused by multi-block write command 1146 * followed by single-read. 1147 */ 1148 while(READ4(sc, SDMMC_STATUS) & (SDMMC_STATUS_DATA_BUSY)) 1149 continue; 1150 1151 if (sc->flags & PENDING_CMD) { 1152 sc->flags &= ~PENDING_CMD; 1153 dwmmc_start_cmd(sc, req->cmd); 1154 return; 1155 } else if (sc->flags & PENDING_STOP && !sc->use_auto_stop) { 1156 sc->flags &= ~PENDING_STOP; 1157 dwmmc_start_cmd(sc, req->stop); 1158 return; 1159 } 1160 1161 sc->req = NULL; 1162 sc->curcmd = NULL; 1163 req->done(req); 1164 } 1165 1166 static int 1167 dwmmc_request(device_t brdev, device_t reqdev, struct mmc_request *req) 1168 { 1169 struct dwmmc_softc *sc; 1170 1171 sc = device_get_softc(brdev); 1172 1173 dprintf("%s\n", __func__); 1174 1175 DWMMC_LOCK(sc); 1176 1177 if (sc->req != NULL) { 1178 DWMMC_UNLOCK(sc); 1179 return (EBUSY); 1180 } 1181 1182 sc->req = req; 1183 sc->flags |= PENDING_CMD; 1184 if (sc->req->stop) 1185 sc->flags |= PENDING_STOP; 1186 dwmmc_next_operation(sc); 1187 1188 DWMMC_UNLOCK(sc); 1189 return (0); 1190 } 1191 1192 static int 1193 dwmmc_get_ro(device_t brdev, device_t reqdev) 1194 { 1195 1196 dprintf("%s\n", __func__); 1197 1198 return (0); 1199 } 1200 1201 static int 1202 dwmmc_acquire_host(device_t brdev, device_t reqdev) 1203 { 1204 struct dwmmc_softc *sc; 1205 1206 sc = device_get_softc(brdev); 1207 1208 DWMMC_LOCK(sc); 1209 while (sc->bus_busy) 1210 msleep(sc, &sc->sc_mtx, PZERO, "dwmmcah", hz / 5); 1211 sc->bus_busy++; 1212 DWMMC_UNLOCK(sc); 1213 return (0); 1214 } 1215 1216 static int 1217 dwmmc_release_host(device_t brdev, device_t reqdev) 1218 { 1219 struct dwmmc_softc *sc; 1220 1221 sc = device_get_softc(brdev); 1222 1223 DWMMC_LOCK(sc); 1224 sc->bus_busy--; 1225 wakeup(sc); 1226 DWMMC_UNLOCK(sc); 1227 return (0); 1228 } 1229 1230 static int 1231 dwmmc_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 1232 { 1233 struct dwmmc_softc *sc; 1234 1235 sc = device_get_softc(bus); 1236 1237 switch (which) { 1238 default: 1239 return (EINVAL); 1240 case MMCBR_IVAR_BUS_MODE: 1241 *(int *)result = sc->host.ios.bus_mode; 1242 break; 1243 case MMCBR_IVAR_BUS_WIDTH: 1244 *(int *)result = sc->host.ios.bus_width; 1245 break; 1246 case MMCBR_IVAR_CHIP_SELECT: 1247 *(int *)result = sc->host.ios.chip_select; 1248 break; 1249 case MMCBR_IVAR_CLOCK: 1250 *(int *)result = sc->host.ios.clock; 1251 break; 1252 case MMCBR_IVAR_F_MIN: 1253 *(int *)result = sc->host.f_min; 1254 break; 1255 case MMCBR_IVAR_F_MAX: 1256 *(int *)result = sc->host.f_max; 1257 break; 1258 case MMCBR_IVAR_HOST_OCR: 1259 *(int *)result = sc->host.host_ocr; 1260 break; 1261 case MMCBR_IVAR_MODE: 1262 *(int *)result = sc->host.mode; 1263 break; 1264 case MMCBR_IVAR_OCR: 1265 *(int *)result = sc->host.ocr; 1266 break; 1267 case MMCBR_IVAR_POWER_MODE: 1268 *(int *)result = sc->host.ios.power_mode; 1269 break; 1270 case MMCBR_IVAR_VDD: 1271 *(int *)result = sc->host.ios.vdd; 1272 break; 1273 case MMCBR_IVAR_VCCQ: 1274 *(int *)result = sc->host.ios.vccq; 1275 break; 1276 case MMCBR_IVAR_CAPS: 1277 *(int *)result = sc->host.caps; 1278 break; 1279 case MMCBR_IVAR_MAX_DATA: 1280 *(int *)result = (IDMAC_MAX_SIZE * IDMAC_DESC_SEGS) / MMC_SECTOR_SIZE; 1281 break; 1282 case MMCBR_IVAR_TIMING: 1283 *(int *)result = sc->host.ios.timing; 1284 break; 1285 } 1286 return (0); 1287 } 1288 1289 static int 1290 dwmmc_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1291 { 1292 struct dwmmc_softc *sc; 1293 1294 sc = device_get_softc(bus); 1295 1296 switch (which) { 1297 default: 1298 return (EINVAL); 1299 case MMCBR_IVAR_BUS_MODE: 1300 sc->host.ios.bus_mode = value; 1301 break; 1302 case MMCBR_IVAR_BUS_WIDTH: 1303 sc->host.ios.bus_width = value; 1304 break; 1305 case MMCBR_IVAR_CHIP_SELECT: 1306 sc->host.ios.chip_select = value; 1307 break; 1308 case MMCBR_IVAR_CLOCK: 1309 sc->host.ios.clock = value; 1310 break; 1311 case MMCBR_IVAR_MODE: 1312 sc->host.mode = value; 1313 break; 1314 case MMCBR_IVAR_OCR: 1315 sc->host.ocr = value; 1316 break; 1317 case MMCBR_IVAR_POWER_MODE: 1318 sc->host.ios.power_mode = value; 1319 break; 1320 case MMCBR_IVAR_VDD: 1321 sc->host.ios.vdd = value; 1322 break; 1323 case MMCBR_IVAR_TIMING: 1324 sc->host.ios.timing = value; 1325 break; 1326 case MMCBR_IVAR_VCCQ: 1327 sc->host.ios.vccq = value; 1328 break; 1329 /* These are read-only */ 1330 case MMCBR_IVAR_CAPS: 1331 case MMCBR_IVAR_HOST_OCR: 1332 case MMCBR_IVAR_F_MIN: 1333 case MMCBR_IVAR_F_MAX: 1334 case MMCBR_IVAR_MAX_DATA: 1335 return (EINVAL); 1336 } 1337 return (0); 1338 } 1339 1340 static device_method_t dwmmc_methods[] = { 1341 /* Bus interface */ 1342 DEVMETHOD(bus_read_ivar, dwmmc_read_ivar), 1343 DEVMETHOD(bus_write_ivar, dwmmc_write_ivar), 1344 1345 /* mmcbr_if */ 1346 DEVMETHOD(mmcbr_update_ios, dwmmc_update_ios), 1347 DEVMETHOD(mmcbr_request, dwmmc_request), 1348 DEVMETHOD(mmcbr_get_ro, dwmmc_get_ro), 1349 DEVMETHOD(mmcbr_acquire_host, dwmmc_acquire_host), 1350 DEVMETHOD(mmcbr_release_host, dwmmc_release_host), 1351 1352 DEVMETHOD_END 1353 }; 1354 1355 DEFINE_CLASS_0(dwmmc, dwmmc_driver, dwmmc_methods, 1356 sizeof(struct dwmmc_softc)); 1357