1 /*- 2 * Copyright (c) 2014-2019 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Synopsys DesignWare Mobile Storage Host Controller 33 * Chapter 14, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22) 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/bus.h> 42 #include <sys/kernel.h> 43 #include <sys/lock.h> 44 #include <sys/module.h> 45 #include <sys/malloc.h> 46 #include <sys/mutex.h> 47 #include <sys/rman.h> 48 #include <sys/queue.h> 49 #include <sys/taskqueue.h> 50 51 #include <dev/mmc/bridge.h> 52 #include <dev/mmc/mmcbrvar.h> 53 #include <dev/mmc/mmc_fdt_helpers.h> 54 55 #include <dev/fdt/fdt_common.h> 56 #include <dev/ofw/openfirm.h> 57 #include <dev/ofw/ofw_bus.h> 58 #include <dev/ofw/ofw_bus_subr.h> 59 60 #include <machine/bus.h> 61 #include <machine/cpu.h> 62 #include <machine/intr.h> 63 64 #ifdef EXT_RESOURCES 65 #include <dev/extres/clk/clk.h> 66 #endif 67 68 #include <dev/mmc/host/dwmmc_reg.h> 69 #include <dev/mmc/host/dwmmc_var.h> 70 71 #include "opt_mmccam.h" 72 73 #ifdef MMCCAM 74 #include <cam/cam.h> 75 #include <cam/cam_ccb.h> 76 #include <cam/cam_debug.h> 77 #include <cam/cam_sim.h> 78 #include <cam/cam_xpt_sim.h> 79 80 #include "mmc_sim_if.h" 81 #endif 82 83 #include "mmcbr_if.h" 84 85 #ifdef DEBUG 86 #define dprintf(fmt, args...) printf(fmt, ##args) 87 #else 88 #define dprintf(x, arg...) 89 #endif 90 91 #define READ4(_sc, _reg) \ 92 bus_read_4((_sc)->res[0], _reg) 93 #define WRITE4(_sc, _reg, _val) \ 94 bus_write_4((_sc)->res[0], _reg, _val) 95 96 #define DIV_ROUND_UP(n, d) howmany(n, d) 97 98 #define DWMMC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 99 #define DWMMC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 100 #define DWMMC_LOCK_INIT(_sc) \ 101 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 102 "dwmmc", MTX_DEF) 103 #define DWMMC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 104 #define DWMMC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 105 #define DWMMC_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 106 107 #define PENDING_CMD 0x01 108 #define PENDING_STOP 0x02 109 #define CARD_INIT_DONE 0x04 110 111 #define DWMMC_DATA_ERR_FLAGS (SDMMC_INTMASK_DRT | SDMMC_INTMASK_DCRC \ 112 |SDMMC_INTMASK_SBE | SDMMC_INTMASK_EBE) 113 #define DWMMC_CMD_ERR_FLAGS (SDMMC_INTMASK_RTO | SDMMC_INTMASK_RCRC \ 114 |SDMMC_INTMASK_RE) 115 #define DWMMC_ERR_FLAGS (DWMMC_DATA_ERR_FLAGS | DWMMC_CMD_ERR_FLAGS \ 116 |SDMMC_INTMASK_HLE) 117 118 #define DES0_DIC (1 << 1) /* Disable Interrupt on Completion */ 119 #define DES0_LD (1 << 2) /* Last Descriptor */ 120 #define DES0_FS (1 << 3) /* First Descriptor */ 121 #define DES0_CH (1 << 4) /* second address CHained */ 122 #define DES0_ER (1 << 5) /* End of Ring */ 123 #define DES0_CES (1 << 30) /* Card Error Summary */ 124 #define DES0_OWN (1 << 31) /* OWN */ 125 126 #define DES1_BS1_MASK 0x1fff 127 128 struct idmac_desc { 129 uint32_t des0; /* control */ 130 uint32_t des1; /* bufsize */ 131 uint32_t des2; /* buf1 phys addr */ 132 uint32_t des3; /* buf2 phys addr or next descr */ 133 }; 134 135 #define IDMAC_DESC_SEGS (PAGE_SIZE / (sizeof(struct idmac_desc))) 136 #define IDMAC_DESC_SIZE (sizeof(struct idmac_desc) * IDMAC_DESC_SEGS) 137 #define DEF_MSIZE 0x2 /* Burst size of multiple transaction */ 138 /* 139 * Size field in DMA descriptor is 13 bits long (up to 4095 bytes), 140 * but must be a multiple of the data bus size.Additionally, we must ensure 141 * that bus_dmamap_load() doesn't additionally fragments buffer (because it 142 * is processed with page size granularity). Thus limit fragment size to half 143 * of page. 144 * XXX switch descriptor format to array and use second buffer pointer for 145 * second half of page 146 */ 147 #define IDMAC_MAX_SIZE 2048 148 149 static void dwmmc_next_operation(struct dwmmc_softc *); 150 static int dwmmc_setup_bus(struct dwmmc_softc *, int); 151 static int dma_done(struct dwmmc_softc *, struct mmc_command *); 152 static int dma_stop(struct dwmmc_softc *); 153 static void pio_read(struct dwmmc_softc *, struct mmc_command *); 154 static void pio_write(struct dwmmc_softc *, struct mmc_command *); 155 static void dwmmc_handle_card_present(struct dwmmc_softc *sc, bool is_present); 156 157 static struct resource_spec dwmmc_spec[] = { 158 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 159 { SYS_RES_IRQ, 0, RF_ACTIVE }, 160 { -1, 0 } 161 }; 162 163 #define HWTYPE_MASK (0x0000ffff) 164 #define HWFLAG_MASK (0xffff << 16) 165 166 static void 167 dwmmc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 168 { 169 170 if (nsegs != 1) 171 panic("%s: nsegs != 1 (%d)\n", __func__, nsegs); 172 if (error != 0) 173 panic("%s: error != 0 (%d)\n", __func__, error); 174 175 *(bus_addr_t *)arg = segs[0].ds_addr; 176 } 177 178 static void 179 dwmmc_ring_setup(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 180 { 181 struct dwmmc_softc *sc; 182 int idx; 183 184 sc = arg; 185 dprintf("nsegs %d seg0len %lu\n", nsegs, segs[0].ds_len); 186 if (error != 0) 187 panic("%s: error != 0 (%d)\n", __func__, error); 188 189 for (idx = 0; idx < nsegs; idx++) { 190 sc->desc_ring[idx].des0 = DES0_DIC | DES0_CH; 191 sc->desc_ring[idx].des1 = segs[idx].ds_len & DES1_BS1_MASK; 192 sc->desc_ring[idx].des2 = segs[idx].ds_addr; 193 194 if (idx == 0) 195 sc->desc_ring[idx].des0 |= DES0_FS; 196 197 if (idx == (nsegs - 1)) { 198 sc->desc_ring[idx].des0 &= ~(DES0_DIC | DES0_CH); 199 sc->desc_ring[idx].des0 |= DES0_LD; 200 } 201 wmb(); 202 sc->desc_ring[idx].des0 |= DES0_OWN; 203 } 204 } 205 206 static int 207 dwmmc_ctrl_reset(struct dwmmc_softc *sc, int reset_bits) 208 { 209 int reg; 210 int i; 211 212 reg = READ4(sc, SDMMC_CTRL); 213 reg |= (reset_bits); 214 WRITE4(sc, SDMMC_CTRL, reg); 215 216 /* Wait reset done */ 217 for (i = 0; i < 100; i++) { 218 if (!(READ4(sc, SDMMC_CTRL) & reset_bits)) 219 return (0); 220 DELAY(10); 221 } 222 223 device_printf(sc->dev, "Reset failed\n"); 224 225 return (1); 226 } 227 228 static int 229 dma_setup(struct dwmmc_softc *sc) 230 { 231 int error; 232 int nidx; 233 int idx; 234 235 /* 236 * Set up TX descriptor ring, descriptors, and dma maps. 237 */ 238 error = bus_dma_tag_create( 239 bus_get_dma_tag(sc->dev), /* Parent tag. */ 240 4096, 0, /* alignment, boundary */ 241 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 242 BUS_SPACE_MAXADDR, /* highaddr */ 243 NULL, NULL, /* filter, filterarg */ 244 IDMAC_DESC_SIZE, 1, /* maxsize, nsegments */ 245 IDMAC_DESC_SIZE, /* maxsegsize */ 246 0, /* flags */ 247 NULL, NULL, /* lockfunc, lockarg */ 248 &sc->desc_tag); 249 if (error != 0) { 250 device_printf(sc->dev, 251 "could not create ring DMA tag.\n"); 252 return (1); 253 } 254 255 error = bus_dmamem_alloc(sc->desc_tag, (void**)&sc->desc_ring, 256 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 257 &sc->desc_map); 258 if (error != 0) { 259 device_printf(sc->dev, 260 "could not allocate descriptor ring.\n"); 261 return (1); 262 } 263 264 error = bus_dmamap_load(sc->desc_tag, sc->desc_map, 265 sc->desc_ring, IDMAC_DESC_SIZE, dwmmc_get1paddr, 266 &sc->desc_ring_paddr, 0); 267 if (error != 0) { 268 device_printf(sc->dev, 269 "could not load descriptor ring map.\n"); 270 return (1); 271 } 272 273 for (idx = 0; idx < IDMAC_DESC_SEGS; idx++) { 274 sc->desc_ring[idx].des0 = DES0_CH; 275 sc->desc_ring[idx].des1 = 0; 276 nidx = (idx + 1) % IDMAC_DESC_SEGS; 277 sc->desc_ring[idx].des3 = sc->desc_ring_paddr + \ 278 (nidx * sizeof(struct idmac_desc)); 279 } 280 sc->desc_ring[idx - 1].des3 = sc->desc_ring_paddr; 281 sc->desc_ring[idx - 1].des0 |= DES0_ER; 282 283 error = bus_dma_tag_create( 284 bus_get_dma_tag(sc->dev), /* Parent tag. */ 285 8, 0, /* alignment, boundary */ 286 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 287 BUS_SPACE_MAXADDR, /* highaddr */ 288 NULL, NULL, /* filter, filterarg */ 289 IDMAC_MAX_SIZE * IDMAC_DESC_SEGS, /* maxsize */ 290 IDMAC_DESC_SEGS, /* nsegments */ 291 IDMAC_MAX_SIZE, /* maxsegsize */ 292 0, /* flags */ 293 NULL, NULL, /* lockfunc, lockarg */ 294 &sc->buf_tag); 295 if (error != 0) { 296 device_printf(sc->dev, 297 "could not create ring DMA tag.\n"); 298 return (1); 299 } 300 301 error = bus_dmamap_create(sc->buf_tag, 0, 302 &sc->buf_map); 303 if (error != 0) { 304 device_printf(sc->dev, 305 "could not create TX buffer DMA map.\n"); 306 return (1); 307 } 308 309 return (0); 310 } 311 312 static void 313 dwmmc_cmd_done(struct dwmmc_softc *sc) 314 { 315 struct mmc_command *cmd; 316 #ifdef MMCCAM 317 union ccb *ccb; 318 #endif 319 320 #ifdef MMCCAM 321 ccb = sc->ccb; 322 if (ccb == NULL) 323 return; 324 cmd = &ccb->mmcio.cmd; 325 #else 326 cmd = sc->curcmd; 327 #endif 328 if (cmd == NULL) 329 return; 330 331 if (cmd->flags & MMC_RSP_PRESENT) { 332 if (cmd->flags & MMC_RSP_136) { 333 cmd->resp[3] = READ4(sc, SDMMC_RESP0); 334 cmd->resp[2] = READ4(sc, SDMMC_RESP1); 335 cmd->resp[1] = READ4(sc, SDMMC_RESP2); 336 cmd->resp[0] = READ4(sc, SDMMC_RESP3); 337 } else { 338 cmd->resp[3] = 0; 339 cmd->resp[2] = 0; 340 cmd->resp[1] = 0; 341 cmd->resp[0] = READ4(sc, SDMMC_RESP0); 342 } 343 } 344 } 345 346 static void 347 dwmmc_tasklet(struct dwmmc_softc *sc) 348 { 349 struct mmc_command *cmd; 350 351 cmd = sc->curcmd; 352 if (cmd == NULL) 353 return; 354 355 if (!sc->cmd_done) 356 return; 357 358 if (cmd->error != MMC_ERR_NONE || !cmd->data) { 359 dwmmc_next_operation(sc); 360 } else if (cmd->data && sc->dto_rcvd) { 361 if ((cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK || 362 cmd->opcode == MMC_READ_MULTIPLE_BLOCK) && 363 sc->use_auto_stop) { 364 if (sc->acd_rcvd) 365 dwmmc_next_operation(sc); 366 } else { 367 dwmmc_next_operation(sc); 368 } 369 } 370 } 371 372 static void 373 dwmmc_intr(void *arg) 374 { 375 struct mmc_command *cmd; 376 struct dwmmc_softc *sc; 377 uint32_t reg; 378 379 sc = arg; 380 381 DWMMC_LOCK(sc); 382 383 cmd = sc->curcmd; 384 385 /* First handle SDMMC controller interrupts */ 386 reg = READ4(sc, SDMMC_MINTSTS); 387 if (reg) { 388 dprintf("%s 0x%08x\n", __func__, reg); 389 390 if (reg & DWMMC_CMD_ERR_FLAGS) { 391 dprintf("cmd err 0x%08x cmd 0x%08x\n", 392 reg, cmd->opcode); 393 cmd->error = MMC_ERR_TIMEOUT; 394 } 395 396 if (reg & DWMMC_DATA_ERR_FLAGS) { 397 dprintf("data err 0x%08x cmd 0x%08x\n", 398 reg, cmd->opcode); 399 cmd->error = MMC_ERR_FAILED; 400 if (!sc->use_pio) { 401 dma_done(sc, cmd); 402 dma_stop(sc); 403 } 404 } 405 406 if (reg & SDMMC_INTMASK_CMD_DONE) { 407 dwmmc_cmd_done(sc); 408 sc->cmd_done = 1; 409 } 410 411 if (reg & SDMMC_INTMASK_ACD) 412 sc->acd_rcvd = 1; 413 414 if (reg & SDMMC_INTMASK_DTO) 415 sc->dto_rcvd = 1; 416 417 if (reg & SDMMC_INTMASK_CD) { 418 dwmmc_handle_card_present(sc, 419 READ4(sc, SDMMC_CDETECT) == 0 ? true : false); 420 } 421 } 422 423 /* Ack interrupts */ 424 WRITE4(sc, SDMMC_RINTSTS, reg); 425 426 if (sc->use_pio) { 427 if (reg & (SDMMC_INTMASK_RXDR|SDMMC_INTMASK_DTO)) { 428 pio_read(sc, cmd); 429 } 430 if (reg & (SDMMC_INTMASK_TXDR|SDMMC_INTMASK_DTO)) { 431 pio_write(sc, cmd); 432 } 433 } else { 434 /* Now handle DMA interrupts */ 435 reg = READ4(sc, SDMMC_IDSTS); 436 if (reg) { 437 dprintf("dma intr 0x%08x\n", reg); 438 if (reg & (SDMMC_IDINTEN_TI | SDMMC_IDINTEN_RI)) { 439 WRITE4(sc, SDMMC_IDSTS, (SDMMC_IDINTEN_TI | 440 SDMMC_IDINTEN_RI)); 441 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_NI); 442 dma_done(sc, cmd); 443 } 444 } 445 } 446 447 dwmmc_tasklet(sc); 448 449 DWMMC_UNLOCK(sc); 450 } 451 452 static void 453 dwmmc_handle_card_present(struct dwmmc_softc *sc, bool is_present) 454 { 455 bool was_present; 456 457 was_present = sc->child != NULL; 458 459 if (!was_present && is_present) { 460 taskqueue_enqueue_timeout(taskqueue_swi_giant, 461 &sc->card_delayed_task, -(hz / 2)); 462 } else if (was_present && !is_present) { 463 taskqueue_enqueue(taskqueue_swi_giant, &sc->card_task); 464 } 465 } 466 467 static void 468 dwmmc_card_task(void *arg, int pending __unused) 469 { 470 struct dwmmc_softc *sc = arg; 471 472 #ifdef MMCCAM 473 mmc_cam_sim_discover(&sc->mmc_sim); 474 #else 475 DWMMC_LOCK(sc); 476 477 if (READ4(sc, SDMMC_CDETECT) == 0 || 478 (sc->mmc_helper.props & MMC_PROP_BROKEN_CD)) { 479 if (sc->child == NULL) { 480 if (bootverbose) 481 device_printf(sc->dev, "Card inserted\n"); 482 483 sc->child = device_add_child(sc->dev, "mmc", -1); 484 DWMMC_UNLOCK(sc); 485 if (sc->child) { 486 device_set_ivars(sc->child, sc); 487 (void)device_probe_and_attach(sc->child); 488 } 489 } else 490 DWMMC_UNLOCK(sc); 491 } else { 492 /* Card isn't present, detach if necessary */ 493 if (sc->child != NULL) { 494 if (bootverbose) 495 device_printf(sc->dev, "Card removed\n"); 496 497 DWMMC_UNLOCK(sc); 498 device_delete_child(sc->dev, sc->child); 499 sc->child = NULL; 500 } else 501 DWMMC_UNLOCK(sc); 502 } 503 #endif /* MMCCAM */ 504 } 505 506 static int 507 parse_fdt(struct dwmmc_softc *sc) 508 { 509 pcell_t dts_value[3]; 510 phandle_t node; 511 uint32_t bus_hz = 0; 512 int len; 513 #ifdef EXT_RESOURCES 514 int error; 515 #endif 516 517 if ((node = ofw_bus_get_node(sc->dev)) == -1) 518 return (ENXIO); 519 520 /* Set some defaults for freq and supported mode */ 521 sc->host.f_min = 400000; 522 sc->host.f_max = 200000000; 523 sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340; 524 sc->host.caps = MMC_CAP_HSPEED | MMC_CAP_SIGNALING_330; 525 mmc_fdt_parse(sc->dev, node, &sc->mmc_helper, &sc->host); 526 527 /* fifo-depth */ 528 if ((len = OF_getproplen(node, "fifo-depth")) > 0) { 529 OF_getencprop(node, "fifo-depth", dts_value, len); 530 sc->fifo_depth = dts_value[0]; 531 } 532 533 /* num-slots (Deprecated) */ 534 sc->num_slots = 1; 535 if ((len = OF_getproplen(node, "num-slots")) > 0) { 536 device_printf(sc->dev, "num-slots property is deprecated\n"); 537 OF_getencprop(node, "num-slots", dts_value, len); 538 sc->num_slots = dts_value[0]; 539 } 540 541 /* clock-frequency */ 542 if ((len = OF_getproplen(node, "clock-frequency")) > 0) { 543 OF_getencprop(node, "clock-frequency", dts_value, len); 544 bus_hz = dts_value[0]; 545 } 546 547 #ifdef EXT_RESOURCES 548 549 /* IP block reset is optional */ 550 error = hwreset_get_by_ofw_name(sc->dev, 0, "reset", &sc->hwreset); 551 if (error != 0 && 552 error != ENOENT && 553 error != ENODEV) { 554 device_printf(sc->dev, "Cannot get reset\n"); 555 goto fail; 556 } 557 558 /* vmmc regulator is optional */ 559 error = regulator_get_by_ofw_property(sc->dev, 0, "vmmc-supply", 560 &sc->vmmc); 561 if (error != 0 && 562 error != ENOENT && 563 error != ENODEV) { 564 device_printf(sc->dev, "Cannot get regulator 'vmmc-supply'\n"); 565 goto fail; 566 } 567 568 /* vqmmc regulator is optional */ 569 error = regulator_get_by_ofw_property(sc->dev, 0, "vqmmc-supply", 570 &sc->vqmmc); 571 if (error != 0 && 572 error != ENOENT && 573 error != ENODEV) { 574 device_printf(sc->dev, "Cannot get regulator 'vqmmc-supply'\n"); 575 goto fail; 576 } 577 578 /* Assert reset first */ 579 if (sc->hwreset != NULL) { 580 error = hwreset_assert(sc->hwreset); 581 if (error != 0) { 582 device_printf(sc->dev, "Cannot assert reset\n"); 583 goto fail; 584 } 585 } 586 587 /* BIU (Bus Interface Unit clock) is optional */ 588 error = clk_get_by_ofw_name(sc->dev, 0, "biu", &sc->biu); 589 if (error != 0 && 590 error != ENOENT && 591 error != ENODEV) { 592 device_printf(sc->dev, "Cannot get 'biu' clock\n"); 593 goto fail; 594 } 595 596 if (sc->biu) { 597 error = clk_enable(sc->biu); 598 if (error != 0) { 599 device_printf(sc->dev, "cannot enable biu clock\n"); 600 goto fail; 601 } 602 } 603 604 /* 605 * CIU (Controller Interface Unit clock) is mandatory 606 * if no clock-frequency property is given 607 */ 608 error = clk_get_by_ofw_name(sc->dev, 0, "ciu", &sc->ciu); 609 if (error != 0 && 610 error != ENOENT && 611 error != ENODEV) { 612 device_printf(sc->dev, "Cannot get 'ciu' clock\n"); 613 goto fail; 614 } 615 616 if (sc->ciu) { 617 if (bus_hz != 0) { 618 error = clk_set_freq(sc->ciu, bus_hz, 0); 619 if (error != 0) 620 device_printf(sc->dev, 621 "cannot set ciu clock to %u\n", bus_hz); 622 } 623 error = clk_enable(sc->ciu); 624 if (error != 0) { 625 device_printf(sc->dev, "cannot enable ciu clock\n"); 626 goto fail; 627 } 628 clk_get_freq(sc->ciu, &sc->bus_hz); 629 } 630 631 /* Enable regulators */ 632 if (sc->vmmc != NULL) { 633 error = regulator_enable(sc->vmmc); 634 if (error != 0) { 635 device_printf(sc->dev, "Cannot enable vmmc regulator\n"); 636 goto fail; 637 } 638 } 639 if (sc->vqmmc != NULL) { 640 error = regulator_enable(sc->vqmmc); 641 if (error != 0) { 642 device_printf(sc->dev, "Cannot enable vqmmc regulator\n"); 643 goto fail; 644 } 645 } 646 647 /* Take dwmmc out of reset */ 648 if (sc->hwreset != NULL) { 649 error = hwreset_deassert(sc->hwreset); 650 if (error != 0) { 651 device_printf(sc->dev, "Cannot deassert reset\n"); 652 goto fail; 653 } 654 } 655 #endif /* EXT_RESOURCES */ 656 657 if (sc->bus_hz == 0) { 658 device_printf(sc->dev, "No bus speed provided\n"); 659 goto fail; 660 } 661 662 return (0); 663 664 fail: 665 return (ENXIO); 666 } 667 668 int 669 dwmmc_attach(device_t dev) 670 { 671 struct dwmmc_softc *sc; 672 int error; 673 674 sc = device_get_softc(dev); 675 676 sc->dev = dev; 677 678 /* Why not to use Auto Stop? It save a hundred of irq per second */ 679 sc->use_auto_stop = 1; 680 681 error = parse_fdt(sc); 682 if (error != 0) { 683 device_printf(dev, "Can't get FDT property.\n"); 684 return (ENXIO); 685 } 686 687 DWMMC_LOCK_INIT(sc); 688 689 if (bus_alloc_resources(dev, dwmmc_spec, sc->res)) { 690 device_printf(dev, "could not allocate resources\n"); 691 return (ENXIO); 692 } 693 694 /* Setup interrupt handler. */ 695 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE, 696 NULL, dwmmc_intr, sc, &sc->intr_cookie); 697 if (error != 0) { 698 device_printf(dev, "could not setup interrupt handler.\n"); 699 return (ENXIO); 700 } 701 702 device_printf(dev, "Hardware version ID is %04x\n", 703 READ4(sc, SDMMC_VERID) & 0xffff); 704 705 /* Reset all */ 706 if (dwmmc_ctrl_reset(sc, (SDMMC_CTRL_RESET | 707 SDMMC_CTRL_FIFO_RESET | 708 SDMMC_CTRL_DMA_RESET))) 709 return (ENXIO); 710 711 dwmmc_setup_bus(sc, sc->host.f_min); 712 713 if (sc->fifo_depth == 0) { 714 sc->fifo_depth = 1 + 715 ((READ4(sc, SDMMC_FIFOTH) >> SDMMC_FIFOTH_RXWMARK_S) & 0xfff); 716 device_printf(dev, "No fifo-depth, using FIFOTH %x\n", 717 sc->fifo_depth); 718 } 719 720 if (!sc->use_pio) { 721 dma_stop(sc); 722 if (dma_setup(sc)) 723 return (ENXIO); 724 725 /* Install desc base */ 726 WRITE4(sc, SDMMC_DBADDR, sc->desc_ring_paddr); 727 728 /* Enable DMA interrupts */ 729 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_MASK); 730 WRITE4(sc, SDMMC_IDINTEN, (SDMMC_IDINTEN_NI | 731 SDMMC_IDINTEN_RI | 732 SDMMC_IDINTEN_TI)); 733 } 734 735 /* Clear and disable interrups for a while */ 736 WRITE4(sc, SDMMC_RINTSTS, 0xffffffff); 737 WRITE4(sc, SDMMC_INTMASK, 0); 738 739 /* Maximum timeout */ 740 WRITE4(sc, SDMMC_TMOUT, 0xffffffff); 741 742 /* Enable interrupts */ 743 WRITE4(sc, SDMMC_RINTSTS, 0xffffffff); 744 WRITE4(sc, SDMMC_INTMASK, (SDMMC_INTMASK_CMD_DONE | 745 SDMMC_INTMASK_DTO | 746 SDMMC_INTMASK_ACD | 747 SDMMC_INTMASK_TXDR | 748 SDMMC_INTMASK_RXDR | 749 DWMMC_ERR_FLAGS | 750 SDMMC_INTMASK_CD)); 751 WRITE4(sc, SDMMC_CTRL, SDMMC_CTRL_INT_ENABLE); 752 753 TASK_INIT(&sc->card_task, 0, dwmmc_card_task, sc); 754 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &sc->card_delayed_task, 0, 755 dwmmc_card_task, sc); 756 757 #ifdef MMCCAM 758 sc->ccb = NULL; 759 if (mmc_cam_sim_alloc(dev, "dw_mmc", &sc->mmc_sim) != 0) { 760 device_printf(dev, "cannot alloc cam sim\n"); 761 dwmmc_detach(dev); 762 return (ENXIO); 763 } 764 #endif 765 /* 766 * Schedule a card detection as we won't get an interrupt 767 * if the card is inserted when we attach 768 */ 769 dwmmc_card_task(sc, 0); 770 return (0); 771 } 772 773 int 774 dwmmc_detach(device_t dev) 775 { 776 struct dwmmc_softc *sc; 777 int ret; 778 779 sc = device_get_softc(dev); 780 781 ret = device_delete_children(dev); 782 if (ret != 0) 783 return (ret); 784 785 taskqueue_drain(taskqueue_swi_giant, &sc->card_task); 786 taskqueue_drain_timeout(taskqueue_swi_giant, &sc->card_delayed_task); 787 788 if (sc->intr_cookie != NULL) { 789 ret = bus_teardown_intr(dev, sc->res[1], sc->intr_cookie); 790 if (ret != 0) 791 return (ret); 792 } 793 bus_release_resources(dev, dwmmc_spec, sc->res); 794 795 DWMMC_LOCK_DESTROY(sc); 796 797 #ifdef EXT_RESOURCES 798 if (sc->hwreset != NULL && hwreset_deassert(sc->hwreset) != 0) 799 device_printf(sc->dev, "cannot deassert reset\n"); 800 if (sc->biu != NULL && clk_disable(sc->biu) != 0) 801 device_printf(sc->dev, "cannot disable biu clock\n"); 802 if (sc->ciu != NULL && clk_disable(sc->ciu) != 0) 803 device_printf(sc->dev, "cannot disable ciu clock\n"); 804 805 if (sc->vmmc && regulator_disable(sc->vmmc) != 0) 806 device_printf(sc->dev, "Cannot disable vmmc regulator\n"); 807 if (sc->vqmmc && regulator_disable(sc->vqmmc) != 0) 808 device_printf(sc->dev, "Cannot disable vqmmc regulator\n"); 809 #endif 810 811 #ifdef MMCCAM 812 mmc_cam_sim_free(&sc->mmc_sim); 813 #endif 814 815 return (0); 816 } 817 818 static int 819 dwmmc_setup_bus(struct dwmmc_softc *sc, int freq) 820 { 821 int tout; 822 int div; 823 824 if (freq == 0) { 825 WRITE4(sc, SDMMC_CLKENA, 0); 826 WRITE4(sc, SDMMC_CMD, (SDMMC_CMD_WAIT_PRVDATA | 827 SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START)); 828 829 tout = 1000; 830 do { 831 if (tout-- < 0) { 832 device_printf(sc->dev, "Failed update clk\n"); 833 return (1); 834 } 835 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START); 836 837 return (0); 838 } 839 840 WRITE4(sc, SDMMC_CLKENA, 0); 841 WRITE4(sc, SDMMC_CLKSRC, 0); 842 843 div = (sc->bus_hz != freq) ? DIV_ROUND_UP(sc->bus_hz, 2 * freq) : 0; 844 845 WRITE4(sc, SDMMC_CLKDIV, div); 846 WRITE4(sc, SDMMC_CMD, (SDMMC_CMD_WAIT_PRVDATA | 847 SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START)); 848 849 tout = 1000; 850 do { 851 if (tout-- < 0) { 852 device_printf(sc->dev, "Failed to update clk\n"); 853 return (1); 854 } 855 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START); 856 857 WRITE4(sc, SDMMC_CLKENA, (SDMMC_CLKENA_CCLK_EN | SDMMC_CLKENA_LP)); 858 WRITE4(sc, SDMMC_CMD, SDMMC_CMD_WAIT_PRVDATA | 859 SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START); 860 861 tout = 1000; 862 do { 863 if (tout-- < 0) { 864 device_printf(sc->dev, "Failed to enable clk\n"); 865 return (1); 866 } 867 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START); 868 869 return (0); 870 } 871 872 static int 873 dwmmc_update_ios(device_t brdev, device_t reqdev) 874 { 875 struct dwmmc_softc *sc; 876 struct mmc_ios *ios; 877 uint32_t reg; 878 int ret = 0; 879 880 sc = device_get_softc(brdev); 881 ios = &sc->host.ios; 882 883 dprintf("Setting up clk %u bus_width %d, timming: %d\n", 884 ios->clock, ios->bus_width, ios->timing); 885 886 switch (ios->power_mode) { 887 case power_on: 888 break; 889 case power_off: 890 WRITE4(sc, SDMMC_PWREN, 0); 891 break; 892 case power_up: 893 WRITE4(sc, SDMMC_PWREN, 1); 894 break; 895 } 896 897 mmc_fdt_set_power(&sc->mmc_helper, ios->power_mode); 898 899 if (ios->bus_width == bus_width_8) 900 WRITE4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT); 901 else if (ios->bus_width == bus_width_4) 902 WRITE4(sc, SDMMC_CTYPE, SDMMC_CTYPE_4BIT); 903 else 904 WRITE4(sc, SDMMC_CTYPE, 0); 905 906 if ((sc->hwtype & HWTYPE_MASK) == HWTYPE_EXYNOS) { 907 /* XXX: take care about DDR or SDR use here */ 908 WRITE4(sc, SDMMC_CLKSEL, sc->sdr_timing); 909 } 910 911 /* Set DDR mode */ 912 reg = READ4(sc, SDMMC_UHS_REG); 913 if (ios->timing == bus_timing_uhs_ddr50 || 914 ios->timing == bus_timing_mmc_ddr52 || 915 ios->timing == bus_timing_mmc_hs400) 916 reg |= (SDMMC_UHS_REG_DDR); 917 else 918 reg &= ~(SDMMC_UHS_REG_DDR); 919 WRITE4(sc, SDMMC_UHS_REG, reg); 920 921 if (sc->update_ios) 922 ret = sc->update_ios(sc, ios); 923 924 dwmmc_setup_bus(sc, ios->clock); 925 926 return (ret); 927 } 928 929 static int 930 dma_done(struct dwmmc_softc *sc, struct mmc_command *cmd) 931 { 932 struct mmc_data *data; 933 934 data = cmd->data; 935 936 if (data->flags & MMC_DATA_WRITE) 937 bus_dmamap_sync(sc->buf_tag, sc->buf_map, 938 BUS_DMASYNC_POSTWRITE); 939 else 940 bus_dmamap_sync(sc->buf_tag, sc->buf_map, 941 BUS_DMASYNC_POSTREAD); 942 943 bus_dmamap_sync(sc->desc_tag, sc->desc_map, 944 BUS_DMASYNC_POSTWRITE); 945 946 bus_dmamap_unload(sc->buf_tag, sc->buf_map); 947 948 return (0); 949 } 950 951 static int 952 dma_stop(struct dwmmc_softc *sc) 953 { 954 int reg; 955 956 reg = READ4(sc, SDMMC_CTRL); 957 reg &= ~(SDMMC_CTRL_USE_IDMAC); 958 reg |= (SDMMC_CTRL_DMA_RESET); 959 WRITE4(sc, SDMMC_CTRL, reg); 960 961 reg = READ4(sc, SDMMC_BMOD); 962 reg &= ~(SDMMC_BMOD_DE | SDMMC_BMOD_FB); 963 reg |= (SDMMC_BMOD_SWR); 964 WRITE4(sc, SDMMC_BMOD, reg); 965 966 return (0); 967 } 968 969 static int 970 dma_prepare(struct dwmmc_softc *sc, struct mmc_command *cmd) 971 { 972 struct mmc_data *data; 973 int err; 974 int reg; 975 976 data = cmd->data; 977 978 reg = READ4(sc, SDMMC_INTMASK); 979 reg &= ~(SDMMC_INTMASK_TXDR | SDMMC_INTMASK_RXDR); 980 WRITE4(sc, SDMMC_INTMASK, reg); 981 dprintf("%s: bus_dmamap_load size: %zu\n", __func__, data->len); 982 err = bus_dmamap_load(sc->buf_tag, sc->buf_map, 983 data->data, data->len, dwmmc_ring_setup, 984 sc, BUS_DMA_NOWAIT); 985 if (err != 0) 986 panic("dmamap_load failed\n"); 987 988 /* Ensure the device can see the desc */ 989 bus_dmamap_sync(sc->desc_tag, sc->desc_map, 990 BUS_DMASYNC_PREWRITE); 991 992 if (data->flags & MMC_DATA_WRITE) 993 bus_dmamap_sync(sc->buf_tag, sc->buf_map, 994 BUS_DMASYNC_PREWRITE); 995 else 996 bus_dmamap_sync(sc->buf_tag, sc->buf_map, 997 BUS_DMASYNC_PREREAD); 998 999 reg = (DEF_MSIZE << SDMMC_FIFOTH_MSIZE_S); 1000 reg |= ((sc->fifo_depth / 2) - 1) << SDMMC_FIFOTH_RXWMARK_S; 1001 reg |= (sc->fifo_depth / 2) << SDMMC_FIFOTH_TXWMARK_S; 1002 1003 WRITE4(sc, SDMMC_FIFOTH, reg); 1004 wmb(); 1005 1006 reg = READ4(sc, SDMMC_CTRL); 1007 reg |= (SDMMC_CTRL_USE_IDMAC | SDMMC_CTRL_DMA_ENABLE); 1008 WRITE4(sc, SDMMC_CTRL, reg); 1009 wmb(); 1010 1011 reg = READ4(sc, SDMMC_BMOD); 1012 reg |= (SDMMC_BMOD_DE | SDMMC_BMOD_FB); 1013 WRITE4(sc, SDMMC_BMOD, reg); 1014 1015 /* Start */ 1016 WRITE4(sc, SDMMC_PLDMND, 1); 1017 1018 return (0); 1019 } 1020 1021 static int 1022 pio_prepare(struct dwmmc_softc *sc, struct mmc_command *cmd) 1023 { 1024 struct mmc_data *data; 1025 int reg; 1026 1027 data = cmd->data; 1028 data->xfer_len = 0; 1029 1030 reg = (DEF_MSIZE << SDMMC_FIFOTH_MSIZE_S); 1031 reg |= ((sc->fifo_depth / 2) - 1) << SDMMC_FIFOTH_RXWMARK_S; 1032 reg |= (sc->fifo_depth / 2) << SDMMC_FIFOTH_TXWMARK_S; 1033 1034 WRITE4(sc, SDMMC_FIFOTH, reg); 1035 wmb(); 1036 1037 return (0); 1038 } 1039 1040 static void 1041 pio_read(struct dwmmc_softc *sc, struct mmc_command *cmd) 1042 { 1043 struct mmc_data *data; 1044 uint32_t *p, status; 1045 1046 if (cmd == NULL || cmd->data == NULL) 1047 return; 1048 1049 data = cmd->data; 1050 if ((data->flags & MMC_DATA_READ) == 0) 1051 return; 1052 1053 KASSERT((data->xfer_len & 3) == 0, ("xfer_len not aligned")); 1054 p = (uint32_t *)data->data + (data->xfer_len >> 2); 1055 1056 while (data->xfer_len < data->len) { 1057 status = READ4(sc, SDMMC_STATUS); 1058 if (status & SDMMC_STATUS_FIFO_EMPTY) 1059 break; 1060 *p++ = READ4(sc, SDMMC_DATA); 1061 data->xfer_len += 4; 1062 } 1063 1064 WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_RXDR); 1065 } 1066 1067 static void 1068 pio_write(struct dwmmc_softc *sc, struct mmc_command *cmd) 1069 { 1070 struct mmc_data *data; 1071 uint32_t *p, status; 1072 1073 if (cmd == NULL || cmd->data == NULL) 1074 return; 1075 1076 data = cmd->data; 1077 if ((data->flags & MMC_DATA_WRITE) == 0) 1078 return; 1079 1080 KASSERT((data->xfer_len & 3) == 0, ("xfer_len not aligned")); 1081 p = (uint32_t *)data->data + (data->xfer_len >> 2); 1082 1083 while (data->xfer_len < data->len) { 1084 status = READ4(sc, SDMMC_STATUS); 1085 if (status & SDMMC_STATUS_FIFO_FULL) 1086 break; 1087 WRITE4(sc, SDMMC_DATA, *p++); 1088 data->xfer_len += 4; 1089 } 1090 1091 WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_TXDR); 1092 } 1093 1094 static void 1095 dwmmc_start_cmd(struct dwmmc_softc *sc, struct mmc_command *cmd) 1096 { 1097 struct mmc_data *data; 1098 uint32_t blksz; 1099 uint32_t cmdr; 1100 1101 dprintf("%s\n", __func__); 1102 sc->curcmd = cmd; 1103 data = cmd->data; 1104 1105 if ((sc->hwtype & HWTYPE_MASK) == HWTYPE_ROCKCHIP) 1106 dwmmc_setup_bus(sc, sc->host.ios.clock); 1107 1108 #ifndef MMCCAM 1109 /* XXX Upper layers don't always set this */ 1110 cmd->mrq = sc->req; 1111 #endif 1112 /* Begin setting up command register. */ 1113 1114 cmdr = cmd->opcode; 1115 1116 dprintf("cmd->opcode 0x%08x\n", cmd->opcode); 1117 1118 if (cmd->opcode == MMC_STOP_TRANSMISSION || 1119 cmd->opcode == MMC_GO_IDLE_STATE || 1120 cmd->opcode == MMC_GO_INACTIVE_STATE) 1121 cmdr |= SDMMC_CMD_STOP_ABORT; 1122 else if (cmd->opcode != MMC_SEND_STATUS && data) 1123 cmdr |= SDMMC_CMD_WAIT_PRVDATA; 1124 1125 /* Set up response handling. */ 1126 if (MMC_RSP(cmd->flags) != MMC_RSP_NONE) { 1127 cmdr |= SDMMC_CMD_RESP_EXP; 1128 if (cmd->flags & MMC_RSP_136) 1129 cmdr |= SDMMC_CMD_RESP_LONG; 1130 } 1131 1132 if (cmd->flags & MMC_RSP_CRC) 1133 cmdr |= SDMMC_CMD_RESP_CRC; 1134 1135 /* 1136 * XXX: Not all platforms want this. 1137 */ 1138 cmdr |= SDMMC_CMD_USE_HOLD_REG; 1139 1140 if ((sc->flags & CARD_INIT_DONE) == 0) { 1141 sc->flags |= (CARD_INIT_DONE); 1142 cmdr |= SDMMC_CMD_SEND_INIT; 1143 } 1144 1145 if (data) { 1146 if ((cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK || 1147 cmd->opcode == MMC_READ_MULTIPLE_BLOCK) && 1148 sc->use_auto_stop) 1149 cmdr |= SDMMC_CMD_SEND_ASTOP; 1150 1151 cmdr |= SDMMC_CMD_DATA_EXP; 1152 if (data->flags & MMC_DATA_STREAM) 1153 cmdr |= SDMMC_CMD_MODE_STREAM; 1154 if (data->flags & MMC_DATA_WRITE) 1155 cmdr |= SDMMC_CMD_DATA_WRITE; 1156 1157 WRITE4(sc, SDMMC_TMOUT, 0xffffffff); 1158 #ifdef MMCCAM 1159 if (cmd->data->flags & MMC_DATA_BLOCK_SIZE) { 1160 WRITE4(sc, SDMMC_BLKSIZ, cmd->data->block_size); 1161 WRITE4(sc, SDMMC_BYTCNT, cmd->data->len); 1162 } else 1163 #endif 1164 { 1165 WRITE4(sc, SDMMC_BYTCNT, data->len); 1166 blksz = (data->len < MMC_SECTOR_SIZE) ? \ 1167 data->len : MMC_SECTOR_SIZE; 1168 WRITE4(sc, SDMMC_BLKSIZ, blksz); 1169 } 1170 1171 if (sc->use_pio) { 1172 pio_prepare(sc, cmd); 1173 } else { 1174 dma_prepare(sc, cmd); 1175 } 1176 wmb(); 1177 } 1178 1179 dprintf("cmdr 0x%08x\n", cmdr); 1180 1181 WRITE4(sc, SDMMC_CMDARG, cmd->arg); 1182 wmb(); 1183 WRITE4(sc, SDMMC_CMD, cmdr | SDMMC_CMD_START); 1184 }; 1185 1186 static void 1187 dwmmc_next_operation(struct dwmmc_softc *sc) 1188 { 1189 struct mmc_command *cmd; 1190 dprintf("%s\n", __func__); 1191 #ifdef MMCCAM 1192 union ccb *ccb; 1193 1194 ccb = sc->ccb; 1195 if (ccb == NULL) 1196 return; 1197 cmd = &ccb->mmcio.cmd; 1198 #else 1199 struct mmc_request *req; 1200 1201 req = sc->req; 1202 if (req == NULL) 1203 return; 1204 cmd = req->cmd; 1205 #endif 1206 1207 sc->acd_rcvd = 0; 1208 sc->dto_rcvd = 0; 1209 sc->cmd_done = 0; 1210 1211 /* 1212 * XXX: Wait until card is still busy. 1213 * We do need this to prevent data timeouts, 1214 * mostly caused by multi-block write command 1215 * followed by single-read. 1216 */ 1217 while(READ4(sc, SDMMC_STATUS) & (SDMMC_STATUS_DATA_BUSY)) 1218 continue; 1219 1220 if (sc->flags & PENDING_CMD) { 1221 sc->flags &= ~PENDING_CMD; 1222 dwmmc_start_cmd(sc, cmd); 1223 return; 1224 } else if (sc->flags & PENDING_STOP && !sc->use_auto_stop) { 1225 sc->flags &= ~PENDING_STOP; 1226 /// XXX: What to do with this? 1227 //dwmmc_start_cmd(sc, req->stop); 1228 return; 1229 } 1230 1231 #ifdef MMCCAM 1232 sc->ccb = NULL; 1233 sc->curcmd = NULL; 1234 ccb->ccb_h.status = 1235 (ccb->mmcio.cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 1236 xpt_done(ccb); 1237 #else 1238 sc->req = NULL; 1239 sc->curcmd = NULL; 1240 req->done(req); 1241 #endif 1242 } 1243 1244 static int 1245 dwmmc_request(device_t brdev, device_t reqdev, struct mmc_request *req) 1246 { 1247 struct dwmmc_softc *sc; 1248 1249 sc = device_get_softc(brdev); 1250 1251 dprintf("%s\n", __func__); 1252 1253 DWMMC_LOCK(sc); 1254 1255 #ifdef MMCCAM 1256 sc->flags |= PENDING_CMD; 1257 #else 1258 if (sc->req != NULL) { 1259 DWMMC_UNLOCK(sc); 1260 return (EBUSY); 1261 } 1262 1263 sc->req = req; 1264 sc->flags |= PENDING_CMD; 1265 if (sc->req->stop) 1266 sc->flags |= PENDING_STOP; 1267 #endif 1268 dwmmc_next_operation(sc); 1269 1270 DWMMC_UNLOCK(sc); 1271 return (0); 1272 } 1273 1274 #ifndef MMCCAM 1275 static int 1276 dwmmc_get_ro(device_t brdev, device_t reqdev) 1277 { 1278 1279 dprintf("%s\n", __func__); 1280 1281 return (0); 1282 } 1283 1284 static int 1285 dwmmc_acquire_host(device_t brdev, device_t reqdev) 1286 { 1287 struct dwmmc_softc *sc; 1288 1289 sc = device_get_softc(brdev); 1290 1291 DWMMC_LOCK(sc); 1292 while (sc->bus_busy) 1293 msleep(sc, &sc->sc_mtx, PZERO, "dwmmcah", hz / 5); 1294 sc->bus_busy++; 1295 DWMMC_UNLOCK(sc); 1296 return (0); 1297 } 1298 1299 static int 1300 dwmmc_release_host(device_t brdev, device_t reqdev) 1301 { 1302 struct dwmmc_softc *sc; 1303 1304 sc = device_get_softc(brdev); 1305 1306 DWMMC_LOCK(sc); 1307 sc->bus_busy--; 1308 wakeup(sc); 1309 DWMMC_UNLOCK(sc); 1310 return (0); 1311 } 1312 #endif /* !MMCCAM */ 1313 1314 static int 1315 dwmmc_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 1316 { 1317 struct dwmmc_softc *sc; 1318 1319 sc = device_get_softc(bus); 1320 1321 switch (which) { 1322 default: 1323 return (EINVAL); 1324 case MMCBR_IVAR_BUS_MODE: 1325 *(int *)result = sc->host.ios.bus_mode; 1326 break; 1327 case MMCBR_IVAR_BUS_WIDTH: 1328 *(int *)result = sc->host.ios.bus_width; 1329 break; 1330 case MMCBR_IVAR_CHIP_SELECT: 1331 *(int *)result = sc->host.ios.chip_select; 1332 break; 1333 case MMCBR_IVAR_CLOCK: 1334 *(int *)result = sc->host.ios.clock; 1335 break; 1336 case MMCBR_IVAR_F_MIN: 1337 *(int *)result = sc->host.f_min; 1338 break; 1339 case MMCBR_IVAR_F_MAX: 1340 *(int *)result = sc->host.f_max; 1341 break; 1342 case MMCBR_IVAR_HOST_OCR: 1343 *(int *)result = sc->host.host_ocr; 1344 break; 1345 case MMCBR_IVAR_MODE: 1346 *(int *)result = sc->host.mode; 1347 break; 1348 case MMCBR_IVAR_OCR: 1349 *(int *)result = sc->host.ocr; 1350 break; 1351 case MMCBR_IVAR_POWER_MODE: 1352 *(int *)result = sc->host.ios.power_mode; 1353 break; 1354 case MMCBR_IVAR_VDD: 1355 *(int *)result = sc->host.ios.vdd; 1356 break; 1357 case MMCBR_IVAR_VCCQ: 1358 *(int *)result = sc->host.ios.vccq; 1359 break; 1360 case MMCBR_IVAR_CAPS: 1361 *(int *)result = sc->host.caps; 1362 break; 1363 case MMCBR_IVAR_MAX_DATA: 1364 /* 1365 * Busdma may bounce buffers, so we must reserve 2 descriptors 1366 * (on start and on end) for bounced fragments. 1367 * 1368 */ 1369 *(int *)result = (IDMAC_MAX_SIZE * IDMAC_DESC_SEGS) / 1370 MMC_SECTOR_SIZE - 3; 1371 break; 1372 case MMCBR_IVAR_TIMING: 1373 *(int *)result = sc->host.ios.timing; 1374 break; 1375 } 1376 return (0); 1377 } 1378 1379 static int 1380 dwmmc_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1381 { 1382 struct dwmmc_softc *sc; 1383 1384 sc = device_get_softc(bus); 1385 1386 switch (which) { 1387 default: 1388 return (EINVAL); 1389 case MMCBR_IVAR_BUS_MODE: 1390 sc->host.ios.bus_mode = value; 1391 break; 1392 case MMCBR_IVAR_BUS_WIDTH: 1393 sc->host.ios.bus_width = value; 1394 break; 1395 case MMCBR_IVAR_CHIP_SELECT: 1396 sc->host.ios.chip_select = value; 1397 break; 1398 case MMCBR_IVAR_CLOCK: 1399 sc->host.ios.clock = value; 1400 break; 1401 case MMCBR_IVAR_MODE: 1402 sc->host.mode = value; 1403 break; 1404 case MMCBR_IVAR_OCR: 1405 sc->host.ocr = value; 1406 break; 1407 case MMCBR_IVAR_POWER_MODE: 1408 sc->host.ios.power_mode = value; 1409 break; 1410 case MMCBR_IVAR_VDD: 1411 sc->host.ios.vdd = value; 1412 break; 1413 case MMCBR_IVAR_TIMING: 1414 sc->host.ios.timing = value; 1415 break; 1416 case MMCBR_IVAR_VCCQ: 1417 sc->host.ios.vccq = value; 1418 break; 1419 /* These are read-only */ 1420 case MMCBR_IVAR_CAPS: 1421 case MMCBR_IVAR_HOST_OCR: 1422 case MMCBR_IVAR_F_MIN: 1423 case MMCBR_IVAR_F_MAX: 1424 case MMCBR_IVAR_MAX_DATA: 1425 return (EINVAL); 1426 } 1427 return (0); 1428 } 1429 1430 #ifdef MMCCAM 1431 /* Note: this function likely belongs to the specific driver impl */ 1432 static int 1433 dwmmc_switch_vccq(device_t dev, device_t child) 1434 { 1435 device_printf(dev, "This is a default impl of switch_vccq() that always fails\n"); 1436 return EINVAL; 1437 } 1438 1439 static int 1440 dwmmc_get_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts) 1441 { 1442 struct dwmmc_softc *sc; 1443 1444 sc = device_get_softc(dev); 1445 1446 cts->host_ocr = sc->host.host_ocr; 1447 cts->host_f_min = sc->host.f_min; 1448 cts->host_f_max = sc->host.f_max; 1449 cts->host_caps = sc->host.caps; 1450 cts->host_max_data = (IDMAC_MAX_SIZE * IDMAC_DESC_SEGS) / MMC_SECTOR_SIZE; 1451 memcpy(&cts->ios, &sc->host.ios, sizeof(struct mmc_ios)); 1452 1453 return (0); 1454 } 1455 1456 static int 1457 dwmmc_set_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts) 1458 { 1459 struct dwmmc_softc *sc; 1460 struct mmc_ios *ios; 1461 struct mmc_ios *new_ios; 1462 int res; 1463 1464 sc = device_get_softc(dev); 1465 ios = &sc->host.ios; 1466 1467 new_ios = &cts->ios; 1468 1469 /* Update only requested fields */ 1470 if (cts->ios_valid & MMC_CLK) { 1471 ios->clock = new_ios->clock; 1472 if (bootverbose) 1473 device_printf(sc->dev, "Clock => %d\n", ios->clock); 1474 } 1475 if (cts->ios_valid & MMC_VDD) { 1476 ios->vdd = new_ios->vdd; 1477 if (bootverbose) 1478 device_printf(sc->dev, "VDD => %d\n", ios->vdd); 1479 } 1480 if (cts->ios_valid & MMC_CS) { 1481 ios->chip_select = new_ios->chip_select; 1482 if (bootverbose) 1483 device_printf(sc->dev, "CS => %d\n", ios->chip_select); 1484 } 1485 if (cts->ios_valid & MMC_BW) { 1486 ios->bus_width = new_ios->bus_width; 1487 if (bootverbose) 1488 device_printf(sc->dev, "Bus width => %d\n", ios->bus_width); 1489 } 1490 if (cts->ios_valid & MMC_PM) { 1491 ios->power_mode = new_ios->power_mode; 1492 if (bootverbose) 1493 device_printf(sc->dev, "Power mode => %d\n", ios->power_mode); 1494 } 1495 if (cts->ios_valid & MMC_BT) { 1496 ios->timing = new_ios->timing; 1497 if (bootverbose) 1498 device_printf(sc->dev, "Timing => %d\n", ios->timing); 1499 } 1500 if (cts->ios_valid & MMC_BM) { 1501 ios->bus_mode = new_ios->bus_mode; 1502 if (bootverbose) 1503 device_printf(sc->dev, "Bus mode => %d\n", ios->bus_mode); 1504 } 1505 if (cts->ios_valid & MMC_VCCQ) { 1506 ios->vccq = new_ios->vccq; 1507 if (bootverbose) 1508 device_printf(sc->dev, "VCCQ => %d\n", ios->vccq); 1509 res = dwmmc_switch_vccq(sc->dev, NULL); 1510 device_printf(sc->dev, "VCCQ switch result: %d\n", res); 1511 } 1512 1513 return (dwmmc_update_ios(sc->dev, NULL)); 1514 } 1515 1516 static int 1517 dwmmc_cam_request(device_t dev, union ccb *ccb) 1518 { 1519 struct dwmmc_softc *sc; 1520 struct ccb_mmcio *mmcio; 1521 1522 sc = device_get_softc(dev); 1523 mmcio = &ccb->mmcio; 1524 1525 DWMMC_LOCK(sc); 1526 1527 #ifdef DEBUG 1528 if (__predict_false(bootverbose)) { 1529 device_printf(sc->dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1530 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags, 1531 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0, 1532 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0); 1533 } 1534 #endif 1535 if (mmcio->cmd.data != NULL) { 1536 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0) 1537 panic("data->len = %d, data->flags = %d -- something is b0rked", 1538 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags); 1539 } 1540 if (sc->ccb != NULL) { 1541 device_printf(sc->dev, "Controller still has an active command\n"); 1542 return (EBUSY); 1543 } 1544 sc->ccb = ccb; 1545 DWMMC_UNLOCK(sc); 1546 dwmmc_request(sc->dev, NULL, NULL); 1547 1548 return (0); 1549 } 1550 #endif /* MMCCAM */ 1551 1552 static device_method_t dwmmc_methods[] = { 1553 /* Bus interface */ 1554 DEVMETHOD(bus_read_ivar, dwmmc_read_ivar), 1555 DEVMETHOD(bus_write_ivar, dwmmc_write_ivar), 1556 1557 #ifndef MMCCAM 1558 /* mmcbr_if */ 1559 DEVMETHOD(mmcbr_update_ios, dwmmc_update_ios), 1560 DEVMETHOD(mmcbr_request, dwmmc_request), 1561 DEVMETHOD(mmcbr_get_ro, dwmmc_get_ro), 1562 DEVMETHOD(mmcbr_acquire_host, dwmmc_acquire_host), 1563 DEVMETHOD(mmcbr_release_host, dwmmc_release_host), 1564 #endif 1565 1566 #ifdef MMCCAM 1567 /* MMCCAM interface */ 1568 DEVMETHOD(mmc_sim_get_tran_settings, dwmmc_get_tran_settings), 1569 DEVMETHOD(mmc_sim_set_tran_settings, dwmmc_set_tran_settings), 1570 DEVMETHOD(mmc_sim_cam_request, dwmmc_cam_request), 1571 1572 DEVMETHOD(bus_add_child, bus_generic_add_child), 1573 #endif 1574 1575 DEVMETHOD_END 1576 }; 1577 1578 DEFINE_CLASS_0(dwmmc, dwmmc_driver, dwmmc_methods, 1579 sizeof(struct dwmmc_softc)); 1580