1 /*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Synopsys DesignWare Mobile Storage Host Controller 33 * Chapter 14, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22) 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/bus.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/malloc.h> 45 #include <sys/rman.h> 46 #include <sys/timeet.h> 47 #include <sys/timetc.h> 48 49 #include <dev/mmc/bridge.h> 50 #include <dev/mmc/mmcreg.h> 51 #include <dev/mmc/mmcbrvar.h> 52 53 #include <dev/fdt/fdt_common.h> 54 #include <dev/ofw/openfirm.h> 55 #include <dev/ofw/ofw_bus.h> 56 #include <dev/ofw/ofw_bus_subr.h> 57 58 #include <machine/bus.h> 59 #include <machine/fdt.h> 60 #include <machine/cpu.h> 61 #include <machine/intr.h> 62 63 #include <dev/mmc/host/dwmmc.h> 64 65 #include "mmcbr_if.h" 66 67 #define dprintf(x, arg...) 68 69 #define READ4(_sc, _reg) \ 70 bus_read_4((_sc)->res[0], _reg) 71 #define WRITE4(_sc, _reg, _val) \ 72 bus_write_4((_sc)->res[0], _reg, _val) 73 74 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 75 76 #define DWMMC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 77 #define DWMMC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 78 #define DWMMC_LOCK_INIT(_sc) \ 79 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 80 "dwmmc", MTX_DEF) 81 #define DWMMC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 82 #define DWMMC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 83 #define DWMMC_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 84 85 #define PENDING_CMD 0x01 86 #define PENDING_STOP 0x02 87 #define CARD_INIT_DONE 0x04 88 89 #define DWMMC_DATA_ERR_FLAGS (SDMMC_INTMASK_DRT | SDMMC_INTMASK_DCRC \ 90 |SDMMC_INTMASK_HTO | SDMMC_INTMASK_SBE \ 91 |SDMMC_INTMASK_EBE) 92 #define DWMMC_CMD_ERR_FLAGS (SDMMC_INTMASK_RTO | SDMMC_INTMASK_RCRC \ 93 |SDMMC_INTMASK_RE) 94 #define DWMMC_ERR_FLAGS (DWMMC_DATA_ERR_FLAGS | DWMMC_CMD_ERR_FLAGS \ 95 |SDMMC_INTMASK_HLE) 96 97 #define DES0_DIC (1 << 1) 98 #define DES0_LD (1 << 2) 99 #define DES0_FS (1 << 3) 100 #define DES0_CH (1 << 4) 101 #define DES0_ER (1 << 5) 102 #define DES0_CES (1 << 30) 103 #define DES0_OWN (1 << 31) 104 105 #define DES1_BS1_MASK 0xfff 106 #define DES1_BS1_SHIFT 0 107 108 struct idmac_desc { 109 uint32_t des0; /* control */ 110 uint32_t des1; /* bufsize */ 111 uint32_t des2; /* buf1 phys addr */ 112 uint32_t des3; /* buf2 phys addr or next descr */ 113 }; 114 115 #define DESC_COUNT 256 116 #define DESC_SIZE (sizeof(struct idmac_desc) * DESC_COUNT) 117 #define DEF_MSIZE 0x2 /* Burst size of multiple transaction */ 118 119 struct dwmmc_softc { 120 struct resource *res[2]; 121 bus_space_tag_t bst; 122 bus_space_handle_t bsh; 123 device_t dev; 124 void *intr_cookie; 125 struct mmc_host host; 126 struct mtx sc_mtx; 127 struct mmc_request *req; 128 struct mmc_command *curcmd; 129 uint32_t flags; 130 uint32_t hwtype; 131 uint32_t use_auto_stop; 132 133 bus_dma_tag_t desc_tag; 134 bus_dmamap_t desc_map; 135 struct idmac_desc *desc_ring; 136 bus_addr_t desc_ring_paddr; 137 bus_dma_tag_t buf_tag; 138 bus_dmamap_t buf_map; 139 140 uint32_t bus_busy; 141 uint32_t dto_rcvd; 142 uint32_t acd_rcvd; 143 uint32_t cmd_done; 144 uint32_t bus_hz; 145 uint32_t fifo_depth; 146 uint32_t num_slots; 147 uint32_t sdr_timing; 148 uint32_t ddr_timing; 149 }; 150 151 static void dwmmc_next_operation(struct dwmmc_softc *); 152 static int dwmmc_setup_bus(struct dwmmc_softc *, int); 153 static int dma_done(struct dwmmc_softc *, struct mmc_command *); 154 static int dma_stop(struct dwmmc_softc *); 155 156 static struct resource_spec dwmmc_spec[] = { 157 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 158 { SYS_RES_IRQ, 0, RF_ACTIVE }, 159 { -1, 0 } 160 }; 161 162 enum { 163 HWTYPE_NONE, 164 HWTYPE_ALTERA, 165 HWTYPE_EXYNOS, 166 }; 167 168 #define HWTYPE_MASK (0x0000ffff) 169 #define HWFLAG_MASK (0xffff << 16) 170 171 static struct ofw_compat_data compat_data[] = { 172 {"altr,socfpga-dw-mshc", HWTYPE_ALTERA}, 173 {"samsung,exynos5420-dw-mshc", HWTYPE_EXYNOS}, 174 {NULL, HWTYPE_NONE}, 175 }; 176 177 static void 178 dwmmc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 179 { 180 181 if (error != 0) 182 return; 183 *(bus_addr_t *)arg = segs[0].ds_addr; 184 } 185 186 static void 187 dwmmc_ring_setup(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 188 { 189 struct dwmmc_softc *sc; 190 int idx; 191 192 if (error != 0) 193 return; 194 195 sc = arg; 196 197 dprintf("nsegs %d seg0len %lu\n", nsegs, segs[0].ds_len); 198 199 for (idx = 0; idx < nsegs; idx++) { 200 sc->desc_ring[idx].des0 = (DES0_OWN | DES0_DIC | DES0_CH); 201 sc->desc_ring[idx].des1 = segs[idx].ds_len; 202 sc->desc_ring[idx].des2 = segs[idx].ds_addr; 203 204 if (idx == 0) 205 sc->desc_ring[idx].des0 |= DES0_FS; 206 207 if (idx == (nsegs - 1)) { 208 sc->desc_ring[idx].des0 &= ~(DES0_DIC | DES0_CH); 209 sc->desc_ring[idx].des0 |= DES0_LD; 210 } 211 } 212 } 213 214 static int 215 dwmmc_ctrl_reset(struct dwmmc_softc *sc, int reset_bits) 216 { 217 int reg; 218 int i; 219 220 reg = READ4(sc, SDMMC_CTRL); 221 reg |= (reset_bits); 222 WRITE4(sc, SDMMC_CTRL, reg); 223 224 /* Wait reset done */ 225 for (i = 0; i < 100; i++) { 226 if (!(READ4(sc, SDMMC_CTRL) & reset_bits)) 227 return (0); 228 DELAY(10); 229 }; 230 231 device_printf(sc->dev, "Reset failed\n"); 232 233 return (1); 234 } 235 236 static int 237 dma_setup(struct dwmmc_softc *sc) 238 { 239 int error; 240 int nidx; 241 int idx; 242 243 /* 244 * Set up TX descriptor ring, descriptors, and dma maps. 245 */ 246 error = bus_dma_tag_create( 247 bus_get_dma_tag(sc->dev), /* Parent tag. */ 248 4096, 0, /* alignment, boundary */ 249 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 250 BUS_SPACE_MAXADDR, /* highaddr */ 251 NULL, NULL, /* filter, filterarg */ 252 DESC_SIZE, 1, /* maxsize, nsegments */ 253 DESC_SIZE, /* maxsegsize */ 254 0, /* flags */ 255 NULL, NULL, /* lockfunc, lockarg */ 256 &sc->desc_tag); 257 if (error != 0) { 258 device_printf(sc->dev, 259 "could not create ring DMA tag.\n"); 260 return (1); 261 } 262 263 error = bus_dmamem_alloc(sc->desc_tag, (void**)&sc->desc_ring, 264 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 265 &sc->desc_map); 266 if (error != 0) { 267 device_printf(sc->dev, 268 "could not allocate descriptor ring.\n"); 269 return (1); 270 } 271 272 error = bus_dmamap_load(sc->desc_tag, sc->desc_map, 273 sc->desc_ring, DESC_SIZE, dwmmc_get1paddr, 274 &sc->desc_ring_paddr, 0); 275 if (error != 0) { 276 device_printf(sc->dev, 277 "could not load descriptor ring map.\n"); 278 return (1); 279 } 280 281 for (idx = 0; idx < DESC_COUNT; idx++) { 282 sc->desc_ring[idx].des0 = DES0_CH; 283 sc->desc_ring[idx].des1 = 0; 284 nidx = (idx + 1) % DESC_COUNT; 285 sc->desc_ring[idx].des3 = sc->desc_ring_paddr + \ 286 (nidx * sizeof(struct idmac_desc)); 287 } 288 289 error = bus_dma_tag_create( 290 bus_get_dma_tag(sc->dev), /* Parent tag. */ 291 4096, 0, /* alignment, boundary */ 292 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 293 BUS_SPACE_MAXADDR, /* highaddr */ 294 NULL, NULL, /* filter, filterarg */ 295 DESC_COUNT*MMC_SECTOR_SIZE, /* maxsize */ 296 DESC_COUNT, /* nsegments */ 297 MMC_SECTOR_SIZE, /* maxsegsize */ 298 0, /* flags */ 299 NULL, NULL, /* lockfunc, lockarg */ 300 &sc->buf_tag); 301 if (error != 0) { 302 device_printf(sc->dev, 303 "could not create ring DMA tag.\n"); 304 return (1); 305 } 306 307 error = bus_dmamap_create(sc->buf_tag, 0, 308 &sc->buf_map); 309 if (error != 0) { 310 device_printf(sc->dev, 311 "could not create TX buffer DMA map.\n"); 312 return (1); 313 } 314 315 return (0); 316 } 317 318 static void 319 dwmmc_cmd_done(struct dwmmc_softc *sc) 320 { 321 struct mmc_command *cmd; 322 323 cmd = sc->curcmd; 324 if (cmd == NULL) 325 return; 326 327 if (cmd->flags & MMC_RSP_PRESENT) { 328 if (cmd->flags & MMC_RSP_136) { 329 cmd->resp[3] = READ4(sc, SDMMC_RESP0); 330 cmd->resp[2] = READ4(sc, SDMMC_RESP1); 331 cmd->resp[1] = READ4(sc, SDMMC_RESP2); 332 cmd->resp[0] = READ4(sc, SDMMC_RESP3); 333 } else { 334 cmd->resp[3] = 0; 335 cmd->resp[2] = 0; 336 cmd->resp[1] = 0; 337 cmd->resp[0] = READ4(sc, SDMMC_RESP0); 338 } 339 } 340 } 341 342 static void 343 dwmmc_tasklet(struct dwmmc_softc *sc) 344 { 345 struct mmc_command *cmd; 346 347 cmd = sc->curcmd; 348 if (cmd == NULL) 349 return; 350 351 if (!sc->cmd_done) 352 return; 353 354 if (cmd->error != MMC_ERR_NONE || !cmd->data) { 355 dwmmc_next_operation(sc); 356 } else if (cmd->data && sc->dto_rcvd) { 357 if ((cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK || 358 cmd->opcode == MMC_READ_MULTIPLE_BLOCK) && 359 sc->use_auto_stop) { 360 if (sc->acd_rcvd) 361 dwmmc_next_operation(sc); 362 } else { 363 dwmmc_next_operation(sc); 364 } 365 } 366 } 367 368 static void 369 dwmmc_intr(void *arg) 370 { 371 struct mmc_command *cmd; 372 struct dwmmc_softc *sc; 373 uint32_t reg; 374 375 sc = arg; 376 377 DWMMC_LOCK(sc); 378 379 cmd = sc->curcmd; 380 381 /* First handle SDMMC controller interrupts */ 382 reg = READ4(sc, SDMMC_MINTSTS); 383 if (reg) { 384 dprintf("%s 0x%08x\n", __func__, reg); 385 386 if (reg & DWMMC_CMD_ERR_FLAGS) { 387 WRITE4(sc, SDMMC_RINTSTS, DWMMC_CMD_ERR_FLAGS); 388 dprintf("cmd err 0x%08x cmd 0x%08x\n", 389 reg, cmd->opcode); 390 cmd->error = MMC_ERR_TIMEOUT; 391 } 392 393 if (reg & DWMMC_DATA_ERR_FLAGS) { 394 WRITE4(sc, SDMMC_RINTSTS, DWMMC_DATA_ERR_FLAGS); 395 dprintf("data err 0x%08x cmd 0x%08x\n", 396 reg, cmd->opcode); 397 cmd->error = MMC_ERR_FAILED; 398 dma_done(sc, cmd); 399 dma_stop(sc); 400 } 401 402 if (reg & SDMMC_INTMASK_CMD_DONE) { 403 dwmmc_cmd_done(sc); 404 sc->cmd_done = 1; 405 WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_CMD_DONE); 406 } 407 408 if (reg & SDMMC_INTMASK_ACD) { 409 sc->acd_rcvd = 1; 410 WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_ACD); 411 } 412 413 if (reg & SDMMC_INTMASK_DTO) { 414 sc->dto_rcvd = 1; 415 WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_DTO); 416 } 417 418 if (reg & SDMMC_INTMASK_CD) { 419 /* XXX: Handle card detect */ 420 WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_CD); 421 } 422 } 423 424 /* Now handle DMA interrupts */ 425 reg = READ4(sc, SDMMC_IDSTS); 426 if (reg) { 427 dprintf("dma intr 0x%08x\n", reg); 428 if (reg & (SDMMC_IDINTEN_TI | SDMMC_IDINTEN_RI)) { 429 WRITE4(sc, SDMMC_IDSTS, (SDMMC_IDINTEN_TI | 430 SDMMC_IDINTEN_RI)); 431 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_NI); 432 dma_done(sc, cmd); 433 } 434 } 435 436 dwmmc_tasklet(sc); 437 438 DWMMC_UNLOCK(sc); 439 } 440 441 static int 442 parse_fdt(struct dwmmc_softc *sc) 443 { 444 pcell_t dts_value[3]; 445 phandle_t node; 446 int len; 447 448 if ((node = ofw_bus_get_node(sc->dev)) == -1) 449 return (ENXIO); 450 451 /* fifo-depth */ 452 if ((len = OF_getproplen(node, "fifo-depth")) <= 0) 453 return (ENXIO); 454 OF_getencprop(node, "fifo-depth", dts_value, len); 455 sc->fifo_depth = dts_value[0]; 456 457 /* num-slots */ 458 if ((len = OF_getproplen(node, "num-slots")) <= 0) 459 return (ENXIO); 460 OF_getencprop(node, "num-slots", dts_value, len); 461 sc->num_slots = dts_value[0]; 462 463 /* 464 * We need some platform-specific code to know 465 * what the clock is supplied for our device. 466 * For now rely on the value specified in FDT. 467 */ 468 if ((len = OF_getproplen(node, "bus-frequency")) <= 0) 469 return (ENXIO); 470 OF_getencprop(node, "bus-frequency", dts_value, len); 471 sc->bus_hz = dts_value[0]; 472 473 /* 474 * Platform-specific stuff 475 * XXX: Move to separate file 476 */ 477 478 if ((sc->hwtype & HWTYPE_MASK) != HWTYPE_EXYNOS) 479 return (0); 480 481 if ((len = OF_getproplen(node, "samsung,dw-mshc-ciu-div")) <= 0) 482 return (ENXIO); 483 OF_getencprop(node, "samsung,dw-mshc-ciu-div", dts_value, len); 484 sc->sdr_timing = (dts_value[0] << SDMMC_CLKSEL_DIVIDER_SHIFT); 485 sc->ddr_timing = (dts_value[0] << SDMMC_CLKSEL_DIVIDER_SHIFT); 486 487 if ((len = OF_getproplen(node, "samsung,dw-mshc-sdr-timing")) <= 0) 488 return (ENXIO); 489 OF_getencprop(node, "samsung,dw-mshc-sdr-timing", dts_value, len); 490 sc->sdr_timing |= ((dts_value[0] << SDMMC_CLKSEL_SAMPLE_SHIFT) | 491 (dts_value[1] << SDMMC_CLKSEL_DRIVE_SHIFT)); 492 493 if ((len = OF_getproplen(node, "samsung,dw-mshc-ddr-timing")) <= 0) 494 return (ENXIO); 495 OF_getencprop(node, "samsung,dw-mshc-ddr-timing", dts_value, len); 496 sc->ddr_timing |= ((dts_value[0] << SDMMC_CLKSEL_SAMPLE_SHIFT) | 497 (dts_value[1] << SDMMC_CLKSEL_DRIVE_SHIFT)); 498 499 return (0); 500 } 501 502 static int 503 dwmmc_probe(device_t dev) 504 { 505 uintptr_t hwtype; 506 507 if (!ofw_bus_status_okay(dev)) 508 return (ENXIO); 509 510 hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 511 if (hwtype == HWTYPE_NONE) 512 return (ENXIO); 513 514 device_set_desc(dev, "Synopsys DesignWare Mobile " 515 "Storage Host Controller"); 516 return (BUS_PROBE_DEFAULT); 517 } 518 519 static int 520 dwmmc_attach(device_t dev) 521 { 522 struct dwmmc_softc *sc; 523 device_t child; 524 int error; 525 int slot; 526 527 sc = device_get_softc(dev); 528 529 sc->dev = dev; 530 sc->hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 531 532 /* Why not to use Auto Stop? It save a hundred of irq per second */ 533 sc->use_auto_stop = 1; 534 535 error = parse_fdt(sc); 536 if (error != 0) { 537 device_printf(dev, "Can't get FDT property.\n"); 538 return (ENXIO); 539 } 540 541 DWMMC_LOCK_INIT(sc); 542 543 if (bus_alloc_resources(dev, dwmmc_spec, sc->res)) { 544 device_printf(dev, "could not allocate resources\n"); 545 return (ENXIO); 546 } 547 548 /* Memory interface */ 549 sc->bst = rman_get_bustag(sc->res[0]); 550 sc->bsh = rman_get_bushandle(sc->res[0]); 551 552 /* Setup interrupt handler. */ 553 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE, 554 NULL, dwmmc_intr, sc, &sc->intr_cookie); 555 if (error != 0) { 556 device_printf(dev, "could not setup interrupt handler.\n"); 557 return (ENXIO); 558 } 559 560 device_printf(dev, "Hardware version ID is %04x\n", 561 READ4(sc, SDMMC_VERID) & 0xffff); 562 563 WRITE4(sc, EMMCP_MPSBEGIN0, 0); 564 WRITE4(sc, EMMCP_SEND0, 0); 565 WRITE4(sc, EMMCP_CTRL0, (MPSCTRL_SECURE_READ_BIT | 566 MPSCTRL_SECURE_WRITE_BIT | 567 MPSCTRL_NON_SECURE_READ_BIT | 568 MPSCTRL_NON_SECURE_WRITE_BIT | 569 MPSCTRL_VALID)); 570 571 /* XXX: we support operation for slot index 0 only */ 572 slot = 0; 573 WRITE4(sc, SDMMC_PWREN, (1 << slot)); 574 575 /* Reset all */ 576 if (dwmmc_ctrl_reset(sc, (SDMMC_CTRL_RESET | 577 SDMMC_CTRL_FIFO_RESET | 578 SDMMC_CTRL_DMA_RESET))) 579 return (ENXIO); 580 581 dwmmc_setup_bus(sc, sc->host.f_min); 582 583 if (dma_setup(sc)) 584 return (ENXIO); 585 586 /* Install desc base */ 587 WRITE4(sc, SDMMC_DBADDR, sc->desc_ring_paddr); 588 589 /* Enable DMA interrupts */ 590 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_MASK); 591 WRITE4(sc, SDMMC_IDINTEN, (SDMMC_IDINTEN_NI | 592 SDMMC_IDINTEN_RI | 593 SDMMC_IDINTEN_TI)); 594 595 /* Clear and disable interrups for a while */ 596 WRITE4(sc, SDMMC_RINTSTS, 0xffffffff); 597 WRITE4(sc, SDMMC_INTMASK, 0); 598 599 /* Maximum timeout */ 600 WRITE4(sc, SDMMC_TMOUT, 0xffffffff); 601 602 /* Enable interrupts */ 603 WRITE4(sc, SDMMC_RINTSTS, 0xffffffff); 604 WRITE4(sc, SDMMC_INTMASK, (SDMMC_INTMASK_CMD_DONE | 605 SDMMC_INTMASK_DTO | 606 SDMMC_INTMASK_ACD | 607 SDMMC_INTMASK_TXDR | 608 SDMMC_INTMASK_RXDR | 609 DWMMC_ERR_FLAGS | 610 SDMMC_INTMASK_CD)); 611 WRITE4(sc, SDMMC_CTRL, SDMMC_CTRL_INT_ENABLE); 612 613 sc->host.f_min = 400000; 614 sc->host.f_max = 200000000; 615 sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340; 616 sc->host.caps = MMC_CAP_4_BIT_DATA; 617 618 child = device_add_child(dev, "mmc", 0); 619 return (bus_generic_attach(dev)); 620 } 621 622 static int 623 dwmmc_setup_bus(struct dwmmc_softc *sc, int freq) 624 { 625 int tout; 626 int div; 627 628 if (freq == 0) { 629 WRITE4(sc, SDMMC_CLKENA, 0); 630 WRITE4(sc, SDMMC_CMD, (SDMMC_CMD_WAIT_PRVDATA | 631 SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START)); 632 633 tout = 1000; 634 do { 635 if (tout-- < 0) { 636 device_printf(sc->dev, "Failed update clk\n"); 637 return (1); 638 } 639 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START); 640 641 return (0); 642 } 643 644 WRITE4(sc, SDMMC_CLKENA, 0); 645 WRITE4(sc, SDMMC_CLKSRC, 0); 646 647 div = (sc->bus_hz != freq) ? DIV_ROUND_UP(sc->bus_hz, 2 * freq) : 0; 648 649 WRITE4(sc, SDMMC_CLKDIV, div); 650 WRITE4(sc, SDMMC_CMD, (SDMMC_CMD_WAIT_PRVDATA | 651 SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START)); 652 653 tout = 1000; 654 do { 655 if (tout-- < 0) { 656 device_printf(sc->dev, "Failed to update clk"); 657 return (1); 658 } 659 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START); 660 661 WRITE4(sc, SDMMC_CLKENA, (SDMMC_CLKENA_CCLK_EN | SDMMC_CLKENA_LP)); 662 WRITE4(sc, SDMMC_CMD, SDMMC_CMD_WAIT_PRVDATA | 663 SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START); 664 665 tout = 1000; 666 do { 667 if (tout-- < 0) { 668 device_printf(sc->dev, "Failed to enable clk\n"); 669 return (1); 670 } 671 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START); 672 673 return (0); 674 } 675 676 static int 677 dwmmc_update_ios(device_t brdev, device_t reqdev) 678 { 679 struct dwmmc_softc *sc; 680 struct mmc_ios *ios; 681 682 sc = device_get_softc(brdev); 683 ios = &sc->host.ios; 684 685 dprintf("Setting up clk %u bus_width %d\n", 686 ios->clock, ios->bus_width); 687 688 dwmmc_setup_bus(sc, ios->clock); 689 690 if (ios->bus_width == bus_width_8) 691 WRITE4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT); 692 else if (ios->bus_width == bus_width_4) 693 WRITE4(sc, SDMMC_CTYPE, SDMMC_CTYPE_4BIT); 694 else 695 WRITE4(sc, SDMMC_CTYPE, 0); 696 697 if ((sc->hwtype & HWTYPE_MASK) == HWTYPE_EXYNOS) { 698 /* XXX: take care about DDR or SDR use here */ 699 WRITE4(sc, SDMMC_CLKSEL, sc->sdr_timing); 700 } 701 702 /* 703 * XXX: take care about DDR bit 704 * 705 * reg = READ4(sc, SDMMC_UHS_REG); 706 * reg |= (SDMMC_UHS_REG_DDR); 707 * WRITE4(sc, SDMMC_UHS_REG, reg); 708 */ 709 710 return (0); 711 } 712 713 static int 714 dma_done(struct dwmmc_softc *sc, struct mmc_command *cmd) 715 { 716 struct mmc_data *data; 717 718 data = cmd->data; 719 720 if (data->flags & MMC_DATA_WRITE) 721 bus_dmamap_sync(sc->buf_tag, sc->buf_map, 722 BUS_DMASYNC_POSTWRITE); 723 else 724 bus_dmamap_sync(sc->buf_tag, sc->buf_map, 725 BUS_DMASYNC_POSTREAD); 726 727 bus_dmamap_unload(sc->buf_tag, sc->buf_map); 728 729 return (0); 730 } 731 732 static int 733 dma_stop(struct dwmmc_softc *sc) 734 { 735 int reg; 736 737 reg = READ4(sc, SDMMC_CTRL); 738 reg &= ~(SDMMC_CTRL_USE_IDMAC); 739 reg |= (SDMMC_CTRL_DMA_RESET); 740 WRITE4(sc, SDMMC_CTRL, reg); 741 742 reg = READ4(sc, SDMMC_BMOD); 743 reg &= ~(SDMMC_BMOD_DE | SDMMC_BMOD_FB); 744 reg |= (SDMMC_BMOD_SWR); 745 WRITE4(sc, SDMMC_BMOD, reg); 746 747 return (0); 748 } 749 750 static int 751 dma_prepare(struct dwmmc_softc *sc, struct mmc_command *cmd) 752 { 753 struct mmc_data *data; 754 int len; 755 int err; 756 int reg; 757 758 data = cmd->data; 759 len = data->len; 760 761 reg = READ4(sc, SDMMC_INTMASK); 762 reg &= ~(SDMMC_INTMASK_TXDR | SDMMC_INTMASK_RXDR); 763 WRITE4(sc, SDMMC_INTMASK, reg); 764 765 err = bus_dmamap_load(sc->buf_tag, sc->buf_map, 766 data->data, data->len, dwmmc_ring_setup, 767 sc, BUS_DMA_NOWAIT); 768 if (err != 0) 769 panic("dmamap_load failed\n"); 770 771 if (data->flags & MMC_DATA_WRITE) 772 bus_dmamap_sync(sc->buf_tag, sc->buf_map, 773 BUS_DMASYNC_PREWRITE); 774 else 775 bus_dmamap_sync(sc->buf_tag, sc->buf_map, 776 BUS_DMASYNC_PREREAD); 777 778 reg = (DEF_MSIZE << SDMMC_FIFOTH_MSIZE_S); 779 reg |= ((sc->fifo_depth / 2) - 1) << SDMMC_FIFOTH_RXWMARK_S; 780 reg |= (sc->fifo_depth / 2) << SDMMC_FIFOTH_TXWMARK_S; 781 782 WRITE4(sc, SDMMC_FIFOTH, reg); 783 wmb(); 784 785 reg = READ4(sc, SDMMC_CTRL); 786 reg |= (SDMMC_CTRL_USE_IDMAC | SDMMC_CTRL_DMA_ENABLE); 787 WRITE4(sc, SDMMC_CTRL, reg); 788 wmb(); 789 790 reg = READ4(sc, SDMMC_BMOD); 791 reg |= (SDMMC_BMOD_DE | SDMMC_BMOD_FB); 792 WRITE4(sc, SDMMC_BMOD, reg); 793 794 /* Start */ 795 WRITE4(sc, SDMMC_PLDMND, 1); 796 797 return (0); 798 } 799 800 static void 801 dwmmc_start_cmd(struct dwmmc_softc *sc, struct mmc_command *cmd) 802 { 803 struct mmc_data *data; 804 uint32_t blksz; 805 uint32_t cmdr; 806 807 sc->curcmd = cmd; 808 data = cmd->data; 809 810 /* XXX Upper layers don't always set this */ 811 cmd->mrq = sc->req; 812 813 /* Begin setting up command register. */ 814 815 cmdr = cmd->opcode; 816 817 dprintf("cmd->opcode 0x%08x\n", cmd->opcode); 818 819 if (cmd->opcode == MMC_STOP_TRANSMISSION || 820 cmd->opcode == MMC_GO_IDLE_STATE || 821 cmd->opcode == MMC_GO_INACTIVE_STATE) 822 cmdr |= SDMMC_CMD_STOP_ABORT; 823 else if (cmd->opcode != MMC_SEND_STATUS && data) 824 cmdr |= SDMMC_CMD_WAIT_PRVDATA; 825 826 /* Set up response handling. */ 827 if (MMC_RSP(cmd->flags) != MMC_RSP_NONE) { 828 cmdr |= SDMMC_CMD_RESP_EXP; 829 if (cmd->flags & MMC_RSP_136) 830 cmdr |= SDMMC_CMD_RESP_LONG; 831 } 832 833 if (cmd->flags & MMC_RSP_CRC) 834 cmdr |= SDMMC_CMD_RESP_CRC; 835 836 /* 837 * XXX: Not all platforms want this. 838 */ 839 cmdr |= SDMMC_CMD_USE_HOLD_REG; 840 841 if ((sc->flags & CARD_INIT_DONE) == 0) { 842 sc->flags |= (CARD_INIT_DONE); 843 cmdr |= SDMMC_CMD_SEND_INIT; 844 } 845 846 if (data) { 847 if ((cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK || 848 cmd->opcode == MMC_READ_MULTIPLE_BLOCK) && 849 sc->use_auto_stop) 850 cmdr |= SDMMC_CMD_SEND_ASTOP; 851 852 cmdr |= SDMMC_CMD_DATA_EXP; 853 if (data->flags & MMC_DATA_STREAM) 854 cmdr |= SDMMC_CMD_MODE_STREAM; 855 if (data->flags & MMC_DATA_WRITE) 856 cmdr |= SDMMC_CMD_DATA_WRITE; 857 858 WRITE4(sc, SDMMC_TMOUT, 0xffffffff); 859 WRITE4(sc, SDMMC_BYTCNT, data->len); 860 blksz = (data->len < MMC_SECTOR_SIZE) ? \ 861 data->len : MMC_SECTOR_SIZE; 862 WRITE4(sc, SDMMC_BLKSIZ, blksz); 863 864 dma_prepare(sc, cmd); 865 wmb(); 866 } 867 868 dprintf("cmdr 0x%08x\n", cmdr); 869 870 WRITE4(sc, SDMMC_CMDARG, cmd->arg); 871 wmb(); 872 WRITE4(sc, SDMMC_CMD, cmdr | SDMMC_CMD_START); 873 }; 874 875 static void 876 dwmmc_next_operation(struct dwmmc_softc *sc) 877 { 878 struct mmc_request *req; 879 880 req = sc->req; 881 if (req == NULL) 882 return; 883 884 sc->acd_rcvd = 0; 885 sc->dto_rcvd = 0; 886 sc->cmd_done = 0; 887 888 /* 889 * XXX: Wait until card is still busy. 890 * We do need this to prevent data timeouts, 891 * mostly caused by multi-block write command 892 * followed by single-read. 893 */ 894 while(READ4(sc, SDMMC_STATUS) & (SDMMC_STATUS_DATA_BUSY)) 895 continue; 896 897 if (sc->flags & PENDING_CMD) { 898 sc->flags &= ~PENDING_CMD; 899 dwmmc_start_cmd(sc, req->cmd); 900 return; 901 } else if (sc->flags & PENDING_STOP && !sc->use_auto_stop) { 902 sc->flags &= ~PENDING_STOP; 903 dwmmc_start_cmd(sc, req->stop); 904 return; 905 } 906 907 sc->req = NULL; 908 sc->curcmd = NULL; 909 req->done(req); 910 } 911 912 static int 913 dwmmc_request(device_t brdev, device_t reqdev, struct mmc_request *req) 914 { 915 struct dwmmc_softc *sc; 916 917 sc = device_get_softc(brdev); 918 919 dprintf("%s\n", __func__); 920 921 DWMMC_LOCK(sc); 922 923 if (sc->req != NULL) { 924 DWMMC_UNLOCK(sc); 925 return (EBUSY); 926 } 927 928 sc->req = req; 929 sc->flags |= PENDING_CMD; 930 if (sc->req->stop) 931 sc->flags |= PENDING_STOP; 932 dwmmc_next_operation(sc); 933 934 DWMMC_UNLOCK(sc); 935 return (0); 936 } 937 938 static int 939 dwmmc_get_ro(device_t brdev, device_t reqdev) 940 { 941 942 dprintf("%s\n", __func__); 943 944 return (0); 945 } 946 947 static int 948 dwmmc_acquire_host(device_t brdev, device_t reqdev) 949 { 950 struct dwmmc_softc *sc; 951 952 sc = device_get_softc(brdev); 953 954 DWMMC_LOCK(sc); 955 while (sc->bus_busy) 956 msleep(sc, &sc->sc_mtx, PZERO, "dwmmcah", hz / 5); 957 sc->bus_busy++; 958 DWMMC_UNLOCK(sc); 959 return (0); 960 } 961 962 static int 963 dwmmc_release_host(device_t brdev, device_t reqdev) 964 { 965 struct dwmmc_softc *sc; 966 967 sc = device_get_softc(brdev); 968 969 DWMMC_LOCK(sc); 970 sc->bus_busy--; 971 wakeup(sc); 972 DWMMC_UNLOCK(sc); 973 return (0); 974 } 975 976 static int 977 dwmmc_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 978 { 979 struct dwmmc_softc *sc; 980 981 sc = device_get_softc(bus); 982 983 switch (which) { 984 default: 985 return (EINVAL); 986 case MMCBR_IVAR_BUS_MODE: 987 *(int *)result = sc->host.ios.bus_mode; 988 break; 989 case MMCBR_IVAR_BUS_WIDTH: 990 *(int *)result = sc->host.ios.bus_width; 991 break; 992 case MMCBR_IVAR_CHIP_SELECT: 993 *(int *)result = sc->host.ios.chip_select; 994 break; 995 case MMCBR_IVAR_CLOCK: 996 *(int *)result = sc->host.ios.clock; 997 break; 998 case MMCBR_IVAR_F_MIN: 999 *(int *)result = sc->host.f_min; 1000 break; 1001 case MMCBR_IVAR_F_MAX: 1002 *(int *)result = sc->host.f_max; 1003 break; 1004 case MMCBR_IVAR_HOST_OCR: 1005 *(int *)result = sc->host.host_ocr; 1006 break; 1007 case MMCBR_IVAR_MODE: 1008 *(int *)result = sc->host.mode; 1009 break; 1010 case MMCBR_IVAR_OCR: 1011 *(int *)result = sc->host.ocr; 1012 break; 1013 case MMCBR_IVAR_POWER_MODE: 1014 *(int *)result = sc->host.ios.power_mode; 1015 break; 1016 case MMCBR_IVAR_VDD: 1017 *(int *)result = sc->host.ios.vdd; 1018 break; 1019 case MMCBR_IVAR_CAPS: 1020 sc->host.caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA; 1021 *(int *)result = sc->host.caps; 1022 break; 1023 case MMCBR_IVAR_MAX_DATA: 1024 *(int *)result = DESC_COUNT; 1025 } 1026 return (0); 1027 } 1028 1029 static int 1030 dwmmc_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1031 { 1032 struct dwmmc_softc *sc; 1033 1034 sc = device_get_softc(bus); 1035 1036 switch (which) { 1037 default: 1038 return (EINVAL); 1039 case MMCBR_IVAR_BUS_MODE: 1040 sc->host.ios.bus_mode = value; 1041 break; 1042 case MMCBR_IVAR_BUS_WIDTH: 1043 sc->host.ios.bus_width = value; 1044 break; 1045 case MMCBR_IVAR_CHIP_SELECT: 1046 sc->host.ios.chip_select = value; 1047 break; 1048 case MMCBR_IVAR_CLOCK: 1049 sc->host.ios.clock = value; 1050 break; 1051 case MMCBR_IVAR_MODE: 1052 sc->host.mode = value; 1053 break; 1054 case MMCBR_IVAR_OCR: 1055 sc->host.ocr = value; 1056 break; 1057 case MMCBR_IVAR_POWER_MODE: 1058 sc->host.ios.power_mode = value; 1059 break; 1060 case MMCBR_IVAR_VDD: 1061 sc->host.ios.vdd = value; 1062 break; 1063 /* These are read-only */ 1064 case MMCBR_IVAR_CAPS: 1065 case MMCBR_IVAR_HOST_OCR: 1066 case MMCBR_IVAR_F_MIN: 1067 case MMCBR_IVAR_F_MAX: 1068 case MMCBR_IVAR_MAX_DATA: 1069 return (EINVAL); 1070 } 1071 return (0); 1072 } 1073 1074 static device_method_t dwmmc_methods[] = { 1075 DEVMETHOD(device_probe, dwmmc_probe), 1076 DEVMETHOD(device_attach, dwmmc_attach), 1077 1078 /* Bus interface */ 1079 DEVMETHOD(bus_read_ivar, dwmmc_read_ivar), 1080 DEVMETHOD(bus_write_ivar, dwmmc_write_ivar), 1081 1082 /* mmcbr_if */ 1083 DEVMETHOD(mmcbr_update_ios, dwmmc_update_ios), 1084 DEVMETHOD(mmcbr_request, dwmmc_request), 1085 DEVMETHOD(mmcbr_get_ro, dwmmc_get_ro), 1086 DEVMETHOD(mmcbr_acquire_host, dwmmc_acquire_host), 1087 DEVMETHOD(mmcbr_release_host, dwmmc_release_host), 1088 1089 DEVMETHOD_END 1090 }; 1091 1092 static driver_t dwmmc_driver = { 1093 "dwmmc", 1094 dwmmc_methods, 1095 sizeof(struct dwmmc_softc), 1096 }; 1097 1098 static devclass_t dwmmc_devclass; 1099 1100 DRIVER_MODULE(dwmmc, simplebus, dwmmc_driver, dwmmc_devclass, 0, 0); 1101 1102