1 /*- 2 * Copyright (c) 2014-2019 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Synopsys DesignWare Mobile Storage Host Controller 33 * Chapter 14, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22) 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/bus.h> 42 #include <sys/kernel.h> 43 #include <sys/lock.h> 44 #include <sys/module.h> 45 #include <sys/malloc.h> 46 #include <sys/mutex.h> 47 #include <sys/rman.h> 48 49 #include <dev/mmc/bridge.h> 50 #include <dev/mmc/mmcbrvar.h> 51 52 #include <dev/fdt/fdt_common.h> 53 #include <dev/ofw/openfirm.h> 54 #include <dev/ofw/ofw_bus.h> 55 #include <dev/ofw/ofw_bus_subr.h> 56 57 #include <machine/bus.h> 58 #include <machine/cpu.h> 59 #include <machine/intr.h> 60 61 #ifdef EXT_RESOURCES 62 #include <dev/extres/clk/clk.h> 63 #endif 64 65 #include <dev/mmc/host/dwmmc_reg.h> 66 #include <dev/mmc/host/dwmmc_var.h> 67 68 #include "opt_mmccam.h" 69 70 #include "mmcbr_if.h" 71 72 #define dprintf(x, arg...) 73 74 #define READ4(_sc, _reg) \ 75 bus_read_4((_sc)->res[0], _reg) 76 #define WRITE4(_sc, _reg, _val) \ 77 bus_write_4((_sc)->res[0], _reg, _val) 78 79 #define DIV_ROUND_UP(n, d) howmany(n, d) 80 81 #define DWMMC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 82 #define DWMMC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 83 #define DWMMC_LOCK_INIT(_sc) \ 84 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 85 "dwmmc", MTX_DEF) 86 #define DWMMC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 87 #define DWMMC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 88 #define DWMMC_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 89 90 #define PENDING_CMD 0x01 91 #define PENDING_STOP 0x02 92 #define CARD_INIT_DONE 0x04 93 94 #define DWMMC_DATA_ERR_FLAGS (SDMMC_INTMASK_DRT | SDMMC_INTMASK_DCRC \ 95 |SDMMC_INTMASK_HTO | SDMMC_INTMASK_SBE \ 96 |SDMMC_INTMASK_EBE) 97 #define DWMMC_CMD_ERR_FLAGS (SDMMC_INTMASK_RTO | SDMMC_INTMASK_RCRC \ 98 |SDMMC_INTMASK_RE) 99 #define DWMMC_ERR_FLAGS (DWMMC_DATA_ERR_FLAGS | DWMMC_CMD_ERR_FLAGS \ 100 |SDMMC_INTMASK_HLE) 101 102 #define DES0_DIC (1 << 1) 103 #define DES0_LD (1 << 2) 104 #define DES0_FS (1 << 3) 105 #define DES0_CH (1 << 4) 106 #define DES0_ER (1 << 5) 107 #define DES0_CES (1 << 30) 108 #define DES0_OWN (1 << 31) 109 110 #define DES1_BS1_MASK 0xfff 111 #define DES1_BS1_SHIFT 0 112 113 struct idmac_desc { 114 uint32_t des0; /* control */ 115 uint32_t des1; /* bufsize */ 116 uint32_t des2; /* buf1 phys addr */ 117 uint32_t des3; /* buf2 phys addr or next descr */ 118 }; 119 120 #define DESC_MAX 256 121 #define DESC_SIZE (sizeof(struct idmac_desc) * DESC_MAX) 122 #define DEF_MSIZE 0x2 /* Burst size of multiple transaction */ 123 124 static void dwmmc_next_operation(struct dwmmc_softc *); 125 static int dwmmc_setup_bus(struct dwmmc_softc *, int); 126 static int dma_done(struct dwmmc_softc *, struct mmc_command *); 127 static int dma_stop(struct dwmmc_softc *); 128 static void pio_read(struct dwmmc_softc *, struct mmc_command *); 129 static void pio_write(struct dwmmc_softc *, struct mmc_command *); 130 131 static struct resource_spec dwmmc_spec[] = { 132 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 133 { SYS_RES_IRQ, 0, RF_ACTIVE }, 134 { -1, 0 } 135 }; 136 137 #define HWTYPE_MASK (0x0000ffff) 138 #define HWFLAG_MASK (0xffff << 16) 139 140 static void 141 dwmmc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 142 { 143 144 if (error != 0) 145 return; 146 *(bus_addr_t *)arg = segs[0].ds_addr; 147 } 148 149 static void 150 dwmmc_ring_setup(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 151 { 152 struct dwmmc_softc *sc; 153 int idx; 154 155 if (error != 0) 156 return; 157 158 sc = arg; 159 160 dprintf("nsegs %d seg0len %lu\n", nsegs, segs[0].ds_len); 161 162 for (idx = 0; idx < nsegs; idx++) { 163 sc->desc_ring[idx].des0 = (DES0_OWN | DES0_DIC | DES0_CH); 164 sc->desc_ring[idx].des1 = segs[idx].ds_len; 165 sc->desc_ring[idx].des2 = segs[idx].ds_addr; 166 167 if (idx == 0) 168 sc->desc_ring[idx].des0 |= DES0_FS; 169 170 if (idx == (nsegs - 1)) { 171 sc->desc_ring[idx].des0 &= ~(DES0_DIC | DES0_CH); 172 sc->desc_ring[idx].des0 |= DES0_LD; 173 } 174 } 175 } 176 177 static int 178 dwmmc_ctrl_reset(struct dwmmc_softc *sc, int reset_bits) 179 { 180 int reg; 181 int i; 182 183 reg = READ4(sc, SDMMC_CTRL); 184 reg |= (reset_bits); 185 WRITE4(sc, SDMMC_CTRL, reg); 186 187 /* Wait reset done */ 188 for (i = 0; i < 100; i++) { 189 if (!(READ4(sc, SDMMC_CTRL) & reset_bits)) 190 return (0); 191 DELAY(10); 192 } 193 194 device_printf(sc->dev, "Reset failed\n"); 195 196 return (1); 197 } 198 199 static int 200 dma_setup(struct dwmmc_softc *sc) 201 { 202 int error; 203 int nidx; 204 int idx; 205 206 /* 207 * Set up TX descriptor ring, descriptors, and dma maps. 208 */ 209 error = bus_dma_tag_create( 210 bus_get_dma_tag(sc->dev), /* Parent tag. */ 211 4096, 0, /* alignment, boundary */ 212 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 213 BUS_SPACE_MAXADDR, /* highaddr */ 214 NULL, NULL, /* filter, filterarg */ 215 DESC_SIZE, 1, /* maxsize, nsegments */ 216 DESC_SIZE, /* maxsegsize */ 217 0, /* flags */ 218 NULL, NULL, /* lockfunc, lockarg */ 219 &sc->desc_tag); 220 if (error != 0) { 221 device_printf(sc->dev, 222 "could not create ring DMA tag.\n"); 223 return (1); 224 } 225 226 error = bus_dmamem_alloc(sc->desc_tag, (void**)&sc->desc_ring, 227 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 228 &sc->desc_map); 229 if (error != 0) { 230 device_printf(sc->dev, 231 "could not allocate descriptor ring.\n"); 232 return (1); 233 } 234 235 error = bus_dmamap_load(sc->desc_tag, sc->desc_map, 236 sc->desc_ring, DESC_SIZE, dwmmc_get1paddr, 237 &sc->desc_ring_paddr, 0); 238 if (error != 0) { 239 device_printf(sc->dev, 240 "could not load descriptor ring map.\n"); 241 return (1); 242 } 243 244 for (idx = 0; idx < sc->desc_count; idx++) { 245 sc->desc_ring[idx].des0 = DES0_CH; 246 sc->desc_ring[idx].des1 = 0; 247 nidx = (idx + 1) % sc->desc_count; 248 sc->desc_ring[idx].des3 = sc->desc_ring_paddr + \ 249 (nidx * sizeof(struct idmac_desc)); 250 } 251 252 error = bus_dma_tag_create( 253 bus_get_dma_tag(sc->dev), /* Parent tag. */ 254 4096, 0, /* alignment, boundary */ 255 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 256 BUS_SPACE_MAXADDR, /* highaddr */ 257 NULL, NULL, /* filter, filterarg */ 258 sc->desc_count * MMC_SECTOR_SIZE, /* maxsize */ 259 sc->desc_count, /* nsegments */ 260 MMC_SECTOR_SIZE, /* maxsegsize */ 261 0, /* flags */ 262 NULL, NULL, /* lockfunc, lockarg */ 263 &sc->buf_tag); 264 if (error != 0) { 265 device_printf(sc->dev, 266 "could not create ring DMA tag.\n"); 267 return (1); 268 } 269 270 error = bus_dmamap_create(sc->buf_tag, 0, 271 &sc->buf_map); 272 if (error != 0) { 273 device_printf(sc->dev, 274 "could not create TX buffer DMA map.\n"); 275 return (1); 276 } 277 278 return (0); 279 } 280 281 static void 282 dwmmc_cmd_done(struct dwmmc_softc *sc) 283 { 284 struct mmc_command *cmd; 285 286 cmd = sc->curcmd; 287 if (cmd == NULL) 288 return; 289 290 if (cmd->flags & MMC_RSP_PRESENT) { 291 if (cmd->flags & MMC_RSP_136) { 292 cmd->resp[3] = READ4(sc, SDMMC_RESP0); 293 cmd->resp[2] = READ4(sc, SDMMC_RESP1); 294 cmd->resp[1] = READ4(sc, SDMMC_RESP2); 295 cmd->resp[0] = READ4(sc, SDMMC_RESP3); 296 } else { 297 cmd->resp[3] = 0; 298 cmd->resp[2] = 0; 299 cmd->resp[1] = 0; 300 cmd->resp[0] = READ4(sc, SDMMC_RESP0); 301 } 302 } 303 } 304 305 static void 306 dwmmc_tasklet(struct dwmmc_softc *sc) 307 { 308 struct mmc_command *cmd; 309 310 cmd = sc->curcmd; 311 if (cmd == NULL) 312 return; 313 314 if (!sc->cmd_done) 315 return; 316 317 if (cmd->error != MMC_ERR_NONE || !cmd->data) { 318 dwmmc_next_operation(sc); 319 } else if (cmd->data && sc->dto_rcvd) { 320 if ((cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK || 321 cmd->opcode == MMC_READ_MULTIPLE_BLOCK) && 322 sc->use_auto_stop) { 323 if (sc->acd_rcvd) 324 dwmmc_next_operation(sc); 325 } else { 326 dwmmc_next_operation(sc); 327 } 328 } 329 } 330 331 static void 332 dwmmc_intr(void *arg) 333 { 334 struct mmc_command *cmd; 335 struct dwmmc_softc *sc; 336 uint32_t reg; 337 338 sc = arg; 339 340 DWMMC_LOCK(sc); 341 342 cmd = sc->curcmd; 343 344 /* First handle SDMMC controller interrupts */ 345 reg = READ4(sc, SDMMC_MINTSTS); 346 if (reg) { 347 dprintf("%s 0x%08x\n", __func__, reg); 348 349 if (reg & DWMMC_CMD_ERR_FLAGS) { 350 dprintf("cmd err 0x%08x cmd 0x%08x\n", 351 reg, cmd->opcode); 352 cmd->error = MMC_ERR_TIMEOUT; 353 } 354 355 if (reg & DWMMC_DATA_ERR_FLAGS) { 356 dprintf("data err 0x%08x cmd 0x%08x\n", 357 reg, cmd->opcode); 358 cmd->error = MMC_ERR_FAILED; 359 if (!sc->use_pio) { 360 dma_done(sc, cmd); 361 dma_stop(sc); 362 } 363 } 364 365 if (reg & SDMMC_INTMASK_CMD_DONE) { 366 dwmmc_cmd_done(sc); 367 sc->cmd_done = 1; 368 } 369 370 if (reg & SDMMC_INTMASK_ACD) 371 sc->acd_rcvd = 1; 372 373 if (reg & SDMMC_INTMASK_DTO) 374 sc->dto_rcvd = 1; 375 376 if (reg & SDMMC_INTMASK_CD) { 377 /* XXX: Handle card detect */ 378 } 379 } 380 381 /* Ack interrupts */ 382 WRITE4(sc, SDMMC_RINTSTS, reg); 383 384 if (sc->use_pio) { 385 if (reg & (SDMMC_INTMASK_RXDR|SDMMC_INTMASK_DTO)) { 386 pio_read(sc, cmd); 387 } 388 if (reg & (SDMMC_INTMASK_TXDR|SDMMC_INTMASK_DTO)) { 389 pio_write(sc, cmd); 390 } 391 } else { 392 /* Now handle DMA interrupts */ 393 reg = READ4(sc, SDMMC_IDSTS); 394 if (reg) { 395 dprintf("dma intr 0x%08x\n", reg); 396 if (reg & (SDMMC_IDINTEN_TI | SDMMC_IDINTEN_RI)) { 397 WRITE4(sc, SDMMC_IDSTS, (SDMMC_IDINTEN_TI | 398 SDMMC_IDINTEN_RI)); 399 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_NI); 400 dma_done(sc, cmd); 401 } 402 } 403 } 404 405 dwmmc_tasklet(sc); 406 407 DWMMC_UNLOCK(sc); 408 } 409 410 static int 411 parse_fdt(struct dwmmc_softc *sc) 412 { 413 pcell_t dts_value[3]; 414 phandle_t node; 415 uint32_t bus_hz = 0, bus_width; 416 int len; 417 #ifdef EXT_RESOURCES 418 int error; 419 #endif 420 421 if ((node = ofw_bus_get_node(sc->dev)) == -1) 422 return (ENXIO); 423 424 /* bus-width */ 425 if (OF_getencprop(node, "bus-width", &bus_width, sizeof(uint32_t)) <= 0) 426 bus_width = 4; 427 if (bus_width >= 4) 428 sc->host.caps |= MMC_CAP_4_BIT_DATA; 429 if (bus_width >= 8) 430 sc->host.caps |= MMC_CAP_8_BIT_DATA; 431 432 /* max-frequency */ 433 if (OF_getencprop(node, "max-frequency", &sc->max_hz, sizeof(uint32_t)) <= 0) 434 sc->max_hz = 200000000; 435 436 /* fifo-depth */ 437 if ((len = OF_getproplen(node, "fifo-depth")) > 0) { 438 OF_getencprop(node, "fifo-depth", dts_value, len); 439 sc->fifo_depth = dts_value[0]; 440 } 441 442 /* num-slots (Deprecated) */ 443 sc->num_slots = 1; 444 if ((len = OF_getproplen(node, "num-slots")) > 0) { 445 device_printf(sc->dev, "num-slots property is deprecated\n"); 446 OF_getencprop(node, "num-slots", dts_value, len); 447 sc->num_slots = dts_value[0]; 448 } 449 450 /* clock-frequency */ 451 if ((len = OF_getproplen(node, "clock-frequency")) > 0) { 452 OF_getencprop(node, "clock-frequency", dts_value, len); 453 bus_hz = dts_value[0]; 454 } 455 456 #ifdef EXT_RESOURCES 457 458 /* IP block reset is optional */ 459 error = hwreset_get_by_ofw_name(sc->dev, 0, "reset", &sc->hwreset); 460 if (error != 0 && 461 error != ENOENT && 462 error != ENODEV) { 463 device_printf(sc->dev, "Cannot get reset\n"); 464 goto fail; 465 } 466 467 /* vmmc regulator is optional */ 468 error = regulator_get_by_ofw_property(sc->dev, 0, "vmmc-supply", 469 &sc->vmmc); 470 if (error != 0 && 471 error != ENOENT && 472 error != ENODEV) { 473 device_printf(sc->dev, "Cannot get regulator 'vmmc-supply'\n"); 474 goto fail; 475 } 476 477 /* vqmmc regulator is optional */ 478 error = regulator_get_by_ofw_property(sc->dev, 0, "vqmmc-supply", 479 &sc->vqmmc); 480 if (error != 0 && 481 error != ENOENT && 482 error != ENODEV) { 483 device_printf(sc->dev, "Cannot get regulator 'vqmmc-supply'\n"); 484 goto fail; 485 } 486 487 /* Assert reset first */ 488 if (sc->hwreset != NULL) { 489 error = hwreset_assert(sc->hwreset); 490 if (error != 0) { 491 device_printf(sc->dev, "Cannot assert reset\n"); 492 goto fail; 493 } 494 } 495 496 /* BIU (Bus Interface Unit clock) is optional */ 497 error = clk_get_by_ofw_name(sc->dev, 0, "biu", &sc->biu); 498 if (error != 0 && 499 error != ENOENT && 500 error != ENODEV) { 501 device_printf(sc->dev, "Cannot get 'biu' clock\n"); 502 goto fail; 503 } 504 505 if (sc->biu) { 506 error = clk_enable(sc->biu); 507 if (error != 0) { 508 device_printf(sc->dev, "cannot enable biu clock\n"); 509 goto fail; 510 } 511 } 512 513 /* 514 * CIU (Controller Interface Unit clock) is mandatory 515 * if no clock-frequency property is given 516 */ 517 error = clk_get_by_ofw_name(sc->dev, 0, "ciu", &sc->ciu); 518 if (error != 0 && 519 error != ENOENT && 520 error != ENODEV) { 521 device_printf(sc->dev, "Cannot get 'ciu' clock\n"); 522 goto fail; 523 } 524 525 if (sc->ciu) { 526 if (bus_hz != 0) { 527 error = clk_set_freq(sc->ciu, bus_hz, 0); 528 if (error != 0) 529 device_printf(sc->dev, 530 "cannot set ciu clock to %u\n", bus_hz); 531 } 532 error = clk_enable(sc->ciu); 533 if (error != 0) { 534 device_printf(sc->dev, "cannot enable ciu clock\n"); 535 goto fail; 536 } 537 clk_get_freq(sc->ciu, &sc->bus_hz); 538 } 539 540 /* Take dwmmc out of reset */ 541 if (sc->hwreset != NULL) { 542 error = hwreset_deassert(sc->hwreset); 543 if (error != 0) { 544 device_printf(sc->dev, "Cannot deassert reset\n"); 545 goto fail; 546 } 547 } 548 #endif /* EXT_RESOURCES */ 549 550 if (sc->bus_hz == 0) { 551 device_printf(sc->dev, "No bus speed provided\n"); 552 goto fail; 553 } 554 555 return (0); 556 557 fail: 558 return (ENXIO); 559 } 560 561 int 562 dwmmc_attach(device_t dev) 563 { 564 struct dwmmc_softc *sc; 565 int error; 566 int slot; 567 568 sc = device_get_softc(dev); 569 570 sc->dev = dev; 571 572 /* Why not to use Auto Stop? It save a hundred of irq per second */ 573 sc->use_auto_stop = 1; 574 575 error = parse_fdt(sc); 576 if (error != 0) { 577 device_printf(dev, "Can't get FDT property.\n"); 578 return (ENXIO); 579 } 580 581 DWMMC_LOCK_INIT(sc); 582 583 if (bus_alloc_resources(dev, dwmmc_spec, sc->res)) { 584 device_printf(dev, "could not allocate resources\n"); 585 return (ENXIO); 586 } 587 588 /* Setup interrupt handler. */ 589 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE, 590 NULL, dwmmc_intr, sc, &sc->intr_cookie); 591 if (error != 0) { 592 device_printf(dev, "could not setup interrupt handler.\n"); 593 return (ENXIO); 594 } 595 596 device_printf(dev, "Hardware version ID is %04x\n", 597 READ4(sc, SDMMC_VERID) & 0xffff); 598 599 if (sc->desc_count == 0) 600 sc->desc_count = DESC_MAX; 601 602 /* XXX: we support operation for slot index 0 only */ 603 slot = 0; 604 if (sc->pwren_inverted) { 605 WRITE4(sc, SDMMC_PWREN, (0 << slot)); 606 } else { 607 WRITE4(sc, SDMMC_PWREN, (1 << slot)); 608 } 609 610 /* Reset all */ 611 if (dwmmc_ctrl_reset(sc, (SDMMC_CTRL_RESET | 612 SDMMC_CTRL_FIFO_RESET | 613 SDMMC_CTRL_DMA_RESET))) 614 return (ENXIO); 615 616 dwmmc_setup_bus(sc, sc->host.f_min); 617 618 if (sc->fifo_depth == 0) { 619 sc->fifo_depth = 1 + 620 ((READ4(sc, SDMMC_FIFOTH) >> SDMMC_FIFOTH_RXWMARK_S) & 0xfff); 621 device_printf(dev, "No fifo-depth, using FIFOTH %x\n", 622 sc->fifo_depth); 623 } 624 625 if (!sc->use_pio) { 626 dma_stop(sc); 627 if (dma_setup(sc)) 628 return (ENXIO); 629 630 /* Install desc base */ 631 WRITE4(sc, SDMMC_DBADDR, sc->desc_ring_paddr); 632 633 /* Enable DMA interrupts */ 634 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_MASK); 635 WRITE4(sc, SDMMC_IDINTEN, (SDMMC_IDINTEN_NI | 636 SDMMC_IDINTEN_RI | 637 SDMMC_IDINTEN_TI)); 638 } 639 640 /* Clear and disable interrups for a while */ 641 WRITE4(sc, SDMMC_RINTSTS, 0xffffffff); 642 WRITE4(sc, SDMMC_INTMASK, 0); 643 644 /* Maximum timeout */ 645 WRITE4(sc, SDMMC_TMOUT, 0xffffffff); 646 647 /* Enable interrupts */ 648 WRITE4(sc, SDMMC_RINTSTS, 0xffffffff); 649 WRITE4(sc, SDMMC_INTMASK, (SDMMC_INTMASK_CMD_DONE | 650 SDMMC_INTMASK_DTO | 651 SDMMC_INTMASK_ACD | 652 SDMMC_INTMASK_TXDR | 653 SDMMC_INTMASK_RXDR | 654 DWMMC_ERR_FLAGS | 655 SDMMC_INTMASK_CD)); 656 WRITE4(sc, SDMMC_CTRL, SDMMC_CTRL_INT_ENABLE); 657 658 sc->host.f_min = 400000; 659 sc->host.f_max = sc->max_hz; 660 sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340; 661 sc->host.caps |= MMC_CAP_HSPEED; 662 sc->host.caps |= MMC_CAP_SIGNALING_330; 663 664 device_add_child(dev, "mmc", -1); 665 return (bus_generic_attach(dev)); 666 } 667 668 static int 669 dwmmc_setup_bus(struct dwmmc_softc *sc, int freq) 670 { 671 int tout; 672 int div; 673 674 if (freq == 0) { 675 WRITE4(sc, SDMMC_CLKENA, 0); 676 WRITE4(sc, SDMMC_CMD, (SDMMC_CMD_WAIT_PRVDATA | 677 SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START)); 678 679 tout = 1000; 680 do { 681 if (tout-- < 0) { 682 device_printf(sc->dev, "Failed update clk\n"); 683 return (1); 684 } 685 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START); 686 687 return (0); 688 } 689 690 WRITE4(sc, SDMMC_CLKENA, 0); 691 WRITE4(sc, SDMMC_CLKSRC, 0); 692 693 div = (sc->bus_hz != freq) ? DIV_ROUND_UP(sc->bus_hz, 2 * freq) : 0; 694 695 WRITE4(sc, SDMMC_CLKDIV, div); 696 WRITE4(sc, SDMMC_CMD, (SDMMC_CMD_WAIT_PRVDATA | 697 SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START)); 698 699 tout = 1000; 700 do { 701 if (tout-- < 0) { 702 device_printf(sc->dev, "Failed to update clk"); 703 return (1); 704 } 705 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START); 706 707 WRITE4(sc, SDMMC_CLKENA, (SDMMC_CLKENA_CCLK_EN | SDMMC_CLKENA_LP)); 708 WRITE4(sc, SDMMC_CMD, SDMMC_CMD_WAIT_PRVDATA | 709 SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START); 710 711 tout = 1000; 712 do { 713 if (tout-- < 0) { 714 device_printf(sc->dev, "Failed to enable clk\n"); 715 return (1); 716 } 717 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START); 718 719 return (0); 720 } 721 722 static int 723 dwmmc_update_ios(device_t brdev, device_t reqdev) 724 { 725 struct dwmmc_softc *sc; 726 struct mmc_ios *ios; 727 uint32_t reg; 728 int ret = 0; 729 730 sc = device_get_softc(brdev); 731 ios = &sc->host.ios; 732 733 dprintf("Setting up clk %u bus_width %d\n", 734 ios->clock, ios->bus_width); 735 736 if (ios->bus_width == bus_width_8) 737 WRITE4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT); 738 else if (ios->bus_width == bus_width_4) 739 WRITE4(sc, SDMMC_CTYPE, SDMMC_CTYPE_4BIT); 740 else 741 WRITE4(sc, SDMMC_CTYPE, 0); 742 743 if ((sc->hwtype & HWTYPE_MASK) == HWTYPE_EXYNOS) { 744 /* XXX: take care about DDR or SDR use here */ 745 WRITE4(sc, SDMMC_CLKSEL, sc->sdr_timing); 746 } 747 748 /* Set DDR mode */ 749 reg = READ4(sc, SDMMC_UHS_REG); 750 if (ios->timing == bus_timing_uhs_ddr50 || 751 ios->timing == bus_timing_mmc_ddr52 || 752 ios->timing == bus_timing_mmc_hs400) 753 reg |= (SDMMC_UHS_REG_DDR); 754 else 755 reg &= ~(SDMMC_UHS_REG_DDR); 756 WRITE4(sc, SDMMC_UHS_REG, reg); 757 758 if (sc->update_ios) 759 ret = sc->update_ios(sc, ios); 760 761 dwmmc_setup_bus(sc, ios->clock); 762 763 return (ret); 764 } 765 766 static int 767 dma_done(struct dwmmc_softc *sc, struct mmc_command *cmd) 768 { 769 struct mmc_data *data; 770 771 data = cmd->data; 772 773 if (data->flags & MMC_DATA_WRITE) 774 bus_dmamap_sync(sc->buf_tag, sc->buf_map, 775 BUS_DMASYNC_POSTWRITE); 776 else 777 bus_dmamap_sync(sc->buf_tag, sc->buf_map, 778 BUS_DMASYNC_POSTREAD); 779 780 bus_dmamap_sync(sc->desc_tag, sc->desc_map, 781 BUS_DMASYNC_POSTWRITE); 782 783 bus_dmamap_unload(sc->buf_tag, sc->buf_map); 784 785 return (0); 786 } 787 788 static int 789 dma_stop(struct dwmmc_softc *sc) 790 { 791 int reg; 792 793 reg = READ4(sc, SDMMC_CTRL); 794 reg &= ~(SDMMC_CTRL_USE_IDMAC); 795 reg |= (SDMMC_CTRL_DMA_RESET); 796 WRITE4(sc, SDMMC_CTRL, reg); 797 798 reg = READ4(sc, SDMMC_BMOD); 799 reg &= ~(SDMMC_BMOD_DE | SDMMC_BMOD_FB); 800 reg |= (SDMMC_BMOD_SWR); 801 WRITE4(sc, SDMMC_BMOD, reg); 802 803 return (0); 804 } 805 806 static int 807 dma_prepare(struct dwmmc_softc *sc, struct mmc_command *cmd) 808 { 809 struct mmc_data *data; 810 int err; 811 int reg; 812 813 data = cmd->data; 814 815 reg = READ4(sc, SDMMC_INTMASK); 816 reg &= ~(SDMMC_INTMASK_TXDR | SDMMC_INTMASK_RXDR); 817 WRITE4(sc, SDMMC_INTMASK, reg); 818 819 err = bus_dmamap_load(sc->buf_tag, sc->buf_map, 820 data->data, data->len, dwmmc_ring_setup, 821 sc, BUS_DMA_NOWAIT); 822 if (err != 0) 823 panic("dmamap_load failed\n"); 824 825 /* Ensure the device can see the desc */ 826 bus_dmamap_sync(sc->desc_tag, sc->desc_map, 827 BUS_DMASYNC_PREWRITE); 828 829 if (data->flags & MMC_DATA_WRITE) 830 bus_dmamap_sync(sc->buf_tag, sc->buf_map, 831 BUS_DMASYNC_PREWRITE); 832 else 833 bus_dmamap_sync(sc->buf_tag, sc->buf_map, 834 BUS_DMASYNC_PREREAD); 835 836 reg = (DEF_MSIZE << SDMMC_FIFOTH_MSIZE_S); 837 reg |= ((sc->fifo_depth / 2) - 1) << SDMMC_FIFOTH_RXWMARK_S; 838 reg |= (sc->fifo_depth / 2) << SDMMC_FIFOTH_TXWMARK_S; 839 840 WRITE4(sc, SDMMC_FIFOTH, reg); 841 wmb(); 842 843 reg = READ4(sc, SDMMC_CTRL); 844 reg |= (SDMMC_CTRL_USE_IDMAC | SDMMC_CTRL_DMA_ENABLE); 845 WRITE4(sc, SDMMC_CTRL, reg); 846 wmb(); 847 848 reg = READ4(sc, SDMMC_BMOD); 849 reg |= (SDMMC_BMOD_DE | SDMMC_BMOD_FB); 850 WRITE4(sc, SDMMC_BMOD, reg); 851 852 /* Start */ 853 WRITE4(sc, SDMMC_PLDMND, 1); 854 855 return (0); 856 } 857 858 static int 859 pio_prepare(struct dwmmc_softc *sc, struct mmc_command *cmd) 860 { 861 struct mmc_data *data; 862 int reg; 863 864 data = cmd->data; 865 data->xfer_len = 0; 866 867 reg = (DEF_MSIZE << SDMMC_FIFOTH_MSIZE_S); 868 reg |= ((sc->fifo_depth / 2) - 1) << SDMMC_FIFOTH_RXWMARK_S; 869 reg |= (sc->fifo_depth / 2) << SDMMC_FIFOTH_TXWMARK_S; 870 871 WRITE4(sc, SDMMC_FIFOTH, reg); 872 wmb(); 873 874 return (0); 875 } 876 877 static void 878 pio_read(struct dwmmc_softc *sc, struct mmc_command *cmd) 879 { 880 struct mmc_data *data; 881 uint32_t *p, status; 882 883 if (cmd == NULL || cmd->data == NULL) 884 return; 885 886 data = cmd->data; 887 if ((data->flags & MMC_DATA_READ) == 0) 888 return; 889 890 KASSERT((data->xfer_len & 3) == 0, ("xfer_len not aligned")); 891 p = (uint32_t *)data->data + (data->xfer_len >> 2); 892 893 while (data->xfer_len < data->len) { 894 status = READ4(sc, SDMMC_STATUS); 895 if (status & SDMMC_STATUS_FIFO_EMPTY) 896 break; 897 *p++ = READ4(sc, SDMMC_DATA); 898 data->xfer_len += 4; 899 } 900 901 WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_RXDR); 902 } 903 904 static void 905 pio_write(struct dwmmc_softc *sc, struct mmc_command *cmd) 906 { 907 struct mmc_data *data; 908 uint32_t *p, status; 909 910 if (cmd == NULL || cmd->data == NULL) 911 return; 912 913 data = cmd->data; 914 if ((data->flags & MMC_DATA_WRITE) == 0) 915 return; 916 917 KASSERT((data->xfer_len & 3) == 0, ("xfer_len not aligned")); 918 p = (uint32_t *)data->data + (data->xfer_len >> 2); 919 920 while (data->xfer_len < data->len) { 921 status = READ4(sc, SDMMC_STATUS); 922 if (status & SDMMC_STATUS_FIFO_FULL) 923 break; 924 WRITE4(sc, SDMMC_DATA, *p++); 925 data->xfer_len += 4; 926 } 927 928 WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_TXDR); 929 } 930 931 static void 932 dwmmc_start_cmd(struct dwmmc_softc *sc, struct mmc_command *cmd) 933 { 934 struct mmc_data *data; 935 uint32_t blksz; 936 uint32_t cmdr; 937 938 sc->curcmd = cmd; 939 data = cmd->data; 940 941 if ((sc->hwtype & HWTYPE_MASK) == HWTYPE_ROCKCHIP) 942 dwmmc_setup_bus(sc, sc->host.ios.clock); 943 944 /* XXX Upper layers don't always set this */ 945 cmd->mrq = sc->req; 946 947 /* Begin setting up command register. */ 948 949 cmdr = cmd->opcode; 950 951 dprintf("cmd->opcode 0x%08x\n", cmd->opcode); 952 953 if (cmd->opcode == MMC_STOP_TRANSMISSION || 954 cmd->opcode == MMC_GO_IDLE_STATE || 955 cmd->opcode == MMC_GO_INACTIVE_STATE) 956 cmdr |= SDMMC_CMD_STOP_ABORT; 957 else if (cmd->opcode != MMC_SEND_STATUS && data) 958 cmdr |= SDMMC_CMD_WAIT_PRVDATA; 959 960 /* Set up response handling. */ 961 if (MMC_RSP(cmd->flags) != MMC_RSP_NONE) { 962 cmdr |= SDMMC_CMD_RESP_EXP; 963 if (cmd->flags & MMC_RSP_136) 964 cmdr |= SDMMC_CMD_RESP_LONG; 965 } 966 967 if (cmd->flags & MMC_RSP_CRC) 968 cmdr |= SDMMC_CMD_RESP_CRC; 969 970 /* 971 * XXX: Not all platforms want this. 972 */ 973 cmdr |= SDMMC_CMD_USE_HOLD_REG; 974 975 if ((sc->flags & CARD_INIT_DONE) == 0) { 976 sc->flags |= (CARD_INIT_DONE); 977 cmdr |= SDMMC_CMD_SEND_INIT; 978 } 979 980 if (data) { 981 if ((cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK || 982 cmd->opcode == MMC_READ_MULTIPLE_BLOCK) && 983 sc->use_auto_stop) 984 cmdr |= SDMMC_CMD_SEND_ASTOP; 985 986 cmdr |= SDMMC_CMD_DATA_EXP; 987 if (data->flags & MMC_DATA_STREAM) 988 cmdr |= SDMMC_CMD_MODE_STREAM; 989 if (data->flags & MMC_DATA_WRITE) 990 cmdr |= SDMMC_CMD_DATA_WRITE; 991 992 WRITE4(sc, SDMMC_TMOUT, 0xffffffff); 993 WRITE4(sc, SDMMC_BYTCNT, data->len); 994 blksz = (data->len < MMC_SECTOR_SIZE) ? \ 995 data->len : MMC_SECTOR_SIZE; 996 WRITE4(sc, SDMMC_BLKSIZ, blksz); 997 998 if (sc->use_pio) { 999 pio_prepare(sc, cmd); 1000 } else { 1001 dma_prepare(sc, cmd); 1002 } 1003 wmb(); 1004 } 1005 1006 dprintf("cmdr 0x%08x\n", cmdr); 1007 1008 WRITE4(sc, SDMMC_CMDARG, cmd->arg); 1009 wmb(); 1010 WRITE4(sc, SDMMC_CMD, cmdr | SDMMC_CMD_START); 1011 }; 1012 1013 static void 1014 dwmmc_next_operation(struct dwmmc_softc *sc) 1015 { 1016 struct mmc_request *req; 1017 1018 req = sc->req; 1019 if (req == NULL) 1020 return; 1021 1022 sc->acd_rcvd = 0; 1023 sc->dto_rcvd = 0; 1024 sc->cmd_done = 0; 1025 1026 /* 1027 * XXX: Wait until card is still busy. 1028 * We do need this to prevent data timeouts, 1029 * mostly caused by multi-block write command 1030 * followed by single-read. 1031 */ 1032 while(READ4(sc, SDMMC_STATUS) & (SDMMC_STATUS_DATA_BUSY)) 1033 continue; 1034 1035 if (sc->flags & PENDING_CMD) { 1036 sc->flags &= ~PENDING_CMD; 1037 dwmmc_start_cmd(sc, req->cmd); 1038 return; 1039 } else if (sc->flags & PENDING_STOP && !sc->use_auto_stop) { 1040 sc->flags &= ~PENDING_STOP; 1041 dwmmc_start_cmd(sc, req->stop); 1042 return; 1043 } 1044 1045 sc->req = NULL; 1046 sc->curcmd = NULL; 1047 req->done(req); 1048 } 1049 1050 static int 1051 dwmmc_request(device_t brdev, device_t reqdev, struct mmc_request *req) 1052 { 1053 struct dwmmc_softc *sc; 1054 1055 sc = device_get_softc(brdev); 1056 1057 dprintf("%s\n", __func__); 1058 1059 DWMMC_LOCK(sc); 1060 1061 if (sc->req != NULL) { 1062 DWMMC_UNLOCK(sc); 1063 return (EBUSY); 1064 } 1065 1066 sc->req = req; 1067 sc->flags |= PENDING_CMD; 1068 if (sc->req->stop) 1069 sc->flags |= PENDING_STOP; 1070 dwmmc_next_operation(sc); 1071 1072 DWMMC_UNLOCK(sc); 1073 return (0); 1074 } 1075 1076 static int 1077 dwmmc_get_ro(device_t brdev, device_t reqdev) 1078 { 1079 1080 dprintf("%s\n", __func__); 1081 1082 return (0); 1083 } 1084 1085 static int 1086 dwmmc_acquire_host(device_t brdev, device_t reqdev) 1087 { 1088 struct dwmmc_softc *sc; 1089 1090 sc = device_get_softc(brdev); 1091 1092 DWMMC_LOCK(sc); 1093 while (sc->bus_busy) 1094 msleep(sc, &sc->sc_mtx, PZERO, "dwmmcah", hz / 5); 1095 sc->bus_busy++; 1096 DWMMC_UNLOCK(sc); 1097 return (0); 1098 } 1099 1100 static int 1101 dwmmc_release_host(device_t brdev, device_t reqdev) 1102 { 1103 struct dwmmc_softc *sc; 1104 1105 sc = device_get_softc(brdev); 1106 1107 DWMMC_LOCK(sc); 1108 sc->bus_busy--; 1109 wakeup(sc); 1110 DWMMC_UNLOCK(sc); 1111 return (0); 1112 } 1113 1114 static int 1115 dwmmc_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 1116 { 1117 struct dwmmc_softc *sc; 1118 1119 sc = device_get_softc(bus); 1120 1121 switch (which) { 1122 default: 1123 return (EINVAL); 1124 case MMCBR_IVAR_BUS_MODE: 1125 *(int *)result = sc->host.ios.bus_mode; 1126 break; 1127 case MMCBR_IVAR_BUS_WIDTH: 1128 *(int *)result = sc->host.ios.bus_width; 1129 break; 1130 case MMCBR_IVAR_CHIP_SELECT: 1131 *(int *)result = sc->host.ios.chip_select; 1132 break; 1133 case MMCBR_IVAR_CLOCK: 1134 *(int *)result = sc->host.ios.clock; 1135 break; 1136 case MMCBR_IVAR_F_MIN: 1137 *(int *)result = sc->host.f_min; 1138 break; 1139 case MMCBR_IVAR_F_MAX: 1140 *(int *)result = sc->host.f_max; 1141 break; 1142 case MMCBR_IVAR_HOST_OCR: 1143 *(int *)result = sc->host.host_ocr; 1144 break; 1145 case MMCBR_IVAR_MODE: 1146 *(int *)result = sc->host.mode; 1147 break; 1148 case MMCBR_IVAR_OCR: 1149 *(int *)result = sc->host.ocr; 1150 break; 1151 case MMCBR_IVAR_POWER_MODE: 1152 *(int *)result = sc->host.ios.power_mode; 1153 break; 1154 case MMCBR_IVAR_VDD: 1155 *(int *)result = sc->host.ios.vdd; 1156 break; 1157 case MMCBR_IVAR_VCCQ: 1158 *(int *)result = sc->host.ios.vccq; 1159 break; 1160 case MMCBR_IVAR_CAPS: 1161 *(int *)result = sc->host.caps; 1162 break; 1163 case MMCBR_IVAR_MAX_DATA: 1164 *(int *)result = sc->desc_count; 1165 break; 1166 case MMCBR_IVAR_TIMING: 1167 *(int *)result = sc->host.ios.timing; 1168 break; 1169 } 1170 return (0); 1171 } 1172 1173 static int 1174 dwmmc_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1175 { 1176 struct dwmmc_softc *sc; 1177 1178 sc = device_get_softc(bus); 1179 1180 switch (which) { 1181 default: 1182 return (EINVAL); 1183 case MMCBR_IVAR_BUS_MODE: 1184 sc->host.ios.bus_mode = value; 1185 break; 1186 case MMCBR_IVAR_BUS_WIDTH: 1187 sc->host.ios.bus_width = value; 1188 break; 1189 case MMCBR_IVAR_CHIP_SELECT: 1190 sc->host.ios.chip_select = value; 1191 break; 1192 case MMCBR_IVAR_CLOCK: 1193 sc->host.ios.clock = value; 1194 break; 1195 case MMCBR_IVAR_MODE: 1196 sc->host.mode = value; 1197 break; 1198 case MMCBR_IVAR_OCR: 1199 sc->host.ocr = value; 1200 break; 1201 case MMCBR_IVAR_POWER_MODE: 1202 sc->host.ios.power_mode = value; 1203 break; 1204 case MMCBR_IVAR_VDD: 1205 sc->host.ios.vdd = value; 1206 break; 1207 case MMCBR_IVAR_TIMING: 1208 sc->host.ios.timing = value; 1209 break; 1210 case MMCBR_IVAR_VCCQ: 1211 sc->host.ios.vccq = value; 1212 break; 1213 /* These are read-only */ 1214 case MMCBR_IVAR_CAPS: 1215 case MMCBR_IVAR_HOST_OCR: 1216 case MMCBR_IVAR_F_MIN: 1217 case MMCBR_IVAR_F_MAX: 1218 case MMCBR_IVAR_MAX_DATA: 1219 return (EINVAL); 1220 } 1221 return (0); 1222 } 1223 1224 static device_method_t dwmmc_methods[] = { 1225 /* Bus interface */ 1226 DEVMETHOD(bus_read_ivar, dwmmc_read_ivar), 1227 DEVMETHOD(bus_write_ivar, dwmmc_write_ivar), 1228 1229 /* mmcbr_if */ 1230 DEVMETHOD(mmcbr_update_ios, dwmmc_update_ios), 1231 DEVMETHOD(mmcbr_request, dwmmc_request), 1232 DEVMETHOD(mmcbr_get_ro, dwmmc_get_ro), 1233 DEVMETHOD(mmcbr_acquire_host, dwmmc_acquire_host), 1234 DEVMETHOD(mmcbr_release_host, dwmmc_release_host), 1235 1236 DEVMETHOD_END 1237 }; 1238 1239 DEFINE_CLASS_0(dwmmc, dwmmc_driver, dwmmc_methods, 1240 sizeof(struct dwmmc_softc)); 1241