1 /*- 2 * Copyright (c) 2014-2019 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Synopsys DesignWare Mobile Storage Host Controller 33 * Chapter 14, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22) 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/bus.h> 42 #include <sys/kernel.h> 43 #include <sys/lock.h> 44 #include <sys/module.h> 45 #include <sys/malloc.h> 46 #include <sys/mutex.h> 47 #include <sys/rman.h> 48 #include <sys/queue.h> 49 #include <sys/taskqueue.h> 50 51 #include <dev/mmc/bridge.h> 52 #include <dev/mmc/mmcbrvar.h> 53 54 #include <dev/fdt/fdt_common.h> 55 #include <dev/ofw/openfirm.h> 56 #include <dev/ofw/ofw_bus.h> 57 #include <dev/ofw/ofw_bus_subr.h> 58 59 #include <machine/bus.h> 60 #include <machine/cpu.h> 61 #include <machine/intr.h> 62 63 #ifdef EXT_RESOURCES 64 #include <dev/extres/clk/clk.h> 65 #endif 66 67 #include <dev/mmc/host/dwmmc_reg.h> 68 #include <dev/mmc/host/dwmmc_var.h> 69 70 #include "opt_mmccam.h" 71 72 #include "mmcbr_if.h" 73 74 #define dprintf(x, arg...) 75 76 #define READ4(_sc, _reg) \ 77 bus_read_4((_sc)->res[0], _reg) 78 #define WRITE4(_sc, _reg, _val) \ 79 bus_write_4((_sc)->res[0], _reg, _val) 80 81 #define DIV_ROUND_UP(n, d) howmany(n, d) 82 83 #define DWMMC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 84 #define DWMMC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 85 #define DWMMC_LOCK_INIT(_sc) \ 86 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 87 "dwmmc", MTX_DEF) 88 #define DWMMC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 89 #define DWMMC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 90 #define DWMMC_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 91 92 #define PENDING_CMD 0x01 93 #define PENDING_STOP 0x02 94 #define CARD_INIT_DONE 0x04 95 96 #define DWMMC_DATA_ERR_FLAGS (SDMMC_INTMASK_DRT | SDMMC_INTMASK_DCRC \ 97 |SDMMC_INTMASK_HTO | SDMMC_INTMASK_SBE \ 98 |SDMMC_INTMASK_EBE) 99 #define DWMMC_CMD_ERR_FLAGS (SDMMC_INTMASK_RTO | SDMMC_INTMASK_RCRC \ 100 |SDMMC_INTMASK_RE) 101 #define DWMMC_ERR_FLAGS (DWMMC_DATA_ERR_FLAGS | DWMMC_CMD_ERR_FLAGS \ 102 |SDMMC_INTMASK_HLE) 103 104 #define DES0_DIC (1 << 1) 105 #define DES0_LD (1 << 2) 106 #define DES0_FS (1 << 3) 107 #define DES0_CH (1 << 4) 108 #define DES0_ER (1 << 5) 109 #define DES0_CES (1 << 30) 110 #define DES0_OWN (1 << 31) 111 112 #define DES1_BS1_MASK 0xfff 113 #define DES1_BS1_SHIFT 0 114 115 struct idmac_desc { 116 uint32_t des0; /* control */ 117 uint32_t des1; /* bufsize */ 118 uint32_t des2; /* buf1 phys addr */ 119 uint32_t des3; /* buf2 phys addr or next descr */ 120 }; 121 122 #define DESC_MAX 256 123 #define DESC_SIZE (sizeof(struct idmac_desc) * DESC_MAX) 124 #define DEF_MSIZE 0x2 /* Burst size of multiple transaction */ 125 126 static void dwmmc_next_operation(struct dwmmc_softc *); 127 static int dwmmc_setup_bus(struct dwmmc_softc *, int); 128 static int dma_done(struct dwmmc_softc *, struct mmc_command *); 129 static int dma_stop(struct dwmmc_softc *); 130 static void pio_read(struct dwmmc_softc *, struct mmc_command *); 131 static void pio_write(struct dwmmc_softc *, struct mmc_command *); 132 static void dwmmc_handle_card_present(struct dwmmc_softc *sc, bool is_present); 133 134 static struct resource_spec dwmmc_spec[] = { 135 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 136 { SYS_RES_IRQ, 0, RF_ACTIVE }, 137 { -1, 0 } 138 }; 139 140 #define HWTYPE_MASK (0x0000ffff) 141 #define HWFLAG_MASK (0xffff << 16) 142 143 static void 144 dwmmc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 145 { 146 147 if (error != 0) 148 return; 149 *(bus_addr_t *)arg = segs[0].ds_addr; 150 } 151 152 static void 153 dwmmc_ring_setup(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 154 { 155 struct dwmmc_softc *sc; 156 int idx; 157 158 if (error != 0) 159 return; 160 161 sc = arg; 162 163 dprintf("nsegs %d seg0len %lu\n", nsegs, segs[0].ds_len); 164 165 for (idx = 0; idx < nsegs; idx++) { 166 sc->desc_ring[idx].des0 = (DES0_OWN | DES0_DIC | DES0_CH); 167 sc->desc_ring[idx].des1 = segs[idx].ds_len; 168 sc->desc_ring[idx].des2 = segs[idx].ds_addr; 169 170 if (idx == 0) 171 sc->desc_ring[idx].des0 |= DES0_FS; 172 173 if (idx == (nsegs - 1)) { 174 sc->desc_ring[idx].des0 &= ~(DES0_DIC | DES0_CH); 175 sc->desc_ring[idx].des0 |= DES0_LD; 176 } 177 } 178 } 179 180 static int 181 dwmmc_ctrl_reset(struct dwmmc_softc *sc, int reset_bits) 182 { 183 int reg; 184 int i; 185 186 reg = READ4(sc, SDMMC_CTRL); 187 reg |= (reset_bits); 188 WRITE4(sc, SDMMC_CTRL, reg); 189 190 /* Wait reset done */ 191 for (i = 0; i < 100; i++) { 192 if (!(READ4(sc, SDMMC_CTRL) & reset_bits)) 193 return (0); 194 DELAY(10); 195 } 196 197 device_printf(sc->dev, "Reset failed\n"); 198 199 return (1); 200 } 201 202 static int 203 dma_setup(struct dwmmc_softc *sc) 204 { 205 int error; 206 int nidx; 207 int idx; 208 209 /* 210 * Set up TX descriptor ring, descriptors, and dma maps. 211 */ 212 error = bus_dma_tag_create( 213 bus_get_dma_tag(sc->dev), /* Parent tag. */ 214 4096, 0, /* alignment, boundary */ 215 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 216 BUS_SPACE_MAXADDR, /* highaddr */ 217 NULL, NULL, /* filter, filterarg */ 218 DESC_SIZE, 1, /* maxsize, nsegments */ 219 DESC_SIZE, /* maxsegsize */ 220 0, /* flags */ 221 NULL, NULL, /* lockfunc, lockarg */ 222 &sc->desc_tag); 223 if (error != 0) { 224 device_printf(sc->dev, 225 "could not create ring DMA tag.\n"); 226 return (1); 227 } 228 229 error = bus_dmamem_alloc(sc->desc_tag, (void**)&sc->desc_ring, 230 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 231 &sc->desc_map); 232 if (error != 0) { 233 device_printf(sc->dev, 234 "could not allocate descriptor ring.\n"); 235 return (1); 236 } 237 238 error = bus_dmamap_load(sc->desc_tag, sc->desc_map, 239 sc->desc_ring, DESC_SIZE, dwmmc_get1paddr, 240 &sc->desc_ring_paddr, 0); 241 if (error != 0) { 242 device_printf(sc->dev, 243 "could not load descriptor ring map.\n"); 244 return (1); 245 } 246 247 for (idx = 0; idx < sc->desc_count; idx++) { 248 sc->desc_ring[idx].des0 = DES0_CH; 249 sc->desc_ring[idx].des1 = 0; 250 nidx = (idx + 1) % sc->desc_count; 251 sc->desc_ring[idx].des3 = sc->desc_ring_paddr + \ 252 (nidx * sizeof(struct idmac_desc)); 253 } 254 255 error = bus_dma_tag_create( 256 bus_get_dma_tag(sc->dev), /* Parent tag. */ 257 4096, 0, /* alignment, boundary */ 258 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 259 BUS_SPACE_MAXADDR, /* highaddr */ 260 NULL, NULL, /* filter, filterarg */ 261 sc->desc_count * MMC_SECTOR_SIZE, /* maxsize */ 262 sc->desc_count, /* nsegments */ 263 MMC_SECTOR_SIZE, /* maxsegsize */ 264 0, /* flags */ 265 NULL, NULL, /* lockfunc, lockarg */ 266 &sc->buf_tag); 267 if (error != 0) { 268 device_printf(sc->dev, 269 "could not create ring DMA tag.\n"); 270 return (1); 271 } 272 273 error = bus_dmamap_create(sc->buf_tag, 0, 274 &sc->buf_map); 275 if (error != 0) { 276 device_printf(sc->dev, 277 "could not create TX buffer DMA map.\n"); 278 return (1); 279 } 280 281 return (0); 282 } 283 284 static void 285 dwmmc_cmd_done(struct dwmmc_softc *sc) 286 { 287 struct mmc_command *cmd; 288 289 cmd = sc->curcmd; 290 if (cmd == NULL) 291 return; 292 293 if (cmd->flags & MMC_RSP_PRESENT) { 294 if (cmd->flags & MMC_RSP_136) { 295 cmd->resp[3] = READ4(sc, SDMMC_RESP0); 296 cmd->resp[2] = READ4(sc, SDMMC_RESP1); 297 cmd->resp[1] = READ4(sc, SDMMC_RESP2); 298 cmd->resp[0] = READ4(sc, SDMMC_RESP3); 299 } else { 300 cmd->resp[3] = 0; 301 cmd->resp[2] = 0; 302 cmd->resp[1] = 0; 303 cmd->resp[0] = READ4(sc, SDMMC_RESP0); 304 } 305 } 306 } 307 308 static void 309 dwmmc_tasklet(struct dwmmc_softc *sc) 310 { 311 struct mmc_command *cmd; 312 313 cmd = sc->curcmd; 314 if (cmd == NULL) 315 return; 316 317 if (!sc->cmd_done) 318 return; 319 320 if (cmd->error != MMC_ERR_NONE || !cmd->data) { 321 dwmmc_next_operation(sc); 322 } else if (cmd->data && sc->dto_rcvd) { 323 if ((cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK || 324 cmd->opcode == MMC_READ_MULTIPLE_BLOCK) && 325 sc->use_auto_stop) { 326 if (sc->acd_rcvd) 327 dwmmc_next_operation(sc); 328 } else { 329 dwmmc_next_operation(sc); 330 } 331 } 332 } 333 334 static void 335 dwmmc_intr(void *arg) 336 { 337 struct mmc_command *cmd; 338 struct dwmmc_softc *sc; 339 uint32_t reg; 340 341 sc = arg; 342 343 DWMMC_LOCK(sc); 344 345 cmd = sc->curcmd; 346 347 /* First handle SDMMC controller interrupts */ 348 reg = READ4(sc, SDMMC_MINTSTS); 349 if (reg) { 350 dprintf("%s 0x%08x\n", __func__, reg); 351 352 if (reg & DWMMC_CMD_ERR_FLAGS) { 353 dprintf("cmd err 0x%08x cmd 0x%08x\n", 354 reg, cmd->opcode); 355 cmd->error = MMC_ERR_TIMEOUT; 356 } 357 358 if (reg & DWMMC_DATA_ERR_FLAGS) { 359 dprintf("data err 0x%08x cmd 0x%08x\n", 360 reg, cmd->opcode); 361 cmd->error = MMC_ERR_FAILED; 362 if (!sc->use_pio) { 363 dma_done(sc, cmd); 364 dma_stop(sc); 365 } 366 } 367 368 if (reg & SDMMC_INTMASK_CMD_DONE) { 369 dwmmc_cmd_done(sc); 370 sc->cmd_done = 1; 371 } 372 373 if (reg & SDMMC_INTMASK_ACD) 374 sc->acd_rcvd = 1; 375 376 if (reg & SDMMC_INTMASK_DTO) 377 sc->dto_rcvd = 1; 378 379 if (reg & SDMMC_INTMASK_CD) { 380 dwmmc_handle_card_present(sc, 381 READ4(sc, SDMMC_CDETECT) == 0 ? true : false); 382 } 383 } 384 385 /* Ack interrupts */ 386 WRITE4(sc, SDMMC_RINTSTS, reg); 387 388 if (sc->use_pio) { 389 if (reg & (SDMMC_INTMASK_RXDR|SDMMC_INTMASK_DTO)) { 390 pio_read(sc, cmd); 391 } 392 if (reg & (SDMMC_INTMASK_TXDR|SDMMC_INTMASK_DTO)) { 393 pio_write(sc, cmd); 394 } 395 } else { 396 /* Now handle DMA interrupts */ 397 reg = READ4(sc, SDMMC_IDSTS); 398 if (reg) { 399 dprintf("dma intr 0x%08x\n", reg); 400 if (reg & (SDMMC_IDINTEN_TI | SDMMC_IDINTEN_RI)) { 401 WRITE4(sc, SDMMC_IDSTS, (SDMMC_IDINTEN_TI | 402 SDMMC_IDINTEN_RI)); 403 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_NI); 404 dma_done(sc, cmd); 405 } 406 } 407 } 408 409 dwmmc_tasklet(sc); 410 411 DWMMC_UNLOCK(sc); 412 } 413 414 static void 415 dwmmc_handle_card_present(struct dwmmc_softc *sc, bool is_present) 416 { 417 bool was_present; 418 419 was_present = sc->child != NULL; 420 421 if (!was_present && is_present) { 422 taskqueue_enqueue_timeout(taskqueue_swi_giant, 423 &sc->card_delayed_task, -(hz / 2)); 424 } else if (was_present && !is_present) { 425 taskqueue_enqueue(taskqueue_swi_giant, &sc->card_task); 426 } 427 } 428 429 static void 430 dwmmc_card_task(void *arg, int pending __unused) 431 { 432 struct dwmmc_softc *sc = arg; 433 434 DWMMC_LOCK(sc); 435 436 if (READ4(sc, SDMMC_CDETECT) == 0) { 437 if (sc->child == NULL) { 438 if (bootverbose) 439 device_printf(sc->dev, "Card inserted\n"); 440 441 sc->child = device_add_child(sc->dev, "mmc", -1); 442 DWMMC_UNLOCK(sc); 443 if (sc->child) { 444 device_set_ivars(sc->child, sc); 445 (void)device_probe_and_attach(sc->child); 446 } 447 } else 448 DWMMC_UNLOCK(sc); 449 450 } else { 451 /* Card isn't present, detach if necessary */ 452 if (sc->child != NULL) { 453 if (bootverbose) 454 device_printf(sc->dev, "Card removed\n"); 455 456 DWMMC_UNLOCK(sc); 457 device_delete_child(sc->dev, sc->child); 458 sc->child = NULL; 459 } else 460 DWMMC_UNLOCK(sc); 461 } 462 } 463 464 static int 465 parse_fdt(struct dwmmc_softc *sc) 466 { 467 pcell_t dts_value[3]; 468 phandle_t node; 469 uint32_t bus_hz = 0, bus_width; 470 int len; 471 #ifdef EXT_RESOURCES 472 int error; 473 #endif 474 475 if ((node = ofw_bus_get_node(sc->dev)) == -1) 476 return (ENXIO); 477 478 /* bus-width */ 479 if (OF_getencprop(node, "bus-width", &bus_width, sizeof(uint32_t)) <= 0) 480 bus_width = 4; 481 if (bus_width >= 4) 482 sc->host.caps |= MMC_CAP_4_BIT_DATA; 483 if (bus_width >= 8) 484 sc->host.caps |= MMC_CAP_8_BIT_DATA; 485 486 /* max-frequency */ 487 if (OF_getencprop(node, "max-frequency", &sc->max_hz, sizeof(uint32_t)) <= 0) 488 sc->max_hz = 200000000; 489 490 /* fifo-depth */ 491 if ((len = OF_getproplen(node, "fifo-depth")) > 0) { 492 OF_getencprop(node, "fifo-depth", dts_value, len); 493 sc->fifo_depth = dts_value[0]; 494 } 495 496 /* num-slots (Deprecated) */ 497 sc->num_slots = 1; 498 if ((len = OF_getproplen(node, "num-slots")) > 0) { 499 device_printf(sc->dev, "num-slots property is deprecated\n"); 500 OF_getencprop(node, "num-slots", dts_value, len); 501 sc->num_slots = dts_value[0]; 502 } 503 504 /* clock-frequency */ 505 if ((len = OF_getproplen(node, "clock-frequency")) > 0) { 506 OF_getencprop(node, "clock-frequency", dts_value, len); 507 bus_hz = dts_value[0]; 508 } 509 510 #ifdef EXT_RESOURCES 511 512 /* IP block reset is optional */ 513 error = hwreset_get_by_ofw_name(sc->dev, 0, "reset", &sc->hwreset); 514 if (error != 0 && 515 error != ENOENT && 516 error != ENODEV) { 517 device_printf(sc->dev, "Cannot get reset\n"); 518 goto fail; 519 } 520 521 /* vmmc regulator is optional */ 522 error = regulator_get_by_ofw_property(sc->dev, 0, "vmmc-supply", 523 &sc->vmmc); 524 if (error != 0 && 525 error != ENOENT && 526 error != ENODEV) { 527 device_printf(sc->dev, "Cannot get regulator 'vmmc-supply'\n"); 528 goto fail; 529 } 530 531 /* vqmmc regulator is optional */ 532 error = regulator_get_by_ofw_property(sc->dev, 0, "vqmmc-supply", 533 &sc->vqmmc); 534 if (error != 0 && 535 error != ENOENT && 536 error != ENODEV) { 537 device_printf(sc->dev, "Cannot get regulator 'vqmmc-supply'\n"); 538 goto fail; 539 } 540 541 /* Assert reset first */ 542 if (sc->hwreset != NULL) { 543 error = hwreset_assert(sc->hwreset); 544 if (error != 0) { 545 device_printf(sc->dev, "Cannot assert reset\n"); 546 goto fail; 547 } 548 } 549 550 /* BIU (Bus Interface Unit clock) is optional */ 551 error = clk_get_by_ofw_name(sc->dev, 0, "biu", &sc->biu); 552 if (error != 0 && 553 error != ENOENT && 554 error != ENODEV) { 555 device_printf(sc->dev, "Cannot get 'biu' clock\n"); 556 goto fail; 557 } 558 559 if (sc->biu) { 560 error = clk_enable(sc->biu); 561 if (error != 0) { 562 device_printf(sc->dev, "cannot enable biu clock\n"); 563 goto fail; 564 } 565 } 566 567 /* 568 * CIU (Controller Interface Unit clock) is mandatory 569 * if no clock-frequency property is given 570 */ 571 error = clk_get_by_ofw_name(sc->dev, 0, "ciu", &sc->ciu); 572 if (error != 0 && 573 error != ENOENT && 574 error != ENODEV) { 575 device_printf(sc->dev, "Cannot get 'ciu' clock\n"); 576 goto fail; 577 } 578 579 if (sc->ciu) { 580 if (bus_hz != 0) { 581 error = clk_set_freq(sc->ciu, bus_hz, 0); 582 if (error != 0) 583 device_printf(sc->dev, 584 "cannot set ciu clock to %u\n", bus_hz); 585 } 586 error = clk_enable(sc->ciu); 587 if (error != 0) { 588 device_printf(sc->dev, "cannot enable ciu clock\n"); 589 goto fail; 590 } 591 clk_get_freq(sc->ciu, &sc->bus_hz); 592 } 593 594 /* Enable regulators */ 595 if (sc->vmmc != NULL) { 596 error = regulator_enable(sc->vmmc); 597 if (error != 0) { 598 device_printf(sc->dev, "Cannot enable vmmc regulator\n"); 599 goto fail; 600 } 601 } 602 if (sc->vqmmc != NULL) { 603 error = regulator_enable(sc->vqmmc); 604 if (error != 0) { 605 device_printf(sc->dev, "Cannot enable vqmmc regulator\n"); 606 goto fail; 607 } 608 } 609 610 /* Take dwmmc out of reset */ 611 if (sc->hwreset != NULL) { 612 error = hwreset_deassert(sc->hwreset); 613 if (error != 0) { 614 device_printf(sc->dev, "Cannot deassert reset\n"); 615 goto fail; 616 } 617 } 618 #endif /* EXT_RESOURCES */ 619 620 if (sc->bus_hz == 0) { 621 device_printf(sc->dev, "No bus speed provided\n"); 622 goto fail; 623 } 624 625 return (0); 626 627 fail: 628 return (ENXIO); 629 } 630 631 int 632 dwmmc_attach(device_t dev) 633 { 634 struct dwmmc_softc *sc; 635 int error; 636 int slot; 637 638 sc = device_get_softc(dev); 639 640 sc->dev = dev; 641 642 /* Why not to use Auto Stop? It save a hundred of irq per second */ 643 sc->use_auto_stop = 1; 644 645 error = parse_fdt(sc); 646 if (error != 0) { 647 device_printf(dev, "Can't get FDT property.\n"); 648 return (ENXIO); 649 } 650 651 DWMMC_LOCK_INIT(sc); 652 653 if (bus_alloc_resources(dev, dwmmc_spec, sc->res)) { 654 device_printf(dev, "could not allocate resources\n"); 655 return (ENXIO); 656 } 657 658 /* Setup interrupt handler. */ 659 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE, 660 NULL, dwmmc_intr, sc, &sc->intr_cookie); 661 if (error != 0) { 662 device_printf(dev, "could not setup interrupt handler.\n"); 663 return (ENXIO); 664 } 665 666 device_printf(dev, "Hardware version ID is %04x\n", 667 READ4(sc, SDMMC_VERID) & 0xffff); 668 669 if (sc->desc_count == 0) 670 sc->desc_count = DESC_MAX; 671 672 /* XXX: we support operation for slot index 0 only */ 673 slot = 0; 674 if (sc->pwren_inverted) { 675 WRITE4(sc, SDMMC_PWREN, (0 << slot)); 676 } else { 677 WRITE4(sc, SDMMC_PWREN, (1 << slot)); 678 } 679 680 /* Reset all */ 681 if (dwmmc_ctrl_reset(sc, (SDMMC_CTRL_RESET | 682 SDMMC_CTRL_FIFO_RESET | 683 SDMMC_CTRL_DMA_RESET))) 684 return (ENXIO); 685 686 dwmmc_setup_bus(sc, sc->host.f_min); 687 688 if (sc->fifo_depth == 0) { 689 sc->fifo_depth = 1 + 690 ((READ4(sc, SDMMC_FIFOTH) >> SDMMC_FIFOTH_RXWMARK_S) & 0xfff); 691 device_printf(dev, "No fifo-depth, using FIFOTH %x\n", 692 sc->fifo_depth); 693 } 694 695 if (!sc->use_pio) { 696 dma_stop(sc); 697 if (dma_setup(sc)) 698 return (ENXIO); 699 700 /* Install desc base */ 701 WRITE4(sc, SDMMC_DBADDR, sc->desc_ring_paddr); 702 703 /* Enable DMA interrupts */ 704 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_MASK); 705 WRITE4(sc, SDMMC_IDINTEN, (SDMMC_IDINTEN_NI | 706 SDMMC_IDINTEN_RI | 707 SDMMC_IDINTEN_TI)); 708 } 709 710 /* Clear and disable interrups for a while */ 711 WRITE4(sc, SDMMC_RINTSTS, 0xffffffff); 712 WRITE4(sc, SDMMC_INTMASK, 0); 713 714 /* Maximum timeout */ 715 WRITE4(sc, SDMMC_TMOUT, 0xffffffff); 716 717 /* Enable interrupts */ 718 WRITE4(sc, SDMMC_RINTSTS, 0xffffffff); 719 WRITE4(sc, SDMMC_INTMASK, (SDMMC_INTMASK_CMD_DONE | 720 SDMMC_INTMASK_DTO | 721 SDMMC_INTMASK_ACD | 722 SDMMC_INTMASK_TXDR | 723 SDMMC_INTMASK_RXDR | 724 DWMMC_ERR_FLAGS | 725 SDMMC_INTMASK_CD)); 726 WRITE4(sc, SDMMC_CTRL, SDMMC_CTRL_INT_ENABLE); 727 728 sc->host.f_min = 400000; 729 sc->host.f_max = sc->max_hz; 730 sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340; 731 sc->host.caps |= MMC_CAP_HSPEED; 732 sc->host.caps |= MMC_CAP_SIGNALING_330; 733 734 TASK_INIT(&sc->card_task, 0, dwmmc_card_task, sc); 735 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &sc->card_delayed_task, 0, 736 dwmmc_card_task, sc); 737 738 /* 739 * Schedule a card detection as we won't get an interrupt 740 * if the card is inserted when we attach 741 */ 742 dwmmc_card_task(sc, 0); 743 744 return (0); 745 } 746 747 int 748 dwmmc_detach(device_t dev) 749 { 750 struct dwmmc_softc *sc; 751 int ret; 752 753 sc = device_get_softc(dev); 754 755 ret = device_delete_children(dev); 756 if (ret != 0) 757 return (ret); 758 759 taskqueue_drain(taskqueue_swi_giant, &sc->card_task); 760 taskqueue_drain_timeout(taskqueue_swi_giant, &sc->card_delayed_task); 761 762 if (sc->intr_cookie != NULL) { 763 ret = bus_teardown_intr(dev, sc->res[1], sc->intr_cookie); 764 if (ret != 0) 765 return (ret); 766 } 767 bus_release_resources(dev, dwmmc_spec, sc->res); 768 769 DWMMC_LOCK_DESTROY(sc); 770 771 #ifdef EXT_RESOURCES 772 if (sc->hwreset != NULL && hwreset_deassert(sc->hwreset) != 0) 773 device_printf(sc->dev, "cannot deassert reset\n"); 774 if (sc->biu != NULL && clk_disable(sc->biu) != 0) 775 device_printf(sc->dev, "cannot disable biu clock\n"); 776 if (sc->ciu != NULL && clk_disable(sc->ciu) != 0) 777 device_printf(sc->dev, "cannot disable ciu clock\n"); 778 779 if (sc->vmmc && regulator_disable(sc->vmmc) != 0) 780 device_printf(sc->dev, "Cannot disable vmmc regulator\n"); 781 if (sc->vqmmc && regulator_disable(sc->vqmmc) != 0) 782 device_printf(sc->dev, "Cannot disable vqmmc regulator\n"); 783 #endif 784 785 return (0); 786 } 787 788 static int 789 dwmmc_setup_bus(struct dwmmc_softc *sc, int freq) 790 { 791 int tout; 792 int div; 793 794 if (freq == 0) { 795 WRITE4(sc, SDMMC_CLKENA, 0); 796 WRITE4(sc, SDMMC_CMD, (SDMMC_CMD_WAIT_PRVDATA | 797 SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START)); 798 799 tout = 1000; 800 do { 801 if (tout-- < 0) { 802 device_printf(sc->dev, "Failed update clk\n"); 803 return (1); 804 } 805 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START); 806 807 return (0); 808 } 809 810 WRITE4(sc, SDMMC_CLKENA, 0); 811 WRITE4(sc, SDMMC_CLKSRC, 0); 812 813 div = (sc->bus_hz != freq) ? DIV_ROUND_UP(sc->bus_hz, 2 * freq) : 0; 814 815 WRITE4(sc, SDMMC_CLKDIV, div); 816 WRITE4(sc, SDMMC_CMD, (SDMMC_CMD_WAIT_PRVDATA | 817 SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START)); 818 819 tout = 1000; 820 do { 821 if (tout-- < 0) { 822 device_printf(sc->dev, "Failed to update clk"); 823 return (1); 824 } 825 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START); 826 827 WRITE4(sc, SDMMC_CLKENA, (SDMMC_CLKENA_CCLK_EN | SDMMC_CLKENA_LP)); 828 WRITE4(sc, SDMMC_CMD, SDMMC_CMD_WAIT_PRVDATA | 829 SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START); 830 831 tout = 1000; 832 do { 833 if (tout-- < 0) { 834 device_printf(sc->dev, "Failed to enable clk\n"); 835 return (1); 836 } 837 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START); 838 839 return (0); 840 } 841 842 static int 843 dwmmc_update_ios(device_t brdev, device_t reqdev) 844 { 845 struct dwmmc_softc *sc; 846 struct mmc_ios *ios; 847 uint32_t reg; 848 int ret = 0; 849 850 sc = device_get_softc(brdev); 851 ios = &sc->host.ios; 852 853 dprintf("Setting up clk %u bus_width %d\n", 854 ios->clock, ios->bus_width); 855 856 if (ios->bus_width == bus_width_8) 857 WRITE4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT); 858 else if (ios->bus_width == bus_width_4) 859 WRITE4(sc, SDMMC_CTYPE, SDMMC_CTYPE_4BIT); 860 else 861 WRITE4(sc, SDMMC_CTYPE, 0); 862 863 if ((sc->hwtype & HWTYPE_MASK) == HWTYPE_EXYNOS) { 864 /* XXX: take care about DDR or SDR use here */ 865 WRITE4(sc, SDMMC_CLKSEL, sc->sdr_timing); 866 } 867 868 /* Set DDR mode */ 869 reg = READ4(sc, SDMMC_UHS_REG); 870 if (ios->timing == bus_timing_uhs_ddr50 || 871 ios->timing == bus_timing_mmc_ddr52 || 872 ios->timing == bus_timing_mmc_hs400) 873 reg |= (SDMMC_UHS_REG_DDR); 874 else 875 reg &= ~(SDMMC_UHS_REG_DDR); 876 WRITE4(sc, SDMMC_UHS_REG, reg); 877 878 if (sc->update_ios) 879 ret = sc->update_ios(sc, ios); 880 881 dwmmc_setup_bus(sc, ios->clock); 882 883 return (ret); 884 } 885 886 static int 887 dma_done(struct dwmmc_softc *sc, struct mmc_command *cmd) 888 { 889 struct mmc_data *data; 890 891 data = cmd->data; 892 893 if (data->flags & MMC_DATA_WRITE) 894 bus_dmamap_sync(sc->buf_tag, sc->buf_map, 895 BUS_DMASYNC_POSTWRITE); 896 else 897 bus_dmamap_sync(sc->buf_tag, sc->buf_map, 898 BUS_DMASYNC_POSTREAD); 899 900 bus_dmamap_sync(sc->desc_tag, sc->desc_map, 901 BUS_DMASYNC_POSTWRITE); 902 903 bus_dmamap_unload(sc->buf_tag, sc->buf_map); 904 905 return (0); 906 } 907 908 static int 909 dma_stop(struct dwmmc_softc *sc) 910 { 911 int reg; 912 913 reg = READ4(sc, SDMMC_CTRL); 914 reg &= ~(SDMMC_CTRL_USE_IDMAC); 915 reg |= (SDMMC_CTRL_DMA_RESET); 916 WRITE4(sc, SDMMC_CTRL, reg); 917 918 reg = READ4(sc, SDMMC_BMOD); 919 reg &= ~(SDMMC_BMOD_DE | SDMMC_BMOD_FB); 920 reg |= (SDMMC_BMOD_SWR); 921 WRITE4(sc, SDMMC_BMOD, reg); 922 923 return (0); 924 } 925 926 static int 927 dma_prepare(struct dwmmc_softc *sc, struct mmc_command *cmd) 928 { 929 struct mmc_data *data; 930 int err; 931 int reg; 932 933 data = cmd->data; 934 935 reg = READ4(sc, SDMMC_INTMASK); 936 reg &= ~(SDMMC_INTMASK_TXDR | SDMMC_INTMASK_RXDR); 937 WRITE4(sc, SDMMC_INTMASK, reg); 938 939 err = bus_dmamap_load(sc->buf_tag, sc->buf_map, 940 data->data, data->len, dwmmc_ring_setup, 941 sc, BUS_DMA_NOWAIT); 942 if (err != 0) 943 panic("dmamap_load failed\n"); 944 945 /* Ensure the device can see the desc */ 946 bus_dmamap_sync(sc->desc_tag, sc->desc_map, 947 BUS_DMASYNC_PREWRITE); 948 949 if (data->flags & MMC_DATA_WRITE) 950 bus_dmamap_sync(sc->buf_tag, sc->buf_map, 951 BUS_DMASYNC_PREWRITE); 952 else 953 bus_dmamap_sync(sc->buf_tag, sc->buf_map, 954 BUS_DMASYNC_PREREAD); 955 956 reg = (DEF_MSIZE << SDMMC_FIFOTH_MSIZE_S); 957 reg |= ((sc->fifo_depth / 2) - 1) << SDMMC_FIFOTH_RXWMARK_S; 958 reg |= (sc->fifo_depth / 2) << SDMMC_FIFOTH_TXWMARK_S; 959 960 WRITE4(sc, SDMMC_FIFOTH, reg); 961 wmb(); 962 963 reg = READ4(sc, SDMMC_CTRL); 964 reg |= (SDMMC_CTRL_USE_IDMAC | SDMMC_CTRL_DMA_ENABLE); 965 WRITE4(sc, SDMMC_CTRL, reg); 966 wmb(); 967 968 reg = READ4(sc, SDMMC_BMOD); 969 reg |= (SDMMC_BMOD_DE | SDMMC_BMOD_FB); 970 WRITE4(sc, SDMMC_BMOD, reg); 971 972 /* Start */ 973 WRITE4(sc, SDMMC_PLDMND, 1); 974 975 return (0); 976 } 977 978 static int 979 pio_prepare(struct dwmmc_softc *sc, struct mmc_command *cmd) 980 { 981 struct mmc_data *data; 982 int reg; 983 984 data = cmd->data; 985 data->xfer_len = 0; 986 987 reg = (DEF_MSIZE << SDMMC_FIFOTH_MSIZE_S); 988 reg |= ((sc->fifo_depth / 2) - 1) << SDMMC_FIFOTH_RXWMARK_S; 989 reg |= (sc->fifo_depth / 2) << SDMMC_FIFOTH_TXWMARK_S; 990 991 WRITE4(sc, SDMMC_FIFOTH, reg); 992 wmb(); 993 994 return (0); 995 } 996 997 static void 998 pio_read(struct dwmmc_softc *sc, struct mmc_command *cmd) 999 { 1000 struct mmc_data *data; 1001 uint32_t *p, status; 1002 1003 if (cmd == NULL || cmd->data == NULL) 1004 return; 1005 1006 data = cmd->data; 1007 if ((data->flags & MMC_DATA_READ) == 0) 1008 return; 1009 1010 KASSERT((data->xfer_len & 3) == 0, ("xfer_len not aligned")); 1011 p = (uint32_t *)data->data + (data->xfer_len >> 2); 1012 1013 while (data->xfer_len < data->len) { 1014 status = READ4(sc, SDMMC_STATUS); 1015 if (status & SDMMC_STATUS_FIFO_EMPTY) 1016 break; 1017 *p++ = READ4(sc, SDMMC_DATA); 1018 data->xfer_len += 4; 1019 } 1020 1021 WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_RXDR); 1022 } 1023 1024 static void 1025 pio_write(struct dwmmc_softc *sc, struct mmc_command *cmd) 1026 { 1027 struct mmc_data *data; 1028 uint32_t *p, status; 1029 1030 if (cmd == NULL || cmd->data == NULL) 1031 return; 1032 1033 data = cmd->data; 1034 if ((data->flags & MMC_DATA_WRITE) == 0) 1035 return; 1036 1037 KASSERT((data->xfer_len & 3) == 0, ("xfer_len not aligned")); 1038 p = (uint32_t *)data->data + (data->xfer_len >> 2); 1039 1040 while (data->xfer_len < data->len) { 1041 status = READ4(sc, SDMMC_STATUS); 1042 if (status & SDMMC_STATUS_FIFO_FULL) 1043 break; 1044 WRITE4(sc, SDMMC_DATA, *p++); 1045 data->xfer_len += 4; 1046 } 1047 1048 WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_TXDR); 1049 } 1050 1051 static void 1052 dwmmc_start_cmd(struct dwmmc_softc *sc, struct mmc_command *cmd) 1053 { 1054 struct mmc_data *data; 1055 uint32_t blksz; 1056 uint32_t cmdr; 1057 1058 sc->curcmd = cmd; 1059 data = cmd->data; 1060 1061 if ((sc->hwtype & HWTYPE_MASK) == HWTYPE_ROCKCHIP) 1062 dwmmc_setup_bus(sc, sc->host.ios.clock); 1063 1064 /* XXX Upper layers don't always set this */ 1065 cmd->mrq = sc->req; 1066 1067 /* Begin setting up command register. */ 1068 1069 cmdr = cmd->opcode; 1070 1071 dprintf("cmd->opcode 0x%08x\n", cmd->opcode); 1072 1073 if (cmd->opcode == MMC_STOP_TRANSMISSION || 1074 cmd->opcode == MMC_GO_IDLE_STATE || 1075 cmd->opcode == MMC_GO_INACTIVE_STATE) 1076 cmdr |= SDMMC_CMD_STOP_ABORT; 1077 else if (cmd->opcode != MMC_SEND_STATUS && data) 1078 cmdr |= SDMMC_CMD_WAIT_PRVDATA; 1079 1080 /* Set up response handling. */ 1081 if (MMC_RSP(cmd->flags) != MMC_RSP_NONE) { 1082 cmdr |= SDMMC_CMD_RESP_EXP; 1083 if (cmd->flags & MMC_RSP_136) 1084 cmdr |= SDMMC_CMD_RESP_LONG; 1085 } 1086 1087 if (cmd->flags & MMC_RSP_CRC) 1088 cmdr |= SDMMC_CMD_RESP_CRC; 1089 1090 /* 1091 * XXX: Not all platforms want this. 1092 */ 1093 cmdr |= SDMMC_CMD_USE_HOLD_REG; 1094 1095 if ((sc->flags & CARD_INIT_DONE) == 0) { 1096 sc->flags |= (CARD_INIT_DONE); 1097 cmdr |= SDMMC_CMD_SEND_INIT; 1098 } 1099 1100 if (data) { 1101 if ((cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK || 1102 cmd->opcode == MMC_READ_MULTIPLE_BLOCK) && 1103 sc->use_auto_stop) 1104 cmdr |= SDMMC_CMD_SEND_ASTOP; 1105 1106 cmdr |= SDMMC_CMD_DATA_EXP; 1107 if (data->flags & MMC_DATA_STREAM) 1108 cmdr |= SDMMC_CMD_MODE_STREAM; 1109 if (data->flags & MMC_DATA_WRITE) 1110 cmdr |= SDMMC_CMD_DATA_WRITE; 1111 1112 WRITE4(sc, SDMMC_TMOUT, 0xffffffff); 1113 WRITE4(sc, SDMMC_BYTCNT, data->len); 1114 blksz = (data->len < MMC_SECTOR_SIZE) ? \ 1115 data->len : MMC_SECTOR_SIZE; 1116 WRITE4(sc, SDMMC_BLKSIZ, blksz); 1117 1118 if (sc->use_pio) { 1119 pio_prepare(sc, cmd); 1120 } else { 1121 dma_prepare(sc, cmd); 1122 } 1123 wmb(); 1124 } 1125 1126 dprintf("cmdr 0x%08x\n", cmdr); 1127 1128 WRITE4(sc, SDMMC_CMDARG, cmd->arg); 1129 wmb(); 1130 WRITE4(sc, SDMMC_CMD, cmdr | SDMMC_CMD_START); 1131 }; 1132 1133 static void 1134 dwmmc_next_operation(struct dwmmc_softc *sc) 1135 { 1136 struct mmc_request *req; 1137 1138 req = sc->req; 1139 if (req == NULL) 1140 return; 1141 1142 sc->acd_rcvd = 0; 1143 sc->dto_rcvd = 0; 1144 sc->cmd_done = 0; 1145 1146 /* 1147 * XXX: Wait until card is still busy. 1148 * We do need this to prevent data timeouts, 1149 * mostly caused by multi-block write command 1150 * followed by single-read. 1151 */ 1152 while(READ4(sc, SDMMC_STATUS) & (SDMMC_STATUS_DATA_BUSY)) 1153 continue; 1154 1155 if (sc->flags & PENDING_CMD) { 1156 sc->flags &= ~PENDING_CMD; 1157 dwmmc_start_cmd(sc, req->cmd); 1158 return; 1159 } else if (sc->flags & PENDING_STOP && !sc->use_auto_stop) { 1160 sc->flags &= ~PENDING_STOP; 1161 dwmmc_start_cmd(sc, req->stop); 1162 return; 1163 } 1164 1165 sc->req = NULL; 1166 sc->curcmd = NULL; 1167 req->done(req); 1168 } 1169 1170 static int 1171 dwmmc_request(device_t brdev, device_t reqdev, struct mmc_request *req) 1172 { 1173 struct dwmmc_softc *sc; 1174 1175 sc = device_get_softc(brdev); 1176 1177 dprintf("%s\n", __func__); 1178 1179 DWMMC_LOCK(sc); 1180 1181 if (sc->req != NULL) { 1182 DWMMC_UNLOCK(sc); 1183 return (EBUSY); 1184 } 1185 1186 sc->req = req; 1187 sc->flags |= PENDING_CMD; 1188 if (sc->req->stop) 1189 sc->flags |= PENDING_STOP; 1190 dwmmc_next_operation(sc); 1191 1192 DWMMC_UNLOCK(sc); 1193 return (0); 1194 } 1195 1196 static int 1197 dwmmc_get_ro(device_t brdev, device_t reqdev) 1198 { 1199 1200 dprintf("%s\n", __func__); 1201 1202 return (0); 1203 } 1204 1205 static int 1206 dwmmc_acquire_host(device_t brdev, device_t reqdev) 1207 { 1208 struct dwmmc_softc *sc; 1209 1210 sc = device_get_softc(brdev); 1211 1212 DWMMC_LOCK(sc); 1213 while (sc->bus_busy) 1214 msleep(sc, &sc->sc_mtx, PZERO, "dwmmcah", hz / 5); 1215 sc->bus_busy++; 1216 DWMMC_UNLOCK(sc); 1217 return (0); 1218 } 1219 1220 static int 1221 dwmmc_release_host(device_t brdev, device_t reqdev) 1222 { 1223 struct dwmmc_softc *sc; 1224 1225 sc = device_get_softc(brdev); 1226 1227 DWMMC_LOCK(sc); 1228 sc->bus_busy--; 1229 wakeup(sc); 1230 DWMMC_UNLOCK(sc); 1231 return (0); 1232 } 1233 1234 static int 1235 dwmmc_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 1236 { 1237 struct dwmmc_softc *sc; 1238 1239 sc = device_get_softc(bus); 1240 1241 switch (which) { 1242 default: 1243 return (EINVAL); 1244 case MMCBR_IVAR_BUS_MODE: 1245 *(int *)result = sc->host.ios.bus_mode; 1246 break; 1247 case MMCBR_IVAR_BUS_WIDTH: 1248 *(int *)result = sc->host.ios.bus_width; 1249 break; 1250 case MMCBR_IVAR_CHIP_SELECT: 1251 *(int *)result = sc->host.ios.chip_select; 1252 break; 1253 case MMCBR_IVAR_CLOCK: 1254 *(int *)result = sc->host.ios.clock; 1255 break; 1256 case MMCBR_IVAR_F_MIN: 1257 *(int *)result = sc->host.f_min; 1258 break; 1259 case MMCBR_IVAR_F_MAX: 1260 *(int *)result = sc->host.f_max; 1261 break; 1262 case MMCBR_IVAR_HOST_OCR: 1263 *(int *)result = sc->host.host_ocr; 1264 break; 1265 case MMCBR_IVAR_MODE: 1266 *(int *)result = sc->host.mode; 1267 break; 1268 case MMCBR_IVAR_OCR: 1269 *(int *)result = sc->host.ocr; 1270 break; 1271 case MMCBR_IVAR_POWER_MODE: 1272 *(int *)result = sc->host.ios.power_mode; 1273 break; 1274 case MMCBR_IVAR_VDD: 1275 *(int *)result = sc->host.ios.vdd; 1276 break; 1277 case MMCBR_IVAR_VCCQ: 1278 *(int *)result = sc->host.ios.vccq; 1279 break; 1280 case MMCBR_IVAR_CAPS: 1281 *(int *)result = sc->host.caps; 1282 break; 1283 case MMCBR_IVAR_MAX_DATA: 1284 *(int *)result = sc->desc_count; 1285 break; 1286 case MMCBR_IVAR_TIMING: 1287 *(int *)result = sc->host.ios.timing; 1288 break; 1289 } 1290 return (0); 1291 } 1292 1293 static int 1294 dwmmc_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1295 { 1296 struct dwmmc_softc *sc; 1297 1298 sc = device_get_softc(bus); 1299 1300 switch (which) { 1301 default: 1302 return (EINVAL); 1303 case MMCBR_IVAR_BUS_MODE: 1304 sc->host.ios.bus_mode = value; 1305 break; 1306 case MMCBR_IVAR_BUS_WIDTH: 1307 sc->host.ios.bus_width = value; 1308 break; 1309 case MMCBR_IVAR_CHIP_SELECT: 1310 sc->host.ios.chip_select = value; 1311 break; 1312 case MMCBR_IVAR_CLOCK: 1313 sc->host.ios.clock = value; 1314 break; 1315 case MMCBR_IVAR_MODE: 1316 sc->host.mode = value; 1317 break; 1318 case MMCBR_IVAR_OCR: 1319 sc->host.ocr = value; 1320 break; 1321 case MMCBR_IVAR_POWER_MODE: 1322 sc->host.ios.power_mode = value; 1323 break; 1324 case MMCBR_IVAR_VDD: 1325 sc->host.ios.vdd = value; 1326 break; 1327 case MMCBR_IVAR_TIMING: 1328 sc->host.ios.timing = value; 1329 break; 1330 case MMCBR_IVAR_VCCQ: 1331 sc->host.ios.vccq = value; 1332 break; 1333 /* These are read-only */ 1334 case MMCBR_IVAR_CAPS: 1335 case MMCBR_IVAR_HOST_OCR: 1336 case MMCBR_IVAR_F_MIN: 1337 case MMCBR_IVAR_F_MAX: 1338 case MMCBR_IVAR_MAX_DATA: 1339 return (EINVAL); 1340 } 1341 return (0); 1342 } 1343 1344 static device_method_t dwmmc_methods[] = { 1345 /* Bus interface */ 1346 DEVMETHOD(bus_read_ivar, dwmmc_read_ivar), 1347 DEVMETHOD(bus_write_ivar, dwmmc_write_ivar), 1348 1349 /* mmcbr_if */ 1350 DEVMETHOD(mmcbr_update_ios, dwmmc_update_ios), 1351 DEVMETHOD(mmcbr_request, dwmmc_request), 1352 DEVMETHOD(mmcbr_get_ro, dwmmc_get_ro), 1353 DEVMETHOD(mmcbr_acquire_host, dwmmc_acquire_host), 1354 DEVMETHOD(mmcbr_release_host, dwmmc_release_host), 1355 1356 DEVMETHOD_END 1357 }; 1358 1359 DEFINE_CLASS_0(dwmmc, dwmmc_driver, dwmmc_methods, 1360 sizeof(struct dwmmc_softc)); 1361