1 /*- 2 * Copyright (c) 2014-2019 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Synopsys DesignWare Mobile Storage Host Controller 33 * Chapter 14, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22) 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/bus.h> 42 #include <sys/kernel.h> 43 #include <sys/lock.h> 44 #include <sys/module.h> 45 #include <sys/malloc.h> 46 #include <sys/mutex.h> 47 #include <sys/rman.h> 48 #include <sys/queue.h> 49 #include <sys/taskqueue.h> 50 51 #include <dev/mmc/bridge.h> 52 #include <dev/mmc/mmcbrvar.h> 53 #include <dev/mmc/mmc_fdt_helpers.h> 54 55 #include <dev/fdt/fdt_common.h> 56 #include <dev/ofw/openfirm.h> 57 #include <dev/ofw/ofw_bus.h> 58 #include <dev/ofw/ofw_bus_subr.h> 59 60 #include <machine/bus.h> 61 #include <machine/cpu.h> 62 #include <machine/intr.h> 63 64 #ifdef EXT_RESOURCES 65 #include <dev/extres/clk/clk.h> 66 #endif 67 68 #include <dev/mmc/host/dwmmc_reg.h> 69 #include <dev/mmc/host/dwmmc_var.h> 70 71 #include "opt_mmccam.h" 72 73 #ifdef MMCCAM 74 #include <cam/cam.h> 75 #include <cam/cam_ccb.h> 76 #include <cam/cam_debug.h> 77 #include <cam/cam_sim.h> 78 #include <cam/cam_xpt_sim.h> 79 80 #include "mmc_sim_if.h" 81 #endif 82 83 #include "mmcbr_if.h" 84 85 #ifdef DEBUG 86 #define dprintf(fmt, args...) printf(fmt, ##args) 87 #else 88 #define dprintf(x, arg...) 89 #endif 90 91 #define READ4(_sc, _reg) \ 92 bus_read_4((_sc)->res[0], _reg) 93 #define WRITE4(_sc, _reg, _val) \ 94 bus_write_4((_sc)->res[0], _reg, _val) 95 96 #define DIV_ROUND_UP(n, d) howmany(n, d) 97 98 #define DWMMC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 99 #define DWMMC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 100 #define DWMMC_LOCK_INIT(_sc) \ 101 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 102 "dwmmc", MTX_DEF) 103 #define DWMMC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 104 #define DWMMC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 105 #define DWMMC_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 106 107 #define PENDING_CMD 0x01 108 #define PENDING_STOP 0x02 109 #define CARD_INIT_DONE 0x04 110 111 #define DWMMC_DATA_ERR_FLAGS (SDMMC_INTMASK_DRT | SDMMC_INTMASK_DCRC \ 112 |SDMMC_INTMASK_SBE | SDMMC_INTMASK_EBE) 113 #define DWMMC_CMD_ERR_FLAGS (SDMMC_INTMASK_RTO | SDMMC_INTMASK_RCRC \ 114 |SDMMC_INTMASK_RE) 115 #define DWMMC_ERR_FLAGS (DWMMC_DATA_ERR_FLAGS | DWMMC_CMD_ERR_FLAGS \ 116 |SDMMC_INTMASK_HLE) 117 118 #define DES0_DIC (1 << 1) /* Disable Interrupt on Completion */ 119 #define DES0_LD (1 << 2) /* Last Descriptor */ 120 #define DES0_FS (1 << 3) /* First Descriptor */ 121 #define DES0_CH (1 << 4) /* second address CHained */ 122 #define DES0_ER (1 << 5) /* End of Ring */ 123 #define DES0_CES (1 << 30) /* Card Error Summary */ 124 #define DES0_OWN (1 << 31) /* OWN */ 125 126 #define DES1_BS1_MASK 0x1fff 127 128 struct idmac_desc { 129 uint32_t des0; /* control */ 130 uint32_t des1; /* bufsize */ 131 uint32_t des2; /* buf1 phys addr */ 132 uint32_t des3; /* buf2 phys addr or next descr */ 133 }; 134 135 #define IDMAC_DESC_SEGS (PAGE_SIZE / (sizeof(struct idmac_desc))) 136 #define IDMAC_DESC_SIZE (sizeof(struct idmac_desc) * IDMAC_DESC_SEGS) 137 #define DEF_MSIZE 0x2 /* Burst size of multiple transaction */ 138 /* 139 * Size field in DMA descriptor is 13 bits long (up to 4095 bytes), 140 * but must be a multiple of the data bus size.Additionally, we must ensure 141 * that bus_dmamap_load() doesn't additionally fragments buffer (because it 142 * is processed with page size granularity). Thus limit fragment size to half 143 * of page. 144 * XXX switch descriptor format to array and use second buffer pointer for 145 * second half of page 146 */ 147 #define IDMAC_MAX_SIZE 2048 148 /* 149 * Busdma may bounce buffers, so we must reserve 2 descriptors 150 * (on start and on end) for bounced fragments. 151 */ 152 #define DWMMC_MAX_DATA (IDMAC_MAX_SIZE * (IDMAC_DESC_SEGS - 2)) / MMC_SECTOR_SIZE 153 154 static void dwmmc_next_operation(struct dwmmc_softc *); 155 static int dwmmc_setup_bus(struct dwmmc_softc *, int); 156 static int dma_done(struct dwmmc_softc *, struct mmc_command *); 157 static int dma_stop(struct dwmmc_softc *); 158 static void pio_read(struct dwmmc_softc *, struct mmc_command *); 159 static void pio_write(struct dwmmc_softc *, struct mmc_command *); 160 static void dwmmc_handle_card_present(struct dwmmc_softc *sc, bool is_present); 161 162 static struct resource_spec dwmmc_spec[] = { 163 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 164 { SYS_RES_IRQ, 0, RF_ACTIVE }, 165 { -1, 0 } 166 }; 167 168 #define HWTYPE_MASK (0x0000ffff) 169 #define HWFLAG_MASK (0xffff << 16) 170 171 static void 172 dwmmc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 173 { 174 175 if (nsegs != 1) 176 panic("%s: nsegs != 1 (%d)\n", __func__, nsegs); 177 if (error != 0) 178 panic("%s: error != 0 (%d)\n", __func__, error); 179 180 *(bus_addr_t *)arg = segs[0].ds_addr; 181 } 182 183 static void 184 dwmmc_ring_setup(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 185 { 186 struct dwmmc_softc *sc; 187 int idx; 188 189 sc = arg; 190 dprintf("nsegs %d seg0len %lu\n", nsegs, segs[0].ds_len); 191 if (error != 0) 192 panic("%s: error != 0 (%d)\n", __func__, error); 193 194 for (idx = 0; idx < nsegs; idx++) { 195 sc->desc_ring[idx].des0 = DES0_DIC | DES0_CH; 196 sc->desc_ring[idx].des1 = segs[idx].ds_len & DES1_BS1_MASK; 197 sc->desc_ring[idx].des2 = segs[idx].ds_addr; 198 199 if (idx == 0) 200 sc->desc_ring[idx].des0 |= DES0_FS; 201 202 if (idx == (nsegs - 1)) { 203 sc->desc_ring[idx].des0 &= ~(DES0_DIC | DES0_CH); 204 sc->desc_ring[idx].des0 |= DES0_LD; 205 } 206 wmb(); 207 sc->desc_ring[idx].des0 |= DES0_OWN; 208 } 209 } 210 211 static int 212 dwmmc_ctrl_reset(struct dwmmc_softc *sc, int reset_bits) 213 { 214 int reg; 215 int i; 216 217 reg = READ4(sc, SDMMC_CTRL); 218 reg |= (reset_bits); 219 WRITE4(sc, SDMMC_CTRL, reg); 220 221 /* Wait reset done */ 222 for (i = 0; i < 100; i++) { 223 if (!(READ4(sc, SDMMC_CTRL) & reset_bits)) 224 return (0); 225 DELAY(10); 226 } 227 228 device_printf(sc->dev, "Reset failed\n"); 229 230 return (1); 231 } 232 233 static int 234 dma_setup(struct dwmmc_softc *sc) 235 { 236 int error; 237 int nidx; 238 int idx; 239 240 /* 241 * Set up TX descriptor ring, descriptors, and dma maps. 242 */ 243 error = bus_dma_tag_create( 244 bus_get_dma_tag(sc->dev), /* Parent tag. */ 245 4096, 0, /* alignment, boundary */ 246 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 247 BUS_SPACE_MAXADDR, /* highaddr */ 248 NULL, NULL, /* filter, filterarg */ 249 IDMAC_DESC_SIZE, 1, /* maxsize, nsegments */ 250 IDMAC_DESC_SIZE, /* maxsegsize */ 251 0, /* flags */ 252 NULL, NULL, /* lockfunc, lockarg */ 253 &sc->desc_tag); 254 if (error != 0) { 255 device_printf(sc->dev, 256 "could not create ring DMA tag.\n"); 257 return (1); 258 } 259 260 error = bus_dmamem_alloc(sc->desc_tag, (void**)&sc->desc_ring, 261 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 262 &sc->desc_map); 263 if (error != 0) { 264 device_printf(sc->dev, 265 "could not allocate descriptor ring.\n"); 266 return (1); 267 } 268 269 error = bus_dmamap_load(sc->desc_tag, sc->desc_map, 270 sc->desc_ring, IDMAC_DESC_SIZE, dwmmc_get1paddr, 271 &sc->desc_ring_paddr, 0); 272 if (error != 0) { 273 device_printf(sc->dev, 274 "could not load descriptor ring map.\n"); 275 return (1); 276 } 277 278 for (idx = 0; idx < IDMAC_DESC_SEGS; idx++) { 279 sc->desc_ring[idx].des0 = DES0_CH; 280 sc->desc_ring[idx].des1 = 0; 281 nidx = (idx + 1) % IDMAC_DESC_SEGS; 282 sc->desc_ring[idx].des3 = sc->desc_ring_paddr + \ 283 (nidx * sizeof(struct idmac_desc)); 284 } 285 sc->desc_ring[idx - 1].des3 = sc->desc_ring_paddr; 286 sc->desc_ring[idx - 1].des0 |= DES0_ER; 287 288 error = bus_dma_tag_create( 289 bus_get_dma_tag(sc->dev), /* Parent tag. */ 290 8, 0, /* alignment, boundary */ 291 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 292 BUS_SPACE_MAXADDR, /* highaddr */ 293 NULL, NULL, /* filter, filterarg */ 294 IDMAC_MAX_SIZE * IDMAC_DESC_SEGS, /* maxsize */ 295 IDMAC_DESC_SEGS, /* nsegments */ 296 IDMAC_MAX_SIZE, /* maxsegsize */ 297 0, /* flags */ 298 NULL, NULL, /* lockfunc, lockarg */ 299 &sc->buf_tag); 300 if (error != 0) { 301 device_printf(sc->dev, 302 "could not create ring DMA tag.\n"); 303 return (1); 304 } 305 306 error = bus_dmamap_create(sc->buf_tag, 0, 307 &sc->buf_map); 308 if (error != 0) { 309 device_printf(sc->dev, 310 "could not create TX buffer DMA map.\n"); 311 return (1); 312 } 313 314 return (0); 315 } 316 317 static void 318 dwmmc_cmd_done(struct dwmmc_softc *sc) 319 { 320 struct mmc_command *cmd; 321 #ifdef MMCCAM 322 union ccb *ccb; 323 #endif 324 325 #ifdef MMCCAM 326 ccb = sc->ccb; 327 if (ccb == NULL) 328 return; 329 cmd = &ccb->mmcio.cmd; 330 #else 331 cmd = sc->curcmd; 332 #endif 333 if (cmd == NULL) 334 return; 335 336 if (cmd->flags & MMC_RSP_PRESENT) { 337 if (cmd->flags & MMC_RSP_136) { 338 cmd->resp[3] = READ4(sc, SDMMC_RESP0); 339 cmd->resp[2] = READ4(sc, SDMMC_RESP1); 340 cmd->resp[1] = READ4(sc, SDMMC_RESP2); 341 cmd->resp[0] = READ4(sc, SDMMC_RESP3); 342 } else { 343 cmd->resp[3] = 0; 344 cmd->resp[2] = 0; 345 cmd->resp[1] = 0; 346 cmd->resp[0] = READ4(sc, SDMMC_RESP0); 347 } 348 } 349 } 350 351 static void 352 dwmmc_tasklet(struct dwmmc_softc *sc) 353 { 354 struct mmc_command *cmd; 355 356 cmd = sc->curcmd; 357 if (cmd == NULL) 358 return; 359 360 if (!sc->cmd_done) 361 return; 362 363 if (cmd->error != MMC_ERR_NONE || !cmd->data) { 364 dwmmc_next_operation(sc); 365 } else if (cmd->data && sc->dto_rcvd) { 366 if ((cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK || 367 cmd->opcode == MMC_READ_MULTIPLE_BLOCK) && 368 sc->use_auto_stop) { 369 if (sc->acd_rcvd) 370 dwmmc_next_operation(sc); 371 } else { 372 dwmmc_next_operation(sc); 373 } 374 } 375 } 376 377 static void 378 dwmmc_intr(void *arg) 379 { 380 struct mmc_command *cmd; 381 struct dwmmc_softc *sc; 382 uint32_t reg; 383 384 sc = arg; 385 386 DWMMC_LOCK(sc); 387 388 cmd = sc->curcmd; 389 390 /* First handle SDMMC controller interrupts */ 391 reg = READ4(sc, SDMMC_MINTSTS); 392 if (reg) { 393 dprintf("%s 0x%08x\n", __func__, reg); 394 395 if (reg & DWMMC_CMD_ERR_FLAGS) { 396 dprintf("cmd err 0x%08x cmd 0x%08x\n", 397 reg, cmd->opcode); 398 cmd->error = MMC_ERR_TIMEOUT; 399 } 400 401 if (reg & DWMMC_DATA_ERR_FLAGS) { 402 dprintf("data err 0x%08x cmd 0x%08x\n", 403 reg, cmd->opcode); 404 cmd->error = MMC_ERR_FAILED; 405 if (!sc->use_pio) { 406 dma_done(sc, cmd); 407 dma_stop(sc); 408 } 409 } 410 411 if (reg & SDMMC_INTMASK_CMD_DONE) { 412 dwmmc_cmd_done(sc); 413 sc->cmd_done = 1; 414 } 415 416 if (reg & SDMMC_INTMASK_ACD) 417 sc->acd_rcvd = 1; 418 419 if (reg & SDMMC_INTMASK_DTO) 420 sc->dto_rcvd = 1; 421 422 if (reg & SDMMC_INTMASK_CD) { 423 dwmmc_handle_card_present(sc, 424 READ4(sc, SDMMC_CDETECT) == 0 ? true : false); 425 } 426 } 427 428 /* Ack interrupts */ 429 WRITE4(sc, SDMMC_RINTSTS, reg); 430 431 if (sc->use_pio) { 432 if (reg & (SDMMC_INTMASK_RXDR|SDMMC_INTMASK_DTO)) { 433 pio_read(sc, cmd); 434 } 435 if (reg & (SDMMC_INTMASK_TXDR|SDMMC_INTMASK_DTO)) { 436 pio_write(sc, cmd); 437 } 438 } else { 439 /* Now handle DMA interrupts */ 440 reg = READ4(sc, SDMMC_IDSTS); 441 if (reg) { 442 dprintf("dma intr 0x%08x\n", reg); 443 if (reg & (SDMMC_IDINTEN_TI | SDMMC_IDINTEN_RI)) { 444 WRITE4(sc, SDMMC_IDSTS, (SDMMC_IDINTEN_TI | 445 SDMMC_IDINTEN_RI)); 446 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_NI); 447 dma_done(sc, cmd); 448 } 449 } 450 } 451 452 dwmmc_tasklet(sc); 453 454 DWMMC_UNLOCK(sc); 455 } 456 457 static void 458 dwmmc_handle_card_present(struct dwmmc_softc *sc, bool is_present) 459 { 460 bool was_present; 461 462 was_present = sc->child != NULL; 463 464 if (!was_present && is_present) { 465 taskqueue_enqueue_timeout(taskqueue_swi_giant, 466 &sc->card_delayed_task, -(hz / 2)); 467 } else if (was_present && !is_present) { 468 taskqueue_enqueue(taskqueue_swi_giant, &sc->card_task); 469 } 470 } 471 472 static void 473 dwmmc_card_task(void *arg, int pending __unused) 474 { 475 struct dwmmc_softc *sc = arg; 476 477 #ifdef MMCCAM 478 mmc_cam_sim_discover(&sc->mmc_sim); 479 #else 480 DWMMC_LOCK(sc); 481 482 if (READ4(sc, SDMMC_CDETECT) == 0 || 483 (sc->mmc_helper.props & MMC_PROP_BROKEN_CD)) { 484 if (sc->child == NULL) { 485 if (bootverbose) 486 device_printf(sc->dev, "Card inserted\n"); 487 488 sc->child = device_add_child(sc->dev, "mmc", -1); 489 DWMMC_UNLOCK(sc); 490 if (sc->child) { 491 device_set_ivars(sc->child, sc); 492 (void)device_probe_and_attach(sc->child); 493 } 494 } else 495 DWMMC_UNLOCK(sc); 496 } else { 497 /* Card isn't present, detach if necessary */ 498 if (sc->child != NULL) { 499 if (bootverbose) 500 device_printf(sc->dev, "Card removed\n"); 501 502 DWMMC_UNLOCK(sc); 503 device_delete_child(sc->dev, sc->child); 504 sc->child = NULL; 505 } else 506 DWMMC_UNLOCK(sc); 507 } 508 #endif /* MMCCAM */ 509 } 510 511 static int 512 parse_fdt(struct dwmmc_softc *sc) 513 { 514 pcell_t dts_value[3]; 515 phandle_t node; 516 uint32_t bus_hz = 0; 517 int len; 518 #ifdef EXT_RESOURCES 519 int error; 520 #endif 521 522 if ((node = ofw_bus_get_node(sc->dev)) == -1) 523 return (ENXIO); 524 525 /* Set some defaults for freq and supported mode */ 526 sc->host.f_min = 400000; 527 sc->host.f_max = 200000000; 528 sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340; 529 sc->host.caps = MMC_CAP_HSPEED | MMC_CAP_SIGNALING_330; 530 mmc_fdt_parse(sc->dev, node, &sc->mmc_helper, &sc->host); 531 532 /* fifo-depth */ 533 if ((len = OF_getproplen(node, "fifo-depth")) > 0) { 534 OF_getencprop(node, "fifo-depth", dts_value, len); 535 sc->fifo_depth = dts_value[0]; 536 } 537 538 /* num-slots (Deprecated) */ 539 sc->num_slots = 1; 540 if ((len = OF_getproplen(node, "num-slots")) > 0) { 541 device_printf(sc->dev, "num-slots property is deprecated\n"); 542 OF_getencprop(node, "num-slots", dts_value, len); 543 sc->num_slots = dts_value[0]; 544 } 545 546 /* clock-frequency */ 547 if ((len = OF_getproplen(node, "clock-frequency")) > 0) { 548 OF_getencprop(node, "clock-frequency", dts_value, len); 549 bus_hz = dts_value[0]; 550 } 551 552 #ifdef EXT_RESOURCES 553 554 /* IP block reset is optional */ 555 error = hwreset_get_by_ofw_name(sc->dev, 0, "reset", &sc->hwreset); 556 if (error != 0 && 557 error != ENOENT && 558 error != ENODEV) { 559 device_printf(sc->dev, "Cannot get reset\n"); 560 goto fail; 561 } 562 563 /* vmmc regulator is optional */ 564 error = regulator_get_by_ofw_property(sc->dev, 0, "vmmc-supply", 565 &sc->vmmc); 566 if (error != 0 && 567 error != ENOENT && 568 error != ENODEV) { 569 device_printf(sc->dev, "Cannot get regulator 'vmmc-supply'\n"); 570 goto fail; 571 } 572 573 /* vqmmc regulator is optional */ 574 error = regulator_get_by_ofw_property(sc->dev, 0, "vqmmc-supply", 575 &sc->vqmmc); 576 if (error != 0 && 577 error != ENOENT && 578 error != ENODEV) { 579 device_printf(sc->dev, "Cannot get regulator 'vqmmc-supply'\n"); 580 goto fail; 581 } 582 583 /* Assert reset first */ 584 if (sc->hwreset != NULL) { 585 error = hwreset_assert(sc->hwreset); 586 if (error != 0) { 587 device_printf(sc->dev, "Cannot assert reset\n"); 588 goto fail; 589 } 590 } 591 592 /* BIU (Bus Interface Unit clock) is optional */ 593 error = clk_get_by_ofw_name(sc->dev, 0, "biu", &sc->biu); 594 if (error != 0 && 595 error != ENOENT && 596 error != ENODEV) { 597 device_printf(sc->dev, "Cannot get 'biu' clock\n"); 598 goto fail; 599 } 600 601 if (sc->biu) { 602 error = clk_enable(sc->biu); 603 if (error != 0) { 604 device_printf(sc->dev, "cannot enable biu clock\n"); 605 goto fail; 606 } 607 } 608 609 /* 610 * CIU (Controller Interface Unit clock) is mandatory 611 * if no clock-frequency property is given 612 */ 613 error = clk_get_by_ofw_name(sc->dev, 0, "ciu", &sc->ciu); 614 if (error != 0 && 615 error != ENOENT && 616 error != ENODEV) { 617 device_printf(sc->dev, "Cannot get 'ciu' clock\n"); 618 goto fail; 619 } 620 621 if (sc->ciu) { 622 if (bus_hz != 0) { 623 error = clk_set_freq(sc->ciu, bus_hz, 0); 624 if (error != 0) 625 device_printf(sc->dev, 626 "cannot set ciu clock to %u\n", bus_hz); 627 } 628 error = clk_enable(sc->ciu); 629 if (error != 0) { 630 device_printf(sc->dev, "cannot enable ciu clock\n"); 631 goto fail; 632 } 633 clk_get_freq(sc->ciu, &sc->bus_hz); 634 } 635 636 /* Enable regulators */ 637 if (sc->vmmc != NULL) { 638 error = regulator_enable(sc->vmmc); 639 if (error != 0) { 640 device_printf(sc->dev, "Cannot enable vmmc regulator\n"); 641 goto fail; 642 } 643 } 644 if (sc->vqmmc != NULL) { 645 error = regulator_enable(sc->vqmmc); 646 if (error != 0) { 647 device_printf(sc->dev, "Cannot enable vqmmc regulator\n"); 648 goto fail; 649 } 650 } 651 652 /* Take dwmmc out of reset */ 653 if (sc->hwreset != NULL) { 654 error = hwreset_deassert(sc->hwreset); 655 if (error != 0) { 656 device_printf(sc->dev, "Cannot deassert reset\n"); 657 goto fail; 658 } 659 } 660 #endif /* EXT_RESOURCES */ 661 662 if (sc->bus_hz == 0) { 663 device_printf(sc->dev, "No bus speed provided\n"); 664 goto fail; 665 } 666 667 return (0); 668 669 fail: 670 return (ENXIO); 671 } 672 673 int 674 dwmmc_attach(device_t dev) 675 { 676 struct dwmmc_softc *sc; 677 int error; 678 679 sc = device_get_softc(dev); 680 681 sc->dev = dev; 682 683 /* Why not to use Auto Stop? It save a hundred of irq per second */ 684 sc->use_auto_stop = 1; 685 686 error = parse_fdt(sc); 687 if (error != 0) { 688 device_printf(dev, "Can't get FDT property.\n"); 689 return (ENXIO); 690 } 691 692 DWMMC_LOCK_INIT(sc); 693 694 if (bus_alloc_resources(dev, dwmmc_spec, sc->res)) { 695 device_printf(dev, "could not allocate resources\n"); 696 return (ENXIO); 697 } 698 699 /* Setup interrupt handler. */ 700 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE, 701 NULL, dwmmc_intr, sc, &sc->intr_cookie); 702 if (error != 0) { 703 device_printf(dev, "could not setup interrupt handler.\n"); 704 return (ENXIO); 705 } 706 707 device_printf(dev, "Hardware version ID is %04x\n", 708 READ4(sc, SDMMC_VERID) & 0xffff); 709 710 /* Reset all */ 711 if (dwmmc_ctrl_reset(sc, (SDMMC_CTRL_RESET | 712 SDMMC_CTRL_FIFO_RESET | 713 SDMMC_CTRL_DMA_RESET))) 714 return (ENXIO); 715 716 dwmmc_setup_bus(sc, sc->host.f_min); 717 718 if (sc->fifo_depth == 0) { 719 sc->fifo_depth = 1 + 720 ((READ4(sc, SDMMC_FIFOTH) >> SDMMC_FIFOTH_RXWMARK_S) & 0xfff); 721 device_printf(dev, "No fifo-depth, using FIFOTH %x\n", 722 sc->fifo_depth); 723 } 724 725 if (!sc->use_pio) { 726 dma_stop(sc); 727 if (dma_setup(sc)) 728 return (ENXIO); 729 730 /* Install desc base */ 731 WRITE4(sc, SDMMC_DBADDR, sc->desc_ring_paddr); 732 733 /* Enable DMA interrupts */ 734 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_MASK); 735 WRITE4(sc, SDMMC_IDINTEN, (SDMMC_IDINTEN_NI | 736 SDMMC_IDINTEN_RI | 737 SDMMC_IDINTEN_TI)); 738 } 739 740 /* Clear and disable interrups for a while */ 741 WRITE4(sc, SDMMC_RINTSTS, 0xffffffff); 742 WRITE4(sc, SDMMC_INTMASK, 0); 743 744 /* Maximum timeout */ 745 WRITE4(sc, SDMMC_TMOUT, 0xffffffff); 746 747 /* Enable interrupts */ 748 WRITE4(sc, SDMMC_RINTSTS, 0xffffffff); 749 WRITE4(sc, SDMMC_INTMASK, (SDMMC_INTMASK_CMD_DONE | 750 SDMMC_INTMASK_DTO | 751 SDMMC_INTMASK_ACD | 752 SDMMC_INTMASK_TXDR | 753 SDMMC_INTMASK_RXDR | 754 DWMMC_ERR_FLAGS | 755 SDMMC_INTMASK_CD)); 756 WRITE4(sc, SDMMC_CTRL, SDMMC_CTRL_INT_ENABLE); 757 758 TASK_INIT(&sc->card_task, 0, dwmmc_card_task, sc); 759 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &sc->card_delayed_task, 0, 760 dwmmc_card_task, sc); 761 762 #ifdef MMCCAM 763 sc->ccb = NULL; 764 if (mmc_cam_sim_alloc(dev, "dw_mmc", &sc->mmc_sim) != 0) { 765 device_printf(dev, "cannot alloc cam sim\n"); 766 dwmmc_detach(dev); 767 return (ENXIO); 768 } 769 #endif 770 /* 771 * Schedule a card detection as we won't get an interrupt 772 * if the card is inserted when we attach 773 */ 774 dwmmc_card_task(sc, 0); 775 return (0); 776 } 777 778 int 779 dwmmc_detach(device_t dev) 780 { 781 struct dwmmc_softc *sc; 782 int ret; 783 784 sc = device_get_softc(dev); 785 786 ret = device_delete_children(dev); 787 if (ret != 0) 788 return (ret); 789 790 taskqueue_drain(taskqueue_swi_giant, &sc->card_task); 791 taskqueue_drain_timeout(taskqueue_swi_giant, &sc->card_delayed_task); 792 793 if (sc->intr_cookie != NULL) { 794 ret = bus_teardown_intr(dev, sc->res[1], sc->intr_cookie); 795 if (ret != 0) 796 return (ret); 797 } 798 bus_release_resources(dev, dwmmc_spec, sc->res); 799 800 DWMMC_LOCK_DESTROY(sc); 801 802 #ifdef EXT_RESOURCES 803 if (sc->hwreset != NULL && hwreset_deassert(sc->hwreset) != 0) 804 device_printf(sc->dev, "cannot deassert reset\n"); 805 if (sc->biu != NULL && clk_disable(sc->biu) != 0) 806 device_printf(sc->dev, "cannot disable biu clock\n"); 807 if (sc->ciu != NULL && clk_disable(sc->ciu) != 0) 808 device_printf(sc->dev, "cannot disable ciu clock\n"); 809 810 if (sc->vmmc && regulator_disable(sc->vmmc) != 0) 811 device_printf(sc->dev, "Cannot disable vmmc regulator\n"); 812 if (sc->vqmmc && regulator_disable(sc->vqmmc) != 0) 813 device_printf(sc->dev, "Cannot disable vqmmc regulator\n"); 814 #endif 815 816 #ifdef MMCCAM 817 mmc_cam_sim_free(&sc->mmc_sim); 818 #endif 819 820 return (0); 821 } 822 823 static int 824 dwmmc_setup_bus(struct dwmmc_softc *sc, int freq) 825 { 826 int tout; 827 int div; 828 829 if (freq == 0) { 830 WRITE4(sc, SDMMC_CLKENA, 0); 831 WRITE4(sc, SDMMC_CMD, (SDMMC_CMD_WAIT_PRVDATA | 832 SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START)); 833 834 tout = 1000; 835 do { 836 if (tout-- < 0) { 837 device_printf(sc->dev, "Failed update clk\n"); 838 return (1); 839 } 840 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START); 841 842 return (0); 843 } 844 845 WRITE4(sc, SDMMC_CLKENA, 0); 846 WRITE4(sc, SDMMC_CLKSRC, 0); 847 848 div = (sc->bus_hz != freq) ? DIV_ROUND_UP(sc->bus_hz, 2 * freq) : 0; 849 850 WRITE4(sc, SDMMC_CLKDIV, div); 851 WRITE4(sc, SDMMC_CMD, (SDMMC_CMD_WAIT_PRVDATA | 852 SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START)); 853 854 tout = 1000; 855 do { 856 if (tout-- < 0) { 857 device_printf(sc->dev, "Failed to update clk\n"); 858 return (1); 859 } 860 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START); 861 862 WRITE4(sc, SDMMC_CLKENA, (SDMMC_CLKENA_CCLK_EN | SDMMC_CLKENA_LP)); 863 WRITE4(sc, SDMMC_CMD, SDMMC_CMD_WAIT_PRVDATA | 864 SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START); 865 866 tout = 1000; 867 do { 868 if (tout-- < 0) { 869 device_printf(sc->dev, "Failed to enable clk\n"); 870 return (1); 871 } 872 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START); 873 874 return (0); 875 } 876 877 static int 878 dwmmc_update_ios(device_t brdev, device_t reqdev) 879 { 880 struct dwmmc_softc *sc; 881 struct mmc_ios *ios; 882 uint32_t reg; 883 int ret = 0; 884 885 sc = device_get_softc(brdev); 886 ios = &sc->host.ios; 887 888 dprintf("Setting up clk %u bus_width %d, timming: %d\n", 889 ios->clock, ios->bus_width, ios->timing); 890 891 switch (ios->power_mode) { 892 case power_on: 893 break; 894 case power_off: 895 WRITE4(sc, SDMMC_PWREN, 0); 896 break; 897 case power_up: 898 WRITE4(sc, SDMMC_PWREN, 1); 899 break; 900 } 901 902 mmc_fdt_set_power(&sc->mmc_helper, ios->power_mode); 903 904 if (ios->bus_width == bus_width_8) 905 WRITE4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT); 906 else if (ios->bus_width == bus_width_4) 907 WRITE4(sc, SDMMC_CTYPE, SDMMC_CTYPE_4BIT); 908 else 909 WRITE4(sc, SDMMC_CTYPE, 0); 910 911 if ((sc->hwtype & HWTYPE_MASK) == HWTYPE_EXYNOS) { 912 /* XXX: take care about DDR or SDR use here */ 913 WRITE4(sc, SDMMC_CLKSEL, sc->sdr_timing); 914 } 915 916 /* Set DDR mode */ 917 reg = READ4(sc, SDMMC_UHS_REG); 918 if (ios->timing == bus_timing_uhs_ddr50 || 919 ios->timing == bus_timing_mmc_ddr52 || 920 ios->timing == bus_timing_mmc_hs400) 921 reg |= (SDMMC_UHS_REG_DDR); 922 else 923 reg &= ~(SDMMC_UHS_REG_DDR); 924 WRITE4(sc, SDMMC_UHS_REG, reg); 925 926 if (sc->update_ios) 927 ret = sc->update_ios(sc, ios); 928 929 dwmmc_setup_bus(sc, ios->clock); 930 931 return (ret); 932 } 933 934 static int 935 dma_done(struct dwmmc_softc *sc, struct mmc_command *cmd) 936 { 937 struct mmc_data *data; 938 939 data = cmd->data; 940 941 if (data->flags & MMC_DATA_WRITE) 942 bus_dmamap_sync(sc->buf_tag, sc->buf_map, 943 BUS_DMASYNC_POSTWRITE); 944 else 945 bus_dmamap_sync(sc->buf_tag, sc->buf_map, 946 BUS_DMASYNC_POSTREAD); 947 948 bus_dmamap_sync(sc->desc_tag, sc->desc_map, 949 BUS_DMASYNC_POSTWRITE); 950 951 bus_dmamap_unload(sc->buf_tag, sc->buf_map); 952 953 return (0); 954 } 955 956 static int 957 dma_stop(struct dwmmc_softc *sc) 958 { 959 int reg; 960 961 reg = READ4(sc, SDMMC_CTRL); 962 reg &= ~(SDMMC_CTRL_USE_IDMAC); 963 reg |= (SDMMC_CTRL_DMA_RESET); 964 WRITE4(sc, SDMMC_CTRL, reg); 965 966 reg = READ4(sc, SDMMC_BMOD); 967 reg &= ~(SDMMC_BMOD_DE | SDMMC_BMOD_FB); 968 reg |= (SDMMC_BMOD_SWR); 969 WRITE4(sc, SDMMC_BMOD, reg); 970 971 return (0); 972 } 973 974 static int 975 dma_prepare(struct dwmmc_softc *sc, struct mmc_command *cmd) 976 { 977 struct mmc_data *data; 978 int err; 979 int reg; 980 981 data = cmd->data; 982 983 reg = READ4(sc, SDMMC_INTMASK); 984 reg &= ~(SDMMC_INTMASK_TXDR | SDMMC_INTMASK_RXDR); 985 WRITE4(sc, SDMMC_INTMASK, reg); 986 dprintf("%s: bus_dmamap_load size: %zu\n", __func__, data->len); 987 err = bus_dmamap_load(sc->buf_tag, sc->buf_map, 988 data->data, data->len, dwmmc_ring_setup, 989 sc, BUS_DMA_NOWAIT); 990 if (err != 0) 991 panic("dmamap_load failed\n"); 992 993 /* Ensure the device can see the desc */ 994 bus_dmamap_sync(sc->desc_tag, sc->desc_map, 995 BUS_DMASYNC_PREWRITE); 996 997 if (data->flags & MMC_DATA_WRITE) 998 bus_dmamap_sync(sc->buf_tag, sc->buf_map, 999 BUS_DMASYNC_PREWRITE); 1000 else 1001 bus_dmamap_sync(sc->buf_tag, sc->buf_map, 1002 BUS_DMASYNC_PREREAD); 1003 1004 reg = (DEF_MSIZE << SDMMC_FIFOTH_MSIZE_S); 1005 reg |= ((sc->fifo_depth / 2) - 1) << SDMMC_FIFOTH_RXWMARK_S; 1006 reg |= (sc->fifo_depth / 2) << SDMMC_FIFOTH_TXWMARK_S; 1007 1008 WRITE4(sc, SDMMC_FIFOTH, reg); 1009 wmb(); 1010 1011 reg = READ4(sc, SDMMC_CTRL); 1012 reg |= (SDMMC_CTRL_USE_IDMAC | SDMMC_CTRL_DMA_ENABLE); 1013 WRITE4(sc, SDMMC_CTRL, reg); 1014 wmb(); 1015 1016 reg = READ4(sc, SDMMC_BMOD); 1017 reg |= (SDMMC_BMOD_DE | SDMMC_BMOD_FB); 1018 WRITE4(sc, SDMMC_BMOD, reg); 1019 1020 /* Start */ 1021 WRITE4(sc, SDMMC_PLDMND, 1); 1022 1023 return (0); 1024 } 1025 1026 static int 1027 pio_prepare(struct dwmmc_softc *sc, struct mmc_command *cmd) 1028 { 1029 struct mmc_data *data; 1030 int reg; 1031 1032 data = cmd->data; 1033 data->xfer_len = 0; 1034 1035 reg = (DEF_MSIZE << SDMMC_FIFOTH_MSIZE_S); 1036 reg |= ((sc->fifo_depth / 2) - 1) << SDMMC_FIFOTH_RXWMARK_S; 1037 reg |= (sc->fifo_depth / 2) << SDMMC_FIFOTH_TXWMARK_S; 1038 1039 WRITE4(sc, SDMMC_FIFOTH, reg); 1040 wmb(); 1041 1042 return (0); 1043 } 1044 1045 static void 1046 pio_read(struct dwmmc_softc *sc, struct mmc_command *cmd) 1047 { 1048 struct mmc_data *data; 1049 uint32_t *p, status; 1050 1051 if (cmd == NULL || cmd->data == NULL) 1052 return; 1053 1054 data = cmd->data; 1055 if ((data->flags & MMC_DATA_READ) == 0) 1056 return; 1057 1058 KASSERT((data->xfer_len & 3) == 0, ("xfer_len not aligned")); 1059 p = (uint32_t *)data->data + (data->xfer_len >> 2); 1060 1061 while (data->xfer_len < data->len) { 1062 status = READ4(sc, SDMMC_STATUS); 1063 if (status & SDMMC_STATUS_FIFO_EMPTY) 1064 break; 1065 *p++ = READ4(sc, SDMMC_DATA); 1066 data->xfer_len += 4; 1067 } 1068 1069 WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_RXDR); 1070 } 1071 1072 static void 1073 pio_write(struct dwmmc_softc *sc, struct mmc_command *cmd) 1074 { 1075 struct mmc_data *data; 1076 uint32_t *p, status; 1077 1078 if (cmd == NULL || cmd->data == NULL) 1079 return; 1080 1081 data = cmd->data; 1082 if ((data->flags & MMC_DATA_WRITE) == 0) 1083 return; 1084 1085 KASSERT((data->xfer_len & 3) == 0, ("xfer_len not aligned")); 1086 p = (uint32_t *)data->data + (data->xfer_len >> 2); 1087 1088 while (data->xfer_len < data->len) { 1089 status = READ4(sc, SDMMC_STATUS); 1090 if (status & SDMMC_STATUS_FIFO_FULL) 1091 break; 1092 WRITE4(sc, SDMMC_DATA, *p++); 1093 data->xfer_len += 4; 1094 } 1095 1096 WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_TXDR); 1097 } 1098 1099 static void 1100 dwmmc_start_cmd(struct dwmmc_softc *sc, struct mmc_command *cmd) 1101 { 1102 struct mmc_data *data; 1103 uint32_t blksz; 1104 uint32_t cmdr; 1105 1106 dprintf("%s\n", __func__); 1107 sc->curcmd = cmd; 1108 data = cmd->data; 1109 1110 #ifndef MMCCAM 1111 /* XXX Upper layers don't always set this */ 1112 cmd->mrq = sc->req; 1113 #endif 1114 /* Begin setting up command register. */ 1115 1116 cmdr = cmd->opcode; 1117 1118 dprintf("cmd->opcode 0x%08x\n", cmd->opcode); 1119 1120 if (cmd->opcode == MMC_STOP_TRANSMISSION || 1121 cmd->opcode == MMC_GO_IDLE_STATE || 1122 cmd->opcode == MMC_GO_INACTIVE_STATE) 1123 cmdr |= SDMMC_CMD_STOP_ABORT; 1124 else if (cmd->opcode != MMC_SEND_STATUS && data) 1125 cmdr |= SDMMC_CMD_WAIT_PRVDATA; 1126 1127 /* Set up response handling. */ 1128 if (MMC_RSP(cmd->flags) != MMC_RSP_NONE) { 1129 cmdr |= SDMMC_CMD_RESP_EXP; 1130 if (cmd->flags & MMC_RSP_136) 1131 cmdr |= SDMMC_CMD_RESP_LONG; 1132 } 1133 1134 if (cmd->flags & MMC_RSP_CRC) 1135 cmdr |= SDMMC_CMD_RESP_CRC; 1136 1137 /* 1138 * XXX: Not all platforms want this. 1139 */ 1140 cmdr |= SDMMC_CMD_USE_HOLD_REG; 1141 1142 if ((sc->flags & CARD_INIT_DONE) == 0) { 1143 sc->flags |= (CARD_INIT_DONE); 1144 cmdr |= SDMMC_CMD_SEND_INIT; 1145 } 1146 1147 if (data) { 1148 if ((cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK || 1149 cmd->opcode == MMC_READ_MULTIPLE_BLOCK) && 1150 sc->use_auto_stop) 1151 cmdr |= SDMMC_CMD_SEND_ASTOP; 1152 1153 cmdr |= SDMMC_CMD_DATA_EXP; 1154 if (data->flags & MMC_DATA_STREAM) 1155 cmdr |= SDMMC_CMD_MODE_STREAM; 1156 if (data->flags & MMC_DATA_WRITE) 1157 cmdr |= SDMMC_CMD_DATA_WRITE; 1158 1159 WRITE4(sc, SDMMC_TMOUT, 0xffffffff); 1160 #ifdef MMCCAM 1161 if (cmd->data->flags & MMC_DATA_BLOCK_SIZE) { 1162 WRITE4(sc, SDMMC_BLKSIZ, cmd->data->block_size); 1163 WRITE4(sc, SDMMC_BYTCNT, cmd->data->len); 1164 } else 1165 #endif 1166 { 1167 WRITE4(sc, SDMMC_BYTCNT, data->len); 1168 blksz = (data->len < MMC_SECTOR_SIZE) ? \ 1169 data->len : MMC_SECTOR_SIZE; 1170 WRITE4(sc, SDMMC_BLKSIZ, blksz); 1171 } 1172 1173 if (sc->use_pio) { 1174 pio_prepare(sc, cmd); 1175 } else { 1176 dma_prepare(sc, cmd); 1177 } 1178 wmb(); 1179 } 1180 1181 dprintf("cmdr 0x%08x\n", cmdr); 1182 1183 WRITE4(sc, SDMMC_CMDARG, cmd->arg); 1184 wmb(); 1185 WRITE4(sc, SDMMC_CMD, cmdr | SDMMC_CMD_START); 1186 }; 1187 1188 static void 1189 dwmmc_next_operation(struct dwmmc_softc *sc) 1190 { 1191 struct mmc_command *cmd; 1192 dprintf("%s\n", __func__); 1193 #ifdef MMCCAM 1194 union ccb *ccb; 1195 1196 ccb = sc->ccb; 1197 if (ccb == NULL) 1198 return; 1199 cmd = &ccb->mmcio.cmd; 1200 #else 1201 struct mmc_request *req; 1202 1203 req = sc->req; 1204 if (req == NULL) 1205 return; 1206 cmd = req->cmd; 1207 #endif 1208 1209 sc->acd_rcvd = 0; 1210 sc->dto_rcvd = 0; 1211 sc->cmd_done = 0; 1212 1213 /* 1214 * XXX: Wait until card is still busy. 1215 * We do need this to prevent data timeouts, 1216 * mostly caused by multi-block write command 1217 * followed by single-read. 1218 */ 1219 while(READ4(sc, SDMMC_STATUS) & (SDMMC_STATUS_DATA_BUSY)) 1220 continue; 1221 1222 if (sc->flags & PENDING_CMD) { 1223 sc->flags &= ~PENDING_CMD; 1224 dwmmc_start_cmd(sc, cmd); 1225 return; 1226 } else if (sc->flags & PENDING_STOP && !sc->use_auto_stop) { 1227 sc->flags &= ~PENDING_STOP; 1228 /// XXX: What to do with this? 1229 //dwmmc_start_cmd(sc, req->stop); 1230 return; 1231 } 1232 1233 #ifdef MMCCAM 1234 sc->ccb = NULL; 1235 sc->curcmd = NULL; 1236 ccb->ccb_h.status = 1237 (ccb->mmcio.cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 1238 xpt_done(ccb); 1239 #else 1240 sc->req = NULL; 1241 sc->curcmd = NULL; 1242 req->done(req); 1243 #endif 1244 } 1245 1246 static int 1247 dwmmc_request(device_t brdev, device_t reqdev, struct mmc_request *req) 1248 { 1249 struct dwmmc_softc *sc; 1250 1251 sc = device_get_softc(brdev); 1252 1253 dprintf("%s\n", __func__); 1254 1255 DWMMC_LOCK(sc); 1256 1257 #ifdef MMCCAM 1258 sc->flags |= PENDING_CMD; 1259 #else 1260 if (sc->req != NULL) { 1261 DWMMC_UNLOCK(sc); 1262 return (EBUSY); 1263 } 1264 1265 sc->req = req; 1266 sc->flags |= PENDING_CMD; 1267 if (sc->req->stop) 1268 sc->flags |= PENDING_STOP; 1269 #endif 1270 dwmmc_next_operation(sc); 1271 1272 DWMMC_UNLOCK(sc); 1273 return (0); 1274 } 1275 1276 #ifndef MMCCAM 1277 static int 1278 dwmmc_get_ro(device_t brdev, device_t reqdev) 1279 { 1280 1281 dprintf("%s\n", __func__); 1282 1283 return (0); 1284 } 1285 1286 static int 1287 dwmmc_acquire_host(device_t brdev, device_t reqdev) 1288 { 1289 struct dwmmc_softc *sc; 1290 1291 sc = device_get_softc(brdev); 1292 1293 DWMMC_LOCK(sc); 1294 while (sc->bus_busy) 1295 msleep(sc, &sc->sc_mtx, PZERO, "dwmmcah", hz / 5); 1296 sc->bus_busy++; 1297 DWMMC_UNLOCK(sc); 1298 return (0); 1299 } 1300 1301 static int 1302 dwmmc_release_host(device_t brdev, device_t reqdev) 1303 { 1304 struct dwmmc_softc *sc; 1305 1306 sc = device_get_softc(brdev); 1307 1308 DWMMC_LOCK(sc); 1309 sc->bus_busy--; 1310 wakeup(sc); 1311 DWMMC_UNLOCK(sc); 1312 return (0); 1313 } 1314 #endif /* !MMCCAM */ 1315 1316 static int 1317 dwmmc_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 1318 { 1319 struct dwmmc_softc *sc; 1320 1321 sc = device_get_softc(bus); 1322 1323 switch (which) { 1324 default: 1325 return (EINVAL); 1326 case MMCBR_IVAR_BUS_MODE: 1327 *(int *)result = sc->host.ios.bus_mode; 1328 break; 1329 case MMCBR_IVAR_BUS_WIDTH: 1330 *(int *)result = sc->host.ios.bus_width; 1331 break; 1332 case MMCBR_IVAR_CHIP_SELECT: 1333 *(int *)result = sc->host.ios.chip_select; 1334 break; 1335 case MMCBR_IVAR_CLOCK: 1336 *(int *)result = sc->host.ios.clock; 1337 break; 1338 case MMCBR_IVAR_F_MIN: 1339 *(int *)result = sc->host.f_min; 1340 break; 1341 case MMCBR_IVAR_F_MAX: 1342 *(int *)result = sc->host.f_max; 1343 break; 1344 case MMCBR_IVAR_HOST_OCR: 1345 *(int *)result = sc->host.host_ocr; 1346 break; 1347 case MMCBR_IVAR_MODE: 1348 *(int *)result = sc->host.mode; 1349 break; 1350 case MMCBR_IVAR_OCR: 1351 *(int *)result = sc->host.ocr; 1352 break; 1353 case MMCBR_IVAR_POWER_MODE: 1354 *(int *)result = sc->host.ios.power_mode; 1355 break; 1356 case MMCBR_IVAR_VDD: 1357 *(int *)result = sc->host.ios.vdd; 1358 break; 1359 case MMCBR_IVAR_VCCQ: 1360 *(int *)result = sc->host.ios.vccq; 1361 break; 1362 case MMCBR_IVAR_CAPS: 1363 *(int *)result = sc->host.caps; 1364 break; 1365 case MMCBR_IVAR_MAX_DATA: 1366 *(int *)result = DWMMC_MAX_DATA; 1367 break; 1368 case MMCBR_IVAR_TIMING: 1369 *(int *)result = sc->host.ios.timing; 1370 break; 1371 } 1372 return (0); 1373 } 1374 1375 static int 1376 dwmmc_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1377 { 1378 struct dwmmc_softc *sc; 1379 1380 sc = device_get_softc(bus); 1381 1382 switch (which) { 1383 default: 1384 return (EINVAL); 1385 case MMCBR_IVAR_BUS_MODE: 1386 sc->host.ios.bus_mode = value; 1387 break; 1388 case MMCBR_IVAR_BUS_WIDTH: 1389 sc->host.ios.bus_width = value; 1390 break; 1391 case MMCBR_IVAR_CHIP_SELECT: 1392 sc->host.ios.chip_select = value; 1393 break; 1394 case MMCBR_IVAR_CLOCK: 1395 sc->host.ios.clock = value; 1396 break; 1397 case MMCBR_IVAR_MODE: 1398 sc->host.mode = value; 1399 break; 1400 case MMCBR_IVAR_OCR: 1401 sc->host.ocr = value; 1402 break; 1403 case MMCBR_IVAR_POWER_MODE: 1404 sc->host.ios.power_mode = value; 1405 break; 1406 case MMCBR_IVAR_VDD: 1407 sc->host.ios.vdd = value; 1408 break; 1409 case MMCBR_IVAR_TIMING: 1410 sc->host.ios.timing = value; 1411 break; 1412 case MMCBR_IVAR_VCCQ: 1413 sc->host.ios.vccq = value; 1414 break; 1415 /* These are read-only */ 1416 case MMCBR_IVAR_CAPS: 1417 case MMCBR_IVAR_HOST_OCR: 1418 case MMCBR_IVAR_F_MIN: 1419 case MMCBR_IVAR_F_MAX: 1420 case MMCBR_IVAR_MAX_DATA: 1421 return (EINVAL); 1422 } 1423 return (0); 1424 } 1425 1426 #ifdef MMCCAM 1427 /* Note: this function likely belongs to the specific driver impl */ 1428 static int 1429 dwmmc_switch_vccq(device_t dev, device_t child) 1430 { 1431 device_printf(dev, "This is a default impl of switch_vccq() that always fails\n"); 1432 return EINVAL; 1433 } 1434 1435 static int 1436 dwmmc_get_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts) 1437 { 1438 struct dwmmc_softc *sc; 1439 1440 sc = device_get_softc(dev); 1441 1442 cts->host_ocr = sc->host.host_ocr; 1443 cts->host_f_min = sc->host.f_min; 1444 cts->host_f_max = sc->host.f_max; 1445 cts->host_caps = sc->host.caps; 1446 cts->host_max_data = DWMMC_MAX_DATA; 1447 memcpy(&cts->ios, &sc->host.ios, sizeof(struct mmc_ios)); 1448 1449 return (0); 1450 } 1451 1452 static int 1453 dwmmc_set_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts) 1454 { 1455 struct dwmmc_softc *sc; 1456 struct mmc_ios *ios; 1457 struct mmc_ios *new_ios; 1458 int res; 1459 1460 sc = device_get_softc(dev); 1461 ios = &sc->host.ios; 1462 1463 new_ios = &cts->ios; 1464 1465 /* Update only requested fields */ 1466 if (cts->ios_valid & MMC_CLK) { 1467 ios->clock = new_ios->clock; 1468 if (bootverbose) 1469 device_printf(sc->dev, "Clock => %d\n", ios->clock); 1470 } 1471 if (cts->ios_valid & MMC_VDD) { 1472 ios->vdd = new_ios->vdd; 1473 if (bootverbose) 1474 device_printf(sc->dev, "VDD => %d\n", ios->vdd); 1475 } 1476 if (cts->ios_valid & MMC_CS) { 1477 ios->chip_select = new_ios->chip_select; 1478 if (bootverbose) 1479 device_printf(sc->dev, "CS => %d\n", ios->chip_select); 1480 } 1481 if (cts->ios_valid & MMC_BW) { 1482 ios->bus_width = new_ios->bus_width; 1483 if (bootverbose) 1484 device_printf(sc->dev, "Bus width => %d\n", ios->bus_width); 1485 } 1486 if (cts->ios_valid & MMC_PM) { 1487 ios->power_mode = new_ios->power_mode; 1488 if (bootverbose) 1489 device_printf(sc->dev, "Power mode => %d\n", ios->power_mode); 1490 } 1491 if (cts->ios_valid & MMC_BT) { 1492 ios->timing = new_ios->timing; 1493 if (bootverbose) 1494 device_printf(sc->dev, "Timing => %d\n", ios->timing); 1495 } 1496 if (cts->ios_valid & MMC_BM) { 1497 ios->bus_mode = new_ios->bus_mode; 1498 if (bootverbose) 1499 device_printf(sc->dev, "Bus mode => %d\n", ios->bus_mode); 1500 } 1501 if (cts->ios_valid & MMC_VCCQ) { 1502 ios->vccq = new_ios->vccq; 1503 if (bootverbose) 1504 device_printf(sc->dev, "VCCQ => %d\n", ios->vccq); 1505 res = dwmmc_switch_vccq(sc->dev, NULL); 1506 device_printf(sc->dev, "VCCQ switch result: %d\n", res); 1507 } 1508 1509 return (dwmmc_update_ios(sc->dev, NULL)); 1510 } 1511 1512 static int 1513 dwmmc_cam_request(device_t dev, union ccb *ccb) 1514 { 1515 struct dwmmc_softc *sc; 1516 struct ccb_mmcio *mmcio; 1517 1518 sc = device_get_softc(dev); 1519 mmcio = &ccb->mmcio; 1520 1521 DWMMC_LOCK(sc); 1522 1523 #ifdef DEBUG 1524 if (__predict_false(bootverbose)) { 1525 device_printf(sc->dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1526 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags, 1527 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0, 1528 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0); 1529 } 1530 #endif 1531 if (mmcio->cmd.data != NULL) { 1532 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0) 1533 panic("data->len = %d, data->flags = %d -- something is b0rked", 1534 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags); 1535 } 1536 if (sc->ccb != NULL) { 1537 device_printf(sc->dev, "Controller still has an active command\n"); 1538 return (EBUSY); 1539 } 1540 sc->ccb = ccb; 1541 DWMMC_UNLOCK(sc); 1542 dwmmc_request(sc->dev, NULL, NULL); 1543 1544 return (0); 1545 } 1546 #endif /* MMCCAM */ 1547 1548 static device_method_t dwmmc_methods[] = { 1549 /* Bus interface */ 1550 DEVMETHOD(bus_read_ivar, dwmmc_read_ivar), 1551 DEVMETHOD(bus_write_ivar, dwmmc_write_ivar), 1552 1553 #ifndef MMCCAM 1554 /* mmcbr_if */ 1555 DEVMETHOD(mmcbr_update_ios, dwmmc_update_ios), 1556 DEVMETHOD(mmcbr_request, dwmmc_request), 1557 DEVMETHOD(mmcbr_get_ro, dwmmc_get_ro), 1558 DEVMETHOD(mmcbr_acquire_host, dwmmc_acquire_host), 1559 DEVMETHOD(mmcbr_release_host, dwmmc_release_host), 1560 #endif 1561 1562 #ifdef MMCCAM 1563 /* MMCCAM interface */ 1564 DEVMETHOD(mmc_sim_get_tran_settings, dwmmc_get_tran_settings), 1565 DEVMETHOD(mmc_sim_set_tran_settings, dwmmc_set_tran_settings), 1566 DEVMETHOD(mmc_sim_cam_request, dwmmc_cam_request), 1567 1568 DEVMETHOD(bus_add_child, bus_generic_add_child), 1569 #endif 1570 1571 DEVMETHOD_END 1572 }; 1573 1574 DEFINE_CLASS_0(dwmmc, dwmmc_driver, dwmmc_methods, 1575 sizeof(struct dwmmc_softc)); 1576