1 /*- 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_QP_H 29 #define MLX5_QP_H 30 31 #include <dev/mlx5/device.h> 32 #include <dev/mlx5/driver.h> 33 #include <dev/mlx5/mlx5_ifc.h> 34 35 #define MLX5_INVALID_LKEY 0x100 36 #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5) 37 #define MLX5_DIF_SIZE 8 38 #define MLX5_STRIDE_BLOCK_OP 0x400 39 #define MLX5_CPY_GRD_MASK 0xc0 40 #define MLX5_CPY_APP_MASK 0x30 41 #define MLX5_CPY_REF_MASK 0x0f 42 #define MLX5_BSF_INC_REFTAG (1 << 6) 43 #define MLX5_BSF_INL_VALID (1 << 15) 44 #define MLX5_BSF_REFRESH_DIF (1 << 14) 45 #define MLX5_BSF_REPEAT_BLOCK (1 << 7) 46 #define MLX5_BSF_APPTAG_ESCAPE 0x1 47 #define MLX5_BSF_APPREF_ESCAPE 0x2 48 49 enum mlx5_qp_optpar { 50 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 51 MLX5_QP_OPTPAR_RRE = 1 << 1, 52 MLX5_QP_OPTPAR_RAE = 1 << 2, 53 MLX5_QP_OPTPAR_RWE = 1 << 3, 54 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4, 55 MLX5_QP_OPTPAR_Q_KEY = 1 << 5, 56 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 57 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 58 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8, 59 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9, 60 MLX5_QP_OPTPAR_PM_STATE = 1 << 10, 61 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12, 62 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13, 63 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 64 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16, 65 MLX5_QP_OPTPAR_SRQN = 1 << 18, 66 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19, 67 MLX5_QP_OPTPAR_DC_HS = 1 << 20, 68 MLX5_QP_OPTPAR_DC_KEY = 1 << 21, 69 }; 70 71 enum mlx5_qp_state { 72 MLX5_QP_STATE_RST = 0, 73 MLX5_QP_STATE_INIT = 1, 74 MLX5_QP_STATE_RTR = 2, 75 MLX5_QP_STATE_RTS = 3, 76 MLX5_QP_STATE_SQER = 4, 77 MLX5_QP_STATE_SQD = 5, 78 MLX5_QP_STATE_ERR = 6, 79 MLX5_QP_STATE_SQ_DRAINING = 7, 80 MLX5_QP_STATE_SUSPENDED = 9, 81 MLX5_QP_NUM_STATE 82 }; 83 84 enum { 85 MLX5_QP_ST_RC = 0x0, 86 MLX5_QP_ST_UC = 0x1, 87 MLX5_QP_ST_UD = 0x2, 88 MLX5_QP_ST_XRC = 0x3, 89 MLX5_QP_ST_MLX = 0x4, 90 MLX5_QP_ST_DCI = 0x5, 91 MLX5_QP_ST_DCT = 0x6, 92 MLX5_QP_ST_QP0 = 0x7, 93 MLX5_QP_ST_QP1 = 0x8, 94 MLX5_QP_ST_RAW_ETHERTYPE = 0x9, 95 MLX5_QP_ST_RAW_IPV6 = 0xa, 96 MLX5_QP_ST_SNIFFER = 0xb, 97 MLX5_QP_ST_SYNC_UMR = 0xe, 98 MLX5_QP_ST_PTP_1588 = 0xd, 99 MLX5_QP_ST_REG_UMR = 0xc, 100 MLX5_QP_ST_SW_CNAK = 0x10, 101 MLX5_QP_ST_MAX 102 }; 103 104 enum { 105 MLX5_NON_ZERO_RQ = 0 << 24, 106 MLX5_SRQ_RQ = 1 << 24, 107 MLX5_CRQ_RQ = 2 << 24, 108 MLX5_ZERO_LEN_RQ = 3 << 24 109 }; 110 111 enum { 112 /* params1 */ 113 MLX5_QP_BIT_SRE = 1 << 15, 114 MLX5_QP_BIT_SWE = 1 << 14, 115 MLX5_QP_BIT_SAE = 1 << 13, 116 /* params2 */ 117 MLX5_QP_BIT_RRE = 1 << 15, 118 MLX5_QP_BIT_RWE = 1 << 14, 119 MLX5_QP_BIT_RAE = 1 << 13, 120 MLX5_QP_BIT_RIC = 1 << 4, 121 MLX5_QP_BIT_COLL_SYNC_RQ = 1 << 2, 122 MLX5_QP_BIT_COLL_SYNC_SQ = 1 << 1, 123 MLX5_QP_BIT_COLL_MASTER = 1 << 0 124 }; 125 126 enum { 127 MLX5_DCT_BIT_RRE = 1 << 19, 128 MLX5_DCT_BIT_RWE = 1 << 18, 129 MLX5_DCT_BIT_RAE = 1 << 17, 130 }; 131 132 enum { 133 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2, 134 MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2, 135 MLX5_WQE_CTRL_SOLICITED = 1 << 1, 136 }; 137 138 enum { 139 MLX5_SEND_WQE_DS = 16, 140 MLX5_SEND_WQE_BB = 64, 141 }; 142 143 #define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS) 144 145 enum { 146 MLX5_SEND_WQE_MAX_WQEBBS = 16, 147 }; 148 149 enum { 150 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27, 151 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, 152 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29, 153 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30, 154 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31 155 }; 156 157 enum { 158 MLX5_FENCE_MODE_NONE = 0 << 5, 159 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5, 160 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5, 161 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5, 162 }; 163 164 enum { 165 MLX5_QP_DRAIN_SIGERR = 1 << 26, 166 MLX5_QP_LAT_SENSITIVE = 1 << 28, 167 MLX5_QP_BLOCK_MCAST = 1 << 30, 168 MLX5_QP_ENABLE_SIG = 1 << 31, 169 }; 170 171 enum { 172 MLX5_RCV_DBR = 0, 173 MLX5_SND_DBR = 1, 174 }; 175 176 enum { 177 MLX5_FLAGS_INLINE = 1<<7, 178 MLX5_FLAGS_CHECK_FREE = 1<<5, 179 }; 180 181 struct mlx5_wqe_fmr_seg { 182 __be32 flags; 183 __be32 mem_key; 184 __be64 buf_list; 185 __be64 start_addr; 186 __be64 reg_len; 187 __be32 offset; 188 __be32 page_size; 189 u32 reserved[2]; 190 }; 191 192 struct mlx5_wqe_ctrl_seg { 193 __be32 opmod_idx_opcode; 194 __be32 qpn_ds; 195 u8 signature; 196 u8 rsvd[2]; 197 u8 fm_ce_se; 198 __be32 imm; 199 }; 200 201 enum { 202 MLX5_MLX_FLAG_MASK_VL15 = 0x40, 203 MLX5_MLX_FLAG_MASK_SLR = 0x20, 204 MLX5_MLX_FLAG_MASK_ICRC = 0x8, 205 MLX5_MLX_FLAG_MASK_FL = 4 206 }; 207 208 struct mlx5_mlx_seg { 209 __be32 rsvd0; 210 u8 flags; 211 u8 stat_rate_sl; 212 u8 rsvd1[8]; 213 __be16 dlid; 214 }; 215 216 enum { 217 MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4, 218 MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5, 219 MLX5_ETH_WQE_L3_CSUM = 1 << 6, 220 MLX5_ETH_WQE_L4_CSUM = 1 << 7, 221 }; 222 223 enum { 224 MLX5_ETH_WQE_SWP_OUTER_L3_TYPE = 1 << 0, 225 MLX5_ETH_WQE_SWP_OUTER_L4_TYPE = 1 << 1, 226 MLX5_ETH_WQE_SWP_INNER_L3_TYPE = 1 << 4, 227 MLX5_ETH_WQE_SWP_INNER_L4_TYPE = 1 << 5, 228 }; 229 230 struct mlx5_wqe_eth_seg { 231 u8 swp_outer_l4_offset; 232 u8 swp_outer_l3_offset; 233 u8 swp_inner_l4_offset; 234 u8 swp_inner_l3_offset; 235 u8 cs_flags; 236 u8 swp_flags; 237 __be16 mss; 238 __be32 rsvd2; 239 __be16 inline_hdr_sz; 240 u8 inline_hdr_start[2]; 241 }; 242 243 struct mlx5_wqe_xrc_seg { 244 __be32 xrc_srqn; 245 u8 rsvd[12]; 246 }; 247 248 struct mlx5_wqe_masked_atomic_seg { 249 __be64 swap_add; 250 __be64 compare; 251 __be64 swap_add_mask; 252 __be64 compare_mask; 253 }; 254 255 struct mlx5_av { 256 union { 257 struct { 258 __be32 qkey; 259 __be32 reserved; 260 } qkey; 261 __be64 dc_key; 262 } key; 263 __be32 dqp_dct; 264 u8 stat_rate_sl; 265 u8 fl_mlid; 266 union { 267 __be16 rlid; 268 __be16 udp_sport; 269 }; 270 u8 reserved0[4]; 271 u8 rmac[6]; 272 u8 tclass; 273 u8 hop_limit; 274 __be32 grh_gid_fl; 275 u8 rgid[16]; 276 }; 277 278 struct mlx5_wqe_datagram_seg { 279 struct mlx5_av av; 280 }; 281 282 struct mlx5_wqe_raddr_seg { 283 __be64 raddr; 284 __be32 rkey; 285 u32 reserved; 286 }; 287 288 struct mlx5_wqe_atomic_seg { 289 __be64 swap_add; 290 __be64 compare; 291 }; 292 293 struct mlx5_wqe_data_seg { 294 __be32 byte_count; 295 __be32 lkey; 296 __be64 addr; 297 }; 298 299 struct mlx5_wqe_umr_ctrl_seg { 300 u8 flags; 301 u8 rsvd0[3]; 302 __be16 klm_octowords; 303 __be16 bsf_octowords; 304 __be64 mkey_mask; 305 u8 rsvd1[32]; 306 }; 307 308 struct mlx5_seg_set_psv { 309 __be32 psv_num; 310 __be16 syndrome; 311 __be16 status; 312 __be32 transient_sig; 313 __be32 ref_tag; 314 }; 315 316 struct mlx5_seg_get_psv { 317 u8 rsvd[19]; 318 u8 num_psv; 319 __be32 l_key; 320 __be64 va; 321 __be32 psv_index[4]; 322 }; 323 324 struct mlx5_seg_check_psv { 325 u8 rsvd0[2]; 326 __be16 err_coalescing_op; 327 u8 rsvd1[2]; 328 __be16 xport_err_op; 329 u8 rsvd2[2]; 330 __be16 xport_err_mask; 331 u8 rsvd3[7]; 332 u8 num_psv; 333 __be32 l_key; 334 __be64 va; 335 __be32 psv_index[4]; 336 }; 337 338 struct mlx5_rwqe_sig { 339 u8 rsvd0[4]; 340 u8 signature; 341 u8 rsvd1[11]; 342 }; 343 344 struct mlx5_wqe_signature_seg { 345 u8 rsvd0[4]; 346 u8 signature; 347 u8 rsvd1[11]; 348 }; 349 350 struct mlx5_wqe_inline_seg { 351 __be32 byte_count; 352 }; 353 354 enum mlx5_sig_type { 355 MLX5_DIF_CRC = 0x1, 356 MLX5_DIF_IPCS = 0x2, 357 }; 358 359 struct mlx5_bsf_inl { 360 __be16 vld_refresh; 361 __be16 dif_apptag; 362 __be32 dif_reftag; 363 u8 sig_type; 364 u8 rp_inv_seed; 365 u8 rsvd[3]; 366 u8 dif_inc_ref_guard_check; 367 __be16 dif_app_bitmask_check; 368 }; 369 370 struct mlx5_bsf { 371 struct mlx5_bsf_basic { 372 u8 bsf_size_sbs; 373 u8 check_byte_mask; 374 union { 375 u8 copy_byte_mask; 376 u8 bs_selector; 377 u8 rsvd_wflags; 378 } wire; 379 union { 380 u8 bs_selector; 381 u8 rsvd_mflags; 382 } mem; 383 __be32 raw_data_size; 384 __be32 w_bfs_psv; 385 __be32 m_bfs_psv; 386 } basic; 387 struct mlx5_bsf_ext { 388 __be32 t_init_gen_pro_size; 389 __be32 rsvd_epi_size; 390 __be32 w_tfs_psv; 391 __be32 m_tfs_psv; 392 } ext; 393 struct mlx5_bsf_inl w_inl; 394 struct mlx5_bsf_inl m_inl; 395 }; 396 397 struct mlx5_klm { 398 __be32 bcount; 399 __be32 key; 400 __be64 va; 401 }; 402 403 struct mlx5_stride_block_entry { 404 __be16 stride; 405 __be16 bcount; 406 __be32 key; 407 __be64 va; 408 }; 409 410 struct mlx5_stride_block_ctrl_seg { 411 __be32 bcount_per_cycle; 412 __be32 op; 413 __be32 repeat_count; 414 u16 rsvd; 415 __be16 num_entries; 416 }; 417 418 struct mlx5_core_qp { 419 struct mlx5_core_rsc_common common; /* must be first */ 420 void (*event) (struct mlx5_core_qp *, int); 421 int qpn; 422 struct mlx5_rsc_debug *dbg; 423 int pid; 424 }; 425 426 struct mlx5_qp_path { 427 u8 fl_free_ar; 428 u8 rsvd3; 429 __be16 pkey_index; 430 u8 rsvd0; 431 u8 grh_mlid; 432 __be16 rlid; 433 u8 ackto_lt; 434 u8 mgid_index; 435 u8 static_rate; 436 u8 hop_limit; 437 __be32 tclass_flowlabel; 438 union { 439 u8 rgid[16]; 440 u8 rip[16]; 441 }; 442 u8 f_dscp_ecn_prio; 443 u8 ecn_dscp; 444 __be16 udp_sport; 445 u8 dci_cfi_prio_sl; 446 u8 port; 447 u8 rmac[6]; 448 }; 449 450 struct mlx5_qp_context { 451 __be32 flags; 452 __be32 flags_pd; 453 u8 mtu_msgmax; 454 u8 rq_size_stride; 455 __be16 sq_crq_size; 456 __be32 qp_counter_set_usr_page; 457 __be32 wire_qpn; 458 __be32 log_pg_sz_remote_qpn; 459 struct mlx5_qp_path pri_path; 460 struct mlx5_qp_path alt_path; 461 __be32 params1; 462 u8 reserved2[4]; 463 __be32 next_send_psn; 464 __be32 cqn_send; 465 u8 reserved3[8]; 466 __be32 last_acked_psn; 467 __be32 ssn; 468 __be32 params2; 469 __be32 rnr_nextrecvpsn; 470 __be32 xrcd; 471 __be32 cqn_recv; 472 __be64 db_rec_addr; 473 __be32 qkey; 474 __be32 rq_type_srqn; 475 __be32 rmsn; 476 __be16 hw_sq_wqe_counter; 477 __be16 sw_sq_wqe_counter; 478 __be16 hw_rcyclic_byte_counter; 479 __be16 hw_rq_counter; 480 __be16 sw_rcyclic_byte_counter; 481 __be16 sw_rq_counter; 482 u8 rsvd0[5]; 483 u8 cgs; 484 u8 cs_req; 485 u8 cs_res; 486 __be64 dc_access_key; 487 u8 rsvd1[24]; 488 }; 489 490 struct mlx5_create_qp_mbox_in { 491 struct mlx5_inbox_hdr hdr; 492 __be32 input_qpn; 493 u8 rsvd0[4]; 494 __be32 opt_param_mask; 495 u8 rsvd1[4]; 496 struct mlx5_qp_context ctx; 497 u8 rsvd3[16]; 498 __be64 pas[0]; 499 }; 500 501 struct mlx5_dct_context { 502 u8 state; 503 u8 rsvd0[7]; 504 __be32 cqn; 505 __be32 flags; 506 u8 rsvd1; 507 u8 cs_res; 508 u8 min_rnr; 509 u8 rsvd2; 510 __be32 srqn; 511 __be32 pdn; 512 __be32 tclass_flow_label; 513 __be64 access_key; 514 u8 mtu; 515 u8 port; 516 __be16 pkey_index; 517 u8 rsvd4; 518 u8 mgid_index; 519 u8 rsvd5; 520 u8 hop_limit; 521 __be32 access_violations; 522 u8 rsvd[12]; 523 }; 524 525 struct mlx5_create_dct_mbox_in { 526 struct mlx5_inbox_hdr hdr; 527 u8 rsvd0[8]; 528 struct mlx5_dct_context context; 529 u8 rsvd[48]; 530 }; 531 532 struct mlx5_create_dct_mbox_out { 533 struct mlx5_outbox_hdr hdr; 534 __be32 dctn; 535 u8 rsvd0[4]; 536 }; 537 538 struct mlx5_destroy_dct_mbox_in { 539 struct mlx5_inbox_hdr hdr; 540 __be32 dctn; 541 u8 rsvd0[4]; 542 }; 543 544 struct mlx5_destroy_dct_mbox_out { 545 struct mlx5_outbox_hdr hdr; 546 u8 rsvd0[8]; 547 }; 548 549 struct mlx5_drain_dct_mbox_in { 550 struct mlx5_inbox_hdr hdr; 551 __be32 dctn; 552 u8 rsvd0[4]; 553 }; 554 555 struct mlx5_drain_dct_mbox_out { 556 struct mlx5_outbox_hdr hdr; 557 u8 rsvd0[8]; 558 }; 559 560 struct mlx5_create_qp_mbox_out { 561 struct mlx5_outbox_hdr hdr; 562 __be32 qpn; 563 u8 rsvd0[4]; 564 }; 565 566 struct mlx5_destroy_qp_mbox_in { 567 struct mlx5_inbox_hdr hdr; 568 __be32 qpn; 569 u8 rsvd0[4]; 570 }; 571 572 struct mlx5_destroy_qp_mbox_out { 573 struct mlx5_outbox_hdr hdr; 574 u8 rsvd0[8]; 575 }; 576 577 struct mlx5_modify_qp_mbox_in { 578 struct mlx5_inbox_hdr hdr; 579 __be32 qpn; 580 u8 rsvd1[4]; 581 __be32 optparam; 582 u8 rsvd0[4]; 583 struct mlx5_qp_context ctx; 584 u8 rsvd2[16]; 585 }; 586 587 struct mlx5_modify_qp_mbox_out { 588 struct mlx5_outbox_hdr hdr; 589 u8 rsvd0[8]; 590 }; 591 592 struct mlx5_query_qp_mbox_in { 593 struct mlx5_inbox_hdr hdr; 594 __be32 qpn; 595 u8 rsvd[4]; 596 }; 597 598 struct mlx5_query_qp_mbox_out { 599 struct mlx5_outbox_hdr hdr; 600 u8 rsvd1[8]; 601 __be32 optparam; 602 u8 rsvd0[4]; 603 struct mlx5_qp_context ctx; 604 u8 rsvd2[16]; 605 __be64 pas[0]; 606 }; 607 608 struct mlx5_query_dct_mbox_in { 609 struct mlx5_inbox_hdr hdr; 610 __be32 dctn; 611 u8 rsvd[4]; 612 }; 613 614 struct mlx5_query_dct_mbox_out { 615 struct mlx5_outbox_hdr hdr; 616 u8 rsvd0[8]; 617 struct mlx5_dct_context ctx; 618 u8 rsvd1[48]; 619 }; 620 621 struct mlx5_arm_dct_mbox_in { 622 struct mlx5_inbox_hdr hdr; 623 __be32 dctn; 624 u8 rsvd[4]; 625 }; 626 627 struct mlx5_arm_dct_mbox_out { 628 struct mlx5_outbox_hdr hdr; 629 u8 rsvd0[8]; 630 }; 631 632 struct mlx5_conf_sqp_mbox_in { 633 struct mlx5_inbox_hdr hdr; 634 __be32 qpn; 635 u8 rsvd[3]; 636 u8 type; 637 }; 638 639 struct mlx5_conf_sqp_mbox_out { 640 struct mlx5_outbox_hdr hdr; 641 u8 rsvd[8]; 642 }; 643 644 static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn) 645 { 646 return radix_tree_lookup(&dev->priv.qp_table.tree, qpn); 647 } 648 649 static inline struct mlx5_core_mr *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key) 650 { 651 return radix_tree_lookup(&dev->priv.mr_table.tree, key); 652 } 653 654 int mlx5_core_create_qp(struct mlx5_core_dev *dev, 655 struct mlx5_core_qp *qp, 656 struct mlx5_create_qp_mbox_in *in, 657 int inlen); 658 int mlx5_core_qp_modify(struct mlx5_core_dev *dev, u16 operation, 659 struct mlx5_modify_qp_mbox_in *in, int sqd_event, 660 struct mlx5_core_qp *qp); 661 int mlx5_core_destroy_qp(struct mlx5_core_dev *dev, 662 struct mlx5_core_qp *qp); 663 int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp, 664 struct mlx5_query_qp_mbox_out *out, int outlen); 665 int mlx5_core_dct_query(struct mlx5_core_dev *dev, struct mlx5_core_dct *dct, 666 struct mlx5_query_dct_mbox_out *out); 667 int mlx5_core_arm_dct(struct mlx5_core_dev *dev, struct mlx5_core_dct *dct); 668 669 int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn); 670 int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn); 671 int mlx5_core_create_dct(struct mlx5_core_dev *dev, 672 struct mlx5_core_dct *dct, 673 struct mlx5_create_dct_mbox_in *in); 674 int mlx5_core_destroy_dct(struct mlx5_core_dev *dev, 675 struct mlx5_core_dct *dct); 676 int mlx5_core_create_rq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen, 677 struct mlx5_core_qp *rq); 678 void mlx5_core_destroy_rq_tracked(struct mlx5_core_dev *dev, 679 struct mlx5_core_qp *rq); 680 int mlx5_core_create_sq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen, 681 struct mlx5_core_qp *sq); 682 void mlx5_core_destroy_sq_tracked(struct mlx5_core_dev *dev, 683 struct mlx5_core_qp *sq); 684 void mlx5_init_qp_table(struct mlx5_core_dev *dev); 685 void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev); 686 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 687 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 688 689 static inline const char *mlx5_qp_type_str(int type) 690 { 691 switch (type) { 692 case MLX5_QP_ST_RC: return "RC"; 693 case MLX5_QP_ST_UC: return "C"; 694 case MLX5_QP_ST_UD: return "UD"; 695 case MLX5_QP_ST_XRC: return "XRC"; 696 case MLX5_QP_ST_MLX: return "MLX"; 697 case MLX5_QP_ST_DCI: return "DCI"; 698 case MLX5_QP_ST_QP0: return "QP0"; 699 case MLX5_QP_ST_QP1: return "QP1"; 700 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE"; 701 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6"; 702 case MLX5_QP_ST_SNIFFER: return "SNIFFER"; 703 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR"; 704 case MLX5_QP_ST_PTP_1588: return "PTP_1588"; 705 case MLX5_QP_ST_REG_UMR: return "REG_UMR"; 706 case MLX5_QP_ST_SW_CNAK: return "DC_CNAK"; 707 default: return "Invalid transport type"; 708 } 709 } 710 711 static inline const char *mlx5_qp_state_str(int state) 712 { 713 switch (state) { 714 case MLX5_QP_STATE_RST: 715 return "RST"; 716 case MLX5_QP_STATE_INIT: 717 return "INIT"; 718 case MLX5_QP_STATE_RTR: 719 return "RTR"; 720 case MLX5_QP_STATE_RTS: 721 return "RTS"; 722 case MLX5_QP_STATE_SQER: 723 return "SQER"; 724 case MLX5_QP_STATE_SQD: 725 return "SQD"; 726 case MLX5_QP_STATE_ERR: 727 return "ERR"; 728 case MLX5_QP_STATE_SQ_DRAINING: 729 return "SQ_DRAINING"; 730 case MLX5_QP_STATE_SUSPENDED: 731 return "SUSPENDED"; 732 default: return "Invalid QP state"; 733 } 734 } 735 736 #endif /* MLX5_QP_H */ 737