1 /*- 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_QP_H 29 #define MLX5_QP_H 30 31 #include <dev/mlx5/device.h> 32 #include <dev/mlx5/driver.h> 33 #include <dev/mlx5/mlx5_ifc.h> 34 35 #define MLX5_INVALID_LKEY 0x100 36 #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5) 37 #define MLX5_DIF_SIZE 8 38 #define MLX5_STRIDE_BLOCK_OP 0x400 39 #define MLX5_CPY_GRD_MASK 0xc0 40 #define MLX5_CPY_APP_MASK 0x30 41 #define MLX5_CPY_REF_MASK 0x0f 42 #define MLX5_BSF_INC_REFTAG (1 << 6) 43 #define MLX5_BSF_INL_VALID (1 << 15) 44 #define MLX5_BSF_REFRESH_DIF (1 << 14) 45 #define MLX5_BSF_REPEAT_BLOCK (1 << 7) 46 #define MLX5_BSF_APPTAG_ESCAPE 0x1 47 #define MLX5_BSF_APPREF_ESCAPE 0x2 48 49 enum mlx5_qp_optpar { 50 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 51 MLX5_QP_OPTPAR_RRE = 1 << 1, 52 MLX5_QP_OPTPAR_RAE = 1 << 2, 53 MLX5_QP_OPTPAR_RWE = 1 << 3, 54 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4, 55 MLX5_QP_OPTPAR_Q_KEY = 1 << 5, 56 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 57 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 58 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8, 59 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9, 60 MLX5_QP_OPTPAR_PM_STATE = 1 << 10, 61 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12, 62 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13, 63 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 64 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16, 65 MLX5_QP_OPTPAR_SRQN = 1 << 18, 66 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19, 67 MLX5_QP_OPTPAR_DC_HS = 1 << 20, 68 MLX5_QP_OPTPAR_DC_KEY = 1 << 21, 69 }; 70 71 enum mlx5_qp_state { 72 MLX5_QP_STATE_RST = 0, 73 MLX5_QP_STATE_INIT = 1, 74 MLX5_QP_STATE_RTR = 2, 75 MLX5_QP_STATE_RTS = 3, 76 MLX5_QP_STATE_SQER = 4, 77 MLX5_QP_STATE_SQD = 5, 78 MLX5_QP_STATE_ERR = 6, 79 MLX5_QP_STATE_SQ_DRAINING = 7, 80 MLX5_QP_STATE_SUSPENDED = 9, 81 MLX5_QP_NUM_STATE 82 }; 83 84 enum { 85 MLX5_QP_ST_RC = 0x0, 86 MLX5_QP_ST_UC = 0x1, 87 MLX5_QP_ST_UD = 0x2, 88 MLX5_QP_ST_XRC = 0x3, 89 MLX5_QP_ST_MLX = 0x4, 90 MLX5_QP_ST_DCI = 0x5, 91 MLX5_QP_ST_DCT = 0x6, 92 MLX5_QP_ST_QP0 = 0x7, 93 MLX5_QP_ST_QP1 = 0x8, 94 MLX5_QP_ST_RAW_ETHERTYPE = 0x9, 95 MLX5_QP_ST_RAW_IPV6 = 0xa, 96 MLX5_QP_ST_SNIFFER = 0xb, 97 MLX5_QP_ST_SYNC_UMR = 0xe, 98 MLX5_QP_ST_PTP_1588 = 0xd, 99 MLX5_QP_ST_REG_UMR = 0xc, 100 MLX5_QP_ST_SW_CNAK = 0x10, 101 MLX5_QP_ST_MAX 102 }; 103 104 enum { 105 MLX5_NON_ZERO_RQ = 0 << 24, 106 MLX5_SRQ_RQ = 1 << 24, 107 MLX5_CRQ_RQ = 2 << 24, 108 MLX5_ZERO_LEN_RQ = 3 << 24 109 }; 110 111 enum { 112 /* params1 */ 113 MLX5_QP_BIT_SRE = 1 << 15, 114 MLX5_QP_BIT_SWE = 1 << 14, 115 MLX5_QP_BIT_SAE = 1 << 13, 116 /* params2 */ 117 MLX5_QP_BIT_RRE = 1 << 15, 118 MLX5_QP_BIT_RWE = 1 << 14, 119 MLX5_QP_BIT_RAE = 1 << 13, 120 MLX5_QP_BIT_RIC = 1 << 4, 121 MLX5_QP_BIT_COLL_SYNC_RQ = 1 << 2, 122 MLX5_QP_BIT_COLL_SYNC_SQ = 1 << 1, 123 MLX5_QP_BIT_COLL_MASTER = 1 << 0 124 }; 125 126 enum { 127 MLX5_DCT_BIT_RRE = 1 << 19, 128 MLX5_DCT_BIT_RWE = 1 << 18, 129 MLX5_DCT_BIT_RAE = 1 << 17, 130 }; 131 132 enum { 133 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2, 134 MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2, 135 MLX5_WQE_CTRL_SOLICITED = 1 << 1, 136 }; 137 138 enum { 139 MLX5_SEND_WQE_DS = 16, 140 MLX5_SEND_WQE_BB = 64, 141 }; 142 143 #define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS) 144 145 enum { 146 MLX5_SEND_WQE_MAX_WQEBBS = 16, 147 }; 148 149 enum { 150 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27, 151 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, 152 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29, 153 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30, 154 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31 155 }; 156 157 enum { 158 MLX5_FENCE_MODE_NONE = 0 << 5, 159 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5, 160 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5, 161 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5, 162 }; 163 164 enum { 165 MLX5_QP_DRAIN_SIGERR = 1 << 26, 166 MLX5_QP_LAT_SENSITIVE = 1 << 28, 167 MLX5_QP_BLOCK_MCAST = 1 << 30, 168 MLX5_QP_ENABLE_SIG = 1 << 31, 169 }; 170 171 enum { 172 MLX5_RCV_DBR = 0, 173 MLX5_SND_DBR = 1, 174 }; 175 176 enum { 177 MLX5_FLAGS_INLINE = 1<<7, 178 MLX5_FLAGS_CHECK_FREE = 1<<5, 179 }; 180 181 struct mlx5_wqe_fmr_seg { 182 __be32 flags; 183 __be32 mem_key; 184 __be64 buf_list; 185 __be64 start_addr; 186 __be64 reg_len; 187 __be32 offset; 188 __be32 page_size; 189 u32 reserved[2]; 190 }; 191 192 struct mlx5_wqe_ctrl_seg { 193 __be32 opmod_idx_opcode; 194 __be32 qpn_ds; 195 u8 signature; 196 u8 rsvd[2]; 197 u8 fm_ce_se; 198 __be32 imm; 199 }; 200 201 enum { 202 MLX5_MLX_FLAG_MASK_VL15 = 0x40, 203 MLX5_MLX_FLAG_MASK_SLR = 0x20, 204 MLX5_MLX_FLAG_MASK_ICRC = 0x8, 205 MLX5_MLX_FLAG_MASK_FL = 4 206 }; 207 208 struct mlx5_mlx_seg { 209 __be32 rsvd0; 210 u8 flags; 211 u8 stat_rate_sl; 212 u8 rsvd1[8]; 213 __be16 dlid; 214 }; 215 216 enum { 217 MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4, 218 MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5, 219 MLX5_ETH_WQE_L3_CSUM = 1 << 6, 220 MLX5_ETH_WQE_L4_CSUM = 1 << 7, 221 }; 222 223 struct mlx5_wqe_eth_seg { 224 u8 rsvd0[4]; 225 u8 cs_flags; 226 u8 rsvd1; 227 __be16 mss; 228 __be32 rsvd2; 229 __be16 inline_hdr_sz; 230 u8 inline_hdr_start[2]; 231 }; 232 233 struct mlx5_wqe_xrc_seg { 234 __be32 xrc_srqn; 235 u8 rsvd[12]; 236 }; 237 238 struct mlx5_wqe_masked_atomic_seg { 239 __be64 swap_add; 240 __be64 compare; 241 __be64 swap_add_mask; 242 __be64 compare_mask; 243 }; 244 245 struct mlx5_av { 246 union { 247 struct { 248 __be32 qkey; 249 __be32 reserved; 250 } qkey; 251 __be64 dc_key; 252 } key; 253 __be32 dqp_dct; 254 u8 stat_rate_sl; 255 u8 fl_mlid; 256 union { 257 __be16 rlid; 258 __be16 udp_sport; 259 }; 260 u8 reserved0[4]; 261 u8 rmac[6]; 262 u8 tclass; 263 u8 hop_limit; 264 __be32 grh_gid_fl; 265 u8 rgid[16]; 266 }; 267 268 struct mlx5_wqe_datagram_seg { 269 struct mlx5_av av; 270 }; 271 272 struct mlx5_wqe_raddr_seg { 273 __be64 raddr; 274 __be32 rkey; 275 u32 reserved; 276 }; 277 278 struct mlx5_wqe_atomic_seg { 279 __be64 swap_add; 280 __be64 compare; 281 }; 282 283 struct mlx5_wqe_data_seg { 284 __be32 byte_count; 285 __be32 lkey; 286 __be64 addr; 287 }; 288 289 struct mlx5_wqe_umr_ctrl_seg { 290 u8 flags; 291 u8 rsvd0[3]; 292 __be16 klm_octowords; 293 __be16 bsf_octowords; 294 __be64 mkey_mask; 295 u8 rsvd1[32]; 296 }; 297 298 struct mlx5_seg_set_psv { 299 __be32 psv_num; 300 __be16 syndrome; 301 __be16 status; 302 __be32 transient_sig; 303 __be32 ref_tag; 304 }; 305 306 struct mlx5_seg_get_psv { 307 u8 rsvd[19]; 308 u8 num_psv; 309 __be32 l_key; 310 __be64 va; 311 __be32 psv_index[4]; 312 }; 313 314 struct mlx5_seg_check_psv { 315 u8 rsvd0[2]; 316 __be16 err_coalescing_op; 317 u8 rsvd1[2]; 318 __be16 xport_err_op; 319 u8 rsvd2[2]; 320 __be16 xport_err_mask; 321 u8 rsvd3[7]; 322 u8 num_psv; 323 __be32 l_key; 324 __be64 va; 325 __be32 psv_index[4]; 326 }; 327 328 struct mlx5_rwqe_sig { 329 u8 rsvd0[4]; 330 u8 signature; 331 u8 rsvd1[11]; 332 }; 333 334 struct mlx5_wqe_signature_seg { 335 u8 rsvd0[4]; 336 u8 signature; 337 u8 rsvd1[11]; 338 }; 339 340 struct mlx5_wqe_inline_seg { 341 __be32 byte_count; 342 }; 343 344 enum mlx5_sig_type { 345 MLX5_DIF_CRC = 0x1, 346 MLX5_DIF_IPCS = 0x2, 347 }; 348 349 struct mlx5_bsf_inl { 350 __be16 vld_refresh; 351 __be16 dif_apptag; 352 __be32 dif_reftag; 353 u8 sig_type; 354 u8 rp_inv_seed; 355 u8 rsvd[3]; 356 u8 dif_inc_ref_guard_check; 357 __be16 dif_app_bitmask_check; 358 }; 359 360 struct mlx5_bsf { 361 struct mlx5_bsf_basic { 362 u8 bsf_size_sbs; 363 u8 check_byte_mask; 364 union { 365 u8 copy_byte_mask; 366 u8 bs_selector; 367 u8 rsvd_wflags; 368 } wire; 369 union { 370 u8 bs_selector; 371 u8 rsvd_mflags; 372 } mem; 373 __be32 raw_data_size; 374 __be32 w_bfs_psv; 375 __be32 m_bfs_psv; 376 } basic; 377 struct mlx5_bsf_ext { 378 __be32 t_init_gen_pro_size; 379 __be32 rsvd_epi_size; 380 __be32 w_tfs_psv; 381 __be32 m_tfs_psv; 382 } ext; 383 struct mlx5_bsf_inl w_inl; 384 struct mlx5_bsf_inl m_inl; 385 }; 386 387 struct mlx5_klm { 388 __be32 bcount; 389 __be32 key; 390 __be64 va; 391 }; 392 393 struct mlx5_stride_block_entry { 394 __be16 stride; 395 __be16 bcount; 396 __be32 key; 397 __be64 va; 398 }; 399 400 struct mlx5_stride_block_ctrl_seg { 401 __be32 bcount_per_cycle; 402 __be32 op; 403 __be32 repeat_count; 404 u16 rsvd; 405 __be16 num_entries; 406 }; 407 408 struct mlx5_core_qp { 409 struct mlx5_core_rsc_common common; /* must be first */ 410 void (*event) (struct mlx5_core_qp *, int); 411 int qpn; 412 struct mlx5_rsc_debug *dbg; 413 int pid; 414 }; 415 416 struct mlx5_qp_path { 417 u8 fl_free_ar; 418 u8 rsvd3; 419 __be16 pkey_index; 420 u8 rsvd0; 421 u8 grh_mlid; 422 __be16 rlid; 423 u8 ackto_lt; 424 u8 mgid_index; 425 u8 static_rate; 426 u8 hop_limit; 427 __be32 tclass_flowlabel; 428 union { 429 u8 rgid[16]; 430 u8 rip[16]; 431 }; 432 u8 f_dscp_ecn_prio; 433 u8 ecn_dscp; 434 __be16 udp_sport; 435 u8 dci_cfi_prio_sl; 436 u8 port; 437 u8 rmac[6]; 438 }; 439 440 struct mlx5_qp_context { 441 __be32 flags; 442 __be32 flags_pd; 443 u8 mtu_msgmax; 444 u8 rq_size_stride; 445 __be16 sq_crq_size; 446 __be32 qp_counter_set_usr_page; 447 __be32 wire_qpn; 448 __be32 log_pg_sz_remote_qpn; 449 struct mlx5_qp_path pri_path; 450 struct mlx5_qp_path alt_path; 451 __be32 params1; 452 u8 reserved2[4]; 453 __be32 next_send_psn; 454 __be32 cqn_send; 455 u8 reserved3[8]; 456 __be32 last_acked_psn; 457 __be32 ssn; 458 __be32 params2; 459 __be32 rnr_nextrecvpsn; 460 __be32 xrcd; 461 __be32 cqn_recv; 462 __be64 db_rec_addr; 463 __be32 qkey; 464 __be32 rq_type_srqn; 465 __be32 rmsn; 466 __be16 hw_sq_wqe_counter; 467 __be16 sw_sq_wqe_counter; 468 __be16 hw_rcyclic_byte_counter; 469 __be16 hw_rq_counter; 470 __be16 sw_rcyclic_byte_counter; 471 __be16 sw_rq_counter; 472 u8 rsvd0[5]; 473 u8 cgs; 474 u8 cs_req; 475 u8 cs_res; 476 __be64 dc_access_key; 477 u8 rsvd1[24]; 478 }; 479 480 struct mlx5_create_qp_mbox_in { 481 struct mlx5_inbox_hdr hdr; 482 __be32 input_qpn; 483 u8 rsvd0[4]; 484 __be32 opt_param_mask; 485 u8 rsvd1[4]; 486 struct mlx5_qp_context ctx; 487 u8 rsvd3[16]; 488 __be64 pas[0]; 489 }; 490 491 struct mlx5_dct_context { 492 u8 state; 493 u8 rsvd0[7]; 494 __be32 cqn; 495 __be32 flags; 496 u8 rsvd1; 497 u8 cs_res; 498 u8 min_rnr; 499 u8 rsvd2; 500 __be32 srqn; 501 __be32 pdn; 502 __be32 tclass_flow_label; 503 __be64 access_key; 504 u8 mtu; 505 u8 port; 506 __be16 pkey_index; 507 u8 rsvd4; 508 u8 mgid_index; 509 u8 rsvd5; 510 u8 hop_limit; 511 __be32 access_violations; 512 u8 rsvd[12]; 513 }; 514 515 struct mlx5_create_dct_mbox_in { 516 struct mlx5_inbox_hdr hdr; 517 u8 rsvd0[8]; 518 struct mlx5_dct_context context; 519 u8 rsvd[48]; 520 }; 521 522 struct mlx5_create_dct_mbox_out { 523 struct mlx5_outbox_hdr hdr; 524 __be32 dctn; 525 u8 rsvd0[4]; 526 }; 527 528 struct mlx5_destroy_dct_mbox_in { 529 struct mlx5_inbox_hdr hdr; 530 __be32 dctn; 531 u8 rsvd0[4]; 532 }; 533 534 struct mlx5_destroy_dct_mbox_out { 535 struct mlx5_outbox_hdr hdr; 536 u8 rsvd0[8]; 537 }; 538 539 struct mlx5_drain_dct_mbox_in { 540 struct mlx5_inbox_hdr hdr; 541 __be32 dctn; 542 u8 rsvd0[4]; 543 }; 544 545 struct mlx5_drain_dct_mbox_out { 546 struct mlx5_outbox_hdr hdr; 547 u8 rsvd0[8]; 548 }; 549 550 struct mlx5_create_qp_mbox_out { 551 struct mlx5_outbox_hdr hdr; 552 __be32 qpn; 553 u8 rsvd0[4]; 554 }; 555 556 struct mlx5_destroy_qp_mbox_in { 557 struct mlx5_inbox_hdr hdr; 558 __be32 qpn; 559 u8 rsvd0[4]; 560 }; 561 562 struct mlx5_destroy_qp_mbox_out { 563 struct mlx5_outbox_hdr hdr; 564 u8 rsvd0[8]; 565 }; 566 567 struct mlx5_modify_qp_mbox_in { 568 struct mlx5_inbox_hdr hdr; 569 __be32 qpn; 570 u8 rsvd1[4]; 571 __be32 optparam; 572 u8 rsvd0[4]; 573 struct mlx5_qp_context ctx; 574 u8 rsvd2[16]; 575 }; 576 577 struct mlx5_modify_qp_mbox_out { 578 struct mlx5_outbox_hdr hdr; 579 u8 rsvd0[8]; 580 }; 581 582 struct mlx5_query_qp_mbox_in { 583 struct mlx5_inbox_hdr hdr; 584 __be32 qpn; 585 u8 rsvd[4]; 586 }; 587 588 struct mlx5_query_qp_mbox_out { 589 struct mlx5_outbox_hdr hdr; 590 u8 rsvd1[8]; 591 __be32 optparam; 592 u8 rsvd0[4]; 593 struct mlx5_qp_context ctx; 594 u8 rsvd2[16]; 595 __be64 pas[0]; 596 }; 597 598 struct mlx5_query_dct_mbox_in { 599 struct mlx5_inbox_hdr hdr; 600 __be32 dctn; 601 u8 rsvd[4]; 602 }; 603 604 struct mlx5_query_dct_mbox_out { 605 struct mlx5_outbox_hdr hdr; 606 u8 rsvd0[8]; 607 struct mlx5_dct_context ctx; 608 u8 rsvd1[48]; 609 }; 610 611 struct mlx5_arm_dct_mbox_in { 612 struct mlx5_inbox_hdr hdr; 613 __be32 dctn; 614 u8 rsvd[4]; 615 }; 616 617 struct mlx5_arm_dct_mbox_out { 618 struct mlx5_outbox_hdr hdr; 619 u8 rsvd0[8]; 620 }; 621 622 struct mlx5_conf_sqp_mbox_in { 623 struct mlx5_inbox_hdr hdr; 624 __be32 qpn; 625 u8 rsvd[3]; 626 u8 type; 627 }; 628 629 struct mlx5_conf_sqp_mbox_out { 630 struct mlx5_outbox_hdr hdr; 631 u8 rsvd[8]; 632 }; 633 634 static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn) 635 { 636 return radix_tree_lookup(&dev->priv.qp_table.tree, qpn); 637 } 638 639 static inline struct mlx5_core_mr *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key) 640 { 641 return radix_tree_lookup(&dev->priv.mr_table.tree, key); 642 } 643 644 int mlx5_core_create_qp(struct mlx5_core_dev *dev, 645 struct mlx5_core_qp *qp, 646 struct mlx5_create_qp_mbox_in *in, 647 int inlen); 648 int mlx5_core_qp_modify(struct mlx5_core_dev *dev, u16 operation, 649 struct mlx5_modify_qp_mbox_in *in, int sqd_event, 650 struct mlx5_core_qp *qp); 651 int mlx5_core_destroy_qp(struct mlx5_core_dev *dev, 652 struct mlx5_core_qp *qp); 653 int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp, 654 struct mlx5_query_qp_mbox_out *out, int outlen); 655 int mlx5_core_dct_query(struct mlx5_core_dev *dev, struct mlx5_core_dct *dct, 656 struct mlx5_query_dct_mbox_out *out); 657 int mlx5_core_arm_dct(struct mlx5_core_dev *dev, struct mlx5_core_dct *dct); 658 659 int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn); 660 int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn); 661 int mlx5_core_create_dct(struct mlx5_core_dev *dev, 662 struct mlx5_core_dct *dct, 663 struct mlx5_create_dct_mbox_in *in); 664 int mlx5_core_destroy_dct(struct mlx5_core_dev *dev, 665 struct mlx5_core_dct *dct); 666 int mlx5_core_create_rq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen, 667 struct mlx5_core_qp *rq); 668 void mlx5_core_destroy_rq_tracked(struct mlx5_core_dev *dev, 669 struct mlx5_core_qp *rq); 670 int mlx5_core_create_sq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen, 671 struct mlx5_core_qp *sq); 672 void mlx5_core_destroy_sq_tracked(struct mlx5_core_dev *dev, 673 struct mlx5_core_qp *sq); 674 void mlx5_init_qp_table(struct mlx5_core_dev *dev); 675 void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev); 676 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 677 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 678 679 static inline const char *mlx5_qp_type_str(int type) 680 { 681 switch (type) { 682 case MLX5_QP_ST_RC: return "RC"; 683 case MLX5_QP_ST_UC: return "C"; 684 case MLX5_QP_ST_UD: return "UD"; 685 case MLX5_QP_ST_XRC: return "XRC"; 686 case MLX5_QP_ST_MLX: return "MLX"; 687 case MLX5_QP_ST_DCI: return "DCI"; 688 case MLX5_QP_ST_QP0: return "QP0"; 689 case MLX5_QP_ST_QP1: return "QP1"; 690 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE"; 691 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6"; 692 case MLX5_QP_ST_SNIFFER: return "SNIFFER"; 693 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR"; 694 case MLX5_QP_ST_PTP_1588: return "PTP_1588"; 695 case MLX5_QP_ST_REG_UMR: return "REG_UMR"; 696 case MLX5_QP_ST_SW_CNAK: return "DC_CNAK"; 697 default: return "Invalid transport type"; 698 } 699 } 700 701 static inline const char *mlx5_qp_state_str(int state) 702 { 703 switch (state) { 704 case MLX5_QP_STATE_RST: 705 return "RST"; 706 case MLX5_QP_STATE_INIT: 707 return "INIT"; 708 case MLX5_QP_STATE_RTR: 709 return "RTR"; 710 case MLX5_QP_STATE_RTS: 711 return "RTS"; 712 case MLX5_QP_STATE_SQER: 713 return "SQER"; 714 case MLX5_QP_STATE_SQD: 715 return "SQD"; 716 case MLX5_QP_STATE_ERR: 717 return "ERR"; 718 case MLX5_QP_STATE_SQ_DRAINING: 719 return "SQ_DRAINING"; 720 case MLX5_QP_STATE_SUSPENDED: 721 return "SUSPENDED"; 722 default: return "Invalid QP state"; 723 } 724 } 725 726 #endif /* MLX5_QP_H */ 727