1 /*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 #ifndef MLX5_QP_H 27 #define MLX5_QP_H 28 29 #include <dev/mlx5/driver.h> 30 31 #define MLX5_INVALID_LKEY 0x100 32 #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5) 33 #define MLX5_DIF_SIZE 8 34 #define MLX5_STRIDE_BLOCK_OP 0x400 35 #define MLX5_CPY_GRD_MASK 0xc0 36 #define MLX5_CPY_APP_MASK 0x30 37 #define MLX5_CPY_REF_MASK 0x0f 38 #define MLX5_BSF_INC_REFTAG (1 << 6) 39 #define MLX5_BSF_INL_VALID (1 << 15) 40 #define MLX5_BSF_REFRESH_DIF (1 << 14) 41 #define MLX5_BSF_REPEAT_BLOCK (1 << 7) 42 #define MLX5_BSF_APPTAG_ESCAPE 0x1 43 #define MLX5_BSF_APPREF_ESCAPE 0x2 44 #define MLX5_WQE_DS_UNITS 16 45 46 enum mlx5_qp_optpar { 47 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 48 MLX5_QP_OPTPAR_RRE = 1 << 1, 49 MLX5_QP_OPTPAR_RAE = 1 << 2, 50 MLX5_QP_OPTPAR_RWE = 1 << 3, 51 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4, 52 MLX5_QP_OPTPAR_Q_KEY = 1 << 5, 53 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 54 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 55 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8, 56 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9, 57 MLX5_QP_OPTPAR_PM_STATE = 1 << 10, 58 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12, 59 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13, 60 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 61 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16, 62 MLX5_QP_OPTPAR_SRQN = 1 << 18, 63 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19, 64 MLX5_QP_OPTPAR_DC_HS = 1 << 20, 65 MLX5_QP_OPTPAR_DC_KEY = 1 << 21, 66 }; 67 68 enum mlx5_qp_state { 69 MLX5_QP_STATE_RST = 0, 70 MLX5_QP_STATE_INIT = 1, 71 MLX5_QP_STATE_RTR = 2, 72 MLX5_QP_STATE_RTS = 3, 73 MLX5_QP_STATE_SQER = 4, 74 MLX5_QP_STATE_SQD = 5, 75 MLX5_QP_STATE_ERR = 6, 76 MLX5_QP_STATE_SQ_DRAINING = 7, 77 MLX5_QP_STATE_SUSPENDED = 9, 78 MLX5_QP_NUM_STATE, 79 MLX5_QP_STATE, 80 MLX5_QP_STATE_BAD, 81 }; 82 83 enum { 84 MLX5_SQ_STATE_NA = MLX5_SQC_STATE_ERR + 1, 85 MLX5_SQ_NUM_STATE = MLX5_SQ_STATE_NA + 1, 86 MLX5_RQ_STATE_NA = MLX5_RQC_STATE_ERR + 1, 87 MLX5_RQ_NUM_STATE = MLX5_RQ_STATE_NA + 1, 88 }; 89 90 enum { 91 MLX5_QP_ST_RC = 0x0, 92 MLX5_QP_ST_UC = 0x1, 93 MLX5_QP_ST_UD = 0x2, 94 MLX5_QP_ST_XRC = 0x3, 95 MLX5_QP_ST_MLX = 0x4, 96 MLX5_QP_ST_DCI = 0x5, 97 MLX5_QP_ST_DCT = 0x6, 98 MLX5_QP_ST_QP0 = 0x7, 99 MLX5_QP_ST_QP1 = 0x8, 100 MLX5_QP_ST_RAW_ETHERTYPE = 0x9, 101 MLX5_QP_ST_RAW_IPV6 = 0xa, 102 MLX5_QP_ST_SNIFFER = 0xb, 103 MLX5_QP_ST_SYNC_UMR = 0xe, 104 MLX5_QP_ST_PTP_1588 = 0xd, 105 MLX5_QP_ST_REG_UMR = 0xc, 106 MLX5_QP_ST_SW_CNAK = 0x10, 107 MLX5_QP_ST_MAX 108 }; 109 110 enum { 111 MLX5_NON_ZERO_RQ = 0x0, 112 MLX5_SRQ_RQ = 0x1, 113 MLX5_CRQ_RQ = 0x2, 114 MLX5_ZERO_LEN_RQ = 0x3 115 }; 116 117 enum { 118 /* params1 */ 119 MLX5_QP_BIT_SRE = 1 << 15, 120 MLX5_QP_BIT_SWE = 1 << 14, 121 MLX5_QP_BIT_SAE = 1 << 13, 122 /* params2 */ 123 MLX5_QP_BIT_RRE = 1 << 15, 124 MLX5_QP_BIT_RWE = 1 << 14, 125 MLX5_QP_BIT_RAE = 1 << 13, 126 MLX5_QP_BIT_RIC = 1 << 4, 127 MLX5_QP_BIT_COLL_SYNC_RQ = 1 << 2, 128 MLX5_QP_BIT_COLL_SYNC_SQ = 1 << 1, 129 MLX5_QP_BIT_COLL_MASTER = 1 << 0 130 }; 131 132 enum { 133 MLX5_DCT_BIT_RRE = 1 << 19, 134 MLX5_DCT_BIT_RWE = 1 << 18, 135 MLX5_DCT_BIT_RAE = 1 << 17, 136 }; 137 138 enum { 139 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2, 140 MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2, 141 MLX5_WQE_CTRL_SOLICITED = 1 << 1, 142 }; 143 144 #define MLX5_SEND_WQE_DS 16 145 #define MLX5_SEND_WQE_BB 64 146 #define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS) 147 148 enum { 149 MLX5_SEND_WQE_MAX_WQEBBS = 16, 150 }; 151 152 enum { 153 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27, 154 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, 155 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29, 156 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30, 157 MLX5_WQE_FMR_PERM_ATOMIC = 1U << 31 158 }; 159 160 enum { 161 MLX5_FENCE_MODE_NONE = 0 << 5, 162 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5, 163 MLX5_FENCE_MODE_FENCE = 2 << 5, 164 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5, 165 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5, 166 }; 167 168 enum { 169 MLX5_RCV_DBR = 0, 170 MLX5_SND_DBR = 1, 171 }; 172 173 enum { 174 MLX5_FLAGS_INLINE = 1<<7, 175 MLX5_FLAGS_CHECK_FREE = 1<<5, 176 }; 177 178 struct mlx5_wqe_fmr_seg { 179 __be32 flags; 180 __be32 mem_key; 181 __be64 buf_list; 182 __be64 start_addr; 183 __be64 reg_len; 184 __be32 offset; 185 __be32 page_size; 186 u32 reserved[2]; 187 }; 188 189 struct mlx5_wqe_ctrl_seg { 190 __be32 opmod_idx_opcode; 191 __be32 qpn_ds; 192 u8 signature; 193 u8 rsvd[2]; 194 u8 fm_ce_se; 195 __be32 imm; 196 }; 197 198 #define MLX5_WQE_CTRL_DS_MASK 0x3f 199 200 enum { 201 MLX5_MLX_FLAG_MASK_VL15 = 0x40, 202 MLX5_MLX_FLAG_MASK_SLR = 0x20, 203 MLX5_MLX_FLAG_MASK_ICRC = 0x8, 204 MLX5_MLX_FLAG_MASK_FL = 4 205 }; 206 207 struct mlx5_mlx_seg { 208 __be32 rsvd0; 209 u8 flags; 210 u8 stat_rate_sl; 211 u8 rsvd1[8]; 212 __be16 dlid; 213 }; 214 215 enum { 216 MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4, 217 MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5, 218 MLX5_ETH_WQE_L3_CSUM = 1 << 6, 219 MLX5_ETH_WQE_L4_CSUM = 1 << 7, 220 }; 221 222 enum { 223 MLX5_ETH_WQE_SWP_INNER_L3_TYPE = 1 << 0, 224 MLX5_ETH_WQE_SWP_INNER_L4_TYPE = 1 << 1, 225 MLX5_ETH_WQE_SWP_OUTER_L3_TYPE = 1 << 4, 226 MLX5_ETH_WQE_SWP_OUTER_L4_TYPE = 1 << 5, 227 }; 228 229 struct mlx5_wqe_eth_seg { 230 u8 swp_outer_l4_offset; 231 u8 swp_outer_l3_offset; 232 u8 swp_inner_l4_offset; 233 u8 swp_inner_l3_offset; 234 u8 cs_flags; 235 u8 swp_flags; 236 __be16 mss; 237 __be32 rsvd2; 238 union { 239 struct { 240 __be16 inline_hdr_sz; 241 u8 inline_hdr_start[2]; 242 }; 243 struct { 244 __be16 vlan_cmd; 245 __be16 vlan_hdr; 246 }; 247 }; 248 }; 249 250 struct mlx5_wqe_xrc_seg { 251 __be32 xrc_srqn; 252 u8 rsvd[12]; 253 }; 254 255 struct mlx5_wqe_masked_atomic_seg { 256 __be64 swap_add; 257 __be64 compare; 258 __be64 swap_add_mask; 259 __be64 compare_mask; 260 }; 261 262 struct mlx5_av { 263 union { 264 struct { 265 __be32 qkey; 266 __be32 reserved; 267 } qkey; 268 __be64 dc_key; 269 } key; 270 __be32 dqp_dct; 271 u8 stat_rate_sl; 272 u8 fl_mlid; 273 union { 274 __be16 rlid; 275 __be16 udp_sport; 276 }; 277 u8 reserved0[4]; 278 u8 rmac[6]; 279 u8 tclass; 280 u8 hop_limit; 281 __be32 grh_gid_fl; 282 u8 rgid[16]; 283 }; 284 285 struct mlx5_wqe_datagram_seg { 286 struct mlx5_av av; 287 }; 288 289 struct mlx5_wqe_raddr_seg { 290 __be64 raddr; 291 __be32 rkey; 292 u32 reserved; 293 }; 294 295 struct mlx5_wqe_atomic_seg { 296 __be64 swap_add; 297 __be64 compare; 298 }; 299 300 struct mlx5_wqe_data_seg { 301 __be32 byte_count; 302 __be32 lkey; 303 __be64 addr; 304 }; 305 306 struct mlx5_wqe_umr_ctrl_seg { 307 u8 flags; 308 u8 rsvd0[3]; 309 __be16 klm_octowords; 310 __be16 bsf_octowords; 311 __be64 mkey_mask; 312 u8 rsvd1[32]; 313 }; 314 315 struct mlx5_seg_set_psv { 316 __be32 psv_num; 317 __be16 syndrome; 318 __be16 status; 319 __be32 transient_sig; 320 __be32 ref_tag; 321 }; 322 323 struct mlx5_wqe_qos_remap_seg { 324 u8 rsvd0[4]; 325 u8 rsvd1[4]; 326 __be32 qos_handle; 327 __be32 queue_handle; 328 }; 329 330 struct mlx5_seg_get_psv { 331 u8 rsvd[19]; 332 u8 num_psv; 333 __be32 l_key; 334 __be64 va; 335 __be32 psv_index[4]; 336 }; 337 338 struct mlx5_seg_check_psv { 339 u8 rsvd0[2]; 340 __be16 err_coalescing_op; 341 u8 rsvd1[2]; 342 __be16 xport_err_op; 343 u8 rsvd2[2]; 344 __be16 xport_err_mask; 345 u8 rsvd3[7]; 346 u8 num_psv; 347 __be32 l_key; 348 __be64 va; 349 __be32 psv_index[4]; 350 }; 351 352 struct mlx5_rwqe_sig { 353 u8 rsvd0[4]; 354 u8 signature; 355 u8 rsvd1[11]; 356 }; 357 358 struct mlx5_wqe_signature_seg { 359 u8 rsvd0[4]; 360 u8 signature; 361 u8 rsvd1[11]; 362 }; 363 364 struct mlx5_wqe_inline_seg { 365 __be32 byte_count; 366 }; 367 368 enum mlx5_sig_type { 369 MLX5_DIF_CRC = 0x1, 370 MLX5_DIF_IPCS = 0x2, 371 }; 372 373 struct mlx5_bsf_inl { 374 __be16 vld_refresh; 375 __be16 dif_apptag; 376 __be32 dif_reftag; 377 u8 sig_type; 378 u8 rp_inv_seed; 379 u8 rsvd[3]; 380 u8 dif_inc_ref_guard_check; 381 __be16 dif_app_bitmask_check; 382 }; 383 384 struct mlx5_bsf { 385 struct mlx5_bsf_basic { 386 u8 bsf_size_sbs; 387 u8 check_byte_mask; 388 union { 389 u8 copy_byte_mask; 390 u8 bs_selector; 391 u8 rsvd_wflags; 392 } wire; 393 union { 394 u8 bs_selector; 395 u8 rsvd_mflags; 396 } mem; 397 __be32 raw_data_size; 398 __be32 w_bfs_psv; 399 __be32 m_bfs_psv; 400 } basic; 401 struct mlx5_bsf_ext { 402 __be32 t_init_gen_pro_size; 403 __be32 rsvd_epi_size; 404 __be32 w_tfs_psv; 405 __be32 m_tfs_psv; 406 } ext; 407 struct mlx5_bsf_inl w_inl; 408 struct mlx5_bsf_inl m_inl; 409 }; 410 411 struct mlx5_klm { 412 __be32 bcount; 413 __be32 key; 414 __be64 va; 415 }; 416 417 struct mlx5_stride_block_entry { 418 __be16 stride; 419 __be16 bcount; 420 __be32 key; 421 __be64 va; 422 }; 423 424 struct mlx5_stride_block_ctrl_seg { 425 __be32 bcount_per_cycle; 426 __be32 op; 427 __be32 repeat_count; 428 u16 rsvd; 429 __be16 num_entries; 430 }; 431 432 enum mlx5_pagefault_flags { 433 MLX5_PFAULT_REQUESTOR = 1 << 0, 434 MLX5_PFAULT_WRITE = 1 << 1, 435 MLX5_PFAULT_RDMA = 1 << 2, 436 }; 437 438 /* Contains the details of a pagefault. */ 439 struct mlx5_pagefault { 440 u32 bytes_committed; 441 u8 event_subtype; 442 enum mlx5_pagefault_flags flags; 443 union { 444 /* Initiator or send message responder pagefault details. */ 445 struct { 446 /* Received packet size, only valid for responders. */ 447 u32 packet_size; 448 /* 449 * WQE index. Refers to either the send queue or 450 * receive queue, according to event_subtype. 451 */ 452 u16 wqe_index; 453 } wqe; 454 /* RDMA responder pagefault details */ 455 struct { 456 u32 r_key; 457 /* 458 * Received packet size, minimal size page fault 459 * resolution required for forward progress. 460 */ 461 u32 packet_size; 462 u32 rdma_op_len; 463 u64 rdma_va; 464 } rdma; 465 }; 466 }; 467 468 struct mlx5_core_qp { 469 struct mlx5_core_rsc_common common; /* must be first */ 470 void (*event) (struct mlx5_core_qp *, int); 471 int qpn; 472 struct mlx5_rsc_debug *dbg; 473 int pid; 474 u16 uid; 475 }; 476 477 struct mlx5_qp_path { 478 u8 fl_free_ar; 479 u8 rsvd3; 480 __be16 pkey_index; 481 u8 rsvd0; 482 u8 grh_mlid; 483 __be16 rlid; 484 u8 ackto_lt; 485 u8 mgid_index; 486 u8 static_rate; 487 u8 hop_limit; 488 __be32 tclass_flowlabel; 489 union { 490 u8 rgid[16]; 491 u8 rip[16]; 492 }; 493 u8 f_dscp_ecn_prio; 494 u8 ecn_dscp; 495 __be16 udp_sport; 496 u8 dci_cfi_prio_sl; 497 u8 port; 498 u8 rmac[6]; 499 }; 500 501 struct mlx5_qp_context { 502 __be32 flags; 503 __be32 flags_pd; 504 u8 mtu_msgmax; 505 u8 rq_size_stride; 506 __be16 sq_crq_size; 507 __be32 qp_counter_set_usr_page; 508 __be32 wire_qpn; 509 __be32 log_pg_sz_remote_qpn; 510 struct mlx5_qp_path pri_path; 511 struct mlx5_qp_path alt_path; 512 __be32 params1; 513 u8 reserved2[4]; 514 __be32 next_send_psn; 515 __be32 cqn_send; 516 __be32 deth_sqpn; 517 u8 reserved3[4]; 518 __be32 last_acked_psn; 519 __be32 ssn; 520 __be32 params2; 521 __be32 rnr_nextrecvpsn; 522 __be32 xrcd; 523 __be32 cqn_recv; 524 __be64 db_rec_addr; 525 __be32 qkey; 526 __be32 rq_type_srqn; 527 __be32 rmsn; 528 __be16 hw_sq_wqe_counter; 529 __be16 sw_sq_wqe_counter; 530 __be16 hw_rcyclic_byte_counter; 531 __be16 hw_rq_counter; 532 __be16 sw_rcyclic_byte_counter; 533 __be16 sw_rq_counter; 534 u8 rsvd0[5]; 535 u8 cgs; 536 u8 cs_req; 537 u8 cs_res; 538 __be64 dc_access_key; 539 u8 rsvd1[24]; 540 }; 541 542 struct mlx5_dct_context { 543 u8 state; 544 u8 rsvd0[7]; 545 __be32 cqn; 546 __be32 flags; 547 u8 rsvd1; 548 u8 cs_res; 549 u8 min_rnr; 550 u8 rsvd2; 551 __be32 srqn; 552 __be32 pdn; 553 __be32 tclass_flow_label; 554 __be64 access_key; 555 u8 mtu; 556 u8 port; 557 __be16 pkey_index; 558 u8 rsvd4; 559 u8 mgid_index; 560 u8 rsvd5; 561 u8 hop_limit; 562 __be32 access_violations; 563 u8 rsvd[12]; 564 }; 565 566 static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn) 567 { 568 return radix_tree_lookup(&dev->priv.qp_table.tree, qpn); 569 } 570 571 static inline struct mlx5_core_mkey *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key) 572 { 573 return radix_tree_lookup(&dev->priv.mr_table.tree, key); 574 } 575 576 int mlx5_core_create_qp(struct mlx5_core_dev *dev, 577 struct mlx5_core_qp *qp, 578 u32 *in, 579 int inlen); 580 int mlx5_core_qp_modify(struct mlx5_core_dev *dev, u16 opcode, 581 u32 opt_param_mask, void *qpc, 582 struct mlx5_core_qp *qp); 583 int mlx5_core_destroy_qp(struct mlx5_core_dev *dev, 584 struct mlx5_core_qp *qp); 585 int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp, 586 u32 *out, int outlen); 587 int mlx5_core_dct_query(struct mlx5_core_dev *dev, struct mlx5_core_dct *dct, 588 u32 *out, int outlen); 589 int mlx5_core_arm_dct(struct mlx5_core_dev *dev, struct mlx5_core_dct *dct); 590 591 int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn); 592 int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn); 593 int mlx5_core_create_dct(struct mlx5_core_dev *dev, 594 struct mlx5_core_dct *dct, 595 u32 *in, int inlen, 596 u32 *out, int outlen); 597 int mlx5_core_destroy_dct(struct mlx5_core_dev *dev, 598 struct mlx5_core_dct *dct); 599 int mlx5_core_create_rq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen, 600 struct mlx5_core_qp *rq); 601 void mlx5_core_destroy_rq_tracked(struct mlx5_core_dev *dev, 602 struct mlx5_core_qp *rq); 603 int mlx5_core_create_sq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen, 604 struct mlx5_core_qp *sq); 605 void mlx5_core_destroy_sq_tracked(struct mlx5_core_dev *dev, 606 struct mlx5_core_qp *sq); 607 void mlx5_init_qp_table(struct mlx5_core_dev *dev); 608 void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev); 609 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 610 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 611 612 static inline const char *mlx5_qp_type_str(int type) 613 { 614 switch (type) { 615 case MLX5_QP_ST_RC: return "RC"; 616 case MLX5_QP_ST_UC: return "C"; 617 case MLX5_QP_ST_UD: return "UD"; 618 case MLX5_QP_ST_XRC: return "XRC"; 619 case MLX5_QP_ST_MLX: return "MLX"; 620 case MLX5_QP_ST_DCI: return "DCI"; 621 case MLX5_QP_ST_QP0: return "QP0"; 622 case MLX5_QP_ST_QP1: return "QP1"; 623 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE"; 624 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6"; 625 case MLX5_QP_ST_SNIFFER: return "SNIFFER"; 626 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR"; 627 case MLX5_QP_ST_PTP_1588: return "PTP_1588"; 628 case MLX5_QP_ST_REG_UMR: return "REG_UMR"; 629 case MLX5_QP_ST_SW_CNAK: return "DC_CNAK"; 630 default: return "Invalid transport type"; 631 } 632 } 633 634 static inline const char *mlx5_qp_state_str(int state) 635 { 636 switch (state) { 637 case MLX5_QP_STATE_RST: 638 return "RST"; 639 case MLX5_QP_STATE_INIT: 640 return "INIT"; 641 case MLX5_QP_STATE_RTR: 642 return "RTR"; 643 case MLX5_QP_STATE_RTS: 644 return "RTS"; 645 case MLX5_QP_STATE_SQER: 646 return "SQER"; 647 case MLX5_QP_STATE_SQD: 648 return "SQD"; 649 case MLX5_QP_STATE_ERR: 650 return "ERR"; 651 case MLX5_QP_STATE_SQ_DRAINING: 652 return "SQ_DRAINING"; 653 case MLX5_QP_STATE_SUSPENDED: 654 return "SUSPENDED"; 655 default: return "Invalid QP state"; 656 } 657 } 658 659 #endif /* MLX5_QP_H */ 660