xref: /freebsd/sys/dev/mlx5/port.h (revision 85f87cf491bec6f90948a85b10f5523ea24db9e3)
1 /*-
2  * Copyright (c) 2016-2018, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  * 1. Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  *
13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23  * SUCH DAMAGE.
24  *
25  * $FreeBSD$
26  */
27 
28 #ifndef __MLX5_PORT_H__
29 #define	__MLX5_PORT_H__
30 
31 #include <dev/mlx5/driver.h>
32 
33 enum mlx5_beacon_duration {
34 	MLX5_BEACON_DURATION_OFF = 0x0,
35 	MLX5_BEACON_DURATION_INF = 0xffff,
36 };
37 
38 enum mlx5_module_id {
39 	MLX5_MODULE_ID_SFP              = 0x3,
40 	MLX5_MODULE_ID_QSFP             = 0xC,
41 	MLX5_MODULE_ID_QSFP_PLUS        = 0xD,
42 	MLX5_MODULE_ID_QSFP28           = 0x11,
43 };
44 
45 enum mlx5_an_status {
46 	MLX5_AN_UNAVAILABLE = 0,
47 	MLX5_AN_COMPLETE    = 1,
48 	MLX5_AN_FAILED      = 2,
49 	MLX5_AN_LINK_UP     = 3,
50 	MLX5_AN_LINK_DOWN   = 4,
51 };
52 
53 /* EEPROM I2C Addresses */
54 #define	MLX5_I2C_ADDR_LOW			0x50
55 #define	MLX5_I2C_ADDR_HIGH			0x51
56 #define	MLX5_EEPROM_PAGE_LENGTH			256
57 #define	MLX5_EEPROM_MAX_BYTES			32
58 #define	MLX5_EEPROM_IDENTIFIER_BYTE_MASK	0x000000ff
59 #define	MLX5_EEPROM_REVISION_ID_BYTE_MASK       0x0000ff00
60 #define	MLX5_EEPROM_PAGE_3_VALID_BIT_MASK       0x00040000
61 #define	MLX5_EEPROM_LOW_PAGE			0x0
62 #define	MLX5_EEPROM_HIGH_PAGE			0x3
63 #define	MLX5_EEPROM_HIGH_PAGE_OFFSET		128
64 #define	MLX5_EEPROM_INFO_BYTES			0x3
65 
66 /* EEPROM Standards for plug in modules */
67 #ifndef MLX5_ETH_MODULE_SFF_8472
68 #define	MLX5_ETH_MODULE_SFF_8472	0x1
69 #define	MLX5_ETH_MODULE_SFF_8472_LEN	128
70 #endif
71 
72 #ifndef MLX5_ETH_MODULE_SFF_8636
73 #define	MLX5_ETH_MODULE_SFF_8636	0x2
74 #define	MLX5_ETH_MODULE_SFF_8636_LEN	256
75 #endif
76 
77 #ifndef MLX5_ETH_MODULE_SFF_8436
78 #define	MLX5_ETH_MODULE_SFF_8436	0x3
79 #define	MLX5_ETH_MODULE_SFF_8436_LEN	256
80 #endif
81 
82 enum mlx5e_link_speed {
83 	MLX5E_1000BASE_CX_SGMII	 = 0,
84 	MLX5E_1000BASE_KX	 = 1,
85 	MLX5E_10GBASE_CX4	 = 2,
86 	MLX5E_10GBASE_KX4	 = 3,
87 	MLX5E_10GBASE_KR	 = 4,
88 	MLX5E_20GBASE_KR2	 = 5,
89 	MLX5E_40GBASE_CR4	 = 6,
90 	MLX5E_40GBASE_KR4	 = 7,
91 	MLX5E_56GBASE_R4	 = 8,
92 	MLX5E_10GBASE_CR	 = 12,
93 	MLX5E_10GBASE_SR	 = 13,
94 	MLX5E_10GBASE_ER_LR	 = 14,
95 	MLX5E_40GBASE_SR4	 = 15,
96 	MLX5E_40GBASE_LR4_ER4	 = 16,
97 	MLX5E_50GBASE_SR2	 = 18,
98 	MLX5E_100GBASE_CR4	 = 20,
99 	MLX5E_100GBASE_SR4	 = 21,
100 	MLX5E_100GBASE_KR4	 = 22,
101 	MLX5E_100GBASE_LR4	 = 23,
102 	MLX5E_100BASE_TX	 = 24,
103 	MLX5E_1000BASE_T	 = 25,
104 	MLX5E_10GBASE_T		 = 26,
105 	MLX5E_25GBASE_CR	 = 27,
106 	MLX5E_25GBASE_KR	 = 28,
107 	MLX5E_25GBASE_SR	 = 29,
108 	MLX5E_50GBASE_CR2	 = 30,
109 	MLX5E_50GBASE_KR2	 = 31,
110 	MLX5E_LINK_SPEEDS_NUMBER,
111 };
112 
113 enum mlx5e_ext_link_speed {
114 	MLX5E_SGMII_100M			= 0,
115 	MLX5E_1000BASE_X_SGMII			= 1,
116 	MLX5E_5GBASE_R				= 3,
117 	MLX5E_10GBASE_XFI_XAUI_1		= 4,
118 	MLX5E_40GBASE_XLAUI_4_XLPPI_4		= 5,
119 	MLX5E_25GAUI_1_25GBASE_CR_KR		= 6,
120 	MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2	= 7,
121 	MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR	= 8,
122 	MLX5E_CAUI_4_100GBASE_CR4_KR4		= 9,
123 	MLX5E_100GAUI_2_100GBASE_CR2_KR2	= 10,
124 	MLX5E_200GAUI_4_200GBASE_CR4_KR4	= 12,
125 	MLX5E_400GAUI_8				= 15,
126 	MLX5E_EXT_LINK_SPEEDS_NUMBER,
127 };
128 
129 enum mlx5e_link_mode {
130 	MLX5E_ACC,
131 	MLX5E_AOC,
132 	MLX5E_AUI,
133 	MLX5E_AUI_AC,
134 	MLX5E_AUI2,
135 	MLX5E_AUI2_AC,
136 	MLX5E_AUI4,
137 	MLX5E_AUI4_AC,
138 	MLX5E_CAUI2,
139 	MLX5E_CAUI2_AC,
140 	MLX5E_CAUI4,
141 	MLX5E_CAUI4_AC,
142 	MLX5E_CP,
143 	MLX5E_CP2,
144 	MLX5E_CR,
145 	MLX5E_CR_S,
146 	MLX5E_CR1,
147 	MLX5E_CR2,
148 	MLX5E_CR4,
149 	MLX5E_CR_PAM4,
150 	MLX5E_CR4_PAM4,
151 	MLX5E_CX4,
152 	MLX5E_CX,
153 	MLX5E_CX_SGMII,
154 	MLX5E_DR,
155 	MLX5E_DR4,
156 	MLX5E_ER,
157 	MLX5E_ER4,
158 	MLX5E_FR,
159 	MLX5E_FR4,
160 	MLX5E_KR,
161 	MLX5E_KR1,
162 	MLX5E_KR_PAM4,
163 	MLX5E_KR_S,
164 	MLX5E_KR2,
165 	MLX5E_KR2_PAM4,
166 	MLX5E_KR4,
167 	MLX5E_KR4_PAM4,
168 	MLX5E_KX,
169 	MLX5E_KX4,
170 	MLX5E_LR,
171 	MLX5E_LR2,
172 	MLX5E_LR4,
173 	MLX5E_LX,
174 	MLX5E_R,
175 	MLX5E_SGMII,
176 	MLX5E_SR,
177 	MLX5E_SR2,
178 	MLX5E_SR4,
179 	MLX5E_SX,
180 	MLX5E_T,
181 	MLX5E_TX,
182 	MLX5E_LINK_MODES_NUMBER,
183 };
184 
185 enum mlx5e_connector_type {
186 	MLX5E_PORT_UNKNOWN	= 0,
187 	MLX5E_PORT_NONE			= 1,
188 	MLX5E_PORT_TP			= 2,
189 	MLX5E_PORT_AUI			= 3,
190 	MLX5E_PORT_BNC			= 4,
191 	MLX5E_PORT_MII			= 5,
192 	MLX5E_PORT_FIBRE		= 6,
193 	MLX5E_PORT_DA			= 7,
194 	MLX5E_PORT_OTHER		= 8,
195 	MLX5E_CONNECTOR_TYPE_NUMBER,
196 };
197 
198 enum mlx5_qpts_trust_state {
199 	MLX5_QPTS_TRUST_PCP = 1,
200 	MLX5_QPTS_TRUST_DSCP = 2,
201 	MLX5_QPTS_TRUST_BOTH = 3,
202 };
203 struct mlx5e_port_eth_proto {
204 	u32 cap;
205 	u32 admin;
206 	u32 oper;
207 };
208 
209 #ifndef SPEED_40000
210 #define SPEED_40000 40000
211 #endif
212 
213 #define	MLX5E_PROT_MASK(link_mode) (1 << (link_mode))
214 
215 #define	PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF
216 #define	PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF
217 
218 #define MLX5_GET_ETH_PROTO(reg, out, ext, field)    \
219     ((ext) ? MLX5_GET(reg, out, ext_##field) :        \
220     MLX5_GET(reg, out, field))
221 
222 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
223 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
224 			 int ptys_size, int proto_mask, u8 local_port);
225 int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
226 			      u32 *proto_cap, int proto_mask);
227 int mlx5_query_port_autoneg(struct mlx5_core_dev *dev, int proto_mask,
228 			    u8 *an_disable_cap, u8 *an_disable_status);
229 int mlx5_set_port_autoneg(struct mlx5_core_dev *dev, bool disable,
230 			  u32 eth_proto_admin, int proto_mask);
231 int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
232 				u32 *proto_admin, int proto_mask);
233 int mlx5_query_port_eth_proto_oper(struct mlx5_core_dev *dev,
234 				   u32 *proto_oper, u8 local_port);
235 int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
236 			int proto_mask, bool ext);
237 int mlx5_set_port_status(struct mlx5_core_dev *dev,
238 			 enum mlx5_port_status status);
239 int mlx5_query_port_status(struct mlx5_core_dev *dev, u8 *status);
240 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
241 				 enum mlx5_port_status *status);
242 int mlx5_set_port_pause_and_pfc(struct mlx5_core_dev *dev, u32 port,
243 				u8 rx_pause, u8 tx_pause,
244 				u8 pfc_en_rx, u8 pfc_en_tx);
245 int mlx5_query_port_pause(struct mlx5_core_dev *dev, u32 port,
246 			  u32 *rx_pause, u32 *tx_pause);
247 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx);
248 
249 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu);
250 int mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu);
251 int mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu);
252 
253 unsigned int mlx5_query_module_status(struct mlx5_core_dev *dev, int module_num);
254 int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num);
255 int mlx5_query_eeprom(struct mlx5_core_dev *dev, int i2c_addr, int page_num,
256 		      int device_addr, int size, int module_num, u32 *data,
257 		      int *size_read);
258 
259 int mlx5_max_tc(struct mlx5_core_dev *mdev);
260 int mlx5_query_port_tc_rate_limit(struct mlx5_core_dev *mdev,
261 				   u8 *max_bw_value,
262 				   u8 *max_bw_units);
263 int mlx5_modify_port_tc_rate_limit(struct mlx5_core_dev *mdev,
264 				   const u8 *max_bw_value,
265 				   const u8 *max_bw_units);
266 int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev,
267 			    u8 prio, u8 *tc);
268 int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, int prio_index,
269 			  const u8 prio_tc);
270 int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, const u8 *tc_group);
271 int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev,
272 			     u8 tc, u8 *tc_group);
273 int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, const u8 *tc_bw);
274 int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *bw_pct);
275 
276 int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state);
277 int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state);
278 
279 #define	MLX5_MAX_SUPPORTED_DSCP 64
280 int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, const u8 *dscp2prio);
281 int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio);
282 
283 int mlx5_query_pddr_range_info(struct mlx5_core_dev *mdev, u8 local_port, u8 *is_er_type);
284 
285 u32 mlx5e_port_ptys2speed(struct mlx5_core_dev *mdev, u32 eth_proto_oper);
286 int mlx5e_port_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
287 int mlx5_port_query_eth_proto(struct mlx5_core_dev *dev, u8 port, bool ext,
288 			      struct mlx5e_port_eth_proto *eproto);
289 
290 int mlx5e_port_query_pbmc(struct mlx5_core_dev *mdev, void *out);
291 int mlx5e_port_set_pbmc(struct mlx5_core_dev *mdev, void *in);
292 int mlx5e_port_query_priority2buffer(struct mlx5_core_dev *mdev, u8 *buffer);
293 int mlx5e_port_set_priority2buffer(struct mlx5_core_dev *mdev, u8 *buffer);
294 
295 #endif /* __MLX5_PORT_H__ */
296