1 /*- 2 * Copyright (c) 2016-2018, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef __MLX5_PORT_H__ 29 #define __MLX5_PORT_H__ 30 31 #include <dev/mlx5/driver.h> 32 33 enum mlx5_beacon_duration { 34 MLX5_BEACON_DURATION_OFF = 0x0, 35 MLX5_BEACON_DURATION_INF = 0xffff, 36 }; 37 38 enum mlx5_module_id { 39 MLX5_MODULE_ID_SFP = 0x3, 40 MLX5_MODULE_ID_QSFP = 0xC, 41 MLX5_MODULE_ID_QSFP_PLUS = 0xD, 42 MLX5_MODULE_ID_QSFP28 = 0x11, 43 }; 44 45 enum mlx5_an_status { 46 MLX5_AN_UNAVAILABLE = 0, 47 MLX5_AN_COMPLETE = 1, 48 MLX5_AN_FAILED = 2, 49 MLX5_AN_LINK_UP = 3, 50 MLX5_AN_LINK_DOWN = 4, 51 }; 52 53 #define MLX5_EEPROM_MAX_BYTES 32 54 #define MLX5_EEPROM_IDENTIFIER_BYTE_MASK 0x000000ff 55 #define MLX5_EEPROM_REVISION_ID_BYTE_MASK 0x0000ff00 56 #define MLX5_EEPROM_PAGE_3_VALID_BIT_MASK 0x00040000 57 #define MLX5_I2C_ADDR_LOW 0x50 58 #define MLX5_I2C_ADDR_HIGH 0x51 59 #define MLX5_EEPROM_PAGE_LENGTH 256 60 61 enum mlx5e_link_speed { 62 MLX5E_1000BASE_CX_SGMII = 0, 63 MLX5E_1000BASE_KX = 1, 64 MLX5E_10GBASE_CX4 = 2, 65 MLX5E_10GBASE_KX4 = 3, 66 MLX5E_10GBASE_KR = 4, 67 MLX5E_20GBASE_KR2 = 5, 68 MLX5E_40GBASE_CR4 = 6, 69 MLX5E_40GBASE_KR4 = 7, 70 MLX5E_56GBASE_R4 = 8, 71 MLX5E_10GBASE_CR = 12, 72 MLX5E_10GBASE_SR = 13, 73 MLX5E_10GBASE_ER_LR = 14, 74 MLX5E_40GBASE_SR4 = 15, 75 MLX5E_40GBASE_LR4_ER4 = 16, 76 MLX5E_50GBASE_SR2 = 18, 77 MLX5E_100GBASE_CR4 = 20, 78 MLX5E_100GBASE_SR4 = 21, 79 MLX5E_100GBASE_KR4 = 22, 80 MLX5E_100GBASE_LR4 = 23, 81 MLX5E_100BASE_TX = 24, 82 MLX5E_1000BASE_T = 25, 83 MLX5E_10GBASE_T = 26, 84 MLX5E_25GBASE_CR = 27, 85 MLX5E_25GBASE_KR = 28, 86 MLX5E_25GBASE_SR = 29, 87 MLX5E_50GBASE_CR2 = 30, 88 MLX5E_50GBASE_KR2 = 31, 89 MLX5E_LINK_SPEEDS_NUMBER, 90 }; 91 92 enum mlx5e_ext_link_speed { 93 MLX5E_SGMII_100M = 0, 94 MLX5E_1000BASE_X_SGMII = 1, 95 MLX5E_5GBASE_R = 3, 96 MLX5E_10GBASE_XFI_XAUI_1 = 4, 97 MLX5E_40GBASE_XLAUI_4_XLPPI_4 = 5, 98 MLX5E_25GAUI_1_25GBASE_CR_KR = 6, 99 MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 = 7, 100 MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR = 8, 101 MLX5E_CAUI_4_100GBASE_CR4_KR4 = 9, 102 MLX5E_100GAUI_2_100GBASE_CR2_KR2 = 10, 103 MLX5E_200GAUI_4_200GBASE_CR4_KR4 = 12, 104 MLX5E_400GAUI_8 = 15, 105 MLX5E_EXT_LINK_SPEEDS_NUMBER, 106 }; 107 108 enum mlx5e_link_mode { 109 MLX5E_ACC, 110 MLX5E_AOC, 111 MLX5E_AUI, 112 MLX5E_AUI_AC, 113 MLX5E_AUI2, 114 MLX5E_AUI2_AC, 115 MLX5E_AUI4, 116 MLX5E_AUI4_AC, 117 MLX5E_CAUI2, 118 MLX5E_CAUI2_AC, 119 MLX5E_CAUI4, 120 MLX5E_CAUI4_AC, 121 MLX5E_CP, 122 MLX5E_CP2, 123 MLX5E_CR, 124 MLX5E_CR_S, 125 MLX5E_CR1, 126 MLX5E_CR2, 127 MLX5E_CR4, 128 MLX5E_CR_PAM4, 129 MLX5E_CR4_PAM4, 130 MLX5E_CX4, 131 MLX5E_CX, 132 MLX5E_CX_SGMII, 133 MLX5E_DR, 134 MLX5E_DR4, 135 MLX5E_ER, 136 MLX5E_ER4, 137 MLX5E_FR, 138 MLX5E_FR4, 139 MLX5E_KR, 140 MLX5E_KR1, 141 MLX5E_KR_PAM4, 142 MLX5E_KR_S, 143 MLX5E_KR2, 144 MLX5E_KR2_PAM4, 145 MLX5E_KR4, 146 MLX5E_KR4_PAM4, 147 MLX5E_KX, 148 MLX5E_KX4, 149 MLX5E_LR, 150 MLX5E_LR2, 151 MLX5E_LR4, 152 MLX5E_LX, 153 MLX5E_R, 154 MLX5E_SGMII, 155 MLX5E_SR, 156 MLX5E_SR2, 157 MLX5E_SR4, 158 MLX5E_SX, 159 MLX5E_T, 160 MLX5E_TX, 161 MLX5E_LINK_MODES_NUMBER, 162 }; 163 164 enum mlx5e_connector_type { 165 MLX5E_PORT_UNKNOWN = 0, 166 MLX5E_PORT_NONE = 1, 167 MLX5E_PORT_TP = 2, 168 MLX5E_PORT_AUI = 3, 169 MLX5E_PORT_BNC = 4, 170 MLX5E_PORT_MII = 5, 171 MLX5E_PORT_FIBRE = 6, 172 MLX5E_PORT_DA = 7, 173 MLX5E_PORT_OTHER = 8, 174 MLX5E_CONNECTOR_TYPE_NUMBER, 175 }; 176 177 enum mlx5_qpts_trust_state { 178 MLX5_QPTS_TRUST_PCP = 1, 179 MLX5_QPTS_TRUST_DSCP = 2, 180 MLX5_QPTS_TRUST_BOTH = 3, 181 }; 182 183 #define MLX5E_PROT_MASK(link_mode) (1 << (link_mode)) 184 185 #define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF 186 #define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF 187 188 #define MLX5_GET_ETH_PROTO(reg, out, ext, field) \ 189 ((ext) ? MLX5_GET(reg, out, ext_##field) : \ 190 MLX5_GET(reg, out, field)) 191 192 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps); 193 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys, 194 int ptys_size, int proto_mask, u8 local_port); 195 int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev, 196 u32 *proto_cap, int proto_mask); 197 int mlx5_query_port_autoneg(struct mlx5_core_dev *dev, int proto_mask, 198 u8 *an_disable_cap, u8 *an_disable_status); 199 int mlx5_set_port_autoneg(struct mlx5_core_dev *dev, bool disable, 200 u32 eth_proto_admin, int proto_mask); 201 int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev, 202 u32 *proto_admin, int proto_mask); 203 int mlx5_query_port_eth_proto_oper(struct mlx5_core_dev *dev, 204 u32 *proto_oper, u8 local_port); 205 int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin, 206 int proto_mask, bool ext); 207 int mlx5_set_port_status(struct mlx5_core_dev *dev, 208 enum mlx5_port_status status); 209 int mlx5_query_port_status(struct mlx5_core_dev *dev, u8 *status); 210 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev, 211 enum mlx5_port_status *status); 212 int mlx5_set_port_pause_and_pfc(struct mlx5_core_dev *dev, u32 port, 213 u8 rx_pause, u8 tx_pause, 214 u8 pfc_en_rx, u8 pfc_en_tx); 215 int mlx5_query_port_pause(struct mlx5_core_dev *dev, u32 port, 216 u32 *rx_pause, u32 *tx_pause); 217 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx); 218 219 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu); 220 int mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu); 221 int mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu); 222 223 unsigned int mlx5_query_module_status(struct mlx5_core_dev *dev, int module_num); 224 int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num); 225 int mlx5_query_eeprom(struct mlx5_core_dev *dev, int i2c_addr, int page_num, 226 int device_addr, int size, int module_num, u32 *data, 227 int *size_read); 228 229 int mlx5_max_tc(struct mlx5_core_dev *mdev); 230 int mlx5_query_port_tc_rate_limit(struct mlx5_core_dev *mdev, 231 u8 *max_bw_value, 232 u8 *max_bw_units); 233 int mlx5_modify_port_tc_rate_limit(struct mlx5_core_dev *mdev, 234 const u8 *max_bw_value, 235 const u8 *max_bw_units); 236 int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev, 237 u8 prio, u8 *tc); 238 int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, int prio_index, 239 const u8 prio_tc); 240 int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, const u8 *tc_group); 241 int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev, 242 u8 tc, u8 *tc_group); 243 int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, const u8 *tc_bw); 244 int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *bw_pct); 245 246 int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state); 247 int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state); 248 249 #define MLX5_MAX_SUPPORTED_DSCP 64 250 int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, const u8 *dscp2prio); 251 int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio); 252 253 int mlx5_query_pddr_range_info(struct mlx5_core_dev *mdev, u8 local_port, u8 *is_er_type); 254 255 #endif /* __MLX5_PORT_H__ */ 256