1 /*- 2 * Copyright (c) 2018, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef _DEV_MLX5_MLX5IO_H_ 29 #define _DEV_MLX5_MLX5IO_H_ 30 31 #include <sys/ioccom.h> 32 33 struct mlx5_fwdump_reg { 34 uint32_t addr; 35 uint32_t val; 36 }; 37 38 struct mlx5_fwdump_addr { 39 uint32_t domain; 40 uint8_t bus; 41 uint8_t slot; 42 uint8_t func; 43 }; 44 45 struct mlx5_fwdump_get { 46 struct mlx5_fwdump_addr devaddr; 47 struct mlx5_fwdump_reg *buf; 48 size_t reg_cnt; 49 size_t reg_filled; /* out */ 50 }; 51 52 #define MLX5_FWDUMP_GET _IOWR('m', 1, struct mlx5_fwdump_get) 53 #define MLX5_FWDUMP_RESET _IOW('m', 2, struct mlx5_fwdump_addr) 54 #define MLX5_FWDUMP_FORCE _IOW('m', 3, struct mlx5_fwdump_addr) 55 56 #ifndef _KERNEL 57 #define MLX5_DEV_PATH _PATH_DEV"mlx5ctl" 58 #endif 59 60 enum mlx5_fpga_id { 61 MLX5_FPGA_NEWTON = 0, 62 MLX5_FPGA_EDISON = 1, 63 MLX5_FPGA_MORSE = 2, 64 }; 65 66 enum mlx5_fpga_image { 67 MLX5_FPGA_IMAGE_USER = 0, 68 MLX5_FPGA_IMAGE_FACTORY = 1, 69 MLX5_FPGA_IMAGE_MAX = MLX5_FPGA_IMAGE_FACTORY, 70 MLX5_FPGA_IMAGE_FACTORY_FAILOVER = 2, 71 }; 72 73 enum mlx5_fpga_status { 74 MLX5_FPGA_STATUS_SUCCESS = 0, 75 MLX5_FPGA_STATUS_FAILURE = 1, 76 MLX5_FPGA_STATUS_IN_PROGRESS = 2, 77 MLX5_FPGA_STATUS_DISCONNECTED = 3, 78 }; 79 80 struct mlx5_fpga_query { 81 enum mlx5_fpga_image admin_image; 82 enum mlx5_fpga_image oper_image; 83 enum mlx5_fpga_status image_status; 84 }; 85 86 /** 87 * enum mlx5_fpga_access_type - Enumerated the different methods possible for 88 * accessing the device memory address space 89 */ 90 enum mlx5_fpga_access_type { 91 /** Use the slow CX-FPGA I2C bus*/ 92 MLX5_FPGA_ACCESS_TYPE_I2C = 0x0, 93 /** Use the fast 'shell QP' */ 94 MLX5_FPGA_ACCESS_TYPE_RDMA, 95 /** Use the fastest available method */ 96 MLX5_FPGA_ACCESS_TYPE_DONTCARE, 97 MLX5_FPGA_ACCESS_TYPE_MAX = MLX5_FPGA_ACCESS_TYPE_DONTCARE, 98 }; 99 100 #endif 101