1*e23731dbSKonstantin Belousov /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2*e23731dbSKonstantin Belousov /* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */ 3*e23731dbSKonstantin Belousov 4*e23731dbSKonstantin Belousov #ifndef __MLX5_LIB_ASO_H__ 5*e23731dbSKonstantin Belousov #define __MLX5_LIB_ASO_H__ 6*e23731dbSKonstantin Belousov 7*e23731dbSKonstantin Belousov #include <dev/mlx5/qp.h> 8*e23731dbSKonstantin Belousov #include <dev/mlx5/mlx5_core/mlx5_core.h> 9*e23731dbSKonstantin Belousov 10*e23731dbSKonstantin Belousov #define MLX5_ASO_WQEBBS \ 11*e23731dbSKonstantin Belousov (DIV_ROUND_UP(sizeof(struct mlx5_aso_wqe), MLX5_SEND_WQE_BB)) 12*e23731dbSKonstantin Belousov #define MLX5_ASO_WQEBBS_DATA \ 13*e23731dbSKonstantin Belousov (DIV_ROUND_UP(sizeof(struct mlx5_aso_wqe_data), MLX5_SEND_WQE_BB)) 14*e23731dbSKonstantin Belousov #define ASO_CTRL_READ_EN BIT(0) 15*e23731dbSKonstantin Belousov #define MLX5_WQE_CTRL_WQE_OPC_MOD_SHIFT 24 16*e23731dbSKonstantin Belousov #define MLX5_MACSEC_ASO_DS_CNT (DIV_ROUND_UP(sizeof(struct mlx5_aso_wqe), MLX5_SEND_WQE_DS)) 17*e23731dbSKonstantin Belousov 18*e23731dbSKonstantin Belousov #define ASO_CTRL_READ_EN BIT(0) 19*e23731dbSKonstantin Belousov struct mlx5_wqe_aso_ctrl_seg { 20*e23731dbSKonstantin Belousov __be32 va_h; 21*e23731dbSKonstantin Belousov __be32 va_l; /* include read_enable */ 22*e23731dbSKonstantin Belousov __be32 l_key; 23*e23731dbSKonstantin Belousov u8 data_mask_mode; 24*e23731dbSKonstantin Belousov u8 condition_1_0_operand; 25*e23731dbSKonstantin Belousov u8 condition_1_0_offset; 26*e23731dbSKonstantin Belousov u8 data_offset_condition_operand; 27*e23731dbSKonstantin Belousov __be32 condition_0_data; 28*e23731dbSKonstantin Belousov __be32 condition_0_mask; 29*e23731dbSKonstantin Belousov __be32 condition_1_data; 30*e23731dbSKonstantin Belousov __be32 condition_1_mask; 31*e23731dbSKonstantin Belousov __be64 bitwise_data; 32*e23731dbSKonstantin Belousov __be64 data_mask; 33*e23731dbSKonstantin Belousov }; 34*e23731dbSKonstantin Belousov 35*e23731dbSKonstantin Belousov struct mlx5_wqe_aso_data_seg { 36*e23731dbSKonstantin Belousov __be32 bytewise_data[16]; 37*e23731dbSKonstantin Belousov }; 38*e23731dbSKonstantin Belousov 39*e23731dbSKonstantin Belousov struct mlx5_aso_wqe { 40*e23731dbSKonstantin Belousov struct mlx5_wqe_ctrl_seg ctrl; 41*e23731dbSKonstantin Belousov struct mlx5_wqe_aso_ctrl_seg aso_ctrl; 42*e23731dbSKonstantin Belousov }; 43*e23731dbSKonstantin Belousov 44*e23731dbSKonstantin Belousov struct mlx5_aso_wqe_data { 45*e23731dbSKonstantin Belousov struct mlx5_wqe_ctrl_seg ctrl; 46*e23731dbSKonstantin Belousov struct mlx5_wqe_aso_ctrl_seg aso_ctrl; 47*e23731dbSKonstantin Belousov struct mlx5_wqe_aso_data_seg aso_data; 48*e23731dbSKonstantin Belousov }; 49*e23731dbSKonstantin Belousov 50*e23731dbSKonstantin Belousov enum { 51*e23731dbSKonstantin Belousov MLX5_ASO_LOGICAL_AND, 52*e23731dbSKonstantin Belousov MLX5_ASO_LOGICAL_OR, 53*e23731dbSKonstantin Belousov }; 54*e23731dbSKonstantin Belousov 55*e23731dbSKonstantin Belousov enum { 56*e23731dbSKonstantin Belousov MLX5_ASO_ALWAYS_FALSE, 57*e23731dbSKonstantin Belousov MLX5_ASO_ALWAYS_TRUE, 58*e23731dbSKonstantin Belousov MLX5_ASO_EQUAL, 59*e23731dbSKonstantin Belousov MLX5_ASO_NOT_EQUAL, 60*e23731dbSKonstantin Belousov MLX5_ASO_GREATER_OR_EQUAL, 61*e23731dbSKonstantin Belousov MLX5_ASO_LESSER_OR_EQUAL, 62*e23731dbSKonstantin Belousov MLX5_ASO_LESSER, 63*e23731dbSKonstantin Belousov MLX5_ASO_GREATER, 64*e23731dbSKonstantin Belousov MLX5_ASO_CYCLIC_GREATER, 65*e23731dbSKonstantin Belousov MLX5_ASO_CYCLIC_LESSER, 66*e23731dbSKonstantin Belousov }; 67*e23731dbSKonstantin Belousov 68*e23731dbSKonstantin Belousov enum { 69*e23731dbSKonstantin Belousov MLX5_ASO_DATA_MASK_MODE_BITWISE_64BIT, 70*e23731dbSKonstantin Belousov MLX5_ASO_DATA_MASK_MODE_BYTEWISE_64BYTE, 71*e23731dbSKonstantin Belousov MLX5_ASO_DATA_MASK_MODE_CALCULATED_64BYTE, 72*e23731dbSKonstantin Belousov }; 73*e23731dbSKonstantin Belousov 74*e23731dbSKonstantin Belousov enum { 75*e23731dbSKonstantin Belousov MLX5_ACCESS_ASO_OPC_MOD_IPSEC = 0x0, 76*e23731dbSKonstantin Belousov MLX5_ACCESS_ASO_OPC_MOD_FLOW_METER = 0x2, 77*e23731dbSKonstantin Belousov MLX5_ACCESS_ASO_OPC_MOD_MACSEC = 0x5, 78*e23731dbSKonstantin Belousov }; 79*e23731dbSKonstantin Belousov 80*e23731dbSKonstantin Belousov struct mlx5_aso; 81*e23731dbSKonstantin Belousov 82*e23731dbSKonstantin Belousov struct mlx5_aso_wqe *mlx5_aso_get_wqe(struct mlx5_aso *aso); 83*e23731dbSKonstantin Belousov void mlx5_aso_build_wqe(struct mlx5_aso *aso, u8 ds_cnt, 84*e23731dbSKonstantin Belousov struct mlx5_aso_wqe *aso_wqe, 85*e23731dbSKonstantin Belousov u32 obj_id, u32 opc_mode); 86*e23731dbSKonstantin Belousov void mlx5_aso_post_wqe(struct mlx5_aso *aso, bool with_data, 87*e23731dbSKonstantin Belousov struct mlx5_wqe_ctrl_seg *doorbell_cseg); 88*e23731dbSKonstantin Belousov int mlx5_aso_poll_cq(struct mlx5_aso *aso, bool with_data); 89*e23731dbSKonstantin Belousov 90*e23731dbSKonstantin Belousov struct mlx5_aso *mlx5_aso_create(struct mlx5_core_dev *mdev, u32 pdn); 91*e23731dbSKonstantin Belousov void mlx5_aso_destroy(struct mlx5_aso *aso); 92*e23731dbSKonstantin Belousov #endif /* __MLX5_LIB_ASO_H__ */ 93