xref: /freebsd/sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c (revision cfd6422a5217410fbd66f7a7a8a64d9d85e61229)
1 /*-
2  * Copyright (c) 2013-2020, Mellanox Technologies. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  * 1. Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  *
13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23  * SUCH DAMAGE.
24  *
25  * $FreeBSD$
26  */
27 
28 #include <linux/module.h>
29 #include <rdma/ib_umem.h>
30 #include <rdma/ib_cache.h>
31 #include <rdma/ib_user_verbs.h>
32 #include "mlx5_ib.h"
33 
34 /* not supported currently */
35 static int wq_signature;
36 
37 enum {
38 	MLX5_IB_ACK_REQ_FREQ	= 8,
39 };
40 
41 enum {
42 	MLX5_IB_DEFAULT_SCHED_QUEUE	= 0x83,
43 	MLX5_IB_DEFAULT_QP0_SCHED_QUEUE	= 0x3f,
44 	MLX5_IB_LINK_TYPE_IB		= 0,
45 	MLX5_IB_LINK_TYPE_ETH		= 1
46 };
47 
48 enum {
49 	MLX5_IB_SQ_STRIDE	= 6,
50 };
51 
52 static const u32 mlx5_ib_opcode[] = {
53 	[IB_WR_SEND]				= MLX5_OPCODE_SEND,
54 	[IB_WR_LSO]				= MLX5_OPCODE_LSO,
55 	[IB_WR_SEND_WITH_IMM]			= MLX5_OPCODE_SEND_IMM,
56 	[IB_WR_RDMA_WRITE]			= MLX5_OPCODE_RDMA_WRITE,
57 	[IB_WR_RDMA_WRITE_WITH_IMM]		= MLX5_OPCODE_RDMA_WRITE_IMM,
58 	[IB_WR_RDMA_READ]			= MLX5_OPCODE_RDMA_READ,
59 	[IB_WR_ATOMIC_CMP_AND_SWP]		= MLX5_OPCODE_ATOMIC_CS,
60 	[IB_WR_ATOMIC_FETCH_AND_ADD]		= MLX5_OPCODE_ATOMIC_FA,
61 	[IB_WR_SEND_WITH_INV]			= MLX5_OPCODE_SEND_INVAL,
62 	[IB_WR_LOCAL_INV]			= MLX5_OPCODE_UMR,
63 	[IB_WR_REG_MR]				= MLX5_OPCODE_UMR,
64 	[IB_WR_MASKED_ATOMIC_CMP_AND_SWP]	= MLX5_OPCODE_ATOMIC_MASKED_CS,
65 	[IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]	= MLX5_OPCODE_ATOMIC_MASKED_FA,
66 	[MLX5_IB_WR_UMR]			= MLX5_OPCODE_UMR,
67 };
68 
69 struct mlx5_wqe_eth_pad {
70 	u8 rsvd0[16];
71 };
72 
73 enum raw_qp_set_mask_map {
74 	MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID		= 1UL << 0,
75 };
76 
77 struct mlx5_modify_raw_qp_param {
78 	u16 operation;
79 
80 	u32 set_mask; /* raw_qp_set_mask_map */
81 	u8 rq_q_ctr_id;
82 };
83 
84 static void get_cqs(enum ib_qp_type qp_type,
85 		    struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
86 		    struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
87 
88 static int is_qp0(enum ib_qp_type qp_type)
89 {
90 	return qp_type == IB_QPT_SMI;
91 }
92 
93 static int is_sqp(enum ib_qp_type qp_type)
94 {
95 	return is_qp0(qp_type) || is_qp1(qp_type);
96 }
97 
98 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
99 {
100 	return mlx5_buf_offset(&qp->buf, offset);
101 }
102 
103 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
104 {
105 	return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
106 }
107 
108 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
109 {
110 	return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
111 }
112 
113 /**
114  * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
115  *
116  * @qp: QP to copy from.
117  * @send: copy from the send queue when non-zero, use the receive queue
118  *	  otherwise.
119  * @wqe_index:  index to start copying from. For send work queues, the
120  *		wqe_index is in units of MLX5_SEND_WQE_BB.
121  *		For receive work queue, it is the number of work queue
122  *		element in the queue.
123  * @buffer: destination buffer.
124  * @length: maximum number of bytes to copy.
125  *
126  * Copies at least a single WQE, but may copy more data.
127  *
128  * Return: the number of bytes copied, or an error code.
129  */
130 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
131 			  void *buffer, u32 length,
132 			  struct mlx5_ib_qp_base *base)
133 {
134 	struct ib_device *ibdev = qp->ibqp.device;
135 	struct mlx5_ib_dev *dev = to_mdev(ibdev);
136 	struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
137 	size_t offset;
138 	size_t wq_end;
139 	struct ib_umem *umem = base->ubuffer.umem;
140 	u32 first_copy_length;
141 	int wqe_length;
142 	int ret;
143 
144 	if (wq->wqe_cnt == 0) {
145 		mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
146 			    qp->ibqp.qp_type);
147 		return -EINVAL;
148 	}
149 
150 	offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
151 	wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
152 
153 	if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
154 		return -EINVAL;
155 
156 	if (offset > umem->length ||
157 	    (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
158 		return -EINVAL;
159 
160 	first_copy_length = min_t(u32, offset + length, wq_end) - offset;
161 	ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
162 	if (ret)
163 		return ret;
164 
165 	if (send) {
166 		struct mlx5_wqe_ctrl_seg *ctrl = buffer;
167 		int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
168 
169 		wqe_length = ds * MLX5_WQE_DS_UNITS;
170 	} else {
171 		wqe_length = 1 << wq->wqe_shift;
172 	}
173 
174 	if (wqe_length <= first_copy_length)
175 		return first_copy_length;
176 
177 	ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
178 				wqe_length - first_copy_length);
179 	if (ret)
180 		return ret;
181 
182 	return wqe_length;
183 }
184 
185 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
186 {
187 	struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
188 	struct ib_event event;
189 
190 	if (type == MLX5_EVENT_TYPE_PATH_MIG) {
191 		/* This event is only valid for trans_qps */
192 		to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
193 	}
194 
195 	if (ibqp->event_handler) {
196 		event.device     = ibqp->device;
197 		event.element.qp = ibqp;
198 		switch (type) {
199 		case MLX5_EVENT_TYPE_PATH_MIG:
200 			event.event = IB_EVENT_PATH_MIG;
201 			break;
202 		case MLX5_EVENT_TYPE_COMM_EST:
203 			event.event = IB_EVENT_COMM_EST;
204 			break;
205 		case MLX5_EVENT_TYPE_SQ_DRAINED:
206 			event.event = IB_EVENT_SQ_DRAINED;
207 			break;
208 		case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
209 			event.event = IB_EVENT_QP_LAST_WQE_REACHED;
210 			break;
211 		case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
212 			event.event = IB_EVENT_QP_FATAL;
213 			break;
214 		case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
215 			event.event = IB_EVENT_PATH_MIG_ERR;
216 			break;
217 		case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
218 			event.event = IB_EVENT_QP_REQ_ERR;
219 			break;
220 		case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
221 			event.event = IB_EVENT_QP_ACCESS_ERR;
222 			break;
223 		default:
224 			pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
225 			return;
226 		}
227 
228 		ibqp->event_handler(&event, ibqp->qp_context);
229 	}
230 }
231 
232 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
233 		       int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
234 {
235 	int wqe_size;
236 	int wq_size;
237 
238 	/* Sanity check RQ size before proceeding */
239 	if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
240 		return -EINVAL;
241 
242 	if (!has_rq) {
243 		qp->rq.max_gs = 0;
244 		qp->rq.wqe_cnt = 0;
245 		qp->rq.wqe_shift = 0;
246 		cap->max_recv_wr = 0;
247 		cap->max_recv_sge = 0;
248 	} else {
249 		if (ucmd) {
250 			qp->rq.wqe_cnt = ucmd->rq_wqe_count;
251 			qp->rq.wqe_shift = ucmd->rq_wqe_shift;
252 			qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
253 			qp->rq.max_post = qp->rq.wqe_cnt;
254 		} else {
255 			wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
256 			wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
257 			wqe_size = roundup_pow_of_two(wqe_size);
258 			wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
259 			wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
260 			qp->rq.wqe_cnt = wq_size / wqe_size;
261 			if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
262 				mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
263 					    wqe_size,
264 					    MLX5_CAP_GEN(dev->mdev,
265 							 max_wqe_sz_rq));
266 				return -EINVAL;
267 			}
268 			qp->rq.wqe_shift = ilog2(wqe_size);
269 			qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
270 			qp->rq.max_post = qp->rq.wqe_cnt;
271 		}
272 	}
273 
274 	return 0;
275 }
276 
277 static int sq_overhead(struct ib_qp_init_attr *attr)
278 {
279 	int size = 0;
280 
281 	switch (attr->qp_type) {
282 	case IB_QPT_XRC_INI:
283 		size += sizeof(struct mlx5_wqe_xrc_seg);
284 		/* fall through */
285 	case IB_QPT_RC:
286 		size += sizeof(struct mlx5_wqe_ctrl_seg) +
287 			max(sizeof(struct mlx5_wqe_atomic_seg) +
288 			    sizeof(struct mlx5_wqe_raddr_seg),
289 			    sizeof(struct mlx5_wqe_umr_ctrl_seg) +
290 			    sizeof(struct mlx5_mkey_seg));
291 		break;
292 
293 	case IB_QPT_XRC_TGT:
294 		return 0;
295 
296 	case IB_QPT_UC:
297 		size += sizeof(struct mlx5_wqe_ctrl_seg) +
298 			max(sizeof(struct mlx5_wqe_raddr_seg),
299 			    sizeof(struct mlx5_wqe_umr_ctrl_seg) +
300 			    sizeof(struct mlx5_mkey_seg));
301 		break;
302 
303 	case IB_QPT_UD:
304 		if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
305 			size += sizeof(struct mlx5_wqe_eth_pad) +
306 				sizeof(struct mlx5_wqe_eth_seg);
307 		/* fall through */
308 	case IB_QPT_SMI:
309 	case MLX5_IB_QPT_HW_GSI:
310 		size += sizeof(struct mlx5_wqe_ctrl_seg) +
311 			sizeof(struct mlx5_wqe_datagram_seg);
312 		break;
313 
314 	case MLX5_IB_QPT_REG_UMR:
315 		size += sizeof(struct mlx5_wqe_ctrl_seg) +
316 			sizeof(struct mlx5_wqe_umr_ctrl_seg) +
317 			sizeof(struct mlx5_mkey_seg);
318 		break;
319 
320 	default:
321 		return -EINVAL;
322 	}
323 
324 	return size;
325 }
326 
327 static int calc_send_wqe(struct ib_qp_init_attr *attr)
328 {
329 	int inl_size = 0;
330 	int size;
331 
332 	size = sq_overhead(attr);
333 	if (size < 0)
334 		return size;
335 
336 	if (attr->cap.max_inline_data) {
337 		inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
338 			attr->cap.max_inline_data;
339 	}
340 
341 	size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
342 	if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
343 	    ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
344 			return MLX5_SIG_WQE_SIZE;
345 	else
346 		return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
347 }
348 
349 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
350 {
351 	int max_sge;
352 
353 	if (attr->qp_type == IB_QPT_RC)
354 		max_sge = (min_t(int, wqe_size, 512) -
355 			   sizeof(struct mlx5_wqe_ctrl_seg) -
356 			   sizeof(struct mlx5_wqe_raddr_seg)) /
357 			sizeof(struct mlx5_wqe_data_seg);
358 	else if (attr->qp_type == IB_QPT_XRC_INI)
359 		max_sge = (min_t(int, wqe_size, 512) -
360 			   sizeof(struct mlx5_wqe_ctrl_seg) -
361 			   sizeof(struct mlx5_wqe_xrc_seg) -
362 			   sizeof(struct mlx5_wqe_raddr_seg)) /
363 			sizeof(struct mlx5_wqe_data_seg);
364 	else
365 		max_sge = (wqe_size - sq_overhead(attr)) /
366 			sizeof(struct mlx5_wqe_data_seg);
367 
368 	return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
369 		     sizeof(struct mlx5_wqe_data_seg));
370 }
371 
372 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
373 			struct mlx5_ib_qp *qp)
374 {
375 	int wqe_size;
376 	int wq_size;
377 
378 	if (!attr->cap.max_send_wr)
379 		return 0;
380 
381 	wqe_size = calc_send_wqe(attr);
382 	mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
383 	if (wqe_size < 0)
384 		return wqe_size;
385 
386 	if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
387 		mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
388 			    wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
389 		return -EINVAL;
390 	}
391 
392 	qp->max_inline_data = wqe_size - sq_overhead(attr) -
393 			      sizeof(struct mlx5_wqe_inline_seg);
394 	attr->cap.max_inline_data = qp->max_inline_data;
395 
396 	if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
397 		qp->signature_en = true;
398 
399 	wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
400 	qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
401 	if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
402 		mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
403 			    qp->sq.wqe_cnt,
404 			    1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
405 		return -ENOMEM;
406 	}
407 	qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
408 	qp->sq.max_gs = get_send_sge(attr, wqe_size);
409 	if (qp->sq.max_gs < attr->cap.max_send_sge)
410 		return -ENOMEM;
411 
412 	attr->cap.max_send_sge = qp->sq.max_gs;
413 	qp->sq.max_post = wq_size / wqe_size;
414 	attr->cap.max_send_wr = qp->sq.max_post;
415 
416 	return wq_size;
417 }
418 
419 static int set_user_buf_size(struct mlx5_ib_dev *dev,
420 			    struct mlx5_ib_qp *qp,
421 			    struct mlx5_ib_create_qp *ucmd,
422 			    struct mlx5_ib_qp_base *base,
423 			    struct ib_qp_init_attr *attr)
424 {
425 	int desc_sz = 1 << qp->sq.wqe_shift;
426 
427 	if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
428 		mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
429 			     desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
430 		return -EINVAL;
431 	}
432 
433 	if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
434 		mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
435 			     ucmd->sq_wqe_count, ucmd->sq_wqe_count);
436 		return -EINVAL;
437 	}
438 
439 	qp->sq.wqe_cnt = ucmd->sq_wqe_count;
440 
441 	if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
442 		mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
443 			     qp->sq.wqe_cnt,
444 			     1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
445 		return -EINVAL;
446 	}
447 
448 	if (attr->qp_type == IB_QPT_RAW_PACKET) {
449 		base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
450 		qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
451 	} else {
452 		base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
453 					 (qp->sq.wqe_cnt << 6);
454 	}
455 
456 	return 0;
457 }
458 
459 static int qp_has_rq(struct ib_qp_init_attr *attr)
460 {
461 	if (attr->qp_type == IB_QPT_XRC_INI ||
462 	    attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
463 	    attr->qp_type == MLX5_IB_QPT_REG_UMR ||
464 	    !attr->cap.max_recv_wr)
465 		return 0;
466 
467 	return 1;
468 }
469 
470 enum {
471 	/* this is the first blue flame register in the array of bfregs assigned
472 	 * to a processes. Since we do not use it for blue flame but rather
473 	 * regular 64 bit doorbells, we do not need a lock for maintaiing
474 	 * "odd/even" order
475 	 */
476 	NUM_NON_BLUE_FLAME_BFREGS = 1,
477 };
478 
479 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
480 {
481 	return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
482 }
483 
484 static int num_med_bfreg(struct mlx5_ib_dev *dev,
485 			 struct mlx5_bfreg_info *bfregi)
486 {
487 	int n;
488 
489 	n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
490 	    NUM_NON_BLUE_FLAME_BFREGS;
491 
492 	return n >= 0 ? n : 0;
493 }
494 
495 static int first_med_bfreg(struct mlx5_ib_dev *dev,
496 			   struct mlx5_bfreg_info *bfregi)
497 {
498 	return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
499 }
500 
501 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
502 			  struct mlx5_bfreg_info *bfregi)
503 {
504 	int med;
505 
506 	med = num_med_bfreg(dev, bfregi);
507 	return ++med;
508 }
509 
510 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
511 				  struct mlx5_bfreg_info *bfregi)
512 {
513 	int i;
514 
515 	for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
516 		if (!bfregi->count[i]) {
517 			bfregi->count[i]++;
518 			return i;
519 		}
520 	}
521 
522 	return -ENOMEM;
523 }
524 
525 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
526 				 struct mlx5_bfreg_info *bfregi)
527 {
528 	int minidx = first_med_bfreg(dev, bfregi);
529 	int i;
530 
531 	if (minidx < 0)
532 		return minidx;
533 
534 	for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
535 		if (bfregi->count[i] < bfregi->count[minidx])
536 			minidx = i;
537 		if (!bfregi->count[minidx])
538 			break;
539 	}
540 
541 	bfregi->count[minidx]++;
542 	return minidx;
543 }
544 
545 static int alloc_bfreg(struct mlx5_ib_dev *dev,
546 		       struct mlx5_bfreg_info *bfregi)
547 {
548 	int bfregn = -ENOMEM;
549 
550 	if (bfregi->lib_uar_dyn)
551 		return -EINVAL;
552 
553 	mutex_lock(&bfregi->lock);
554 	if (bfregi->ver >= 2) {
555 		bfregn = alloc_high_class_bfreg(dev, bfregi);
556 		if (bfregn < 0)
557 			bfregn = alloc_med_class_bfreg(dev, bfregi);
558 	}
559 
560 	if (bfregn < 0) {
561 		BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
562 		bfregn = 0;
563 		bfregi->count[bfregn]++;
564 	}
565 	mutex_unlock(&bfregi->lock);
566 
567 	return bfregn;
568 }
569 
570 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
571 {
572 	mutex_lock(&bfregi->lock);
573 	bfregi->count[bfregn]--;
574 	mutex_unlock(&bfregi->lock);
575 }
576 
577 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
578 {
579 	switch (state) {
580 	case IB_QPS_RESET:	return MLX5_QP_STATE_RST;
581 	case IB_QPS_INIT:	return MLX5_QP_STATE_INIT;
582 	case IB_QPS_RTR:	return MLX5_QP_STATE_RTR;
583 	case IB_QPS_RTS:	return MLX5_QP_STATE_RTS;
584 	case IB_QPS_SQD:	return MLX5_QP_STATE_SQD;
585 	case IB_QPS_SQE:	return MLX5_QP_STATE_SQER;
586 	case IB_QPS_ERR:	return MLX5_QP_STATE_ERR;
587 	default:		return -1;
588 	}
589 }
590 
591 static int to_mlx5_st(enum ib_qp_type type)
592 {
593 	switch (type) {
594 	case IB_QPT_RC:			return MLX5_QP_ST_RC;
595 	case IB_QPT_UC:			return MLX5_QP_ST_UC;
596 	case IB_QPT_UD:			return MLX5_QP_ST_UD;
597 	case MLX5_IB_QPT_REG_UMR:	return MLX5_QP_ST_REG_UMR;
598 	case IB_QPT_XRC_INI:
599 	case IB_QPT_XRC_TGT:		return MLX5_QP_ST_XRC;
600 	case IB_QPT_SMI:		return MLX5_QP_ST_QP0;
601 	case MLX5_IB_QPT_HW_GSI:	return MLX5_QP_ST_QP1;
602 	case IB_QPT_RAW_IPV6:		return MLX5_QP_ST_RAW_IPV6;
603 	case IB_QPT_RAW_PACKET:
604 	case IB_QPT_RAW_ETHERTYPE:	return MLX5_QP_ST_RAW_ETHERTYPE;
605 	case IB_QPT_MAX:
606 	default:		return -EINVAL;
607 	}
608 }
609 
610 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
611 			     struct mlx5_ib_cq *recv_cq);
612 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
613 			       struct mlx5_ib_cq *recv_cq);
614 
615 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
616 			struct mlx5_bfreg_info *bfregi, u32 bfregn,
617 			bool dyn_bfreg)
618 {
619 	unsigned int bfregs_per_sys_page;
620 	u32 index_of_sys_page;
621 	u32 offset;
622 
623 	if (bfregi->lib_uar_dyn)
624 		return -EINVAL;
625 
626 	bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
627 				MLX5_NON_FP_BFREGS_PER_UAR;
628 	index_of_sys_page = bfregn / bfregs_per_sys_page;
629 
630 	if (dyn_bfreg) {
631 		index_of_sys_page += bfregi->num_static_sys_pages;
632 
633 		if (index_of_sys_page >= bfregi->num_sys_pages)
634 			return -EINVAL;
635 
636 		if (bfregn > bfregi->num_dyn_bfregs ||
637 		    bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
638 			mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
639 			return -EINVAL;
640 		}
641 	}
642 
643 	offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
644 	return bfregi->sys_pages[index_of_sys_page] + offset;
645 }
646 
647 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
648 			    struct ib_pd *pd,
649 			    unsigned long addr, size_t size,
650 			    struct ib_umem **umem,
651 			    int *npages, int *page_shift, int *ncont,
652 			    u32 *offset)
653 {
654 	int err;
655 
656 	*umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
657 	if (IS_ERR(*umem)) {
658 		mlx5_ib_dbg(dev, "umem_get failed\n");
659 		return PTR_ERR(*umem);
660 	}
661 
662 	mlx5_ib_cont_pages(*umem, addr, npages, page_shift, ncont, NULL);
663 
664 	err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
665 	if (err) {
666 		mlx5_ib_warn(dev, "bad offset\n");
667 		goto err_umem;
668 	}
669 
670 	mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
671 		    addr, size, *npages, *page_shift, *ncont, *offset);
672 
673 	return 0;
674 
675 err_umem:
676 	ib_umem_release(*umem);
677 	*umem = NULL;
678 
679 	return err;
680 }
681 
682 static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq)
683 {
684 	struct mlx5_ib_ucontext *context;
685 
686 	context = to_mucontext(pd->uobject->context);
687 	mlx5_ib_db_unmap_user(context, &rwq->db);
688 	if (rwq->umem)
689 		ib_umem_release(rwq->umem);
690 }
691 
692 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
693 			  struct mlx5_ib_rwq *rwq,
694 			  struct mlx5_ib_create_wq *ucmd)
695 {
696 	struct mlx5_ib_ucontext *context;
697 	int page_shift = 0;
698 	int npages;
699 	u32 offset = 0;
700 	int ncont = 0;
701 	int err;
702 
703 	if (!ucmd->buf_addr)
704 		return -EINVAL;
705 
706 	context = to_mucontext(pd->uobject->context);
707 	rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
708 			       rwq->buf_size, 0, 0);
709 	if (IS_ERR(rwq->umem)) {
710 		mlx5_ib_dbg(dev, "umem_get failed\n");
711 		err = PTR_ERR(rwq->umem);
712 		return err;
713 	}
714 
715 	mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, &npages, &page_shift,
716 			   &ncont, NULL);
717 	err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
718 				     &rwq->rq_page_offset);
719 	if (err) {
720 		mlx5_ib_warn(dev, "bad offset\n");
721 		goto err_umem;
722 	}
723 
724 	rwq->rq_num_pas = ncont;
725 	rwq->page_shift = page_shift;
726 	rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
727 	rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
728 
729 	mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
730 		    (unsigned long long)ucmd->buf_addr, rwq->buf_size,
731 		    npages, page_shift, ncont, offset);
732 
733 	err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
734 	if (err) {
735 		mlx5_ib_dbg(dev, "map failed\n");
736 		goto err_umem;
737 	}
738 
739 	rwq->create_type = MLX5_WQ_USER;
740 	return 0;
741 
742 err_umem:
743 	ib_umem_release(rwq->umem);
744 	return err;
745 }
746 
747 static int adjust_bfregn(struct mlx5_ib_dev *dev,
748 			 struct mlx5_bfreg_info *bfregi, int bfregn)
749 {
750 	return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
751 				bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
752 }
753 
754 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
755 			  struct mlx5_ib_qp *qp, struct ib_udata *udata,
756 			  struct ib_qp_init_attr *attr,
757 			  u32 **in,
758 			  struct mlx5_ib_create_qp_resp *resp, int *inlen,
759 			  struct mlx5_ib_qp_base *base)
760 {
761 	struct mlx5_ib_ucontext *context;
762 	struct mlx5_ib_create_qp ucmd;
763 	struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
764 	int page_shift = 0;
765 	int uar_index = 0;
766 	int npages;
767 	u32 offset = 0;
768 	int bfregn;
769 	int ncont = 0;
770 	__be64 *pas;
771 	void *qpc;
772 	int err;
773 	u32 uar_flags;
774 
775 	err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
776 	if (err) {
777 		mlx5_ib_dbg(dev, "copy failed\n");
778 		return err;
779 	}
780 
781 	context = to_mucontext(pd->uobject->context);
782 	uar_flags = ucmd.flags & (MLX5_QP_FLAG_UAR_PAGE_INDEX |
783 				  MLX5_QP_FLAG_BFREG_INDEX);
784 	switch (uar_flags) {
785 	case MLX5_QP_FLAG_UAR_PAGE_INDEX:
786 		uar_index = ucmd.bfreg_index;
787 		bfregn = MLX5_IB_INVALID_BFREG;
788 		break;
789 	case MLX5_QP_FLAG_BFREG_INDEX:
790 		uar_index = bfregn_to_uar_index(dev, &context->bfregi,
791 						ucmd.bfreg_index, true);
792 		if (uar_index < 0)
793 			return uar_index;
794 		bfregn = MLX5_IB_INVALID_BFREG;
795 		break;
796 	case 0:
797 		if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
798 			return -EINVAL;
799 		bfregn = alloc_bfreg(dev, &context->bfregi);
800 		if (bfregn < 0)
801 			return bfregn;
802 		break;
803 	default:
804 		return -EINVAL;
805 	}
806 
807 	mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
808 	if (bfregn != MLX5_IB_INVALID_BFREG)
809 		uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
810 						false);
811 
812 	qp->rq.offset = 0;
813 	qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
814 	qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
815 
816 	err = set_user_buf_size(dev, qp, &ucmd, base, attr);
817 	if (err)
818 		goto err_bfreg;
819 
820 	if (ucmd.buf_addr && ubuffer->buf_size) {
821 		ubuffer->buf_addr = ucmd.buf_addr;
822 		err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
823 				       ubuffer->buf_size,
824 				       &ubuffer->umem, &npages, &page_shift,
825 				       &ncont, &offset);
826 		if (err)
827 			goto err_bfreg;
828 	} else {
829 		ubuffer->umem = NULL;
830 	}
831 
832 	*inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
833 		 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
834 	*in = mlx5_vzalloc(*inlen);
835 	if (!*in) {
836 		err = -ENOMEM;
837 		goto err_umem;
838 	}
839 
840 	pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
841 	if (ubuffer->umem)
842 		mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
843 
844 	qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
845 
846 	MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
847 	MLX5_SET(qpc, qpc, page_offset, offset);
848 
849 	MLX5_SET(qpc, qpc, uar_page, uar_index);
850 	if (bfregn != MLX5_IB_INVALID_BFREG)
851 		resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
852 	else
853 		resp->bfreg_index = MLX5_IB_INVALID_BFREG;
854 	qp->bfregn = bfregn;
855 
856 	err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
857 	if (err) {
858 		mlx5_ib_dbg(dev, "map failed\n");
859 		goto err_free;
860 	}
861 
862 	err = ib_copy_to_udata(udata, resp, sizeof(*resp));
863 	if (err) {
864 		mlx5_ib_dbg(dev, "copy failed\n");
865 		goto err_unmap;
866 	}
867 	qp->create_type = MLX5_QP_USER;
868 
869 	return 0;
870 
871 err_unmap:
872 	mlx5_ib_db_unmap_user(context, &qp->db);
873 
874 err_free:
875 	kvfree(*in);
876 
877 err_umem:
878 	if (ubuffer->umem)
879 		ib_umem_release(ubuffer->umem);
880 
881 err_bfreg:
882 	if (bfregn != MLX5_IB_INVALID_BFREG)
883 		mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
884 	return err;
885 }
886 
887 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd, struct mlx5_ib_qp *qp,
888 			    struct mlx5_ib_qp_base *base)
889 {
890 	struct mlx5_ib_ucontext *context;
891 
892 	context = to_mucontext(pd->uobject->context);
893 	mlx5_ib_db_unmap_user(context, &qp->db);
894 	if (base->ubuffer.umem)
895 		ib_umem_release(base->ubuffer.umem);
896 
897 	/*
898 	 * Free only the BFREGs which are handled by the kernel.
899 	 * BFREGs of UARs allocated dynamically are handled by user.
900 	 */
901 	if (qp->bfregn != MLX5_IB_INVALID_BFREG)
902 		mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
903 }
904 
905 static int create_kernel_qp(struct mlx5_ib_dev *dev,
906 			    struct ib_qp_init_attr *init_attr,
907 			    struct mlx5_ib_qp *qp,
908 			    u32 **in, int *inlen,
909 			    struct mlx5_ib_qp_base *base)
910 {
911 	int uar_index;
912 	void *qpc;
913 	int err;
914 
915 	if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
916 					IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
917 					IB_QP_CREATE_IPOIB_UD_LSO |
918 					MLX5_IB_QP_CREATE_SQPN_QP1 |
919 					MLX5_IB_QP_CREATE_WC_TEST))
920 		return -EINVAL;
921 
922 	spin_lock_init(&qp->bf.lock32);
923 
924 	if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
925 		qp->bf.bfreg = &dev->fp_bfreg;
926 	else if (init_attr->create_flags & MLX5_IB_QP_CREATE_WC_TEST)
927 		qp->bf.bfreg = &dev->wc_bfreg;
928 	else
929 		qp->bf.bfreg = &dev->bfreg;
930 
931 	/* We need to divide by two since each register is comprised of
932 	 * two buffers of identical size, namely odd and even
933 	 */
934 	qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
935 	uar_index = qp->bf.bfreg->index;
936 
937 	err = calc_sq_size(dev, init_attr, qp);
938 	if (err < 0) {
939 		mlx5_ib_dbg(dev, "err %d\n", err);
940 		return err;
941 	}
942 
943 	qp->rq.offset = 0;
944 	qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
945 	base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
946 
947 	err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size,
948 	    2 * PAGE_SIZE, &qp->buf);
949 	if (err) {
950 		mlx5_ib_dbg(dev, "err %d\n", err);
951 		return err;
952 	}
953 
954 	qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
955 	*inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
956 		 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
957 	*in = mlx5_vzalloc(*inlen);
958 	if (!*in) {
959 		err = -ENOMEM;
960 		goto err_buf;
961 	}
962 
963 	qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
964 	MLX5_SET(qpc, qpc, uar_page, uar_index);
965 	MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
966 
967 	/* Set "fast registration enabled" for all kernel QPs */
968 	MLX5_SET(qpc, qpc, fre, 1);
969 	MLX5_SET(qpc, qpc, rlky, 1);
970 
971 	if (init_attr->create_flags & MLX5_IB_QP_CREATE_SQPN_QP1) {
972 		MLX5_SET(qpc, qpc, deth_sqpn, 1);
973 		qp->flags |= MLX5_IB_QP_SQPN_QP1;
974 	}
975 
976 	mlx5_fill_page_array(&qp->buf,
977 			     (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
978 
979 	err = mlx5_db_alloc(dev->mdev, &qp->db);
980 	if (err) {
981 		mlx5_ib_dbg(dev, "err %d\n", err);
982 		goto err_free;
983 	}
984 
985 	qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
986 	qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
987 	qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
988 	qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
989 	qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
990 
991 	if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
992 	    !qp->sq.w_list || !qp->sq.wqe_head) {
993 		err = -ENOMEM;
994 		goto err_wrid;
995 	}
996 	qp->create_type = MLX5_QP_KERNEL;
997 
998 	return 0;
999 
1000 err_wrid:
1001 	kfree(qp->sq.wqe_head);
1002 	kfree(qp->sq.w_list);
1003 	kfree(qp->sq.wrid);
1004 	kfree(qp->sq.wr_data);
1005 	kfree(qp->rq.wrid);
1006 	mlx5_db_free(dev->mdev, &qp->db);
1007 
1008 err_free:
1009 	kvfree(*in);
1010 
1011 err_buf:
1012 	mlx5_buf_free(dev->mdev, &qp->buf);
1013 	return err;
1014 }
1015 
1016 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1017 {
1018 	kfree(qp->sq.wqe_head);
1019 	kfree(qp->sq.w_list);
1020 	kfree(qp->sq.wrid);
1021 	kfree(qp->sq.wr_data);
1022 	kfree(qp->rq.wrid);
1023 	mlx5_db_free(dev->mdev, &qp->db);
1024 	mlx5_buf_free(dev->mdev, &qp->buf);
1025 }
1026 
1027 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1028 {
1029 	if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1030 	    (attr->qp_type == IB_QPT_XRC_INI))
1031 		return MLX5_SRQ_RQ;
1032 	else if (!qp->has_rq)
1033 		return MLX5_ZERO_LEN_RQ;
1034 	else
1035 		return MLX5_NON_ZERO_RQ;
1036 }
1037 
1038 static int is_connected(enum ib_qp_type qp_type)
1039 {
1040 	if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1041 		return 1;
1042 
1043 	return 0;
1044 }
1045 
1046 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1047 				    struct mlx5_ib_sq *sq, u32 tdn)
1048 {
1049 	u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1050 	void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1051 
1052 	MLX5_SET(tisc, tisc, transport_domain, tdn);
1053 	return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1054 }
1055 
1056 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1057 				      struct mlx5_ib_sq *sq)
1058 {
1059 	mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1060 }
1061 
1062 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1063 				   struct mlx5_ib_sq *sq, void *qpin,
1064 				   struct ib_pd *pd)
1065 {
1066 	struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1067 	__be64 *pas;
1068 	void *in;
1069 	void *sqc;
1070 	void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1071 	void *wq;
1072 	int inlen;
1073 	int err;
1074 	int page_shift = 0;
1075 	int npages;
1076 	int ncont = 0;
1077 	u32 offset = 0;
1078 
1079 	err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1080 			       &sq->ubuffer.umem, &npages, &page_shift,
1081 			       &ncont, &offset);
1082 	if (err)
1083 		return err;
1084 
1085 	inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1086 	in = mlx5_vzalloc(inlen);
1087 	if (!in) {
1088 		err = -ENOMEM;
1089 		goto err_umem;
1090 	}
1091 
1092 	sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1093 	MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1094 	MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1095 	MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1096 	MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1097 	MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1098 	MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1099 
1100 	wq = MLX5_ADDR_OF(sqc, sqc, wq);
1101 	MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1102 	MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1103 	MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1104 	MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1105 	MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1106 	MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1107 	MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1108 	MLX5_SET(wq, wq, page_offset, offset);
1109 
1110 	pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1111 	mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1112 
1113 	err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1114 
1115 	kvfree(in);
1116 
1117 	if (err)
1118 		goto err_umem;
1119 
1120 	return 0;
1121 
1122 err_umem:
1123 	ib_umem_release(sq->ubuffer.umem);
1124 	sq->ubuffer.umem = NULL;
1125 
1126 	return err;
1127 }
1128 
1129 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1130 				     struct mlx5_ib_sq *sq)
1131 {
1132 	mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1133 	ib_umem_release(sq->ubuffer.umem);
1134 }
1135 
1136 static int get_rq_pas_size(void *qpc)
1137 {
1138 	u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1139 	u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1140 	u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1141 	u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1142 	u32 po_quanta	  = 1 << (log_page_size - 6);
1143 	u32 rq_sz	  = 1 << (log_rq_size + 4 + log_rq_stride);
1144 	u32 page_size	  = 1 << log_page_size;
1145 	u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1146 	u32 rq_num_pas	  = (rq_sz_po + page_size - 1) / page_size;
1147 
1148 	return rq_num_pas * sizeof(u64);
1149 }
1150 
1151 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1152 				   struct mlx5_ib_rq *rq, void *qpin)
1153 {
1154 	struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1155 	__be64 *pas;
1156 	__be64 *qp_pas;
1157 	void *in;
1158 	void *rqc;
1159 	void *wq;
1160 	void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1161 	int inlen;
1162 	int err;
1163 	u32 rq_pas_size = get_rq_pas_size(qpc);
1164 
1165 	inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1166 	in = mlx5_vzalloc(inlen);
1167 	if (!in)
1168 		return -ENOMEM;
1169 
1170 	rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1171 	MLX5_SET(rqc, rqc, vlan_strip_disable, 1);
1172 	MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE);
1173 	MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1174 	MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1175 	MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1176 	MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1177 
1178 	if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1179 		MLX5_SET(rqc, rqc, scatter_fcs, 1);
1180 
1181 	wq = MLX5_ADDR_OF(rqc, rqc, wq);
1182 	MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1183 	MLX5_SET(wq, wq, end_padding_mode,
1184 		 MLX5_GET(qpc, qpc, end_padding_mode));
1185 	MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1186 	MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1187 	MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1188 	MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1189 	MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1190 	MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1191 
1192 	pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1193 	qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1194 	memcpy(pas, qp_pas, rq_pas_size);
1195 
1196 	err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1197 
1198 	kvfree(in);
1199 
1200 	return err;
1201 }
1202 
1203 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1204 				     struct mlx5_ib_rq *rq)
1205 {
1206 	mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1207 }
1208 
1209 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1210 				    struct mlx5_ib_rq *rq, u32 tdn)
1211 {
1212 	u32 *in;
1213 	void *tirc;
1214 	int inlen;
1215 	int err;
1216 
1217 	inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1218 	in = mlx5_vzalloc(inlen);
1219 	if (!in)
1220 		return -ENOMEM;
1221 
1222 	tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
1223 	MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1224 	MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1225 	MLX5_SET(tirc, tirc, transport_domain, tdn);
1226 
1227 	err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1228 
1229 	kvfree(in);
1230 
1231 	return err;
1232 }
1233 
1234 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1235 				      struct mlx5_ib_rq *rq)
1236 {
1237 	mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1238 }
1239 
1240 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1241 				u32 *in,
1242 				struct ib_pd *pd)
1243 {
1244 	struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1245 	struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1246 	struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1247 	struct ib_uobject *uobj = pd->uobject;
1248 	struct ib_ucontext *ucontext = uobj->context;
1249 	struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1250 	int err;
1251 	u32 tdn = mucontext->tdn;
1252 
1253 	if (qp->sq.wqe_cnt) {
1254 		err = create_raw_packet_qp_tis(dev, sq, tdn);
1255 		if (err)
1256 			return err;
1257 
1258 		err = create_raw_packet_qp_sq(dev, sq, in, pd);
1259 		if (err)
1260 			goto err_destroy_tis;
1261 
1262 		sq->base.container_mibqp = qp;
1263 	}
1264 
1265 	if (qp->rq.wqe_cnt) {
1266 		rq->base.container_mibqp = qp;
1267 
1268 		err = create_raw_packet_qp_rq(dev, rq, in);
1269 		if (err)
1270 			goto err_destroy_sq;
1271 
1272 
1273 		err = create_raw_packet_qp_tir(dev, rq, tdn);
1274 		if (err)
1275 			goto err_destroy_rq;
1276 	}
1277 
1278 	qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1279 						     rq->base.mqp.qpn;
1280 
1281 	return 0;
1282 
1283 err_destroy_rq:
1284 	destroy_raw_packet_qp_rq(dev, rq);
1285 err_destroy_sq:
1286 	if (!qp->sq.wqe_cnt)
1287 		return err;
1288 	destroy_raw_packet_qp_sq(dev, sq);
1289 err_destroy_tis:
1290 	destroy_raw_packet_qp_tis(dev, sq);
1291 
1292 	return err;
1293 }
1294 
1295 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1296 				  struct mlx5_ib_qp *qp)
1297 {
1298 	struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1299 	struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1300 	struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1301 
1302 	if (qp->rq.wqe_cnt) {
1303 		destroy_raw_packet_qp_tir(dev, rq);
1304 		destroy_raw_packet_qp_rq(dev, rq);
1305 	}
1306 
1307 	if (qp->sq.wqe_cnt) {
1308 		destroy_raw_packet_qp_sq(dev, sq);
1309 		destroy_raw_packet_qp_tis(dev, sq);
1310 	}
1311 }
1312 
1313 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1314 				    struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1315 {
1316 	struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1317 	struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1318 
1319 	sq->sq = &qp->sq;
1320 	rq->rq = &qp->rq;
1321 	sq->doorbell = &qp->db;
1322 	rq->doorbell = &qp->db;
1323 }
1324 
1325 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1326 {
1327 	mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1328 }
1329 
1330 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1331 				 struct ib_pd *pd,
1332 				 struct ib_qp_init_attr *init_attr,
1333 				 struct ib_udata *udata)
1334 {
1335 	struct ib_uobject *uobj = pd->uobject;
1336 	struct ib_ucontext *ucontext = uobj->context;
1337 	struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1338 	struct mlx5_ib_create_qp_resp resp = {};
1339 	int inlen;
1340 	int err;
1341 	u32 *in;
1342 	void *tirc;
1343 	void *hfso;
1344 	u32 selected_fields = 0;
1345 	size_t min_resp_len;
1346 	u32 tdn = mucontext->tdn;
1347 	struct mlx5_ib_create_qp_rss ucmd = {};
1348 	size_t required_cmd_sz;
1349 
1350 	if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1351 		return -EOPNOTSUPP;
1352 
1353 	if (init_attr->create_flags || init_attr->send_cq)
1354 		return -EINVAL;
1355 
1356 	min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1357 	if (udata->outlen < min_resp_len)
1358 		return -EINVAL;
1359 
1360 	required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1);
1361 	if (udata->inlen < required_cmd_sz) {
1362 		mlx5_ib_dbg(dev, "invalid inlen\n");
1363 		return -EINVAL;
1364 	}
1365 
1366 	if (udata->inlen > sizeof(ucmd) &&
1367 	    !ib_is_udata_cleared(udata, sizeof(ucmd),
1368 				 udata->inlen - sizeof(ucmd))) {
1369 		mlx5_ib_dbg(dev, "inlen is not supported\n");
1370 		return -EOPNOTSUPP;
1371 	}
1372 
1373 	if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1374 		mlx5_ib_dbg(dev, "copy failed\n");
1375 		return -EFAULT;
1376 	}
1377 
1378 	if (ucmd.comp_mask) {
1379 		mlx5_ib_dbg(dev, "invalid comp mask\n");
1380 		return -EOPNOTSUPP;
1381 	}
1382 
1383 	if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) {
1384 		mlx5_ib_dbg(dev, "invalid reserved\n");
1385 		return -EOPNOTSUPP;
1386 	}
1387 
1388 	err = ib_copy_to_udata(udata, &resp, min_resp_len);
1389 	if (err) {
1390 		mlx5_ib_dbg(dev, "copy failed\n");
1391 		return -EINVAL;
1392 	}
1393 
1394 	inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1395 	in = mlx5_vzalloc(inlen);
1396 	if (!in)
1397 		return -ENOMEM;
1398 
1399 	tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
1400 	MLX5_SET(tirc, tirc, disp_type,
1401 		 MLX5_TIRC_DISP_TYPE_INDIRECT);
1402 	MLX5_SET(tirc, tirc, indirect_table,
1403 		 init_attr->rwq_ind_tbl->ind_tbl_num);
1404 	MLX5_SET(tirc, tirc, transport_domain, tdn);
1405 
1406 	hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1407 	switch (ucmd.rx_hash_function) {
1408 	case MLX5_RX_HASH_FUNC_TOEPLITZ:
1409 	{
1410 		void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1411 		size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1412 
1413 		if (len != ucmd.rx_key_len) {
1414 			err = -EINVAL;
1415 			goto err;
1416 		}
1417 
1418 		MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FUNC_TOEPLITZ);
1419 		MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1420 		memcpy(rss_key, ucmd.rx_hash_key, len);
1421 		break;
1422 	}
1423 	default:
1424 		err = -EOPNOTSUPP;
1425 		goto err;
1426 	}
1427 
1428 	if (!ucmd.rx_hash_fields_mask) {
1429 		/* special case when this TIR serves as steering entry without hashing */
1430 		if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1431 			goto create_tir;
1432 		err = -EINVAL;
1433 		goto err;
1434 	}
1435 
1436 	if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1437 	     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1438 	     ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1439 	     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1440 		err = -EINVAL;
1441 		goto err;
1442 	}
1443 
1444 	/* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1445 	if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1446 	    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1447 		MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1448 			 MLX5_L3_PROT_TYPE_IPV4);
1449 	else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1450 		 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1451 		MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1452 			 MLX5_L3_PROT_TYPE_IPV6);
1453 
1454 	if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1455 	     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1456 	     ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1457 	     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1458 		err = -EINVAL;
1459 		goto err;
1460 	}
1461 
1462 	/* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1463 	if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1464 	    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1465 		MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1466 			 MLX5_L4_PROT_TYPE_TCP);
1467 	else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1468 		 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1469 		MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1470 			 MLX5_L4_PROT_TYPE_UDP);
1471 
1472 	if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1473 	    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1474 		selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1475 
1476 	if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1477 	    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1478 		selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1479 
1480 	if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1481 	    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1482 		selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1483 
1484 	if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1485 	    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1486 		selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1487 
1488 	MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1489 
1490 create_tir:
1491 	err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1492 
1493 	if (err)
1494 		goto err;
1495 
1496 	kvfree(in);
1497 	/* qpn is reserved for that QP */
1498 	qp->trans_qp.base.mqp.qpn = 0;
1499 	qp->flags |= MLX5_IB_QP_RSS;
1500 	return 0;
1501 
1502 err:
1503 	kvfree(in);
1504 	return err;
1505 }
1506 
1507 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1508 			    struct ib_qp_init_attr *init_attr,
1509 			    struct ib_udata *udata, struct mlx5_ib_qp *qp)
1510 {
1511 	struct mlx5_ib_resources *devr = &dev->devr;
1512 	int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1513 	struct mlx5_core_dev *mdev = dev->mdev;
1514 	struct mlx5_ib_create_qp_resp resp;
1515 	struct mlx5_ib_cq *send_cq;
1516 	struct mlx5_ib_cq *recv_cq;
1517 	unsigned long flags;
1518 	u32 uidx = MLX5_IB_DEFAULT_UIDX;
1519 	struct mlx5_ib_create_qp ucmd;
1520 	struct mlx5_ib_qp_base *base;
1521 	void *qpc;
1522 	u32 *in;
1523 	int err;
1524 
1525 	base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1526 	       &qp->raw_packet_qp.rq.base :
1527 	       &qp->trans_qp.base;
1528 
1529 	if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1530 		mlx5_ib_odp_create_qp(qp);
1531 
1532 	mutex_init(&qp->mutex);
1533 	spin_lock_init(&qp->sq.lock);
1534 	spin_lock_init(&qp->rq.lock);
1535 
1536 	if (init_attr->rwq_ind_tbl) {
1537 		if (!udata)
1538 			return -ENOSYS;
1539 
1540 		err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1541 		return err;
1542 	}
1543 
1544 	if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1545 		if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1546 			mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1547 			return -EINVAL;
1548 		} else {
1549 			qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1550 		}
1551 	}
1552 
1553 	if (init_attr->create_flags &
1554 			(IB_QP_CREATE_CROSS_CHANNEL |
1555 			 IB_QP_CREATE_MANAGED_SEND |
1556 			 IB_QP_CREATE_MANAGED_RECV)) {
1557 		if (!MLX5_CAP_GEN(mdev, cd)) {
1558 			mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1559 			return -EINVAL;
1560 		}
1561 		if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1562 			qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1563 		if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1564 			qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1565 		if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1566 			qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1567 	}
1568 
1569 	if (init_attr->qp_type == IB_QPT_UD &&
1570 	    (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1571 		if (!MLX5_CAP_GEN(mdev, ipoib_ipoib_offloads)) {
1572 			mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1573 			return -EOPNOTSUPP;
1574 		}
1575 
1576 	if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1577 		if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1578 			mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1579 			return -EOPNOTSUPP;
1580 		}
1581 		if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1582 		    !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1583 			mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1584 			return -EOPNOTSUPP;
1585 		}
1586 		qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1587 	}
1588 
1589 	if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1590 		qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1591 
1592 	if (pd && pd->uobject) {
1593 		if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1594 			mlx5_ib_dbg(dev, "copy failed\n");
1595 			return -EFAULT;
1596 		}
1597 
1598 		err = get_qp_user_index(to_mucontext(pd->uobject->context),
1599 					&ucmd, udata->inlen, &uidx);
1600 		if (err)
1601 			return err;
1602 
1603 		qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1604 		qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1605 	} else {
1606 		qp->wq_sig = !!wq_signature;
1607 	}
1608 
1609 	qp->has_rq = qp_has_rq(init_attr);
1610 	err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1611 			  qp, (pd && pd->uobject) ? &ucmd : NULL);
1612 	if (err) {
1613 		mlx5_ib_dbg(dev, "err %d\n", err);
1614 		return err;
1615 	}
1616 
1617 	if (pd) {
1618 		if (pd->uobject) {
1619 			__u32 max_wqes =
1620 				1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1621 			mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1622 			if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1623 			    ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1624 				mlx5_ib_dbg(dev, "invalid rq params\n");
1625 				return -EINVAL;
1626 			}
1627 			if (ucmd.sq_wqe_count > max_wqes) {
1628 				mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1629 					    ucmd.sq_wqe_count, max_wqes);
1630 				return -EINVAL;
1631 			}
1632 			if (init_attr->create_flags &
1633 			    MLX5_IB_QP_CREATE_SQPN_QP1) {
1634 				mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1635 				return -EINVAL;
1636 			}
1637 			err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1638 					     &resp, &inlen, base);
1639 			if (err)
1640 				mlx5_ib_dbg(dev, "err %d\n", err);
1641 		} else {
1642 			err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1643 					       base);
1644 			if (err)
1645 				mlx5_ib_dbg(dev, "err %d\n", err);
1646 		}
1647 
1648 		if (err)
1649 			return err;
1650 	} else {
1651 		in = mlx5_vzalloc(inlen);
1652 		if (!in)
1653 			return -ENOMEM;
1654 
1655 		qp->create_type = MLX5_QP_EMPTY;
1656 	}
1657 
1658 	if (is_sqp(init_attr->qp_type))
1659 		qp->port = init_attr->port_num;
1660 
1661 	qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1662 
1663 	MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type));
1664 	MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1665 
1666 	if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1667 		MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1668 	else
1669 		MLX5_SET(qpc, qpc, latency_sensitive, 1);
1670 
1671 
1672 	if (qp->wq_sig)
1673 		MLX5_SET(qpc, qpc, wq_signature, 1);
1674 
1675 	if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1676 		MLX5_SET(qpc, qpc, block_lb_mc, 1);
1677 
1678 	if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1679 		MLX5_SET(qpc, qpc, cd_master, 1);
1680 	if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1681 		MLX5_SET(qpc, qpc, cd_slave_send, 1);
1682 	if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1683 		MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1684 
1685 	if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1686 		int rcqe_sz;
1687 		int scqe_sz;
1688 
1689 		rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1690 		scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1691 
1692 		if (rcqe_sz == 128)
1693 			MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1694 		else
1695 			MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1696 
1697 		if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1698 			if (scqe_sz == 128)
1699 				MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1700 			else
1701 				MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1702 		}
1703 	}
1704 
1705 	if (qp->rq.wqe_cnt) {
1706 		MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1707 		MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1708 	}
1709 
1710 	MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1711 
1712 	if (qp->sq.wqe_cnt)
1713 		MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1714 	else
1715 		MLX5_SET(qpc, qpc, no_sq, 1);
1716 
1717 	/* Set default resources */
1718 	switch (init_attr->qp_type) {
1719 	case IB_QPT_XRC_TGT:
1720 		MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1721 		MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1722 		MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s0)->msrq.srqn);
1723 		MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1724 		break;
1725 	case IB_QPT_XRC_INI:
1726 		MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1727 		MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1728 		MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s0)->msrq.srqn);
1729 		break;
1730 	default:
1731 		if (init_attr->srq) {
1732 			MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1733 			MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(init_attr->srq)->msrq.srqn);
1734 		} else {
1735 			MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1736 			MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s1)->msrq.srqn);
1737 		}
1738 	}
1739 
1740 	if (init_attr->send_cq)
1741 		MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1742 
1743 	if (init_attr->recv_cq)
1744 		MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1745 
1746 	MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1747 
1748 	/* 0xffffff means we ask to work with cqe version 0 */
1749 	if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1750 		MLX5_SET(qpc, qpc, user_index, uidx);
1751 
1752 	/* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1753 	if (init_attr->qp_type == IB_QPT_UD &&
1754 	    (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1755 		MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1756 		qp->flags |= MLX5_IB_QP_LSO;
1757 	}
1758 
1759 	if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1760 		qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1761 		raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1762 		err = create_raw_packet_qp(dev, qp, in, pd);
1763 	} else {
1764 		err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1765 	}
1766 
1767 	if (err) {
1768 		mlx5_ib_dbg(dev, "create qp failed\n");
1769 		goto err_create;
1770 	}
1771 
1772 	kvfree(in);
1773 
1774 	base->container_mibqp = qp;
1775 	base->mqp.event = mlx5_ib_qp_event;
1776 
1777 	get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1778 		&send_cq, &recv_cq);
1779 	spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1780 	mlx5_ib_lock_cqs(send_cq, recv_cq);
1781 	/* Maintain device to QPs access, needed for further handling via reset
1782 	 * flow
1783 	 */
1784 	list_add_tail(&qp->qps_list, &dev->qp_list);
1785 	/* Maintain CQ to QPs access, needed for further handling via reset flow
1786 	 */
1787 	if (send_cq)
1788 		list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1789 	if (recv_cq)
1790 		list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1791 	mlx5_ib_unlock_cqs(send_cq, recv_cq);
1792 	spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1793 
1794 	return 0;
1795 
1796 err_create:
1797 	if (qp->create_type == MLX5_QP_USER)
1798 		destroy_qp_user(dev, pd, qp, base);
1799 	else if (qp->create_type == MLX5_QP_KERNEL)
1800 		destroy_qp_kernel(dev, qp);
1801 
1802 	kvfree(in);
1803 	return err;
1804 }
1805 
1806 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1807 	__acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1808 {
1809 	if (send_cq) {
1810 		if (recv_cq) {
1811 			if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1812 				spin_lock(&send_cq->lock);
1813 				spin_lock_nested(&recv_cq->lock,
1814 						 SINGLE_DEPTH_NESTING);
1815 			} else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1816 				spin_lock(&send_cq->lock);
1817 				__acquire(&recv_cq->lock);
1818 			} else {
1819 				spin_lock(&recv_cq->lock);
1820 				spin_lock_nested(&send_cq->lock,
1821 						 SINGLE_DEPTH_NESTING);
1822 			}
1823 		} else {
1824 			spin_lock(&send_cq->lock);
1825 			__acquire(&recv_cq->lock);
1826 		}
1827 	} else if (recv_cq) {
1828 		spin_lock(&recv_cq->lock);
1829 		__acquire(&send_cq->lock);
1830 	} else {
1831 		__acquire(&send_cq->lock);
1832 		__acquire(&recv_cq->lock);
1833 	}
1834 }
1835 
1836 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1837 	__releases(&send_cq->lock) __releases(&recv_cq->lock)
1838 {
1839 	if (send_cq) {
1840 		if (recv_cq) {
1841 			if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1842 				spin_unlock(&recv_cq->lock);
1843 				spin_unlock(&send_cq->lock);
1844 			} else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1845 				__release(&recv_cq->lock);
1846 				spin_unlock(&send_cq->lock);
1847 			} else {
1848 				spin_unlock(&send_cq->lock);
1849 				spin_unlock(&recv_cq->lock);
1850 			}
1851 		} else {
1852 			__release(&recv_cq->lock);
1853 			spin_unlock(&send_cq->lock);
1854 		}
1855 	} else if (recv_cq) {
1856 		__release(&send_cq->lock);
1857 		spin_unlock(&recv_cq->lock);
1858 	} else {
1859 		__release(&recv_cq->lock);
1860 		__release(&send_cq->lock);
1861 	}
1862 }
1863 
1864 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1865 {
1866 	return to_mpd(qp->ibqp.pd);
1867 }
1868 
1869 static void get_cqs(enum ib_qp_type qp_type,
1870 		    struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
1871 		    struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1872 {
1873 	switch (qp_type) {
1874 	case IB_QPT_XRC_TGT:
1875 		*send_cq = NULL;
1876 		*recv_cq = NULL;
1877 		break;
1878 	case MLX5_IB_QPT_REG_UMR:
1879 	case IB_QPT_XRC_INI:
1880 		*send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1881 		*recv_cq = NULL;
1882 		break;
1883 
1884 	case IB_QPT_SMI:
1885 	case MLX5_IB_QPT_HW_GSI:
1886 	case IB_QPT_RC:
1887 	case IB_QPT_UC:
1888 	case IB_QPT_UD:
1889 	case IB_QPT_RAW_IPV6:
1890 	case IB_QPT_RAW_ETHERTYPE:
1891 	case IB_QPT_RAW_PACKET:
1892 		*send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1893 		*recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
1894 		break;
1895 
1896 	case IB_QPT_MAX:
1897 	default:
1898 		*send_cq = NULL;
1899 		*recv_cq = NULL;
1900 		break;
1901 	}
1902 }
1903 
1904 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1905 				const struct mlx5_modify_raw_qp_param *raw_qp_param,
1906 				u8 lag_tx_affinity);
1907 
1908 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1909 {
1910 	struct mlx5_ib_cq *send_cq, *recv_cq;
1911 	struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
1912 	unsigned long flags;
1913 	int err;
1914 
1915 	if (qp->ibqp.rwq_ind_tbl) {
1916 		destroy_rss_raw_qp_tir(dev, qp);
1917 		return;
1918 	}
1919 
1920 	base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1921 	       &qp->raw_packet_qp.rq.base :
1922 	       &qp->trans_qp.base;
1923 
1924 	if (qp->state != IB_QPS_RESET) {
1925 		if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
1926 			mlx5_ib_qp_disable_pagefaults(qp);
1927 			err = mlx5_core_qp_modify(dev->mdev,
1928 						  MLX5_CMD_OP_2RST_QP, 0,
1929 						  NULL, &base->mqp);
1930 		} else {
1931 			struct mlx5_modify_raw_qp_param raw_qp_param = {
1932 				.operation = MLX5_CMD_OP_2RST_QP
1933 			};
1934 
1935 			err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
1936 		}
1937 		if (err)
1938 			mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
1939 				     base->mqp.qpn);
1940 	}
1941 
1942 	get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
1943 		&send_cq, &recv_cq);
1944 
1945 	spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1946 	mlx5_ib_lock_cqs(send_cq, recv_cq);
1947 	/* del from lists under both locks above to protect reset flow paths */
1948 	list_del(&qp->qps_list);
1949 	if (send_cq)
1950 		list_del(&qp->cq_send_list);
1951 
1952 	if (recv_cq)
1953 		list_del(&qp->cq_recv_list);
1954 
1955 	if (qp->create_type == MLX5_QP_KERNEL) {
1956 		__mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
1957 				   qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1958 		if (send_cq != recv_cq)
1959 			__mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1960 					   NULL);
1961 	}
1962 	mlx5_ib_unlock_cqs(send_cq, recv_cq);
1963 	spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1964 
1965 	if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1966 		destroy_raw_packet_qp(dev, qp);
1967 	} else {
1968 		err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1969 		if (err)
1970 			mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1971 				     base->mqp.qpn);
1972 	}
1973 
1974 	if (qp->create_type == MLX5_QP_KERNEL)
1975 		destroy_qp_kernel(dev, qp);
1976 	else if (qp->create_type == MLX5_QP_USER)
1977 		destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
1978 }
1979 
1980 static const char *ib_qp_type_str(enum ib_qp_type type)
1981 {
1982 	switch (type) {
1983 	case IB_QPT_SMI:
1984 		return "IB_QPT_SMI";
1985 	case IB_QPT_GSI:
1986 		return "IB_QPT_GSI";
1987 	case IB_QPT_RC:
1988 		return "IB_QPT_RC";
1989 	case IB_QPT_UC:
1990 		return "IB_QPT_UC";
1991 	case IB_QPT_UD:
1992 		return "IB_QPT_UD";
1993 	case IB_QPT_RAW_IPV6:
1994 		return "IB_QPT_RAW_IPV6";
1995 	case IB_QPT_RAW_ETHERTYPE:
1996 		return "IB_QPT_RAW_ETHERTYPE";
1997 	case IB_QPT_XRC_INI:
1998 		return "IB_QPT_XRC_INI";
1999 	case IB_QPT_XRC_TGT:
2000 		return "IB_QPT_XRC_TGT";
2001 	case IB_QPT_RAW_PACKET:
2002 		return "IB_QPT_RAW_PACKET";
2003 	case MLX5_IB_QPT_REG_UMR:
2004 		return "MLX5_IB_QPT_REG_UMR";
2005 	case IB_QPT_MAX:
2006 	default:
2007 		return "Invalid QP type";
2008 	}
2009 }
2010 
2011 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2012 				struct ib_qp_init_attr *init_attr,
2013 				struct ib_udata *udata)
2014 {
2015 	struct mlx5_ib_dev *dev;
2016 	struct mlx5_ib_qp *qp;
2017 	u16 xrcdn = 0;
2018 	int err;
2019 
2020 	if (pd) {
2021 		dev = to_mdev(pd->device);
2022 
2023 		if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2024 			if (!pd->uobject) {
2025 				mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2026 				return ERR_PTR(-EINVAL);
2027 			} else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2028 				mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2029 				return ERR_PTR(-EINVAL);
2030 			}
2031 		}
2032 	} else {
2033 		/* being cautious here */
2034 		if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2035 		    init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2036 			pr_warn("%s: no PD for transport %s\n", __func__,
2037 				ib_qp_type_str(init_attr->qp_type));
2038 			return ERR_PTR(-EINVAL);
2039 		}
2040 		dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2041 	}
2042 
2043 	switch (init_attr->qp_type) {
2044 	case IB_QPT_XRC_TGT:
2045 	case IB_QPT_XRC_INI:
2046 		if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2047 			mlx5_ib_dbg(dev, "XRC not supported\n");
2048 			return ERR_PTR(-ENOSYS);
2049 		}
2050 		init_attr->recv_cq = NULL;
2051 		if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2052 			xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2053 			init_attr->send_cq = NULL;
2054 		}
2055 
2056 		/* fall through */
2057 	case IB_QPT_RAW_PACKET:
2058 	case IB_QPT_RC:
2059 	case IB_QPT_UC:
2060 	case IB_QPT_UD:
2061 	case IB_QPT_SMI:
2062 	case MLX5_IB_QPT_HW_GSI:
2063 	case MLX5_IB_QPT_REG_UMR:
2064 		qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2065 		if (!qp)
2066 			return ERR_PTR(-ENOMEM);
2067 
2068 		err = create_qp_common(dev, pd, init_attr, udata, qp);
2069 		if (err) {
2070 			mlx5_ib_dbg(dev, "create_qp_common failed\n");
2071 			kfree(qp);
2072 			return ERR_PTR(err);
2073 		}
2074 
2075 		if (is_qp0(init_attr->qp_type))
2076 			qp->ibqp.qp_num = 0;
2077 		else if (is_qp1(init_attr->qp_type))
2078 			qp->ibqp.qp_num = 1;
2079 		else
2080 			qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2081 
2082 		mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2083 			    qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2084 			    init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2085 			    init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2086 
2087 		qp->trans_qp.xrcdn = xrcdn;
2088 
2089 		break;
2090 
2091 	case IB_QPT_GSI:
2092 		return mlx5_ib_gsi_create_qp(pd, init_attr);
2093 
2094 	case IB_QPT_RAW_IPV6:
2095 	case IB_QPT_RAW_ETHERTYPE:
2096 	case IB_QPT_MAX:
2097 	default:
2098 		mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2099 			    init_attr->qp_type);
2100 		/* Don't support raw QPs */
2101 		return ERR_PTR(-EINVAL);
2102 	}
2103 
2104 	return &qp->ibqp;
2105 }
2106 
2107 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2108 {
2109 	struct mlx5_ib_dev *dev = to_mdev(qp->device);
2110 	struct mlx5_ib_qp *mqp = to_mqp(qp);
2111 
2112 	if (unlikely(qp->qp_type == IB_QPT_GSI))
2113 		return mlx5_ib_gsi_destroy_qp(qp);
2114 
2115 	destroy_qp_common(dev, mqp);
2116 
2117 	kfree(mqp);
2118 
2119 	return 0;
2120 }
2121 
2122 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2123 				   int attr_mask)
2124 {
2125 	u32 hw_access_flags = 0;
2126 	u8 dest_rd_atomic;
2127 	u32 access_flags;
2128 
2129 	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2130 		dest_rd_atomic = attr->max_dest_rd_atomic;
2131 	else
2132 		dest_rd_atomic = qp->trans_qp.resp_depth;
2133 
2134 	if (attr_mask & IB_QP_ACCESS_FLAGS)
2135 		access_flags = attr->qp_access_flags;
2136 	else
2137 		access_flags = qp->trans_qp.atomic_rd_en;
2138 
2139 	if (!dest_rd_atomic)
2140 		access_flags &= IB_ACCESS_REMOTE_WRITE;
2141 
2142 	if (access_flags & IB_ACCESS_REMOTE_READ)
2143 		hw_access_flags |= MLX5_QP_BIT_RRE;
2144 	if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2145 		hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2146 	if (access_flags & IB_ACCESS_REMOTE_WRITE)
2147 		hw_access_flags |= MLX5_QP_BIT_RWE;
2148 
2149 	return cpu_to_be32(hw_access_flags);
2150 }
2151 
2152 enum {
2153 	MLX5_PATH_FLAG_FL	= 1 << 0,
2154 	MLX5_PATH_FLAG_FREE_AR	= 1 << 1,
2155 	MLX5_PATH_FLAG_COUNTER	= 1 << 2,
2156 };
2157 
2158 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2159 {
2160 	if (rate == IB_RATE_PORT_CURRENT) {
2161 		return 0;
2162 	} else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS) {
2163 		return -EINVAL;
2164 	} else {
2165 		while (rate != IB_RATE_2_5_GBPS &&
2166 		       !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2167 			 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2168 			--rate;
2169 	}
2170 
2171 	return rate + MLX5_STAT_RATE_OFFSET;
2172 }
2173 
2174 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2175 				      struct mlx5_ib_sq *sq, u8 sl)
2176 {
2177 	void *in;
2178 	void *tisc;
2179 	int inlen;
2180 	int err;
2181 
2182 	inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2183 	in = mlx5_vzalloc(inlen);
2184 	if (!in)
2185 		return -ENOMEM;
2186 
2187 	MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2188 
2189 	tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2190 	MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2191 
2192 	err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2193 
2194 	kvfree(in);
2195 
2196 	return err;
2197 }
2198 
2199 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2200 					 struct mlx5_ib_sq *sq, u8 tx_affinity)
2201 {
2202 	void *in;
2203 	void *tisc;
2204 	int inlen;
2205 	int err;
2206 
2207 	inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2208 	in = mlx5_vzalloc(inlen);
2209 	if (!in)
2210 		return -ENOMEM;
2211 
2212 	MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2213 
2214 	tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2215 	MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2216 
2217 	err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2218 
2219 	kvfree(in);
2220 
2221 	return err;
2222 }
2223 
2224 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2225 			 const struct ib_ah_attr *ah,
2226 			 struct mlx5_qp_path *path, u8 port, int attr_mask,
2227 			 u32 path_flags, const struct ib_qp_attr *attr,
2228 			 bool alt)
2229 {
2230 	enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2231 	int err;
2232 	enum ib_gid_type gid_type;
2233 
2234 	if (attr_mask & IB_QP_PKEY_INDEX)
2235 		path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2236 						     attr->pkey_index);
2237 
2238 	if (ah->ah_flags & IB_AH_GRH) {
2239 		if (ah->grh.sgid_index >=
2240 		    dev->mdev->port_caps[port - 1].gid_table_len) {
2241 			pr_err("sgid_index (%u) too large. max is %d\n",
2242 			       ah->grh.sgid_index,
2243 			       dev->mdev->port_caps[port - 1].gid_table_len);
2244 			return -EINVAL;
2245 		}
2246 	}
2247 
2248 	if (ll == IB_LINK_LAYER_ETHERNET) {
2249 		if (!(ah->ah_flags & IB_AH_GRH))
2250 			return -EINVAL;
2251 		err = mlx5_get_roce_gid_type(dev, port, ah->grh.sgid_index,
2252 					     &gid_type);
2253 		if (err)
2254 			return err;
2255 		memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));
2256 		path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2257 							  ah->grh.sgid_index);
2258 		path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;
2259 		if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2260 			path->ecn_dscp = (ah->grh.traffic_class >> 2) & 0x3f;
2261 	} else {
2262 		path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2263 		path->fl_free_ar |=
2264 			(path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2265 		path->rlid = cpu_to_be16(ah->dlid);
2266 		path->grh_mlid = ah->src_path_bits & 0x7f;
2267 		if (ah->ah_flags & IB_AH_GRH)
2268 			path->grh_mlid	|= 1 << 7;
2269 		path->dci_cfi_prio_sl = ah->sl & 0xf;
2270 	}
2271 
2272 	if (ah->ah_flags & IB_AH_GRH) {
2273 		path->mgid_index = ah->grh.sgid_index;
2274 		path->hop_limit  = ah->grh.hop_limit;
2275 		path->tclass_flowlabel =
2276 			cpu_to_be32((ah->grh.traffic_class << 20) |
2277 				    (ah->grh.flow_label));
2278 		memcpy(path->rgid, ah->grh.dgid.raw, 16);
2279 	}
2280 
2281 	err = ib_rate_to_mlx5(dev, ah->static_rate);
2282 	if (err < 0)
2283 		return err;
2284 	path->static_rate = err;
2285 	path->port = port;
2286 
2287 	if (attr_mask & IB_QP_TIMEOUT)
2288 		path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2289 
2290 	if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2291 		return modify_raw_packet_eth_prio(dev->mdev,
2292 						  &qp->raw_packet_qp.sq,
2293 						  ah->sl & 0xf);
2294 
2295 	return 0;
2296 }
2297 
2298 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2299 	[MLX5_QP_STATE_INIT] = {
2300 		[MLX5_QP_STATE_INIT] = {
2301 			[MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE		|
2302 					  MLX5_QP_OPTPAR_RAE		|
2303 					  MLX5_QP_OPTPAR_RWE		|
2304 					  MLX5_QP_OPTPAR_PKEY_INDEX	|
2305 					  MLX5_QP_OPTPAR_PRI_PORT,
2306 			[MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE		|
2307 					  MLX5_QP_OPTPAR_PKEY_INDEX	|
2308 					  MLX5_QP_OPTPAR_PRI_PORT,
2309 			[MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX	|
2310 					  MLX5_QP_OPTPAR_Q_KEY		|
2311 					  MLX5_QP_OPTPAR_PRI_PORT,
2312 		},
2313 		[MLX5_QP_STATE_RTR] = {
2314 			[MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2315 					  MLX5_QP_OPTPAR_RRE            |
2316 					  MLX5_QP_OPTPAR_RAE            |
2317 					  MLX5_QP_OPTPAR_RWE            |
2318 					  MLX5_QP_OPTPAR_PKEY_INDEX,
2319 			[MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2320 					  MLX5_QP_OPTPAR_RWE            |
2321 					  MLX5_QP_OPTPAR_PKEY_INDEX,
2322 			[MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2323 					  MLX5_QP_OPTPAR_Q_KEY,
2324 			[MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX	|
2325 					   MLX5_QP_OPTPAR_Q_KEY,
2326 			[MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2327 					  MLX5_QP_OPTPAR_RRE            |
2328 					  MLX5_QP_OPTPAR_RAE            |
2329 					  MLX5_QP_OPTPAR_RWE            |
2330 					  MLX5_QP_OPTPAR_PKEY_INDEX,
2331 		},
2332 	},
2333 	[MLX5_QP_STATE_RTR] = {
2334 		[MLX5_QP_STATE_RTS] = {
2335 			[MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH	|
2336 					  MLX5_QP_OPTPAR_RRE		|
2337 					  MLX5_QP_OPTPAR_RAE		|
2338 					  MLX5_QP_OPTPAR_RWE		|
2339 					  MLX5_QP_OPTPAR_PM_STATE	|
2340 					  MLX5_QP_OPTPAR_RNR_TIMEOUT,
2341 			[MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH	|
2342 					  MLX5_QP_OPTPAR_RWE		|
2343 					  MLX5_QP_OPTPAR_PM_STATE,
2344 			[MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2345 		},
2346 	},
2347 	[MLX5_QP_STATE_RTS] = {
2348 		[MLX5_QP_STATE_RTS] = {
2349 			[MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE		|
2350 					  MLX5_QP_OPTPAR_RAE		|
2351 					  MLX5_QP_OPTPAR_RWE		|
2352 					  MLX5_QP_OPTPAR_RNR_TIMEOUT	|
2353 					  MLX5_QP_OPTPAR_PM_STATE	|
2354 					  MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2355 			[MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE		|
2356 					  MLX5_QP_OPTPAR_PM_STATE	|
2357 					  MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2358 			[MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY		|
2359 					  MLX5_QP_OPTPAR_SRQN		|
2360 					  MLX5_QP_OPTPAR_CQN_RCV,
2361 		},
2362 	},
2363 	[MLX5_QP_STATE_SQER] = {
2364 		[MLX5_QP_STATE_RTS] = {
2365 			[MLX5_QP_ST_UD]	 = MLX5_QP_OPTPAR_Q_KEY,
2366 			[MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2367 			[MLX5_QP_ST_UC]	 = MLX5_QP_OPTPAR_RWE,
2368 			[MLX5_QP_ST_RC]	 = MLX5_QP_OPTPAR_RNR_TIMEOUT	|
2369 					   MLX5_QP_OPTPAR_RWE		|
2370 					   MLX5_QP_OPTPAR_RAE		|
2371 					   MLX5_QP_OPTPAR_RRE,
2372 		},
2373 	},
2374 };
2375 
2376 static int ib_nr_to_mlx5_nr(int ib_mask)
2377 {
2378 	switch (ib_mask) {
2379 	case IB_QP_STATE:
2380 		return 0;
2381 	case IB_QP_CUR_STATE:
2382 		return 0;
2383 	case IB_QP_EN_SQD_ASYNC_NOTIFY:
2384 		return 0;
2385 	case IB_QP_ACCESS_FLAGS:
2386 		return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2387 			MLX5_QP_OPTPAR_RAE;
2388 	case IB_QP_PKEY_INDEX:
2389 		return MLX5_QP_OPTPAR_PKEY_INDEX;
2390 	case IB_QP_PORT:
2391 		return MLX5_QP_OPTPAR_PRI_PORT;
2392 	case IB_QP_QKEY:
2393 		return MLX5_QP_OPTPAR_Q_KEY;
2394 	case IB_QP_AV:
2395 		return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2396 			MLX5_QP_OPTPAR_PRI_PORT;
2397 	case IB_QP_PATH_MTU:
2398 		return 0;
2399 	case IB_QP_TIMEOUT:
2400 		return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2401 	case IB_QP_RETRY_CNT:
2402 		return MLX5_QP_OPTPAR_RETRY_COUNT;
2403 	case IB_QP_RNR_RETRY:
2404 		return MLX5_QP_OPTPAR_RNR_RETRY;
2405 	case IB_QP_RQ_PSN:
2406 		return 0;
2407 	case IB_QP_MAX_QP_RD_ATOMIC:
2408 		return MLX5_QP_OPTPAR_SRA_MAX;
2409 	case IB_QP_ALT_PATH:
2410 		return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2411 	case IB_QP_MIN_RNR_TIMER:
2412 		return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2413 	case IB_QP_SQ_PSN:
2414 		return 0;
2415 	case IB_QP_MAX_DEST_RD_ATOMIC:
2416 		return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2417 			MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2418 	case IB_QP_PATH_MIG_STATE:
2419 		return MLX5_QP_OPTPAR_PM_STATE;
2420 	case IB_QP_CAP:
2421 		return 0;
2422 	case IB_QP_DEST_QPN:
2423 		return 0;
2424 	}
2425 	return 0;
2426 }
2427 
2428 static int ib_mask_to_mlx5_opt(int ib_mask)
2429 {
2430 	int result = 0;
2431 	int i;
2432 
2433 	for (i = 0; i < 8 * sizeof(int); i++) {
2434 		if ((1 << i) & ib_mask)
2435 			result |= ib_nr_to_mlx5_nr(1 << i);
2436 	}
2437 
2438 	return result;
2439 }
2440 
2441 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2442 				   struct mlx5_ib_rq *rq, int new_state,
2443 				   const struct mlx5_modify_raw_qp_param *raw_qp_param)
2444 {
2445 	void *in;
2446 	void *rqc;
2447 	int inlen;
2448 	int err;
2449 
2450 	inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2451 	in = mlx5_vzalloc(inlen);
2452 	if (!in)
2453 		return -ENOMEM;
2454 
2455 	MLX5_SET(modify_rq_in, in, rqn, rq->base.mqp.qpn);
2456 	MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2457 
2458 	rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2459 	MLX5_SET(rqc, rqc, state, new_state);
2460 
2461 	if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2462 		if (MLX5_CAP_GEN(dev->mdev, modify_rq_counters_set_id)) {
2463 			MLX5_SET64(modify_rq_in, in, modify_bitmask,
2464 				   MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID);
2465 			MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2466 		} else
2467 			pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2468 				     dev->ib_dev.name);
2469 	}
2470 
2471 	err = mlx5_core_modify_rq(dev->mdev, in, inlen);
2472 	if (err)
2473 		goto out;
2474 
2475 	rq->state = new_state;
2476 
2477 out:
2478 	kvfree(in);
2479 	return err;
2480 }
2481 
2482 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2483 				   struct mlx5_ib_sq *sq, int new_state)
2484 {
2485 	void *in;
2486 	void *sqc;
2487 	int inlen;
2488 	int err;
2489 
2490 	inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2491 	in = mlx5_vzalloc(inlen);
2492 	if (!in)
2493 		return -ENOMEM;
2494 
2495 	MLX5_SET(modify_sq_in, in, sqn, sq->base.mqp.qpn);
2496 	MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2497 
2498 	sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2499 	MLX5_SET(sqc, sqc, state, new_state);
2500 
2501 	err = mlx5_core_modify_sq(dev, in, inlen);
2502 	if (err)
2503 		goto out;
2504 
2505 	sq->state = new_state;
2506 
2507 out:
2508 	kvfree(in);
2509 	return err;
2510 }
2511 
2512 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2513 				const struct mlx5_modify_raw_qp_param *raw_qp_param,
2514 				u8 tx_affinity)
2515 {
2516 	struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2517 	struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2518 	struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2519 	int rq_state;
2520 	int sq_state;
2521 	int err;
2522 
2523 	switch (raw_qp_param->operation) {
2524 	case MLX5_CMD_OP_RST2INIT_QP:
2525 		rq_state = MLX5_RQC_STATE_RDY;
2526 		sq_state = MLX5_SQC_STATE_RDY;
2527 		break;
2528 	case MLX5_CMD_OP_2ERR_QP:
2529 		rq_state = MLX5_RQC_STATE_ERR;
2530 		sq_state = MLX5_SQC_STATE_ERR;
2531 		break;
2532 	case MLX5_CMD_OP_2RST_QP:
2533 		rq_state = MLX5_RQC_STATE_RST;
2534 		sq_state = MLX5_SQC_STATE_RST;
2535 		break;
2536 	case MLX5_CMD_OP_INIT2INIT_QP:
2537 	case MLX5_CMD_OP_INIT2RTR_QP:
2538 	case MLX5_CMD_OP_RTR2RTS_QP:
2539 	case MLX5_CMD_OP_RTS2RTS_QP:
2540 		if (raw_qp_param->set_mask)
2541 			return -EINVAL;
2542 		else
2543 			return 0;
2544 	default:
2545 		WARN_ON(1);
2546 		return -EINVAL;
2547 	}
2548 
2549 	if (qp->rq.wqe_cnt) {
2550 		err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
2551 		if (err)
2552 			return err;
2553 	}
2554 
2555 	if (qp->sq.wqe_cnt) {
2556 		if (tx_affinity) {
2557 			err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2558 							    tx_affinity);
2559 			if (err)
2560 				return err;
2561 		}
2562 
2563 		return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state);
2564 	}
2565 
2566 	return 0;
2567 }
2568 
2569 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2570 			       const struct ib_qp_attr *attr, int attr_mask,
2571 			       enum ib_qp_state cur_state, enum ib_qp_state new_state)
2572 {
2573 	static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2574 		[MLX5_QP_STATE_RST] = {
2575 			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
2576 			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
2577 			[MLX5_QP_STATE_INIT]	= MLX5_CMD_OP_RST2INIT_QP,
2578 		},
2579 		[MLX5_QP_STATE_INIT]  = {
2580 			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
2581 			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
2582 			[MLX5_QP_STATE_INIT]	= MLX5_CMD_OP_INIT2INIT_QP,
2583 			[MLX5_QP_STATE_RTR]	= MLX5_CMD_OP_INIT2RTR_QP,
2584 		},
2585 		[MLX5_QP_STATE_RTR]   = {
2586 			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
2587 			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
2588 			[MLX5_QP_STATE_RTS]	= MLX5_CMD_OP_RTR2RTS_QP,
2589 		},
2590 		[MLX5_QP_STATE_RTS]   = {
2591 			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
2592 			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
2593 			[MLX5_QP_STATE_RTS]	= MLX5_CMD_OP_RTS2RTS_QP,
2594 		},
2595 		[MLX5_QP_STATE_SQD] = {
2596 			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
2597 			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
2598 		},
2599 		[MLX5_QP_STATE_SQER] = {
2600 			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
2601 			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
2602 			[MLX5_QP_STATE_RTS]	= MLX5_CMD_OP_SQERR2RTS_QP,
2603 		},
2604 		[MLX5_QP_STATE_ERR] = {
2605 			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
2606 			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
2607 		}
2608 	};
2609 
2610 	struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2611 	struct mlx5_ib_qp *qp = to_mqp(ibqp);
2612 	struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2613 	struct mlx5_ib_cq *send_cq, *recv_cq;
2614 	struct mlx5_qp_context *context;
2615 	struct mlx5_ib_pd *pd;
2616 	struct mlx5_ib_port *mibport = NULL;
2617 	enum mlx5_qp_state mlx5_cur, mlx5_new;
2618 	enum mlx5_qp_optpar optpar;
2619 	int sqd_event;
2620 	int mlx5_st;
2621 	int err;
2622 	u16 op;
2623 
2624 	context = kzalloc(sizeof(*context), GFP_KERNEL);
2625 	if (!context)
2626 		return -ENOMEM;
2627 
2628 	err = to_mlx5_st(ibqp->qp_type);
2629 	if (err < 0) {
2630 		mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
2631 		goto out;
2632 	}
2633 
2634 	context->flags = cpu_to_be32(err << 16);
2635 
2636 	if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2637 		context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2638 	} else {
2639 		switch (attr->path_mig_state) {
2640 		case IB_MIG_MIGRATED:
2641 			context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2642 			break;
2643 		case IB_MIG_REARM:
2644 			context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2645 			break;
2646 		case IB_MIG_ARMED:
2647 			context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2648 			break;
2649 		}
2650 	}
2651 
2652 	if (is_sqp(ibqp->qp_type)) {
2653 		context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2654 	} else if (ibqp->qp_type == IB_QPT_UD ||
2655 		   ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2656 		context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2657 	} else if (attr_mask & IB_QP_PATH_MTU) {
2658 		if (attr->path_mtu < IB_MTU_256 ||
2659 		    attr->path_mtu > IB_MTU_4096) {
2660 			mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2661 			err = -EINVAL;
2662 			goto out;
2663 		}
2664 		context->mtu_msgmax = (attr->path_mtu << 5) |
2665 				      (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
2666 	}
2667 
2668 	if (attr_mask & IB_QP_DEST_QPN)
2669 		context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2670 
2671 	if (attr_mask & IB_QP_PKEY_INDEX)
2672 		context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
2673 
2674 	/* todo implement counter_index functionality */
2675 
2676 	if (is_sqp(ibqp->qp_type))
2677 		context->pri_path.port = qp->port;
2678 
2679 	if (attr_mask & IB_QP_PORT)
2680 		context->pri_path.port = attr->port_num;
2681 
2682 	if (attr_mask & IB_QP_AV) {
2683 		err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
2684 				    attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
2685 				    attr_mask, 0, attr, false);
2686 		if (err)
2687 			goto out;
2688 	}
2689 
2690 	if (attr_mask & IB_QP_TIMEOUT)
2691 		context->pri_path.ackto_lt |= attr->timeout << 3;
2692 
2693 	if (attr_mask & IB_QP_ALT_PATH) {
2694 		err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2695 				    &context->alt_path,
2696 				    attr->alt_port_num,
2697 				    attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2698 				    0, attr, true);
2699 		if (err)
2700 			goto out;
2701 	}
2702 
2703 	pd = get_pd(qp);
2704 	get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2705 		&send_cq, &recv_cq);
2706 
2707 	context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2708 	context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2709 	context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2710 	context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2711 
2712 	if (attr_mask & IB_QP_RNR_RETRY)
2713 		context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2714 
2715 	if (attr_mask & IB_QP_RETRY_CNT)
2716 		context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2717 
2718 	if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2719 		if (attr->max_rd_atomic)
2720 			context->params1 |=
2721 				cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2722 	}
2723 
2724 	if (attr_mask & IB_QP_SQ_PSN)
2725 		context->next_send_psn = cpu_to_be32(attr->sq_psn);
2726 
2727 	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2728 		if (attr->max_dest_rd_atomic)
2729 			context->params2 |=
2730 				cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2731 	}
2732 
2733 	if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2734 		context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2735 
2736 	if (attr_mask & IB_QP_MIN_RNR_TIMER)
2737 		context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2738 
2739 	if (attr_mask & IB_QP_RQ_PSN)
2740 		context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2741 
2742 	if (attr_mask & IB_QP_QKEY)
2743 		context->qkey = cpu_to_be32(attr->qkey);
2744 
2745 	if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2746 		context->db_rec_addr = cpu_to_be64(qp->db.dma);
2747 
2748 	if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD	&&
2749 	    attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2750 		sqd_event = 1;
2751 	else
2752 		sqd_event = 0;
2753 
2754 	if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2755 		u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2756 			       qp->port) - 1;
2757 		mibport = &dev->port[port_num];
2758 		context->qp_counter_set_usr_page |=
2759 			cpu_to_be32((u32)(mibport->q_cnt_id) << 24);
2760 	}
2761 
2762 	if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2763 		context->sq_crq_size |= cpu_to_be16(1 << 4);
2764 
2765 	if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2766 		context->deth_sqpn = cpu_to_be32(1);
2767 
2768 	mlx5_cur = to_mlx5_state(cur_state);
2769 	mlx5_new = to_mlx5_state(new_state);
2770 	mlx5_st = to_mlx5_st(ibqp->qp_type);
2771 	if (mlx5_st < 0)
2772 		goto out;
2773 
2774 	/* If moving to a reset or error state, we must disable page faults on
2775 	 * this QP and flush all current page faults. Otherwise a stale page
2776 	 * fault may attempt to work on this QP after it is reset and moved
2777 	 * again to RTS, and may cause the driver and the device to get out of
2778 	 * sync. */
2779 	if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2780 	    (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) &&
2781 	    (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2782 		mlx5_ib_qp_disable_pagefaults(qp);
2783 
2784 	if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2785 	    !optab[mlx5_cur][mlx5_new])
2786 		goto out;
2787 
2788 	op = optab[mlx5_cur][mlx5_new];
2789 	optpar = ib_mask_to_mlx5_opt(attr_mask);
2790 	optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2791 
2792 	if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
2793 		struct mlx5_modify_raw_qp_param raw_qp_param = {};
2794 
2795 		raw_qp_param.operation = op;
2796 		if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2797 			raw_qp_param.rq_q_ctr_id = mibport->q_cnt_id;
2798 			raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
2799 		}
2800 		err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2801 	} else {
2802 		err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
2803 					  &base->mqp);
2804 	}
2805 
2806 	if (err)
2807 		goto out;
2808 
2809 	if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT &&
2810 	    (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2811 		mlx5_ib_qp_enable_pagefaults(qp);
2812 
2813 	qp->state = new_state;
2814 
2815 	if (attr_mask & IB_QP_ACCESS_FLAGS)
2816 		qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
2817 	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2818 		qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
2819 	if (attr_mask & IB_QP_PORT)
2820 		qp->port = attr->port_num;
2821 	if (attr_mask & IB_QP_ALT_PATH)
2822 		qp->trans_qp.alt_port = attr->alt_port_num;
2823 
2824 	/*
2825 	 * If we moved a kernel QP to RESET, clean up all old CQ
2826 	 * entries and reinitialize the QP.
2827 	 */
2828 	if (new_state == IB_QPS_RESET && !ibqp->uobject) {
2829 		mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2830 				 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2831 		if (send_cq != recv_cq)
2832 			mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
2833 
2834 		qp->rq.head = 0;
2835 		qp->rq.tail = 0;
2836 		qp->sq.head = 0;
2837 		qp->sq.tail = 0;
2838 		qp->sq.cur_post = 0;
2839 		qp->sq.last_poll = 0;
2840 		qp->db.db[MLX5_RCV_DBR] = 0;
2841 		qp->db.db[MLX5_SND_DBR] = 0;
2842 	}
2843 
2844 out:
2845 	kfree(context);
2846 	return err;
2847 }
2848 
2849 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2850 		      int attr_mask, struct ib_udata *udata)
2851 {
2852 	struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2853 	struct mlx5_ib_qp *qp = to_mqp(ibqp);
2854 	enum ib_qp_type qp_type;
2855 	enum ib_qp_state cur_state, new_state;
2856 	int err = -EINVAL;
2857 	int port;
2858 	enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
2859 
2860 	if (ibqp->rwq_ind_tbl)
2861 		return -ENOSYS;
2862 
2863 	if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2864 		return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2865 
2866 	qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2867 		IB_QPT_GSI : ibqp->qp_type;
2868 
2869 	mutex_lock(&qp->mutex);
2870 
2871 	cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2872 	new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2873 
2874 	if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2875 		port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2876 		ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2877 	}
2878 
2879 	if (qp_type != MLX5_IB_QPT_REG_UMR &&
2880 	    !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
2881 		mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2882 			    cur_state, new_state, ibqp->qp_type, attr_mask);
2883 		goto out;
2884 	}
2885 
2886 	if ((attr_mask & IB_QP_PORT) &&
2887 	    (attr->port_num == 0 ||
2888 	     attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2889 		mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2890 			    attr->port_num, dev->num_ports);
2891 		goto out;
2892 	}
2893 
2894 	if (attr_mask & IB_QP_PKEY_INDEX) {
2895 		port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2896 		if (attr->pkey_index >=
2897 		    dev->mdev->port_caps[port - 1].pkey_table_len) {
2898 			mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2899 				    attr->pkey_index);
2900 			goto out;
2901 		}
2902 	}
2903 
2904 	if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2905 	    attr->max_rd_atomic >
2906 	    (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
2907 		mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
2908 			    attr->max_rd_atomic);
2909 		goto out;
2910 	}
2911 
2912 	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2913 	    attr->max_dest_rd_atomic >
2914 	    (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
2915 		mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
2916 			    attr->max_dest_rd_atomic);
2917 		goto out;
2918 	}
2919 
2920 	if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2921 		err = 0;
2922 		goto out;
2923 	}
2924 
2925 	err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2926 
2927 out:
2928 	mutex_unlock(&qp->mutex);
2929 	return err;
2930 }
2931 
2932 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2933 {
2934 	struct mlx5_ib_cq *cq;
2935 	unsigned cur;
2936 
2937 	cur = wq->head - wq->tail;
2938 	if (likely(cur + nreq < wq->max_post))
2939 		return 0;
2940 
2941 	cq = to_mcq(ib_cq);
2942 	spin_lock(&cq->lock);
2943 	cur = wq->head - wq->tail;
2944 	spin_unlock(&cq->lock);
2945 
2946 	return cur + nreq >= wq->max_post;
2947 }
2948 
2949 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
2950 					  u64 remote_addr, u32 rkey)
2951 {
2952 	rseg->raddr    = cpu_to_be64(remote_addr);
2953 	rseg->rkey     = cpu_to_be32(rkey);
2954 	rseg->reserved = 0;
2955 }
2956 
2957 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
2958 			 struct ib_send_wr *wr, void *qend,
2959 			 struct mlx5_ib_qp *qp, int *size)
2960 {
2961 	void *seg = eseg;
2962 
2963 	memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
2964 
2965 	if (wr->send_flags & IB_SEND_IP_CSUM)
2966 		eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
2967 				 MLX5_ETH_WQE_L4_CSUM;
2968 
2969 	seg += sizeof(struct mlx5_wqe_eth_seg);
2970 	*size += sizeof(struct mlx5_wqe_eth_seg) / 16;
2971 
2972 	if (wr->opcode == IB_WR_LSO) {
2973 		struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2974 		int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start);
2975 		u64 left, leftlen, copysz;
2976 		void *pdata = ud_wr->header;
2977 
2978 		left = ud_wr->hlen;
2979 		eseg->mss = cpu_to_be16(ud_wr->mss);
2980 		eseg->inline_hdr_sz = cpu_to_be16(left);
2981 
2982 		/*
2983 		 * check if there is space till the end of queue, if yes,
2984 		 * copy all in one shot, otherwise copy till the end of queue,
2985 		 * rollback and than the copy the left
2986 		 */
2987 		leftlen = qend - (void *)eseg->inline_hdr_start;
2988 		copysz = min_t(u64, leftlen, left);
2989 
2990 		memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
2991 
2992 		if (likely(copysz > size_of_inl_hdr_start)) {
2993 			seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
2994 			*size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
2995 		}
2996 
2997 		if (unlikely(copysz < left)) { /* the last wqe in the queue */
2998 			seg = mlx5_get_send_wqe(qp, 0);
2999 			left -= copysz;
3000 			pdata += copysz;
3001 			memcpy(seg, pdata, left);
3002 			seg += ALIGN(left, 16);
3003 			*size += ALIGN(left, 16) / 16;
3004 		}
3005 	}
3006 
3007 	return seg;
3008 }
3009 
3010 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3011 			     struct ib_send_wr *wr)
3012 {
3013 	memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3014 	dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3015 	dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
3016 }
3017 
3018 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3019 {
3020 	dseg->byte_count = cpu_to_be32(sg->length);
3021 	dseg->lkey       = cpu_to_be32(sg->lkey);
3022 	dseg->addr       = cpu_to_be64(sg->addr);
3023 }
3024 
3025 static __be16 get_klm_octo(int npages)
3026 {
3027 	return cpu_to_be16(ALIGN(npages, 8) / 2);
3028 }
3029 
3030 static __be64 frwr_mkey_mask(void)
3031 {
3032 	u64 result;
3033 
3034 	result = MLX5_MKEY_MASK_LEN		|
3035 		MLX5_MKEY_MASK_PAGE_SIZE	|
3036 		MLX5_MKEY_MASK_START_ADDR	|
3037 		MLX5_MKEY_MASK_EN_RINVAL	|
3038 		MLX5_MKEY_MASK_KEY		|
3039 		MLX5_MKEY_MASK_LR		|
3040 		MLX5_MKEY_MASK_LW		|
3041 		MLX5_MKEY_MASK_RR		|
3042 		MLX5_MKEY_MASK_RW		|
3043 		MLX5_MKEY_MASK_A		|
3044 		MLX5_MKEY_MASK_SMALL_FENCE	|
3045 		MLX5_MKEY_MASK_FREE;
3046 
3047 	return cpu_to_be64(result);
3048 }
3049 
3050 static __be64 sig_mkey_mask(void)
3051 {
3052 	u64 result;
3053 
3054 	result = MLX5_MKEY_MASK_LEN		|
3055 		MLX5_MKEY_MASK_PAGE_SIZE	|
3056 		MLX5_MKEY_MASK_START_ADDR	|
3057 		MLX5_MKEY_MASK_EN_SIGERR	|
3058 		MLX5_MKEY_MASK_EN_RINVAL	|
3059 		MLX5_MKEY_MASK_KEY		|
3060 		MLX5_MKEY_MASK_LR		|
3061 		MLX5_MKEY_MASK_LW		|
3062 		MLX5_MKEY_MASK_RR		|
3063 		MLX5_MKEY_MASK_RW		|
3064 		MLX5_MKEY_MASK_SMALL_FENCE	|
3065 		MLX5_MKEY_MASK_FREE		|
3066 		MLX5_MKEY_MASK_BSF_EN;
3067 
3068 	return cpu_to_be64(result);
3069 }
3070 
3071 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3072 				struct mlx5_ib_mr *mr)
3073 {
3074 	int ndescs = mr->ndescs;
3075 
3076 	memset(umr, 0, sizeof(*umr));
3077 
3078 	if (mr->access_mode == MLX5_ACCESS_MODE_KLM)
3079 		/* KLMs take twice the size of MTTs */
3080 		ndescs *= 2;
3081 
3082 	umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3083 	umr->klm_octowords = get_klm_octo(ndescs);
3084 	umr->mkey_mask = frwr_mkey_mask();
3085 }
3086 
3087 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
3088 {
3089 	memset(umr, 0, sizeof(*umr));
3090 	umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
3091 	umr->flags = 1 << 7;
3092 }
3093 
3094 static __be64 get_umr_reg_mr_mask(void)
3095 {
3096 	u64 result;
3097 
3098 	result = MLX5_MKEY_MASK_LEN		|
3099 		 MLX5_MKEY_MASK_PAGE_SIZE	|
3100 		 MLX5_MKEY_MASK_START_ADDR	|
3101 		 MLX5_MKEY_MASK_PD		|
3102 		 MLX5_MKEY_MASK_LR		|
3103 		 MLX5_MKEY_MASK_LW		|
3104 		 MLX5_MKEY_MASK_KEY		|
3105 		 MLX5_MKEY_MASK_RR		|
3106 		 MLX5_MKEY_MASK_RW		|
3107 		 MLX5_MKEY_MASK_A		|
3108 		 MLX5_MKEY_MASK_FREE;
3109 
3110 	return cpu_to_be64(result);
3111 }
3112 
3113 static __be64 get_umr_unreg_mr_mask(void)
3114 {
3115 	u64 result;
3116 
3117 	result = MLX5_MKEY_MASK_FREE;
3118 
3119 	return cpu_to_be64(result);
3120 }
3121 
3122 static __be64 get_umr_update_mtt_mask(void)
3123 {
3124 	u64 result;
3125 
3126 	result = MLX5_MKEY_MASK_FREE;
3127 
3128 	return cpu_to_be64(result);
3129 }
3130 
3131 static __be64 get_umr_update_translation_mask(void)
3132 {
3133 	u64 result;
3134 
3135 	result = MLX5_MKEY_MASK_LEN |
3136 		 MLX5_MKEY_MASK_PAGE_SIZE |
3137 		 MLX5_MKEY_MASK_START_ADDR |
3138 		 MLX5_MKEY_MASK_KEY |
3139 		 MLX5_MKEY_MASK_FREE;
3140 
3141 	return cpu_to_be64(result);
3142 }
3143 
3144 static __be64 get_umr_update_access_mask(void)
3145 {
3146 	u64 result;
3147 
3148 	result = MLX5_MKEY_MASK_LW |
3149 		 MLX5_MKEY_MASK_RR |
3150 		 MLX5_MKEY_MASK_RW |
3151 		 MLX5_MKEY_MASK_A |
3152 		 MLX5_MKEY_MASK_KEY |
3153 		 MLX5_MKEY_MASK_FREE;
3154 
3155 	return cpu_to_be64(result);
3156 }
3157 
3158 static __be64 get_umr_update_pd_mask(void)
3159 {
3160 	u64 result;
3161 
3162 	result = MLX5_MKEY_MASK_PD |
3163 		 MLX5_MKEY_MASK_KEY |
3164 		 MLX5_MKEY_MASK_FREE;
3165 
3166 	return cpu_to_be64(result);
3167 }
3168 
3169 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3170 				struct ib_send_wr *wr)
3171 {
3172 	struct mlx5_umr_wr *umrwr = umr_wr(wr);
3173 
3174 	memset(umr, 0, sizeof(*umr));
3175 
3176 	if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3177 		umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3178 	else
3179 		umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3180 
3181 	if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
3182 		umr->klm_octowords = get_klm_octo(umrwr->npages);
3183 		if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) {
3184 			umr->mkey_mask = get_umr_update_mtt_mask();
3185 			umr->bsf_octowords = get_klm_octo(umrwr->target.offset);
3186 			umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3187 		}
3188 		if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3189 			umr->mkey_mask |= get_umr_update_translation_mask();
3190 		if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_ACCESS)
3191 			umr->mkey_mask |= get_umr_update_access_mask();
3192 		if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD)
3193 			umr->mkey_mask |= get_umr_update_pd_mask();
3194 		if (!umr->mkey_mask)
3195 			umr->mkey_mask = get_umr_reg_mr_mask();
3196 	} else {
3197 		umr->mkey_mask = get_umr_unreg_mr_mask();
3198 	}
3199 
3200 	if (!wr->num_sge)
3201 		umr->flags |= MLX5_UMR_INLINE;
3202 }
3203 
3204 static u8 get_umr_flags(int acc)
3205 {
3206 	return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
3207 	       (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
3208 	       (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
3209 	       (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
3210 		MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3211 }
3212 
3213 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3214 			     struct mlx5_ib_mr *mr,
3215 			     u32 key, int access)
3216 {
3217 	int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3218 
3219 	memset(seg, 0, sizeof(*seg));
3220 
3221 	if (mr->access_mode == MLX5_ACCESS_MODE_MTT)
3222 		seg->log2_page_size = ilog2(mr->ibmr.page_size);
3223 	else if (mr->access_mode == MLX5_ACCESS_MODE_KLM)
3224 		/* KLMs take twice the size of MTTs */
3225 		ndescs *= 2;
3226 
3227 	seg->flags = get_umr_flags(access) | mr->access_mode;
3228 	seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3229 	seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3230 	seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3231 	seg->len = cpu_to_be64(mr->ibmr.length);
3232 	seg->xlt_oct_size = cpu_to_be32(ndescs);
3233 }
3234 
3235 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3236 {
3237 	memset(seg, 0, sizeof(*seg));
3238 	seg->status = MLX5_MKEY_STATUS_FREE;
3239 }
3240 
3241 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3242 {
3243 	struct mlx5_umr_wr *umrwr = umr_wr(wr);
3244 
3245 	memset(seg, 0, sizeof(*seg));
3246 	if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
3247 		seg->status = MLX5_MKEY_STATUS_FREE;
3248 		return;
3249 	}
3250 
3251 	seg->flags = convert_access(umrwr->access_flags);
3252 	if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) {
3253 		if (umrwr->pd)
3254 			seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3255 		seg->start_addr = cpu_to_be64(umrwr->target.virt_addr);
3256 	}
3257 	seg->len = cpu_to_be64(umrwr->length);
3258 	seg->log2_page_size = umrwr->page_shift;
3259 	seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3260 				       mlx5_mkey_variant(umrwr->mkey));
3261 }
3262 
3263 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3264 			     struct mlx5_ib_mr *mr,
3265 			     struct mlx5_ib_pd *pd)
3266 {
3267 	int bcount = mr->desc_size * mr->ndescs;
3268 
3269 	dseg->addr = cpu_to_be64(mr->desc_map);
3270 	dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3271 	dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3272 }
3273 
3274 static __be32 send_ieth(struct ib_send_wr *wr)
3275 {
3276 	switch (wr->opcode) {
3277 	case IB_WR_SEND_WITH_IMM:
3278 	case IB_WR_RDMA_WRITE_WITH_IMM:
3279 		return wr->ex.imm_data;
3280 
3281 	case IB_WR_SEND_WITH_INV:
3282 		return cpu_to_be32(wr->ex.invalidate_rkey);
3283 
3284 	default:
3285 		return 0;
3286 	}
3287 }
3288 
3289 static u8 calc_sig(void *wqe, int size)
3290 {
3291 	u8 *p = wqe;
3292 	u8 res = 0;
3293 	int i;
3294 
3295 	for (i = 0; i < size; i++)
3296 		res ^= p[i];
3297 
3298 	return ~res;
3299 }
3300 
3301 static u8 wq_sig(void *wqe)
3302 {
3303 	return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3304 }
3305 
3306 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3307 			    void *wqe, int *sz)
3308 {
3309 	struct mlx5_wqe_inline_seg *seg;
3310 	void *qend = qp->sq.qend;
3311 	void *addr;
3312 	int inl = 0;
3313 	int copy;
3314 	int len;
3315 	int i;
3316 
3317 	seg = wqe;
3318 	wqe += sizeof(*seg);
3319 	for (i = 0; i < wr->num_sge; i++) {
3320 		addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3321 		len  = wr->sg_list[i].length;
3322 		inl += len;
3323 
3324 		if (unlikely(inl > qp->max_inline_data))
3325 			return -ENOMEM;
3326 
3327 		if (unlikely(wqe + len > qend)) {
3328 			copy = qend - wqe;
3329 			memcpy(wqe, addr, copy);
3330 			addr += copy;
3331 			len -= copy;
3332 			wqe = mlx5_get_send_wqe(qp, 0);
3333 		}
3334 		memcpy(wqe, addr, len);
3335 		wqe += len;
3336 	}
3337 
3338 	seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3339 
3340 	*sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3341 
3342 	return 0;
3343 }
3344 
3345 static u16 prot_field_size(enum ib_signature_type type)
3346 {
3347 	switch (type) {
3348 	case IB_SIG_TYPE_T10_DIF:
3349 		return MLX5_DIF_SIZE;
3350 	default:
3351 		return 0;
3352 	}
3353 }
3354 
3355 static u8 bs_selector(int block_size)
3356 {
3357 	switch (block_size) {
3358 	case 512:	    return 0x1;
3359 	case 520:	    return 0x2;
3360 	case 4096:	    return 0x3;
3361 	case 4160:	    return 0x4;
3362 	case 1073741824:    return 0x5;
3363 	default:	    return 0;
3364 	}
3365 }
3366 
3367 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3368 			      struct mlx5_bsf_inl *inl)
3369 {
3370 	/* Valid inline section and allow BSF refresh */
3371 	inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3372 				       MLX5_BSF_REFRESH_DIF);
3373 	inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3374 	inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
3375 	/* repeating block */
3376 	inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3377 	inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3378 			MLX5_DIF_CRC : MLX5_DIF_IPCS;
3379 
3380 	if (domain->sig.dif.ref_remap)
3381 		inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
3382 
3383 	if (domain->sig.dif.app_escape) {
3384 		if (domain->sig.dif.ref_escape)
3385 			inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3386 		else
3387 			inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
3388 	}
3389 
3390 	inl->dif_app_bitmask_check =
3391 		cpu_to_be16(domain->sig.dif.apptag_check_mask);
3392 }
3393 
3394 static int mlx5_set_bsf(struct ib_mr *sig_mr,
3395 			struct ib_sig_attrs *sig_attrs,
3396 			struct mlx5_bsf *bsf, u32 data_size)
3397 {
3398 	struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3399 	struct mlx5_bsf_basic *basic = &bsf->basic;
3400 	struct ib_sig_domain *mem = &sig_attrs->mem;
3401 	struct ib_sig_domain *wire = &sig_attrs->wire;
3402 
3403 	memset(bsf, 0, sizeof(*bsf));
3404 
3405 	/* Basic + Extended + Inline */
3406 	basic->bsf_size_sbs = 1 << 7;
3407 	/* Input domain check byte mask */
3408 	basic->check_byte_mask = sig_attrs->check_mask;
3409 	basic->raw_data_size = cpu_to_be32(data_size);
3410 
3411 	/* Memory domain */
3412 	switch (sig_attrs->mem.sig_type) {
3413 	case IB_SIG_TYPE_NONE:
3414 		break;
3415 	case IB_SIG_TYPE_T10_DIF:
3416 		basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3417 		basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3418 		mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3419 		break;
3420 	default:
3421 		return -EINVAL;
3422 	}
3423 
3424 	/* Wire domain */
3425 	switch (sig_attrs->wire.sig_type) {
3426 	case IB_SIG_TYPE_NONE:
3427 		break;
3428 	case IB_SIG_TYPE_T10_DIF:
3429 		if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
3430 		    mem->sig_type == wire->sig_type) {
3431 			/* Same block structure */
3432 			basic->bsf_size_sbs |= 1 << 4;
3433 			if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
3434 				basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
3435 			if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
3436 				basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
3437 			if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
3438 				basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
3439 		} else
3440 			basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3441 
3442 		basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
3443 		mlx5_fill_inl_bsf(wire, &bsf->w_inl);
3444 		break;
3445 	default:
3446 		return -EINVAL;
3447 	}
3448 
3449 	return 0;
3450 }
3451 
3452 static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3453 				struct mlx5_ib_qp *qp, void **seg, int *size)
3454 {
3455 	struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3456 	struct ib_mr *sig_mr = wr->sig_mr;
3457 	struct mlx5_bsf *bsf;
3458 	u32 data_len = wr->wr.sg_list->length;
3459 	u32 data_key = wr->wr.sg_list->lkey;
3460 	u64 data_va = wr->wr.sg_list->addr;
3461 	int ret;
3462 	int wqe_size;
3463 
3464 	if (!wr->prot ||
3465 	    (data_key == wr->prot->lkey &&
3466 	     data_va == wr->prot->addr &&
3467 	     data_len == wr->prot->length)) {
3468 		/**
3469 		 * Source domain doesn't contain signature information
3470 		 * or data and protection are interleaved in memory.
3471 		 * So need construct:
3472 		 *                  ------------------
3473 		 *                 |     data_klm     |
3474 		 *                  ------------------
3475 		 *                 |       BSF        |
3476 		 *                  ------------------
3477 		 **/
3478 		struct mlx5_klm *data_klm = *seg;
3479 
3480 		data_klm->bcount = cpu_to_be32(data_len);
3481 		data_klm->key = cpu_to_be32(data_key);
3482 		data_klm->va = cpu_to_be64(data_va);
3483 		wqe_size = ALIGN(sizeof(*data_klm), 64);
3484 	} else {
3485 		/**
3486 		 * Source domain contains signature information
3487 		 * So need construct a strided block format:
3488 		 *               ---------------------------
3489 		 *              |     stride_block_ctrl     |
3490 		 *               ---------------------------
3491 		 *              |          data_klm         |
3492 		 *               ---------------------------
3493 		 *              |          prot_klm         |
3494 		 *               ---------------------------
3495 		 *              |             BSF           |
3496 		 *               ---------------------------
3497 		 **/
3498 		struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3499 		struct mlx5_stride_block_entry *data_sentry;
3500 		struct mlx5_stride_block_entry *prot_sentry;
3501 		u32 prot_key = wr->prot->lkey;
3502 		u64 prot_va = wr->prot->addr;
3503 		u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3504 		int prot_size;
3505 
3506 		sblock_ctrl = *seg;
3507 		data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3508 		prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3509 
3510 		prot_size = prot_field_size(sig_attrs->mem.sig_type);
3511 		if (!prot_size) {
3512 			pr_err("Bad block size given: %u\n", block_size);
3513 			return -EINVAL;
3514 		}
3515 		sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3516 							    prot_size);
3517 		sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3518 		sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3519 		sblock_ctrl->num_entries = cpu_to_be16(2);
3520 
3521 		data_sentry->bcount = cpu_to_be16(block_size);
3522 		data_sentry->key = cpu_to_be32(data_key);
3523 		data_sentry->va = cpu_to_be64(data_va);
3524 		data_sentry->stride = cpu_to_be16(block_size);
3525 
3526 		prot_sentry->bcount = cpu_to_be16(prot_size);
3527 		prot_sentry->key = cpu_to_be32(prot_key);
3528 		prot_sentry->va = cpu_to_be64(prot_va);
3529 		prot_sentry->stride = cpu_to_be16(prot_size);
3530 
3531 		wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3532 				 sizeof(*prot_sentry), 64);
3533 	}
3534 
3535 	*seg += wqe_size;
3536 	*size += wqe_size / 16;
3537 	if (unlikely((*seg == qp->sq.qend)))
3538 		*seg = mlx5_get_send_wqe(qp, 0);
3539 
3540 	bsf = *seg;
3541 	ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3542 	if (ret)
3543 		return -EINVAL;
3544 
3545 	*seg += sizeof(*bsf);
3546 	*size += sizeof(*bsf) / 16;
3547 	if (unlikely((*seg == qp->sq.qend)))
3548 		*seg = mlx5_get_send_wqe(qp, 0);
3549 
3550 	return 0;
3551 }
3552 
3553 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
3554 				 struct ib_sig_handover_wr *wr, u32 nelements,
3555 				 u32 length, u32 pdn)
3556 {
3557 	struct ib_mr *sig_mr = wr->sig_mr;
3558 	u32 sig_key = sig_mr->rkey;
3559 	u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
3560 
3561 	memset(seg, 0, sizeof(*seg));
3562 
3563 	seg->flags = get_umr_flags(wr->access_flags) |
3564 				   MLX5_ACCESS_MODE_KLM;
3565 	seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
3566 	seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
3567 				    MLX5_MKEY_BSF_EN | pdn);
3568 	seg->len = cpu_to_be64(length);
3569 	seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements)));
3570 	seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3571 }
3572 
3573 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3574 				u32 nelements)
3575 {
3576 	memset(umr, 0, sizeof(*umr));
3577 
3578 	umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
3579 	umr->klm_octowords = get_klm_octo(nelements);
3580 	umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3581 	umr->mkey_mask = sig_mkey_mask();
3582 }
3583 
3584 
3585 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
3586 			  void **seg, int *size)
3587 {
3588 	struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3589 	struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
3590 	u32 pdn = get_pd(qp)->pdn;
3591 	u32 klm_oct_size;
3592 	int region_len, ret;
3593 
3594 	if (unlikely(wr->wr.num_sge != 1) ||
3595 	    unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
3596 	    unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3597 	    unlikely(!sig_mr->sig->sig_status_checked))
3598 		return -EINVAL;
3599 
3600 	/* length of the protected region, data + protection */
3601 	region_len = wr->wr.sg_list->length;
3602 	if (wr->prot &&
3603 	    (wr->prot->lkey != wr->wr.sg_list->lkey  ||
3604 	     wr->prot->addr != wr->wr.sg_list->addr  ||
3605 	     wr->prot->length != wr->wr.sg_list->length))
3606 		region_len += wr->prot->length;
3607 
3608 	/**
3609 	 * KLM octoword size - if protection was provided
3610 	 * then we use strided block format (3 octowords),
3611 	 * else we use single KLM (1 octoword)
3612 	 **/
3613 	klm_oct_size = wr->prot ? 3 : 1;
3614 
3615 	set_sig_umr_segment(*seg, klm_oct_size);
3616 	*seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3617 	*size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3618 	if (unlikely((*seg == qp->sq.qend)))
3619 		*seg = mlx5_get_send_wqe(qp, 0);
3620 
3621 	set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn);
3622 	*seg += sizeof(struct mlx5_mkey_seg);
3623 	*size += sizeof(struct mlx5_mkey_seg) / 16;
3624 	if (unlikely((*seg == qp->sq.qend)))
3625 		*seg = mlx5_get_send_wqe(qp, 0);
3626 
3627 	ret = set_sig_data_segment(wr, qp, seg, size);
3628 	if (ret)
3629 		return ret;
3630 
3631 	sig_mr->sig->sig_status_checked = false;
3632 	return 0;
3633 }
3634 
3635 static int set_psv_wr(struct ib_sig_domain *domain,
3636 		      u32 psv_idx, void **seg, int *size)
3637 {
3638 	struct mlx5_seg_set_psv *psv_seg = *seg;
3639 
3640 	memset(psv_seg, 0, sizeof(*psv_seg));
3641 	psv_seg->psv_num = cpu_to_be32(psv_idx);
3642 	switch (domain->sig_type) {
3643 	case IB_SIG_TYPE_NONE:
3644 		break;
3645 	case IB_SIG_TYPE_T10_DIF:
3646 		psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3647 						     domain->sig.dif.app_tag);
3648 		psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
3649 		break;
3650 	default:
3651 		pr_err("Bad signature type given.\n");
3652 		return 1;
3653 	}
3654 
3655 	*seg += sizeof(*psv_seg);
3656 	*size += sizeof(*psv_seg) / 16;
3657 
3658 	return 0;
3659 }
3660 
3661 static int set_reg_wr(struct mlx5_ib_qp *qp,
3662 		      struct ib_reg_wr *wr,
3663 		      void **seg, int *size)
3664 {
3665 	struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3666 	struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3667 
3668 	if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3669 		mlx5_ib_warn(to_mdev(qp->ibqp.device),
3670 			     "Invalid IB_SEND_INLINE send flag\n");
3671 		return -EINVAL;
3672 	}
3673 
3674 	set_reg_umr_seg(*seg, mr);
3675 	*seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3676 	*size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3677 	if (unlikely((*seg == qp->sq.qend)))
3678 		*seg = mlx5_get_send_wqe(qp, 0);
3679 
3680 	set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3681 	*seg += sizeof(struct mlx5_mkey_seg);
3682 	*size += sizeof(struct mlx5_mkey_seg) / 16;
3683 	if (unlikely((*seg == qp->sq.qend)))
3684 		*seg = mlx5_get_send_wqe(qp, 0);
3685 
3686 	set_reg_data_seg(*seg, mr, pd);
3687 	*seg += sizeof(struct mlx5_wqe_data_seg);
3688 	*size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3689 
3690 	return 0;
3691 }
3692 
3693 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
3694 {
3695 	set_linv_umr_seg(*seg);
3696 	*seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3697 	*size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3698 	if (unlikely((*seg == qp->sq.qend)))
3699 		*seg = mlx5_get_send_wqe(qp, 0);
3700 	set_linv_mkey_seg(*seg);
3701 	*seg += sizeof(struct mlx5_mkey_seg);
3702 	*size += sizeof(struct mlx5_mkey_seg) / 16;
3703 	if (unlikely((*seg == qp->sq.qend)))
3704 		*seg = mlx5_get_send_wqe(qp, 0);
3705 }
3706 
3707 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3708 {
3709 	__be32 *p = NULL;
3710 	int tidx = idx;
3711 	int i, j;
3712 
3713 	pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3714 	for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3715 		if ((i & 0xf) == 0) {
3716 			void *buf = mlx5_get_send_wqe(qp, tidx);
3717 			tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3718 			p = buf;
3719 			j = 0;
3720 		}
3721 		pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3722 			 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3723 			 be32_to_cpu(p[j + 3]));
3724 	}
3725 }
3726 
3727 static u8 get_fence(u8 fence, struct ib_send_wr *wr)
3728 {
3729 	if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
3730 		     wr->send_flags & IB_SEND_FENCE))
3731 		return MLX5_FENCE_MODE_STRONG_ORDERING;
3732 
3733 	if (unlikely(fence)) {
3734 		if (wr->send_flags & IB_SEND_FENCE)
3735 			return MLX5_FENCE_MODE_SMALL_AND_FENCE;
3736 		else
3737 			return fence;
3738 	} else if (unlikely(wr->send_flags & IB_SEND_FENCE)) {
3739 		return MLX5_FENCE_MODE_FENCE;
3740 	}
3741 
3742 	return 0;
3743 }
3744 
3745 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3746 		     struct mlx5_wqe_ctrl_seg **ctrl,
3747 		     struct ib_send_wr *wr, unsigned *idx,
3748 		     int *size, int nreq)
3749 {
3750 	if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
3751 		return -ENOMEM;
3752 
3753 	*idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3754 	*seg = mlx5_get_send_wqe(qp, *idx);
3755 	*ctrl = *seg;
3756 	*(uint32_t *)(*seg + 8) = 0;
3757 	(*ctrl)->imm = send_ieth(wr);
3758 	(*ctrl)->fm_ce_se = qp->sq_signal_bits |
3759 		(wr->send_flags & IB_SEND_SIGNALED ?
3760 		 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3761 		(wr->send_flags & IB_SEND_SOLICITED ?
3762 		 MLX5_WQE_CTRL_SOLICITED : 0);
3763 
3764 	*seg += sizeof(**ctrl);
3765 	*size = sizeof(**ctrl) / 16;
3766 
3767 	return 0;
3768 }
3769 
3770 static void finish_wqe(struct mlx5_ib_qp *qp,
3771 		       struct mlx5_wqe_ctrl_seg *ctrl,
3772 		       u8 size, unsigned idx, u64 wr_id,
3773 		       int nreq, u8 fence, u8 next_fence,
3774 		       u32 mlx5_opcode)
3775 {
3776 	u8 opmod = 0;
3777 
3778 	ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3779 					     mlx5_opcode | ((u32)opmod << 24));
3780 	ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
3781 	ctrl->fm_ce_se |= fence;
3782 	qp->fm_cache = next_fence;
3783 	if (unlikely(qp->wq_sig))
3784 		ctrl->signature = wq_sig(ctrl);
3785 
3786 	qp->sq.wrid[idx] = wr_id;
3787 	qp->sq.w_list[idx].opcode = mlx5_opcode;
3788 	qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3789 	qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3790 	qp->sq.w_list[idx].next = qp->sq.cur_post;
3791 }
3792 
3793 
3794 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3795 		      struct ib_send_wr **bad_wr)
3796 {
3797 	struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
3798 	struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3799 	struct mlx5_core_dev *mdev = dev->mdev;
3800 	struct mlx5_ib_qp *qp;
3801 	struct mlx5_ib_mr *mr;
3802 	struct mlx5_wqe_data_seg *dpseg;
3803 	struct mlx5_wqe_xrc_seg *xrc;
3804 	struct mlx5_bf *bf;
3805 	int uninitialized_var(size);
3806 	void *qend;
3807 	unsigned long flags;
3808 	unsigned idx;
3809 	int err = 0;
3810 	int inl = 0;
3811 	int num_sge;
3812 	void *seg;
3813 	int nreq;
3814 	int i;
3815 	u8 next_fence = 0;
3816 	u8 fence;
3817 
3818 	if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3819 		return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3820 
3821 	qp = to_mqp(ibqp);
3822 	bf = &qp->bf;
3823 	qend = qp->sq.qend;
3824 
3825 	spin_lock_irqsave(&qp->sq.lock, flags);
3826 
3827 	if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
3828 		err = -EIO;
3829 		*bad_wr = wr;
3830 		nreq = 0;
3831 		goto out;
3832 	}
3833 
3834 	for (nreq = 0; wr; nreq++, wr = wr->next) {
3835 		if (unlikely(wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
3836 			mlx5_ib_warn(dev, "\n");
3837 			err = -EINVAL;
3838 			*bad_wr = wr;
3839 			goto out;
3840 		}
3841 
3842 		fence = qp->fm_cache;
3843 		num_sge = wr->num_sge;
3844 		if (unlikely(num_sge > qp->sq.max_gs)) {
3845 			mlx5_ib_warn(dev, "\n");
3846 			err = -EINVAL;
3847 			*bad_wr = wr;
3848 			goto out;
3849 		}
3850 
3851 		err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3852 		if (err) {
3853 			mlx5_ib_warn(dev, "\n");
3854 			err = -ENOMEM;
3855 			*bad_wr = wr;
3856 			goto out;
3857 		}
3858 
3859 		switch (ibqp->qp_type) {
3860 		case IB_QPT_XRC_INI:
3861 			xrc = seg;
3862 			seg += sizeof(*xrc);
3863 			size += sizeof(*xrc) / 16;
3864 			/* fall through */
3865 		case IB_QPT_RC:
3866 			switch (wr->opcode) {
3867 			case IB_WR_RDMA_READ:
3868 			case IB_WR_RDMA_WRITE:
3869 			case IB_WR_RDMA_WRITE_WITH_IMM:
3870 				set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3871 					      rdma_wr(wr)->rkey);
3872 				seg += sizeof(struct mlx5_wqe_raddr_seg);
3873 				size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3874 				break;
3875 
3876 			case IB_WR_ATOMIC_CMP_AND_SWP:
3877 			case IB_WR_ATOMIC_FETCH_AND_ADD:
3878 			case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3879 				mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3880 				err = -ENOSYS;
3881 				*bad_wr = wr;
3882 				goto out;
3883 
3884 			case IB_WR_LOCAL_INV:
3885 				next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3886 				qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3887 				ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
3888 				set_linv_wr(qp, &seg, &size);
3889 				num_sge = 0;
3890 				break;
3891 
3892 			case IB_WR_REG_MR:
3893 				next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3894 				qp->sq.wr_data[idx] = IB_WR_REG_MR;
3895 				ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3896 				err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3897 				if (err) {
3898 					*bad_wr = wr;
3899 					goto out;
3900 				}
3901 				num_sge = 0;
3902 				break;
3903 
3904 			case IB_WR_REG_SIG_MR:
3905 				qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
3906 				mr = to_mmr(sig_handover_wr(wr)->sig_mr);
3907 
3908 				ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3909 				err = set_sig_umr_wr(wr, qp, &seg, &size);
3910 				if (err) {
3911 					mlx5_ib_warn(dev, "\n");
3912 					*bad_wr = wr;
3913 					goto out;
3914 				}
3915 
3916 				finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3917 					   nreq, get_fence(fence, wr),
3918 					   next_fence, MLX5_OPCODE_UMR);
3919 				/*
3920 				 * SET_PSV WQEs are not signaled and solicited
3921 				 * on error
3922 				 */
3923 				wr->send_flags &= ~IB_SEND_SIGNALED;
3924 				wr->send_flags |= IB_SEND_SOLICITED;
3925 				err = begin_wqe(qp, &seg, &ctrl, wr,
3926 						&idx, &size, nreq);
3927 				if (err) {
3928 					mlx5_ib_warn(dev, "\n");
3929 					err = -ENOMEM;
3930 					*bad_wr = wr;
3931 					goto out;
3932 				}
3933 
3934 				err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
3935 						 mr->sig->psv_memory.psv_idx, &seg,
3936 						 &size);
3937 				if (err) {
3938 					mlx5_ib_warn(dev, "\n");
3939 					*bad_wr = wr;
3940 					goto out;
3941 				}
3942 
3943 				finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3944 					   nreq, get_fence(fence, wr),
3945 					   next_fence, MLX5_OPCODE_SET_PSV);
3946 				err = begin_wqe(qp, &seg, &ctrl, wr,
3947 						&idx, &size, nreq);
3948 				if (err) {
3949 					mlx5_ib_warn(dev, "\n");
3950 					err = -ENOMEM;
3951 					*bad_wr = wr;
3952 					goto out;
3953 				}
3954 
3955 				next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3956 				err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
3957 						 mr->sig->psv_wire.psv_idx, &seg,
3958 						 &size);
3959 				if (err) {
3960 					mlx5_ib_warn(dev, "\n");
3961 					*bad_wr = wr;
3962 					goto out;
3963 				}
3964 
3965 				finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3966 					   nreq, get_fence(fence, wr),
3967 					   next_fence, MLX5_OPCODE_SET_PSV);
3968 				num_sge = 0;
3969 				goto skip_psv;
3970 
3971 			default:
3972 				break;
3973 			}
3974 			break;
3975 
3976 		case IB_QPT_UC:
3977 			switch (wr->opcode) {
3978 			case IB_WR_RDMA_WRITE:
3979 			case IB_WR_RDMA_WRITE_WITH_IMM:
3980 				set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3981 					      rdma_wr(wr)->rkey);
3982 				seg  += sizeof(struct mlx5_wqe_raddr_seg);
3983 				size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3984 				break;
3985 
3986 			default:
3987 				break;
3988 			}
3989 			break;
3990 
3991 		case IB_QPT_SMI:
3992 		case MLX5_IB_QPT_HW_GSI:
3993 			set_datagram_seg(seg, wr);
3994 			seg += sizeof(struct mlx5_wqe_datagram_seg);
3995 			size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3996 			if (unlikely((seg == qend)))
3997 				seg = mlx5_get_send_wqe(qp, 0);
3998 			break;
3999 		case IB_QPT_UD:
4000 			set_datagram_seg(seg, wr);
4001 			seg += sizeof(struct mlx5_wqe_datagram_seg);
4002 			size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4003 
4004 			if (unlikely((seg == qend)))
4005 				seg = mlx5_get_send_wqe(qp, 0);
4006 
4007 			/* handle qp that supports ud offload */
4008 			if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4009 				struct mlx5_wqe_eth_pad *pad;
4010 
4011 				pad = seg;
4012 				memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4013 				seg += sizeof(struct mlx5_wqe_eth_pad);
4014 				size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4015 
4016 				seg = set_eth_seg(seg, wr, qend, qp, &size);
4017 
4018 				if (unlikely((seg == qend)))
4019 					seg = mlx5_get_send_wqe(qp, 0);
4020 			}
4021 			break;
4022 		case MLX5_IB_QPT_REG_UMR:
4023 			if (wr->opcode != MLX5_IB_WR_UMR) {
4024 				err = -EINVAL;
4025 				mlx5_ib_warn(dev, "bad opcode\n");
4026 				goto out;
4027 			}
4028 			qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4029 			ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4030 			set_reg_umr_segment(seg, wr);
4031 			seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4032 			size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4033 			if (unlikely((seg == qend)))
4034 				seg = mlx5_get_send_wqe(qp, 0);
4035 			set_reg_mkey_segment(seg, wr);
4036 			seg += sizeof(struct mlx5_mkey_seg);
4037 			size += sizeof(struct mlx5_mkey_seg) / 16;
4038 			if (unlikely((seg == qend)))
4039 				seg = mlx5_get_send_wqe(qp, 0);
4040 			break;
4041 
4042 		default:
4043 			break;
4044 		}
4045 
4046 		if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4047 			int uninitialized_var(sz);
4048 
4049 			err = set_data_inl_seg(qp, wr, seg, &sz);
4050 			if (unlikely(err)) {
4051 				mlx5_ib_warn(dev, "\n");
4052 				*bad_wr = wr;
4053 				goto out;
4054 			}
4055 			inl = 1;
4056 			size += sz;
4057 		} else {
4058 			dpseg = seg;
4059 			for (i = 0; i < num_sge; i++) {
4060 				if (unlikely(dpseg == qend)) {
4061 					seg = mlx5_get_send_wqe(qp, 0);
4062 					dpseg = seg;
4063 				}
4064 				if (likely(wr->sg_list[i].length)) {
4065 					set_data_ptr_seg(dpseg, wr->sg_list + i);
4066 					size += sizeof(struct mlx5_wqe_data_seg) / 16;
4067 					dpseg++;
4068 				}
4069 			}
4070 		}
4071 
4072 		finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4073 			   get_fence(fence, wr), next_fence,
4074 			   mlx5_ib_opcode[wr->opcode]);
4075 skip_psv:
4076 		if (0)
4077 			dump_wqe(qp, idx, size);
4078 	}
4079 
4080 out:
4081 	if (likely(nreq)) {
4082 		qp->sq.head += nreq;
4083 
4084 		/* Make sure that descriptors are written before
4085 		 * updating doorbell record and ringing the doorbell
4086 		 */
4087 		wmb();
4088 
4089 		qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4090 
4091 		/* Make sure doorbell record is visible to the HCA before
4092 		 * we hit doorbell */
4093 		wmb();
4094 
4095 		mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset,
4096 			     MLX5_GET_DOORBELL_LOCK(&bf->lock32));
4097 		/* Make sure doorbells don't leak out of SQ spinlock
4098 		 * and reach the HCA out of order.
4099 		 */
4100 		bf->offset ^= bf->buf_size;
4101 	}
4102 
4103 	spin_unlock_irqrestore(&qp->sq.lock, flags);
4104 
4105 	return err;
4106 }
4107 
4108 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4109 {
4110 	sig->signature = calc_sig(sig, size);
4111 }
4112 
4113 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4114 		      struct ib_recv_wr **bad_wr)
4115 {
4116 	struct mlx5_ib_qp *qp = to_mqp(ibqp);
4117 	struct mlx5_wqe_data_seg *scat;
4118 	struct mlx5_rwqe_sig *sig;
4119 	struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4120 	struct mlx5_core_dev *mdev = dev->mdev;
4121 	unsigned long flags;
4122 	int err = 0;
4123 	int nreq;
4124 	int ind;
4125 	int i;
4126 
4127 	if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4128 		return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4129 
4130 	spin_lock_irqsave(&qp->rq.lock, flags);
4131 
4132 	if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4133 		err = -EIO;
4134 		*bad_wr = wr;
4135 		nreq = 0;
4136 		goto out;
4137 	}
4138 
4139 	ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4140 
4141 	for (nreq = 0; wr; nreq++, wr = wr->next) {
4142 		if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4143 			err = -ENOMEM;
4144 			*bad_wr = wr;
4145 			goto out;
4146 		}
4147 
4148 		if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4149 			err = -EINVAL;
4150 			*bad_wr = wr;
4151 			goto out;
4152 		}
4153 
4154 		scat = get_recv_wqe(qp, ind);
4155 		if (qp->wq_sig)
4156 			scat++;
4157 
4158 		for (i = 0; i < wr->num_sge; i++)
4159 			set_data_ptr_seg(scat + i, wr->sg_list + i);
4160 
4161 		if (i < qp->rq.max_gs) {
4162 			scat[i].byte_count = 0;
4163 			scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
4164 			scat[i].addr       = 0;
4165 		}
4166 
4167 		if (qp->wq_sig) {
4168 			sig = (struct mlx5_rwqe_sig *)scat;
4169 			set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4170 		}
4171 
4172 		qp->rq.wrid[ind] = wr->wr_id;
4173 
4174 		ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4175 	}
4176 
4177 out:
4178 	if (likely(nreq)) {
4179 		qp->rq.head += nreq;
4180 
4181 		/* Make sure that descriptors are written before
4182 		 * doorbell record.
4183 		 */
4184 		wmb();
4185 
4186 		*qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4187 	}
4188 
4189 	spin_unlock_irqrestore(&qp->rq.lock, flags);
4190 
4191 	return err;
4192 }
4193 
4194 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4195 {
4196 	switch (mlx5_state) {
4197 	case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
4198 	case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
4199 	case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
4200 	case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
4201 	case MLX5_QP_STATE_SQ_DRAINING:
4202 	case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
4203 	case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
4204 	case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
4205 	default:		     return -1;
4206 	}
4207 }
4208 
4209 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4210 {
4211 	switch (mlx5_mig_state) {
4212 	case MLX5_QP_PM_ARMED:		return IB_MIG_ARMED;
4213 	case MLX5_QP_PM_REARM:		return IB_MIG_REARM;
4214 	case MLX5_QP_PM_MIGRATED:	return IB_MIG_MIGRATED;
4215 	default: return -1;
4216 	}
4217 }
4218 
4219 static int to_ib_qp_access_flags(int mlx5_flags)
4220 {
4221 	int ib_flags = 0;
4222 
4223 	if (mlx5_flags & MLX5_QP_BIT_RRE)
4224 		ib_flags |= IB_ACCESS_REMOTE_READ;
4225 	if (mlx5_flags & MLX5_QP_BIT_RWE)
4226 		ib_flags |= IB_ACCESS_REMOTE_WRITE;
4227 	if (mlx5_flags & MLX5_QP_BIT_RAE)
4228 		ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4229 
4230 	return ib_flags;
4231 }
4232 
4233 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
4234 				struct mlx5_qp_path *path)
4235 {
4236 	struct mlx5_core_dev *dev = ibdev->mdev;
4237 
4238 	memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
4239 	ib_ah_attr->port_num	  = path->port;
4240 
4241 	if (ib_ah_attr->port_num == 0 ||
4242 	    ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports))
4243 		return;
4244 
4245 	ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf;
4246 
4247 	ib_ah_attr->dlid	  = be16_to_cpu(path->rlid);
4248 	ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
4249 	ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
4250 	ib_ah_attr->ah_flags      = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
4251 	if (ib_ah_attr->ah_flags) {
4252 		ib_ah_attr->grh.sgid_index = path->mgid_index;
4253 		ib_ah_attr->grh.hop_limit  = path->hop_limit;
4254 		ib_ah_attr->grh.traffic_class =
4255 			(be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
4256 		ib_ah_attr->grh.flow_label =
4257 			be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
4258 		memcpy(ib_ah_attr->grh.dgid.raw,
4259 		       path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
4260 	}
4261 }
4262 
4263 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4264 					struct mlx5_ib_sq *sq,
4265 					u8 *sq_state)
4266 {
4267 	void *out;
4268 	void *sqc;
4269 	int inlen;
4270 	int err;
4271 
4272 	inlen = MLX5_ST_SZ_BYTES(query_sq_out);
4273 	out = mlx5_vzalloc(inlen);
4274 	if (!out)
4275 		return -ENOMEM;
4276 
4277 	err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4278 	if (err)
4279 		goto out;
4280 
4281 	sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4282 	*sq_state = MLX5_GET(sqc, sqc, state);
4283 	sq->state = *sq_state;
4284 
4285 out:
4286 	kvfree(out);
4287 	return err;
4288 }
4289 
4290 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4291 					struct mlx5_ib_rq *rq,
4292 					u8 *rq_state)
4293 {
4294 	void *out;
4295 	void *rqc;
4296 	int inlen;
4297 	int err;
4298 
4299 	inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4300 	out = mlx5_vzalloc(inlen);
4301 	if (!out)
4302 		return -ENOMEM;
4303 
4304 	err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4305 	if (err)
4306 		goto out;
4307 
4308 	rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4309 	*rq_state = MLX5_GET(rqc, rqc, state);
4310 	rq->state = *rq_state;
4311 
4312 out:
4313 	kvfree(out);
4314 	return err;
4315 }
4316 
4317 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4318 				  struct mlx5_ib_qp *qp, u8 *qp_state)
4319 {
4320 	static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4321 		[MLX5_RQC_STATE_RST] = {
4322 			[MLX5_SQC_STATE_RST]	= IB_QPS_RESET,
4323 			[MLX5_SQC_STATE_RDY]	= MLX5_QP_STATE_BAD,
4324 			[MLX5_SQC_STATE_ERR]	= MLX5_QP_STATE_BAD,
4325 			[MLX5_SQ_STATE_NA]	= IB_QPS_RESET,
4326 		},
4327 		[MLX5_RQC_STATE_RDY] = {
4328 			[MLX5_SQC_STATE_RST]	= MLX5_QP_STATE_BAD,
4329 			[MLX5_SQC_STATE_RDY]	= MLX5_QP_STATE,
4330 			[MLX5_SQC_STATE_ERR]	= IB_QPS_SQE,
4331 			[MLX5_SQ_STATE_NA]	= MLX5_QP_STATE,
4332 		},
4333 		[MLX5_RQC_STATE_ERR] = {
4334 			[MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
4335 			[MLX5_SQC_STATE_RDY]	= MLX5_QP_STATE_BAD,
4336 			[MLX5_SQC_STATE_ERR]	= IB_QPS_ERR,
4337 			[MLX5_SQ_STATE_NA]	= IB_QPS_ERR,
4338 		},
4339 		[MLX5_RQ_STATE_NA] = {
4340 			[MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
4341 			[MLX5_SQC_STATE_RDY]	= MLX5_QP_STATE,
4342 			[MLX5_SQC_STATE_ERR]	= MLX5_QP_STATE,
4343 			[MLX5_SQ_STATE_NA]	= MLX5_QP_STATE_BAD,
4344 		},
4345 	};
4346 
4347 	*qp_state = sqrq_trans[rq_state][sq_state];
4348 
4349 	if (*qp_state == MLX5_QP_STATE_BAD) {
4350 		WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4351 		     qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4352 		     qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4353 		return -EINVAL;
4354 	}
4355 
4356 	if (*qp_state == MLX5_QP_STATE)
4357 		*qp_state = qp->state;
4358 
4359 	return 0;
4360 }
4361 
4362 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4363 				     struct mlx5_ib_qp *qp,
4364 				     u8 *raw_packet_qp_state)
4365 {
4366 	struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4367 	struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4368 	struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4369 	int err;
4370 	u8 sq_state = MLX5_SQ_STATE_NA;
4371 	u8 rq_state = MLX5_RQ_STATE_NA;
4372 
4373 	if (qp->sq.wqe_cnt) {
4374 		err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4375 		if (err)
4376 			return err;
4377 	}
4378 
4379 	if (qp->rq.wqe_cnt) {
4380 		err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4381 		if (err)
4382 			return err;
4383 	}
4384 
4385 	return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4386 				      raw_packet_qp_state);
4387 }
4388 
4389 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4390 			 struct ib_qp_attr *qp_attr)
4391 {
4392 	int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
4393 	struct mlx5_qp_context *context;
4394 	int mlx5_state;
4395 	u32 *outb;
4396 	int err = 0;
4397 
4398 	outb = kzalloc(outlen, GFP_KERNEL);
4399 	if (!outb)
4400 		return -ENOMEM;
4401 
4402 	err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
4403 				 outlen);
4404 	if (err)
4405 		goto out;
4406 
4407 	/* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4408 	context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4409 
4410 	mlx5_state = be32_to_cpu(context->flags) >> 28;
4411 
4412 	qp->state		     = to_ib_qp_state(mlx5_state);
4413 	qp_attr->path_mtu	     = context->mtu_msgmax >> 5;
4414 	qp_attr->path_mig_state	     =
4415 		to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4416 	qp_attr->qkey		     = be32_to_cpu(context->qkey);
4417 	qp_attr->rq_psn		     = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4418 	qp_attr->sq_psn		     = be32_to_cpu(context->next_send_psn) & 0xffffff;
4419 	qp_attr->dest_qp_num	     = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4420 	qp_attr->qp_access_flags     =
4421 		to_ib_qp_access_flags(be32_to_cpu(context->params2));
4422 
4423 	if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4424 		to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4425 		to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
4426 		qp_attr->alt_pkey_index =
4427 			be16_to_cpu(context->alt_path.pkey_index);
4428 		qp_attr->alt_port_num	= qp_attr->alt_ah_attr.port_num;
4429 	}
4430 
4431 	qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
4432 	qp_attr->port_num = context->pri_path.port;
4433 
4434 	/* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4435 	qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4436 
4437 	qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4438 
4439 	qp_attr->max_dest_rd_atomic =
4440 		1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4441 	qp_attr->min_rnr_timer	    =
4442 		(be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4443 	qp_attr->timeout	    = context->pri_path.ackto_lt >> 3;
4444 	qp_attr->retry_cnt	    = (be32_to_cpu(context->params1) >> 16) & 0x7;
4445 	qp_attr->rnr_retry	    = (be32_to_cpu(context->params1) >> 13) & 0x7;
4446 	qp_attr->alt_timeout	    = context->alt_path.ackto_lt >> 3;
4447 
4448 out:
4449 	kfree(outb);
4450 	return err;
4451 }
4452 
4453 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4454 		     int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4455 {
4456 	struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4457 	struct mlx5_ib_qp *qp = to_mqp(ibqp);
4458 	int err = 0;
4459 	u8 raw_packet_qp_state;
4460 
4461 	if (ibqp->rwq_ind_tbl)
4462 		return -ENOSYS;
4463 
4464 	if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4465 		return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4466 					    qp_init_attr);
4467 
4468 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4469 	/*
4470 	 * Wait for any outstanding page faults, in case the user frees memory
4471 	 * based upon this query's result.
4472 	 */
4473 	flush_workqueue(mlx5_ib_page_fault_wq);
4474 #endif
4475 
4476 	mutex_lock(&qp->mutex);
4477 
4478 	if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
4479 		err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4480 		if (err)
4481 			goto out;
4482 		qp->state = raw_packet_qp_state;
4483 		qp_attr->port_num = 1;
4484 	} else {
4485 		err = query_qp_attr(dev, qp, qp_attr);
4486 		if (err)
4487 			goto out;
4488 	}
4489 
4490 	qp_attr->qp_state	     = qp->state;
4491 	qp_attr->cur_qp_state	     = qp_attr->qp_state;
4492 	qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
4493 	qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
4494 
4495 	if (!ibqp->uobject) {
4496 		qp_attr->cap.max_send_wr  = qp->sq.max_post;
4497 		qp_attr->cap.max_send_sge = qp->sq.max_gs;
4498 		qp_init_attr->qp_context = ibqp->qp_context;
4499 	} else {
4500 		qp_attr->cap.max_send_wr  = 0;
4501 		qp_attr->cap.max_send_sge = 0;
4502 	}
4503 
4504 	qp_init_attr->qp_type = ibqp->qp_type;
4505 	qp_init_attr->recv_cq = ibqp->recv_cq;
4506 	qp_init_attr->send_cq = ibqp->send_cq;
4507 	qp_init_attr->srq = ibqp->srq;
4508 	qp_attr->cap.max_inline_data = qp->max_inline_data;
4509 
4510 	qp_init_attr->cap	     = qp_attr->cap;
4511 
4512 	qp_init_attr->create_flags = 0;
4513 	if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4514 		qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4515 
4516 	if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4517 		qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4518 	if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4519 		qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4520 	if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4521 		qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
4522 	if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4523 		qp_init_attr->create_flags |= MLX5_IB_QP_CREATE_SQPN_QP1;
4524 
4525 	qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4526 		IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4527 
4528 out:
4529 	mutex_unlock(&qp->mutex);
4530 	return err;
4531 }
4532 
4533 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4534 					  struct ib_ucontext *context,
4535 					  struct ib_udata *udata)
4536 {
4537 	struct mlx5_ib_dev *dev = to_mdev(ibdev);
4538 	struct mlx5_ib_xrcd *xrcd;
4539 	int err;
4540 
4541 	if (!MLX5_CAP_GEN(dev->mdev, xrc))
4542 		return ERR_PTR(-ENOSYS);
4543 
4544 	xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4545 	if (!xrcd)
4546 		return ERR_PTR(-ENOMEM);
4547 
4548 	err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
4549 	if (err) {
4550 		kfree(xrcd);
4551 		return ERR_PTR(-ENOMEM);
4552 	}
4553 
4554 	return &xrcd->ibxrcd;
4555 }
4556 
4557 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4558 {
4559 	struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4560 	u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4561 	int err;
4562 
4563 	err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
4564 	if (err) {
4565 		mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4566 		return err;
4567 	}
4568 
4569 	kfree(xrcd);
4570 
4571 	return 0;
4572 }
4573 
4574 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4575 {
4576 	struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4577 	struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4578 	struct ib_event event;
4579 
4580 	if (rwq->ibwq.event_handler) {
4581 		event.device     = rwq->ibwq.device;
4582 		event.element.wq = &rwq->ibwq;
4583 		switch (type) {
4584 		case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4585 			event.event = IB_EVENT_WQ_FATAL;
4586 			break;
4587 		default:
4588 			mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4589 			return;
4590 		}
4591 
4592 		rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4593 	}
4594 }
4595 
4596 static int  create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4597 		      struct ib_wq_init_attr *init_attr)
4598 {
4599 	struct mlx5_ib_dev *dev;
4600 	__be64 *rq_pas0;
4601 	void *in;
4602 	void *rqc;
4603 	void *wq;
4604 	int inlen;
4605 	int err;
4606 
4607 	dev = to_mdev(pd->device);
4608 
4609 	inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4610 	in = mlx5_vzalloc(inlen);
4611 	if (!in)
4612 		return -ENOMEM;
4613 
4614 	rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4615 	MLX5_SET(rqc,  rqc, mem_rq_type,
4616 		 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE);
4617 	MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4618 	MLX5_SET(rqc,  rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4619 	MLX5_SET(rqc,  rqc, state, MLX5_RQC_STATE_RST);
4620 	MLX5_SET(rqc,  rqc, flush_in_error_en, 1);
4621 	wq = MLX5_ADDR_OF(rqc, rqc, wq);
4622 	MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
4623 	MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4624 	MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4625 	MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4626 	MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4627 	MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4628 	MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4629 	MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4630 	MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4631 	rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4632 	mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
4633 	err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
4634 	kvfree(in);
4635 	return err;
4636 }
4637 
4638 static int set_user_rq_size(struct mlx5_ib_dev *dev,
4639 			    struct ib_wq_init_attr *wq_init_attr,
4640 			    struct mlx5_ib_create_wq *ucmd,
4641 			    struct mlx5_ib_rwq *rwq)
4642 {
4643 	/* Sanity check RQ size before proceeding */
4644 	if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4645 		return -EINVAL;
4646 
4647 	if (!ucmd->rq_wqe_count)
4648 		return -EINVAL;
4649 
4650 	rwq->wqe_count = ucmd->rq_wqe_count;
4651 	rwq->wqe_shift = ucmd->rq_wqe_shift;
4652 	rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4653 	rwq->log_rq_stride = rwq->wqe_shift;
4654 	rwq->log_rq_size = ilog2(rwq->wqe_count);
4655 	return 0;
4656 }
4657 
4658 static int prepare_user_rq(struct ib_pd *pd,
4659 			   struct ib_wq_init_attr *init_attr,
4660 			   struct ib_udata *udata,
4661 			   struct mlx5_ib_rwq *rwq)
4662 {
4663 	struct mlx5_ib_dev *dev = to_mdev(pd->device);
4664 	struct mlx5_ib_create_wq ucmd = {};
4665 	int err;
4666 	size_t required_cmd_sz;
4667 
4668 	required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4669 	if (udata->inlen < required_cmd_sz) {
4670 		mlx5_ib_dbg(dev, "invalid inlen\n");
4671 		return -EINVAL;
4672 	}
4673 
4674 	if (udata->inlen > sizeof(ucmd) &&
4675 	    !ib_is_udata_cleared(udata, sizeof(ucmd),
4676 				 udata->inlen - sizeof(ucmd))) {
4677 		mlx5_ib_dbg(dev, "inlen is not supported\n");
4678 		return -EOPNOTSUPP;
4679 	}
4680 
4681 	if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4682 		mlx5_ib_dbg(dev, "copy failed\n");
4683 		return -EFAULT;
4684 	}
4685 
4686 	if (ucmd.comp_mask) {
4687 		mlx5_ib_dbg(dev, "invalid comp mask\n");
4688 		return -EOPNOTSUPP;
4689 	}
4690 
4691 	if (ucmd.reserved) {
4692 		mlx5_ib_dbg(dev, "invalid reserved\n");
4693 		return -EOPNOTSUPP;
4694 	}
4695 
4696 	err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4697 	if (err) {
4698 		mlx5_ib_dbg(dev, "err %d\n", err);
4699 		return err;
4700 	}
4701 
4702 	err = create_user_rq(dev, pd, rwq, &ucmd);
4703 	if (err) {
4704 		mlx5_ib_dbg(dev, "err %d\n", err);
4705 		if (err)
4706 			return err;
4707 	}
4708 
4709 	rwq->user_index = ucmd.user_index;
4710 	return 0;
4711 }
4712 
4713 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4714 				struct ib_wq_init_attr *init_attr,
4715 				struct ib_udata *udata)
4716 {
4717 	struct mlx5_ib_dev *dev;
4718 	struct mlx5_ib_rwq *rwq;
4719 	struct mlx5_ib_create_wq_resp resp = {};
4720 	size_t min_resp_len;
4721 	int err;
4722 
4723 	if (!udata)
4724 		return ERR_PTR(-ENOSYS);
4725 
4726 	min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4727 	if (udata->outlen && udata->outlen < min_resp_len)
4728 		return ERR_PTR(-EINVAL);
4729 
4730 	dev = to_mdev(pd->device);
4731 	switch (init_attr->wq_type) {
4732 	case IB_WQT_RQ:
4733 		rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4734 		if (!rwq)
4735 			return ERR_PTR(-ENOMEM);
4736 		err = prepare_user_rq(pd, init_attr, udata, rwq);
4737 		if (err)
4738 			goto err;
4739 		err = create_rq(rwq, pd, init_attr);
4740 		if (err)
4741 			goto err_user_rq;
4742 		break;
4743 	default:
4744 		mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4745 			    init_attr->wq_type);
4746 		return ERR_PTR(-EINVAL);
4747 	}
4748 
4749 	rwq->ibwq.wq_num = rwq->core_qp.qpn;
4750 	rwq->ibwq.state = IB_WQS_RESET;
4751 	if (udata->outlen) {
4752 		resp.response_length = offsetof(typeof(resp), response_length) +
4753 				sizeof(resp.response_length);
4754 		err = ib_copy_to_udata(udata, &resp, resp.response_length);
4755 		if (err)
4756 			goto err_copy;
4757 	}
4758 
4759 	rwq->core_qp.event = mlx5_ib_wq_event;
4760 	rwq->ibwq.event_handler = init_attr->event_handler;
4761 	return &rwq->ibwq;
4762 
4763 err_copy:
4764 	mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4765 err_user_rq:
4766 	destroy_user_rq(pd, rwq);
4767 err:
4768 	kfree(rwq);
4769 	return ERR_PTR(err);
4770 }
4771 
4772 int mlx5_ib_destroy_wq(struct ib_wq *wq)
4773 {
4774 	struct mlx5_ib_dev *dev = to_mdev(wq->device);
4775 	struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4776 
4777 	mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4778 	destroy_user_rq(wq->pd, rwq);
4779 	kfree(rwq);
4780 
4781 	return 0;
4782 }
4783 
4784 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
4785 						      struct ib_rwq_ind_table_init_attr *init_attr,
4786 						      struct ib_udata *udata)
4787 {
4788 	struct mlx5_ib_dev *dev = to_mdev(device);
4789 	struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
4790 	int sz = 1 << init_attr->log_ind_tbl_size;
4791 	struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
4792 	size_t min_resp_len;
4793 	int inlen;
4794 	int err;
4795 	int i;
4796 	u32 *in;
4797 	void *rqtc;
4798 
4799 	if (udata->inlen > 0 &&
4800 	    !ib_is_udata_cleared(udata, 0,
4801 				 udata->inlen))
4802 		return ERR_PTR(-EOPNOTSUPP);
4803 
4804 	if (init_attr->log_ind_tbl_size >
4805 	    MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
4806 		mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
4807 			    init_attr->log_ind_tbl_size,
4808 			    MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
4809 		return ERR_PTR(-EINVAL);
4810 	}
4811 
4812 	min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4813 	if (udata->outlen && udata->outlen < min_resp_len)
4814 		return ERR_PTR(-EINVAL);
4815 
4816 	rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
4817 	if (!rwq_ind_tbl)
4818 		return ERR_PTR(-ENOMEM);
4819 
4820 	inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
4821 	in = mlx5_vzalloc(inlen);
4822 	if (!in) {
4823 		err = -ENOMEM;
4824 		goto err;
4825 	}
4826 
4827 	rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
4828 
4829 	MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
4830 	MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
4831 
4832 	for (i = 0; i < sz; i++)
4833 		MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
4834 
4835 	err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
4836 	kvfree(in);
4837 
4838 	if (err)
4839 		goto err;
4840 
4841 	rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
4842 	if (udata->outlen) {
4843 		resp.response_length = offsetof(typeof(resp), response_length) +
4844 					sizeof(resp.response_length);
4845 		err = ib_copy_to_udata(udata, &resp, resp.response_length);
4846 		if (err)
4847 			goto err_copy;
4848 	}
4849 
4850 	return &rwq_ind_tbl->ib_rwq_ind_tbl;
4851 
4852 err_copy:
4853 	mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4854 err:
4855 	kfree(rwq_ind_tbl);
4856 	return ERR_PTR(err);
4857 }
4858 
4859 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4860 {
4861 	struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
4862 	struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
4863 
4864 	mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4865 
4866 	kfree(rwq_ind_tbl);
4867 	return 0;
4868 }
4869 
4870 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
4871 		      u32 wq_attr_mask, struct ib_udata *udata)
4872 {
4873 	struct mlx5_ib_dev *dev = to_mdev(wq->device);
4874 	struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4875 	struct mlx5_ib_modify_wq ucmd = {};
4876 	size_t required_cmd_sz;
4877 	int curr_wq_state;
4878 	int wq_state;
4879 	int inlen;
4880 	int err;
4881 	void *rqc;
4882 	void *in;
4883 
4884 	required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4885 	if (udata->inlen < required_cmd_sz)
4886 		return -EINVAL;
4887 
4888 	if (udata->inlen > sizeof(ucmd) &&
4889 	    !ib_is_udata_cleared(udata, sizeof(ucmd),
4890 				 udata->inlen - sizeof(ucmd)))
4891 		return -EOPNOTSUPP;
4892 
4893 	if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4894 		return -EFAULT;
4895 
4896 	if (ucmd.comp_mask || ucmd.reserved)
4897 		return -EOPNOTSUPP;
4898 
4899 	inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
4900 	in = mlx5_vzalloc(inlen);
4901 	if (!in)
4902 		return -ENOMEM;
4903 
4904 	rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
4905 
4906 	MLX5_SET(modify_rq_in, in, rqn, rwq->core_qp.qpn);
4907 	curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
4908 		wq_attr->curr_wq_state : wq->state;
4909 	wq_state = (wq_attr_mask & IB_WQ_STATE) ?
4910 		wq_attr->wq_state : curr_wq_state;
4911 	if (curr_wq_state == IB_WQS_ERR)
4912 		curr_wq_state = MLX5_RQC_STATE_ERR;
4913 	if (wq_state == IB_WQS_ERR)
4914 		wq_state = MLX5_RQC_STATE_ERR;
4915 	MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
4916 	MLX5_SET(rqc, rqc, state, wq_state);
4917 
4918 	err = mlx5_core_modify_rq(dev->mdev, in, inlen);
4919 	kvfree(in);
4920 	if (!err)
4921 		rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
4922 
4923 	return err;
4924 }
4925