xref: /freebsd/sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c (revision cf88b86e4954215eb447729042dab8dea722c044)
1 /*-
2  * Copyright (c) 2013-2020, Mellanox Technologies. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  * 1. Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  *
13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23  * SUCH DAMAGE.
24  *
25  * $FreeBSD$
26  */
27 
28 #include <linux/module.h>
29 #include <rdma/ib_umem.h>
30 #include <rdma/ib_cache.h>
31 #include <rdma/ib_user_verbs.h>
32 #include "mlx5_ib.h"
33 
34 /* not supported currently */
35 static int wq_signature;
36 
37 enum {
38 	MLX5_IB_ACK_REQ_FREQ	= 8,
39 };
40 
41 enum {
42 	MLX5_IB_DEFAULT_SCHED_QUEUE	= 0x83,
43 	MLX5_IB_DEFAULT_QP0_SCHED_QUEUE	= 0x3f,
44 	MLX5_IB_LINK_TYPE_IB		= 0,
45 	MLX5_IB_LINK_TYPE_ETH		= 1
46 };
47 
48 enum {
49 	MLX5_IB_SQ_STRIDE	= 6,
50 };
51 
52 static const u32 mlx5_ib_opcode[] = {
53 	[IB_WR_SEND]				= MLX5_OPCODE_SEND,
54 	[IB_WR_LSO]				= MLX5_OPCODE_LSO,
55 	[IB_WR_SEND_WITH_IMM]			= MLX5_OPCODE_SEND_IMM,
56 	[IB_WR_RDMA_WRITE]			= MLX5_OPCODE_RDMA_WRITE,
57 	[IB_WR_RDMA_WRITE_WITH_IMM]		= MLX5_OPCODE_RDMA_WRITE_IMM,
58 	[IB_WR_RDMA_READ]			= MLX5_OPCODE_RDMA_READ,
59 	[IB_WR_ATOMIC_CMP_AND_SWP]		= MLX5_OPCODE_ATOMIC_CS,
60 	[IB_WR_ATOMIC_FETCH_AND_ADD]		= MLX5_OPCODE_ATOMIC_FA,
61 	[IB_WR_SEND_WITH_INV]			= MLX5_OPCODE_SEND_INVAL,
62 	[IB_WR_LOCAL_INV]			= MLX5_OPCODE_UMR,
63 	[IB_WR_REG_MR]				= MLX5_OPCODE_UMR,
64 	[IB_WR_MASKED_ATOMIC_CMP_AND_SWP]	= MLX5_OPCODE_ATOMIC_MASKED_CS,
65 	[IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]	= MLX5_OPCODE_ATOMIC_MASKED_FA,
66 	[MLX5_IB_WR_UMR]			= MLX5_OPCODE_UMR,
67 };
68 
69 struct mlx5_wqe_eth_pad {
70 	u8 rsvd0[16];
71 };
72 
73 enum raw_qp_set_mask_map {
74 	MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID		= 1UL << 0,
75 };
76 
77 struct mlx5_modify_raw_qp_param {
78 	u16 operation;
79 
80 	u32 set_mask; /* raw_qp_set_mask_map */
81 	u8 rq_q_ctr_id;
82 };
83 
84 static void get_cqs(enum ib_qp_type qp_type,
85 		    struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
86 		    struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
87 
88 static int is_qp0(enum ib_qp_type qp_type)
89 {
90 	return qp_type == IB_QPT_SMI;
91 }
92 
93 static int is_sqp(enum ib_qp_type qp_type)
94 {
95 	return is_qp0(qp_type) || is_qp1(qp_type);
96 }
97 
98 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
99 {
100 	return mlx5_buf_offset(&qp->buf, offset);
101 }
102 
103 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
104 {
105 	return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
106 }
107 
108 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
109 {
110 	return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
111 }
112 
113 /**
114  * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
115  *
116  * @qp: QP to copy from.
117  * @send: copy from the send queue when non-zero, use the receive queue
118  *	  otherwise.
119  * @wqe_index:  index to start copying from. For send work queues, the
120  *		wqe_index is in units of MLX5_SEND_WQE_BB.
121  *		For receive work queue, it is the number of work queue
122  *		element in the queue.
123  * @buffer: destination buffer.
124  * @length: maximum number of bytes to copy.
125  *
126  * Copies at least a single WQE, but may copy more data.
127  *
128  * Return: the number of bytes copied, or an error code.
129  */
130 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
131 			  void *buffer, u32 length,
132 			  struct mlx5_ib_qp_base *base)
133 {
134 	struct ib_device *ibdev = qp->ibqp.device;
135 	struct mlx5_ib_dev *dev = to_mdev(ibdev);
136 	struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
137 	size_t offset;
138 	size_t wq_end;
139 	struct ib_umem *umem = base->ubuffer.umem;
140 	u32 first_copy_length;
141 	int wqe_length;
142 	int ret;
143 
144 	if (wq->wqe_cnt == 0) {
145 		mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
146 			    qp->ibqp.qp_type);
147 		return -EINVAL;
148 	}
149 
150 	offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
151 	wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
152 
153 	if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
154 		return -EINVAL;
155 
156 	if (offset > umem->length ||
157 	    (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
158 		return -EINVAL;
159 
160 	first_copy_length = min_t(u32, offset + length, wq_end) - offset;
161 	ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
162 	if (ret)
163 		return ret;
164 
165 	if (send) {
166 		struct mlx5_wqe_ctrl_seg *ctrl = buffer;
167 		int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
168 
169 		wqe_length = ds * MLX5_WQE_DS_UNITS;
170 	} else {
171 		wqe_length = 1 << wq->wqe_shift;
172 	}
173 
174 	if (wqe_length <= first_copy_length)
175 		return first_copy_length;
176 
177 	ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
178 				wqe_length - first_copy_length);
179 	if (ret)
180 		return ret;
181 
182 	return wqe_length;
183 }
184 
185 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
186 {
187 	struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
188 	struct ib_event event;
189 
190 	if (type == MLX5_EVENT_TYPE_PATH_MIG) {
191 		/* This event is only valid for trans_qps */
192 		to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
193 	}
194 
195 	if (ibqp->event_handler) {
196 		event.device     = ibqp->device;
197 		event.element.qp = ibqp;
198 		switch (type) {
199 		case MLX5_EVENT_TYPE_PATH_MIG:
200 			event.event = IB_EVENT_PATH_MIG;
201 			break;
202 		case MLX5_EVENT_TYPE_COMM_EST:
203 			event.event = IB_EVENT_COMM_EST;
204 			break;
205 		case MLX5_EVENT_TYPE_SQ_DRAINED:
206 			event.event = IB_EVENT_SQ_DRAINED;
207 			break;
208 		case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
209 			event.event = IB_EVENT_QP_LAST_WQE_REACHED;
210 			break;
211 		case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
212 			event.event = IB_EVENT_QP_FATAL;
213 			break;
214 		case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
215 			event.event = IB_EVENT_PATH_MIG_ERR;
216 			break;
217 		case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
218 			event.event = IB_EVENT_QP_REQ_ERR;
219 			break;
220 		case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
221 			event.event = IB_EVENT_QP_ACCESS_ERR;
222 			break;
223 		default:
224 			pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
225 			return;
226 		}
227 
228 		ibqp->event_handler(&event, ibqp->qp_context);
229 	}
230 }
231 
232 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
233 		       int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
234 {
235 	int wqe_size;
236 	int wq_size;
237 
238 	/* Sanity check RQ size before proceeding */
239 	if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
240 		return -EINVAL;
241 
242 	if (!has_rq) {
243 		qp->rq.max_gs = 0;
244 		qp->rq.wqe_cnt = 0;
245 		qp->rq.wqe_shift = 0;
246 		cap->max_recv_wr = 0;
247 		cap->max_recv_sge = 0;
248 	} else {
249 		if (ucmd) {
250 			qp->rq.wqe_cnt = ucmd->rq_wqe_count;
251 			qp->rq.wqe_shift = ucmd->rq_wqe_shift;
252 			qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
253 			qp->rq.max_post = qp->rq.wqe_cnt;
254 		} else {
255 			wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
256 			wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
257 			wqe_size = roundup_pow_of_two(wqe_size);
258 			wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
259 			wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
260 			qp->rq.wqe_cnt = wq_size / wqe_size;
261 			if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
262 				mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
263 					    wqe_size,
264 					    MLX5_CAP_GEN(dev->mdev,
265 							 max_wqe_sz_rq));
266 				return -EINVAL;
267 			}
268 			qp->rq.wqe_shift = ilog2(wqe_size);
269 			qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
270 			qp->rq.max_post = qp->rq.wqe_cnt;
271 		}
272 	}
273 
274 	return 0;
275 }
276 
277 static int sq_overhead(struct ib_qp_init_attr *attr)
278 {
279 	int size = 0;
280 
281 	switch (attr->qp_type) {
282 	case IB_QPT_XRC_INI:
283 		size += sizeof(struct mlx5_wqe_xrc_seg);
284 		/* fall through */
285 	case IB_QPT_RC:
286 		size += sizeof(struct mlx5_wqe_ctrl_seg) +
287 			max(sizeof(struct mlx5_wqe_atomic_seg) +
288 			    sizeof(struct mlx5_wqe_raddr_seg),
289 			    sizeof(struct mlx5_wqe_umr_ctrl_seg) +
290 			    sizeof(struct mlx5_mkey_seg));
291 		break;
292 
293 	case IB_QPT_XRC_TGT:
294 		return 0;
295 
296 	case IB_QPT_UC:
297 		size += sizeof(struct mlx5_wqe_ctrl_seg) +
298 			max(sizeof(struct mlx5_wqe_raddr_seg),
299 			    sizeof(struct mlx5_wqe_umr_ctrl_seg) +
300 			    sizeof(struct mlx5_mkey_seg));
301 		break;
302 
303 	case IB_QPT_UD:
304 		if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
305 			size += sizeof(struct mlx5_wqe_eth_pad) +
306 				sizeof(struct mlx5_wqe_eth_seg);
307 		/* fall through */
308 	case IB_QPT_SMI:
309 	case MLX5_IB_QPT_HW_GSI:
310 		size += sizeof(struct mlx5_wqe_ctrl_seg) +
311 			sizeof(struct mlx5_wqe_datagram_seg);
312 		break;
313 
314 	case MLX5_IB_QPT_REG_UMR:
315 		size += sizeof(struct mlx5_wqe_ctrl_seg) +
316 			sizeof(struct mlx5_wqe_umr_ctrl_seg) +
317 			sizeof(struct mlx5_mkey_seg);
318 		break;
319 
320 	default:
321 		return -EINVAL;
322 	}
323 
324 	return size;
325 }
326 
327 static int calc_send_wqe(struct ib_qp_init_attr *attr)
328 {
329 	int inl_size = 0;
330 	int size;
331 
332 	size = sq_overhead(attr);
333 	if (size < 0)
334 		return size;
335 
336 	if (attr->cap.max_inline_data) {
337 		inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
338 			attr->cap.max_inline_data;
339 	}
340 
341 	size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
342 	if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
343 	    ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
344 			return MLX5_SIG_WQE_SIZE;
345 	else
346 		return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
347 }
348 
349 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
350 {
351 	int max_sge;
352 
353 	if (attr->qp_type == IB_QPT_RC)
354 		max_sge = (min_t(int, wqe_size, 512) -
355 			   sizeof(struct mlx5_wqe_ctrl_seg) -
356 			   sizeof(struct mlx5_wqe_raddr_seg)) /
357 			sizeof(struct mlx5_wqe_data_seg);
358 	else if (attr->qp_type == IB_QPT_XRC_INI)
359 		max_sge = (min_t(int, wqe_size, 512) -
360 			   sizeof(struct mlx5_wqe_ctrl_seg) -
361 			   sizeof(struct mlx5_wqe_xrc_seg) -
362 			   sizeof(struct mlx5_wqe_raddr_seg)) /
363 			sizeof(struct mlx5_wqe_data_seg);
364 	else
365 		max_sge = (wqe_size - sq_overhead(attr)) /
366 			sizeof(struct mlx5_wqe_data_seg);
367 
368 	return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
369 		     sizeof(struct mlx5_wqe_data_seg));
370 }
371 
372 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
373 			struct mlx5_ib_qp *qp)
374 {
375 	int wqe_size;
376 	int wq_size;
377 
378 	if (!attr->cap.max_send_wr)
379 		return 0;
380 
381 	wqe_size = calc_send_wqe(attr);
382 	mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
383 	if (wqe_size < 0)
384 		return wqe_size;
385 
386 	if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
387 		mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
388 			    wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
389 		return -EINVAL;
390 	}
391 
392 	qp->max_inline_data = wqe_size - sq_overhead(attr) -
393 			      sizeof(struct mlx5_wqe_inline_seg);
394 	attr->cap.max_inline_data = qp->max_inline_data;
395 
396 	if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
397 		qp->signature_en = true;
398 
399 	wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
400 	qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
401 	if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
402 		mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
403 			    qp->sq.wqe_cnt,
404 			    1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
405 		return -ENOMEM;
406 	}
407 	qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
408 	qp->sq.max_gs = get_send_sge(attr, wqe_size);
409 	if (qp->sq.max_gs < attr->cap.max_send_sge)
410 		return -ENOMEM;
411 
412 	attr->cap.max_send_sge = qp->sq.max_gs;
413 	qp->sq.max_post = wq_size / wqe_size;
414 	attr->cap.max_send_wr = qp->sq.max_post;
415 
416 	return wq_size;
417 }
418 
419 static int set_user_buf_size(struct mlx5_ib_dev *dev,
420 			    struct mlx5_ib_qp *qp,
421 			    struct mlx5_ib_create_qp *ucmd,
422 			    struct mlx5_ib_qp_base *base,
423 			    struct ib_qp_init_attr *attr)
424 {
425 	int desc_sz = 1 << qp->sq.wqe_shift;
426 
427 	if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
428 		mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
429 			     desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
430 		return -EINVAL;
431 	}
432 
433 	if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
434 		mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
435 			     ucmd->sq_wqe_count, ucmd->sq_wqe_count);
436 		return -EINVAL;
437 	}
438 
439 	qp->sq.wqe_cnt = ucmd->sq_wqe_count;
440 
441 	if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
442 		mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
443 			     qp->sq.wqe_cnt,
444 			     1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
445 		return -EINVAL;
446 	}
447 
448 	if (attr->qp_type == IB_QPT_RAW_PACKET) {
449 		base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
450 		qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
451 	} else {
452 		base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
453 					 (qp->sq.wqe_cnt << 6);
454 	}
455 
456 	return 0;
457 }
458 
459 static int qp_has_rq(struct ib_qp_init_attr *attr)
460 {
461 	if (attr->qp_type == IB_QPT_XRC_INI ||
462 	    attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
463 	    attr->qp_type == MLX5_IB_QPT_REG_UMR ||
464 	    !attr->cap.max_recv_wr)
465 		return 0;
466 
467 	return 1;
468 }
469 
470 enum {
471 	/* this is the first blue flame register in the array of bfregs assigned
472 	 * to a processes. Since we do not use it for blue flame but rather
473 	 * regular 64 bit doorbells, we do not need a lock for maintaiing
474 	 * "odd/even" order
475 	 */
476 	NUM_NON_BLUE_FLAME_BFREGS = 1,
477 };
478 
479 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
480 {
481 	return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
482 }
483 
484 static int num_med_bfreg(struct mlx5_ib_dev *dev,
485 			 struct mlx5_bfreg_info *bfregi)
486 {
487 	int n;
488 
489 	n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
490 	    NUM_NON_BLUE_FLAME_BFREGS;
491 
492 	return n >= 0 ? n : 0;
493 }
494 
495 static int first_med_bfreg(struct mlx5_ib_dev *dev,
496 			   struct mlx5_bfreg_info *bfregi)
497 {
498 	return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
499 }
500 
501 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
502 			  struct mlx5_bfreg_info *bfregi)
503 {
504 	int med;
505 
506 	med = num_med_bfreg(dev, bfregi);
507 	return ++med;
508 }
509 
510 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
511 				  struct mlx5_bfreg_info *bfregi)
512 {
513 	int i;
514 
515 	for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
516 		if (!bfregi->count[i]) {
517 			bfregi->count[i]++;
518 			return i;
519 		}
520 	}
521 
522 	return -ENOMEM;
523 }
524 
525 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
526 				 struct mlx5_bfreg_info *bfregi)
527 {
528 	int minidx = first_med_bfreg(dev, bfregi);
529 	int i;
530 
531 	if (minidx < 0)
532 		return minidx;
533 
534 	for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
535 		if (bfregi->count[i] < bfregi->count[minidx])
536 			minidx = i;
537 		if (!bfregi->count[minidx])
538 			break;
539 	}
540 
541 	bfregi->count[minidx]++;
542 	return minidx;
543 }
544 
545 static int alloc_bfreg(struct mlx5_ib_dev *dev,
546 		       struct mlx5_bfreg_info *bfregi)
547 {
548 	int bfregn = -ENOMEM;
549 
550 	if (bfregi->lib_uar_dyn)
551 		return -EINVAL;
552 
553 	mutex_lock(&bfregi->lock);
554 	if (bfregi->ver >= 2) {
555 		bfregn = alloc_high_class_bfreg(dev, bfregi);
556 		if (bfregn < 0)
557 			bfregn = alloc_med_class_bfreg(dev, bfregi);
558 	}
559 
560 	if (bfregn < 0) {
561 		BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
562 		bfregn = 0;
563 		bfregi->count[bfregn]++;
564 	}
565 	mutex_unlock(&bfregi->lock);
566 
567 	return bfregn;
568 }
569 
570 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
571 {
572 	mutex_lock(&bfregi->lock);
573 	bfregi->count[bfregn]--;
574 	mutex_unlock(&bfregi->lock);
575 }
576 
577 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
578 {
579 	switch (state) {
580 	case IB_QPS_RESET:	return MLX5_QP_STATE_RST;
581 	case IB_QPS_INIT:	return MLX5_QP_STATE_INIT;
582 	case IB_QPS_RTR:	return MLX5_QP_STATE_RTR;
583 	case IB_QPS_RTS:	return MLX5_QP_STATE_RTS;
584 	case IB_QPS_SQD:	return MLX5_QP_STATE_SQD;
585 	case IB_QPS_SQE:	return MLX5_QP_STATE_SQER;
586 	case IB_QPS_ERR:	return MLX5_QP_STATE_ERR;
587 	default:		return -1;
588 	}
589 }
590 
591 static int to_mlx5_st(enum ib_qp_type type)
592 {
593 	switch (type) {
594 	case IB_QPT_RC:			return MLX5_QP_ST_RC;
595 	case IB_QPT_UC:			return MLX5_QP_ST_UC;
596 	case IB_QPT_UD:			return MLX5_QP_ST_UD;
597 	case MLX5_IB_QPT_REG_UMR:	return MLX5_QP_ST_REG_UMR;
598 	case IB_QPT_XRC_INI:
599 	case IB_QPT_XRC_TGT:		return MLX5_QP_ST_XRC;
600 	case IB_QPT_SMI:		return MLX5_QP_ST_QP0;
601 	case MLX5_IB_QPT_HW_GSI:	return MLX5_QP_ST_QP1;
602 	case IB_QPT_RAW_IPV6:		return MLX5_QP_ST_RAW_IPV6;
603 	case IB_QPT_RAW_PACKET:
604 	case IB_QPT_RAW_ETHERTYPE:	return MLX5_QP_ST_RAW_ETHERTYPE;
605 	case IB_QPT_MAX:
606 	default:		return -EINVAL;
607 	}
608 }
609 
610 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
611 			     struct mlx5_ib_cq *recv_cq);
612 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
613 			       struct mlx5_ib_cq *recv_cq);
614 
615 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
616 			struct mlx5_bfreg_info *bfregi, u32 bfregn,
617 			bool dyn_bfreg)
618 {
619 	unsigned int bfregs_per_sys_page;
620 	u32 index_of_sys_page;
621 	u32 offset;
622 
623 	if (bfregi->lib_uar_dyn)
624 		return -EINVAL;
625 
626 	bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
627 				MLX5_NON_FP_BFREGS_PER_UAR;
628 	index_of_sys_page = bfregn / bfregs_per_sys_page;
629 
630 	if (dyn_bfreg) {
631 		index_of_sys_page += bfregi->num_static_sys_pages;
632 
633 		if (index_of_sys_page >= bfregi->num_sys_pages)
634 			return -EINVAL;
635 
636 		if (bfregn > bfregi->num_dyn_bfregs ||
637 		    bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
638 			mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
639 			return -EINVAL;
640 		}
641 	}
642 
643 	offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
644 	return bfregi->sys_pages[index_of_sys_page] + offset;
645 }
646 
647 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
648 			    struct ib_pd *pd,
649 			    unsigned long addr, size_t size,
650 			    struct ib_umem **umem,
651 			    int *npages, int *page_shift, int *ncont,
652 			    u32 *offset)
653 {
654 	int err;
655 
656 	*umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
657 	if (IS_ERR(*umem)) {
658 		mlx5_ib_dbg(dev, "umem_get failed\n");
659 		return PTR_ERR(*umem);
660 	}
661 
662 	mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
663 
664 	err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
665 	if (err) {
666 		mlx5_ib_warn(dev, "bad offset\n");
667 		goto err_umem;
668 	}
669 
670 	mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
671 		    addr, size, *npages, *page_shift, *ncont, *offset);
672 
673 	return 0;
674 
675 err_umem:
676 	ib_umem_release(*umem);
677 	*umem = NULL;
678 
679 	return err;
680 }
681 
682 static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq)
683 {
684 	struct mlx5_ib_ucontext *context;
685 
686 	context = to_mucontext(pd->uobject->context);
687 	mlx5_ib_db_unmap_user(context, &rwq->db);
688 	if (rwq->umem)
689 		ib_umem_release(rwq->umem);
690 }
691 
692 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
693 			  struct mlx5_ib_rwq *rwq,
694 			  struct mlx5_ib_create_wq *ucmd)
695 {
696 	struct mlx5_ib_ucontext *context;
697 	int page_shift = 0;
698 	int npages;
699 	u32 offset = 0;
700 	int ncont = 0;
701 	int err;
702 
703 	if (!ucmd->buf_addr)
704 		return -EINVAL;
705 
706 	context = to_mucontext(pd->uobject->context);
707 	rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
708 			       rwq->buf_size, 0, 0);
709 	if (IS_ERR(rwq->umem)) {
710 		mlx5_ib_dbg(dev, "umem_get failed\n");
711 		err = PTR_ERR(rwq->umem);
712 		return err;
713 	}
714 
715 	mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
716 			   &ncont, NULL);
717 	err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
718 				     &rwq->rq_page_offset);
719 	if (err) {
720 		mlx5_ib_warn(dev, "bad offset\n");
721 		goto err_umem;
722 	}
723 
724 	rwq->rq_num_pas = ncont;
725 	rwq->page_shift = page_shift;
726 	rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
727 	rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
728 
729 	mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
730 		    (unsigned long long)ucmd->buf_addr, rwq->buf_size,
731 		    npages, page_shift, ncont, offset);
732 
733 	err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
734 	if (err) {
735 		mlx5_ib_dbg(dev, "map failed\n");
736 		goto err_umem;
737 	}
738 
739 	rwq->create_type = MLX5_WQ_USER;
740 	return 0;
741 
742 err_umem:
743 	ib_umem_release(rwq->umem);
744 	return err;
745 }
746 
747 static int adjust_bfregn(struct mlx5_ib_dev *dev,
748 			 struct mlx5_bfreg_info *bfregi, int bfregn)
749 {
750 	return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
751 				bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
752 }
753 
754 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
755 			  struct mlx5_ib_qp *qp, struct ib_udata *udata,
756 			  struct ib_qp_init_attr *attr,
757 			  u32 **in,
758 			  struct mlx5_ib_create_qp_resp *resp, int *inlen,
759 			  struct mlx5_ib_qp_base *base)
760 {
761 	struct mlx5_ib_ucontext *context;
762 	struct mlx5_ib_create_qp ucmd;
763 	struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
764 	int page_shift = 0;
765 	int uar_index = 0;
766 	int npages;
767 	u32 offset = 0;
768 	int bfregn;
769 	int ncont = 0;
770 	__be64 *pas;
771 	void *qpc;
772 	int err;
773 	u32 uar_flags;
774 
775 	err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
776 	if (err) {
777 		mlx5_ib_dbg(dev, "copy failed\n");
778 		return err;
779 	}
780 
781 	context = to_mucontext(pd->uobject->context);
782 	uar_flags = ucmd.flags & (MLX5_QP_FLAG_UAR_PAGE_INDEX |
783 				  MLX5_QP_FLAG_BFREG_INDEX);
784 	switch (uar_flags) {
785 	case MLX5_QP_FLAG_UAR_PAGE_INDEX:
786 		uar_index = ucmd.bfreg_index;
787 		bfregn = MLX5_IB_INVALID_BFREG;
788 		break;
789 	case MLX5_QP_FLAG_BFREG_INDEX:
790 		uar_index = bfregn_to_uar_index(dev, &context->bfregi,
791 						ucmd.bfreg_index, true);
792 		if (uar_index < 0)
793 			return uar_index;
794 		bfregn = MLX5_IB_INVALID_BFREG;
795 		break;
796 	case 0:
797 		if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
798 			return -EINVAL;
799 		bfregn = alloc_bfreg(dev, &context->bfregi);
800 		if (bfregn < 0)
801 			return bfregn;
802 		break;
803 	default:
804 		return -EINVAL;
805 	}
806 
807 	mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
808 	if (bfregn != MLX5_IB_INVALID_BFREG)
809 		uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
810 						false);
811 
812 	qp->rq.offset = 0;
813 	qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
814 	qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
815 
816 	err = set_user_buf_size(dev, qp, &ucmd, base, attr);
817 	if (err)
818 		goto err_bfreg;
819 
820 	if (ucmd.buf_addr && ubuffer->buf_size) {
821 		ubuffer->buf_addr = ucmd.buf_addr;
822 		err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
823 				       ubuffer->buf_size,
824 				       &ubuffer->umem, &npages, &page_shift,
825 				       &ncont, &offset);
826 		if (err)
827 			goto err_bfreg;
828 	} else {
829 		ubuffer->umem = NULL;
830 	}
831 
832 	*inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
833 		 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
834 	*in = mlx5_vzalloc(*inlen);
835 	if (!*in) {
836 		err = -ENOMEM;
837 		goto err_umem;
838 	}
839 
840 	pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
841 	if (ubuffer->umem)
842 		mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
843 
844 	qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
845 
846 	MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
847 	MLX5_SET(qpc, qpc, page_offset, offset);
848 
849 	MLX5_SET(qpc, qpc, uar_page, uar_index);
850 	if (bfregn != MLX5_IB_INVALID_BFREG)
851 		resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
852 	else
853 		resp->bfreg_index = MLX5_IB_INVALID_BFREG;
854 	qp->bfregn = bfregn;
855 
856 	err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
857 	if (err) {
858 		mlx5_ib_dbg(dev, "map failed\n");
859 		goto err_free;
860 	}
861 
862 	err = ib_copy_to_udata(udata, resp, sizeof(*resp));
863 	if (err) {
864 		mlx5_ib_dbg(dev, "copy failed\n");
865 		goto err_unmap;
866 	}
867 	qp->create_type = MLX5_QP_USER;
868 
869 	return 0;
870 
871 err_unmap:
872 	mlx5_ib_db_unmap_user(context, &qp->db);
873 
874 err_free:
875 	kvfree(*in);
876 
877 err_umem:
878 	if (ubuffer->umem)
879 		ib_umem_release(ubuffer->umem);
880 
881 err_bfreg:
882 	if (bfregn != MLX5_IB_INVALID_BFREG)
883 		mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
884 	return err;
885 }
886 
887 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd, struct mlx5_ib_qp *qp,
888 			    struct mlx5_ib_qp_base *base)
889 {
890 	struct mlx5_ib_ucontext *context;
891 
892 	context = to_mucontext(pd->uobject->context);
893 	mlx5_ib_db_unmap_user(context, &qp->db);
894 	if (base->ubuffer.umem)
895 		ib_umem_release(base->ubuffer.umem);
896 
897 	/*
898 	 * Free only the BFREGs which are handled by the kernel.
899 	 * BFREGs of UARs allocated dynamically are handled by user.
900 	 */
901 	if (qp->bfregn != MLX5_IB_INVALID_BFREG)
902 		mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
903 }
904 
905 static int create_kernel_qp(struct mlx5_ib_dev *dev,
906 			    struct ib_qp_init_attr *init_attr,
907 			    struct mlx5_ib_qp *qp,
908 			    u32 **in, int *inlen,
909 			    struct mlx5_ib_qp_base *base)
910 {
911 	int uar_index;
912 	void *qpc;
913 	int err;
914 
915 	if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
916 					IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
917 					IB_QP_CREATE_IPOIB_UD_LSO |
918 					MLX5_IB_QP_CREATE_SQPN_QP1 |
919 					MLX5_IB_QP_CREATE_WC_TEST))
920 		return -EINVAL;
921 
922 	spin_lock_init(&qp->bf.lock32);
923 
924 	if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
925 		qp->bf.bfreg = &dev->fp_bfreg;
926 	else if (init_attr->create_flags & MLX5_IB_QP_CREATE_WC_TEST)
927 		qp->bf.bfreg = &dev->wc_bfreg;
928 	else
929 		qp->bf.bfreg = &dev->bfreg;
930 
931 	/* We need to divide by two since each register is comprised of
932 	 * two buffers of identical size, namely odd and even
933 	 */
934 	qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
935 	uar_index = qp->bf.bfreg->index;
936 
937 	err = calc_sq_size(dev, init_attr, qp);
938 	if (err < 0) {
939 		mlx5_ib_dbg(dev, "err %d\n", err);
940 		return err;
941 	}
942 
943 	qp->rq.offset = 0;
944 	qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
945 	base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
946 
947 	err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size,
948 	    2 * PAGE_SIZE, &qp->buf);
949 	if (err) {
950 		mlx5_ib_dbg(dev, "err %d\n", err);
951 		return err;
952 	}
953 
954 	qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
955 	*inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
956 		 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
957 	*in = mlx5_vzalloc(*inlen);
958 	if (!*in) {
959 		err = -ENOMEM;
960 		goto err_buf;
961 	}
962 
963 	qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
964 	MLX5_SET(qpc, qpc, uar_page, uar_index);
965 	MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
966 
967 	/* Set "fast registration enabled" for all kernel QPs */
968 	MLX5_SET(qpc, qpc, fre, 1);
969 	MLX5_SET(qpc, qpc, rlky, 1);
970 
971 	if (init_attr->create_flags & MLX5_IB_QP_CREATE_SQPN_QP1) {
972 		MLX5_SET(qpc, qpc, deth_sqpn, 1);
973 		qp->flags |= MLX5_IB_QP_SQPN_QP1;
974 	}
975 
976 	mlx5_fill_page_array(&qp->buf,
977 			     (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
978 
979 	err = mlx5_db_alloc(dev->mdev, &qp->db);
980 	if (err) {
981 		mlx5_ib_dbg(dev, "err %d\n", err);
982 		goto err_free;
983 	}
984 
985 	qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
986 	qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
987 	qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
988 	qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
989 	qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
990 
991 	if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
992 	    !qp->sq.w_list || !qp->sq.wqe_head) {
993 		err = -ENOMEM;
994 		goto err_wrid;
995 	}
996 	qp->create_type = MLX5_QP_KERNEL;
997 
998 	return 0;
999 
1000 err_wrid:
1001 	kfree(qp->sq.wqe_head);
1002 	kfree(qp->sq.w_list);
1003 	kfree(qp->sq.wrid);
1004 	kfree(qp->sq.wr_data);
1005 	kfree(qp->rq.wrid);
1006 	mlx5_db_free(dev->mdev, &qp->db);
1007 
1008 err_free:
1009 	kvfree(*in);
1010 
1011 err_buf:
1012 	mlx5_buf_free(dev->mdev, &qp->buf);
1013 	return err;
1014 }
1015 
1016 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1017 {
1018 	kfree(qp->sq.wqe_head);
1019 	kfree(qp->sq.w_list);
1020 	kfree(qp->sq.wrid);
1021 	kfree(qp->sq.wr_data);
1022 	kfree(qp->rq.wrid);
1023 	mlx5_db_free(dev->mdev, &qp->db);
1024 	mlx5_buf_free(dev->mdev, &qp->buf);
1025 }
1026 
1027 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1028 {
1029 	if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1030 	    (attr->qp_type == IB_QPT_XRC_INI))
1031 		return MLX5_SRQ_RQ;
1032 	else if (!qp->has_rq)
1033 		return MLX5_ZERO_LEN_RQ;
1034 	else
1035 		return MLX5_NON_ZERO_RQ;
1036 }
1037 
1038 static int is_connected(enum ib_qp_type qp_type)
1039 {
1040 	if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1041 		return 1;
1042 
1043 	return 0;
1044 }
1045 
1046 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1047 				    struct mlx5_ib_sq *sq, u32 tdn)
1048 {
1049 	u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1050 	void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1051 
1052 	MLX5_SET(tisc, tisc, transport_domain, tdn);
1053 	return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1054 }
1055 
1056 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1057 				      struct mlx5_ib_sq *sq)
1058 {
1059 	mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1060 }
1061 
1062 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1063 				   struct mlx5_ib_sq *sq, void *qpin,
1064 				   struct ib_pd *pd)
1065 {
1066 	struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1067 	__be64 *pas;
1068 	void *in;
1069 	void *sqc;
1070 	void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1071 	void *wq;
1072 	int inlen;
1073 	int err;
1074 	int page_shift = 0;
1075 	int npages;
1076 	int ncont = 0;
1077 	u32 offset = 0;
1078 
1079 	err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1080 			       &sq->ubuffer.umem, &npages, &page_shift,
1081 			       &ncont, &offset);
1082 	if (err)
1083 		return err;
1084 
1085 	inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1086 	in = mlx5_vzalloc(inlen);
1087 	if (!in) {
1088 		err = -ENOMEM;
1089 		goto err_umem;
1090 	}
1091 
1092 	sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1093 	MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1094 	MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1095 	MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1096 	MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1097 	MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1098 	MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1099 
1100 	wq = MLX5_ADDR_OF(sqc, sqc, wq);
1101 	MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1102 	MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1103 	MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1104 	MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1105 	MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1106 	MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1107 	MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1108 	MLX5_SET(wq, wq, page_offset, offset);
1109 
1110 	pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1111 	mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1112 
1113 	err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1114 
1115 	kvfree(in);
1116 
1117 	if (err)
1118 		goto err_umem;
1119 
1120 	return 0;
1121 
1122 err_umem:
1123 	ib_umem_release(sq->ubuffer.umem);
1124 	sq->ubuffer.umem = NULL;
1125 
1126 	return err;
1127 }
1128 
1129 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1130 				     struct mlx5_ib_sq *sq)
1131 {
1132 	mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1133 	ib_umem_release(sq->ubuffer.umem);
1134 }
1135 
1136 static int get_rq_pas_size(void *qpc)
1137 {
1138 	u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1139 	u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1140 	u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1141 	u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1142 	u32 po_quanta	  = 1 << (log_page_size - 6);
1143 	u32 rq_sz	  = 1 << (log_rq_size + 4 + log_rq_stride);
1144 	u32 page_size	  = 1 << log_page_size;
1145 	u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1146 	u32 rq_num_pas	  = (rq_sz_po + page_size - 1) / page_size;
1147 
1148 	return rq_num_pas * sizeof(u64);
1149 }
1150 
1151 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1152 				   struct mlx5_ib_rq *rq, void *qpin)
1153 {
1154 	struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1155 	__be64 *pas;
1156 	__be64 *qp_pas;
1157 	void *in;
1158 	void *rqc;
1159 	void *wq;
1160 	void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1161 	int inlen;
1162 	int err;
1163 	u32 rq_pas_size = get_rq_pas_size(qpc);
1164 
1165 	inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1166 	in = mlx5_vzalloc(inlen);
1167 	if (!in)
1168 		return -ENOMEM;
1169 
1170 	rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1171 	MLX5_SET(rqc, rqc, vlan_strip_disable, 1);
1172 	MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE);
1173 	MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1174 	MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1175 	MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1176 	MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1177 
1178 	if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1179 		MLX5_SET(rqc, rqc, scatter_fcs, 1);
1180 
1181 	wq = MLX5_ADDR_OF(rqc, rqc, wq);
1182 	MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1183 	MLX5_SET(wq, wq, end_padding_mode,
1184 		 MLX5_GET(qpc, qpc, end_padding_mode));
1185 	MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1186 	MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1187 	MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1188 	MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1189 	MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1190 	MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1191 
1192 	pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1193 	qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1194 	memcpy(pas, qp_pas, rq_pas_size);
1195 
1196 	err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1197 
1198 	kvfree(in);
1199 
1200 	return err;
1201 }
1202 
1203 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1204 				     struct mlx5_ib_rq *rq)
1205 {
1206 	mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1207 }
1208 
1209 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1210 				    struct mlx5_ib_rq *rq, u32 tdn)
1211 {
1212 	u32 *in;
1213 	void *tirc;
1214 	int inlen;
1215 	int err;
1216 
1217 	inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1218 	in = mlx5_vzalloc(inlen);
1219 	if (!in)
1220 		return -ENOMEM;
1221 
1222 	tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
1223 	MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1224 	MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1225 	MLX5_SET(tirc, tirc, transport_domain, tdn);
1226 
1227 	err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1228 
1229 	kvfree(in);
1230 
1231 	return err;
1232 }
1233 
1234 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1235 				      struct mlx5_ib_rq *rq)
1236 {
1237 	mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1238 }
1239 
1240 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1241 				u32 *in,
1242 				struct ib_pd *pd)
1243 {
1244 	struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1245 	struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1246 	struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1247 	struct ib_uobject *uobj = pd->uobject;
1248 	struct ib_ucontext *ucontext = uobj->context;
1249 	struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1250 	int err;
1251 	u32 tdn = mucontext->tdn;
1252 
1253 	if (qp->sq.wqe_cnt) {
1254 		err = create_raw_packet_qp_tis(dev, sq, tdn);
1255 		if (err)
1256 			return err;
1257 
1258 		err = create_raw_packet_qp_sq(dev, sq, in, pd);
1259 		if (err)
1260 			goto err_destroy_tis;
1261 
1262 		sq->base.container_mibqp = qp;
1263 	}
1264 
1265 	if (qp->rq.wqe_cnt) {
1266 		rq->base.container_mibqp = qp;
1267 
1268 		err = create_raw_packet_qp_rq(dev, rq, in);
1269 		if (err)
1270 			goto err_destroy_sq;
1271 
1272 
1273 		err = create_raw_packet_qp_tir(dev, rq, tdn);
1274 		if (err)
1275 			goto err_destroy_rq;
1276 	}
1277 
1278 	qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1279 						     rq->base.mqp.qpn;
1280 
1281 	return 0;
1282 
1283 err_destroy_rq:
1284 	destroy_raw_packet_qp_rq(dev, rq);
1285 err_destroy_sq:
1286 	if (!qp->sq.wqe_cnt)
1287 		return err;
1288 	destroy_raw_packet_qp_sq(dev, sq);
1289 err_destroy_tis:
1290 	destroy_raw_packet_qp_tis(dev, sq);
1291 
1292 	return err;
1293 }
1294 
1295 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1296 				  struct mlx5_ib_qp *qp)
1297 {
1298 	struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1299 	struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1300 	struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1301 
1302 	if (qp->rq.wqe_cnt) {
1303 		destroy_raw_packet_qp_tir(dev, rq);
1304 		destroy_raw_packet_qp_rq(dev, rq);
1305 	}
1306 
1307 	if (qp->sq.wqe_cnt) {
1308 		destroy_raw_packet_qp_sq(dev, sq);
1309 		destroy_raw_packet_qp_tis(dev, sq);
1310 	}
1311 }
1312 
1313 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1314 				    struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1315 {
1316 	struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1317 	struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1318 
1319 	sq->sq = &qp->sq;
1320 	rq->rq = &qp->rq;
1321 	sq->doorbell = &qp->db;
1322 	rq->doorbell = &qp->db;
1323 }
1324 
1325 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1326 {
1327 	mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1328 }
1329 
1330 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1331 				 struct ib_pd *pd,
1332 				 struct ib_qp_init_attr *init_attr,
1333 				 struct ib_udata *udata)
1334 {
1335 	struct ib_uobject *uobj = pd->uobject;
1336 	struct ib_ucontext *ucontext = uobj->context;
1337 	struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1338 	struct mlx5_ib_create_qp_resp resp = {};
1339 	int inlen;
1340 	int err;
1341 	u32 *in;
1342 	void *tirc;
1343 	void *hfso;
1344 	u32 selected_fields = 0;
1345 	size_t min_resp_len;
1346 	u32 tdn = mucontext->tdn;
1347 	struct mlx5_ib_create_qp_rss ucmd = {};
1348 	size_t required_cmd_sz;
1349 
1350 	if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1351 		return -EOPNOTSUPP;
1352 
1353 	if (init_attr->create_flags || init_attr->send_cq)
1354 		return -EINVAL;
1355 
1356 	min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1357 	if (udata->outlen < min_resp_len)
1358 		return -EINVAL;
1359 
1360 	required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1);
1361 	if (udata->inlen < required_cmd_sz) {
1362 		mlx5_ib_dbg(dev, "invalid inlen\n");
1363 		return -EINVAL;
1364 	}
1365 
1366 	if (udata->inlen > sizeof(ucmd) &&
1367 	    !ib_is_udata_cleared(udata, sizeof(ucmd),
1368 				 udata->inlen - sizeof(ucmd))) {
1369 		mlx5_ib_dbg(dev, "inlen is not supported\n");
1370 		return -EOPNOTSUPP;
1371 	}
1372 
1373 	if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1374 		mlx5_ib_dbg(dev, "copy failed\n");
1375 		return -EFAULT;
1376 	}
1377 
1378 	if (ucmd.comp_mask) {
1379 		mlx5_ib_dbg(dev, "invalid comp mask\n");
1380 		return -EOPNOTSUPP;
1381 	}
1382 
1383 	if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) {
1384 		mlx5_ib_dbg(dev, "invalid reserved\n");
1385 		return -EOPNOTSUPP;
1386 	}
1387 
1388 	err = ib_copy_to_udata(udata, &resp, min_resp_len);
1389 	if (err) {
1390 		mlx5_ib_dbg(dev, "copy failed\n");
1391 		return -EINVAL;
1392 	}
1393 
1394 	inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1395 	in = mlx5_vzalloc(inlen);
1396 	if (!in)
1397 		return -ENOMEM;
1398 
1399 	tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
1400 	MLX5_SET(tirc, tirc, disp_type,
1401 		 MLX5_TIRC_DISP_TYPE_INDIRECT);
1402 	MLX5_SET(tirc, tirc, indirect_table,
1403 		 init_attr->rwq_ind_tbl->ind_tbl_num);
1404 	MLX5_SET(tirc, tirc, transport_domain, tdn);
1405 
1406 	hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1407 	switch (ucmd.rx_hash_function) {
1408 	case MLX5_RX_HASH_FUNC_TOEPLITZ:
1409 	{
1410 		void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1411 		size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1412 
1413 		if (len != ucmd.rx_key_len) {
1414 			err = -EINVAL;
1415 			goto err;
1416 		}
1417 
1418 		MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FUNC_TOEPLITZ);
1419 		MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1420 		memcpy(rss_key, ucmd.rx_hash_key, len);
1421 		break;
1422 	}
1423 	default:
1424 		err = -EOPNOTSUPP;
1425 		goto err;
1426 	}
1427 
1428 	if (!ucmd.rx_hash_fields_mask) {
1429 		/* special case when this TIR serves as steering entry without hashing */
1430 		if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1431 			goto create_tir;
1432 		err = -EINVAL;
1433 		goto err;
1434 	}
1435 
1436 	if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1437 	     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1438 	     ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1439 	     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1440 		err = -EINVAL;
1441 		goto err;
1442 	}
1443 
1444 	/* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1445 	if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1446 	    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1447 		MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1448 			 MLX5_L3_PROT_TYPE_IPV4);
1449 	else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1450 		 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1451 		MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1452 			 MLX5_L3_PROT_TYPE_IPV6);
1453 
1454 	if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1455 	     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1456 	     ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1457 	     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1458 		err = -EINVAL;
1459 		goto err;
1460 	}
1461 
1462 	/* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1463 	if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1464 	    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1465 		MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1466 			 MLX5_L4_PROT_TYPE_TCP);
1467 	else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1468 		 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1469 		MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1470 			 MLX5_L4_PROT_TYPE_UDP);
1471 
1472 	if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1473 	    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1474 		selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1475 
1476 	if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1477 	    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1478 		selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1479 
1480 	if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1481 	    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1482 		selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1483 
1484 	if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1485 	    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1486 		selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1487 
1488 	MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1489 
1490 create_tir:
1491 	err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1492 
1493 	if (err)
1494 		goto err;
1495 
1496 	kvfree(in);
1497 	/* qpn is reserved for that QP */
1498 	qp->trans_qp.base.mqp.qpn = 0;
1499 	qp->flags |= MLX5_IB_QP_RSS;
1500 	return 0;
1501 
1502 err:
1503 	kvfree(in);
1504 	return err;
1505 }
1506 
1507 static int atomic_size_to_mode(int size_mask)
1508 {
1509 	/* driver does not support atomic_size > 256B
1510 	 * and does not know how to translate bigger sizes
1511 	 */
1512 	int supported_size_mask = size_mask & 0x1ff;
1513 	int log_max_size;
1514 
1515 	if (!supported_size_mask)
1516 		return -EOPNOTSUPP;
1517 
1518 	log_max_size = __fls(supported_size_mask);
1519 
1520 	if (log_max_size > 3)
1521 		return log_max_size;
1522 
1523 	return MLX5_ATOMIC_MODE_8B;
1524 }
1525 
1526 static int get_atomic_mode(struct mlx5_ib_dev *dev,
1527 			   enum ib_qp_type qp_type)
1528 {
1529 	u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
1530 	u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic);
1531 	int atomic_mode = -EOPNOTSUPP;
1532 	int atomic_size_mask;
1533 
1534 	if (!atomic)
1535 		return -EOPNOTSUPP;
1536 
1537 	if (qp_type == MLX5_IB_QPT_DCT)
1538 		atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
1539 	else
1540 		atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
1541 
1542 	if ((atomic_operations & MLX5_ATOMIC_OPS_MASKED_CMP_SWAP) ||
1543 	    (atomic_operations & MLX5_ATOMIC_OPS_MASKED_FETCH_ADD))
1544 		atomic_mode = atomic_size_to_mode(atomic_size_mask);
1545 
1546 	if (atomic_mode <= 0 &&
1547 	    (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP &&
1548 	     atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD))
1549 		atomic_mode = MLX5_ATOMIC_MODE_IB_COMP;
1550 
1551 	return atomic_mode;
1552 }
1553 
1554 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1555 			    struct ib_qp_init_attr *init_attr,
1556 			    struct ib_udata *udata, struct mlx5_ib_qp *qp)
1557 {
1558 	struct mlx5_ib_resources *devr = &dev->devr;
1559 	int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1560 	struct mlx5_core_dev *mdev = dev->mdev;
1561 	struct mlx5_ib_create_qp_resp resp;
1562 	struct mlx5_ib_cq *send_cq;
1563 	struct mlx5_ib_cq *recv_cq;
1564 	unsigned long flags;
1565 	u32 uidx = MLX5_IB_DEFAULT_UIDX;
1566 	struct mlx5_ib_create_qp ucmd;
1567 	struct mlx5_ib_qp_base *base;
1568 	void *qpc;
1569 	u32 *in;
1570 	int err;
1571 
1572 	base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1573 	       &qp->raw_packet_qp.rq.base :
1574 	       &qp->trans_qp.base;
1575 
1576 	if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1577 		mlx5_ib_odp_create_qp(qp);
1578 
1579 	mutex_init(&qp->mutex);
1580 	spin_lock_init(&qp->sq.lock);
1581 	spin_lock_init(&qp->rq.lock);
1582 
1583 	if (init_attr->rwq_ind_tbl) {
1584 		if (!udata)
1585 			return -ENOSYS;
1586 
1587 		err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1588 		return err;
1589 	}
1590 
1591 	if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1592 		if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1593 			mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1594 			return -EINVAL;
1595 		} else {
1596 			qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1597 		}
1598 	}
1599 
1600 	if (init_attr->create_flags &
1601 			(IB_QP_CREATE_CROSS_CHANNEL |
1602 			 IB_QP_CREATE_MANAGED_SEND |
1603 			 IB_QP_CREATE_MANAGED_RECV)) {
1604 		if (!MLX5_CAP_GEN(mdev, cd)) {
1605 			mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1606 			return -EINVAL;
1607 		}
1608 		if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1609 			qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1610 		if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1611 			qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1612 		if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1613 			qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1614 	}
1615 
1616 	if (init_attr->qp_type == IB_QPT_UD &&
1617 	    (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1618 		if (!MLX5_CAP_GEN(mdev, ipoib_ipoib_offloads)) {
1619 			mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1620 			return -EOPNOTSUPP;
1621 		}
1622 
1623 	if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1624 		if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1625 			mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1626 			return -EOPNOTSUPP;
1627 		}
1628 		if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1629 		    !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1630 			mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1631 			return -EOPNOTSUPP;
1632 		}
1633 		qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1634 	}
1635 
1636 	if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1637 		qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1638 
1639 	if (pd && pd->uobject) {
1640 		if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1641 			mlx5_ib_dbg(dev, "copy failed\n");
1642 			return -EFAULT;
1643 		}
1644 
1645 		err = get_qp_user_index(to_mucontext(pd->uobject->context),
1646 					&ucmd, udata->inlen, &uidx);
1647 		if (err)
1648 			return err;
1649 
1650 		qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1651 		qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1652 	} else {
1653 		qp->wq_sig = !!wq_signature;
1654 	}
1655 
1656 	qp->has_rq = qp_has_rq(init_attr);
1657 	err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1658 			  qp, (pd && pd->uobject) ? &ucmd : NULL);
1659 	if (err) {
1660 		mlx5_ib_dbg(dev, "err %d\n", err);
1661 		return err;
1662 	}
1663 
1664 	if (pd) {
1665 		if (pd->uobject) {
1666 			__u32 max_wqes =
1667 				1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1668 			mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1669 			if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1670 			    ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1671 				mlx5_ib_dbg(dev, "invalid rq params\n");
1672 				return -EINVAL;
1673 			}
1674 			if (ucmd.sq_wqe_count > max_wqes) {
1675 				mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1676 					    ucmd.sq_wqe_count, max_wqes);
1677 				return -EINVAL;
1678 			}
1679 			if (init_attr->create_flags &
1680 			    MLX5_IB_QP_CREATE_SQPN_QP1) {
1681 				mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1682 				return -EINVAL;
1683 			}
1684 			err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1685 					     &resp, &inlen, base);
1686 			if (err)
1687 				mlx5_ib_dbg(dev, "err %d\n", err);
1688 		} else {
1689 			err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1690 					       base);
1691 			if (err)
1692 				mlx5_ib_dbg(dev, "err %d\n", err);
1693 		}
1694 
1695 		if (err)
1696 			return err;
1697 	} else {
1698 		in = mlx5_vzalloc(inlen);
1699 		if (!in)
1700 			return -ENOMEM;
1701 
1702 		qp->create_type = MLX5_QP_EMPTY;
1703 	}
1704 
1705 	if (is_sqp(init_attr->qp_type))
1706 		qp->port = init_attr->port_num;
1707 
1708 	qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1709 
1710 	MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type));
1711 	MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1712 
1713 	if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1714 		MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1715 	else
1716 		MLX5_SET(qpc, qpc, latency_sensitive, 1);
1717 
1718 
1719 	if (qp->wq_sig)
1720 		MLX5_SET(qpc, qpc, wq_signature, 1);
1721 
1722 	if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1723 		MLX5_SET(qpc, qpc, block_lb_mc, 1);
1724 
1725 	if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1726 		MLX5_SET(qpc, qpc, cd_master, 1);
1727 	if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1728 		MLX5_SET(qpc, qpc, cd_slave_send, 1);
1729 	if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1730 		MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1731 
1732 	if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1733 		int rcqe_sz;
1734 		int scqe_sz;
1735 
1736 		rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1737 		scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1738 
1739 		if (rcqe_sz == 128)
1740 			MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1741 		else
1742 			MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1743 
1744 		if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1745 			if (scqe_sz == 128)
1746 				MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1747 			else
1748 				MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1749 		}
1750 	}
1751 
1752 	if (qp->rq.wqe_cnt) {
1753 		MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1754 		MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1755 	}
1756 
1757 	MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1758 
1759 	if (qp->sq.wqe_cnt)
1760 		MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1761 	else
1762 		MLX5_SET(qpc, qpc, no_sq, 1);
1763 
1764 	/* Set default resources */
1765 	switch (init_attr->qp_type) {
1766 	case IB_QPT_XRC_TGT:
1767 		MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1768 		MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1769 		MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s0)->msrq.srqn);
1770 		MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1771 		break;
1772 	case IB_QPT_XRC_INI:
1773 		MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1774 		MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1775 		MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s0)->msrq.srqn);
1776 		break;
1777 	default:
1778 		if (init_attr->srq) {
1779 			MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1780 			MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(init_attr->srq)->msrq.srqn);
1781 		} else {
1782 			MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1783 			MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s1)->msrq.srqn);
1784 		}
1785 	}
1786 
1787 	if (init_attr->send_cq)
1788 		MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1789 
1790 	if (init_attr->recv_cq)
1791 		MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1792 
1793 	MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1794 
1795 	/* 0xffffff means we ask to work with cqe version 0 */
1796 	if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1797 		MLX5_SET(qpc, qpc, user_index, uidx);
1798 
1799 	/* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1800 	if (init_attr->qp_type == IB_QPT_UD &&
1801 	    (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1802 		MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1803 		qp->flags |= MLX5_IB_QP_LSO;
1804 	}
1805 
1806 	if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1807 		qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1808 		raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1809 		err = create_raw_packet_qp(dev, qp, in, pd);
1810 	} else {
1811 		err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1812 	}
1813 
1814 	if (err) {
1815 		mlx5_ib_dbg(dev, "create qp failed\n");
1816 		goto err_create;
1817 	}
1818 
1819 	kvfree(in);
1820 
1821 	base->container_mibqp = qp;
1822 	base->mqp.event = mlx5_ib_qp_event;
1823 
1824 	get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1825 		&send_cq, &recv_cq);
1826 	spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1827 	mlx5_ib_lock_cqs(send_cq, recv_cq);
1828 	/* Maintain device to QPs access, needed for further handling via reset
1829 	 * flow
1830 	 */
1831 	list_add_tail(&qp->qps_list, &dev->qp_list);
1832 	/* Maintain CQ to QPs access, needed for further handling via reset flow
1833 	 */
1834 	if (send_cq)
1835 		list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1836 	if (recv_cq)
1837 		list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1838 	mlx5_ib_unlock_cqs(send_cq, recv_cq);
1839 	spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1840 
1841 	return 0;
1842 
1843 err_create:
1844 	if (qp->create_type == MLX5_QP_USER)
1845 		destroy_qp_user(dev, pd, qp, base);
1846 	else if (qp->create_type == MLX5_QP_KERNEL)
1847 		destroy_qp_kernel(dev, qp);
1848 
1849 	kvfree(in);
1850 	return err;
1851 }
1852 
1853 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1854 	__acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1855 {
1856 	if (send_cq) {
1857 		if (recv_cq) {
1858 			if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1859 				spin_lock(&send_cq->lock);
1860 				spin_lock_nested(&recv_cq->lock,
1861 						 SINGLE_DEPTH_NESTING);
1862 			} else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1863 				spin_lock(&send_cq->lock);
1864 				__acquire(&recv_cq->lock);
1865 			} else {
1866 				spin_lock(&recv_cq->lock);
1867 				spin_lock_nested(&send_cq->lock,
1868 						 SINGLE_DEPTH_NESTING);
1869 			}
1870 		} else {
1871 			spin_lock(&send_cq->lock);
1872 			__acquire(&recv_cq->lock);
1873 		}
1874 	} else if (recv_cq) {
1875 		spin_lock(&recv_cq->lock);
1876 		__acquire(&send_cq->lock);
1877 	} else {
1878 		__acquire(&send_cq->lock);
1879 		__acquire(&recv_cq->lock);
1880 	}
1881 }
1882 
1883 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1884 	__releases(&send_cq->lock) __releases(&recv_cq->lock)
1885 {
1886 	if (send_cq) {
1887 		if (recv_cq) {
1888 			if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1889 				spin_unlock(&recv_cq->lock);
1890 				spin_unlock(&send_cq->lock);
1891 			} else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1892 				__release(&recv_cq->lock);
1893 				spin_unlock(&send_cq->lock);
1894 			} else {
1895 				spin_unlock(&send_cq->lock);
1896 				spin_unlock(&recv_cq->lock);
1897 			}
1898 		} else {
1899 			__release(&recv_cq->lock);
1900 			spin_unlock(&send_cq->lock);
1901 		}
1902 	} else if (recv_cq) {
1903 		__release(&send_cq->lock);
1904 		spin_unlock(&recv_cq->lock);
1905 	} else {
1906 		__release(&recv_cq->lock);
1907 		__release(&send_cq->lock);
1908 	}
1909 }
1910 
1911 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1912 {
1913 	return to_mpd(qp->ibqp.pd);
1914 }
1915 
1916 static void get_cqs(enum ib_qp_type qp_type,
1917 		    struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
1918 		    struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1919 {
1920 	switch (qp_type) {
1921 	case IB_QPT_XRC_TGT:
1922 		*send_cq = NULL;
1923 		*recv_cq = NULL;
1924 		break;
1925 	case MLX5_IB_QPT_REG_UMR:
1926 	case IB_QPT_XRC_INI:
1927 		*send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1928 		*recv_cq = NULL;
1929 		break;
1930 
1931 	case IB_QPT_SMI:
1932 	case MLX5_IB_QPT_HW_GSI:
1933 	case IB_QPT_RC:
1934 	case IB_QPT_UC:
1935 	case IB_QPT_UD:
1936 	case IB_QPT_RAW_IPV6:
1937 	case IB_QPT_RAW_ETHERTYPE:
1938 	case IB_QPT_RAW_PACKET:
1939 		*send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1940 		*recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
1941 		break;
1942 
1943 	case IB_QPT_MAX:
1944 	default:
1945 		*send_cq = NULL;
1946 		*recv_cq = NULL;
1947 		break;
1948 	}
1949 }
1950 
1951 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1952 				const struct mlx5_modify_raw_qp_param *raw_qp_param,
1953 				u8 lag_tx_affinity);
1954 
1955 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1956 {
1957 	struct mlx5_ib_cq *send_cq, *recv_cq;
1958 	struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
1959 	unsigned long flags;
1960 	int err;
1961 
1962 	if (qp->ibqp.rwq_ind_tbl) {
1963 		destroy_rss_raw_qp_tir(dev, qp);
1964 		return;
1965 	}
1966 
1967 	base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1968 	       &qp->raw_packet_qp.rq.base :
1969 	       &qp->trans_qp.base;
1970 
1971 	if (qp->state != IB_QPS_RESET) {
1972 		if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
1973 			mlx5_ib_qp_disable_pagefaults(qp);
1974 			err = mlx5_core_qp_modify(dev->mdev,
1975 						  MLX5_CMD_OP_2RST_QP, 0,
1976 						  NULL, &base->mqp);
1977 		} else {
1978 			struct mlx5_modify_raw_qp_param raw_qp_param = {
1979 				.operation = MLX5_CMD_OP_2RST_QP
1980 			};
1981 
1982 			err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
1983 		}
1984 		if (err)
1985 			mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
1986 				     base->mqp.qpn);
1987 	}
1988 
1989 	get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
1990 		&send_cq, &recv_cq);
1991 
1992 	spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1993 	mlx5_ib_lock_cqs(send_cq, recv_cq);
1994 	/* del from lists under both locks above to protect reset flow paths */
1995 	list_del(&qp->qps_list);
1996 	if (send_cq)
1997 		list_del(&qp->cq_send_list);
1998 
1999 	if (recv_cq)
2000 		list_del(&qp->cq_recv_list);
2001 
2002 	if (qp->create_type == MLX5_QP_KERNEL) {
2003 		__mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2004 				   qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2005 		if (send_cq != recv_cq)
2006 			__mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2007 					   NULL);
2008 	}
2009 	mlx5_ib_unlock_cqs(send_cq, recv_cq);
2010 	spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2011 
2012 	if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
2013 		destroy_raw_packet_qp(dev, qp);
2014 	} else {
2015 		err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2016 		if (err)
2017 			mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2018 				     base->mqp.qpn);
2019 	}
2020 
2021 	if (qp->create_type == MLX5_QP_KERNEL)
2022 		destroy_qp_kernel(dev, qp);
2023 	else if (qp->create_type == MLX5_QP_USER)
2024 		destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
2025 }
2026 
2027 static const char *ib_qp_type_str(enum ib_qp_type type)
2028 {
2029 	switch (type) {
2030 	case IB_QPT_SMI:
2031 		return "IB_QPT_SMI";
2032 	case IB_QPT_GSI:
2033 		return "IB_QPT_GSI";
2034 	case IB_QPT_RC:
2035 		return "IB_QPT_RC";
2036 	case IB_QPT_UC:
2037 		return "IB_QPT_UC";
2038 	case IB_QPT_UD:
2039 		return "IB_QPT_UD";
2040 	case IB_QPT_RAW_IPV6:
2041 		return "IB_QPT_RAW_IPV6";
2042 	case IB_QPT_RAW_ETHERTYPE:
2043 		return "IB_QPT_RAW_ETHERTYPE";
2044 	case IB_QPT_XRC_INI:
2045 		return "IB_QPT_XRC_INI";
2046 	case IB_QPT_XRC_TGT:
2047 		return "IB_QPT_XRC_TGT";
2048 	case IB_QPT_RAW_PACKET:
2049 		return "IB_QPT_RAW_PACKET";
2050 	case MLX5_IB_QPT_REG_UMR:
2051 		return "MLX5_IB_QPT_REG_UMR";
2052 	case IB_QPT_MAX:
2053 	default:
2054 		return "Invalid QP type";
2055 	}
2056 }
2057 
2058 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2059 				struct ib_qp_init_attr *init_attr,
2060 				struct ib_udata *udata)
2061 {
2062 	struct mlx5_ib_dev *dev;
2063 	struct mlx5_ib_qp *qp;
2064 	u16 xrcdn = 0;
2065 	int err;
2066 
2067 	if (pd) {
2068 		dev = to_mdev(pd->device);
2069 
2070 		if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2071 			if (!pd->uobject) {
2072 				mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2073 				return ERR_PTR(-EINVAL);
2074 			} else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2075 				mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2076 				return ERR_PTR(-EINVAL);
2077 			}
2078 		}
2079 	} else {
2080 		/* being cautious here */
2081 		if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2082 		    init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2083 			pr_warn("%s: no PD for transport %s\n", __func__,
2084 				ib_qp_type_str(init_attr->qp_type));
2085 			return ERR_PTR(-EINVAL);
2086 		}
2087 		dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2088 	}
2089 
2090 	switch (init_attr->qp_type) {
2091 	case IB_QPT_XRC_TGT:
2092 	case IB_QPT_XRC_INI:
2093 		if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2094 			mlx5_ib_dbg(dev, "XRC not supported\n");
2095 			return ERR_PTR(-ENOSYS);
2096 		}
2097 		init_attr->recv_cq = NULL;
2098 		if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2099 			xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2100 			init_attr->send_cq = NULL;
2101 		}
2102 
2103 		/* fall through */
2104 	case IB_QPT_RAW_PACKET:
2105 	case IB_QPT_RC:
2106 	case IB_QPT_UC:
2107 	case IB_QPT_UD:
2108 	case IB_QPT_SMI:
2109 	case MLX5_IB_QPT_HW_GSI:
2110 	case MLX5_IB_QPT_REG_UMR:
2111 		qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2112 		if (!qp)
2113 			return ERR_PTR(-ENOMEM);
2114 
2115 		err = create_qp_common(dev, pd, init_attr, udata, qp);
2116 		if (err) {
2117 			mlx5_ib_dbg(dev, "create_qp_common failed\n");
2118 			kfree(qp);
2119 			return ERR_PTR(err);
2120 		}
2121 
2122 		if (is_qp0(init_attr->qp_type))
2123 			qp->ibqp.qp_num = 0;
2124 		else if (is_qp1(init_attr->qp_type))
2125 			qp->ibqp.qp_num = 1;
2126 		else
2127 			qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2128 
2129 		mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2130 			    qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2131 			    init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2132 			    init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2133 
2134 		qp->trans_qp.xrcdn = xrcdn;
2135 
2136 		break;
2137 
2138 	case IB_QPT_GSI:
2139 		return mlx5_ib_gsi_create_qp(pd, init_attr);
2140 
2141 	case IB_QPT_RAW_IPV6:
2142 	case IB_QPT_RAW_ETHERTYPE:
2143 	case IB_QPT_MAX:
2144 	default:
2145 		mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2146 			    init_attr->qp_type);
2147 		/* Don't support raw QPs */
2148 		return ERR_PTR(-EINVAL);
2149 	}
2150 
2151 	return &qp->ibqp;
2152 }
2153 
2154 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2155 {
2156 	struct mlx5_ib_dev *dev = to_mdev(qp->device);
2157 	struct mlx5_ib_qp *mqp = to_mqp(qp);
2158 
2159 	if (unlikely(qp->qp_type == IB_QPT_GSI))
2160 		return mlx5_ib_gsi_destroy_qp(qp);
2161 
2162 	destroy_qp_common(dev, mqp);
2163 
2164 	kfree(mqp);
2165 
2166 	return 0;
2167 }
2168 
2169 static int to_mlx5_access_flags(struct mlx5_ib_qp *qp,
2170 				const struct ib_qp_attr *attr,
2171 				int attr_mask, __be32 *hw_access_flags_be)
2172 {
2173 	u8 dest_rd_atomic;
2174 	u32 access_flags, hw_access_flags = 0;
2175 
2176 	struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
2177 
2178 	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2179 		dest_rd_atomic = attr->max_dest_rd_atomic;
2180 	else
2181 		dest_rd_atomic = qp->trans_qp.resp_depth;
2182 
2183 	if (attr_mask & IB_QP_ACCESS_FLAGS)
2184 		access_flags = attr->qp_access_flags;
2185 	else
2186 		access_flags = qp->trans_qp.atomic_rd_en;
2187 
2188 	if (!dest_rd_atomic)
2189 		access_flags &= IB_ACCESS_REMOTE_WRITE;
2190 
2191 	if (access_flags & IB_ACCESS_REMOTE_READ)
2192 		hw_access_flags |= MLX5_QP_BIT_RRE;
2193 	if (access_flags & IB_ACCESS_REMOTE_ATOMIC) {
2194 		int atomic_mode;
2195 
2196 		atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type);
2197 		if (atomic_mode < 0)
2198 			return -EOPNOTSUPP;
2199 
2200 		hw_access_flags |= MLX5_QP_BIT_RAE;
2201 		hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFF;
2202 	}
2203 
2204 	if (access_flags & IB_ACCESS_REMOTE_WRITE)
2205 		hw_access_flags |= MLX5_QP_BIT_RWE;
2206 
2207 	*hw_access_flags_be = cpu_to_be32(hw_access_flags);
2208 
2209 	return 0;
2210 }
2211 
2212 enum {
2213 	MLX5_PATH_FLAG_FL	= 1 << 0,
2214 	MLX5_PATH_FLAG_FREE_AR	= 1 << 1,
2215 	MLX5_PATH_FLAG_COUNTER	= 1 << 2,
2216 };
2217 
2218 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2219 {
2220 	if (rate == IB_RATE_PORT_CURRENT) {
2221 		return 0;
2222 	} else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS) {
2223 		return -EINVAL;
2224 	} else {
2225 		while (rate != IB_RATE_2_5_GBPS &&
2226 		       !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2227 			 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2228 			--rate;
2229 	}
2230 
2231 	return rate + MLX5_STAT_RATE_OFFSET;
2232 }
2233 
2234 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2235 				      struct mlx5_ib_sq *sq, u8 sl)
2236 {
2237 	void *in;
2238 	void *tisc;
2239 	int inlen;
2240 	int err;
2241 
2242 	inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2243 	in = mlx5_vzalloc(inlen);
2244 	if (!in)
2245 		return -ENOMEM;
2246 
2247 	MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2248 
2249 	tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2250 	MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2251 
2252 	err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2253 
2254 	kvfree(in);
2255 
2256 	return err;
2257 }
2258 
2259 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2260 					 struct mlx5_ib_sq *sq, u8 tx_affinity)
2261 {
2262 	void *in;
2263 	void *tisc;
2264 	int inlen;
2265 	int err;
2266 
2267 	inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2268 	in = mlx5_vzalloc(inlen);
2269 	if (!in)
2270 		return -ENOMEM;
2271 
2272 	MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2273 
2274 	tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2275 	MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2276 
2277 	err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2278 
2279 	kvfree(in);
2280 
2281 	return err;
2282 }
2283 
2284 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2285 			 const struct ib_ah_attr *ah,
2286 			 struct mlx5_qp_path *path, u8 port, int attr_mask,
2287 			 u32 path_flags, const struct ib_qp_attr *attr,
2288 			 bool alt)
2289 {
2290 	enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2291 	int err;
2292 	enum ib_gid_type gid_type;
2293 
2294 	if (attr_mask & IB_QP_PKEY_INDEX)
2295 		path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2296 						     attr->pkey_index);
2297 
2298 	if (ah->ah_flags & IB_AH_GRH) {
2299 		if (ah->grh.sgid_index >=
2300 		    dev->mdev->port_caps[port - 1].gid_table_len) {
2301 			pr_err("sgid_index (%u) too large. max is %d\n",
2302 			       ah->grh.sgid_index,
2303 			       dev->mdev->port_caps[port - 1].gid_table_len);
2304 			return -EINVAL;
2305 		}
2306 	}
2307 
2308 	if (ll == IB_LINK_LAYER_ETHERNET) {
2309 		if (!(ah->ah_flags & IB_AH_GRH))
2310 			return -EINVAL;
2311 		err = mlx5_get_roce_gid_type(dev, port, ah->grh.sgid_index,
2312 					     &gid_type);
2313 		if (err)
2314 			return err;
2315 		memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));
2316 		path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2317 							  ah->grh.sgid_index);
2318 		path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;
2319 		if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2320 			path->ecn_dscp = (ah->grh.traffic_class >> 2) & 0x3f;
2321 	} else {
2322 		path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2323 		path->fl_free_ar |=
2324 			(path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2325 		path->rlid = cpu_to_be16(ah->dlid);
2326 		path->grh_mlid = ah->src_path_bits & 0x7f;
2327 		if (ah->ah_flags & IB_AH_GRH)
2328 			path->grh_mlid	|= 1 << 7;
2329 		path->dci_cfi_prio_sl = ah->sl & 0xf;
2330 	}
2331 
2332 	if (ah->ah_flags & IB_AH_GRH) {
2333 		path->mgid_index = ah->grh.sgid_index;
2334 		path->hop_limit  = ah->grh.hop_limit;
2335 		path->tclass_flowlabel =
2336 			cpu_to_be32((ah->grh.traffic_class << 20) |
2337 				    (ah->grh.flow_label));
2338 		memcpy(path->rgid, ah->grh.dgid.raw, 16);
2339 	}
2340 
2341 	err = ib_rate_to_mlx5(dev, ah->static_rate);
2342 	if (err < 0)
2343 		return err;
2344 	path->static_rate = err;
2345 	path->port = port;
2346 
2347 	if (attr_mask & IB_QP_TIMEOUT)
2348 		path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2349 
2350 	if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2351 		return modify_raw_packet_eth_prio(dev->mdev,
2352 						  &qp->raw_packet_qp.sq,
2353 						  ah->sl & 0xf);
2354 
2355 	return 0;
2356 }
2357 
2358 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2359 	[MLX5_QP_STATE_INIT] = {
2360 		[MLX5_QP_STATE_INIT] = {
2361 			[MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE		|
2362 					  MLX5_QP_OPTPAR_RAE		|
2363 					  MLX5_QP_OPTPAR_RWE		|
2364 					  MLX5_QP_OPTPAR_PKEY_INDEX	|
2365 					  MLX5_QP_OPTPAR_PRI_PORT,
2366 			[MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE		|
2367 					  MLX5_QP_OPTPAR_PKEY_INDEX	|
2368 					  MLX5_QP_OPTPAR_PRI_PORT,
2369 			[MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX	|
2370 					  MLX5_QP_OPTPAR_Q_KEY		|
2371 					  MLX5_QP_OPTPAR_PRI_PORT,
2372 		},
2373 		[MLX5_QP_STATE_RTR] = {
2374 			[MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2375 					  MLX5_QP_OPTPAR_RRE            |
2376 					  MLX5_QP_OPTPAR_RAE            |
2377 					  MLX5_QP_OPTPAR_RWE            |
2378 					  MLX5_QP_OPTPAR_PKEY_INDEX,
2379 			[MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2380 					  MLX5_QP_OPTPAR_RWE            |
2381 					  MLX5_QP_OPTPAR_PKEY_INDEX,
2382 			[MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2383 					  MLX5_QP_OPTPAR_Q_KEY,
2384 			[MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX	|
2385 					   MLX5_QP_OPTPAR_Q_KEY,
2386 			[MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2387 					  MLX5_QP_OPTPAR_RRE            |
2388 					  MLX5_QP_OPTPAR_RAE            |
2389 					  MLX5_QP_OPTPAR_RWE            |
2390 					  MLX5_QP_OPTPAR_PKEY_INDEX,
2391 		},
2392 	},
2393 	[MLX5_QP_STATE_RTR] = {
2394 		[MLX5_QP_STATE_RTS] = {
2395 			[MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH	|
2396 					  MLX5_QP_OPTPAR_RRE		|
2397 					  MLX5_QP_OPTPAR_RAE		|
2398 					  MLX5_QP_OPTPAR_RWE		|
2399 					  MLX5_QP_OPTPAR_PM_STATE	|
2400 					  MLX5_QP_OPTPAR_RNR_TIMEOUT,
2401 			[MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH	|
2402 					  MLX5_QP_OPTPAR_RWE		|
2403 					  MLX5_QP_OPTPAR_PM_STATE,
2404 			[MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2405 		},
2406 	},
2407 	[MLX5_QP_STATE_RTS] = {
2408 		[MLX5_QP_STATE_RTS] = {
2409 			[MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE		|
2410 					  MLX5_QP_OPTPAR_RAE		|
2411 					  MLX5_QP_OPTPAR_RWE		|
2412 					  MLX5_QP_OPTPAR_RNR_TIMEOUT	|
2413 					  MLX5_QP_OPTPAR_PM_STATE	|
2414 					  MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2415 			[MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE		|
2416 					  MLX5_QP_OPTPAR_PM_STATE	|
2417 					  MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2418 			[MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY		|
2419 					  MLX5_QP_OPTPAR_SRQN		|
2420 					  MLX5_QP_OPTPAR_CQN_RCV,
2421 		},
2422 	},
2423 	[MLX5_QP_STATE_SQER] = {
2424 		[MLX5_QP_STATE_RTS] = {
2425 			[MLX5_QP_ST_UD]	 = MLX5_QP_OPTPAR_Q_KEY,
2426 			[MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2427 			[MLX5_QP_ST_UC]	 = MLX5_QP_OPTPAR_RWE,
2428 			[MLX5_QP_ST_RC]	 = MLX5_QP_OPTPAR_RNR_TIMEOUT	|
2429 					   MLX5_QP_OPTPAR_RWE		|
2430 					   MLX5_QP_OPTPAR_RAE		|
2431 					   MLX5_QP_OPTPAR_RRE,
2432 		},
2433 	},
2434 };
2435 
2436 static int ib_nr_to_mlx5_nr(int ib_mask)
2437 {
2438 	switch (ib_mask) {
2439 	case IB_QP_STATE:
2440 		return 0;
2441 	case IB_QP_CUR_STATE:
2442 		return 0;
2443 	case IB_QP_EN_SQD_ASYNC_NOTIFY:
2444 		return 0;
2445 	case IB_QP_ACCESS_FLAGS:
2446 		return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2447 			MLX5_QP_OPTPAR_RAE;
2448 	case IB_QP_PKEY_INDEX:
2449 		return MLX5_QP_OPTPAR_PKEY_INDEX;
2450 	case IB_QP_PORT:
2451 		return MLX5_QP_OPTPAR_PRI_PORT;
2452 	case IB_QP_QKEY:
2453 		return MLX5_QP_OPTPAR_Q_KEY;
2454 	case IB_QP_AV:
2455 		return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2456 			MLX5_QP_OPTPAR_PRI_PORT;
2457 	case IB_QP_PATH_MTU:
2458 		return 0;
2459 	case IB_QP_TIMEOUT:
2460 		return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2461 	case IB_QP_RETRY_CNT:
2462 		return MLX5_QP_OPTPAR_RETRY_COUNT;
2463 	case IB_QP_RNR_RETRY:
2464 		return MLX5_QP_OPTPAR_RNR_RETRY;
2465 	case IB_QP_RQ_PSN:
2466 		return 0;
2467 	case IB_QP_MAX_QP_RD_ATOMIC:
2468 		return MLX5_QP_OPTPAR_SRA_MAX;
2469 	case IB_QP_ALT_PATH:
2470 		return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2471 	case IB_QP_MIN_RNR_TIMER:
2472 		return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2473 	case IB_QP_SQ_PSN:
2474 		return 0;
2475 	case IB_QP_MAX_DEST_RD_ATOMIC:
2476 		return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2477 			MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2478 	case IB_QP_PATH_MIG_STATE:
2479 		return MLX5_QP_OPTPAR_PM_STATE;
2480 	case IB_QP_CAP:
2481 		return 0;
2482 	case IB_QP_DEST_QPN:
2483 		return 0;
2484 	}
2485 	return 0;
2486 }
2487 
2488 static int ib_mask_to_mlx5_opt(int ib_mask)
2489 {
2490 	int result = 0;
2491 	int i;
2492 
2493 	for (i = 0; i < 8 * sizeof(int); i++) {
2494 		if ((1 << i) & ib_mask)
2495 			result |= ib_nr_to_mlx5_nr(1 << i);
2496 	}
2497 
2498 	return result;
2499 }
2500 
2501 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2502 				   struct mlx5_ib_rq *rq, int new_state,
2503 				   const struct mlx5_modify_raw_qp_param *raw_qp_param)
2504 {
2505 	void *in;
2506 	void *rqc;
2507 	int inlen;
2508 	int err;
2509 
2510 	inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2511 	in = mlx5_vzalloc(inlen);
2512 	if (!in)
2513 		return -ENOMEM;
2514 
2515 	MLX5_SET(modify_rq_in, in, rqn, rq->base.mqp.qpn);
2516 	MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2517 
2518 	rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2519 	MLX5_SET(rqc, rqc, state, new_state);
2520 
2521 	if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2522 		if (MLX5_CAP_GEN(dev->mdev, modify_rq_counters_set_id)) {
2523 			MLX5_SET64(modify_rq_in, in, modify_bitmask,
2524 				   MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID);
2525 			MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2526 		} else
2527 			pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2528 				     dev->ib_dev.name);
2529 	}
2530 
2531 	err = mlx5_core_modify_rq(dev->mdev, in, inlen);
2532 	if (err)
2533 		goto out;
2534 
2535 	rq->state = new_state;
2536 
2537 out:
2538 	kvfree(in);
2539 	return err;
2540 }
2541 
2542 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2543 				   struct mlx5_ib_sq *sq, int new_state)
2544 {
2545 	void *in;
2546 	void *sqc;
2547 	int inlen;
2548 	int err;
2549 
2550 	inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2551 	in = mlx5_vzalloc(inlen);
2552 	if (!in)
2553 		return -ENOMEM;
2554 
2555 	MLX5_SET(modify_sq_in, in, sqn, sq->base.mqp.qpn);
2556 	MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2557 
2558 	sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2559 	MLX5_SET(sqc, sqc, state, new_state);
2560 
2561 	err = mlx5_core_modify_sq(dev, in, inlen);
2562 	if (err)
2563 		goto out;
2564 
2565 	sq->state = new_state;
2566 
2567 out:
2568 	kvfree(in);
2569 	return err;
2570 }
2571 
2572 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2573 				const struct mlx5_modify_raw_qp_param *raw_qp_param,
2574 				u8 tx_affinity)
2575 {
2576 	struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2577 	struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2578 	struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2579 	int rq_state;
2580 	int sq_state;
2581 	int err;
2582 
2583 	switch (raw_qp_param->operation) {
2584 	case MLX5_CMD_OP_RST2INIT_QP:
2585 		rq_state = MLX5_RQC_STATE_RDY;
2586 		sq_state = MLX5_SQC_STATE_RDY;
2587 		break;
2588 	case MLX5_CMD_OP_2ERR_QP:
2589 		rq_state = MLX5_RQC_STATE_ERR;
2590 		sq_state = MLX5_SQC_STATE_ERR;
2591 		break;
2592 	case MLX5_CMD_OP_2RST_QP:
2593 		rq_state = MLX5_RQC_STATE_RST;
2594 		sq_state = MLX5_SQC_STATE_RST;
2595 		break;
2596 	case MLX5_CMD_OP_INIT2INIT_QP:
2597 	case MLX5_CMD_OP_INIT2RTR_QP:
2598 	case MLX5_CMD_OP_RTR2RTS_QP:
2599 	case MLX5_CMD_OP_RTS2RTS_QP:
2600 		if (raw_qp_param->set_mask)
2601 			return -EINVAL;
2602 		else
2603 			return 0;
2604 	default:
2605 		WARN_ON(1);
2606 		return -EINVAL;
2607 	}
2608 
2609 	if (qp->rq.wqe_cnt) {
2610 		err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
2611 		if (err)
2612 			return err;
2613 	}
2614 
2615 	if (qp->sq.wqe_cnt) {
2616 		if (tx_affinity) {
2617 			err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2618 							    tx_affinity);
2619 			if (err)
2620 				return err;
2621 		}
2622 
2623 		return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state);
2624 	}
2625 
2626 	return 0;
2627 }
2628 
2629 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2630 			       const struct ib_qp_attr *attr, int attr_mask,
2631 			       enum ib_qp_state cur_state, enum ib_qp_state new_state)
2632 {
2633 	static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2634 		[MLX5_QP_STATE_RST] = {
2635 			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
2636 			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
2637 			[MLX5_QP_STATE_INIT]	= MLX5_CMD_OP_RST2INIT_QP,
2638 		},
2639 		[MLX5_QP_STATE_INIT]  = {
2640 			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
2641 			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
2642 			[MLX5_QP_STATE_INIT]	= MLX5_CMD_OP_INIT2INIT_QP,
2643 			[MLX5_QP_STATE_RTR]	= MLX5_CMD_OP_INIT2RTR_QP,
2644 		},
2645 		[MLX5_QP_STATE_RTR]   = {
2646 			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
2647 			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
2648 			[MLX5_QP_STATE_RTS]	= MLX5_CMD_OP_RTR2RTS_QP,
2649 		},
2650 		[MLX5_QP_STATE_RTS]   = {
2651 			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
2652 			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
2653 			[MLX5_QP_STATE_RTS]	= MLX5_CMD_OP_RTS2RTS_QP,
2654 		},
2655 		[MLX5_QP_STATE_SQD] = {
2656 			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
2657 			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
2658 		},
2659 		[MLX5_QP_STATE_SQER] = {
2660 			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
2661 			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
2662 			[MLX5_QP_STATE_RTS]	= MLX5_CMD_OP_SQERR2RTS_QP,
2663 		},
2664 		[MLX5_QP_STATE_ERR] = {
2665 			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
2666 			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
2667 		}
2668 	};
2669 
2670 	struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2671 	struct mlx5_ib_qp *qp = to_mqp(ibqp);
2672 	struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2673 	struct mlx5_ib_cq *send_cq, *recv_cq;
2674 	struct mlx5_qp_context *context;
2675 	struct mlx5_ib_pd *pd;
2676 	struct mlx5_ib_port *mibport = NULL;
2677 	enum mlx5_qp_state mlx5_cur, mlx5_new;
2678 	enum mlx5_qp_optpar optpar;
2679 	int sqd_event;
2680 	int mlx5_st;
2681 	int err;
2682 	u16 op;
2683 
2684 	context = kzalloc(sizeof(*context), GFP_KERNEL);
2685 	if (!context)
2686 		return -ENOMEM;
2687 
2688 	err = to_mlx5_st(ibqp->qp_type);
2689 	if (err < 0) {
2690 		mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
2691 		goto out;
2692 	}
2693 
2694 	context->flags = cpu_to_be32(err << 16);
2695 
2696 	if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2697 		context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2698 	} else {
2699 		switch (attr->path_mig_state) {
2700 		case IB_MIG_MIGRATED:
2701 			context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2702 			break;
2703 		case IB_MIG_REARM:
2704 			context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2705 			break;
2706 		case IB_MIG_ARMED:
2707 			context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2708 			break;
2709 		}
2710 	}
2711 
2712 	if (is_sqp(ibqp->qp_type)) {
2713 		context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2714 	} else if (ibqp->qp_type == IB_QPT_UD ||
2715 		   ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2716 		context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2717 	} else if (attr_mask & IB_QP_PATH_MTU) {
2718 		if (attr->path_mtu < IB_MTU_256 ||
2719 		    attr->path_mtu > IB_MTU_4096) {
2720 			mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2721 			err = -EINVAL;
2722 			goto out;
2723 		}
2724 		context->mtu_msgmax = (attr->path_mtu << 5) |
2725 				      (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
2726 	}
2727 
2728 	if (attr_mask & IB_QP_DEST_QPN)
2729 		context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2730 
2731 	if (attr_mask & IB_QP_PKEY_INDEX)
2732 		context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
2733 
2734 	/* todo implement counter_index functionality */
2735 
2736 	if (is_sqp(ibqp->qp_type))
2737 		context->pri_path.port = qp->port;
2738 
2739 	if (attr_mask & IB_QP_PORT)
2740 		context->pri_path.port = attr->port_num;
2741 
2742 	if (attr_mask & IB_QP_AV) {
2743 		err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
2744 				    attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
2745 				    attr_mask, 0, attr, false);
2746 		if (err)
2747 			goto out;
2748 	}
2749 
2750 	if (attr_mask & IB_QP_TIMEOUT)
2751 		context->pri_path.ackto_lt |= attr->timeout << 3;
2752 
2753 	if (attr_mask & IB_QP_ALT_PATH) {
2754 		err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2755 				    &context->alt_path,
2756 				    attr->alt_port_num,
2757 				    attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2758 				    0, attr, true);
2759 		if (err)
2760 			goto out;
2761 	}
2762 
2763 	pd = get_pd(qp);
2764 	get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2765 		&send_cq, &recv_cq);
2766 
2767 	context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2768 	context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2769 	context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2770 	context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2771 
2772 	if (attr_mask & IB_QP_RNR_RETRY)
2773 		context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2774 
2775 	if (attr_mask & IB_QP_RETRY_CNT)
2776 		context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2777 
2778 	if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2779 		if (attr->max_rd_atomic)
2780 			context->params1 |=
2781 				cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2782 	}
2783 
2784 	if (attr_mask & IB_QP_SQ_PSN)
2785 		context->next_send_psn = cpu_to_be32(attr->sq_psn);
2786 
2787 	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2788 		if (attr->max_dest_rd_atomic)
2789 			context->params2 |=
2790 				cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2791 	}
2792 
2793 	if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
2794 		__be32 access_flags;
2795 
2796 		err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags);
2797 		if (err)
2798 			goto out;
2799 
2800 		context->params2 |= access_flags;
2801 	}
2802 
2803 	if (attr_mask & IB_QP_MIN_RNR_TIMER)
2804 		context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2805 
2806 	if (attr_mask & IB_QP_RQ_PSN)
2807 		context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2808 
2809 	if (attr_mask & IB_QP_QKEY)
2810 		context->qkey = cpu_to_be32(attr->qkey);
2811 
2812 	if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2813 		context->db_rec_addr = cpu_to_be64(qp->db.dma);
2814 
2815 	if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD	&&
2816 	    attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2817 		sqd_event = 1;
2818 	else
2819 		sqd_event = 0;
2820 
2821 	if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2822 		u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2823 			       qp->port) - 1;
2824 		mibport = &dev->port[port_num];
2825 		context->qp_counter_set_usr_page |=
2826 			cpu_to_be32((u32)(mibport->q_cnt_id) << 24);
2827 	}
2828 
2829 	if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2830 		context->sq_crq_size |= cpu_to_be16(1 << 4);
2831 
2832 	if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2833 		context->deth_sqpn = cpu_to_be32(1);
2834 
2835 	mlx5_cur = to_mlx5_state(cur_state);
2836 	mlx5_new = to_mlx5_state(new_state);
2837 	mlx5_st = to_mlx5_st(ibqp->qp_type);
2838 	if (mlx5_st < 0)
2839 		goto out;
2840 
2841 	/* If moving to a reset or error state, we must disable page faults on
2842 	 * this QP and flush all current page faults. Otherwise a stale page
2843 	 * fault may attempt to work on this QP after it is reset and moved
2844 	 * again to RTS, and may cause the driver and the device to get out of
2845 	 * sync. */
2846 	if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2847 	    (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) &&
2848 	    (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2849 		mlx5_ib_qp_disable_pagefaults(qp);
2850 
2851 	if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2852 	    !optab[mlx5_cur][mlx5_new])
2853 		goto out;
2854 
2855 	op = optab[mlx5_cur][mlx5_new];
2856 	optpar = ib_mask_to_mlx5_opt(attr_mask);
2857 	optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2858 
2859 	if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
2860 		struct mlx5_modify_raw_qp_param raw_qp_param = {};
2861 
2862 		raw_qp_param.operation = op;
2863 		if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2864 			raw_qp_param.rq_q_ctr_id = mibport->q_cnt_id;
2865 			raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
2866 		}
2867 		err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2868 	} else {
2869 		err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
2870 					  &base->mqp);
2871 	}
2872 
2873 	if (err)
2874 		goto out;
2875 
2876 	if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT &&
2877 	    (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2878 		mlx5_ib_qp_enable_pagefaults(qp);
2879 
2880 	qp->state = new_state;
2881 
2882 	if (attr_mask & IB_QP_ACCESS_FLAGS)
2883 		qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
2884 	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2885 		qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
2886 	if (attr_mask & IB_QP_PORT)
2887 		qp->port = attr->port_num;
2888 	if (attr_mask & IB_QP_ALT_PATH)
2889 		qp->trans_qp.alt_port = attr->alt_port_num;
2890 
2891 	/*
2892 	 * If we moved a kernel QP to RESET, clean up all old CQ
2893 	 * entries and reinitialize the QP.
2894 	 */
2895 	if (new_state == IB_QPS_RESET && !ibqp->uobject) {
2896 		mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2897 				 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2898 		if (send_cq != recv_cq)
2899 			mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
2900 
2901 		qp->rq.head = 0;
2902 		qp->rq.tail = 0;
2903 		qp->sq.head = 0;
2904 		qp->sq.tail = 0;
2905 		qp->sq.cur_post = 0;
2906 		qp->sq.last_poll = 0;
2907 		qp->db.db[MLX5_RCV_DBR] = 0;
2908 		qp->db.db[MLX5_SND_DBR] = 0;
2909 	}
2910 
2911 out:
2912 	kfree(context);
2913 	return err;
2914 }
2915 
2916 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2917 		      int attr_mask, struct ib_udata *udata)
2918 {
2919 	struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2920 	struct mlx5_ib_qp *qp = to_mqp(ibqp);
2921 	enum ib_qp_type qp_type;
2922 	enum ib_qp_state cur_state, new_state;
2923 	int err = -EINVAL;
2924 	int port;
2925 	enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
2926 
2927 	if (ibqp->rwq_ind_tbl)
2928 		return -ENOSYS;
2929 
2930 	if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2931 		return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2932 
2933 	qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2934 		IB_QPT_GSI : ibqp->qp_type;
2935 
2936 	mutex_lock(&qp->mutex);
2937 
2938 	cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2939 	new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2940 
2941 	if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2942 		port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2943 		ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2944 	}
2945 
2946 	if (qp_type != MLX5_IB_QPT_REG_UMR &&
2947 	    !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
2948 		mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2949 			    cur_state, new_state, ibqp->qp_type, attr_mask);
2950 		goto out;
2951 	}
2952 
2953 	if ((attr_mask & IB_QP_PORT) &&
2954 	    (attr->port_num == 0 ||
2955 	     attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2956 		mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2957 			    attr->port_num, dev->num_ports);
2958 		goto out;
2959 	}
2960 
2961 	if (attr_mask & IB_QP_PKEY_INDEX) {
2962 		port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2963 		if (attr->pkey_index >=
2964 		    dev->mdev->port_caps[port - 1].pkey_table_len) {
2965 			mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2966 				    attr->pkey_index);
2967 			goto out;
2968 		}
2969 	}
2970 
2971 	if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2972 	    attr->max_rd_atomic >
2973 	    (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
2974 		mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
2975 			    attr->max_rd_atomic);
2976 		goto out;
2977 	}
2978 
2979 	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2980 	    attr->max_dest_rd_atomic >
2981 	    (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
2982 		mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
2983 			    attr->max_dest_rd_atomic);
2984 		goto out;
2985 	}
2986 
2987 	if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2988 		err = 0;
2989 		goto out;
2990 	}
2991 
2992 	err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2993 
2994 out:
2995 	mutex_unlock(&qp->mutex);
2996 	return err;
2997 }
2998 
2999 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3000 {
3001 	struct mlx5_ib_cq *cq;
3002 	unsigned cur;
3003 
3004 	cur = wq->head - wq->tail;
3005 	if (likely(cur + nreq < wq->max_post))
3006 		return 0;
3007 
3008 	cq = to_mcq(ib_cq);
3009 	spin_lock(&cq->lock);
3010 	cur = wq->head - wq->tail;
3011 	spin_unlock(&cq->lock);
3012 
3013 	return cur + nreq >= wq->max_post;
3014 }
3015 
3016 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3017 					  u64 remote_addr, u32 rkey)
3018 {
3019 	rseg->raddr    = cpu_to_be64(remote_addr);
3020 	rseg->rkey     = cpu_to_be32(rkey);
3021 	rseg->reserved = 0;
3022 }
3023 
3024 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
3025 			 struct ib_send_wr *wr, void *qend,
3026 			 struct mlx5_ib_qp *qp, int *size)
3027 {
3028 	void *seg = eseg;
3029 
3030 	memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3031 
3032 	if (wr->send_flags & IB_SEND_IP_CSUM)
3033 		eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3034 				 MLX5_ETH_WQE_L4_CSUM;
3035 
3036 	seg += sizeof(struct mlx5_wqe_eth_seg);
3037 	*size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3038 
3039 	if (wr->opcode == IB_WR_LSO) {
3040 		struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
3041 		int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start);
3042 		u64 left, leftlen, copysz;
3043 		void *pdata = ud_wr->header;
3044 
3045 		left = ud_wr->hlen;
3046 		eseg->mss = cpu_to_be16(ud_wr->mss);
3047 		eseg->inline_hdr_sz = cpu_to_be16(left);
3048 
3049 		/*
3050 		 * check if there is space till the end of queue, if yes,
3051 		 * copy all in one shot, otherwise copy till the end of queue,
3052 		 * rollback and than the copy the left
3053 		 */
3054 		leftlen = qend - (void *)eseg->inline_hdr_start;
3055 		copysz = min_t(u64, leftlen, left);
3056 
3057 		memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3058 
3059 		if (likely(copysz > size_of_inl_hdr_start)) {
3060 			seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3061 			*size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3062 		}
3063 
3064 		if (unlikely(copysz < left)) { /* the last wqe in the queue */
3065 			seg = mlx5_get_send_wqe(qp, 0);
3066 			left -= copysz;
3067 			pdata += copysz;
3068 			memcpy(seg, pdata, left);
3069 			seg += ALIGN(left, 16);
3070 			*size += ALIGN(left, 16) / 16;
3071 		}
3072 	}
3073 
3074 	return seg;
3075 }
3076 
3077 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3078 			     struct ib_send_wr *wr)
3079 {
3080 	memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3081 	dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3082 	dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
3083 }
3084 
3085 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3086 {
3087 	dseg->byte_count = cpu_to_be32(sg->length);
3088 	dseg->lkey       = cpu_to_be32(sg->lkey);
3089 	dseg->addr       = cpu_to_be64(sg->addr);
3090 }
3091 
3092 static __be16 get_klm_octo(int npages)
3093 {
3094 	return cpu_to_be16(ALIGN(npages, 8) / 2);
3095 }
3096 
3097 static __be64 frwr_mkey_mask(void)
3098 {
3099 	u64 result;
3100 
3101 	result = MLX5_MKEY_MASK_LEN		|
3102 		MLX5_MKEY_MASK_PAGE_SIZE	|
3103 		MLX5_MKEY_MASK_START_ADDR	|
3104 		MLX5_MKEY_MASK_EN_RINVAL	|
3105 		MLX5_MKEY_MASK_KEY		|
3106 		MLX5_MKEY_MASK_LR		|
3107 		MLX5_MKEY_MASK_LW		|
3108 		MLX5_MKEY_MASK_RR		|
3109 		MLX5_MKEY_MASK_RW		|
3110 		MLX5_MKEY_MASK_A		|
3111 		MLX5_MKEY_MASK_SMALL_FENCE	|
3112 		MLX5_MKEY_MASK_FREE;
3113 
3114 	return cpu_to_be64(result);
3115 }
3116 
3117 static __be64 sig_mkey_mask(void)
3118 {
3119 	u64 result;
3120 
3121 	result = MLX5_MKEY_MASK_LEN		|
3122 		MLX5_MKEY_MASK_PAGE_SIZE	|
3123 		MLX5_MKEY_MASK_START_ADDR	|
3124 		MLX5_MKEY_MASK_EN_SIGERR	|
3125 		MLX5_MKEY_MASK_EN_RINVAL	|
3126 		MLX5_MKEY_MASK_KEY		|
3127 		MLX5_MKEY_MASK_LR		|
3128 		MLX5_MKEY_MASK_LW		|
3129 		MLX5_MKEY_MASK_RR		|
3130 		MLX5_MKEY_MASK_RW		|
3131 		MLX5_MKEY_MASK_SMALL_FENCE	|
3132 		MLX5_MKEY_MASK_FREE		|
3133 		MLX5_MKEY_MASK_BSF_EN;
3134 
3135 	return cpu_to_be64(result);
3136 }
3137 
3138 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3139 				struct mlx5_ib_mr *mr)
3140 {
3141 	int ndescs = mr->ndescs;
3142 
3143 	memset(umr, 0, sizeof(*umr));
3144 
3145 	if (mr->access_mode == MLX5_ACCESS_MODE_KLM)
3146 		/* KLMs take twice the size of MTTs */
3147 		ndescs *= 2;
3148 
3149 	umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3150 	umr->klm_octowords = get_klm_octo(ndescs);
3151 	umr->mkey_mask = frwr_mkey_mask();
3152 }
3153 
3154 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
3155 {
3156 	memset(umr, 0, sizeof(*umr));
3157 	umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
3158 	umr->flags = 1 << 7;
3159 }
3160 
3161 static __be64 get_umr_reg_mr_mask(void)
3162 {
3163 	u64 result;
3164 
3165 	result = MLX5_MKEY_MASK_LEN		|
3166 		 MLX5_MKEY_MASK_PAGE_SIZE	|
3167 		 MLX5_MKEY_MASK_START_ADDR	|
3168 		 MLX5_MKEY_MASK_PD		|
3169 		 MLX5_MKEY_MASK_LR		|
3170 		 MLX5_MKEY_MASK_LW		|
3171 		 MLX5_MKEY_MASK_KEY		|
3172 		 MLX5_MKEY_MASK_RR		|
3173 		 MLX5_MKEY_MASK_RW		|
3174 		 MLX5_MKEY_MASK_A		|
3175 		 MLX5_MKEY_MASK_FREE;
3176 
3177 	return cpu_to_be64(result);
3178 }
3179 
3180 static __be64 get_umr_unreg_mr_mask(void)
3181 {
3182 	u64 result;
3183 
3184 	result = MLX5_MKEY_MASK_FREE;
3185 
3186 	return cpu_to_be64(result);
3187 }
3188 
3189 static __be64 get_umr_update_mtt_mask(void)
3190 {
3191 	u64 result;
3192 
3193 	result = MLX5_MKEY_MASK_FREE;
3194 
3195 	return cpu_to_be64(result);
3196 }
3197 
3198 static __be64 get_umr_update_translation_mask(void)
3199 {
3200 	u64 result;
3201 
3202 	result = MLX5_MKEY_MASK_LEN |
3203 		 MLX5_MKEY_MASK_PAGE_SIZE |
3204 		 MLX5_MKEY_MASK_START_ADDR |
3205 		 MLX5_MKEY_MASK_KEY |
3206 		 MLX5_MKEY_MASK_FREE;
3207 
3208 	return cpu_to_be64(result);
3209 }
3210 
3211 static __be64 get_umr_update_access_mask(void)
3212 {
3213 	u64 result;
3214 
3215 	result = MLX5_MKEY_MASK_LW |
3216 		 MLX5_MKEY_MASK_RR |
3217 		 MLX5_MKEY_MASK_RW |
3218 		 MLX5_MKEY_MASK_A |
3219 		 MLX5_MKEY_MASK_KEY |
3220 		 MLX5_MKEY_MASK_FREE;
3221 
3222 	return cpu_to_be64(result);
3223 }
3224 
3225 static __be64 get_umr_update_pd_mask(void)
3226 {
3227 	u64 result;
3228 
3229 	result = MLX5_MKEY_MASK_PD |
3230 		 MLX5_MKEY_MASK_KEY |
3231 		 MLX5_MKEY_MASK_FREE;
3232 
3233 	return cpu_to_be64(result);
3234 }
3235 
3236 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3237 				struct ib_send_wr *wr)
3238 {
3239 	struct mlx5_umr_wr *umrwr = umr_wr(wr);
3240 
3241 	memset(umr, 0, sizeof(*umr));
3242 
3243 	if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3244 		umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3245 	else
3246 		umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3247 
3248 	if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
3249 		umr->klm_octowords = get_klm_octo(umrwr->npages);
3250 		if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) {
3251 			umr->mkey_mask = get_umr_update_mtt_mask();
3252 			umr->bsf_octowords = get_klm_octo(umrwr->target.offset);
3253 			umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3254 		}
3255 		if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3256 			umr->mkey_mask |= get_umr_update_translation_mask();
3257 		if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_ACCESS)
3258 			umr->mkey_mask |= get_umr_update_access_mask();
3259 		if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD)
3260 			umr->mkey_mask |= get_umr_update_pd_mask();
3261 		if (!umr->mkey_mask)
3262 			umr->mkey_mask = get_umr_reg_mr_mask();
3263 	} else {
3264 		umr->mkey_mask = get_umr_unreg_mr_mask();
3265 	}
3266 
3267 	if (!wr->num_sge)
3268 		umr->flags |= MLX5_UMR_INLINE;
3269 }
3270 
3271 static u8 get_umr_flags(int acc)
3272 {
3273 	return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
3274 	       (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
3275 	       (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
3276 	       (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
3277 		MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3278 }
3279 
3280 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3281 			     struct mlx5_ib_mr *mr,
3282 			     u32 key, int access)
3283 {
3284 	int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3285 
3286 	memset(seg, 0, sizeof(*seg));
3287 
3288 	if (mr->access_mode == MLX5_ACCESS_MODE_MTT)
3289 		seg->log2_page_size = ilog2(mr->ibmr.page_size);
3290 	else if (mr->access_mode == MLX5_ACCESS_MODE_KLM)
3291 		/* KLMs take twice the size of MTTs */
3292 		ndescs *= 2;
3293 
3294 	seg->flags = get_umr_flags(access) | mr->access_mode;
3295 	seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3296 	seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3297 	seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3298 	seg->len = cpu_to_be64(mr->ibmr.length);
3299 	seg->xlt_oct_size = cpu_to_be32(ndescs);
3300 }
3301 
3302 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3303 {
3304 	memset(seg, 0, sizeof(*seg));
3305 	seg->status = MLX5_MKEY_STATUS_FREE;
3306 }
3307 
3308 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3309 {
3310 	struct mlx5_umr_wr *umrwr = umr_wr(wr);
3311 
3312 	memset(seg, 0, sizeof(*seg));
3313 	if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
3314 		seg->status = MLX5_MKEY_STATUS_FREE;
3315 		return;
3316 	}
3317 
3318 	seg->flags = convert_access(umrwr->access_flags);
3319 	if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) {
3320 		if (umrwr->pd)
3321 			seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3322 		seg->start_addr = cpu_to_be64(umrwr->target.virt_addr);
3323 	}
3324 	seg->len = cpu_to_be64(umrwr->length);
3325 	seg->log2_page_size = umrwr->page_shift;
3326 	seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3327 				       mlx5_mkey_variant(umrwr->mkey));
3328 }
3329 
3330 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3331 			     struct mlx5_ib_mr *mr,
3332 			     struct mlx5_ib_pd *pd)
3333 {
3334 	int bcount = mr->desc_size * mr->ndescs;
3335 
3336 	dseg->addr = cpu_to_be64(mr->desc_map);
3337 	dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3338 	dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3339 }
3340 
3341 static __be32 send_ieth(struct ib_send_wr *wr)
3342 {
3343 	switch (wr->opcode) {
3344 	case IB_WR_SEND_WITH_IMM:
3345 	case IB_WR_RDMA_WRITE_WITH_IMM:
3346 		return wr->ex.imm_data;
3347 
3348 	case IB_WR_SEND_WITH_INV:
3349 		return cpu_to_be32(wr->ex.invalidate_rkey);
3350 
3351 	default:
3352 		return 0;
3353 	}
3354 }
3355 
3356 static u8 calc_sig(void *wqe, int size)
3357 {
3358 	u8 *p = wqe;
3359 	u8 res = 0;
3360 	int i;
3361 
3362 	for (i = 0; i < size; i++)
3363 		res ^= p[i];
3364 
3365 	return ~res;
3366 }
3367 
3368 static u8 wq_sig(void *wqe)
3369 {
3370 	return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3371 }
3372 
3373 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3374 			    void *wqe, int *sz)
3375 {
3376 	struct mlx5_wqe_inline_seg *seg;
3377 	void *qend = qp->sq.qend;
3378 	void *addr;
3379 	int inl = 0;
3380 	int copy;
3381 	int len;
3382 	int i;
3383 
3384 	seg = wqe;
3385 	wqe += sizeof(*seg);
3386 	for (i = 0; i < wr->num_sge; i++) {
3387 		addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3388 		len  = wr->sg_list[i].length;
3389 		inl += len;
3390 
3391 		if (unlikely(inl > qp->max_inline_data))
3392 			return -ENOMEM;
3393 
3394 		if (unlikely(wqe + len > qend)) {
3395 			copy = qend - wqe;
3396 			memcpy(wqe, addr, copy);
3397 			addr += copy;
3398 			len -= copy;
3399 			wqe = mlx5_get_send_wqe(qp, 0);
3400 		}
3401 		memcpy(wqe, addr, len);
3402 		wqe += len;
3403 	}
3404 
3405 	seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3406 
3407 	*sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3408 
3409 	return 0;
3410 }
3411 
3412 static u16 prot_field_size(enum ib_signature_type type)
3413 {
3414 	switch (type) {
3415 	case IB_SIG_TYPE_T10_DIF:
3416 		return MLX5_DIF_SIZE;
3417 	default:
3418 		return 0;
3419 	}
3420 }
3421 
3422 static u8 bs_selector(int block_size)
3423 {
3424 	switch (block_size) {
3425 	case 512:	    return 0x1;
3426 	case 520:	    return 0x2;
3427 	case 4096:	    return 0x3;
3428 	case 4160:	    return 0x4;
3429 	case 1073741824:    return 0x5;
3430 	default:	    return 0;
3431 	}
3432 }
3433 
3434 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3435 			      struct mlx5_bsf_inl *inl)
3436 {
3437 	/* Valid inline section and allow BSF refresh */
3438 	inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3439 				       MLX5_BSF_REFRESH_DIF);
3440 	inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3441 	inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
3442 	/* repeating block */
3443 	inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3444 	inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3445 			MLX5_DIF_CRC : MLX5_DIF_IPCS;
3446 
3447 	if (domain->sig.dif.ref_remap)
3448 		inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
3449 
3450 	if (domain->sig.dif.app_escape) {
3451 		if (domain->sig.dif.ref_escape)
3452 			inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3453 		else
3454 			inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
3455 	}
3456 
3457 	inl->dif_app_bitmask_check =
3458 		cpu_to_be16(domain->sig.dif.apptag_check_mask);
3459 }
3460 
3461 static int mlx5_set_bsf(struct ib_mr *sig_mr,
3462 			struct ib_sig_attrs *sig_attrs,
3463 			struct mlx5_bsf *bsf, u32 data_size)
3464 {
3465 	struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3466 	struct mlx5_bsf_basic *basic = &bsf->basic;
3467 	struct ib_sig_domain *mem = &sig_attrs->mem;
3468 	struct ib_sig_domain *wire = &sig_attrs->wire;
3469 
3470 	memset(bsf, 0, sizeof(*bsf));
3471 
3472 	/* Basic + Extended + Inline */
3473 	basic->bsf_size_sbs = 1 << 7;
3474 	/* Input domain check byte mask */
3475 	basic->check_byte_mask = sig_attrs->check_mask;
3476 	basic->raw_data_size = cpu_to_be32(data_size);
3477 
3478 	/* Memory domain */
3479 	switch (sig_attrs->mem.sig_type) {
3480 	case IB_SIG_TYPE_NONE:
3481 		break;
3482 	case IB_SIG_TYPE_T10_DIF:
3483 		basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3484 		basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3485 		mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3486 		break;
3487 	default:
3488 		return -EINVAL;
3489 	}
3490 
3491 	/* Wire domain */
3492 	switch (sig_attrs->wire.sig_type) {
3493 	case IB_SIG_TYPE_NONE:
3494 		break;
3495 	case IB_SIG_TYPE_T10_DIF:
3496 		if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
3497 		    mem->sig_type == wire->sig_type) {
3498 			/* Same block structure */
3499 			basic->bsf_size_sbs |= 1 << 4;
3500 			if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
3501 				basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
3502 			if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
3503 				basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
3504 			if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
3505 				basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
3506 		} else
3507 			basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3508 
3509 		basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
3510 		mlx5_fill_inl_bsf(wire, &bsf->w_inl);
3511 		break;
3512 	default:
3513 		return -EINVAL;
3514 	}
3515 
3516 	return 0;
3517 }
3518 
3519 static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3520 				struct mlx5_ib_qp *qp, void **seg, int *size)
3521 {
3522 	struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3523 	struct ib_mr *sig_mr = wr->sig_mr;
3524 	struct mlx5_bsf *bsf;
3525 	u32 data_len = wr->wr.sg_list->length;
3526 	u32 data_key = wr->wr.sg_list->lkey;
3527 	u64 data_va = wr->wr.sg_list->addr;
3528 	int ret;
3529 	int wqe_size;
3530 
3531 	if (!wr->prot ||
3532 	    (data_key == wr->prot->lkey &&
3533 	     data_va == wr->prot->addr &&
3534 	     data_len == wr->prot->length)) {
3535 		/**
3536 		 * Source domain doesn't contain signature information
3537 		 * or data and protection are interleaved in memory.
3538 		 * So need construct:
3539 		 *                  ------------------
3540 		 *                 |     data_klm     |
3541 		 *                  ------------------
3542 		 *                 |       BSF        |
3543 		 *                  ------------------
3544 		 **/
3545 		struct mlx5_klm *data_klm = *seg;
3546 
3547 		data_klm->bcount = cpu_to_be32(data_len);
3548 		data_klm->key = cpu_to_be32(data_key);
3549 		data_klm->va = cpu_to_be64(data_va);
3550 		wqe_size = ALIGN(sizeof(*data_klm), 64);
3551 	} else {
3552 		/**
3553 		 * Source domain contains signature information
3554 		 * So need construct a strided block format:
3555 		 *               ---------------------------
3556 		 *              |     stride_block_ctrl     |
3557 		 *               ---------------------------
3558 		 *              |          data_klm         |
3559 		 *               ---------------------------
3560 		 *              |          prot_klm         |
3561 		 *               ---------------------------
3562 		 *              |             BSF           |
3563 		 *               ---------------------------
3564 		 **/
3565 		struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3566 		struct mlx5_stride_block_entry *data_sentry;
3567 		struct mlx5_stride_block_entry *prot_sentry;
3568 		u32 prot_key = wr->prot->lkey;
3569 		u64 prot_va = wr->prot->addr;
3570 		u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3571 		int prot_size;
3572 
3573 		sblock_ctrl = *seg;
3574 		data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3575 		prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3576 
3577 		prot_size = prot_field_size(sig_attrs->mem.sig_type);
3578 		if (!prot_size) {
3579 			pr_err("Bad block size given: %u\n", block_size);
3580 			return -EINVAL;
3581 		}
3582 		sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3583 							    prot_size);
3584 		sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3585 		sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3586 		sblock_ctrl->num_entries = cpu_to_be16(2);
3587 
3588 		data_sentry->bcount = cpu_to_be16(block_size);
3589 		data_sentry->key = cpu_to_be32(data_key);
3590 		data_sentry->va = cpu_to_be64(data_va);
3591 		data_sentry->stride = cpu_to_be16(block_size);
3592 
3593 		prot_sentry->bcount = cpu_to_be16(prot_size);
3594 		prot_sentry->key = cpu_to_be32(prot_key);
3595 		prot_sentry->va = cpu_to_be64(prot_va);
3596 		prot_sentry->stride = cpu_to_be16(prot_size);
3597 
3598 		wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3599 				 sizeof(*prot_sentry), 64);
3600 	}
3601 
3602 	*seg += wqe_size;
3603 	*size += wqe_size / 16;
3604 	if (unlikely((*seg == qp->sq.qend)))
3605 		*seg = mlx5_get_send_wqe(qp, 0);
3606 
3607 	bsf = *seg;
3608 	ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3609 	if (ret)
3610 		return -EINVAL;
3611 
3612 	*seg += sizeof(*bsf);
3613 	*size += sizeof(*bsf) / 16;
3614 	if (unlikely((*seg == qp->sq.qend)))
3615 		*seg = mlx5_get_send_wqe(qp, 0);
3616 
3617 	return 0;
3618 }
3619 
3620 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
3621 				 struct ib_sig_handover_wr *wr, u32 nelements,
3622 				 u32 length, u32 pdn)
3623 {
3624 	struct ib_mr *sig_mr = wr->sig_mr;
3625 	u32 sig_key = sig_mr->rkey;
3626 	u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
3627 
3628 	memset(seg, 0, sizeof(*seg));
3629 
3630 	seg->flags = get_umr_flags(wr->access_flags) |
3631 				   MLX5_ACCESS_MODE_KLM;
3632 	seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
3633 	seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
3634 				    MLX5_MKEY_BSF_EN | pdn);
3635 	seg->len = cpu_to_be64(length);
3636 	seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements)));
3637 	seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3638 }
3639 
3640 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3641 				u32 nelements)
3642 {
3643 	memset(umr, 0, sizeof(*umr));
3644 
3645 	umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
3646 	umr->klm_octowords = get_klm_octo(nelements);
3647 	umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3648 	umr->mkey_mask = sig_mkey_mask();
3649 }
3650 
3651 
3652 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
3653 			  void **seg, int *size)
3654 {
3655 	struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3656 	struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
3657 	u32 pdn = get_pd(qp)->pdn;
3658 	u32 klm_oct_size;
3659 	int region_len, ret;
3660 
3661 	if (unlikely(wr->wr.num_sge != 1) ||
3662 	    unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
3663 	    unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3664 	    unlikely(!sig_mr->sig->sig_status_checked))
3665 		return -EINVAL;
3666 
3667 	/* length of the protected region, data + protection */
3668 	region_len = wr->wr.sg_list->length;
3669 	if (wr->prot &&
3670 	    (wr->prot->lkey != wr->wr.sg_list->lkey  ||
3671 	     wr->prot->addr != wr->wr.sg_list->addr  ||
3672 	     wr->prot->length != wr->wr.sg_list->length))
3673 		region_len += wr->prot->length;
3674 
3675 	/**
3676 	 * KLM octoword size - if protection was provided
3677 	 * then we use strided block format (3 octowords),
3678 	 * else we use single KLM (1 octoword)
3679 	 **/
3680 	klm_oct_size = wr->prot ? 3 : 1;
3681 
3682 	set_sig_umr_segment(*seg, klm_oct_size);
3683 	*seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3684 	*size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3685 	if (unlikely((*seg == qp->sq.qend)))
3686 		*seg = mlx5_get_send_wqe(qp, 0);
3687 
3688 	set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn);
3689 	*seg += sizeof(struct mlx5_mkey_seg);
3690 	*size += sizeof(struct mlx5_mkey_seg) / 16;
3691 	if (unlikely((*seg == qp->sq.qend)))
3692 		*seg = mlx5_get_send_wqe(qp, 0);
3693 
3694 	ret = set_sig_data_segment(wr, qp, seg, size);
3695 	if (ret)
3696 		return ret;
3697 
3698 	sig_mr->sig->sig_status_checked = false;
3699 	return 0;
3700 }
3701 
3702 static int set_psv_wr(struct ib_sig_domain *domain,
3703 		      u32 psv_idx, void **seg, int *size)
3704 {
3705 	struct mlx5_seg_set_psv *psv_seg = *seg;
3706 
3707 	memset(psv_seg, 0, sizeof(*psv_seg));
3708 	psv_seg->psv_num = cpu_to_be32(psv_idx);
3709 	switch (domain->sig_type) {
3710 	case IB_SIG_TYPE_NONE:
3711 		break;
3712 	case IB_SIG_TYPE_T10_DIF:
3713 		psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3714 						     domain->sig.dif.app_tag);
3715 		psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
3716 		break;
3717 	default:
3718 		pr_err("Bad signature type given.\n");
3719 		return 1;
3720 	}
3721 
3722 	*seg += sizeof(*psv_seg);
3723 	*size += sizeof(*psv_seg) / 16;
3724 
3725 	return 0;
3726 }
3727 
3728 static int set_reg_wr(struct mlx5_ib_qp *qp,
3729 		      struct ib_reg_wr *wr,
3730 		      void **seg, int *size)
3731 {
3732 	struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3733 	struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3734 
3735 	if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3736 		mlx5_ib_warn(to_mdev(qp->ibqp.device),
3737 			     "Invalid IB_SEND_INLINE send flag\n");
3738 		return -EINVAL;
3739 	}
3740 
3741 	set_reg_umr_seg(*seg, mr);
3742 	*seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3743 	*size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3744 	if (unlikely((*seg == qp->sq.qend)))
3745 		*seg = mlx5_get_send_wqe(qp, 0);
3746 
3747 	set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3748 	*seg += sizeof(struct mlx5_mkey_seg);
3749 	*size += sizeof(struct mlx5_mkey_seg) / 16;
3750 	if (unlikely((*seg == qp->sq.qend)))
3751 		*seg = mlx5_get_send_wqe(qp, 0);
3752 
3753 	set_reg_data_seg(*seg, mr, pd);
3754 	*seg += sizeof(struct mlx5_wqe_data_seg);
3755 	*size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3756 
3757 	return 0;
3758 }
3759 
3760 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
3761 {
3762 	set_linv_umr_seg(*seg);
3763 	*seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3764 	*size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3765 	if (unlikely((*seg == qp->sq.qend)))
3766 		*seg = mlx5_get_send_wqe(qp, 0);
3767 	set_linv_mkey_seg(*seg);
3768 	*seg += sizeof(struct mlx5_mkey_seg);
3769 	*size += sizeof(struct mlx5_mkey_seg) / 16;
3770 	if (unlikely((*seg == qp->sq.qend)))
3771 		*seg = mlx5_get_send_wqe(qp, 0);
3772 }
3773 
3774 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3775 {
3776 	__be32 *p = NULL;
3777 	int tidx = idx;
3778 	int i, j;
3779 
3780 	pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3781 	for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3782 		if ((i & 0xf) == 0) {
3783 			void *buf = mlx5_get_send_wqe(qp, tidx);
3784 			tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3785 			p = buf;
3786 			j = 0;
3787 		}
3788 		pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3789 			 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3790 			 be32_to_cpu(p[j + 3]));
3791 	}
3792 }
3793 
3794 static u8 get_fence(u8 fence, struct ib_send_wr *wr)
3795 {
3796 	if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
3797 		     wr->send_flags & IB_SEND_FENCE))
3798 		return MLX5_FENCE_MODE_STRONG_ORDERING;
3799 
3800 	if (unlikely(fence)) {
3801 		if (wr->send_flags & IB_SEND_FENCE)
3802 			return MLX5_FENCE_MODE_SMALL_AND_FENCE;
3803 		else
3804 			return fence;
3805 	} else if (unlikely(wr->send_flags & IB_SEND_FENCE)) {
3806 		return MLX5_FENCE_MODE_FENCE;
3807 	}
3808 
3809 	return 0;
3810 }
3811 
3812 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3813 		     struct mlx5_wqe_ctrl_seg **ctrl,
3814 		     struct ib_send_wr *wr, unsigned *idx,
3815 		     int *size, int nreq)
3816 {
3817 	if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
3818 		return -ENOMEM;
3819 
3820 	*idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3821 	*seg = mlx5_get_send_wqe(qp, *idx);
3822 	*ctrl = *seg;
3823 	*(uint32_t *)(*seg + 8) = 0;
3824 	(*ctrl)->imm = send_ieth(wr);
3825 	(*ctrl)->fm_ce_se = qp->sq_signal_bits |
3826 		(wr->send_flags & IB_SEND_SIGNALED ?
3827 		 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3828 		(wr->send_flags & IB_SEND_SOLICITED ?
3829 		 MLX5_WQE_CTRL_SOLICITED : 0);
3830 
3831 	*seg += sizeof(**ctrl);
3832 	*size = sizeof(**ctrl) / 16;
3833 
3834 	return 0;
3835 }
3836 
3837 static void finish_wqe(struct mlx5_ib_qp *qp,
3838 		       struct mlx5_wqe_ctrl_seg *ctrl,
3839 		       u8 size, unsigned idx, u64 wr_id,
3840 		       int nreq, u8 fence, u8 next_fence,
3841 		       u32 mlx5_opcode)
3842 {
3843 	u8 opmod = 0;
3844 
3845 	ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3846 					     mlx5_opcode | ((u32)opmod << 24));
3847 	ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
3848 	ctrl->fm_ce_se |= fence;
3849 	qp->fm_cache = next_fence;
3850 	if (unlikely(qp->wq_sig))
3851 		ctrl->signature = wq_sig(ctrl);
3852 
3853 	qp->sq.wrid[idx] = wr_id;
3854 	qp->sq.w_list[idx].opcode = mlx5_opcode;
3855 	qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3856 	qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3857 	qp->sq.w_list[idx].next = qp->sq.cur_post;
3858 }
3859 
3860 
3861 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3862 		      struct ib_send_wr **bad_wr)
3863 {
3864 	struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
3865 	struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3866 	struct mlx5_core_dev *mdev = dev->mdev;
3867 	struct mlx5_ib_qp *qp;
3868 	struct mlx5_ib_mr *mr;
3869 	struct mlx5_wqe_data_seg *dpseg;
3870 	struct mlx5_wqe_xrc_seg *xrc;
3871 	struct mlx5_bf *bf;
3872 	int uninitialized_var(size);
3873 	void *qend;
3874 	unsigned long flags;
3875 	unsigned idx;
3876 	int err = 0;
3877 	int inl = 0;
3878 	int num_sge;
3879 	void *seg;
3880 	int nreq;
3881 	int i;
3882 	u8 next_fence = 0;
3883 	u8 fence;
3884 
3885 	if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3886 		return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3887 
3888 	qp = to_mqp(ibqp);
3889 	bf = &qp->bf;
3890 	qend = qp->sq.qend;
3891 
3892 	spin_lock_irqsave(&qp->sq.lock, flags);
3893 
3894 	if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
3895 		err = -EIO;
3896 		*bad_wr = wr;
3897 		nreq = 0;
3898 		goto out;
3899 	}
3900 
3901 	for (nreq = 0; wr; nreq++, wr = wr->next) {
3902 		if (unlikely(wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
3903 			mlx5_ib_warn(dev, "\n");
3904 			err = -EINVAL;
3905 			*bad_wr = wr;
3906 			goto out;
3907 		}
3908 
3909 		fence = qp->fm_cache;
3910 		num_sge = wr->num_sge;
3911 		if (unlikely(num_sge > qp->sq.max_gs)) {
3912 			mlx5_ib_warn(dev, "\n");
3913 			err = -EINVAL;
3914 			*bad_wr = wr;
3915 			goto out;
3916 		}
3917 
3918 		err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3919 		if (err) {
3920 			mlx5_ib_warn(dev, "\n");
3921 			err = -ENOMEM;
3922 			*bad_wr = wr;
3923 			goto out;
3924 		}
3925 
3926 		switch (ibqp->qp_type) {
3927 		case IB_QPT_XRC_INI:
3928 			xrc = seg;
3929 			seg += sizeof(*xrc);
3930 			size += sizeof(*xrc) / 16;
3931 			/* fall through */
3932 		case IB_QPT_RC:
3933 			switch (wr->opcode) {
3934 			case IB_WR_RDMA_READ:
3935 			case IB_WR_RDMA_WRITE:
3936 			case IB_WR_RDMA_WRITE_WITH_IMM:
3937 				set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3938 					      rdma_wr(wr)->rkey);
3939 				seg += sizeof(struct mlx5_wqe_raddr_seg);
3940 				size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3941 				break;
3942 
3943 			case IB_WR_ATOMIC_CMP_AND_SWP:
3944 			case IB_WR_ATOMIC_FETCH_AND_ADD:
3945 			case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3946 				mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3947 				err = -ENOSYS;
3948 				*bad_wr = wr;
3949 				goto out;
3950 
3951 			case IB_WR_LOCAL_INV:
3952 				next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3953 				qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3954 				ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
3955 				set_linv_wr(qp, &seg, &size);
3956 				num_sge = 0;
3957 				break;
3958 
3959 			case IB_WR_REG_MR:
3960 				next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3961 				qp->sq.wr_data[idx] = IB_WR_REG_MR;
3962 				ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3963 				err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3964 				if (err) {
3965 					*bad_wr = wr;
3966 					goto out;
3967 				}
3968 				num_sge = 0;
3969 				break;
3970 
3971 			case IB_WR_REG_SIG_MR:
3972 				qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
3973 				mr = to_mmr(sig_handover_wr(wr)->sig_mr);
3974 
3975 				ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3976 				err = set_sig_umr_wr(wr, qp, &seg, &size);
3977 				if (err) {
3978 					mlx5_ib_warn(dev, "\n");
3979 					*bad_wr = wr;
3980 					goto out;
3981 				}
3982 
3983 				finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3984 					   nreq, get_fence(fence, wr),
3985 					   next_fence, MLX5_OPCODE_UMR);
3986 				/*
3987 				 * SET_PSV WQEs are not signaled and solicited
3988 				 * on error
3989 				 */
3990 				wr->send_flags &= ~IB_SEND_SIGNALED;
3991 				wr->send_flags |= IB_SEND_SOLICITED;
3992 				err = begin_wqe(qp, &seg, &ctrl, wr,
3993 						&idx, &size, nreq);
3994 				if (err) {
3995 					mlx5_ib_warn(dev, "\n");
3996 					err = -ENOMEM;
3997 					*bad_wr = wr;
3998 					goto out;
3999 				}
4000 
4001 				err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
4002 						 mr->sig->psv_memory.psv_idx, &seg,
4003 						 &size);
4004 				if (err) {
4005 					mlx5_ib_warn(dev, "\n");
4006 					*bad_wr = wr;
4007 					goto out;
4008 				}
4009 
4010 				finish_wqe(qp, ctrl, size, idx, wr->wr_id,
4011 					   nreq, get_fence(fence, wr),
4012 					   next_fence, MLX5_OPCODE_SET_PSV);
4013 				err = begin_wqe(qp, &seg, &ctrl, wr,
4014 						&idx, &size, nreq);
4015 				if (err) {
4016 					mlx5_ib_warn(dev, "\n");
4017 					err = -ENOMEM;
4018 					*bad_wr = wr;
4019 					goto out;
4020 				}
4021 
4022 				next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4023 				err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
4024 						 mr->sig->psv_wire.psv_idx, &seg,
4025 						 &size);
4026 				if (err) {
4027 					mlx5_ib_warn(dev, "\n");
4028 					*bad_wr = wr;
4029 					goto out;
4030 				}
4031 
4032 				finish_wqe(qp, ctrl, size, idx, wr->wr_id,
4033 					   nreq, get_fence(fence, wr),
4034 					   next_fence, MLX5_OPCODE_SET_PSV);
4035 				num_sge = 0;
4036 				goto skip_psv;
4037 
4038 			default:
4039 				break;
4040 			}
4041 			break;
4042 
4043 		case IB_QPT_UC:
4044 			switch (wr->opcode) {
4045 			case IB_WR_RDMA_WRITE:
4046 			case IB_WR_RDMA_WRITE_WITH_IMM:
4047 				set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4048 					      rdma_wr(wr)->rkey);
4049 				seg  += sizeof(struct mlx5_wqe_raddr_seg);
4050 				size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4051 				break;
4052 
4053 			default:
4054 				break;
4055 			}
4056 			break;
4057 
4058 		case IB_QPT_SMI:
4059 		case MLX5_IB_QPT_HW_GSI:
4060 			set_datagram_seg(seg, wr);
4061 			seg += sizeof(struct mlx5_wqe_datagram_seg);
4062 			size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4063 			if (unlikely((seg == qend)))
4064 				seg = mlx5_get_send_wqe(qp, 0);
4065 			break;
4066 		case IB_QPT_UD:
4067 			set_datagram_seg(seg, wr);
4068 			seg += sizeof(struct mlx5_wqe_datagram_seg);
4069 			size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4070 
4071 			if (unlikely((seg == qend)))
4072 				seg = mlx5_get_send_wqe(qp, 0);
4073 
4074 			/* handle qp that supports ud offload */
4075 			if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4076 				struct mlx5_wqe_eth_pad *pad;
4077 
4078 				pad = seg;
4079 				memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4080 				seg += sizeof(struct mlx5_wqe_eth_pad);
4081 				size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4082 
4083 				seg = set_eth_seg(seg, wr, qend, qp, &size);
4084 
4085 				if (unlikely((seg == qend)))
4086 					seg = mlx5_get_send_wqe(qp, 0);
4087 			}
4088 			break;
4089 		case MLX5_IB_QPT_REG_UMR:
4090 			if (wr->opcode != MLX5_IB_WR_UMR) {
4091 				err = -EINVAL;
4092 				mlx5_ib_warn(dev, "bad opcode\n");
4093 				goto out;
4094 			}
4095 			qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4096 			ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4097 			set_reg_umr_segment(seg, wr);
4098 			seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4099 			size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4100 			if (unlikely((seg == qend)))
4101 				seg = mlx5_get_send_wqe(qp, 0);
4102 			set_reg_mkey_segment(seg, wr);
4103 			seg += sizeof(struct mlx5_mkey_seg);
4104 			size += sizeof(struct mlx5_mkey_seg) / 16;
4105 			if (unlikely((seg == qend)))
4106 				seg = mlx5_get_send_wqe(qp, 0);
4107 			break;
4108 
4109 		default:
4110 			break;
4111 		}
4112 
4113 		if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4114 			int uninitialized_var(sz);
4115 
4116 			err = set_data_inl_seg(qp, wr, seg, &sz);
4117 			if (unlikely(err)) {
4118 				mlx5_ib_warn(dev, "\n");
4119 				*bad_wr = wr;
4120 				goto out;
4121 			}
4122 			inl = 1;
4123 			size += sz;
4124 		} else {
4125 			dpseg = seg;
4126 			for (i = 0; i < num_sge; i++) {
4127 				if (unlikely(dpseg == qend)) {
4128 					seg = mlx5_get_send_wqe(qp, 0);
4129 					dpseg = seg;
4130 				}
4131 				if (likely(wr->sg_list[i].length)) {
4132 					set_data_ptr_seg(dpseg, wr->sg_list + i);
4133 					size += sizeof(struct mlx5_wqe_data_seg) / 16;
4134 					dpseg++;
4135 				}
4136 			}
4137 		}
4138 
4139 		finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4140 			   get_fence(fence, wr), next_fence,
4141 			   mlx5_ib_opcode[wr->opcode]);
4142 skip_psv:
4143 		if (0)
4144 			dump_wqe(qp, idx, size);
4145 	}
4146 
4147 out:
4148 	if (likely(nreq)) {
4149 		qp->sq.head += nreq;
4150 
4151 		/* Make sure that descriptors are written before
4152 		 * updating doorbell record and ringing the doorbell
4153 		 */
4154 		wmb();
4155 
4156 		qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4157 
4158 		/* Make sure doorbell record is visible to the HCA before
4159 		 * we hit doorbell */
4160 		wmb();
4161 
4162 		mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset,
4163 			     MLX5_GET_DOORBELL_LOCK(&bf->lock32));
4164 		/* Make sure doorbells don't leak out of SQ spinlock
4165 		 * and reach the HCA out of order.
4166 		 */
4167 		bf->offset ^= bf->buf_size;
4168 	}
4169 
4170 	spin_unlock_irqrestore(&qp->sq.lock, flags);
4171 
4172 	return err;
4173 }
4174 
4175 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4176 {
4177 	sig->signature = calc_sig(sig, size);
4178 }
4179 
4180 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4181 		      struct ib_recv_wr **bad_wr)
4182 {
4183 	struct mlx5_ib_qp *qp = to_mqp(ibqp);
4184 	struct mlx5_wqe_data_seg *scat;
4185 	struct mlx5_rwqe_sig *sig;
4186 	struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4187 	struct mlx5_core_dev *mdev = dev->mdev;
4188 	unsigned long flags;
4189 	int err = 0;
4190 	int nreq;
4191 	int ind;
4192 	int i;
4193 
4194 	if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4195 		return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4196 
4197 	spin_lock_irqsave(&qp->rq.lock, flags);
4198 
4199 	if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4200 		err = -EIO;
4201 		*bad_wr = wr;
4202 		nreq = 0;
4203 		goto out;
4204 	}
4205 
4206 	ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4207 
4208 	for (nreq = 0; wr; nreq++, wr = wr->next) {
4209 		if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4210 			err = -ENOMEM;
4211 			*bad_wr = wr;
4212 			goto out;
4213 		}
4214 
4215 		if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4216 			err = -EINVAL;
4217 			*bad_wr = wr;
4218 			goto out;
4219 		}
4220 
4221 		scat = get_recv_wqe(qp, ind);
4222 		if (qp->wq_sig)
4223 			scat++;
4224 
4225 		for (i = 0; i < wr->num_sge; i++)
4226 			set_data_ptr_seg(scat + i, wr->sg_list + i);
4227 
4228 		if (i < qp->rq.max_gs) {
4229 			scat[i].byte_count = 0;
4230 			scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
4231 			scat[i].addr       = 0;
4232 		}
4233 
4234 		if (qp->wq_sig) {
4235 			sig = (struct mlx5_rwqe_sig *)scat;
4236 			set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4237 		}
4238 
4239 		qp->rq.wrid[ind] = wr->wr_id;
4240 
4241 		ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4242 	}
4243 
4244 out:
4245 	if (likely(nreq)) {
4246 		qp->rq.head += nreq;
4247 
4248 		/* Make sure that descriptors are written before
4249 		 * doorbell record.
4250 		 */
4251 		wmb();
4252 
4253 		*qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4254 	}
4255 
4256 	spin_unlock_irqrestore(&qp->rq.lock, flags);
4257 
4258 	return err;
4259 }
4260 
4261 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4262 {
4263 	switch (mlx5_state) {
4264 	case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
4265 	case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
4266 	case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
4267 	case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
4268 	case MLX5_QP_STATE_SQ_DRAINING:
4269 	case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
4270 	case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
4271 	case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
4272 	default:		     return -1;
4273 	}
4274 }
4275 
4276 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4277 {
4278 	switch (mlx5_mig_state) {
4279 	case MLX5_QP_PM_ARMED:		return IB_MIG_ARMED;
4280 	case MLX5_QP_PM_REARM:		return IB_MIG_REARM;
4281 	case MLX5_QP_PM_MIGRATED:	return IB_MIG_MIGRATED;
4282 	default: return -1;
4283 	}
4284 }
4285 
4286 static int to_ib_qp_access_flags(int mlx5_flags)
4287 {
4288 	int ib_flags = 0;
4289 
4290 	if (mlx5_flags & MLX5_QP_BIT_RRE)
4291 		ib_flags |= IB_ACCESS_REMOTE_READ;
4292 	if (mlx5_flags & MLX5_QP_BIT_RWE)
4293 		ib_flags |= IB_ACCESS_REMOTE_WRITE;
4294 	if (mlx5_flags & MLX5_QP_BIT_RAE)
4295 		ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4296 
4297 	return ib_flags;
4298 }
4299 
4300 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
4301 				struct mlx5_qp_path *path)
4302 {
4303 	struct mlx5_core_dev *dev = ibdev->mdev;
4304 
4305 	memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
4306 	ib_ah_attr->port_num	  = path->port;
4307 
4308 	if (ib_ah_attr->port_num == 0 ||
4309 	    ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports))
4310 		return;
4311 
4312 	ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf;
4313 
4314 	ib_ah_attr->dlid	  = be16_to_cpu(path->rlid);
4315 	ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
4316 	ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
4317 	ib_ah_attr->ah_flags      = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
4318 	if (ib_ah_attr->ah_flags) {
4319 		ib_ah_attr->grh.sgid_index = path->mgid_index;
4320 		ib_ah_attr->grh.hop_limit  = path->hop_limit;
4321 		ib_ah_attr->grh.traffic_class =
4322 			(be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
4323 		ib_ah_attr->grh.flow_label =
4324 			be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
4325 		memcpy(ib_ah_attr->grh.dgid.raw,
4326 		       path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
4327 	}
4328 }
4329 
4330 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4331 					struct mlx5_ib_sq *sq,
4332 					u8 *sq_state)
4333 {
4334 	void *out;
4335 	void *sqc;
4336 	int inlen;
4337 	int err;
4338 
4339 	inlen = MLX5_ST_SZ_BYTES(query_sq_out);
4340 	out = mlx5_vzalloc(inlen);
4341 	if (!out)
4342 		return -ENOMEM;
4343 
4344 	err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4345 	if (err)
4346 		goto out;
4347 
4348 	sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4349 	*sq_state = MLX5_GET(sqc, sqc, state);
4350 	sq->state = *sq_state;
4351 
4352 out:
4353 	kvfree(out);
4354 	return err;
4355 }
4356 
4357 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4358 					struct mlx5_ib_rq *rq,
4359 					u8 *rq_state)
4360 {
4361 	void *out;
4362 	void *rqc;
4363 	int inlen;
4364 	int err;
4365 
4366 	inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4367 	out = mlx5_vzalloc(inlen);
4368 	if (!out)
4369 		return -ENOMEM;
4370 
4371 	err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4372 	if (err)
4373 		goto out;
4374 
4375 	rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4376 	*rq_state = MLX5_GET(rqc, rqc, state);
4377 	rq->state = *rq_state;
4378 
4379 out:
4380 	kvfree(out);
4381 	return err;
4382 }
4383 
4384 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4385 				  struct mlx5_ib_qp *qp, u8 *qp_state)
4386 {
4387 	static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4388 		[MLX5_RQC_STATE_RST] = {
4389 			[MLX5_SQC_STATE_RST]	= IB_QPS_RESET,
4390 			[MLX5_SQC_STATE_RDY]	= MLX5_QP_STATE_BAD,
4391 			[MLX5_SQC_STATE_ERR]	= MLX5_QP_STATE_BAD,
4392 			[MLX5_SQ_STATE_NA]	= IB_QPS_RESET,
4393 		},
4394 		[MLX5_RQC_STATE_RDY] = {
4395 			[MLX5_SQC_STATE_RST]	= MLX5_QP_STATE_BAD,
4396 			[MLX5_SQC_STATE_RDY]	= MLX5_QP_STATE,
4397 			[MLX5_SQC_STATE_ERR]	= IB_QPS_SQE,
4398 			[MLX5_SQ_STATE_NA]	= MLX5_QP_STATE,
4399 		},
4400 		[MLX5_RQC_STATE_ERR] = {
4401 			[MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
4402 			[MLX5_SQC_STATE_RDY]	= MLX5_QP_STATE_BAD,
4403 			[MLX5_SQC_STATE_ERR]	= IB_QPS_ERR,
4404 			[MLX5_SQ_STATE_NA]	= IB_QPS_ERR,
4405 		},
4406 		[MLX5_RQ_STATE_NA] = {
4407 			[MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
4408 			[MLX5_SQC_STATE_RDY]	= MLX5_QP_STATE,
4409 			[MLX5_SQC_STATE_ERR]	= MLX5_QP_STATE,
4410 			[MLX5_SQ_STATE_NA]	= MLX5_QP_STATE_BAD,
4411 		},
4412 	};
4413 
4414 	*qp_state = sqrq_trans[rq_state][sq_state];
4415 
4416 	if (*qp_state == MLX5_QP_STATE_BAD) {
4417 		WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4418 		     qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4419 		     qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4420 		return -EINVAL;
4421 	}
4422 
4423 	if (*qp_state == MLX5_QP_STATE)
4424 		*qp_state = qp->state;
4425 
4426 	return 0;
4427 }
4428 
4429 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4430 				     struct mlx5_ib_qp *qp,
4431 				     u8 *raw_packet_qp_state)
4432 {
4433 	struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4434 	struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4435 	struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4436 	int err;
4437 	u8 sq_state = MLX5_SQ_STATE_NA;
4438 	u8 rq_state = MLX5_RQ_STATE_NA;
4439 
4440 	if (qp->sq.wqe_cnt) {
4441 		err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4442 		if (err)
4443 			return err;
4444 	}
4445 
4446 	if (qp->rq.wqe_cnt) {
4447 		err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4448 		if (err)
4449 			return err;
4450 	}
4451 
4452 	return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4453 				      raw_packet_qp_state);
4454 }
4455 
4456 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4457 			 struct ib_qp_attr *qp_attr)
4458 {
4459 	int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
4460 	struct mlx5_qp_context *context;
4461 	int mlx5_state;
4462 	u32 *outb;
4463 	int err = 0;
4464 
4465 	outb = kzalloc(outlen, GFP_KERNEL);
4466 	if (!outb)
4467 		return -ENOMEM;
4468 
4469 	err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
4470 				 outlen);
4471 	if (err)
4472 		goto out;
4473 
4474 	/* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4475 	context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4476 
4477 	mlx5_state = be32_to_cpu(context->flags) >> 28;
4478 
4479 	qp->state		     = to_ib_qp_state(mlx5_state);
4480 	qp_attr->path_mtu	     = context->mtu_msgmax >> 5;
4481 	qp_attr->path_mig_state	     =
4482 		to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4483 	qp_attr->qkey		     = be32_to_cpu(context->qkey);
4484 	qp_attr->rq_psn		     = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4485 	qp_attr->sq_psn		     = be32_to_cpu(context->next_send_psn) & 0xffffff;
4486 	qp_attr->dest_qp_num	     = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4487 	qp_attr->qp_access_flags     =
4488 		to_ib_qp_access_flags(be32_to_cpu(context->params2));
4489 
4490 	if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4491 		to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4492 		to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
4493 		qp_attr->alt_pkey_index =
4494 			be16_to_cpu(context->alt_path.pkey_index);
4495 		qp_attr->alt_port_num	= qp_attr->alt_ah_attr.port_num;
4496 	}
4497 
4498 	qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
4499 	qp_attr->port_num = context->pri_path.port;
4500 
4501 	/* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4502 	qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4503 
4504 	qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4505 
4506 	qp_attr->max_dest_rd_atomic =
4507 		1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4508 	qp_attr->min_rnr_timer	    =
4509 		(be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4510 	qp_attr->timeout	    = context->pri_path.ackto_lt >> 3;
4511 	qp_attr->retry_cnt	    = (be32_to_cpu(context->params1) >> 16) & 0x7;
4512 	qp_attr->rnr_retry	    = (be32_to_cpu(context->params1) >> 13) & 0x7;
4513 	qp_attr->alt_timeout	    = context->alt_path.ackto_lt >> 3;
4514 
4515 out:
4516 	kfree(outb);
4517 	return err;
4518 }
4519 
4520 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4521 		     int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4522 {
4523 	struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4524 	struct mlx5_ib_qp *qp = to_mqp(ibqp);
4525 	int err = 0;
4526 	u8 raw_packet_qp_state;
4527 
4528 	if (ibqp->rwq_ind_tbl)
4529 		return -ENOSYS;
4530 
4531 	if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4532 		return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4533 					    qp_init_attr);
4534 
4535 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4536 	/*
4537 	 * Wait for any outstanding page faults, in case the user frees memory
4538 	 * based upon this query's result.
4539 	 */
4540 	flush_workqueue(mlx5_ib_page_fault_wq);
4541 #endif
4542 
4543 	mutex_lock(&qp->mutex);
4544 
4545 	if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
4546 		err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4547 		if (err)
4548 			goto out;
4549 		qp->state = raw_packet_qp_state;
4550 		qp_attr->port_num = 1;
4551 	} else {
4552 		err = query_qp_attr(dev, qp, qp_attr);
4553 		if (err)
4554 			goto out;
4555 	}
4556 
4557 	qp_attr->qp_state	     = qp->state;
4558 	qp_attr->cur_qp_state	     = qp_attr->qp_state;
4559 	qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
4560 	qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
4561 
4562 	if (!ibqp->uobject) {
4563 		qp_attr->cap.max_send_wr  = qp->sq.max_post;
4564 		qp_attr->cap.max_send_sge = qp->sq.max_gs;
4565 		qp_init_attr->qp_context = ibqp->qp_context;
4566 	} else {
4567 		qp_attr->cap.max_send_wr  = 0;
4568 		qp_attr->cap.max_send_sge = 0;
4569 	}
4570 
4571 	qp_init_attr->qp_type = ibqp->qp_type;
4572 	qp_init_attr->recv_cq = ibqp->recv_cq;
4573 	qp_init_attr->send_cq = ibqp->send_cq;
4574 	qp_init_attr->srq = ibqp->srq;
4575 	qp_attr->cap.max_inline_data = qp->max_inline_data;
4576 
4577 	qp_init_attr->cap	     = qp_attr->cap;
4578 
4579 	qp_init_attr->create_flags = 0;
4580 	if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4581 		qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4582 
4583 	if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4584 		qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4585 	if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4586 		qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4587 	if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4588 		qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
4589 	if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4590 		qp_init_attr->create_flags |= MLX5_IB_QP_CREATE_SQPN_QP1;
4591 
4592 	qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4593 		IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4594 
4595 out:
4596 	mutex_unlock(&qp->mutex);
4597 	return err;
4598 }
4599 
4600 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4601 					  struct ib_ucontext *context,
4602 					  struct ib_udata *udata)
4603 {
4604 	struct mlx5_ib_dev *dev = to_mdev(ibdev);
4605 	struct mlx5_ib_xrcd *xrcd;
4606 	int err;
4607 
4608 	if (!MLX5_CAP_GEN(dev->mdev, xrc))
4609 		return ERR_PTR(-ENOSYS);
4610 
4611 	xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4612 	if (!xrcd)
4613 		return ERR_PTR(-ENOMEM);
4614 
4615 	err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
4616 	if (err) {
4617 		kfree(xrcd);
4618 		return ERR_PTR(-ENOMEM);
4619 	}
4620 
4621 	return &xrcd->ibxrcd;
4622 }
4623 
4624 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4625 {
4626 	struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4627 	u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4628 	int err;
4629 
4630 	err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
4631 	if (err) {
4632 		mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4633 		return err;
4634 	}
4635 
4636 	kfree(xrcd);
4637 
4638 	return 0;
4639 }
4640 
4641 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4642 {
4643 	struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4644 	struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4645 	struct ib_event event;
4646 
4647 	if (rwq->ibwq.event_handler) {
4648 		event.device     = rwq->ibwq.device;
4649 		event.element.wq = &rwq->ibwq;
4650 		switch (type) {
4651 		case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4652 			event.event = IB_EVENT_WQ_FATAL;
4653 			break;
4654 		default:
4655 			mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4656 			return;
4657 		}
4658 
4659 		rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4660 	}
4661 }
4662 
4663 static int  create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4664 		      struct ib_wq_init_attr *init_attr)
4665 {
4666 	struct mlx5_ib_dev *dev;
4667 	__be64 *rq_pas0;
4668 	void *in;
4669 	void *rqc;
4670 	void *wq;
4671 	int inlen;
4672 	int err;
4673 
4674 	dev = to_mdev(pd->device);
4675 
4676 	inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4677 	in = mlx5_vzalloc(inlen);
4678 	if (!in)
4679 		return -ENOMEM;
4680 
4681 	rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4682 	MLX5_SET(rqc,  rqc, mem_rq_type,
4683 		 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE);
4684 	MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4685 	MLX5_SET(rqc,  rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4686 	MLX5_SET(rqc,  rqc, state, MLX5_RQC_STATE_RST);
4687 	MLX5_SET(rqc,  rqc, flush_in_error_en, 1);
4688 	wq = MLX5_ADDR_OF(rqc, rqc, wq);
4689 	MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
4690 	MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4691 	MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4692 	MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4693 	MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4694 	MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4695 	MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4696 	MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4697 	MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4698 	rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4699 	mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
4700 	err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
4701 	kvfree(in);
4702 	return err;
4703 }
4704 
4705 static int set_user_rq_size(struct mlx5_ib_dev *dev,
4706 			    struct ib_wq_init_attr *wq_init_attr,
4707 			    struct mlx5_ib_create_wq *ucmd,
4708 			    struct mlx5_ib_rwq *rwq)
4709 {
4710 	/* Sanity check RQ size before proceeding */
4711 	if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4712 		return -EINVAL;
4713 
4714 	if (!ucmd->rq_wqe_count)
4715 		return -EINVAL;
4716 
4717 	rwq->wqe_count = ucmd->rq_wqe_count;
4718 	rwq->wqe_shift = ucmd->rq_wqe_shift;
4719 	rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4720 	rwq->log_rq_stride = rwq->wqe_shift;
4721 	rwq->log_rq_size = ilog2(rwq->wqe_count);
4722 	return 0;
4723 }
4724 
4725 static int prepare_user_rq(struct ib_pd *pd,
4726 			   struct ib_wq_init_attr *init_attr,
4727 			   struct ib_udata *udata,
4728 			   struct mlx5_ib_rwq *rwq)
4729 {
4730 	struct mlx5_ib_dev *dev = to_mdev(pd->device);
4731 	struct mlx5_ib_create_wq ucmd = {};
4732 	int err;
4733 	size_t required_cmd_sz;
4734 
4735 	required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4736 	if (udata->inlen < required_cmd_sz) {
4737 		mlx5_ib_dbg(dev, "invalid inlen\n");
4738 		return -EINVAL;
4739 	}
4740 
4741 	if (udata->inlen > sizeof(ucmd) &&
4742 	    !ib_is_udata_cleared(udata, sizeof(ucmd),
4743 				 udata->inlen - sizeof(ucmd))) {
4744 		mlx5_ib_dbg(dev, "inlen is not supported\n");
4745 		return -EOPNOTSUPP;
4746 	}
4747 
4748 	if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4749 		mlx5_ib_dbg(dev, "copy failed\n");
4750 		return -EFAULT;
4751 	}
4752 
4753 	if (ucmd.comp_mask) {
4754 		mlx5_ib_dbg(dev, "invalid comp mask\n");
4755 		return -EOPNOTSUPP;
4756 	}
4757 
4758 	if (ucmd.reserved) {
4759 		mlx5_ib_dbg(dev, "invalid reserved\n");
4760 		return -EOPNOTSUPP;
4761 	}
4762 
4763 	err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4764 	if (err) {
4765 		mlx5_ib_dbg(dev, "err %d\n", err);
4766 		return err;
4767 	}
4768 
4769 	err = create_user_rq(dev, pd, rwq, &ucmd);
4770 	if (err) {
4771 		mlx5_ib_dbg(dev, "err %d\n", err);
4772 		if (err)
4773 			return err;
4774 	}
4775 
4776 	rwq->user_index = ucmd.user_index;
4777 	return 0;
4778 }
4779 
4780 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4781 				struct ib_wq_init_attr *init_attr,
4782 				struct ib_udata *udata)
4783 {
4784 	struct mlx5_ib_dev *dev;
4785 	struct mlx5_ib_rwq *rwq;
4786 	struct mlx5_ib_create_wq_resp resp = {};
4787 	size_t min_resp_len;
4788 	int err;
4789 
4790 	if (!udata)
4791 		return ERR_PTR(-ENOSYS);
4792 
4793 	min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4794 	if (udata->outlen && udata->outlen < min_resp_len)
4795 		return ERR_PTR(-EINVAL);
4796 
4797 	dev = to_mdev(pd->device);
4798 	switch (init_attr->wq_type) {
4799 	case IB_WQT_RQ:
4800 		rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4801 		if (!rwq)
4802 			return ERR_PTR(-ENOMEM);
4803 		err = prepare_user_rq(pd, init_attr, udata, rwq);
4804 		if (err)
4805 			goto err;
4806 		err = create_rq(rwq, pd, init_attr);
4807 		if (err)
4808 			goto err_user_rq;
4809 		break;
4810 	default:
4811 		mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4812 			    init_attr->wq_type);
4813 		return ERR_PTR(-EINVAL);
4814 	}
4815 
4816 	rwq->ibwq.wq_num = rwq->core_qp.qpn;
4817 	rwq->ibwq.state = IB_WQS_RESET;
4818 	if (udata->outlen) {
4819 		resp.response_length = offsetof(typeof(resp), response_length) +
4820 				sizeof(resp.response_length);
4821 		err = ib_copy_to_udata(udata, &resp, resp.response_length);
4822 		if (err)
4823 			goto err_copy;
4824 	}
4825 
4826 	rwq->core_qp.event = mlx5_ib_wq_event;
4827 	rwq->ibwq.event_handler = init_attr->event_handler;
4828 	return &rwq->ibwq;
4829 
4830 err_copy:
4831 	mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4832 err_user_rq:
4833 	destroy_user_rq(pd, rwq);
4834 err:
4835 	kfree(rwq);
4836 	return ERR_PTR(err);
4837 }
4838 
4839 int mlx5_ib_destroy_wq(struct ib_wq *wq)
4840 {
4841 	struct mlx5_ib_dev *dev = to_mdev(wq->device);
4842 	struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4843 
4844 	mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4845 	destroy_user_rq(wq->pd, rwq);
4846 	kfree(rwq);
4847 
4848 	return 0;
4849 }
4850 
4851 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
4852 						      struct ib_rwq_ind_table_init_attr *init_attr,
4853 						      struct ib_udata *udata)
4854 {
4855 	struct mlx5_ib_dev *dev = to_mdev(device);
4856 	struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
4857 	int sz = 1 << init_attr->log_ind_tbl_size;
4858 	struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
4859 	size_t min_resp_len;
4860 	int inlen;
4861 	int err;
4862 	int i;
4863 	u32 *in;
4864 	void *rqtc;
4865 
4866 	if (udata->inlen > 0 &&
4867 	    !ib_is_udata_cleared(udata, 0,
4868 				 udata->inlen))
4869 		return ERR_PTR(-EOPNOTSUPP);
4870 
4871 	if (init_attr->log_ind_tbl_size >
4872 	    MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
4873 		mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
4874 			    init_attr->log_ind_tbl_size,
4875 			    MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
4876 		return ERR_PTR(-EINVAL);
4877 	}
4878 
4879 	min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4880 	if (udata->outlen && udata->outlen < min_resp_len)
4881 		return ERR_PTR(-EINVAL);
4882 
4883 	rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
4884 	if (!rwq_ind_tbl)
4885 		return ERR_PTR(-ENOMEM);
4886 
4887 	inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
4888 	in = mlx5_vzalloc(inlen);
4889 	if (!in) {
4890 		err = -ENOMEM;
4891 		goto err;
4892 	}
4893 
4894 	rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
4895 
4896 	MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
4897 	MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
4898 
4899 	for (i = 0; i < sz; i++)
4900 		MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
4901 
4902 	err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
4903 	kvfree(in);
4904 
4905 	if (err)
4906 		goto err;
4907 
4908 	rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
4909 	if (udata->outlen) {
4910 		resp.response_length = offsetof(typeof(resp), response_length) +
4911 					sizeof(resp.response_length);
4912 		err = ib_copy_to_udata(udata, &resp, resp.response_length);
4913 		if (err)
4914 			goto err_copy;
4915 	}
4916 
4917 	return &rwq_ind_tbl->ib_rwq_ind_tbl;
4918 
4919 err_copy:
4920 	mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4921 err:
4922 	kfree(rwq_ind_tbl);
4923 	return ERR_PTR(err);
4924 }
4925 
4926 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4927 {
4928 	struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
4929 	struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
4930 
4931 	mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4932 
4933 	kfree(rwq_ind_tbl);
4934 	return 0;
4935 }
4936 
4937 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
4938 		      u32 wq_attr_mask, struct ib_udata *udata)
4939 {
4940 	struct mlx5_ib_dev *dev = to_mdev(wq->device);
4941 	struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4942 	struct mlx5_ib_modify_wq ucmd = {};
4943 	size_t required_cmd_sz;
4944 	int curr_wq_state;
4945 	int wq_state;
4946 	int inlen;
4947 	int err;
4948 	void *rqc;
4949 	void *in;
4950 
4951 	required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4952 	if (udata->inlen < required_cmd_sz)
4953 		return -EINVAL;
4954 
4955 	if (udata->inlen > sizeof(ucmd) &&
4956 	    !ib_is_udata_cleared(udata, sizeof(ucmd),
4957 				 udata->inlen - sizeof(ucmd)))
4958 		return -EOPNOTSUPP;
4959 
4960 	if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4961 		return -EFAULT;
4962 
4963 	if (ucmd.comp_mask || ucmd.reserved)
4964 		return -EOPNOTSUPP;
4965 
4966 	inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
4967 	in = mlx5_vzalloc(inlen);
4968 	if (!in)
4969 		return -ENOMEM;
4970 
4971 	rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
4972 
4973 	MLX5_SET(modify_rq_in, in, rqn, rwq->core_qp.qpn);
4974 	curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
4975 		wq_attr->curr_wq_state : wq->state;
4976 	wq_state = (wq_attr_mask & IB_WQ_STATE) ?
4977 		wq_attr->wq_state : curr_wq_state;
4978 	if (curr_wq_state == IB_WQS_ERR)
4979 		curr_wq_state = MLX5_RQC_STATE_ERR;
4980 	if (wq_state == IB_WQS_ERR)
4981 		wq_state = MLX5_RQC_STATE_ERR;
4982 	MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
4983 	MLX5_SET(rqc, rqc, state, wq_state);
4984 
4985 	err = mlx5_core_modify_rq(dev->mdev, in, inlen);
4986 	kvfree(in);
4987 	if (!err)
4988 		rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
4989 
4990 	return err;
4991 }
4992