1 /*- 2 * Copyright (c) 2013-2021, Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include "opt_rss.h" 29 #include "opt_ratelimit.h" 30 31 #include <linux/module.h> 32 #include <rdma/ib_umem.h> 33 #include <rdma/ib_cache.h> 34 #include <rdma/ib_user_verbs.h> 35 #include <rdma/uverbs_ioctl.h> 36 #include <dev/mlx5/mlx5_ib/mlx5_ib.h> 37 38 /* not supported currently */ 39 static int wq_signature; 40 41 enum { 42 MLX5_IB_ACK_REQ_FREQ = 8, 43 }; 44 45 enum { 46 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 47 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 48 MLX5_IB_LINK_TYPE_IB = 0, 49 MLX5_IB_LINK_TYPE_ETH = 1 50 }; 51 52 enum { 53 MLX5_IB_SQ_STRIDE = 6, 54 }; 55 56 static const u32 mlx5_ib_opcode[] = { 57 [IB_WR_SEND] = MLX5_OPCODE_SEND, 58 [IB_WR_LSO] = MLX5_OPCODE_LSO, 59 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 60 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 61 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 62 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 63 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 64 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 65 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 66 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 67 [IB_WR_REG_MR] = MLX5_OPCODE_UMR, 68 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 69 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 70 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 71 }; 72 73 struct mlx5_wqe_eth_pad { 74 u8 rsvd0[16]; 75 }; 76 77 enum raw_qp_set_mask_map { 78 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 79 }; 80 81 struct mlx5_modify_raw_qp_param { 82 u16 operation; 83 84 u32 set_mask; /* raw_qp_set_mask_map */ 85 u8 rq_q_ctr_id; 86 }; 87 88 static void get_cqs(enum ib_qp_type qp_type, 89 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 90 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 91 92 static int is_qp0(enum ib_qp_type qp_type) 93 { 94 return qp_type == IB_QPT_SMI; 95 } 96 97 static int is_sqp(enum ib_qp_type qp_type) 98 { 99 return is_qp0(qp_type) || is_qp1(qp_type); 100 } 101 102 static void *get_wqe(struct mlx5_ib_qp *qp, int offset) 103 { 104 return mlx5_buf_offset(&qp->buf, offset); 105 } 106 107 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n) 108 { 109 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 110 } 111 112 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n) 113 { 114 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE)); 115 } 116 117 /** 118 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space. 119 * 120 * @qp: QP to copy from. 121 * @send: copy from the send queue when non-zero, use the receive queue 122 * otherwise. 123 * @wqe_index: index to start copying from. For send work queues, the 124 * wqe_index is in units of MLX5_SEND_WQE_BB. 125 * For receive work queue, it is the number of work queue 126 * element in the queue. 127 * @buffer: destination buffer. 128 * @length: maximum number of bytes to copy. 129 * 130 * Copies at least a single WQE, but may copy more data. 131 * 132 * Return: the number of bytes copied, or an error code. 133 */ 134 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 135 void *buffer, u32 length, 136 struct mlx5_ib_qp_base *base) 137 { 138 struct ib_device *ibdev = qp->ibqp.device; 139 struct mlx5_ib_dev *dev = to_mdev(ibdev); 140 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq; 141 size_t offset; 142 size_t wq_end; 143 struct ib_umem *umem = base->ubuffer.umem; 144 u32 first_copy_length; 145 int wqe_length; 146 int ret; 147 148 if (wq->wqe_cnt == 0) { 149 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n", 150 qp->ibqp.qp_type); 151 return -EINVAL; 152 } 153 154 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift); 155 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift); 156 157 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg)) 158 return -EINVAL; 159 160 if (offset > umem->length || 161 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length)) 162 return -EINVAL; 163 164 first_copy_length = min_t(u32, offset + length, wq_end) - offset; 165 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length); 166 if (ret) 167 return ret; 168 169 if (send) { 170 struct mlx5_wqe_ctrl_seg *ctrl = buffer; 171 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 172 173 wqe_length = ds * MLX5_WQE_DS_UNITS; 174 } else { 175 wqe_length = 1 << wq->wqe_shift; 176 } 177 178 if (wqe_length <= first_copy_length) 179 return first_copy_length; 180 181 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset, 182 wqe_length - first_copy_length); 183 if (ret) 184 return ret; 185 186 return wqe_length; 187 } 188 189 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 190 { 191 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 192 struct ib_event event; 193 194 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 195 /* This event is only valid for trans_qps */ 196 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 197 } 198 199 if (ibqp->event_handler) { 200 event.device = ibqp->device; 201 event.element.qp = ibqp; 202 switch (type) { 203 case MLX5_EVENT_TYPE_PATH_MIG: 204 event.event = IB_EVENT_PATH_MIG; 205 break; 206 case MLX5_EVENT_TYPE_COMM_EST: 207 event.event = IB_EVENT_COMM_EST; 208 break; 209 case MLX5_EVENT_TYPE_SQ_DRAINED: 210 event.event = IB_EVENT_SQ_DRAINED; 211 break; 212 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 213 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 214 break; 215 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 216 event.event = IB_EVENT_QP_FATAL; 217 break; 218 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 219 event.event = IB_EVENT_PATH_MIG_ERR; 220 break; 221 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 222 event.event = IB_EVENT_QP_REQ_ERR; 223 break; 224 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 225 event.event = IB_EVENT_QP_ACCESS_ERR; 226 break; 227 default: 228 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 229 return; 230 } 231 232 ibqp->event_handler(&event, ibqp->qp_context); 233 } 234 } 235 236 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 237 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 238 { 239 int wqe_size; 240 int wq_size; 241 242 /* Sanity check RQ size before proceeding */ 243 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 244 return -EINVAL; 245 246 if (!has_rq) { 247 qp->rq.max_gs = 0; 248 qp->rq.wqe_cnt = 0; 249 qp->rq.wqe_shift = 0; 250 cap->max_recv_wr = 0; 251 cap->max_recv_sge = 0; 252 } else { 253 if (ucmd) { 254 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 255 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 256 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 257 qp->rq.max_post = qp->rq.wqe_cnt; 258 } else { 259 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 260 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 261 wqe_size = roundup_pow_of_two(wqe_size); 262 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 263 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 264 qp->rq.wqe_cnt = wq_size / wqe_size; 265 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 266 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 267 wqe_size, 268 MLX5_CAP_GEN(dev->mdev, 269 max_wqe_sz_rq)); 270 return -EINVAL; 271 } 272 qp->rq.wqe_shift = ilog2(wqe_size); 273 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 274 qp->rq.max_post = qp->rq.wqe_cnt; 275 } 276 } 277 278 return 0; 279 } 280 281 static int sq_overhead(struct ib_qp_init_attr *attr) 282 { 283 int size = 0; 284 285 switch (attr->qp_type) { 286 case IB_QPT_XRC_INI: 287 size += sizeof(struct mlx5_wqe_xrc_seg); 288 /* fall through */ 289 case IB_QPT_RC: 290 size += sizeof(struct mlx5_wqe_ctrl_seg) + 291 max(sizeof(struct mlx5_wqe_atomic_seg) + 292 sizeof(struct mlx5_wqe_raddr_seg), 293 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 294 sizeof(struct mlx5_mkey_seg)); 295 break; 296 297 case IB_QPT_XRC_TGT: 298 return 0; 299 300 case IB_QPT_UC: 301 size += sizeof(struct mlx5_wqe_ctrl_seg) + 302 max(sizeof(struct mlx5_wqe_raddr_seg), 303 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 304 sizeof(struct mlx5_mkey_seg)); 305 break; 306 307 case IB_QPT_UD: 308 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 309 size += sizeof(struct mlx5_wqe_eth_pad) + 310 sizeof(struct mlx5_wqe_eth_seg); 311 /* fall through */ 312 case IB_QPT_SMI: 313 case MLX5_IB_QPT_HW_GSI: 314 size += sizeof(struct mlx5_wqe_ctrl_seg) + 315 sizeof(struct mlx5_wqe_datagram_seg); 316 break; 317 318 case MLX5_IB_QPT_REG_UMR: 319 size += sizeof(struct mlx5_wqe_ctrl_seg) + 320 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 321 sizeof(struct mlx5_mkey_seg); 322 break; 323 324 default: 325 return -EINVAL; 326 } 327 328 return size; 329 } 330 331 static int calc_send_wqe(struct ib_qp_init_attr *attr) 332 { 333 int inl_size = 0; 334 int size; 335 336 size = sq_overhead(attr); 337 if (size < 0) 338 return size; 339 340 if (attr->cap.max_inline_data) { 341 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 342 attr->cap.max_inline_data; 343 } 344 345 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 346 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && 347 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 348 return MLX5_SIG_WQE_SIZE; 349 else 350 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 351 } 352 353 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 354 { 355 int max_sge; 356 357 if (attr->qp_type == IB_QPT_RC) 358 max_sge = (min_t(int, wqe_size, 512) - 359 sizeof(struct mlx5_wqe_ctrl_seg) - 360 sizeof(struct mlx5_wqe_raddr_seg)) / 361 sizeof(struct mlx5_wqe_data_seg); 362 else if (attr->qp_type == IB_QPT_XRC_INI) 363 max_sge = (min_t(int, wqe_size, 512) - 364 sizeof(struct mlx5_wqe_ctrl_seg) - 365 sizeof(struct mlx5_wqe_xrc_seg) - 366 sizeof(struct mlx5_wqe_raddr_seg)) / 367 sizeof(struct mlx5_wqe_data_seg); 368 else 369 max_sge = (wqe_size - sq_overhead(attr)) / 370 sizeof(struct mlx5_wqe_data_seg); 371 372 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 373 sizeof(struct mlx5_wqe_data_seg)); 374 } 375 376 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 377 struct mlx5_ib_qp *qp) 378 { 379 int wqe_size; 380 int wq_size; 381 382 if (!attr->cap.max_send_wr) 383 return 0; 384 385 wqe_size = calc_send_wqe(attr); 386 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 387 if (wqe_size < 0) 388 return wqe_size; 389 390 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 391 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 392 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 393 return -EINVAL; 394 } 395 396 qp->max_inline_data = wqe_size - sq_overhead(attr) - 397 sizeof(struct mlx5_wqe_inline_seg); 398 attr->cap.max_inline_data = qp->max_inline_data; 399 400 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) 401 qp->signature_en = true; 402 403 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 404 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 405 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 406 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n", 407 qp->sq.wqe_cnt, 408 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 409 return -ENOMEM; 410 } 411 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 412 qp->sq.max_gs = get_send_sge(attr, wqe_size); 413 if (qp->sq.max_gs < attr->cap.max_send_sge) 414 return -ENOMEM; 415 416 attr->cap.max_send_sge = qp->sq.max_gs; 417 qp->sq.max_post = wq_size / wqe_size; 418 attr->cap.max_send_wr = qp->sq.max_post; 419 420 return wq_size; 421 } 422 423 static int set_user_buf_size(struct mlx5_ib_dev *dev, 424 struct mlx5_ib_qp *qp, 425 struct mlx5_ib_create_qp *ucmd, 426 struct mlx5_ib_qp_base *base, 427 struct ib_qp_init_attr *attr) 428 { 429 int desc_sz = 1 << qp->sq.wqe_shift; 430 431 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 432 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 433 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 434 return -EINVAL; 435 } 436 437 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) { 438 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n", 439 ucmd->sq_wqe_count, ucmd->sq_wqe_count); 440 return -EINVAL; 441 } 442 443 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 444 445 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 446 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 447 qp->sq.wqe_cnt, 448 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 449 return -EINVAL; 450 } 451 452 if (attr->qp_type == IB_QPT_RAW_PACKET) { 453 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 454 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 455 } else { 456 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 457 (qp->sq.wqe_cnt << 6); 458 } 459 460 return 0; 461 } 462 463 static int qp_has_rq(struct ib_qp_init_attr *attr) 464 { 465 if (attr->qp_type == IB_QPT_XRC_INI || 466 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 467 attr->qp_type == MLX5_IB_QPT_REG_UMR || 468 !attr->cap.max_recv_wr) 469 return 0; 470 471 return 1; 472 } 473 474 enum { 475 /* this is the first blue flame register in the array of bfregs assigned 476 * to a processes. Since we do not use it for blue flame but rather 477 * regular 64 bit doorbells, we do not need a lock for maintaiing 478 * "odd/even" order 479 */ 480 NUM_NON_BLUE_FLAME_BFREGS = 1, 481 }; 482 483 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 484 { 485 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; 486 } 487 488 static int num_med_bfreg(struct mlx5_ib_dev *dev, 489 struct mlx5_bfreg_info *bfregi) 490 { 491 int n; 492 493 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 494 NUM_NON_BLUE_FLAME_BFREGS; 495 496 return n >= 0 ? n : 0; 497 } 498 499 static int first_med_bfreg(struct mlx5_ib_dev *dev, 500 struct mlx5_bfreg_info *bfregi) 501 { 502 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; 503 } 504 505 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 506 struct mlx5_bfreg_info *bfregi) 507 { 508 int med; 509 510 med = num_med_bfreg(dev, bfregi); 511 return ++med; 512 } 513 514 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 515 struct mlx5_bfreg_info *bfregi) 516 { 517 int i; 518 519 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 520 if (!bfregi->count[i]) { 521 bfregi->count[i]++; 522 return i; 523 } 524 } 525 526 return -ENOMEM; 527 } 528 529 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 530 struct mlx5_bfreg_info *bfregi) 531 { 532 int minidx = first_med_bfreg(dev, bfregi); 533 int i; 534 535 if (minidx < 0) 536 return minidx; 537 538 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { 539 if (bfregi->count[i] < bfregi->count[minidx]) 540 minidx = i; 541 if (!bfregi->count[minidx]) 542 break; 543 } 544 545 bfregi->count[minidx]++; 546 return minidx; 547 } 548 549 static int alloc_bfreg(struct mlx5_ib_dev *dev, 550 struct mlx5_bfreg_info *bfregi) 551 { 552 int bfregn = -ENOMEM; 553 554 if (bfregi->lib_uar_dyn) 555 return -EINVAL; 556 557 mutex_lock(&bfregi->lock); 558 if (bfregi->ver >= 2) { 559 bfregn = alloc_high_class_bfreg(dev, bfregi); 560 if (bfregn < 0) 561 bfregn = alloc_med_class_bfreg(dev, bfregi); 562 } 563 564 if (bfregn < 0) { 565 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 566 bfregn = 0; 567 bfregi->count[bfregn]++; 568 } 569 mutex_unlock(&bfregi->lock); 570 571 return bfregn; 572 } 573 574 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 575 { 576 mutex_lock(&bfregi->lock); 577 bfregi->count[bfregn]--; 578 mutex_unlock(&bfregi->lock); 579 } 580 581 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 582 { 583 switch (state) { 584 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 585 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 586 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 587 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 588 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 589 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 590 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 591 default: return -1; 592 } 593 } 594 595 static int to_mlx5_st(enum ib_qp_type type) 596 { 597 switch (type) { 598 case IB_QPT_RC: return MLX5_QP_ST_RC; 599 case IB_QPT_UC: return MLX5_QP_ST_UC; 600 case IB_QPT_UD: return MLX5_QP_ST_UD; 601 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 602 case IB_QPT_XRC_INI: 603 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 604 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 605 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 606 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 607 case IB_QPT_RAW_PACKET: 608 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 609 case IB_QPT_MAX: 610 default: return -EINVAL; 611 } 612 } 613 614 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 615 struct mlx5_ib_cq *recv_cq); 616 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 617 struct mlx5_ib_cq *recv_cq); 618 619 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 620 struct mlx5_bfreg_info *bfregi, u32 bfregn, 621 bool dyn_bfreg) 622 { 623 unsigned int bfregs_per_sys_page; 624 u32 index_of_sys_page; 625 u32 offset; 626 627 if (bfregi->lib_uar_dyn) 628 return -EINVAL; 629 630 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 631 MLX5_NON_FP_BFREGS_PER_UAR; 632 index_of_sys_page = bfregn / bfregs_per_sys_page; 633 634 if (dyn_bfreg) { 635 index_of_sys_page += bfregi->num_static_sys_pages; 636 637 if (index_of_sys_page >= bfregi->num_sys_pages) 638 return -EINVAL; 639 640 if (bfregn > bfregi->num_dyn_bfregs || 641 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 642 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 643 return -EINVAL; 644 } 645 } 646 647 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 648 return bfregi->sys_pages[index_of_sys_page] + offset; 649 } 650 651 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, 652 struct ib_pd *pd, 653 unsigned long addr, size_t size, 654 struct ib_umem **umem, 655 int *npages, int *page_shift, int *ncont, 656 u32 *offset) 657 { 658 int err; 659 660 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0); 661 if (IS_ERR(*umem)) { 662 mlx5_ib_dbg(dev, "umem_get failed\n"); 663 return PTR_ERR(*umem); 664 } 665 666 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL); 667 668 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 669 if (err) { 670 mlx5_ib_warn(dev, "bad offset\n"); 671 goto err_umem; 672 } 673 674 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", 675 addr, size, *npages, *page_shift, *ncont, *offset); 676 677 return 0; 678 679 err_umem: 680 ib_umem_release(*umem); 681 *umem = NULL; 682 683 return err; 684 } 685 686 static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq, 687 struct ib_udata *udata) 688 { 689 struct mlx5_ib_ucontext *context = 690 rdma_udata_to_drv_context( 691 udata, 692 struct mlx5_ib_ucontext, 693 ibucontext); 694 695 mlx5_ib_db_unmap_user(context, &rwq->db); 696 if (rwq->umem) 697 ib_umem_release(rwq->umem); 698 } 699 700 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 701 struct mlx5_ib_rwq *rwq, 702 struct mlx5_ib_create_wq *ucmd) 703 { 704 struct mlx5_ib_ucontext *context; 705 int page_shift = 0; 706 int npages; 707 u32 offset = 0; 708 int ncont = 0; 709 int err; 710 711 if (!ucmd->buf_addr) 712 return -EINVAL; 713 714 context = to_mucontext(pd->uobject->context); 715 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr, 716 rwq->buf_size, 0, 0); 717 if (IS_ERR(rwq->umem)) { 718 mlx5_ib_dbg(dev, "umem_get failed\n"); 719 err = PTR_ERR(rwq->umem); 720 return err; 721 } 722 723 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift, 724 &ncont, NULL); 725 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, 726 &rwq->rq_page_offset); 727 if (err) { 728 mlx5_ib_warn(dev, "bad offset\n"); 729 goto err_umem; 730 } 731 732 rwq->rq_num_pas = ncont; 733 rwq->page_shift = page_shift; 734 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; 735 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 736 737 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", 738 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 739 npages, page_shift, ncont, offset); 740 741 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db); 742 if (err) { 743 mlx5_ib_dbg(dev, "map failed\n"); 744 goto err_umem; 745 } 746 747 rwq->create_type = MLX5_WQ_USER; 748 return 0; 749 750 err_umem: 751 ib_umem_release(rwq->umem); 752 return err; 753 } 754 755 static int adjust_bfregn(struct mlx5_ib_dev *dev, 756 struct mlx5_bfreg_info *bfregi, int bfregn) 757 { 758 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 759 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 760 } 761 762 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 763 struct mlx5_ib_qp *qp, struct ib_udata *udata, 764 struct ib_qp_init_attr *attr, 765 u32 **in, 766 struct mlx5_ib_create_qp_resp *resp, int *inlen, 767 struct mlx5_ib_qp_base *base) 768 { 769 struct mlx5_ib_ucontext *context; 770 struct mlx5_ib_create_qp ucmd; 771 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 772 int page_shift = 0; 773 int uar_index = 0; 774 int npages; 775 u32 offset = 0; 776 int bfregn; 777 int ncont = 0; 778 __be64 *pas; 779 void *qpc; 780 int err; 781 u16 uid; 782 u32 uar_flags; 783 784 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 785 if (err) { 786 mlx5_ib_dbg(dev, "copy failed\n"); 787 return err; 788 } 789 790 context = to_mucontext(pd->uobject->context); 791 uar_flags = ucmd.flags & (MLX5_QP_FLAG_UAR_PAGE_INDEX | 792 MLX5_QP_FLAG_BFREG_INDEX); 793 switch (uar_flags) { 794 case MLX5_QP_FLAG_UAR_PAGE_INDEX: 795 uar_index = ucmd.bfreg_index; 796 bfregn = MLX5_IB_INVALID_BFREG; 797 break; 798 case MLX5_QP_FLAG_BFREG_INDEX: 799 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 800 ucmd.bfreg_index, true); 801 if (uar_index < 0) 802 return uar_index; 803 bfregn = MLX5_IB_INVALID_BFREG; 804 break; 805 case 0: 806 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 807 return -EINVAL; 808 bfregn = alloc_bfreg(dev, &context->bfregi); 809 if (bfregn < 0) 810 return bfregn; 811 break; 812 default: 813 return -EINVAL; 814 } 815 816 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 817 if (bfregn != MLX5_IB_INVALID_BFREG) 818 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 819 false); 820 821 qp->rq.offset = 0; 822 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 823 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 824 825 err = set_user_buf_size(dev, qp, &ucmd, base, attr); 826 if (err) 827 goto err_bfreg; 828 829 if (ucmd.buf_addr && ubuffer->buf_size) { 830 ubuffer->buf_addr = ucmd.buf_addr; 831 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, 832 ubuffer->buf_size, 833 &ubuffer->umem, &npages, &page_shift, 834 &ncont, &offset); 835 if (err) 836 goto err_bfreg; 837 } else { 838 ubuffer->umem = NULL; 839 } 840 841 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 842 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 843 *in = mlx5_vzalloc(*inlen); 844 if (!*in) { 845 err = -ENOMEM; 846 goto err_umem; 847 } 848 849 uid = (attr->qp_type != IB_QPT_XRC_TGT && 850 attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0; 851 MLX5_SET(create_qp_in, *in, uid, uid); 852 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 853 if (ubuffer->umem) 854 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0); 855 856 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 857 858 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 859 MLX5_SET(qpc, qpc, page_offset, offset); 860 861 MLX5_SET(qpc, qpc, uar_page, uar_index); 862 if (bfregn != MLX5_IB_INVALID_BFREG) 863 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 864 else 865 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 866 qp->bfregn = bfregn; 867 868 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db); 869 if (err) { 870 mlx5_ib_dbg(dev, "map failed\n"); 871 goto err_free; 872 } 873 874 err = ib_copy_to_udata(udata, resp, sizeof(*resp)); 875 if (err) { 876 mlx5_ib_dbg(dev, "copy failed\n"); 877 goto err_unmap; 878 } 879 qp->create_type = MLX5_QP_USER; 880 881 return 0; 882 883 err_unmap: 884 mlx5_ib_db_unmap_user(context, &qp->db); 885 886 err_free: 887 kvfree(*in); 888 889 err_umem: 890 if (ubuffer->umem) 891 ib_umem_release(ubuffer->umem); 892 893 err_bfreg: 894 if (bfregn != MLX5_IB_INVALID_BFREG) 895 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 896 return err; 897 } 898 899 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd, struct mlx5_ib_qp *qp, 900 struct mlx5_ib_qp_base *base, 901 struct ib_udata *udata) 902 { 903 struct mlx5_ib_ucontext *context = 904 rdma_udata_to_drv_context( 905 udata, 906 struct mlx5_ib_ucontext, 907 ibucontext); 908 909 mlx5_ib_db_unmap_user(context, &qp->db); 910 if (base->ubuffer.umem) 911 ib_umem_release(base->ubuffer.umem); 912 913 /* 914 * Free only the BFREGs which are handled by the kernel. 915 * BFREGs of UARs allocated dynamically are handled by user. 916 */ 917 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 918 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 919 } 920 921 static int create_kernel_qp(struct mlx5_ib_dev *dev, 922 struct ib_qp_init_attr *init_attr, 923 struct mlx5_ib_qp *qp, 924 u32 **in, int *inlen, 925 struct mlx5_ib_qp_base *base) 926 { 927 int uar_index; 928 void *qpc; 929 int err; 930 931 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | 932 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK | 933 IB_QP_CREATE_IPOIB_UD_LSO | 934 MLX5_IB_QP_CREATE_SQPN_QP1 | 935 MLX5_IB_QP_CREATE_WC_TEST)) 936 return -EINVAL; 937 938 spin_lock_init(&qp->bf.lock32); 939 940 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 941 qp->bf.bfreg = &dev->fp_bfreg; 942 else if (init_attr->create_flags & MLX5_IB_QP_CREATE_WC_TEST) 943 qp->bf.bfreg = &dev->wc_bfreg; 944 else 945 qp->bf.bfreg = &dev->bfreg; 946 947 /* We need to divide by two since each register is comprised of 948 * two buffers of identical size, namely odd and even 949 */ 950 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 951 uar_index = qp->bf.bfreg->index; 952 953 err = calc_sq_size(dev, init_attr, qp); 954 if (err < 0) { 955 mlx5_ib_dbg(dev, "err %d\n", err); 956 return err; 957 } 958 959 qp->rq.offset = 0; 960 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 961 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 962 963 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, 964 2 * PAGE_SIZE, &qp->buf); 965 if (err) { 966 mlx5_ib_dbg(dev, "err %d\n", err); 967 return err; 968 } 969 970 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt); 971 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 972 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 973 *in = mlx5_vzalloc(*inlen); 974 if (!*in) { 975 err = -ENOMEM; 976 goto err_buf; 977 } 978 979 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 980 MLX5_SET(qpc, qpc, uar_page, uar_index); 981 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev)); 982 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 983 984 /* Set "fast registration enabled" for all kernel QPs */ 985 MLX5_SET(qpc, qpc, fre, 1); 986 MLX5_SET(qpc, qpc, rlky, 1); 987 988 if (init_attr->create_flags & MLX5_IB_QP_CREATE_SQPN_QP1) { 989 MLX5_SET(qpc, qpc, deth_sqpn, 1); 990 qp->flags |= MLX5_IB_QP_SQPN_QP1; 991 } 992 993 mlx5_fill_page_array(&qp->buf, 994 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas)); 995 996 err = mlx5_db_alloc(dev->mdev, &qp->db); 997 if (err) { 998 mlx5_ib_dbg(dev, "err %d\n", err); 999 goto err_free; 1000 } 1001 1002 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL); 1003 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL); 1004 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL); 1005 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL); 1006 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1007 1008 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1009 !qp->sq.w_list || !qp->sq.wqe_head) { 1010 err = -ENOMEM; 1011 goto err_wrid; 1012 } 1013 qp->create_type = MLX5_QP_KERNEL; 1014 1015 return 0; 1016 1017 err_wrid: 1018 kfree(qp->sq.wqe_head); 1019 kfree(qp->sq.w_list); 1020 kfree(qp->sq.wrid); 1021 kfree(qp->sq.wr_data); 1022 kfree(qp->rq.wrid); 1023 mlx5_db_free(dev->mdev, &qp->db); 1024 1025 err_free: 1026 kvfree(*in); 1027 1028 err_buf: 1029 mlx5_buf_free(dev->mdev, &qp->buf); 1030 return err; 1031 } 1032 1033 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1034 { 1035 kfree(qp->sq.wqe_head); 1036 kfree(qp->sq.w_list); 1037 kfree(qp->sq.wrid); 1038 kfree(qp->sq.wr_data); 1039 kfree(qp->rq.wrid); 1040 mlx5_db_free(dev->mdev, &qp->db); 1041 mlx5_buf_free(dev->mdev, &qp->buf); 1042 } 1043 1044 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1045 { 1046 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 1047 (attr->qp_type == IB_QPT_XRC_INI)) 1048 return MLX5_SRQ_RQ; 1049 else if (!qp->has_rq) 1050 return MLX5_ZERO_LEN_RQ; 1051 else 1052 return MLX5_NON_ZERO_RQ; 1053 } 1054 1055 static int is_connected(enum ib_qp_type qp_type) 1056 { 1057 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC) 1058 return 1; 1059 1060 return 0; 1061 } 1062 1063 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1064 struct mlx5_ib_sq *sq, u32 tdn, 1065 struct ib_pd *pd) 1066 { 1067 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1068 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1069 1070 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid); 1071 MLX5_SET(tisc, tisc, transport_domain, tdn); 1072 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn); 1073 } 1074 1075 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1076 struct mlx5_ib_sq *sq, struct ib_pd *pd) 1077 { 1078 mlx5_core_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid); 1079 } 1080 1081 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1082 struct mlx5_ib_sq *sq, void *qpin, 1083 struct ib_pd *pd) 1084 { 1085 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1086 __be64 *pas; 1087 void *in; 1088 void *sqc; 1089 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1090 void *wq; 1091 int inlen; 1092 int err; 1093 int page_shift = 0; 1094 int npages; 1095 int ncont = 0; 1096 u32 offset = 0; 1097 u8 ts_format; 1098 1099 ts_format = mlx5_get_sq_default_ts(dev->mdev); 1100 1101 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size, 1102 &sq->ubuffer.umem, &npages, &page_shift, 1103 &ncont, &offset); 1104 if (err) 1105 return err; 1106 1107 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; 1108 in = mlx5_vzalloc(inlen); 1109 if (!in) { 1110 err = -ENOMEM; 1111 goto err_umem; 1112 } 1113 1114 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid); 1115 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1116 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1117 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1118 MLX5_SET(sqc, sqc, ts_format, ts_format); 1119 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1120 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1121 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1122 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1123 1124 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1125 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1126 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1127 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1128 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1129 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1130 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1131 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1132 MLX5_SET(wq, wq, page_offset, offset); 1133 1134 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1135 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); 1136 1137 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); 1138 1139 kvfree(in); 1140 1141 if (err) 1142 goto err_umem; 1143 1144 return 0; 1145 1146 err_umem: 1147 ib_umem_release(sq->ubuffer.umem); 1148 sq->ubuffer.umem = NULL; 1149 1150 return err; 1151 } 1152 1153 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1154 struct mlx5_ib_sq *sq) 1155 { 1156 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1157 ib_umem_release(sq->ubuffer.umem); 1158 } 1159 1160 static int get_rq_pas_size(void *qpc) 1161 { 1162 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; 1163 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); 1164 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); 1165 u32 page_offset = MLX5_GET(qpc, qpc, page_offset); 1166 u32 po_quanta = 1 << (log_page_size - 6); 1167 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); 1168 u32 page_size = 1 << log_page_size; 1169 u32 rq_sz_po = rq_sz + (page_offset * po_quanta); 1170 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; 1171 1172 return rq_num_pas * sizeof(u64); 1173 } 1174 1175 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1176 struct mlx5_ib_rq *rq, void *qpin, 1177 struct ib_pd *pd) 1178 { 1179 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1180 __be64 *pas; 1181 __be64 *qp_pas; 1182 void *in; 1183 void *rqc; 1184 void *wq; 1185 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1186 int inlen; 1187 int err; 1188 u32 rq_pas_size = get_rq_pas_size(qpc); 1189 u8 ts_format; 1190 1191 ts_format = mlx5_get_rq_default_ts(dev->mdev); 1192 1193 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; 1194 in = mlx5_vzalloc(inlen); 1195 if (!in) 1196 return -ENOMEM; 1197 1198 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 1199 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1200 MLX5_SET(rqc, rqc, vlan_strip_disable, 1); 1201 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE); 1202 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1203 MLX5_SET(rqc, rqc, ts_format, ts_format); 1204 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1205 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1206 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1207 1208 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS) 1209 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1210 1211 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1212 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1213 MLX5_SET(wq, wq, end_padding_mode, 1214 MLX5_GET(qpc, qpc, end_padding_mode)); 1215 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1216 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1217 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1218 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1219 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); 1220 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1221 1222 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1223 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); 1224 memcpy(pas, qp_pas, rq_pas_size); 1225 1226 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); 1227 1228 kvfree(in); 1229 1230 return err; 1231 } 1232 1233 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1234 struct mlx5_ib_rq *rq) 1235 { 1236 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); 1237 } 1238 1239 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1240 struct mlx5_ib_rq *rq, u32 tdn, 1241 struct ib_pd *pd) 1242 { 1243 u32 *in; 1244 void *tirc; 1245 int inlen; 1246 int err; 1247 1248 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1249 in = mlx5_vzalloc(inlen); 1250 if (!in) 1251 return -ENOMEM; 1252 1253 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1254 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context); 1255 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1256 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1257 MLX5_SET(tirc, tirc, transport_domain, tdn); 1258 1259 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn); 1260 1261 kvfree(in); 1262 1263 return err; 1264 } 1265 1266 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1267 struct mlx5_ib_rq *rq, 1268 struct ib_pd *pd) 1269 { 1270 mlx5_core_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid); 1271 } 1272 1273 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1274 u32 *in, 1275 struct ib_pd *pd) 1276 { 1277 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1278 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1279 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1280 struct ib_uobject *uobj = pd->uobject; 1281 struct ib_ucontext *ucontext = uobj->context; 1282 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1283 int err; 1284 u32 tdn = mucontext->tdn; 1285 1286 if (qp->sq.wqe_cnt) { 1287 err = create_raw_packet_qp_tis(dev, sq, tdn, pd); 1288 if (err) 1289 return err; 1290 1291 err = create_raw_packet_qp_sq(dev, sq, in, pd); 1292 if (err) 1293 goto err_destroy_tis; 1294 1295 sq->base.container_mibqp = qp; 1296 } 1297 1298 if (qp->rq.wqe_cnt) { 1299 rq->base.container_mibqp = qp; 1300 1301 err = create_raw_packet_qp_rq(dev, rq, in, pd); 1302 if (err) 1303 goto err_destroy_sq; 1304 1305 1306 err = create_raw_packet_qp_tir(dev, rq, tdn, pd); 1307 if (err) 1308 goto err_destroy_rq; 1309 } 1310 1311 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1312 rq->base.mqp.qpn; 1313 1314 return 0; 1315 1316 err_destroy_rq: 1317 destroy_raw_packet_qp_rq(dev, rq); 1318 err_destroy_sq: 1319 if (!qp->sq.wqe_cnt) 1320 return err; 1321 destroy_raw_packet_qp_sq(dev, sq); 1322 err_destroy_tis: 1323 destroy_raw_packet_qp_tis(dev, sq, pd); 1324 1325 return err; 1326 } 1327 1328 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1329 struct mlx5_ib_qp *qp) 1330 { 1331 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1332 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1333 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1334 1335 if (qp->rq.wqe_cnt) { 1336 destroy_raw_packet_qp_tir(dev, rq, qp->ibqp.pd); 1337 destroy_raw_packet_qp_rq(dev, rq); 1338 } 1339 1340 if (qp->sq.wqe_cnt) { 1341 destroy_raw_packet_qp_sq(dev, sq); 1342 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd); 1343 } 1344 } 1345 1346 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1347 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1348 { 1349 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1350 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1351 1352 sq->sq = &qp->sq; 1353 rq->rq = &qp->rq; 1354 sq->doorbell = &qp->db; 1355 rq->doorbell = &qp->db; 1356 } 1357 1358 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1359 { 1360 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1361 to_mpd(qp->ibqp.pd)->uid); 1362 } 1363 1364 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1365 struct ib_pd *pd, 1366 struct ib_qp_init_attr *init_attr, 1367 struct ib_udata *udata) 1368 { 1369 struct ib_uobject *uobj = pd->uobject; 1370 struct ib_ucontext *ucontext = uobj->context; 1371 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1372 struct mlx5_ib_create_qp_resp resp = {}; 1373 int inlen; 1374 int err; 1375 u32 *in; 1376 void *tirc; 1377 void *hfso; 1378 u32 selected_fields = 0; 1379 size_t min_resp_len; 1380 u32 tdn = mucontext->tdn; 1381 struct mlx5_ib_create_qp_rss ucmd = {}; 1382 size_t required_cmd_sz; 1383 1384 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1385 return -EOPNOTSUPP; 1386 1387 if (init_attr->create_flags || init_attr->send_cq) 1388 return -EINVAL; 1389 1390 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index); 1391 if (udata->outlen < min_resp_len) 1392 return -EINVAL; 1393 1394 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1); 1395 if (udata->inlen < required_cmd_sz) { 1396 mlx5_ib_dbg(dev, "invalid inlen\n"); 1397 return -EINVAL; 1398 } 1399 1400 if (udata->inlen > sizeof(ucmd) && 1401 !ib_is_udata_cleared(udata, sizeof(ucmd), 1402 udata->inlen - sizeof(ucmd))) { 1403 mlx5_ib_dbg(dev, "inlen is not supported\n"); 1404 return -EOPNOTSUPP; 1405 } 1406 1407 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 1408 mlx5_ib_dbg(dev, "copy failed\n"); 1409 return -EFAULT; 1410 } 1411 1412 if (ucmd.comp_mask) { 1413 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1414 return -EOPNOTSUPP; 1415 } 1416 1417 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) { 1418 mlx5_ib_dbg(dev, "invalid reserved\n"); 1419 return -EOPNOTSUPP; 1420 } 1421 1422 err = ib_copy_to_udata(udata, &resp, min_resp_len); 1423 if (err) { 1424 mlx5_ib_dbg(dev, "copy failed\n"); 1425 return -EINVAL; 1426 } 1427 1428 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1429 in = mlx5_vzalloc(inlen); 1430 if (!in) 1431 return -ENOMEM; 1432 1433 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1434 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context); 1435 MLX5_SET(tirc, tirc, disp_type, 1436 MLX5_TIRC_DISP_TYPE_INDIRECT); 1437 MLX5_SET(tirc, tirc, indirect_table, 1438 init_attr->rwq_ind_tbl->ind_tbl_num); 1439 MLX5_SET(tirc, tirc, transport_domain, tdn); 1440 1441 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1442 switch (ucmd.rx_hash_function) { 1443 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1444 { 1445 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1446 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1447 1448 if (len != ucmd.rx_key_len) { 1449 err = -EINVAL; 1450 goto err; 1451 } 1452 1453 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FUNC_TOEPLITZ); 1454 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 1455 memcpy(rss_key, ucmd.rx_hash_key, len); 1456 break; 1457 } 1458 default: 1459 err = -EOPNOTSUPP; 1460 goto err; 1461 } 1462 1463 if (!ucmd.rx_hash_fields_mask) { 1464 /* special case when this TIR serves as steering entry without hashing */ 1465 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1466 goto create_tir; 1467 err = -EINVAL; 1468 goto err; 1469 } 1470 1471 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1472 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1473 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1474 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1475 err = -EINVAL; 1476 goto err; 1477 } 1478 1479 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1480 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1481 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1482 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1483 MLX5_L3_PROT_TYPE_IPV4); 1484 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1485 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1486 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1487 MLX5_L3_PROT_TYPE_IPV6); 1488 1489 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1490 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) && 1491 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1492 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) { 1493 err = -EINVAL; 1494 goto err; 1495 } 1496 1497 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1498 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1499 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1500 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1501 MLX5_L4_PROT_TYPE_TCP); 1502 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1503 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1504 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1505 MLX5_L4_PROT_TYPE_UDP); 1506 1507 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1508 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1509 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1510 1511 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1512 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1513 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1514 1515 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1516 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1517 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1518 1519 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1520 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1521 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1522 1523 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1524 1525 create_tir: 1526 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn); 1527 1528 if (err) 1529 goto err; 1530 1531 kvfree(in); 1532 /* qpn is reserved for that QP */ 1533 qp->trans_qp.base.mqp.qpn = 0; 1534 qp->flags |= MLX5_IB_QP_RSS; 1535 return 0; 1536 1537 err: 1538 kvfree(in); 1539 return err; 1540 } 1541 1542 static int atomic_size_to_mode(int size_mask) 1543 { 1544 /* driver does not support atomic_size > 256B 1545 * and does not know how to translate bigger sizes 1546 */ 1547 int supported_size_mask = size_mask & 0x1ff; 1548 int log_max_size; 1549 1550 if (!supported_size_mask) 1551 return -EOPNOTSUPP; 1552 1553 log_max_size = __fls(supported_size_mask); 1554 1555 if (log_max_size > 3) 1556 return log_max_size; 1557 1558 return MLX5_ATOMIC_MODE_8B; 1559 } 1560 1561 static int get_atomic_mode(struct mlx5_ib_dev *dev, 1562 enum ib_qp_type qp_type) 1563 { 1564 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 1565 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic); 1566 int atomic_mode = -EOPNOTSUPP; 1567 int atomic_size_mask; 1568 1569 if (!atomic) 1570 return -EOPNOTSUPP; 1571 1572 if (qp_type == MLX5_IB_QPT_DCT) 1573 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 1574 else 1575 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 1576 1577 if ((atomic_operations & MLX5_ATOMIC_OPS_MASKED_CMP_SWAP) || 1578 (atomic_operations & MLX5_ATOMIC_OPS_MASKED_FETCH_ADD)) 1579 atomic_mode = atomic_size_to_mode(atomic_size_mask); 1580 1581 if (atomic_mode <= 0 && 1582 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP && 1583 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD)) 1584 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP; 1585 1586 return atomic_mode; 1587 } 1588 1589 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1590 struct ib_qp_init_attr *init_attr, 1591 struct ib_udata *udata, struct mlx5_ib_qp *qp) 1592 { 1593 struct mlx5_ib_resources *devr = &dev->devr; 1594 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1595 struct mlx5_core_dev *mdev = dev->mdev; 1596 struct mlx5_ib_create_qp_resp resp; 1597 struct mlx5_ib_cq *send_cq; 1598 struct mlx5_ib_cq *recv_cq; 1599 unsigned long flags; 1600 u32 uidx = MLX5_IB_DEFAULT_UIDX; 1601 struct mlx5_ib_create_qp ucmd; 1602 struct mlx5_ib_qp_base *base; 1603 void *qpc; 1604 u32 *in; 1605 int err; 1606 1607 base = init_attr->qp_type == IB_QPT_RAW_PACKET ? 1608 &qp->raw_packet_qp.rq.base : 1609 &qp->trans_qp.base; 1610 1611 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1612 mlx5_ib_odp_create_qp(qp); 1613 1614 mutex_init(&qp->mutex); 1615 spin_lock_init(&qp->sq.lock); 1616 spin_lock_init(&qp->rq.lock); 1617 1618 if (init_attr->rwq_ind_tbl) { 1619 if (!udata) 1620 return -ENOSYS; 1621 1622 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata); 1623 return err; 1624 } 1625 1626 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 1627 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { 1628 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); 1629 return -EINVAL; 1630 } else { 1631 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1632 } 1633 } 1634 1635 if (init_attr->create_flags & 1636 (IB_QP_CREATE_CROSS_CHANNEL | 1637 IB_QP_CREATE_MANAGED_SEND | 1638 IB_QP_CREATE_MANAGED_RECV)) { 1639 if (!MLX5_CAP_GEN(mdev, cd)) { 1640 mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); 1641 return -EINVAL; 1642 } 1643 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) 1644 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; 1645 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) 1646 qp->flags |= MLX5_IB_QP_MANAGED_SEND; 1647 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) 1648 qp->flags |= MLX5_IB_QP_MANAGED_RECV; 1649 } 1650 1651 if (init_attr->qp_type == IB_QPT_UD && 1652 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) 1653 if (!MLX5_CAP_GEN(mdev, ipoib_ipoib_offloads)) { 1654 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n"); 1655 return -EOPNOTSUPP; 1656 } 1657 1658 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 1659 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1660 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs"); 1661 return -EOPNOTSUPP; 1662 } 1663 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) || 1664 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 1665 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n"); 1666 return -EOPNOTSUPP; 1667 } 1668 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS; 1669 } 1670 1671 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1672 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1673 1674 if (pd && pd->uobject) { 1675 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 1676 mlx5_ib_dbg(dev, "copy failed\n"); 1677 return -EFAULT; 1678 } 1679 1680 err = get_qp_user_index(to_mucontext(pd->uobject->context), 1681 &ucmd, udata->inlen, &uidx); 1682 if (err) 1683 return err; 1684 1685 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 1686 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 1687 } else { 1688 qp->wq_sig = !!wq_signature; 1689 } 1690 1691 qp->has_rq = qp_has_rq(init_attr); 1692 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 1693 qp, (pd && pd->uobject) ? &ucmd : NULL); 1694 if (err) { 1695 mlx5_ib_dbg(dev, "err %d\n", err); 1696 return err; 1697 } 1698 1699 if (pd) { 1700 if (pd->uobject) { 1701 __u32 max_wqes = 1702 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1703 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 1704 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 1705 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 1706 mlx5_ib_dbg(dev, "invalid rq params\n"); 1707 return -EINVAL; 1708 } 1709 if (ucmd.sq_wqe_count > max_wqes) { 1710 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 1711 ucmd.sq_wqe_count, max_wqes); 1712 return -EINVAL; 1713 } 1714 if (init_attr->create_flags & 1715 MLX5_IB_QP_CREATE_SQPN_QP1) { 1716 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n"); 1717 return -EINVAL; 1718 } 1719 err = create_user_qp(dev, pd, qp, udata, init_attr, &in, 1720 &resp, &inlen, base); 1721 if (err) 1722 mlx5_ib_dbg(dev, "err %d\n", err); 1723 } else { 1724 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, 1725 base); 1726 if (err) 1727 mlx5_ib_dbg(dev, "err %d\n", err); 1728 } 1729 1730 if (err) 1731 return err; 1732 } else { 1733 in = mlx5_vzalloc(inlen); 1734 if (!in) 1735 return -ENOMEM; 1736 1737 qp->create_type = MLX5_QP_EMPTY; 1738 } 1739 1740 if (is_sqp(init_attr->qp_type)) 1741 qp->port = init_attr->port_num; 1742 1743 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1744 1745 MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type)); 1746 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1747 1748 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 1749 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 1750 else 1751 MLX5_SET(qpc, qpc, latency_sensitive, 1); 1752 1753 1754 if (qp->wq_sig) 1755 MLX5_SET(qpc, qpc, wq_signature, 1); 1756 1757 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 1758 MLX5_SET(qpc, qpc, block_lb_mc, 1); 1759 1760 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 1761 MLX5_SET(qpc, qpc, cd_master, 1); 1762 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 1763 MLX5_SET(qpc, qpc, cd_slave_send, 1); 1764 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 1765 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 1766 1767 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 1768 int rcqe_sz; 1769 int scqe_sz; 1770 1771 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq); 1772 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq); 1773 1774 if (rcqe_sz == 128) 1775 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 1776 else 1777 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE); 1778 1779 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) { 1780 if (scqe_sz == 128) 1781 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1782 else 1783 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1784 } 1785 } 1786 1787 if (qp->rq.wqe_cnt) { 1788 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 1789 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 1790 } 1791 1792 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1793 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev)); 1794 1795 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 1796 1797 if (qp->sq.wqe_cnt) 1798 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 1799 else 1800 MLX5_SET(qpc, qpc, no_sq, 1); 1801 1802 /* Set default resources */ 1803 switch (init_attr->qp_type) { 1804 case IB_QPT_XRC_TGT: 1805 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1806 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 1807 MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s0)->msrq.srqn); 1808 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn); 1809 break; 1810 case IB_QPT_XRC_INI: 1811 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1812 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1813 MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s0)->msrq.srqn); 1814 break; 1815 default: 1816 if (init_attr->srq) { 1817 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn); 1818 MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(init_attr->srq)->msrq.srqn); 1819 } else { 1820 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1821 MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s1)->msrq.srqn); 1822 } 1823 } 1824 1825 if (init_attr->send_cq) 1826 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 1827 1828 if (init_attr->recv_cq) 1829 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 1830 1831 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 1832 1833 /* 0xffffff means we ask to work with cqe version 0 */ 1834 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 1835 MLX5_SET(qpc, qpc, user_index, uidx); 1836 1837 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 1838 if (init_attr->qp_type == IB_QPT_UD && 1839 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) { 1840 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 1841 qp->flags |= MLX5_IB_QP_LSO; 1842 } 1843 1844 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 1845 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; 1846 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 1847 err = create_raw_packet_qp(dev, qp, in, pd); 1848 } else { 1849 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); 1850 } 1851 1852 if (err) { 1853 mlx5_ib_dbg(dev, "create qp failed\n"); 1854 goto err_create; 1855 } 1856 1857 kvfree(in); 1858 1859 base->container_mibqp = qp; 1860 base->mqp.event = mlx5_ib_qp_event; 1861 1862 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq, 1863 &send_cq, &recv_cq); 1864 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1865 mlx5_ib_lock_cqs(send_cq, recv_cq); 1866 /* Maintain device to QPs access, needed for further handling via reset 1867 * flow 1868 */ 1869 list_add_tail(&qp->qps_list, &dev->qp_list); 1870 /* Maintain CQ to QPs access, needed for further handling via reset flow 1871 */ 1872 if (send_cq) 1873 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 1874 if (recv_cq) 1875 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 1876 mlx5_ib_unlock_cqs(send_cq, recv_cq); 1877 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1878 1879 return 0; 1880 1881 err_create: 1882 if (qp->create_type == MLX5_QP_USER) 1883 destroy_qp_user(dev, pd, qp, base, udata); 1884 else if (qp->create_type == MLX5_QP_KERNEL) 1885 destroy_qp_kernel(dev, qp); 1886 1887 kvfree(in); 1888 return err; 1889 } 1890 1891 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1892 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1893 { 1894 if (send_cq) { 1895 if (recv_cq) { 1896 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1897 spin_lock(&send_cq->lock); 1898 spin_lock_nested(&recv_cq->lock, 1899 SINGLE_DEPTH_NESTING); 1900 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1901 spin_lock(&send_cq->lock); 1902 __acquire(&recv_cq->lock); 1903 } else { 1904 spin_lock(&recv_cq->lock); 1905 spin_lock_nested(&send_cq->lock, 1906 SINGLE_DEPTH_NESTING); 1907 } 1908 } else { 1909 spin_lock(&send_cq->lock); 1910 __acquire(&recv_cq->lock); 1911 } 1912 } else if (recv_cq) { 1913 spin_lock(&recv_cq->lock); 1914 __acquire(&send_cq->lock); 1915 } else { 1916 __acquire(&send_cq->lock); 1917 __acquire(&recv_cq->lock); 1918 } 1919 } 1920 1921 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1922 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1923 { 1924 if (send_cq) { 1925 if (recv_cq) { 1926 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1927 spin_unlock(&recv_cq->lock); 1928 spin_unlock(&send_cq->lock); 1929 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1930 __release(&recv_cq->lock); 1931 spin_unlock(&send_cq->lock); 1932 } else { 1933 spin_unlock(&send_cq->lock); 1934 spin_unlock(&recv_cq->lock); 1935 } 1936 } else { 1937 __release(&recv_cq->lock); 1938 spin_unlock(&send_cq->lock); 1939 } 1940 } else if (recv_cq) { 1941 __release(&send_cq->lock); 1942 spin_unlock(&recv_cq->lock); 1943 } else { 1944 __release(&recv_cq->lock); 1945 __release(&send_cq->lock); 1946 } 1947 } 1948 1949 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 1950 { 1951 return to_mpd(qp->ibqp.pd); 1952 } 1953 1954 static void get_cqs(enum ib_qp_type qp_type, 1955 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 1956 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 1957 { 1958 switch (qp_type) { 1959 case IB_QPT_XRC_TGT: 1960 *send_cq = NULL; 1961 *recv_cq = NULL; 1962 break; 1963 case MLX5_IB_QPT_REG_UMR: 1964 case IB_QPT_XRC_INI: 1965 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 1966 *recv_cq = NULL; 1967 break; 1968 1969 case IB_QPT_SMI: 1970 case MLX5_IB_QPT_HW_GSI: 1971 case IB_QPT_RC: 1972 case IB_QPT_UC: 1973 case IB_QPT_UD: 1974 case IB_QPT_RAW_IPV6: 1975 case IB_QPT_RAW_ETHERTYPE: 1976 case IB_QPT_RAW_PACKET: 1977 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 1978 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 1979 break; 1980 1981 case IB_QPT_MAX: 1982 default: 1983 *send_cq = NULL; 1984 *recv_cq = NULL; 1985 break; 1986 } 1987 } 1988 1989 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1990 const struct mlx5_modify_raw_qp_param *raw_qp_param, 1991 u8 lag_tx_affinity); 1992 1993 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1994 struct ib_udata *udata) 1995 { 1996 struct mlx5_ib_cq *send_cq, *recv_cq; 1997 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 1998 unsigned long flags; 1999 int err; 2000 2001 if (qp->ibqp.rwq_ind_tbl) { 2002 destroy_rss_raw_qp_tir(dev, qp); 2003 return; 2004 } 2005 2006 base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ? 2007 &qp->raw_packet_qp.rq.base : 2008 &qp->trans_qp.base; 2009 2010 if (qp->state != IB_QPS_RESET) { 2011 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) { 2012 mlx5_ib_qp_disable_pagefaults(qp); 2013 err = mlx5_core_qp_modify(dev->mdev, 2014 MLX5_CMD_OP_2RST_QP, 0, 2015 NULL, &base->mqp); 2016 } else { 2017 struct mlx5_modify_raw_qp_param raw_qp_param = { 2018 .operation = MLX5_CMD_OP_2RST_QP 2019 }; 2020 2021 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2022 } 2023 if (err) 2024 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2025 base->mqp.qpn); 2026 } 2027 2028 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2029 &send_cq, &recv_cq); 2030 2031 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2032 mlx5_ib_lock_cqs(send_cq, recv_cq); 2033 /* del from lists under both locks above to protect reset flow paths */ 2034 list_del(&qp->qps_list); 2035 if (send_cq) 2036 list_del(&qp->cq_send_list); 2037 2038 if (recv_cq) 2039 list_del(&qp->cq_recv_list); 2040 2041 if (qp->create_type == MLX5_QP_KERNEL) { 2042 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2043 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2044 if (send_cq != recv_cq) 2045 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2046 NULL); 2047 } 2048 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2049 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2050 2051 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 2052 destroy_raw_packet_qp(dev, qp); 2053 } else { 2054 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); 2055 if (err) 2056 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2057 base->mqp.qpn); 2058 } 2059 2060 if (qp->create_type == MLX5_QP_KERNEL) 2061 destroy_qp_kernel(dev, qp); 2062 else if (qp->create_type == MLX5_QP_USER) 2063 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base, udata); 2064 } 2065 2066 static const char *ib_qp_type_str(enum ib_qp_type type) 2067 { 2068 switch (type) { 2069 case IB_QPT_SMI: 2070 return "IB_QPT_SMI"; 2071 case IB_QPT_GSI: 2072 return "IB_QPT_GSI"; 2073 case IB_QPT_RC: 2074 return "IB_QPT_RC"; 2075 case IB_QPT_UC: 2076 return "IB_QPT_UC"; 2077 case IB_QPT_UD: 2078 return "IB_QPT_UD"; 2079 case IB_QPT_RAW_IPV6: 2080 return "IB_QPT_RAW_IPV6"; 2081 case IB_QPT_RAW_ETHERTYPE: 2082 return "IB_QPT_RAW_ETHERTYPE"; 2083 case IB_QPT_XRC_INI: 2084 return "IB_QPT_XRC_INI"; 2085 case IB_QPT_XRC_TGT: 2086 return "IB_QPT_XRC_TGT"; 2087 case IB_QPT_RAW_PACKET: 2088 return "IB_QPT_RAW_PACKET"; 2089 case MLX5_IB_QPT_REG_UMR: 2090 return "MLX5_IB_QPT_REG_UMR"; 2091 case IB_QPT_MAX: 2092 default: 2093 return "Invalid QP type"; 2094 } 2095 } 2096 2097 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 2098 struct ib_qp_init_attr *init_attr, 2099 struct ib_udata *udata) 2100 { 2101 struct mlx5_ib_dev *dev; 2102 struct mlx5_ib_qp *qp; 2103 u16 xrcdn = 0; 2104 int err; 2105 2106 if (pd) { 2107 dev = to_mdev(pd->device); 2108 2109 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 2110 if (!pd->uobject) { 2111 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); 2112 return ERR_PTR(-EINVAL); 2113 } else if (!to_mucontext(pd->uobject->context)->cqe_version) { 2114 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); 2115 return ERR_PTR(-EINVAL); 2116 } 2117 } 2118 } else { 2119 /* being cautious here */ 2120 if (init_attr->qp_type != IB_QPT_XRC_TGT && 2121 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 2122 pr_warn("%s: no PD for transport %s\n", __func__, 2123 ib_qp_type_str(init_attr->qp_type)); 2124 return ERR_PTR(-EINVAL); 2125 } 2126 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 2127 } 2128 2129 switch (init_attr->qp_type) { 2130 case IB_QPT_XRC_TGT: 2131 case IB_QPT_XRC_INI: 2132 if (!MLX5_CAP_GEN(dev->mdev, xrc)) { 2133 mlx5_ib_dbg(dev, "XRC not supported\n"); 2134 return ERR_PTR(-ENOSYS); 2135 } 2136 init_attr->recv_cq = NULL; 2137 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 2138 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 2139 init_attr->send_cq = NULL; 2140 } 2141 2142 /* fall through */ 2143 case IB_QPT_RAW_PACKET: 2144 case IB_QPT_RC: 2145 case IB_QPT_UC: 2146 case IB_QPT_UD: 2147 case IB_QPT_SMI: 2148 case MLX5_IB_QPT_HW_GSI: 2149 case MLX5_IB_QPT_REG_UMR: 2150 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2151 if (!qp) 2152 return ERR_PTR(-ENOMEM); 2153 2154 err = create_qp_common(dev, pd, init_attr, udata, qp); 2155 if (err) { 2156 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 2157 kfree(qp); 2158 return ERR_PTR(err); 2159 } 2160 2161 if (is_qp0(init_attr->qp_type)) 2162 qp->ibqp.qp_num = 0; 2163 else if (is_qp1(init_attr->qp_type)) 2164 qp->ibqp.qp_num = 1; 2165 else 2166 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2167 2168 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 2169 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2170 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1, 2171 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1); 2172 2173 qp->trans_qp.xrcdn = xrcdn; 2174 2175 break; 2176 2177 case IB_QPT_GSI: 2178 return mlx5_ib_gsi_create_qp(pd, init_attr); 2179 2180 case IB_QPT_RAW_IPV6: 2181 case IB_QPT_RAW_ETHERTYPE: 2182 case IB_QPT_MAX: 2183 default: 2184 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 2185 init_attr->qp_type); 2186 /* Don't support raw QPs */ 2187 return ERR_PTR(-EINVAL); 2188 } 2189 2190 return &qp->ibqp; 2191 } 2192 2193 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 2194 { 2195 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2196 struct mlx5_ib_qp *mqp = to_mqp(qp); 2197 2198 if (unlikely(qp->qp_type == IB_QPT_GSI)) 2199 return mlx5_ib_gsi_destroy_qp(qp); 2200 2201 destroy_qp_common(dev, mqp, udata); 2202 2203 kfree(mqp); 2204 2205 return 0; 2206 } 2207 2208 static int to_mlx5_access_flags(struct mlx5_ib_qp *qp, 2209 const struct ib_qp_attr *attr, 2210 int attr_mask, __be32 *hw_access_flags_be) 2211 { 2212 u8 dest_rd_atomic; 2213 u32 access_flags, hw_access_flags = 0; 2214 2215 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 2216 2217 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2218 dest_rd_atomic = attr->max_dest_rd_atomic; 2219 else 2220 dest_rd_atomic = qp->trans_qp.resp_depth; 2221 2222 if (attr_mask & IB_QP_ACCESS_FLAGS) 2223 access_flags = attr->qp_access_flags; 2224 else 2225 access_flags = qp->trans_qp.atomic_rd_en; 2226 2227 if (!dest_rd_atomic) 2228 access_flags &= IB_ACCESS_REMOTE_WRITE; 2229 2230 if (access_flags & IB_ACCESS_REMOTE_READ) 2231 hw_access_flags |= MLX5_QP_BIT_RRE; 2232 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) { 2233 int atomic_mode; 2234 2235 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type); 2236 if (atomic_mode < 0) 2237 return -EOPNOTSUPP; 2238 2239 hw_access_flags |= MLX5_QP_BIT_RAE; 2240 hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFF; 2241 } 2242 2243 if (access_flags & IB_ACCESS_REMOTE_WRITE) 2244 hw_access_flags |= MLX5_QP_BIT_RWE; 2245 2246 *hw_access_flags_be = cpu_to_be32(hw_access_flags); 2247 2248 return 0; 2249 } 2250 2251 enum { 2252 MLX5_PATH_FLAG_FL = 1 << 0, 2253 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 2254 MLX5_PATH_FLAG_COUNTER = 1 << 2, 2255 }; 2256 2257 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 2258 { 2259 if (rate == IB_RATE_PORT_CURRENT) { 2260 return 0; 2261 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS) { 2262 return -EINVAL; 2263 } else { 2264 while (rate != IB_RATE_2_5_GBPS && 2265 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 2266 MLX5_CAP_GEN(dev->mdev, stat_rate_support))) 2267 --rate; 2268 } 2269 2270 return rate + MLX5_STAT_RATE_OFFSET; 2271 } 2272 2273 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 2274 struct mlx5_ib_sq *sq, u8 sl, 2275 struct ib_pd *pd) 2276 { 2277 void *in; 2278 void *tisc; 2279 int inlen; 2280 int err; 2281 2282 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2283 in = mlx5_vzalloc(inlen); 2284 if (!in) 2285 return -ENOMEM; 2286 2287 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 2288 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 2289 2290 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2291 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 2292 2293 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2294 2295 kvfree(in); 2296 2297 return err; 2298 } 2299 2300 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 2301 struct mlx5_ib_sq *sq, u8 tx_affinity, 2302 struct ib_pd *pd) 2303 { 2304 void *in; 2305 void *tisc; 2306 int inlen; 2307 int err; 2308 2309 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2310 in = mlx5_vzalloc(inlen); 2311 if (!in) 2312 return -ENOMEM; 2313 2314 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 2315 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 2316 2317 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2318 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 2319 2320 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2321 2322 kvfree(in); 2323 2324 return err; 2325 } 2326 2327 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2328 const struct ib_ah_attr *ah, 2329 struct mlx5_qp_path *path, u8 port, int attr_mask, 2330 u32 path_flags, const struct ib_qp_attr *attr, 2331 bool alt) 2332 { 2333 enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port); 2334 int err; 2335 enum ib_gid_type gid_type; 2336 2337 if (attr_mask & IB_QP_PKEY_INDEX) 2338 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index : 2339 attr->pkey_index); 2340 2341 if (ah->ah_flags & IB_AH_GRH) { 2342 if (ah->grh.sgid_index >= 2343 dev->mdev->port_caps[port - 1].gid_table_len) { 2344 pr_err("sgid_index (%u) too large. max is %d\n", 2345 ah->grh.sgid_index, 2346 dev->mdev->port_caps[port - 1].gid_table_len); 2347 return -EINVAL; 2348 } 2349 } 2350 2351 if (ll == IB_LINK_LAYER_ETHERNET) { 2352 if (!(ah->ah_flags & IB_AH_GRH)) 2353 return -EINVAL; 2354 err = mlx5_get_roce_gid_type(dev, port, ah->grh.sgid_index, 2355 &gid_type); 2356 if (err) 2357 return err; 2358 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac)); 2359 path->udp_sport = mlx5_get_roce_udp_sport(dev, port, 2360 ah->grh.sgid_index); 2361 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4; 2362 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 2363 path->ecn_dscp = (ah->grh.traffic_class >> 2) & 0x3f; 2364 } else { 2365 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 2366 path->fl_free_ar |= 2367 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0; 2368 path->rlid = cpu_to_be16(ah->dlid); 2369 path->grh_mlid = ah->src_path_bits & 0x7f; 2370 if (ah->ah_flags & IB_AH_GRH) 2371 path->grh_mlid |= 1 << 7; 2372 path->dci_cfi_prio_sl = ah->sl & 0xf; 2373 } 2374 2375 if (ah->ah_flags & IB_AH_GRH) { 2376 path->mgid_index = ah->grh.sgid_index; 2377 path->hop_limit = ah->grh.hop_limit; 2378 path->tclass_flowlabel = 2379 cpu_to_be32((ah->grh.traffic_class << 20) | 2380 (ah->grh.flow_label)); 2381 memcpy(path->rgid, ah->grh.dgid.raw, 16); 2382 } 2383 2384 err = ib_rate_to_mlx5(dev, ah->static_rate); 2385 if (err < 0) 2386 return err; 2387 path->static_rate = err; 2388 path->port = port; 2389 2390 if (attr_mask & IB_QP_TIMEOUT) 2391 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3; 2392 2393 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 2394 return modify_raw_packet_eth_prio(dev->mdev, 2395 &qp->raw_packet_qp.sq, 2396 ah->sl & 0xf, qp->ibqp.pd); 2397 2398 return 0; 2399 } 2400 2401 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 2402 [MLX5_QP_STATE_INIT] = { 2403 [MLX5_QP_STATE_INIT] = { 2404 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2405 MLX5_QP_OPTPAR_RAE | 2406 MLX5_QP_OPTPAR_RWE | 2407 MLX5_QP_OPTPAR_PKEY_INDEX | 2408 MLX5_QP_OPTPAR_PRI_PORT, 2409 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2410 MLX5_QP_OPTPAR_PKEY_INDEX | 2411 MLX5_QP_OPTPAR_PRI_PORT, 2412 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2413 MLX5_QP_OPTPAR_Q_KEY | 2414 MLX5_QP_OPTPAR_PRI_PORT, 2415 }, 2416 [MLX5_QP_STATE_RTR] = { 2417 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2418 MLX5_QP_OPTPAR_RRE | 2419 MLX5_QP_OPTPAR_RAE | 2420 MLX5_QP_OPTPAR_RWE | 2421 MLX5_QP_OPTPAR_PKEY_INDEX, 2422 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2423 MLX5_QP_OPTPAR_RWE | 2424 MLX5_QP_OPTPAR_PKEY_INDEX, 2425 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2426 MLX5_QP_OPTPAR_Q_KEY, 2427 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 2428 MLX5_QP_OPTPAR_Q_KEY, 2429 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2430 MLX5_QP_OPTPAR_RRE | 2431 MLX5_QP_OPTPAR_RAE | 2432 MLX5_QP_OPTPAR_RWE | 2433 MLX5_QP_OPTPAR_PKEY_INDEX, 2434 }, 2435 }, 2436 [MLX5_QP_STATE_RTR] = { 2437 [MLX5_QP_STATE_RTS] = { 2438 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2439 MLX5_QP_OPTPAR_RRE | 2440 MLX5_QP_OPTPAR_RAE | 2441 MLX5_QP_OPTPAR_RWE | 2442 MLX5_QP_OPTPAR_PM_STATE | 2443 MLX5_QP_OPTPAR_RNR_TIMEOUT, 2444 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2445 MLX5_QP_OPTPAR_RWE | 2446 MLX5_QP_OPTPAR_PM_STATE, 2447 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2448 }, 2449 }, 2450 [MLX5_QP_STATE_RTS] = { 2451 [MLX5_QP_STATE_RTS] = { 2452 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2453 MLX5_QP_OPTPAR_RAE | 2454 MLX5_QP_OPTPAR_RWE | 2455 MLX5_QP_OPTPAR_RNR_TIMEOUT | 2456 MLX5_QP_OPTPAR_PM_STATE | 2457 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2458 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2459 MLX5_QP_OPTPAR_PM_STATE | 2460 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2461 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 2462 MLX5_QP_OPTPAR_SRQN | 2463 MLX5_QP_OPTPAR_CQN_RCV, 2464 }, 2465 }, 2466 [MLX5_QP_STATE_SQER] = { 2467 [MLX5_QP_STATE_RTS] = { 2468 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2469 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 2470 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 2471 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 2472 MLX5_QP_OPTPAR_RWE | 2473 MLX5_QP_OPTPAR_RAE | 2474 MLX5_QP_OPTPAR_RRE, 2475 }, 2476 }, 2477 }; 2478 2479 static int ib_nr_to_mlx5_nr(int ib_mask) 2480 { 2481 switch (ib_mask) { 2482 case IB_QP_STATE: 2483 return 0; 2484 case IB_QP_CUR_STATE: 2485 return 0; 2486 case IB_QP_EN_SQD_ASYNC_NOTIFY: 2487 return 0; 2488 case IB_QP_ACCESS_FLAGS: 2489 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 2490 MLX5_QP_OPTPAR_RAE; 2491 case IB_QP_PKEY_INDEX: 2492 return MLX5_QP_OPTPAR_PKEY_INDEX; 2493 case IB_QP_PORT: 2494 return MLX5_QP_OPTPAR_PRI_PORT; 2495 case IB_QP_QKEY: 2496 return MLX5_QP_OPTPAR_Q_KEY; 2497 case IB_QP_AV: 2498 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 2499 MLX5_QP_OPTPAR_PRI_PORT; 2500 case IB_QP_PATH_MTU: 2501 return 0; 2502 case IB_QP_TIMEOUT: 2503 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 2504 case IB_QP_RETRY_CNT: 2505 return MLX5_QP_OPTPAR_RETRY_COUNT; 2506 case IB_QP_RNR_RETRY: 2507 return MLX5_QP_OPTPAR_RNR_RETRY; 2508 case IB_QP_RQ_PSN: 2509 return 0; 2510 case IB_QP_MAX_QP_RD_ATOMIC: 2511 return MLX5_QP_OPTPAR_SRA_MAX; 2512 case IB_QP_ALT_PATH: 2513 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 2514 case IB_QP_MIN_RNR_TIMER: 2515 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 2516 case IB_QP_SQ_PSN: 2517 return 0; 2518 case IB_QP_MAX_DEST_RD_ATOMIC: 2519 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 2520 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 2521 case IB_QP_PATH_MIG_STATE: 2522 return MLX5_QP_OPTPAR_PM_STATE; 2523 case IB_QP_CAP: 2524 return 0; 2525 case IB_QP_DEST_QPN: 2526 return 0; 2527 } 2528 return 0; 2529 } 2530 2531 static int ib_mask_to_mlx5_opt(int ib_mask) 2532 { 2533 int result = 0; 2534 int i; 2535 2536 for (i = 0; i < 8 * sizeof(int); i++) { 2537 if ((1 << i) & ib_mask) 2538 result |= ib_nr_to_mlx5_nr(1 << i); 2539 } 2540 2541 return result; 2542 } 2543 2544 static int modify_raw_packet_qp_rq( 2545 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state, 2546 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 2547 { 2548 void *in; 2549 void *rqc; 2550 int inlen; 2551 int err; 2552 2553 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 2554 in = mlx5_vzalloc(inlen); 2555 if (!in) 2556 return -ENOMEM; 2557 2558 MLX5_SET(modify_rq_in, in, rqn, rq->base.mqp.qpn); 2559 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 2560 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid); 2561 2562 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 2563 MLX5_SET(rqc, rqc, state, new_state); 2564 2565 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 2566 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counters_set_id)) { 2567 MLX5_SET64(modify_rq_in, in, modify_bitmask, 2568 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID); 2569 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 2570 } else 2571 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n", 2572 dev->ib_dev.name); 2573 } 2574 2575 err = mlx5_core_modify_rq(dev->mdev, in, inlen); 2576 if (err) 2577 goto out; 2578 2579 rq->state = new_state; 2580 2581 out: 2582 kvfree(in); 2583 return err; 2584 } 2585 2586 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev, 2587 struct mlx5_ib_sq *sq, int new_state, 2588 struct ib_pd *pd) 2589 { 2590 void *in; 2591 void *sqc; 2592 int inlen; 2593 int err; 2594 2595 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 2596 in = mlx5_vzalloc(inlen); 2597 if (!in) 2598 return -ENOMEM; 2599 2600 MLX5_SET(modify_sq_in, in, sqn, sq->base.mqp.qpn); 2601 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid); 2602 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 2603 2604 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 2605 MLX5_SET(sqc, sqc, state, new_state); 2606 2607 err = mlx5_core_modify_sq(dev, in, inlen); 2608 if (err) 2609 goto out; 2610 2611 sq->state = new_state; 2612 2613 out: 2614 kvfree(in); 2615 return err; 2616 } 2617 2618 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2619 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2620 u8 tx_affinity) 2621 { 2622 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 2623 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 2624 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 2625 int modify_rq = !!qp->rq.wqe_cnt; 2626 int modify_sq = !!qp->sq.wqe_cnt; 2627 int rq_state; 2628 int sq_state; 2629 int err; 2630 2631 switch (raw_qp_param->operation) { 2632 case MLX5_CMD_OP_RST2INIT_QP: 2633 rq_state = MLX5_RQC_STATE_RDY; 2634 sq_state = MLX5_SQC_STATE_RDY; 2635 break; 2636 case MLX5_CMD_OP_2ERR_QP: 2637 rq_state = MLX5_RQC_STATE_ERR; 2638 sq_state = MLX5_SQC_STATE_ERR; 2639 break; 2640 case MLX5_CMD_OP_2RST_QP: 2641 rq_state = MLX5_RQC_STATE_RST; 2642 sq_state = MLX5_SQC_STATE_RST; 2643 break; 2644 case MLX5_CMD_OP_RTR2RTS_QP: 2645 case MLX5_CMD_OP_RTS2RTS_QP: 2646 return raw_qp_param->set_mask ? -EINVAL : 0; 2647 case MLX5_CMD_OP_INIT2INIT_QP: 2648 case MLX5_CMD_OP_INIT2RTR_QP: 2649 if (raw_qp_param->set_mask) 2650 return -EINVAL; 2651 else 2652 return 0; 2653 default: 2654 WARN_ON(1); 2655 return -EINVAL; 2656 } 2657 2658 if (modify_rq) { 2659 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param, 2660 qp->ibqp.pd); 2661 if (err) 2662 return err; 2663 } 2664 2665 if (modify_sq) { 2666 if (tx_affinity) { 2667 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 2668 tx_affinity, 2669 qp->ibqp.pd); 2670 if (err) 2671 return err; 2672 } 2673 2674 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, qp->ibqp.pd); 2675 } 2676 2677 return 0; 2678 } 2679 2680 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 2681 const struct ib_qp_attr *attr, int attr_mask, 2682 enum ib_qp_state cur_state, enum ib_qp_state new_state) 2683 { 2684 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 2685 [MLX5_QP_STATE_RST] = { 2686 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2687 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2688 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 2689 }, 2690 [MLX5_QP_STATE_INIT] = { 2691 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2692 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2693 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 2694 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 2695 }, 2696 [MLX5_QP_STATE_RTR] = { 2697 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2698 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2699 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 2700 }, 2701 [MLX5_QP_STATE_RTS] = { 2702 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2703 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2704 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 2705 }, 2706 [MLX5_QP_STATE_SQD] = { 2707 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2708 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2709 }, 2710 [MLX5_QP_STATE_SQER] = { 2711 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2712 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2713 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 2714 }, 2715 [MLX5_QP_STATE_ERR] = { 2716 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2717 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2718 } 2719 }; 2720 2721 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2722 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2723 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 2724 struct mlx5_ib_cq *send_cq, *recv_cq; 2725 struct mlx5_qp_context *context; 2726 struct mlx5_ib_pd *pd; 2727 struct mlx5_ib_port *mibport = NULL; 2728 enum mlx5_qp_state mlx5_cur, mlx5_new; 2729 enum mlx5_qp_optpar optpar; 2730 int sqd_event; 2731 int mlx5_st; 2732 int err; 2733 u16 op; 2734 2735 context = kzalloc(sizeof(*context), GFP_KERNEL); 2736 if (!context) 2737 return -ENOMEM; 2738 2739 err = to_mlx5_st(ibqp->qp_type); 2740 if (err < 0) { 2741 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type); 2742 goto out; 2743 } 2744 2745 context->flags = cpu_to_be32(err << 16); 2746 2747 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 2748 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2749 } else { 2750 switch (attr->path_mig_state) { 2751 case IB_MIG_MIGRATED: 2752 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2753 break; 2754 case IB_MIG_REARM: 2755 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 2756 break; 2757 case IB_MIG_ARMED: 2758 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 2759 break; 2760 } 2761 } 2762 2763 if (is_sqp(ibqp->qp_type)) { 2764 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 2765 } else if (ibqp->qp_type == IB_QPT_UD || 2766 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 2767 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 2768 } else if (attr_mask & IB_QP_PATH_MTU) { 2769 if (attr->path_mtu < IB_MTU_256 || 2770 attr->path_mtu > IB_MTU_4096) { 2771 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 2772 err = -EINVAL; 2773 goto out; 2774 } 2775 context->mtu_msgmax = (attr->path_mtu << 5) | 2776 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); 2777 } 2778 2779 if (attr_mask & IB_QP_DEST_QPN) 2780 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 2781 2782 if (attr_mask & IB_QP_PKEY_INDEX) 2783 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index); 2784 2785 /* todo implement counter_index functionality */ 2786 2787 if (is_sqp(ibqp->qp_type)) 2788 context->pri_path.port = qp->port; 2789 2790 if (attr_mask & IB_QP_PORT) 2791 context->pri_path.port = attr->port_num; 2792 2793 if (attr_mask & IB_QP_AV) { 2794 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, 2795 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 2796 attr_mask, 0, attr, false); 2797 if (err) 2798 goto out; 2799 } 2800 2801 if (attr_mask & IB_QP_TIMEOUT) 2802 context->pri_path.ackto_lt |= attr->timeout << 3; 2803 2804 if (attr_mask & IB_QP_ALT_PATH) { 2805 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, 2806 &context->alt_path, 2807 attr->alt_port_num, 2808 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT, 2809 0, attr, true); 2810 if (err) 2811 goto out; 2812 } 2813 2814 pd = get_pd(qp); 2815 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2816 &send_cq, &recv_cq); 2817 2818 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 2819 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 2820 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 2821 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 2822 2823 if (attr_mask & IB_QP_RNR_RETRY) 2824 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 2825 2826 if (attr_mask & IB_QP_RETRY_CNT) 2827 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 2828 2829 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2830 if (attr->max_rd_atomic) 2831 context->params1 |= 2832 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 2833 } 2834 2835 if (attr_mask & IB_QP_SQ_PSN) 2836 context->next_send_psn = cpu_to_be32(attr->sq_psn); 2837 2838 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2839 if (attr->max_dest_rd_atomic) 2840 context->params2 |= 2841 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 2842 } 2843 2844 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 2845 __be32 access_flags; 2846 2847 err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags); 2848 if (err) 2849 goto out; 2850 2851 context->params2 |= access_flags; 2852 } 2853 2854 if (attr_mask & IB_QP_MIN_RNR_TIMER) 2855 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 2856 2857 if (attr_mask & IB_QP_RQ_PSN) 2858 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 2859 2860 if (attr_mask & IB_QP_QKEY) 2861 context->qkey = cpu_to_be32(attr->qkey); 2862 2863 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2864 context->db_rec_addr = cpu_to_be64(qp->db.dma); 2865 2866 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && 2867 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify) 2868 sqd_event = 1; 2869 else 2870 sqd_event = 0; 2871 2872 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2873 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 2874 qp->port) - 1; 2875 mibport = &dev->port[port_num]; 2876 context->qp_counter_set_usr_page |= 2877 cpu_to_be32((u32)(mibport->q_cnt_id) << 24); 2878 } 2879 2880 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2881 context->sq_crq_size |= cpu_to_be16(1 << 4); 2882 2883 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 2884 context->deth_sqpn = cpu_to_be32(1); 2885 2886 mlx5_cur = to_mlx5_state(cur_state); 2887 mlx5_new = to_mlx5_state(new_state); 2888 mlx5_st = to_mlx5_st(ibqp->qp_type); 2889 if (mlx5_st < 0) 2890 goto out; 2891 2892 /* If moving to a reset or error state, we must disable page faults on 2893 * this QP and flush all current page faults. Otherwise a stale page 2894 * fault may attempt to work on this QP after it is reset and moved 2895 * again to RTS, and may cause the driver and the device to get out of 2896 * sync. */ 2897 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR && 2898 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) && 2899 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET)) 2900 mlx5_ib_qp_disable_pagefaults(qp); 2901 2902 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 2903 !optab[mlx5_cur][mlx5_new]) 2904 goto out; 2905 2906 op = optab[mlx5_cur][mlx5_new]; 2907 optpar = ib_mask_to_mlx5_opt(attr_mask); 2908 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 2909 2910 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 2911 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 2912 2913 raw_qp_param.operation = op; 2914 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2915 raw_qp_param.rq_q_ctr_id = mibport->q_cnt_id; 2916 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 2917 } 2918 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2919 } else { 2920 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context, 2921 &base->mqp); 2922 } 2923 2924 if (err) 2925 goto out; 2926 2927 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT && 2928 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET)) 2929 mlx5_ib_qp_enable_pagefaults(qp); 2930 2931 qp->state = new_state; 2932 2933 if (attr_mask & IB_QP_ACCESS_FLAGS) 2934 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 2935 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2936 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 2937 if (attr_mask & IB_QP_PORT) 2938 qp->port = attr->port_num; 2939 if (attr_mask & IB_QP_ALT_PATH) 2940 qp->trans_qp.alt_port = attr->alt_port_num; 2941 2942 /* 2943 * If we moved a kernel QP to RESET, clean up all old CQ 2944 * entries and reinitialize the QP. 2945 */ 2946 if (new_state == IB_QPS_RESET && !ibqp->uobject) { 2947 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2948 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 2949 if (send_cq != recv_cq) 2950 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 2951 2952 qp->rq.head = 0; 2953 qp->rq.tail = 0; 2954 qp->sq.head = 0; 2955 qp->sq.tail = 0; 2956 qp->sq.cur_post = 0; 2957 qp->sq.last_poll = 0; 2958 qp->db.db[MLX5_RCV_DBR] = 0; 2959 qp->db.db[MLX5_SND_DBR] = 0; 2960 } 2961 2962 out: 2963 kfree(context); 2964 return err; 2965 } 2966 2967 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2968 int attr_mask, struct ib_udata *udata) 2969 { 2970 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2971 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2972 enum ib_qp_type qp_type; 2973 enum ib_qp_state cur_state, new_state; 2974 int err = -EINVAL; 2975 int port; 2976 2977 if (ibqp->rwq_ind_tbl) 2978 return -ENOSYS; 2979 2980 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 2981 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 2982 2983 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? 2984 IB_QPT_GSI : ibqp->qp_type; 2985 2986 mutex_lock(&qp->mutex); 2987 2988 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 2989 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 2990 2991 if (qp_type != MLX5_IB_QPT_REG_UMR && 2992 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask)) { 2993 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 2994 cur_state, new_state, ibqp->qp_type, attr_mask); 2995 goto out; 2996 } 2997 2998 if ((attr_mask & IB_QP_PORT) && 2999 (attr->port_num == 0 || 3000 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) { 3001 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 3002 attr->port_num, dev->num_ports); 3003 goto out; 3004 } 3005 3006 if (attr_mask & IB_QP_PKEY_INDEX) { 3007 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 3008 if (attr->pkey_index >= 3009 dev->mdev->port_caps[port - 1].pkey_table_len) { 3010 mlx5_ib_dbg(dev, "invalid pkey index %d\n", 3011 attr->pkey_index); 3012 goto out; 3013 } 3014 } 3015 3016 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 3017 attr->max_rd_atomic > 3018 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 3019 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 3020 attr->max_rd_atomic); 3021 goto out; 3022 } 3023 3024 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 3025 attr->max_dest_rd_atomic > 3026 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 3027 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 3028 attr->max_dest_rd_atomic); 3029 goto out; 3030 } 3031 3032 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 3033 err = 0; 3034 goto out; 3035 } 3036 3037 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state); 3038 3039 out: 3040 mutex_unlock(&qp->mutex); 3041 return err; 3042 } 3043 3044 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 3045 { 3046 struct mlx5_ib_cq *cq; 3047 unsigned cur; 3048 3049 cur = wq->head - wq->tail; 3050 if (likely(cur + nreq < wq->max_post)) 3051 return 0; 3052 3053 cq = to_mcq(ib_cq); 3054 spin_lock(&cq->lock); 3055 cur = wq->head - wq->tail; 3056 spin_unlock(&cq->lock); 3057 3058 return cur + nreq >= wq->max_post; 3059 } 3060 3061 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 3062 u64 remote_addr, u32 rkey) 3063 { 3064 rseg->raddr = cpu_to_be64(remote_addr); 3065 rseg->rkey = cpu_to_be32(rkey); 3066 rseg->reserved = 0; 3067 } 3068 3069 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg, 3070 const struct ib_send_wr *wr, void *qend, 3071 struct mlx5_ib_qp *qp, int *size) 3072 { 3073 void *seg = eseg; 3074 3075 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); 3076 3077 if (wr->send_flags & IB_SEND_IP_CSUM) 3078 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | 3079 MLX5_ETH_WQE_L4_CSUM; 3080 3081 seg += sizeof(struct mlx5_wqe_eth_seg); 3082 *size += sizeof(struct mlx5_wqe_eth_seg) / 16; 3083 3084 if (wr->opcode == IB_WR_LSO) { 3085 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr); 3086 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start); 3087 u64 left, leftlen, copysz; 3088 void *pdata = ud_wr->header; 3089 3090 left = ud_wr->hlen; 3091 eseg->mss = cpu_to_be16(ud_wr->mss); 3092 eseg->inline_hdr_sz = cpu_to_be16(left); 3093 3094 /* 3095 * check if there is space till the end of queue, if yes, 3096 * copy all in one shot, otherwise copy till the end of queue, 3097 * rollback and than the copy the left 3098 */ 3099 leftlen = qend - (void *)eseg->inline_hdr_start; 3100 copysz = min_t(u64, leftlen, left); 3101 3102 memcpy(seg - size_of_inl_hdr_start, pdata, copysz); 3103 3104 if (likely(copysz > size_of_inl_hdr_start)) { 3105 seg += ALIGN(copysz - size_of_inl_hdr_start, 16); 3106 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16; 3107 } 3108 3109 if (unlikely(copysz < left)) { /* the last wqe in the queue */ 3110 seg = mlx5_get_send_wqe(qp, 0); 3111 left -= copysz; 3112 pdata += copysz; 3113 memcpy(seg, pdata, left); 3114 seg += ALIGN(left, 16); 3115 *size += ALIGN(left, 16) / 16; 3116 } 3117 } 3118 3119 return seg; 3120 } 3121 3122 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 3123 const struct ib_send_wr *wr) 3124 { 3125 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); 3126 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); 3127 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); 3128 } 3129 3130 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 3131 { 3132 dseg->byte_count = cpu_to_be32(sg->length); 3133 dseg->lkey = cpu_to_be32(sg->lkey); 3134 dseg->addr = cpu_to_be64(sg->addr); 3135 } 3136 3137 static __be16 get_klm_octo(int npages) 3138 { 3139 return cpu_to_be16(ALIGN(npages, 8) / 2); 3140 } 3141 3142 static __be64 frwr_mkey_mask(void) 3143 { 3144 u64 result; 3145 3146 result = MLX5_MKEY_MASK_LEN | 3147 MLX5_MKEY_MASK_PAGE_SIZE | 3148 MLX5_MKEY_MASK_START_ADDR | 3149 MLX5_MKEY_MASK_EN_RINVAL | 3150 MLX5_MKEY_MASK_KEY | 3151 MLX5_MKEY_MASK_LR | 3152 MLX5_MKEY_MASK_LW | 3153 MLX5_MKEY_MASK_RR | 3154 MLX5_MKEY_MASK_RW | 3155 MLX5_MKEY_MASK_A | 3156 MLX5_MKEY_MASK_SMALL_FENCE | 3157 MLX5_MKEY_MASK_FREE; 3158 3159 return cpu_to_be64(result); 3160 } 3161 3162 static __be64 sig_mkey_mask(void) 3163 { 3164 u64 result; 3165 3166 result = MLX5_MKEY_MASK_LEN | 3167 MLX5_MKEY_MASK_PAGE_SIZE | 3168 MLX5_MKEY_MASK_START_ADDR | 3169 MLX5_MKEY_MASK_EN_SIGERR | 3170 MLX5_MKEY_MASK_EN_RINVAL | 3171 MLX5_MKEY_MASK_KEY | 3172 MLX5_MKEY_MASK_LR | 3173 MLX5_MKEY_MASK_LW | 3174 MLX5_MKEY_MASK_RR | 3175 MLX5_MKEY_MASK_RW | 3176 MLX5_MKEY_MASK_SMALL_FENCE | 3177 MLX5_MKEY_MASK_FREE | 3178 MLX5_MKEY_MASK_BSF_EN; 3179 3180 return cpu_to_be64(result); 3181 } 3182 3183 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, 3184 struct mlx5_ib_mr *mr) 3185 { 3186 int ndescs = mr->ndescs; 3187 3188 memset(umr, 0, sizeof(*umr)); 3189 3190 if (mr->access_mode == MLX5_ACCESS_MODE_KLM) 3191 /* KLMs take twice the size of MTTs */ 3192 ndescs *= 2; 3193 3194 umr->flags = MLX5_UMR_CHECK_NOT_FREE; 3195 umr->klm_octowords = get_klm_octo(ndescs); 3196 umr->mkey_mask = frwr_mkey_mask(); 3197 } 3198 3199 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) 3200 { 3201 memset(umr, 0, sizeof(*umr)); 3202 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 3203 umr->flags = 1 << 7; 3204 } 3205 3206 static __be64 get_umr_reg_mr_mask(void) 3207 { 3208 u64 result; 3209 3210 result = MLX5_MKEY_MASK_LEN | 3211 MLX5_MKEY_MASK_PAGE_SIZE | 3212 MLX5_MKEY_MASK_START_ADDR | 3213 MLX5_MKEY_MASK_PD | 3214 MLX5_MKEY_MASK_LR | 3215 MLX5_MKEY_MASK_LW | 3216 MLX5_MKEY_MASK_KEY | 3217 MLX5_MKEY_MASK_RR | 3218 MLX5_MKEY_MASK_RW | 3219 MLX5_MKEY_MASK_A | 3220 MLX5_MKEY_MASK_FREE; 3221 3222 return cpu_to_be64(result); 3223 } 3224 3225 static __be64 get_umr_unreg_mr_mask(void) 3226 { 3227 u64 result; 3228 3229 result = MLX5_MKEY_MASK_FREE; 3230 3231 return cpu_to_be64(result); 3232 } 3233 3234 static __be64 get_umr_update_mtt_mask(void) 3235 { 3236 u64 result; 3237 3238 result = MLX5_MKEY_MASK_FREE; 3239 3240 return cpu_to_be64(result); 3241 } 3242 3243 static __be64 get_umr_update_translation_mask(void) 3244 { 3245 u64 result; 3246 3247 result = MLX5_MKEY_MASK_LEN | 3248 MLX5_MKEY_MASK_PAGE_SIZE | 3249 MLX5_MKEY_MASK_START_ADDR | 3250 MLX5_MKEY_MASK_KEY | 3251 MLX5_MKEY_MASK_FREE; 3252 3253 return cpu_to_be64(result); 3254 } 3255 3256 static __be64 get_umr_update_access_mask(void) 3257 { 3258 u64 result; 3259 3260 result = MLX5_MKEY_MASK_LW | 3261 MLX5_MKEY_MASK_RR | 3262 MLX5_MKEY_MASK_RW | 3263 MLX5_MKEY_MASK_A | 3264 MLX5_MKEY_MASK_KEY | 3265 MLX5_MKEY_MASK_FREE; 3266 3267 return cpu_to_be64(result); 3268 } 3269 3270 static __be64 get_umr_update_pd_mask(void) 3271 { 3272 u64 result; 3273 3274 result = MLX5_MKEY_MASK_PD | 3275 MLX5_MKEY_MASK_KEY | 3276 MLX5_MKEY_MASK_FREE; 3277 3278 return cpu_to_be64(result); 3279 } 3280 3281 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 3282 const struct ib_send_wr *wr) 3283 { 3284 const struct mlx5_umr_wr *umrwr = umr_wr(wr); 3285 3286 memset(umr, 0, sizeof(*umr)); 3287 3288 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) 3289 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */ 3290 else 3291 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */ 3292 3293 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) { 3294 umr->klm_octowords = get_klm_octo(umrwr->npages); 3295 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) { 3296 umr->mkey_mask = get_umr_update_mtt_mask(); 3297 umr->bsf_octowords = get_klm_octo(umrwr->target.offset); 3298 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 3299 } 3300 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION) 3301 umr->mkey_mask |= get_umr_update_translation_mask(); 3302 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_ACCESS) 3303 umr->mkey_mask |= get_umr_update_access_mask(); 3304 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD) 3305 umr->mkey_mask |= get_umr_update_pd_mask(); 3306 if (!umr->mkey_mask) 3307 umr->mkey_mask = get_umr_reg_mr_mask(); 3308 } else { 3309 umr->mkey_mask = get_umr_unreg_mr_mask(); 3310 } 3311 3312 if (!wr->num_sge) 3313 umr->flags |= MLX5_UMR_INLINE; 3314 } 3315 3316 static u8 get_umr_flags(int acc) 3317 { 3318 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 3319 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 3320 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 3321 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 3322 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 3323 } 3324 3325 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, 3326 struct mlx5_ib_mr *mr, 3327 u32 key, int access) 3328 { 3329 int ndescs = ALIGN(mr->ndescs, 8) >> 1; 3330 3331 memset(seg, 0, sizeof(*seg)); 3332 3333 if (mr->access_mode == MLX5_ACCESS_MODE_MTT) 3334 seg->log2_page_size = ilog2(mr->ibmr.page_size); 3335 else if (mr->access_mode == MLX5_ACCESS_MODE_KLM) 3336 /* KLMs take twice the size of MTTs */ 3337 ndescs *= 2; 3338 3339 seg->flags = get_umr_flags(access) | mr->access_mode; 3340 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); 3341 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 3342 seg->start_addr = cpu_to_be64(mr->ibmr.iova); 3343 seg->len = cpu_to_be64(mr->ibmr.length); 3344 seg->xlt_oct_size = cpu_to_be32(ndescs); 3345 } 3346 3347 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) 3348 { 3349 memset(seg, 0, sizeof(*seg)); 3350 seg->status = MLX5_MKEY_STATUS_FREE; 3351 } 3352 3353 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, const struct ib_send_wr *wr) 3354 { 3355 const struct mlx5_umr_wr *umrwr = umr_wr(wr); 3356 3357 memset(seg, 0, sizeof(*seg)); 3358 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) { 3359 seg->status = MLX5_MKEY_STATUS_FREE; 3360 return; 3361 } 3362 3363 seg->flags = convert_access(umrwr->access_flags); 3364 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) { 3365 if (umrwr->pd) 3366 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); 3367 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr); 3368 } 3369 seg->len = cpu_to_be64(umrwr->length); 3370 seg->log2_page_size = umrwr->page_shift; 3371 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 3372 mlx5_mkey_variant(umrwr->mkey)); 3373 } 3374 3375 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, 3376 struct mlx5_ib_mr *mr, 3377 struct mlx5_ib_pd *pd) 3378 { 3379 int bcount = mr->desc_size * mr->ndescs; 3380 3381 dseg->addr = cpu_to_be64(mr->desc_map); 3382 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); 3383 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); 3384 } 3385 3386 static __be32 send_ieth(const struct ib_send_wr *wr) 3387 { 3388 switch (wr->opcode) { 3389 case IB_WR_SEND_WITH_IMM: 3390 case IB_WR_RDMA_WRITE_WITH_IMM: 3391 return wr->ex.imm_data; 3392 3393 case IB_WR_SEND_WITH_INV: 3394 return cpu_to_be32(wr->ex.invalidate_rkey); 3395 3396 default: 3397 return 0; 3398 } 3399 } 3400 3401 static u8 calc_sig(void *wqe, int size) 3402 { 3403 u8 *p = wqe; 3404 u8 res = 0; 3405 int i; 3406 3407 for (i = 0; i < size; i++) 3408 res ^= p[i]; 3409 3410 return ~res; 3411 } 3412 3413 static u8 wq_sig(void *wqe) 3414 { 3415 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 3416 } 3417 3418 static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr, 3419 void *wqe, int *sz) 3420 { 3421 struct mlx5_wqe_inline_seg *seg; 3422 void *qend = qp->sq.qend; 3423 void *addr; 3424 int inl = 0; 3425 int copy; 3426 int len; 3427 int i; 3428 3429 seg = wqe; 3430 wqe += sizeof(*seg); 3431 for (i = 0; i < wr->num_sge; i++) { 3432 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 3433 len = wr->sg_list[i].length; 3434 inl += len; 3435 3436 if (unlikely(inl > qp->max_inline_data)) 3437 return -ENOMEM; 3438 3439 if (unlikely(wqe + len > qend)) { 3440 copy = qend - wqe; 3441 memcpy(wqe, addr, copy); 3442 addr += copy; 3443 len -= copy; 3444 wqe = mlx5_get_send_wqe(qp, 0); 3445 } 3446 memcpy(wqe, addr, len); 3447 wqe += len; 3448 } 3449 3450 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 3451 3452 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 3453 3454 return 0; 3455 } 3456 3457 static u16 prot_field_size(enum ib_signature_type type) 3458 { 3459 switch (type) { 3460 case IB_SIG_TYPE_T10_DIF: 3461 return MLX5_DIF_SIZE; 3462 default: 3463 return 0; 3464 } 3465 } 3466 3467 static u8 bs_selector(int block_size) 3468 { 3469 switch (block_size) { 3470 case 512: return 0x1; 3471 case 520: return 0x2; 3472 case 4096: return 0x3; 3473 case 4160: return 0x4; 3474 case 1073741824: return 0x5; 3475 default: return 0; 3476 } 3477 } 3478 3479 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, 3480 struct mlx5_bsf_inl *inl) 3481 { 3482 /* Valid inline section and allow BSF refresh */ 3483 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | 3484 MLX5_BSF_REFRESH_DIF); 3485 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); 3486 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); 3487 /* repeating block */ 3488 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; 3489 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? 3490 MLX5_DIF_CRC : MLX5_DIF_IPCS; 3491 3492 if (domain->sig.dif.ref_remap) 3493 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; 3494 3495 if (domain->sig.dif.app_escape) { 3496 if (domain->sig.dif.ref_escape) 3497 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; 3498 else 3499 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; 3500 } 3501 3502 inl->dif_app_bitmask_check = 3503 cpu_to_be16(domain->sig.dif.apptag_check_mask); 3504 } 3505 3506 static int mlx5_set_bsf(struct ib_mr *sig_mr, 3507 struct ib_sig_attrs *sig_attrs, 3508 struct mlx5_bsf *bsf, u32 data_size) 3509 { 3510 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 3511 struct mlx5_bsf_basic *basic = &bsf->basic; 3512 struct ib_sig_domain *mem = &sig_attrs->mem; 3513 struct ib_sig_domain *wire = &sig_attrs->wire; 3514 3515 memset(bsf, 0, sizeof(*bsf)); 3516 3517 /* Basic + Extended + Inline */ 3518 basic->bsf_size_sbs = 1 << 7; 3519 /* Input domain check byte mask */ 3520 basic->check_byte_mask = sig_attrs->check_mask; 3521 basic->raw_data_size = cpu_to_be32(data_size); 3522 3523 /* Memory domain */ 3524 switch (sig_attrs->mem.sig_type) { 3525 case IB_SIG_TYPE_NONE: 3526 break; 3527 case IB_SIG_TYPE_T10_DIF: 3528 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 3529 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); 3530 mlx5_fill_inl_bsf(mem, &bsf->m_inl); 3531 break; 3532 default: 3533 return -EINVAL; 3534 } 3535 3536 /* Wire domain */ 3537 switch (sig_attrs->wire.sig_type) { 3538 case IB_SIG_TYPE_NONE: 3539 break; 3540 case IB_SIG_TYPE_T10_DIF: 3541 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 3542 mem->sig_type == wire->sig_type) { 3543 /* Same block structure */ 3544 basic->bsf_size_sbs |= 1 << 4; 3545 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 3546 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 3547 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 3548 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; 3549 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) 3550 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; 3551 } else 3552 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 3553 3554 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); 3555 mlx5_fill_inl_bsf(wire, &bsf->w_inl); 3556 break; 3557 default: 3558 return -EINVAL; 3559 } 3560 3561 return 0; 3562 } 3563 3564 static int set_sig_data_segment(const struct ib_sig_handover_wr *wr, 3565 struct mlx5_ib_qp *qp, void **seg, int *size) 3566 { 3567 struct ib_sig_attrs *sig_attrs = wr->sig_attrs; 3568 struct ib_mr *sig_mr = wr->sig_mr; 3569 struct mlx5_bsf *bsf; 3570 u32 data_len = wr->wr.sg_list->length; 3571 u32 data_key = wr->wr.sg_list->lkey; 3572 u64 data_va = wr->wr.sg_list->addr; 3573 int ret; 3574 int wqe_size; 3575 3576 if (!wr->prot || 3577 (data_key == wr->prot->lkey && 3578 data_va == wr->prot->addr && 3579 data_len == wr->prot->length)) { 3580 /** 3581 * Source domain doesn't contain signature information 3582 * or data and protection are interleaved in memory. 3583 * So need construct: 3584 * ------------------ 3585 * | data_klm | 3586 * ------------------ 3587 * | BSF | 3588 * ------------------ 3589 **/ 3590 struct mlx5_klm *data_klm = *seg; 3591 3592 data_klm->bcount = cpu_to_be32(data_len); 3593 data_klm->key = cpu_to_be32(data_key); 3594 data_klm->va = cpu_to_be64(data_va); 3595 wqe_size = ALIGN(sizeof(*data_klm), 64); 3596 } else { 3597 /** 3598 * Source domain contains signature information 3599 * So need construct a strided block format: 3600 * --------------------------- 3601 * | stride_block_ctrl | 3602 * --------------------------- 3603 * | data_klm | 3604 * --------------------------- 3605 * | prot_klm | 3606 * --------------------------- 3607 * | BSF | 3608 * --------------------------- 3609 **/ 3610 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 3611 struct mlx5_stride_block_entry *data_sentry; 3612 struct mlx5_stride_block_entry *prot_sentry; 3613 u32 prot_key = wr->prot->lkey; 3614 u64 prot_va = wr->prot->addr; 3615 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 3616 int prot_size; 3617 3618 sblock_ctrl = *seg; 3619 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 3620 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 3621 3622 prot_size = prot_field_size(sig_attrs->mem.sig_type); 3623 if (!prot_size) { 3624 pr_err("Bad block size given: %u\n", block_size); 3625 return -EINVAL; 3626 } 3627 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 3628 prot_size); 3629 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 3630 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 3631 sblock_ctrl->num_entries = cpu_to_be16(2); 3632 3633 data_sentry->bcount = cpu_to_be16(block_size); 3634 data_sentry->key = cpu_to_be32(data_key); 3635 data_sentry->va = cpu_to_be64(data_va); 3636 data_sentry->stride = cpu_to_be16(block_size); 3637 3638 prot_sentry->bcount = cpu_to_be16(prot_size); 3639 prot_sentry->key = cpu_to_be32(prot_key); 3640 prot_sentry->va = cpu_to_be64(prot_va); 3641 prot_sentry->stride = cpu_to_be16(prot_size); 3642 3643 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 3644 sizeof(*prot_sentry), 64); 3645 } 3646 3647 *seg += wqe_size; 3648 *size += wqe_size / 16; 3649 if (unlikely((*seg == qp->sq.qend))) 3650 *seg = mlx5_get_send_wqe(qp, 0); 3651 3652 bsf = *seg; 3653 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 3654 if (ret) 3655 return -EINVAL; 3656 3657 *seg += sizeof(*bsf); 3658 *size += sizeof(*bsf) / 16; 3659 if (unlikely((*seg == qp->sq.qend))) 3660 *seg = mlx5_get_send_wqe(qp, 0); 3661 3662 return 0; 3663 } 3664 3665 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 3666 const struct ib_sig_handover_wr *wr, u32 nelements, 3667 u32 length, u32 pdn) 3668 { 3669 struct ib_mr *sig_mr = wr->sig_mr; 3670 u32 sig_key = sig_mr->rkey; 3671 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 3672 3673 memset(seg, 0, sizeof(*seg)); 3674 3675 seg->flags = get_umr_flags(wr->access_flags) | 3676 MLX5_ACCESS_MODE_KLM; 3677 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 3678 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 3679 MLX5_MKEY_BSF_EN | pdn); 3680 seg->len = cpu_to_be64(length); 3681 seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements))); 3682 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 3683 } 3684 3685 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 3686 u32 nelements) 3687 { 3688 memset(umr, 0, sizeof(*umr)); 3689 3690 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 3691 umr->klm_octowords = get_klm_octo(nelements); 3692 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 3693 umr->mkey_mask = sig_mkey_mask(); 3694 } 3695 3696 3697 static int set_sig_umr_wr(const struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp, 3698 void **seg, int *size) 3699 { 3700 const struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr); 3701 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr); 3702 u32 pdn = get_pd(qp)->pdn; 3703 u32 klm_oct_size; 3704 int region_len, ret; 3705 3706 if (unlikely(wr->wr.num_sge != 1) || 3707 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) || 3708 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || 3709 unlikely(!sig_mr->sig->sig_status_checked)) 3710 return -EINVAL; 3711 3712 /* length of the protected region, data + protection */ 3713 region_len = wr->wr.sg_list->length; 3714 if (wr->prot && 3715 (wr->prot->lkey != wr->wr.sg_list->lkey || 3716 wr->prot->addr != wr->wr.sg_list->addr || 3717 wr->prot->length != wr->wr.sg_list->length)) 3718 region_len += wr->prot->length; 3719 3720 /** 3721 * KLM octoword size - if protection was provided 3722 * then we use strided block format (3 octowords), 3723 * else we use single KLM (1 octoword) 3724 **/ 3725 klm_oct_size = wr->prot ? 3 : 1; 3726 3727 set_sig_umr_segment(*seg, klm_oct_size); 3728 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3729 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3730 if (unlikely((*seg == qp->sq.qend))) 3731 *seg = mlx5_get_send_wqe(qp, 0); 3732 3733 set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn); 3734 *seg += sizeof(struct mlx5_mkey_seg); 3735 *size += sizeof(struct mlx5_mkey_seg) / 16; 3736 if (unlikely((*seg == qp->sq.qend))) 3737 *seg = mlx5_get_send_wqe(qp, 0); 3738 3739 ret = set_sig_data_segment(wr, qp, seg, size); 3740 if (ret) 3741 return ret; 3742 3743 sig_mr->sig->sig_status_checked = false; 3744 return 0; 3745 } 3746 3747 static int set_psv_wr(struct ib_sig_domain *domain, 3748 u32 psv_idx, void **seg, int *size) 3749 { 3750 struct mlx5_seg_set_psv *psv_seg = *seg; 3751 3752 memset(psv_seg, 0, sizeof(*psv_seg)); 3753 psv_seg->psv_num = cpu_to_be32(psv_idx); 3754 switch (domain->sig_type) { 3755 case IB_SIG_TYPE_NONE: 3756 break; 3757 case IB_SIG_TYPE_T10_DIF: 3758 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 3759 domain->sig.dif.app_tag); 3760 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 3761 break; 3762 default: 3763 pr_err("Bad signature type given.\n"); 3764 return 1; 3765 } 3766 3767 *seg += sizeof(*psv_seg); 3768 *size += sizeof(*psv_seg) / 16; 3769 3770 return 0; 3771 } 3772 3773 static int set_reg_wr(struct mlx5_ib_qp *qp, 3774 const struct ib_reg_wr *wr, 3775 void **seg, int *size) 3776 { 3777 struct mlx5_ib_mr *mr = to_mmr(wr->mr); 3778 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); 3779 3780 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { 3781 mlx5_ib_warn(to_mdev(qp->ibqp.device), 3782 "Invalid IB_SEND_INLINE send flag\n"); 3783 return -EINVAL; 3784 } 3785 3786 set_reg_umr_seg(*seg, mr); 3787 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3788 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3789 if (unlikely((*seg == qp->sq.qend))) 3790 *seg = mlx5_get_send_wqe(qp, 0); 3791 3792 set_reg_mkey_seg(*seg, mr, wr->key, wr->access); 3793 *seg += sizeof(struct mlx5_mkey_seg); 3794 *size += sizeof(struct mlx5_mkey_seg) / 16; 3795 if (unlikely((*seg == qp->sq.qend))) 3796 *seg = mlx5_get_send_wqe(qp, 0); 3797 3798 set_reg_data_seg(*seg, mr, pd); 3799 *seg += sizeof(struct mlx5_wqe_data_seg); 3800 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 3801 3802 return 0; 3803 } 3804 3805 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size) 3806 { 3807 set_linv_umr_seg(*seg); 3808 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3809 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3810 if (unlikely((*seg == qp->sq.qend))) 3811 *seg = mlx5_get_send_wqe(qp, 0); 3812 set_linv_mkey_seg(*seg); 3813 *seg += sizeof(struct mlx5_mkey_seg); 3814 *size += sizeof(struct mlx5_mkey_seg) / 16; 3815 if (unlikely((*seg == qp->sq.qend))) 3816 *seg = mlx5_get_send_wqe(qp, 0); 3817 } 3818 3819 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16) 3820 { 3821 __be32 *p = NULL; 3822 int tidx = idx; 3823 int i, j; 3824 3825 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx)); 3826 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 3827 if ((i & 0xf) == 0) { 3828 void *buf = mlx5_get_send_wqe(qp, tidx); 3829 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1); 3830 p = buf; 3831 j = 0; 3832 } 3833 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 3834 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 3835 be32_to_cpu(p[j + 3])); 3836 } 3837 } 3838 3839 static u8 get_fence(u8 fence, const struct ib_send_wr *wr) 3840 { 3841 if (unlikely(wr->opcode == IB_WR_LOCAL_INV && 3842 wr->send_flags & IB_SEND_FENCE)) 3843 return MLX5_FENCE_MODE_STRONG_ORDERING; 3844 3845 if (unlikely(fence)) { 3846 if (wr->send_flags & IB_SEND_FENCE) 3847 return MLX5_FENCE_MODE_SMALL_AND_FENCE; 3848 else 3849 return fence; 3850 } else if (unlikely(wr->send_flags & IB_SEND_FENCE)) { 3851 return MLX5_FENCE_MODE_FENCE; 3852 } 3853 3854 return 0; 3855 } 3856 3857 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 3858 struct mlx5_wqe_ctrl_seg **ctrl, 3859 const struct ib_send_wr *wr, unsigned *idx, 3860 int *size, int nreq, int send_flags) 3861 { 3862 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) 3863 return -ENOMEM; 3864 3865 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 3866 *seg = mlx5_get_send_wqe(qp, *idx); 3867 *ctrl = *seg; 3868 *(uint32_t *)(*seg + 8) = 0; 3869 (*ctrl)->imm = send_ieth(wr); 3870 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 3871 (send_flags & IB_SEND_SIGNALED ? 3872 MLX5_WQE_CTRL_CQ_UPDATE : 0) | 3873 (send_flags & IB_SEND_SOLICITED ? 3874 MLX5_WQE_CTRL_SOLICITED : 0); 3875 3876 *seg += sizeof(**ctrl); 3877 *size = sizeof(**ctrl) / 16; 3878 3879 return 0; 3880 } 3881 3882 static void finish_wqe(struct mlx5_ib_qp *qp, 3883 struct mlx5_wqe_ctrl_seg *ctrl, 3884 u8 size, unsigned idx, u64 wr_id, 3885 int nreq, u8 fence, u8 next_fence, 3886 u32 mlx5_opcode) 3887 { 3888 u8 opmod = 0; 3889 3890 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 3891 mlx5_opcode | ((u32)opmod << 24)); 3892 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); 3893 ctrl->fm_ce_se |= fence; 3894 qp->fm_cache = next_fence; 3895 if (unlikely(qp->wq_sig)) 3896 ctrl->signature = wq_sig(ctrl); 3897 3898 qp->sq.wrid[idx] = wr_id; 3899 qp->sq.w_list[idx].opcode = mlx5_opcode; 3900 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 3901 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 3902 qp->sq.w_list[idx].next = qp->sq.cur_post; 3903 } 3904 3905 3906 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 3907 const struct ib_send_wr **bad_wr) 3908 { 3909 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 3910 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3911 struct mlx5_core_dev *mdev = dev->mdev; 3912 struct mlx5_ib_qp *qp; 3913 struct mlx5_ib_mr *mr; 3914 struct mlx5_wqe_data_seg *dpseg; 3915 struct mlx5_wqe_xrc_seg *xrc; 3916 struct mlx5_bf *bf; 3917 int uninitialized_var(size); 3918 void *qend; 3919 unsigned long flags; 3920 unsigned idx; 3921 int err = 0; 3922 int inl = 0; 3923 int num_sge; 3924 void *seg; 3925 int nreq; 3926 int i; 3927 u8 next_fence = 0; 3928 u8 fence; 3929 3930 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 3931 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr); 3932 3933 qp = to_mqp(ibqp); 3934 bf = &qp->bf; 3935 qend = qp->sq.qend; 3936 3937 spin_lock_irqsave(&qp->sq.lock, flags); 3938 3939 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 3940 err = -EIO; 3941 *bad_wr = wr; 3942 nreq = 0; 3943 goto out; 3944 } 3945 3946 for (nreq = 0; wr; nreq++, wr = wr->next) { 3947 if (unlikely(wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { 3948 mlx5_ib_warn(dev, "\n"); 3949 err = -EINVAL; 3950 *bad_wr = wr; 3951 goto out; 3952 } 3953 3954 fence = qp->fm_cache; 3955 num_sge = wr->num_sge; 3956 if (unlikely(num_sge > qp->sq.max_gs)) { 3957 mlx5_ib_warn(dev, "\n"); 3958 err = -EINVAL; 3959 *bad_wr = wr; 3960 goto out; 3961 } 3962 3963 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq, wr->send_flags); 3964 if (err) { 3965 mlx5_ib_warn(dev, "\n"); 3966 err = -ENOMEM; 3967 *bad_wr = wr; 3968 goto out; 3969 } 3970 3971 switch (ibqp->qp_type) { 3972 case IB_QPT_XRC_INI: 3973 xrc = seg; 3974 seg += sizeof(*xrc); 3975 size += sizeof(*xrc) / 16; 3976 /* fall through */ 3977 case IB_QPT_RC: 3978 switch (wr->opcode) { 3979 case IB_WR_RDMA_READ: 3980 case IB_WR_RDMA_WRITE: 3981 case IB_WR_RDMA_WRITE_WITH_IMM: 3982 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 3983 rdma_wr(wr)->rkey); 3984 seg += sizeof(struct mlx5_wqe_raddr_seg); 3985 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 3986 break; 3987 3988 case IB_WR_ATOMIC_CMP_AND_SWP: 3989 case IB_WR_ATOMIC_FETCH_AND_ADD: 3990 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 3991 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 3992 err = -ENOSYS; 3993 *bad_wr = wr; 3994 goto out; 3995 3996 case IB_WR_LOCAL_INV: 3997 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 3998 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 3999 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 4000 set_linv_wr(qp, &seg, &size); 4001 num_sge = 0; 4002 break; 4003 4004 case IB_WR_REG_MR: 4005 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4006 qp->sq.wr_data[idx] = IB_WR_REG_MR; 4007 ctrl->imm = cpu_to_be32(reg_wr(wr)->key); 4008 err = set_reg_wr(qp, reg_wr(wr), &seg, &size); 4009 if (err) { 4010 *bad_wr = wr; 4011 goto out; 4012 } 4013 num_sge = 0; 4014 break; 4015 4016 case IB_WR_REG_SIG_MR: 4017 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; 4018 mr = to_mmr(sig_handover_wr(wr)->sig_mr); 4019 4020 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 4021 err = set_sig_umr_wr(wr, qp, &seg, &size); 4022 if (err) { 4023 mlx5_ib_warn(dev, "\n"); 4024 *bad_wr = wr; 4025 goto out; 4026 } 4027 4028 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 4029 nreq, get_fence(fence, wr), 4030 next_fence, MLX5_OPCODE_UMR); 4031 /* 4032 * SET_PSV WQEs are not signaled and solicited 4033 * on error 4034 */ 4035 err = begin_wqe(qp, &seg, &ctrl, wr, 4036 &idx, &size, nreq, IB_SEND_SOLICITED); 4037 if (err) { 4038 mlx5_ib_warn(dev, "\n"); 4039 err = -ENOMEM; 4040 *bad_wr = wr; 4041 goto out; 4042 } 4043 4044 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem, 4045 mr->sig->psv_memory.psv_idx, &seg, 4046 &size); 4047 if (err) { 4048 mlx5_ib_warn(dev, "\n"); 4049 *bad_wr = wr; 4050 goto out; 4051 } 4052 4053 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 4054 nreq, get_fence(fence, wr), 4055 next_fence, MLX5_OPCODE_SET_PSV); 4056 err = begin_wqe(qp, &seg, &ctrl, wr, 4057 &idx, &size, nreq, wr->send_flags); 4058 if (err) { 4059 mlx5_ib_warn(dev, "\n"); 4060 err = -ENOMEM; 4061 *bad_wr = wr; 4062 goto out; 4063 } 4064 4065 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4066 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire, 4067 mr->sig->psv_wire.psv_idx, &seg, 4068 &size); 4069 if (err) { 4070 mlx5_ib_warn(dev, "\n"); 4071 *bad_wr = wr; 4072 goto out; 4073 } 4074 4075 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 4076 nreq, get_fence(fence, wr), 4077 next_fence, MLX5_OPCODE_SET_PSV); 4078 num_sge = 0; 4079 goto skip_psv; 4080 4081 default: 4082 break; 4083 } 4084 break; 4085 4086 case IB_QPT_UC: 4087 switch (wr->opcode) { 4088 case IB_WR_RDMA_WRITE: 4089 case IB_WR_RDMA_WRITE_WITH_IMM: 4090 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 4091 rdma_wr(wr)->rkey); 4092 seg += sizeof(struct mlx5_wqe_raddr_seg); 4093 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 4094 break; 4095 4096 default: 4097 break; 4098 } 4099 break; 4100 4101 case IB_QPT_SMI: 4102 case MLX5_IB_QPT_HW_GSI: 4103 set_datagram_seg(seg, wr); 4104 seg += sizeof(struct mlx5_wqe_datagram_seg); 4105 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4106 if (unlikely((seg == qend))) 4107 seg = mlx5_get_send_wqe(qp, 0); 4108 break; 4109 case IB_QPT_UD: 4110 set_datagram_seg(seg, wr); 4111 seg += sizeof(struct mlx5_wqe_datagram_seg); 4112 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4113 4114 if (unlikely((seg == qend))) 4115 seg = mlx5_get_send_wqe(qp, 0); 4116 4117 /* handle qp that supports ud offload */ 4118 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) { 4119 struct mlx5_wqe_eth_pad *pad; 4120 4121 pad = seg; 4122 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad)); 4123 seg += sizeof(struct mlx5_wqe_eth_pad); 4124 size += sizeof(struct mlx5_wqe_eth_pad) / 16; 4125 4126 seg = set_eth_seg(seg, wr, qend, qp, &size); 4127 4128 if (unlikely((seg == qend))) 4129 seg = mlx5_get_send_wqe(qp, 0); 4130 } 4131 break; 4132 case MLX5_IB_QPT_REG_UMR: 4133 if (wr->opcode != MLX5_IB_WR_UMR) { 4134 err = -EINVAL; 4135 mlx5_ib_warn(dev, "bad opcode\n"); 4136 goto out; 4137 } 4138 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 4139 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); 4140 set_reg_umr_segment(seg, wr); 4141 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4142 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4143 if (unlikely((seg == qend))) 4144 seg = mlx5_get_send_wqe(qp, 0); 4145 set_reg_mkey_segment(seg, wr); 4146 seg += sizeof(struct mlx5_mkey_seg); 4147 size += sizeof(struct mlx5_mkey_seg) / 16; 4148 if (unlikely((seg == qend))) 4149 seg = mlx5_get_send_wqe(qp, 0); 4150 break; 4151 4152 default: 4153 break; 4154 } 4155 4156 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 4157 int uninitialized_var(sz); 4158 4159 err = set_data_inl_seg(qp, wr, seg, &sz); 4160 if (unlikely(err)) { 4161 mlx5_ib_warn(dev, "\n"); 4162 *bad_wr = wr; 4163 goto out; 4164 } 4165 inl = 1; 4166 size += sz; 4167 } else { 4168 dpseg = seg; 4169 for (i = 0; i < num_sge; i++) { 4170 if (unlikely(dpseg == qend)) { 4171 seg = mlx5_get_send_wqe(qp, 0); 4172 dpseg = seg; 4173 } 4174 if (likely(wr->sg_list[i].length)) { 4175 set_data_ptr_seg(dpseg, wr->sg_list + i); 4176 size += sizeof(struct mlx5_wqe_data_seg) / 16; 4177 dpseg++; 4178 } 4179 } 4180 } 4181 4182 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 4183 get_fence(fence, wr), next_fence, 4184 mlx5_ib_opcode[wr->opcode]); 4185 skip_psv: 4186 if (0) 4187 dump_wqe(qp, idx, size); 4188 } 4189 4190 out: 4191 if (likely(nreq)) { 4192 qp->sq.head += nreq; 4193 4194 /* Make sure that descriptors are written before 4195 * updating doorbell record and ringing the doorbell 4196 */ 4197 wmb(); 4198 4199 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 4200 4201 /* Make sure doorbell record is visible to the HCA before 4202 * we hit doorbell */ 4203 wmb(); 4204 4205 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, 4206 MLX5_GET_DOORBELL_LOCK(&bf->lock32)); 4207 /* Make sure doorbells don't leak out of SQ spinlock 4208 * and reach the HCA out of order. 4209 */ 4210 bf->offset ^= bf->buf_size; 4211 } 4212 4213 spin_unlock_irqrestore(&qp->sq.lock, flags); 4214 4215 return err; 4216 } 4217 4218 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 4219 { 4220 sig->signature = calc_sig(sig, size); 4221 } 4222 4223 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 4224 const struct ib_recv_wr **bad_wr) 4225 { 4226 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4227 struct mlx5_wqe_data_seg *scat; 4228 struct mlx5_rwqe_sig *sig; 4229 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4230 struct mlx5_core_dev *mdev = dev->mdev; 4231 unsigned long flags; 4232 int err = 0; 4233 int nreq; 4234 int ind; 4235 int i; 4236 4237 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4238 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr); 4239 4240 spin_lock_irqsave(&qp->rq.lock, flags); 4241 4242 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 4243 err = -EIO; 4244 *bad_wr = wr; 4245 nreq = 0; 4246 goto out; 4247 } 4248 4249 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 4250 4251 for (nreq = 0; wr; nreq++, wr = wr->next) { 4252 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 4253 err = -ENOMEM; 4254 *bad_wr = wr; 4255 goto out; 4256 } 4257 4258 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 4259 err = -EINVAL; 4260 *bad_wr = wr; 4261 goto out; 4262 } 4263 4264 scat = get_recv_wqe(qp, ind); 4265 if (qp->wq_sig) 4266 scat++; 4267 4268 for (i = 0; i < wr->num_sge; i++) 4269 set_data_ptr_seg(scat + i, wr->sg_list + i); 4270 4271 if (i < qp->rq.max_gs) { 4272 scat[i].byte_count = 0; 4273 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 4274 scat[i].addr = 0; 4275 } 4276 4277 if (qp->wq_sig) { 4278 sig = (struct mlx5_rwqe_sig *)scat; 4279 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 4280 } 4281 4282 qp->rq.wrid[ind] = wr->wr_id; 4283 4284 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 4285 } 4286 4287 out: 4288 if (likely(nreq)) { 4289 qp->rq.head += nreq; 4290 4291 /* Make sure that descriptors are written before 4292 * doorbell record. 4293 */ 4294 wmb(); 4295 4296 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 4297 } 4298 4299 spin_unlock_irqrestore(&qp->rq.lock, flags); 4300 4301 return err; 4302 } 4303 4304 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4305 { 4306 switch (mlx5_state) { 4307 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4308 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4309 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4310 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4311 case MLX5_QP_STATE_SQ_DRAINING: 4312 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4313 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4314 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4315 default: return -1; 4316 } 4317 } 4318 4319 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4320 { 4321 switch (mlx5_mig_state) { 4322 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4323 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4324 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4325 default: return -1; 4326 } 4327 } 4328 4329 static int to_ib_qp_access_flags(int mlx5_flags) 4330 { 4331 int ib_flags = 0; 4332 4333 if (mlx5_flags & MLX5_QP_BIT_RRE) 4334 ib_flags |= IB_ACCESS_REMOTE_READ; 4335 if (mlx5_flags & MLX5_QP_BIT_RWE) 4336 ib_flags |= IB_ACCESS_REMOTE_WRITE; 4337 if (mlx5_flags & MLX5_QP_BIT_RAE) 4338 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 4339 4340 return ib_flags; 4341 } 4342 4343 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr, 4344 struct mlx5_qp_path *path) 4345 { 4346 struct mlx5_core_dev *dev = ibdev->mdev; 4347 4348 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr)); 4349 ib_ah_attr->port_num = path->port; 4350 4351 if (ib_ah_attr->port_num == 0 || 4352 ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports)) 4353 return; 4354 4355 ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf; 4356 4357 ib_ah_attr->dlid = be16_to_cpu(path->rlid); 4358 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f; 4359 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0; 4360 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0; 4361 if (ib_ah_attr->ah_flags) { 4362 ib_ah_attr->grh.sgid_index = path->mgid_index; 4363 ib_ah_attr->grh.hop_limit = path->hop_limit; 4364 ib_ah_attr->grh.traffic_class = 4365 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff; 4366 ib_ah_attr->grh.flow_label = 4367 be32_to_cpu(path->tclass_flowlabel) & 0xfffff; 4368 memcpy(ib_ah_attr->grh.dgid.raw, 4369 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw)); 4370 } 4371 } 4372 4373 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4374 struct mlx5_ib_sq *sq, 4375 u8 *sq_state) 4376 { 4377 void *out; 4378 void *sqc; 4379 int inlen; 4380 int err; 4381 4382 inlen = MLX5_ST_SZ_BYTES(query_sq_out); 4383 out = mlx5_vzalloc(inlen); 4384 if (!out) 4385 return -ENOMEM; 4386 4387 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out); 4388 if (err) 4389 goto out; 4390 4391 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context); 4392 *sq_state = MLX5_GET(sqc, sqc, state); 4393 sq->state = *sq_state; 4394 4395 out: 4396 kvfree(out); 4397 return err; 4398 } 4399 4400 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4401 struct mlx5_ib_rq *rq, 4402 u8 *rq_state) 4403 { 4404 void *out; 4405 void *rqc; 4406 int inlen; 4407 int err; 4408 4409 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4410 out = mlx5_vzalloc(inlen); 4411 if (!out) 4412 return -ENOMEM; 4413 4414 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4415 if (err) 4416 goto out; 4417 4418 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4419 *rq_state = MLX5_GET(rqc, rqc, state); 4420 rq->state = *rq_state; 4421 4422 out: 4423 kvfree(out); 4424 return err; 4425 } 4426 4427 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4428 struct mlx5_ib_qp *qp, u8 *qp_state) 4429 { 4430 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4431 [MLX5_RQC_STATE_RST] = { 4432 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4433 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4434 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4435 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4436 }, 4437 [MLX5_RQC_STATE_RDY] = { 4438 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4439 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4440 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4441 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4442 }, 4443 [MLX5_RQC_STATE_ERR] = { 4444 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4445 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4446 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4447 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4448 }, 4449 [MLX5_RQ_STATE_NA] = { 4450 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4451 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4452 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4453 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4454 }, 4455 }; 4456 4457 *qp_state = sqrq_trans[rq_state][sq_state]; 4458 4459 if (*qp_state == MLX5_QP_STATE_BAD) { 4460 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4461 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4462 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4463 return -EINVAL; 4464 } 4465 4466 if (*qp_state == MLX5_QP_STATE) 4467 *qp_state = qp->state; 4468 4469 return 0; 4470 } 4471 4472 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4473 struct mlx5_ib_qp *qp, 4474 u8 *raw_packet_qp_state) 4475 { 4476 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4477 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4478 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4479 int err; 4480 u8 sq_state = MLX5_SQ_STATE_NA; 4481 u8 rq_state = MLX5_RQ_STATE_NA; 4482 4483 if (qp->sq.wqe_cnt) { 4484 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4485 if (err) 4486 return err; 4487 } 4488 4489 if (qp->rq.wqe_cnt) { 4490 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4491 if (err) 4492 return err; 4493 } 4494 4495 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4496 raw_packet_qp_state); 4497 } 4498 4499 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4500 struct ib_qp_attr *qp_attr) 4501 { 4502 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 4503 struct mlx5_qp_context *context; 4504 int mlx5_state; 4505 u32 *outb; 4506 int err = 0; 4507 4508 outb = kzalloc(outlen, GFP_KERNEL); 4509 if (!outb) 4510 return -ENOMEM; 4511 4512 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, 4513 outlen); 4514 if (err) 4515 goto out; 4516 4517 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */ 4518 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc); 4519 4520 mlx5_state = be32_to_cpu(context->flags) >> 28; 4521 4522 qp->state = to_ib_qp_state(mlx5_state); 4523 qp_attr->path_mtu = context->mtu_msgmax >> 5; 4524 qp_attr->path_mig_state = 4525 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 4526 qp_attr->qkey = be32_to_cpu(context->qkey); 4527 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 4528 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 4529 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 4530 qp_attr->qp_access_flags = 4531 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 4532 4533 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 4534 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 4535 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 4536 qp_attr->alt_pkey_index = 4537 be16_to_cpu(context->alt_path.pkey_index); 4538 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num; 4539 } 4540 4541 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index); 4542 qp_attr->port_num = context->pri_path.port; 4543 4544 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 4545 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 4546 4547 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 4548 4549 qp_attr->max_dest_rd_atomic = 4550 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 4551 qp_attr->min_rnr_timer = 4552 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 4553 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 4554 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 4555 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 4556 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 4557 4558 out: 4559 kfree(outb); 4560 return err; 4561 } 4562 4563 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 4564 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 4565 { 4566 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4567 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4568 int err = 0; 4569 u8 raw_packet_qp_state; 4570 4571 if (ibqp->rwq_ind_tbl) 4572 return -ENOSYS; 4573 4574 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4575 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 4576 qp_init_attr); 4577 4578 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 4579 /* 4580 * Wait for any outstanding page faults, in case the user frees memory 4581 * based upon this query's result. 4582 */ 4583 flush_workqueue(mlx5_ib_page_fault_wq); 4584 #endif 4585 4586 mutex_lock(&qp->mutex); 4587 4588 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 4589 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 4590 if (err) 4591 goto out; 4592 qp->state = raw_packet_qp_state; 4593 qp_attr->port_num = 1; 4594 } else { 4595 err = query_qp_attr(dev, qp, qp_attr); 4596 if (err) 4597 goto out; 4598 } 4599 4600 qp_attr->qp_state = qp->state; 4601 qp_attr->cur_qp_state = qp_attr->qp_state; 4602 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 4603 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 4604 4605 if (!ibqp->uobject) { 4606 qp_attr->cap.max_send_wr = qp->sq.max_post; 4607 qp_attr->cap.max_send_sge = qp->sq.max_gs; 4608 qp_init_attr->qp_context = ibqp->qp_context; 4609 } else { 4610 qp_attr->cap.max_send_wr = 0; 4611 qp_attr->cap.max_send_sge = 0; 4612 } 4613 4614 qp_init_attr->qp_type = ibqp->qp_type; 4615 qp_init_attr->recv_cq = ibqp->recv_cq; 4616 qp_init_attr->send_cq = ibqp->send_cq; 4617 qp_init_attr->srq = ibqp->srq; 4618 qp_attr->cap.max_inline_data = qp->max_inline_data; 4619 4620 qp_init_attr->cap = qp_attr->cap; 4621 4622 qp_init_attr->create_flags = 0; 4623 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 4624 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 4625 4626 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 4627 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; 4628 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 4629 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; 4630 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 4631 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; 4632 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 4633 qp_init_attr->create_flags |= MLX5_IB_QP_CREATE_SQPN_QP1; 4634 4635 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 4636 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 4637 4638 out: 4639 mutex_unlock(&qp->mutex); 4640 return err; 4641 } 4642 4643 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 4644 struct ib_udata *udata) 4645 { 4646 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4647 struct mlx5_ib_xrcd *xrcd; 4648 int err; 4649 4650 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 4651 return ERR_PTR(-ENOSYS); 4652 4653 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 4654 if (!xrcd) 4655 return ERR_PTR(-ENOMEM); 4656 4657 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn); 4658 if (err) { 4659 kfree(xrcd); 4660 return ERR_PTR(-ENOMEM); 4661 } 4662 4663 return &xrcd->ibxrcd; 4664 } 4665 4666 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata) 4667 { 4668 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 4669 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 4670 int err; 4671 4672 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn); 4673 if (err) 4674 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 4675 4676 kfree(xrcd); 4677 return 0; 4678 } 4679 4680 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 4681 { 4682 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 4683 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 4684 struct ib_event event; 4685 4686 if (rwq->ibwq.event_handler) { 4687 event.device = rwq->ibwq.device; 4688 event.element.wq = &rwq->ibwq; 4689 switch (type) { 4690 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 4691 event.event = IB_EVENT_WQ_FATAL; 4692 break; 4693 default: 4694 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 4695 return; 4696 } 4697 4698 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 4699 } 4700 } 4701 4702 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 4703 struct ib_wq_init_attr *init_attr) 4704 { 4705 struct mlx5_ib_dev *dev; 4706 __be64 *rq_pas0; 4707 void *in; 4708 void *rqc; 4709 void *wq; 4710 int inlen; 4711 int err; 4712 4713 dev = to_mdev(pd->device); 4714 4715 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 4716 in = mlx5_vzalloc(inlen); 4717 if (!in) 4718 return -ENOMEM; 4719 4720 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 4721 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 4722 MLX5_SET(rqc, rqc, mem_rq_type, 4723 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE); 4724 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 4725 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 4726 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 4727 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 4728 wq = MLX5_ADDR_OF(rqc, rqc, wq); 4729 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 4730 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 4731 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 4732 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 4733 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 4734 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 4735 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 4736 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 4737 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 4738 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 4739 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); 4740 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp); 4741 kvfree(in); 4742 return err; 4743 } 4744 4745 static int set_user_rq_size(struct mlx5_ib_dev *dev, 4746 struct ib_wq_init_attr *wq_init_attr, 4747 struct mlx5_ib_create_wq *ucmd, 4748 struct mlx5_ib_rwq *rwq) 4749 { 4750 /* Sanity check RQ size before proceeding */ 4751 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 4752 return -EINVAL; 4753 4754 if (!ucmd->rq_wqe_count) 4755 return -EINVAL; 4756 4757 rwq->wqe_count = ucmd->rq_wqe_count; 4758 rwq->wqe_shift = ucmd->rq_wqe_shift; 4759 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift); 4760 rwq->log_rq_stride = rwq->wqe_shift; 4761 rwq->log_rq_size = ilog2(rwq->wqe_count); 4762 return 0; 4763 } 4764 4765 static int prepare_user_rq(struct ib_pd *pd, 4766 struct ib_wq_init_attr *init_attr, 4767 struct ib_udata *udata, 4768 struct mlx5_ib_rwq *rwq) 4769 { 4770 struct mlx5_ib_dev *dev = to_mdev(pd->device); 4771 struct mlx5_ib_create_wq ucmd = {}; 4772 int err; 4773 size_t required_cmd_sz; 4774 4775 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 4776 if (udata->inlen < required_cmd_sz) { 4777 mlx5_ib_dbg(dev, "invalid inlen\n"); 4778 return -EINVAL; 4779 } 4780 4781 if (udata->inlen > sizeof(ucmd) && 4782 !ib_is_udata_cleared(udata, sizeof(ucmd), 4783 udata->inlen - sizeof(ucmd))) { 4784 mlx5_ib_dbg(dev, "inlen is not supported\n"); 4785 return -EOPNOTSUPP; 4786 } 4787 4788 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 4789 mlx5_ib_dbg(dev, "copy failed\n"); 4790 return -EFAULT; 4791 } 4792 4793 if (ucmd.comp_mask) { 4794 mlx5_ib_dbg(dev, "invalid comp mask\n"); 4795 return -EOPNOTSUPP; 4796 } 4797 4798 if (ucmd.reserved) { 4799 mlx5_ib_dbg(dev, "invalid reserved\n"); 4800 return -EOPNOTSUPP; 4801 } 4802 4803 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 4804 if (err) { 4805 mlx5_ib_dbg(dev, "err %d\n", err); 4806 return err; 4807 } 4808 4809 err = create_user_rq(dev, pd, rwq, &ucmd); 4810 if (err) { 4811 mlx5_ib_dbg(dev, "err %d\n", err); 4812 if (err) 4813 return err; 4814 } 4815 4816 rwq->user_index = ucmd.user_index; 4817 return 0; 4818 } 4819 4820 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 4821 struct ib_wq_init_attr *init_attr, 4822 struct ib_udata *udata) 4823 { 4824 struct mlx5_ib_dev *dev; 4825 struct mlx5_ib_rwq *rwq; 4826 struct mlx5_ib_create_wq_resp resp = {}; 4827 size_t min_resp_len; 4828 int err; 4829 4830 if (!udata) 4831 return ERR_PTR(-ENOSYS); 4832 4833 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4834 if (udata->outlen && udata->outlen < min_resp_len) 4835 return ERR_PTR(-EINVAL); 4836 4837 dev = to_mdev(pd->device); 4838 switch (init_attr->wq_type) { 4839 case IB_WQT_RQ: 4840 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 4841 if (!rwq) 4842 return ERR_PTR(-ENOMEM); 4843 err = prepare_user_rq(pd, init_attr, udata, rwq); 4844 if (err) 4845 goto err; 4846 err = create_rq(rwq, pd, init_attr); 4847 if (err) 4848 goto err_user_rq; 4849 break; 4850 default: 4851 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 4852 init_attr->wq_type); 4853 return ERR_PTR(-EINVAL); 4854 } 4855 4856 rwq->ibwq.wq_num = rwq->core_qp.qpn; 4857 rwq->ibwq.state = IB_WQS_RESET; 4858 if (udata->outlen) { 4859 resp.response_length = offsetof(typeof(resp), response_length) + 4860 sizeof(resp.response_length); 4861 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4862 if (err) 4863 goto err_copy; 4864 } 4865 4866 rwq->core_qp.event = mlx5_ib_wq_event; 4867 rwq->ibwq.event_handler = init_attr->event_handler; 4868 return &rwq->ibwq; 4869 4870 err_copy: 4871 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 4872 err_user_rq: 4873 destroy_user_rq(pd, rwq, udata); 4874 err: 4875 kfree(rwq); 4876 return ERR_PTR(err); 4877 } 4878 4879 void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata) 4880 { 4881 struct mlx5_ib_dev *dev = to_mdev(wq->device); 4882 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 4883 4884 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 4885 destroy_user_rq(wq->pd, rwq, udata); 4886 kfree(rwq); 4887 } 4888 4889 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 4890 struct ib_rwq_ind_table_init_attr *init_attr, 4891 struct ib_udata *udata) 4892 { 4893 struct mlx5_ib_dev *dev = to_mdev(device); 4894 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl; 4895 int sz = 1 << init_attr->log_ind_tbl_size; 4896 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 4897 size_t min_resp_len; 4898 int inlen; 4899 int err; 4900 int i; 4901 u32 *in; 4902 void *rqtc; 4903 4904 if (udata->inlen > 0 && 4905 !ib_is_udata_cleared(udata, 0, 4906 udata->inlen)) 4907 return ERR_PTR(-EOPNOTSUPP); 4908 4909 if (init_attr->log_ind_tbl_size > 4910 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 4911 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 4912 init_attr->log_ind_tbl_size, 4913 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 4914 return ERR_PTR(-EINVAL); 4915 } 4916 4917 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4918 if (udata->outlen && udata->outlen < min_resp_len) 4919 return ERR_PTR(-EINVAL); 4920 4921 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL); 4922 if (!rwq_ind_tbl) 4923 return ERR_PTR(-ENOMEM); 4924 4925 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 4926 in = mlx5_vzalloc(inlen); 4927 if (!in) { 4928 err = -ENOMEM; 4929 goto err; 4930 } 4931 4932 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 4933 4934 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 4935 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 4936 4937 for (i = 0; i < sz; i++) 4938 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 4939 4940 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid; 4941 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid); 4942 4943 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 4944 kvfree(in); 4945 4946 if (err) 4947 goto err; 4948 4949 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 4950 if (udata->outlen) { 4951 resp.response_length = offsetof(typeof(resp), response_length) + 4952 sizeof(resp.response_length); 4953 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4954 if (err) 4955 goto err_copy; 4956 } 4957 4958 return &rwq_ind_tbl->ib_rwq_ind_tbl; 4959 4960 err_copy: 4961 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 4962 err: 4963 kfree(rwq_ind_tbl); 4964 return ERR_PTR(err); 4965 } 4966 4967 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 4968 { 4969 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 4970 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 4971 4972 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 4973 4974 kfree(rwq_ind_tbl); 4975 return 0; 4976 } 4977 4978 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 4979 u32 wq_attr_mask, struct ib_udata *udata) 4980 { 4981 struct mlx5_ib_dev *dev = to_mdev(wq->device); 4982 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 4983 struct mlx5_ib_modify_wq ucmd = {}; 4984 size_t required_cmd_sz; 4985 int curr_wq_state; 4986 int wq_state; 4987 int inlen; 4988 int err; 4989 void *rqc; 4990 void *in; 4991 4992 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 4993 if (udata->inlen < required_cmd_sz) 4994 return -EINVAL; 4995 4996 if (udata->inlen > sizeof(ucmd) && 4997 !ib_is_udata_cleared(udata, sizeof(ucmd), 4998 udata->inlen - sizeof(ucmd))) 4999 return -EOPNOTSUPP; 5000 5001 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 5002 return -EFAULT; 5003 5004 if (ucmd.comp_mask || ucmd.reserved) 5005 return -EOPNOTSUPP; 5006 5007 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 5008 in = mlx5_vzalloc(inlen); 5009 if (!in) 5010 return -ENOMEM; 5011 5012 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 5013 5014 MLX5_SET(modify_rq_in, in, rqn, rwq->core_qp.qpn); 5015 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 5016 wq_attr->curr_wq_state : wq->state; 5017 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 5018 wq_attr->wq_state : curr_wq_state; 5019 if (curr_wq_state == IB_WQS_ERR) 5020 curr_wq_state = MLX5_RQC_STATE_ERR; 5021 if (wq_state == IB_WQS_ERR) 5022 wq_state = MLX5_RQC_STATE_ERR; 5023 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 5024 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid); 5025 MLX5_SET(rqc, rqc, state, wq_state); 5026 5027 err = mlx5_core_modify_rq(dev->mdev, in, inlen); 5028 kvfree(in); 5029 if (!err) 5030 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 5031 5032 return err; 5033 } 5034