1 /*- 2 * Copyright (c) 2013-2021, Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include <linux/module.h> 29 #include <rdma/ib_umem.h> 30 #include <rdma/ib_cache.h> 31 #include <rdma/ib_user_verbs.h> 32 #include "mlx5_ib.h" 33 34 /* not supported currently */ 35 static int wq_signature; 36 37 enum { 38 MLX5_IB_ACK_REQ_FREQ = 8, 39 }; 40 41 enum { 42 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 43 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 44 MLX5_IB_LINK_TYPE_IB = 0, 45 MLX5_IB_LINK_TYPE_ETH = 1 46 }; 47 48 enum { 49 MLX5_IB_SQ_STRIDE = 6, 50 }; 51 52 static const u32 mlx5_ib_opcode[] = { 53 [IB_WR_SEND] = MLX5_OPCODE_SEND, 54 [IB_WR_LSO] = MLX5_OPCODE_LSO, 55 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 56 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 57 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 58 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 59 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 60 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 61 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 62 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 63 [IB_WR_REG_MR] = MLX5_OPCODE_UMR, 64 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 65 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 66 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 67 }; 68 69 struct mlx5_wqe_eth_pad { 70 u8 rsvd0[16]; 71 }; 72 73 enum raw_qp_set_mask_map { 74 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 75 }; 76 77 struct mlx5_modify_raw_qp_param { 78 u16 operation; 79 80 u32 set_mask; /* raw_qp_set_mask_map */ 81 u8 rq_q_ctr_id; 82 }; 83 84 static void get_cqs(enum ib_qp_type qp_type, 85 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 86 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 87 88 static int is_qp0(enum ib_qp_type qp_type) 89 { 90 return qp_type == IB_QPT_SMI; 91 } 92 93 static int is_sqp(enum ib_qp_type qp_type) 94 { 95 return is_qp0(qp_type) || is_qp1(qp_type); 96 } 97 98 static void *get_wqe(struct mlx5_ib_qp *qp, int offset) 99 { 100 return mlx5_buf_offset(&qp->buf, offset); 101 } 102 103 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n) 104 { 105 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 106 } 107 108 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n) 109 { 110 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE)); 111 } 112 113 /** 114 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space. 115 * 116 * @qp: QP to copy from. 117 * @send: copy from the send queue when non-zero, use the receive queue 118 * otherwise. 119 * @wqe_index: index to start copying from. For send work queues, the 120 * wqe_index is in units of MLX5_SEND_WQE_BB. 121 * For receive work queue, it is the number of work queue 122 * element in the queue. 123 * @buffer: destination buffer. 124 * @length: maximum number of bytes to copy. 125 * 126 * Copies at least a single WQE, but may copy more data. 127 * 128 * Return: the number of bytes copied, or an error code. 129 */ 130 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 131 void *buffer, u32 length, 132 struct mlx5_ib_qp_base *base) 133 { 134 struct ib_device *ibdev = qp->ibqp.device; 135 struct mlx5_ib_dev *dev = to_mdev(ibdev); 136 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq; 137 size_t offset; 138 size_t wq_end; 139 struct ib_umem *umem = base->ubuffer.umem; 140 u32 first_copy_length; 141 int wqe_length; 142 int ret; 143 144 if (wq->wqe_cnt == 0) { 145 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n", 146 qp->ibqp.qp_type); 147 return -EINVAL; 148 } 149 150 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift); 151 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift); 152 153 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg)) 154 return -EINVAL; 155 156 if (offset > umem->length || 157 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length)) 158 return -EINVAL; 159 160 first_copy_length = min_t(u32, offset + length, wq_end) - offset; 161 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length); 162 if (ret) 163 return ret; 164 165 if (send) { 166 struct mlx5_wqe_ctrl_seg *ctrl = buffer; 167 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 168 169 wqe_length = ds * MLX5_WQE_DS_UNITS; 170 } else { 171 wqe_length = 1 << wq->wqe_shift; 172 } 173 174 if (wqe_length <= first_copy_length) 175 return first_copy_length; 176 177 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset, 178 wqe_length - first_copy_length); 179 if (ret) 180 return ret; 181 182 return wqe_length; 183 } 184 185 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 186 { 187 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 188 struct ib_event event; 189 190 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 191 /* This event is only valid for trans_qps */ 192 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 193 } 194 195 if (ibqp->event_handler) { 196 event.device = ibqp->device; 197 event.element.qp = ibqp; 198 switch (type) { 199 case MLX5_EVENT_TYPE_PATH_MIG: 200 event.event = IB_EVENT_PATH_MIG; 201 break; 202 case MLX5_EVENT_TYPE_COMM_EST: 203 event.event = IB_EVENT_COMM_EST; 204 break; 205 case MLX5_EVENT_TYPE_SQ_DRAINED: 206 event.event = IB_EVENT_SQ_DRAINED; 207 break; 208 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 209 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 210 break; 211 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 212 event.event = IB_EVENT_QP_FATAL; 213 break; 214 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 215 event.event = IB_EVENT_PATH_MIG_ERR; 216 break; 217 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 218 event.event = IB_EVENT_QP_REQ_ERR; 219 break; 220 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 221 event.event = IB_EVENT_QP_ACCESS_ERR; 222 break; 223 default: 224 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 225 return; 226 } 227 228 ibqp->event_handler(&event, ibqp->qp_context); 229 } 230 } 231 232 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 233 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 234 { 235 int wqe_size; 236 int wq_size; 237 238 /* Sanity check RQ size before proceeding */ 239 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 240 return -EINVAL; 241 242 if (!has_rq) { 243 qp->rq.max_gs = 0; 244 qp->rq.wqe_cnt = 0; 245 qp->rq.wqe_shift = 0; 246 cap->max_recv_wr = 0; 247 cap->max_recv_sge = 0; 248 } else { 249 if (ucmd) { 250 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 251 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 252 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 253 qp->rq.max_post = qp->rq.wqe_cnt; 254 } else { 255 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 256 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 257 wqe_size = roundup_pow_of_two(wqe_size); 258 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 259 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 260 qp->rq.wqe_cnt = wq_size / wqe_size; 261 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 262 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 263 wqe_size, 264 MLX5_CAP_GEN(dev->mdev, 265 max_wqe_sz_rq)); 266 return -EINVAL; 267 } 268 qp->rq.wqe_shift = ilog2(wqe_size); 269 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 270 qp->rq.max_post = qp->rq.wqe_cnt; 271 } 272 } 273 274 return 0; 275 } 276 277 static int sq_overhead(struct ib_qp_init_attr *attr) 278 { 279 int size = 0; 280 281 switch (attr->qp_type) { 282 case IB_QPT_XRC_INI: 283 size += sizeof(struct mlx5_wqe_xrc_seg); 284 /* fall through */ 285 case IB_QPT_RC: 286 size += sizeof(struct mlx5_wqe_ctrl_seg) + 287 max(sizeof(struct mlx5_wqe_atomic_seg) + 288 sizeof(struct mlx5_wqe_raddr_seg), 289 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 290 sizeof(struct mlx5_mkey_seg)); 291 break; 292 293 case IB_QPT_XRC_TGT: 294 return 0; 295 296 case IB_QPT_UC: 297 size += sizeof(struct mlx5_wqe_ctrl_seg) + 298 max(sizeof(struct mlx5_wqe_raddr_seg), 299 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 300 sizeof(struct mlx5_mkey_seg)); 301 break; 302 303 case IB_QPT_UD: 304 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 305 size += sizeof(struct mlx5_wqe_eth_pad) + 306 sizeof(struct mlx5_wqe_eth_seg); 307 /* fall through */ 308 case IB_QPT_SMI: 309 case MLX5_IB_QPT_HW_GSI: 310 size += sizeof(struct mlx5_wqe_ctrl_seg) + 311 sizeof(struct mlx5_wqe_datagram_seg); 312 break; 313 314 case MLX5_IB_QPT_REG_UMR: 315 size += sizeof(struct mlx5_wqe_ctrl_seg) + 316 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 317 sizeof(struct mlx5_mkey_seg); 318 break; 319 320 default: 321 return -EINVAL; 322 } 323 324 return size; 325 } 326 327 static int calc_send_wqe(struct ib_qp_init_attr *attr) 328 { 329 int inl_size = 0; 330 int size; 331 332 size = sq_overhead(attr); 333 if (size < 0) 334 return size; 335 336 if (attr->cap.max_inline_data) { 337 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 338 attr->cap.max_inline_data; 339 } 340 341 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 342 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && 343 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 344 return MLX5_SIG_WQE_SIZE; 345 else 346 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 347 } 348 349 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 350 { 351 int max_sge; 352 353 if (attr->qp_type == IB_QPT_RC) 354 max_sge = (min_t(int, wqe_size, 512) - 355 sizeof(struct mlx5_wqe_ctrl_seg) - 356 sizeof(struct mlx5_wqe_raddr_seg)) / 357 sizeof(struct mlx5_wqe_data_seg); 358 else if (attr->qp_type == IB_QPT_XRC_INI) 359 max_sge = (min_t(int, wqe_size, 512) - 360 sizeof(struct mlx5_wqe_ctrl_seg) - 361 sizeof(struct mlx5_wqe_xrc_seg) - 362 sizeof(struct mlx5_wqe_raddr_seg)) / 363 sizeof(struct mlx5_wqe_data_seg); 364 else 365 max_sge = (wqe_size - sq_overhead(attr)) / 366 sizeof(struct mlx5_wqe_data_seg); 367 368 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 369 sizeof(struct mlx5_wqe_data_seg)); 370 } 371 372 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 373 struct mlx5_ib_qp *qp) 374 { 375 int wqe_size; 376 int wq_size; 377 378 if (!attr->cap.max_send_wr) 379 return 0; 380 381 wqe_size = calc_send_wqe(attr); 382 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 383 if (wqe_size < 0) 384 return wqe_size; 385 386 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 387 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 388 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 389 return -EINVAL; 390 } 391 392 qp->max_inline_data = wqe_size - sq_overhead(attr) - 393 sizeof(struct mlx5_wqe_inline_seg); 394 attr->cap.max_inline_data = qp->max_inline_data; 395 396 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) 397 qp->signature_en = true; 398 399 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 400 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 401 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 402 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n", 403 qp->sq.wqe_cnt, 404 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 405 return -ENOMEM; 406 } 407 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 408 qp->sq.max_gs = get_send_sge(attr, wqe_size); 409 if (qp->sq.max_gs < attr->cap.max_send_sge) 410 return -ENOMEM; 411 412 attr->cap.max_send_sge = qp->sq.max_gs; 413 qp->sq.max_post = wq_size / wqe_size; 414 attr->cap.max_send_wr = qp->sq.max_post; 415 416 return wq_size; 417 } 418 419 static int set_user_buf_size(struct mlx5_ib_dev *dev, 420 struct mlx5_ib_qp *qp, 421 struct mlx5_ib_create_qp *ucmd, 422 struct mlx5_ib_qp_base *base, 423 struct ib_qp_init_attr *attr) 424 { 425 int desc_sz = 1 << qp->sq.wqe_shift; 426 427 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 428 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 429 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 430 return -EINVAL; 431 } 432 433 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) { 434 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n", 435 ucmd->sq_wqe_count, ucmd->sq_wqe_count); 436 return -EINVAL; 437 } 438 439 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 440 441 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 442 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 443 qp->sq.wqe_cnt, 444 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 445 return -EINVAL; 446 } 447 448 if (attr->qp_type == IB_QPT_RAW_PACKET) { 449 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 450 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 451 } else { 452 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 453 (qp->sq.wqe_cnt << 6); 454 } 455 456 return 0; 457 } 458 459 static int qp_has_rq(struct ib_qp_init_attr *attr) 460 { 461 if (attr->qp_type == IB_QPT_XRC_INI || 462 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 463 attr->qp_type == MLX5_IB_QPT_REG_UMR || 464 !attr->cap.max_recv_wr) 465 return 0; 466 467 return 1; 468 } 469 470 enum { 471 /* this is the first blue flame register in the array of bfregs assigned 472 * to a processes. Since we do not use it for blue flame but rather 473 * regular 64 bit doorbells, we do not need a lock for maintaiing 474 * "odd/even" order 475 */ 476 NUM_NON_BLUE_FLAME_BFREGS = 1, 477 }; 478 479 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 480 { 481 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; 482 } 483 484 static int num_med_bfreg(struct mlx5_ib_dev *dev, 485 struct mlx5_bfreg_info *bfregi) 486 { 487 int n; 488 489 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 490 NUM_NON_BLUE_FLAME_BFREGS; 491 492 return n >= 0 ? n : 0; 493 } 494 495 static int first_med_bfreg(struct mlx5_ib_dev *dev, 496 struct mlx5_bfreg_info *bfregi) 497 { 498 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; 499 } 500 501 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 502 struct mlx5_bfreg_info *bfregi) 503 { 504 int med; 505 506 med = num_med_bfreg(dev, bfregi); 507 return ++med; 508 } 509 510 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 511 struct mlx5_bfreg_info *bfregi) 512 { 513 int i; 514 515 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 516 if (!bfregi->count[i]) { 517 bfregi->count[i]++; 518 return i; 519 } 520 } 521 522 return -ENOMEM; 523 } 524 525 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 526 struct mlx5_bfreg_info *bfregi) 527 { 528 int minidx = first_med_bfreg(dev, bfregi); 529 int i; 530 531 if (minidx < 0) 532 return minidx; 533 534 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { 535 if (bfregi->count[i] < bfregi->count[minidx]) 536 minidx = i; 537 if (!bfregi->count[minidx]) 538 break; 539 } 540 541 bfregi->count[minidx]++; 542 return minidx; 543 } 544 545 static int alloc_bfreg(struct mlx5_ib_dev *dev, 546 struct mlx5_bfreg_info *bfregi) 547 { 548 int bfregn = -ENOMEM; 549 550 if (bfregi->lib_uar_dyn) 551 return -EINVAL; 552 553 mutex_lock(&bfregi->lock); 554 if (bfregi->ver >= 2) { 555 bfregn = alloc_high_class_bfreg(dev, bfregi); 556 if (bfregn < 0) 557 bfregn = alloc_med_class_bfreg(dev, bfregi); 558 } 559 560 if (bfregn < 0) { 561 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 562 bfregn = 0; 563 bfregi->count[bfregn]++; 564 } 565 mutex_unlock(&bfregi->lock); 566 567 return bfregn; 568 } 569 570 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 571 { 572 mutex_lock(&bfregi->lock); 573 bfregi->count[bfregn]--; 574 mutex_unlock(&bfregi->lock); 575 } 576 577 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 578 { 579 switch (state) { 580 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 581 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 582 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 583 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 584 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 585 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 586 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 587 default: return -1; 588 } 589 } 590 591 static int to_mlx5_st(enum ib_qp_type type) 592 { 593 switch (type) { 594 case IB_QPT_RC: return MLX5_QP_ST_RC; 595 case IB_QPT_UC: return MLX5_QP_ST_UC; 596 case IB_QPT_UD: return MLX5_QP_ST_UD; 597 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 598 case IB_QPT_XRC_INI: 599 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 600 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 601 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 602 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 603 case IB_QPT_RAW_PACKET: 604 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 605 case IB_QPT_MAX: 606 default: return -EINVAL; 607 } 608 } 609 610 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 611 struct mlx5_ib_cq *recv_cq); 612 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 613 struct mlx5_ib_cq *recv_cq); 614 615 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 616 struct mlx5_bfreg_info *bfregi, u32 bfregn, 617 bool dyn_bfreg) 618 { 619 unsigned int bfregs_per_sys_page; 620 u32 index_of_sys_page; 621 u32 offset; 622 623 if (bfregi->lib_uar_dyn) 624 return -EINVAL; 625 626 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 627 MLX5_NON_FP_BFREGS_PER_UAR; 628 index_of_sys_page = bfregn / bfregs_per_sys_page; 629 630 if (dyn_bfreg) { 631 index_of_sys_page += bfregi->num_static_sys_pages; 632 633 if (index_of_sys_page >= bfregi->num_sys_pages) 634 return -EINVAL; 635 636 if (bfregn > bfregi->num_dyn_bfregs || 637 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 638 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 639 return -EINVAL; 640 } 641 } 642 643 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 644 return bfregi->sys_pages[index_of_sys_page] + offset; 645 } 646 647 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, 648 struct ib_pd *pd, 649 unsigned long addr, size_t size, 650 struct ib_umem **umem, 651 int *npages, int *page_shift, int *ncont, 652 u32 *offset) 653 { 654 int err; 655 656 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0); 657 if (IS_ERR(*umem)) { 658 mlx5_ib_dbg(dev, "umem_get failed\n"); 659 return PTR_ERR(*umem); 660 } 661 662 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL); 663 664 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 665 if (err) { 666 mlx5_ib_warn(dev, "bad offset\n"); 667 goto err_umem; 668 } 669 670 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", 671 addr, size, *npages, *page_shift, *ncont, *offset); 672 673 return 0; 674 675 err_umem: 676 ib_umem_release(*umem); 677 *umem = NULL; 678 679 return err; 680 } 681 682 static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq) 683 { 684 struct mlx5_ib_ucontext *context; 685 686 context = to_mucontext(pd->uobject->context); 687 mlx5_ib_db_unmap_user(context, &rwq->db); 688 if (rwq->umem) 689 ib_umem_release(rwq->umem); 690 } 691 692 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 693 struct mlx5_ib_rwq *rwq, 694 struct mlx5_ib_create_wq *ucmd) 695 { 696 struct mlx5_ib_ucontext *context; 697 int page_shift = 0; 698 int npages; 699 u32 offset = 0; 700 int ncont = 0; 701 int err; 702 703 if (!ucmd->buf_addr) 704 return -EINVAL; 705 706 context = to_mucontext(pd->uobject->context); 707 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr, 708 rwq->buf_size, 0, 0); 709 if (IS_ERR(rwq->umem)) { 710 mlx5_ib_dbg(dev, "umem_get failed\n"); 711 err = PTR_ERR(rwq->umem); 712 return err; 713 } 714 715 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift, 716 &ncont, NULL); 717 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, 718 &rwq->rq_page_offset); 719 if (err) { 720 mlx5_ib_warn(dev, "bad offset\n"); 721 goto err_umem; 722 } 723 724 rwq->rq_num_pas = ncont; 725 rwq->page_shift = page_shift; 726 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; 727 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 728 729 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", 730 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 731 npages, page_shift, ncont, offset); 732 733 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db); 734 if (err) { 735 mlx5_ib_dbg(dev, "map failed\n"); 736 goto err_umem; 737 } 738 739 rwq->create_type = MLX5_WQ_USER; 740 return 0; 741 742 err_umem: 743 ib_umem_release(rwq->umem); 744 return err; 745 } 746 747 static int adjust_bfregn(struct mlx5_ib_dev *dev, 748 struct mlx5_bfreg_info *bfregi, int bfregn) 749 { 750 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 751 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 752 } 753 754 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 755 struct mlx5_ib_qp *qp, struct ib_udata *udata, 756 struct ib_qp_init_attr *attr, 757 u32 **in, 758 struct mlx5_ib_create_qp_resp *resp, int *inlen, 759 struct mlx5_ib_qp_base *base) 760 { 761 struct mlx5_ib_ucontext *context; 762 struct mlx5_ib_create_qp ucmd; 763 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 764 int page_shift = 0; 765 int uar_index = 0; 766 int npages; 767 u32 offset = 0; 768 int bfregn; 769 int ncont = 0; 770 __be64 *pas; 771 void *qpc; 772 int err; 773 u32 uar_flags; 774 775 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 776 if (err) { 777 mlx5_ib_dbg(dev, "copy failed\n"); 778 return err; 779 } 780 781 context = to_mucontext(pd->uobject->context); 782 uar_flags = ucmd.flags & (MLX5_QP_FLAG_UAR_PAGE_INDEX | 783 MLX5_QP_FLAG_BFREG_INDEX); 784 switch (uar_flags) { 785 case MLX5_QP_FLAG_UAR_PAGE_INDEX: 786 uar_index = ucmd.bfreg_index; 787 bfregn = MLX5_IB_INVALID_BFREG; 788 break; 789 case MLX5_QP_FLAG_BFREG_INDEX: 790 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 791 ucmd.bfreg_index, true); 792 if (uar_index < 0) 793 return uar_index; 794 bfregn = MLX5_IB_INVALID_BFREG; 795 break; 796 case 0: 797 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 798 return -EINVAL; 799 bfregn = alloc_bfreg(dev, &context->bfregi); 800 if (bfregn < 0) 801 return bfregn; 802 break; 803 default: 804 return -EINVAL; 805 } 806 807 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 808 if (bfregn != MLX5_IB_INVALID_BFREG) 809 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 810 false); 811 812 qp->rq.offset = 0; 813 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 814 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 815 816 err = set_user_buf_size(dev, qp, &ucmd, base, attr); 817 if (err) 818 goto err_bfreg; 819 820 if (ucmd.buf_addr && ubuffer->buf_size) { 821 ubuffer->buf_addr = ucmd.buf_addr; 822 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, 823 ubuffer->buf_size, 824 &ubuffer->umem, &npages, &page_shift, 825 &ncont, &offset); 826 if (err) 827 goto err_bfreg; 828 } else { 829 ubuffer->umem = NULL; 830 } 831 832 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 833 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 834 *in = mlx5_vzalloc(*inlen); 835 if (!*in) { 836 err = -ENOMEM; 837 goto err_umem; 838 } 839 840 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 841 if (ubuffer->umem) 842 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0); 843 844 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 845 846 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 847 MLX5_SET(qpc, qpc, page_offset, offset); 848 849 MLX5_SET(qpc, qpc, uar_page, uar_index); 850 if (bfregn != MLX5_IB_INVALID_BFREG) 851 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 852 else 853 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 854 qp->bfregn = bfregn; 855 856 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db); 857 if (err) { 858 mlx5_ib_dbg(dev, "map failed\n"); 859 goto err_free; 860 } 861 862 err = ib_copy_to_udata(udata, resp, sizeof(*resp)); 863 if (err) { 864 mlx5_ib_dbg(dev, "copy failed\n"); 865 goto err_unmap; 866 } 867 qp->create_type = MLX5_QP_USER; 868 869 return 0; 870 871 err_unmap: 872 mlx5_ib_db_unmap_user(context, &qp->db); 873 874 err_free: 875 kvfree(*in); 876 877 err_umem: 878 if (ubuffer->umem) 879 ib_umem_release(ubuffer->umem); 880 881 err_bfreg: 882 if (bfregn != MLX5_IB_INVALID_BFREG) 883 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 884 return err; 885 } 886 887 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd, struct mlx5_ib_qp *qp, 888 struct mlx5_ib_qp_base *base) 889 { 890 struct mlx5_ib_ucontext *context; 891 892 context = to_mucontext(pd->uobject->context); 893 mlx5_ib_db_unmap_user(context, &qp->db); 894 if (base->ubuffer.umem) 895 ib_umem_release(base->ubuffer.umem); 896 897 /* 898 * Free only the BFREGs which are handled by the kernel. 899 * BFREGs of UARs allocated dynamically are handled by user. 900 */ 901 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 902 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 903 } 904 905 static int create_kernel_qp(struct mlx5_ib_dev *dev, 906 struct ib_qp_init_attr *init_attr, 907 struct mlx5_ib_qp *qp, 908 u32 **in, int *inlen, 909 struct mlx5_ib_qp_base *base) 910 { 911 int uar_index; 912 void *qpc; 913 int err; 914 915 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | 916 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK | 917 IB_QP_CREATE_IPOIB_UD_LSO | 918 MLX5_IB_QP_CREATE_SQPN_QP1 | 919 MLX5_IB_QP_CREATE_WC_TEST)) 920 return -EINVAL; 921 922 spin_lock_init(&qp->bf.lock32); 923 924 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 925 qp->bf.bfreg = &dev->fp_bfreg; 926 else if (init_attr->create_flags & MLX5_IB_QP_CREATE_WC_TEST) 927 qp->bf.bfreg = &dev->wc_bfreg; 928 else 929 qp->bf.bfreg = &dev->bfreg; 930 931 /* We need to divide by two since each register is comprised of 932 * two buffers of identical size, namely odd and even 933 */ 934 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 935 uar_index = qp->bf.bfreg->index; 936 937 err = calc_sq_size(dev, init_attr, qp); 938 if (err < 0) { 939 mlx5_ib_dbg(dev, "err %d\n", err); 940 return err; 941 } 942 943 qp->rq.offset = 0; 944 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 945 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 946 947 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, 948 2 * PAGE_SIZE, &qp->buf); 949 if (err) { 950 mlx5_ib_dbg(dev, "err %d\n", err); 951 return err; 952 } 953 954 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt); 955 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 956 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 957 *in = mlx5_vzalloc(*inlen); 958 if (!*in) { 959 err = -ENOMEM; 960 goto err_buf; 961 } 962 963 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 964 MLX5_SET(qpc, qpc, uar_page, uar_index); 965 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev)); 966 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 967 968 /* Set "fast registration enabled" for all kernel QPs */ 969 MLX5_SET(qpc, qpc, fre, 1); 970 MLX5_SET(qpc, qpc, rlky, 1); 971 972 if (init_attr->create_flags & MLX5_IB_QP_CREATE_SQPN_QP1) { 973 MLX5_SET(qpc, qpc, deth_sqpn, 1); 974 qp->flags |= MLX5_IB_QP_SQPN_QP1; 975 } 976 977 mlx5_fill_page_array(&qp->buf, 978 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas)); 979 980 err = mlx5_db_alloc(dev->mdev, &qp->db); 981 if (err) { 982 mlx5_ib_dbg(dev, "err %d\n", err); 983 goto err_free; 984 } 985 986 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL); 987 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL); 988 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL); 989 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL); 990 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL); 991 992 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 993 !qp->sq.w_list || !qp->sq.wqe_head) { 994 err = -ENOMEM; 995 goto err_wrid; 996 } 997 qp->create_type = MLX5_QP_KERNEL; 998 999 return 0; 1000 1001 err_wrid: 1002 kfree(qp->sq.wqe_head); 1003 kfree(qp->sq.w_list); 1004 kfree(qp->sq.wrid); 1005 kfree(qp->sq.wr_data); 1006 kfree(qp->rq.wrid); 1007 mlx5_db_free(dev->mdev, &qp->db); 1008 1009 err_free: 1010 kvfree(*in); 1011 1012 err_buf: 1013 mlx5_buf_free(dev->mdev, &qp->buf); 1014 return err; 1015 } 1016 1017 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1018 { 1019 kfree(qp->sq.wqe_head); 1020 kfree(qp->sq.w_list); 1021 kfree(qp->sq.wrid); 1022 kfree(qp->sq.wr_data); 1023 kfree(qp->rq.wrid); 1024 mlx5_db_free(dev->mdev, &qp->db); 1025 mlx5_buf_free(dev->mdev, &qp->buf); 1026 } 1027 1028 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1029 { 1030 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 1031 (attr->qp_type == IB_QPT_XRC_INI)) 1032 return MLX5_SRQ_RQ; 1033 else if (!qp->has_rq) 1034 return MLX5_ZERO_LEN_RQ; 1035 else 1036 return MLX5_NON_ZERO_RQ; 1037 } 1038 1039 static int is_connected(enum ib_qp_type qp_type) 1040 { 1041 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC) 1042 return 1; 1043 1044 return 0; 1045 } 1046 1047 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1048 struct mlx5_ib_sq *sq, u32 tdn) 1049 { 1050 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1051 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1052 1053 MLX5_SET(tisc, tisc, transport_domain, tdn); 1054 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn); 1055 } 1056 1057 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1058 struct mlx5_ib_sq *sq) 1059 { 1060 mlx5_core_destroy_tis(dev->mdev, sq->tisn); 1061 } 1062 1063 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1064 struct mlx5_ib_sq *sq, void *qpin, 1065 struct ib_pd *pd) 1066 { 1067 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1068 __be64 *pas; 1069 void *in; 1070 void *sqc; 1071 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1072 void *wq; 1073 int inlen; 1074 int err; 1075 int page_shift = 0; 1076 int npages; 1077 int ncont = 0; 1078 u32 offset = 0; 1079 u8 ts_format; 1080 1081 ts_format = mlx5_get_sq_default_ts(dev->mdev); 1082 1083 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size, 1084 &sq->ubuffer.umem, &npages, &page_shift, 1085 &ncont, &offset); 1086 if (err) 1087 return err; 1088 1089 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; 1090 in = mlx5_vzalloc(inlen); 1091 if (!in) { 1092 err = -ENOMEM; 1093 goto err_umem; 1094 } 1095 1096 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1097 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1098 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1099 MLX5_SET(sqc, sqc, ts_format, ts_format); 1100 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1101 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1102 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1103 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1104 1105 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1106 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1107 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1108 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1109 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1110 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1111 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1112 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1113 MLX5_SET(wq, wq, page_offset, offset); 1114 1115 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1116 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); 1117 1118 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); 1119 1120 kvfree(in); 1121 1122 if (err) 1123 goto err_umem; 1124 1125 return 0; 1126 1127 err_umem: 1128 ib_umem_release(sq->ubuffer.umem); 1129 sq->ubuffer.umem = NULL; 1130 1131 return err; 1132 } 1133 1134 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1135 struct mlx5_ib_sq *sq) 1136 { 1137 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1138 ib_umem_release(sq->ubuffer.umem); 1139 } 1140 1141 static int get_rq_pas_size(void *qpc) 1142 { 1143 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; 1144 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); 1145 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); 1146 u32 page_offset = MLX5_GET(qpc, qpc, page_offset); 1147 u32 po_quanta = 1 << (log_page_size - 6); 1148 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); 1149 u32 page_size = 1 << log_page_size; 1150 u32 rq_sz_po = rq_sz + (page_offset * po_quanta); 1151 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; 1152 1153 return rq_num_pas * sizeof(u64); 1154 } 1155 1156 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1157 struct mlx5_ib_rq *rq, void *qpin) 1158 { 1159 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1160 __be64 *pas; 1161 __be64 *qp_pas; 1162 void *in; 1163 void *rqc; 1164 void *wq; 1165 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1166 int inlen; 1167 int err; 1168 u32 rq_pas_size = get_rq_pas_size(qpc); 1169 u8 ts_format; 1170 1171 ts_format = mlx5_get_rq_default_ts(dev->mdev); 1172 1173 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; 1174 in = mlx5_vzalloc(inlen); 1175 if (!in) 1176 return -ENOMEM; 1177 1178 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1179 MLX5_SET(rqc, rqc, vlan_strip_disable, 1); 1180 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE); 1181 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1182 MLX5_SET(rqc, rqc, ts_format, ts_format); 1183 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1184 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1185 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1186 1187 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS) 1188 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1189 1190 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1191 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1192 MLX5_SET(wq, wq, end_padding_mode, 1193 MLX5_GET(qpc, qpc, end_padding_mode)); 1194 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1195 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1196 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1197 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1198 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); 1199 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1200 1201 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1202 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); 1203 memcpy(pas, qp_pas, rq_pas_size); 1204 1205 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); 1206 1207 kvfree(in); 1208 1209 return err; 1210 } 1211 1212 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1213 struct mlx5_ib_rq *rq) 1214 { 1215 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); 1216 } 1217 1218 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1219 struct mlx5_ib_rq *rq, u32 tdn) 1220 { 1221 u32 *in; 1222 void *tirc; 1223 int inlen; 1224 int err; 1225 1226 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1227 in = mlx5_vzalloc(inlen); 1228 if (!in) 1229 return -ENOMEM; 1230 1231 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context); 1232 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1233 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1234 MLX5_SET(tirc, tirc, transport_domain, tdn); 1235 1236 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn); 1237 1238 kvfree(in); 1239 1240 return err; 1241 } 1242 1243 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1244 struct mlx5_ib_rq *rq) 1245 { 1246 mlx5_core_destroy_tir(dev->mdev, rq->tirn); 1247 } 1248 1249 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1250 u32 *in, 1251 struct ib_pd *pd) 1252 { 1253 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1254 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1255 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1256 struct ib_uobject *uobj = pd->uobject; 1257 struct ib_ucontext *ucontext = uobj->context; 1258 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1259 int err; 1260 u32 tdn = mucontext->tdn; 1261 1262 if (qp->sq.wqe_cnt) { 1263 err = create_raw_packet_qp_tis(dev, sq, tdn); 1264 if (err) 1265 return err; 1266 1267 err = create_raw_packet_qp_sq(dev, sq, in, pd); 1268 if (err) 1269 goto err_destroy_tis; 1270 1271 sq->base.container_mibqp = qp; 1272 } 1273 1274 if (qp->rq.wqe_cnt) { 1275 rq->base.container_mibqp = qp; 1276 1277 err = create_raw_packet_qp_rq(dev, rq, in); 1278 if (err) 1279 goto err_destroy_sq; 1280 1281 1282 err = create_raw_packet_qp_tir(dev, rq, tdn); 1283 if (err) 1284 goto err_destroy_rq; 1285 } 1286 1287 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1288 rq->base.mqp.qpn; 1289 1290 return 0; 1291 1292 err_destroy_rq: 1293 destroy_raw_packet_qp_rq(dev, rq); 1294 err_destroy_sq: 1295 if (!qp->sq.wqe_cnt) 1296 return err; 1297 destroy_raw_packet_qp_sq(dev, sq); 1298 err_destroy_tis: 1299 destroy_raw_packet_qp_tis(dev, sq); 1300 1301 return err; 1302 } 1303 1304 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1305 struct mlx5_ib_qp *qp) 1306 { 1307 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1308 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1309 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1310 1311 if (qp->rq.wqe_cnt) { 1312 destroy_raw_packet_qp_tir(dev, rq); 1313 destroy_raw_packet_qp_rq(dev, rq); 1314 } 1315 1316 if (qp->sq.wqe_cnt) { 1317 destroy_raw_packet_qp_sq(dev, sq); 1318 destroy_raw_packet_qp_tis(dev, sq); 1319 } 1320 } 1321 1322 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1323 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1324 { 1325 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1326 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1327 1328 sq->sq = &qp->sq; 1329 rq->rq = &qp->rq; 1330 sq->doorbell = &qp->db; 1331 rq->doorbell = &qp->db; 1332 } 1333 1334 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1335 { 1336 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn); 1337 } 1338 1339 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1340 struct ib_pd *pd, 1341 struct ib_qp_init_attr *init_attr, 1342 struct ib_udata *udata) 1343 { 1344 struct ib_uobject *uobj = pd->uobject; 1345 struct ib_ucontext *ucontext = uobj->context; 1346 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1347 struct mlx5_ib_create_qp_resp resp = {}; 1348 int inlen; 1349 int err; 1350 u32 *in; 1351 void *tirc; 1352 void *hfso; 1353 u32 selected_fields = 0; 1354 size_t min_resp_len; 1355 u32 tdn = mucontext->tdn; 1356 struct mlx5_ib_create_qp_rss ucmd = {}; 1357 size_t required_cmd_sz; 1358 1359 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1360 return -EOPNOTSUPP; 1361 1362 if (init_attr->create_flags || init_attr->send_cq) 1363 return -EINVAL; 1364 1365 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index); 1366 if (udata->outlen < min_resp_len) 1367 return -EINVAL; 1368 1369 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1); 1370 if (udata->inlen < required_cmd_sz) { 1371 mlx5_ib_dbg(dev, "invalid inlen\n"); 1372 return -EINVAL; 1373 } 1374 1375 if (udata->inlen > sizeof(ucmd) && 1376 !ib_is_udata_cleared(udata, sizeof(ucmd), 1377 udata->inlen - sizeof(ucmd))) { 1378 mlx5_ib_dbg(dev, "inlen is not supported\n"); 1379 return -EOPNOTSUPP; 1380 } 1381 1382 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 1383 mlx5_ib_dbg(dev, "copy failed\n"); 1384 return -EFAULT; 1385 } 1386 1387 if (ucmd.comp_mask) { 1388 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1389 return -EOPNOTSUPP; 1390 } 1391 1392 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) { 1393 mlx5_ib_dbg(dev, "invalid reserved\n"); 1394 return -EOPNOTSUPP; 1395 } 1396 1397 err = ib_copy_to_udata(udata, &resp, min_resp_len); 1398 if (err) { 1399 mlx5_ib_dbg(dev, "copy failed\n"); 1400 return -EINVAL; 1401 } 1402 1403 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1404 in = mlx5_vzalloc(inlen); 1405 if (!in) 1406 return -ENOMEM; 1407 1408 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context); 1409 MLX5_SET(tirc, tirc, disp_type, 1410 MLX5_TIRC_DISP_TYPE_INDIRECT); 1411 MLX5_SET(tirc, tirc, indirect_table, 1412 init_attr->rwq_ind_tbl->ind_tbl_num); 1413 MLX5_SET(tirc, tirc, transport_domain, tdn); 1414 1415 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1416 switch (ucmd.rx_hash_function) { 1417 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1418 { 1419 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1420 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1421 1422 if (len != ucmd.rx_key_len) { 1423 err = -EINVAL; 1424 goto err; 1425 } 1426 1427 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FUNC_TOEPLITZ); 1428 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 1429 memcpy(rss_key, ucmd.rx_hash_key, len); 1430 break; 1431 } 1432 default: 1433 err = -EOPNOTSUPP; 1434 goto err; 1435 } 1436 1437 if (!ucmd.rx_hash_fields_mask) { 1438 /* special case when this TIR serves as steering entry without hashing */ 1439 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1440 goto create_tir; 1441 err = -EINVAL; 1442 goto err; 1443 } 1444 1445 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1446 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1447 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1448 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1449 err = -EINVAL; 1450 goto err; 1451 } 1452 1453 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1454 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1455 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1456 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1457 MLX5_L3_PROT_TYPE_IPV4); 1458 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1459 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1460 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1461 MLX5_L3_PROT_TYPE_IPV6); 1462 1463 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1464 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) && 1465 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1466 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) { 1467 err = -EINVAL; 1468 goto err; 1469 } 1470 1471 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1472 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1473 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1474 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1475 MLX5_L4_PROT_TYPE_TCP); 1476 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1477 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1478 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1479 MLX5_L4_PROT_TYPE_UDP); 1480 1481 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1482 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1483 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1484 1485 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1486 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1487 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1488 1489 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1490 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1491 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1492 1493 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1494 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1495 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1496 1497 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1498 1499 create_tir: 1500 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn); 1501 1502 if (err) 1503 goto err; 1504 1505 kvfree(in); 1506 /* qpn is reserved for that QP */ 1507 qp->trans_qp.base.mqp.qpn = 0; 1508 qp->flags |= MLX5_IB_QP_RSS; 1509 return 0; 1510 1511 err: 1512 kvfree(in); 1513 return err; 1514 } 1515 1516 static int atomic_size_to_mode(int size_mask) 1517 { 1518 /* driver does not support atomic_size > 256B 1519 * and does not know how to translate bigger sizes 1520 */ 1521 int supported_size_mask = size_mask & 0x1ff; 1522 int log_max_size; 1523 1524 if (!supported_size_mask) 1525 return -EOPNOTSUPP; 1526 1527 log_max_size = __fls(supported_size_mask); 1528 1529 if (log_max_size > 3) 1530 return log_max_size; 1531 1532 return MLX5_ATOMIC_MODE_8B; 1533 } 1534 1535 static int get_atomic_mode(struct mlx5_ib_dev *dev, 1536 enum ib_qp_type qp_type) 1537 { 1538 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 1539 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic); 1540 int atomic_mode = -EOPNOTSUPP; 1541 int atomic_size_mask; 1542 1543 if (!atomic) 1544 return -EOPNOTSUPP; 1545 1546 if (qp_type == MLX5_IB_QPT_DCT) 1547 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 1548 else 1549 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 1550 1551 if ((atomic_operations & MLX5_ATOMIC_OPS_MASKED_CMP_SWAP) || 1552 (atomic_operations & MLX5_ATOMIC_OPS_MASKED_FETCH_ADD)) 1553 atomic_mode = atomic_size_to_mode(atomic_size_mask); 1554 1555 if (atomic_mode <= 0 && 1556 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP && 1557 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD)) 1558 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP; 1559 1560 return atomic_mode; 1561 } 1562 1563 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1564 struct ib_qp_init_attr *init_attr, 1565 struct ib_udata *udata, struct mlx5_ib_qp *qp) 1566 { 1567 struct mlx5_ib_resources *devr = &dev->devr; 1568 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1569 struct mlx5_core_dev *mdev = dev->mdev; 1570 struct mlx5_ib_create_qp_resp resp; 1571 struct mlx5_ib_cq *send_cq; 1572 struct mlx5_ib_cq *recv_cq; 1573 unsigned long flags; 1574 u32 uidx = MLX5_IB_DEFAULT_UIDX; 1575 struct mlx5_ib_create_qp ucmd; 1576 struct mlx5_ib_qp_base *base; 1577 void *qpc; 1578 u32 *in; 1579 int err; 1580 1581 base = init_attr->qp_type == IB_QPT_RAW_PACKET ? 1582 &qp->raw_packet_qp.rq.base : 1583 &qp->trans_qp.base; 1584 1585 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1586 mlx5_ib_odp_create_qp(qp); 1587 1588 mutex_init(&qp->mutex); 1589 spin_lock_init(&qp->sq.lock); 1590 spin_lock_init(&qp->rq.lock); 1591 1592 if (init_attr->rwq_ind_tbl) { 1593 if (!udata) 1594 return -ENOSYS; 1595 1596 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata); 1597 return err; 1598 } 1599 1600 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 1601 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { 1602 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); 1603 return -EINVAL; 1604 } else { 1605 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1606 } 1607 } 1608 1609 if (init_attr->create_flags & 1610 (IB_QP_CREATE_CROSS_CHANNEL | 1611 IB_QP_CREATE_MANAGED_SEND | 1612 IB_QP_CREATE_MANAGED_RECV)) { 1613 if (!MLX5_CAP_GEN(mdev, cd)) { 1614 mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); 1615 return -EINVAL; 1616 } 1617 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) 1618 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; 1619 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) 1620 qp->flags |= MLX5_IB_QP_MANAGED_SEND; 1621 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) 1622 qp->flags |= MLX5_IB_QP_MANAGED_RECV; 1623 } 1624 1625 if (init_attr->qp_type == IB_QPT_UD && 1626 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) 1627 if (!MLX5_CAP_GEN(mdev, ipoib_ipoib_offloads)) { 1628 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n"); 1629 return -EOPNOTSUPP; 1630 } 1631 1632 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 1633 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1634 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs"); 1635 return -EOPNOTSUPP; 1636 } 1637 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) || 1638 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 1639 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n"); 1640 return -EOPNOTSUPP; 1641 } 1642 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS; 1643 } 1644 1645 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1646 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1647 1648 if (pd && pd->uobject) { 1649 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 1650 mlx5_ib_dbg(dev, "copy failed\n"); 1651 return -EFAULT; 1652 } 1653 1654 err = get_qp_user_index(to_mucontext(pd->uobject->context), 1655 &ucmd, udata->inlen, &uidx); 1656 if (err) 1657 return err; 1658 1659 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 1660 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 1661 } else { 1662 qp->wq_sig = !!wq_signature; 1663 } 1664 1665 qp->has_rq = qp_has_rq(init_attr); 1666 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 1667 qp, (pd && pd->uobject) ? &ucmd : NULL); 1668 if (err) { 1669 mlx5_ib_dbg(dev, "err %d\n", err); 1670 return err; 1671 } 1672 1673 if (pd) { 1674 if (pd->uobject) { 1675 __u32 max_wqes = 1676 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1677 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 1678 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 1679 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 1680 mlx5_ib_dbg(dev, "invalid rq params\n"); 1681 return -EINVAL; 1682 } 1683 if (ucmd.sq_wqe_count > max_wqes) { 1684 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 1685 ucmd.sq_wqe_count, max_wqes); 1686 return -EINVAL; 1687 } 1688 if (init_attr->create_flags & 1689 MLX5_IB_QP_CREATE_SQPN_QP1) { 1690 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n"); 1691 return -EINVAL; 1692 } 1693 err = create_user_qp(dev, pd, qp, udata, init_attr, &in, 1694 &resp, &inlen, base); 1695 if (err) 1696 mlx5_ib_dbg(dev, "err %d\n", err); 1697 } else { 1698 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, 1699 base); 1700 if (err) 1701 mlx5_ib_dbg(dev, "err %d\n", err); 1702 } 1703 1704 if (err) 1705 return err; 1706 } else { 1707 in = mlx5_vzalloc(inlen); 1708 if (!in) 1709 return -ENOMEM; 1710 1711 qp->create_type = MLX5_QP_EMPTY; 1712 } 1713 1714 if (is_sqp(init_attr->qp_type)) 1715 qp->port = init_attr->port_num; 1716 1717 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1718 1719 MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type)); 1720 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1721 1722 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 1723 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 1724 else 1725 MLX5_SET(qpc, qpc, latency_sensitive, 1); 1726 1727 1728 if (qp->wq_sig) 1729 MLX5_SET(qpc, qpc, wq_signature, 1); 1730 1731 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 1732 MLX5_SET(qpc, qpc, block_lb_mc, 1); 1733 1734 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 1735 MLX5_SET(qpc, qpc, cd_master, 1); 1736 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 1737 MLX5_SET(qpc, qpc, cd_slave_send, 1); 1738 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 1739 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 1740 1741 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 1742 int rcqe_sz; 1743 int scqe_sz; 1744 1745 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq); 1746 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq); 1747 1748 if (rcqe_sz == 128) 1749 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 1750 else 1751 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE); 1752 1753 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) { 1754 if (scqe_sz == 128) 1755 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1756 else 1757 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1758 } 1759 } 1760 1761 if (qp->rq.wqe_cnt) { 1762 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 1763 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 1764 } 1765 1766 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1767 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev)); 1768 1769 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 1770 1771 if (qp->sq.wqe_cnt) 1772 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 1773 else 1774 MLX5_SET(qpc, qpc, no_sq, 1); 1775 1776 /* Set default resources */ 1777 switch (init_attr->qp_type) { 1778 case IB_QPT_XRC_TGT: 1779 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1780 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 1781 MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s0)->msrq.srqn); 1782 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn); 1783 break; 1784 case IB_QPT_XRC_INI: 1785 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1786 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1787 MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s0)->msrq.srqn); 1788 break; 1789 default: 1790 if (init_attr->srq) { 1791 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn); 1792 MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(init_attr->srq)->msrq.srqn); 1793 } else { 1794 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1795 MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s1)->msrq.srqn); 1796 } 1797 } 1798 1799 if (init_attr->send_cq) 1800 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 1801 1802 if (init_attr->recv_cq) 1803 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 1804 1805 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 1806 1807 /* 0xffffff means we ask to work with cqe version 0 */ 1808 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 1809 MLX5_SET(qpc, qpc, user_index, uidx); 1810 1811 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 1812 if (init_attr->qp_type == IB_QPT_UD && 1813 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) { 1814 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 1815 qp->flags |= MLX5_IB_QP_LSO; 1816 } 1817 1818 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 1819 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; 1820 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 1821 err = create_raw_packet_qp(dev, qp, in, pd); 1822 } else { 1823 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); 1824 } 1825 1826 if (err) { 1827 mlx5_ib_dbg(dev, "create qp failed\n"); 1828 goto err_create; 1829 } 1830 1831 kvfree(in); 1832 1833 base->container_mibqp = qp; 1834 base->mqp.event = mlx5_ib_qp_event; 1835 1836 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq, 1837 &send_cq, &recv_cq); 1838 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1839 mlx5_ib_lock_cqs(send_cq, recv_cq); 1840 /* Maintain device to QPs access, needed for further handling via reset 1841 * flow 1842 */ 1843 list_add_tail(&qp->qps_list, &dev->qp_list); 1844 /* Maintain CQ to QPs access, needed for further handling via reset flow 1845 */ 1846 if (send_cq) 1847 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 1848 if (recv_cq) 1849 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 1850 mlx5_ib_unlock_cqs(send_cq, recv_cq); 1851 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1852 1853 return 0; 1854 1855 err_create: 1856 if (qp->create_type == MLX5_QP_USER) 1857 destroy_qp_user(dev, pd, qp, base); 1858 else if (qp->create_type == MLX5_QP_KERNEL) 1859 destroy_qp_kernel(dev, qp); 1860 1861 kvfree(in); 1862 return err; 1863 } 1864 1865 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1866 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1867 { 1868 if (send_cq) { 1869 if (recv_cq) { 1870 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1871 spin_lock(&send_cq->lock); 1872 spin_lock_nested(&recv_cq->lock, 1873 SINGLE_DEPTH_NESTING); 1874 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1875 spin_lock(&send_cq->lock); 1876 __acquire(&recv_cq->lock); 1877 } else { 1878 spin_lock(&recv_cq->lock); 1879 spin_lock_nested(&send_cq->lock, 1880 SINGLE_DEPTH_NESTING); 1881 } 1882 } else { 1883 spin_lock(&send_cq->lock); 1884 __acquire(&recv_cq->lock); 1885 } 1886 } else if (recv_cq) { 1887 spin_lock(&recv_cq->lock); 1888 __acquire(&send_cq->lock); 1889 } else { 1890 __acquire(&send_cq->lock); 1891 __acquire(&recv_cq->lock); 1892 } 1893 } 1894 1895 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1896 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1897 { 1898 if (send_cq) { 1899 if (recv_cq) { 1900 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1901 spin_unlock(&recv_cq->lock); 1902 spin_unlock(&send_cq->lock); 1903 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1904 __release(&recv_cq->lock); 1905 spin_unlock(&send_cq->lock); 1906 } else { 1907 spin_unlock(&send_cq->lock); 1908 spin_unlock(&recv_cq->lock); 1909 } 1910 } else { 1911 __release(&recv_cq->lock); 1912 spin_unlock(&send_cq->lock); 1913 } 1914 } else if (recv_cq) { 1915 __release(&send_cq->lock); 1916 spin_unlock(&recv_cq->lock); 1917 } else { 1918 __release(&recv_cq->lock); 1919 __release(&send_cq->lock); 1920 } 1921 } 1922 1923 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 1924 { 1925 return to_mpd(qp->ibqp.pd); 1926 } 1927 1928 static void get_cqs(enum ib_qp_type qp_type, 1929 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 1930 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 1931 { 1932 switch (qp_type) { 1933 case IB_QPT_XRC_TGT: 1934 *send_cq = NULL; 1935 *recv_cq = NULL; 1936 break; 1937 case MLX5_IB_QPT_REG_UMR: 1938 case IB_QPT_XRC_INI: 1939 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 1940 *recv_cq = NULL; 1941 break; 1942 1943 case IB_QPT_SMI: 1944 case MLX5_IB_QPT_HW_GSI: 1945 case IB_QPT_RC: 1946 case IB_QPT_UC: 1947 case IB_QPT_UD: 1948 case IB_QPT_RAW_IPV6: 1949 case IB_QPT_RAW_ETHERTYPE: 1950 case IB_QPT_RAW_PACKET: 1951 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 1952 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 1953 break; 1954 1955 case IB_QPT_MAX: 1956 default: 1957 *send_cq = NULL; 1958 *recv_cq = NULL; 1959 break; 1960 } 1961 } 1962 1963 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1964 const struct mlx5_modify_raw_qp_param *raw_qp_param, 1965 u8 lag_tx_affinity); 1966 1967 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1968 { 1969 struct mlx5_ib_cq *send_cq, *recv_cq; 1970 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 1971 unsigned long flags; 1972 int err; 1973 1974 if (qp->ibqp.rwq_ind_tbl) { 1975 destroy_rss_raw_qp_tir(dev, qp); 1976 return; 1977 } 1978 1979 base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ? 1980 &qp->raw_packet_qp.rq.base : 1981 &qp->trans_qp.base; 1982 1983 if (qp->state != IB_QPS_RESET) { 1984 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) { 1985 mlx5_ib_qp_disable_pagefaults(qp); 1986 err = mlx5_core_qp_modify(dev->mdev, 1987 MLX5_CMD_OP_2RST_QP, 0, 1988 NULL, &base->mqp); 1989 } else { 1990 struct mlx5_modify_raw_qp_param raw_qp_param = { 1991 .operation = MLX5_CMD_OP_2RST_QP 1992 }; 1993 1994 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 1995 } 1996 if (err) 1997 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 1998 base->mqp.qpn); 1999 } 2000 2001 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2002 &send_cq, &recv_cq); 2003 2004 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2005 mlx5_ib_lock_cqs(send_cq, recv_cq); 2006 /* del from lists under both locks above to protect reset flow paths */ 2007 list_del(&qp->qps_list); 2008 if (send_cq) 2009 list_del(&qp->cq_send_list); 2010 2011 if (recv_cq) 2012 list_del(&qp->cq_recv_list); 2013 2014 if (qp->create_type == MLX5_QP_KERNEL) { 2015 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2016 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2017 if (send_cq != recv_cq) 2018 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2019 NULL); 2020 } 2021 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2022 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2023 2024 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 2025 destroy_raw_packet_qp(dev, qp); 2026 } else { 2027 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); 2028 if (err) 2029 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2030 base->mqp.qpn); 2031 } 2032 2033 if (qp->create_type == MLX5_QP_KERNEL) 2034 destroy_qp_kernel(dev, qp); 2035 else if (qp->create_type == MLX5_QP_USER) 2036 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base); 2037 } 2038 2039 static const char *ib_qp_type_str(enum ib_qp_type type) 2040 { 2041 switch (type) { 2042 case IB_QPT_SMI: 2043 return "IB_QPT_SMI"; 2044 case IB_QPT_GSI: 2045 return "IB_QPT_GSI"; 2046 case IB_QPT_RC: 2047 return "IB_QPT_RC"; 2048 case IB_QPT_UC: 2049 return "IB_QPT_UC"; 2050 case IB_QPT_UD: 2051 return "IB_QPT_UD"; 2052 case IB_QPT_RAW_IPV6: 2053 return "IB_QPT_RAW_IPV6"; 2054 case IB_QPT_RAW_ETHERTYPE: 2055 return "IB_QPT_RAW_ETHERTYPE"; 2056 case IB_QPT_XRC_INI: 2057 return "IB_QPT_XRC_INI"; 2058 case IB_QPT_XRC_TGT: 2059 return "IB_QPT_XRC_TGT"; 2060 case IB_QPT_RAW_PACKET: 2061 return "IB_QPT_RAW_PACKET"; 2062 case MLX5_IB_QPT_REG_UMR: 2063 return "MLX5_IB_QPT_REG_UMR"; 2064 case IB_QPT_MAX: 2065 default: 2066 return "Invalid QP type"; 2067 } 2068 } 2069 2070 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 2071 struct ib_qp_init_attr *init_attr, 2072 struct ib_udata *udata) 2073 { 2074 struct mlx5_ib_dev *dev; 2075 struct mlx5_ib_qp *qp; 2076 u16 xrcdn = 0; 2077 int err; 2078 2079 if (pd) { 2080 dev = to_mdev(pd->device); 2081 2082 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 2083 if (!pd->uobject) { 2084 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); 2085 return ERR_PTR(-EINVAL); 2086 } else if (!to_mucontext(pd->uobject->context)->cqe_version) { 2087 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); 2088 return ERR_PTR(-EINVAL); 2089 } 2090 } 2091 } else { 2092 /* being cautious here */ 2093 if (init_attr->qp_type != IB_QPT_XRC_TGT && 2094 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 2095 pr_warn("%s: no PD for transport %s\n", __func__, 2096 ib_qp_type_str(init_attr->qp_type)); 2097 return ERR_PTR(-EINVAL); 2098 } 2099 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 2100 } 2101 2102 switch (init_attr->qp_type) { 2103 case IB_QPT_XRC_TGT: 2104 case IB_QPT_XRC_INI: 2105 if (!MLX5_CAP_GEN(dev->mdev, xrc)) { 2106 mlx5_ib_dbg(dev, "XRC not supported\n"); 2107 return ERR_PTR(-ENOSYS); 2108 } 2109 init_attr->recv_cq = NULL; 2110 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 2111 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 2112 init_attr->send_cq = NULL; 2113 } 2114 2115 /* fall through */ 2116 case IB_QPT_RAW_PACKET: 2117 case IB_QPT_RC: 2118 case IB_QPT_UC: 2119 case IB_QPT_UD: 2120 case IB_QPT_SMI: 2121 case MLX5_IB_QPT_HW_GSI: 2122 case MLX5_IB_QPT_REG_UMR: 2123 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2124 if (!qp) 2125 return ERR_PTR(-ENOMEM); 2126 2127 err = create_qp_common(dev, pd, init_attr, udata, qp); 2128 if (err) { 2129 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 2130 kfree(qp); 2131 return ERR_PTR(err); 2132 } 2133 2134 if (is_qp0(init_attr->qp_type)) 2135 qp->ibqp.qp_num = 0; 2136 else if (is_qp1(init_attr->qp_type)) 2137 qp->ibqp.qp_num = 1; 2138 else 2139 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2140 2141 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 2142 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2143 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1, 2144 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1); 2145 2146 qp->trans_qp.xrcdn = xrcdn; 2147 2148 break; 2149 2150 case IB_QPT_GSI: 2151 return mlx5_ib_gsi_create_qp(pd, init_attr); 2152 2153 case IB_QPT_RAW_IPV6: 2154 case IB_QPT_RAW_ETHERTYPE: 2155 case IB_QPT_MAX: 2156 default: 2157 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 2158 init_attr->qp_type); 2159 /* Don't support raw QPs */ 2160 return ERR_PTR(-EINVAL); 2161 } 2162 2163 return &qp->ibqp; 2164 } 2165 2166 int mlx5_ib_destroy_qp(struct ib_qp *qp) 2167 { 2168 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2169 struct mlx5_ib_qp *mqp = to_mqp(qp); 2170 2171 if (unlikely(qp->qp_type == IB_QPT_GSI)) 2172 return mlx5_ib_gsi_destroy_qp(qp); 2173 2174 destroy_qp_common(dev, mqp); 2175 2176 kfree(mqp); 2177 2178 return 0; 2179 } 2180 2181 static int to_mlx5_access_flags(struct mlx5_ib_qp *qp, 2182 const struct ib_qp_attr *attr, 2183 int attr_mask, __be32 *hw_access_flags_be) 2184 { 2185 u8 dest_rd_atomic; 2186 u32 access_flags, hw_access_flags = 0; 2187 2188 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 2189 2190 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2191 dest_rd_atomic = attr->max_dest_rd_atomic; 2192 else 2193 dest_rd_atomic = qp->trans_qp.resp_depth; 2194 2195 if (attr_mask & IB_QP_ACCESS_FLAGS) 2196 access_flags = attr->qp_access_flags; 2197 else 2198 access_flags = qp->trans_qp.atomic_rd_en; 2199 2200 if (!dest_rd_atomic) 2201 access_flags &= IB_ACCESS_REMOTE_WRITE; 2202 2203 if (access_flags & IB_ACCESS_REMOTE_READ) 2204 hw_access_flags |= MLX5_QP_BIT_RRE; 2205 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) { 2206 int atomic_mode; 2207 2208 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type); 2209 if (atomic_mode < 0) 2210 return -EOPNOTSUPP; 2211 2212 hw_access_flags |= MLX5_QP_BIT_RAE; 2213 hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFF; 2214 } 2215 2216 if (access_flags & IB_ACCESS_REMOTE_WRITE) 2217 hw_access_flags |= MLX5_QP_BIT_RWE; 2218 2219 *hw_access_flags_be = cpu_to_be32(hw_access_flags); 2220 2221 return 0; 2222 } 2223 2224 enum { 2225 MLX5_PATH_FLAG_FL = 1 << 0, 2226 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 2227 MLX5_PATH_FLAG_COUNTER = 1 << 2, 2228 }; 2229 2230 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 2231 { 2232 if (rate == IB_RATE_PORT_CURRENT) { 2233 return 0; 2234 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS) { 2235 return -EINVAL; 2236 } else { 2237 while (rate != IB_RATE_2_5_GBPS && 2238 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 2239 MLX5_CAP_GEN(dev->mdev, stat_rate_support))) 2240 --rate; 2241 } 2242 2243 return rate + MLX5_STAT_RATE_OFFSET; 2244 } 2245 2246 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 2247 struct mlx5_ib_sq *sq, u8 sl) 2248 { 2249 void *in; 2250 void *tisc; 2251 int inlen; 2252 int err; 2253 2254 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2255 in = mlx5_vzalloc(inlen); 2256 if (!in) 2257 return -ENOMEM; 2258 2259 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 2260 2261 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2262 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 2263 2264 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2265 2266 kvfree(in); 2267 2268 return err; 2269 } 2270 2271 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 2272 struct mlx5_ib_sq *sq, u8 tx_affinity) 2273 { 2274 void *in; 2275 void *tisc; 2276 int inlen; 2277 int err; 2278 2279 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2280 in = mlx5_vzalloc(inlen); 2281 if (!in) 2282 return -ENOMEM; 2283 2284 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 2285 2286 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2287 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 2288 2289 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2290 2291 kvfree(in); 2292 2293 return err; 2294 } 2295 2296 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2297 const struct ib_ah_attr *ah, 2298 struct mlx5_qp_path *path, u8 port, int attr_mask, 2299 u32 path_flags, const struct ib_qp_attr *attr, 2300 bool alt) 2301 { 2302 enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port); 2303 int err; 2304 enum ib_gid_type gid_type; 2305 2306 if (attr_mask & IB_QP_PKEY_INDEX) 2307 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index : 2308 attr->pkey_index); 2309 2310 if (ah->ah_flags & IB_AH_GRH) { 2311 if (ah->grh.sgid_index >= 2312 dev->mdev->port_caps[port - 1].gid_table_len) { 2313 pr_err("sgid_index (%u) too large. max is %d\n", 2314 ah->grh.sgid_index, 2315 dev->mdev->port_caps[port - 1].gid_table_len); 2316 return -EINVAL; 2317 } 2318 } 2319 2320 if (ll == IB_LINK_LAYER_ETHERNET) { 2321 if (!(ah->ah_flags & IB_AH_GRH)) 2322 return -EINVAL; 2323 err = mlx5_get_roce_gid_type(dev, port, ah->grh.sgid_index, 2324 &gid_type); 2325 if (err) 2326 return err; 2327 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac)); 2328 path->udp_sport = mlx5_get_roce_udp_sport(dev, port, 2329 ah->grh.sgid_index); 2330 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4; 2331 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 2332 path->ecn_dscp = (ah->grh.traffic_class >> 2) & 0x3f; 2333 } else { 2334 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 2335 path->fl_free_ar |= 2336 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0; 2337 path->rlid = cpu_to_be16(ah->dlid); 2338 path->grh_mlid = ah->src_path_bits & 0x7f; 2339 if (ah->ah_flags & IB_AH_GRH) 2340 path->grh_mlid |= 1 << 7; 2341 path->dci_cfi_prio_sl = ah->sl & 0xf; 2342 } 2343 2344 if (ah->ah_flags & IB_AH_GRH) { 2345 path->mgid_index = ah->grh.sgid_index; 2346 path->hop_limit = ah->grh.hop_limit; 2347 path->tclass_flowlabel = 2348 cpu_to_be32((ah->grh.traffic_class << 20) | 2349 (ah->grh.flow_label)); 2350 memcpy(path->rgid, ah->grh.dgid.raw, 16); 2351 } 2352 2353 err = ib_rate_to_mlx5(dev, ah->static_rate); 2354 if (err < 0) 2355 return err; 2356 path->static_rate = err; 2357 path->port = port; 2358 2359 if (attr_mask & IB_QP_TIMEOUT) 2360 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3; 2361 2362 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 2363 return modify_raw_packet_eth_prio(dev->mdev, 2364 &qp->raw_packet_qp.sq, 2365 ah->sl & 0xf); 2366 2367 return 0; 2368 } 2369 2370 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 2371 [MLX5_QP_STATE_INIT] = { 2372 [MLX5_QP_STATE_INIT] = { 2373 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2374 MLX5_QP_OPTPAR_RAE | 2375 MLX5_QP_OPTPAR_RWE | 2376 MLX5_QP_OPTPAR_PKEY_INDEX | 2377 MLX5_QP_OPTPAR_PRI_PORT, 2378 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2379 MLX5_QP_OPTPAR_PKEY_INDEX | 2380 MLX5_QP_OPTPAR_PRI_PORT, 2381 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2382 MLX5_QP_OPTPAR_Q_KEY | 2383 MLX5_QP_OPTPAR_PRI_PORT, 2384 }, 2385 [MLX5_QP_STATE_RTR] = { 2386 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2387 MLX5_QP_OPTPAR_RRE | 2388 MLX5_QP_OPTPAR_RAE | 2389 MLX5_QP_OPTPAR_RWE | 2390 MLX5_QP_OPTPAR_PKEY_INDEX, 2391 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2392 MLX5_QP_OPTPAR_RWE | 2393 MLX5_QP_OPTPAR_PKEY_INDEX, 2394 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2395 MLX5_QP_OPTPAR_Q_KEY, 2396 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 2397 MLX5_QP_OPTPAR_Q_KEY, 2398 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2399 MLX5_QP_OPTPAR_RRE | 2400 MLX5_QP_OPTPAR_RAE | 2401 MLX5_QP_OPTPAR_RWE | 2402 MLX5_QP_OPTPAR_PKEY_INDEX, 2403 }, 2404 }, 2405 [MLX5_QP_STATE_RTR] = { 2406 [MLX5_QP_STATE_RTS] = { 2407 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2408 MLX5_QP_OPTPAR_RRE | 2409 MLX5_QP_OPTPAR_RAE | 2410 MLX5_QP_OPTPAR_RWE | 2411 MLX5_QP_OPTPAR_PM_STATE | 2412 MLX5_QP_OPTPAR_RNR_TIMEOUT, 2413 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2414 MLX5_QP_OPTPAR_RWE | 2415 MLX5_QP_OPTPAR_PM_STATE, 2416 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2417 }, 2418 }, 2419 [MLX5_QP_STATE_RTS] = { 2420 [MLX5_QP_STATE_RTS] = { 2421 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2422 MLX5_QP_OPTPAR_RAE | 2423 MLX5_QP_OPTPAR_RWE | 2424 MLX5_QP_OPTPAR_RNR_TIMEOUT | 2425 MLX5_QP_OPTPAR_PM_STATE | 2426 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2427 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2428 MLX5_QP_OPTPAR_PM_STATE | 2429 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2430 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 2431 MLX5_QP_OPTPAR_SRQN | 2432 MLX5_QP_OPTPAR_CQN_RCV, 2433 }, 2434 }, 2435 [MLX5_QP_STATE_SQER] = { 2436 [MLX5_QP_STATE_RTS] = { 2437 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2438 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 2439 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 2440 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 2441 MLX5_QP_OPTPAR_RWE | 2442 MLX5_QP_OPTPAR_RAE | 2443 MLX5_QP_OPTPAR_RRE, 2444 }, 2445 }, 2446 }; 2447 2448 static int ib_nr_to_mlx5_nr(int ib_mask) 2449 { 2450 switch (ib_mask) { 2451 case IB_QP_STATE: 2452 return 0; 2453 case IB_QP_CUR_STATE: 2454 return 0; 2455 case IB_QP_EN_SQD_ASYNC_NOTIFY: 2456 return 0; 2457 case IB_QP_ACCESS_FLAGS: 2458 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 2459 MLX5_QP_OPTPAR_RAE; 2460 case IB_QP_PKEY_INDEX: 2461 return MLX5_QP_OPTPAR_PKEY_INDEX; 2462 case IB_QP_PORT: 2463 return MLX5_QP_OPTPAR_PRI_PORT; 2464 case IB_QP_QKEY: 2465 return MLX5_QP_OPTPAR_Q_KEY; 2466 case IB_QP_AV: 2467 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 2468 MLX5_QP_OPTPAR_PRI_PORT; 2469 case IB_QP_PATH_MTU: 2470 return 0; 2471 case IB_QP_TIMEOUT: 2472 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 2473 case IB_QP_RETRY_CNT: 2474 return MLX5_QP_OPTPAR_RETRY_COUNT; 2475 case IB_QP_RNR_RETRY: 2476 return MLX5_QP_OPTPAR_RNR_RETRY; 2477 case IB_QP_RQ_PSN: 2478 return 0; 2479 case IB_QP_MAX_QP_RD_ATOMIC: 2480 return MLX5_QP_OPTPAR_SRA_MAX; 2481 case IB_QP_ALT_PATH: 2482 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 2483 case IB_QP_MIN_RNR_TIMER: 2484 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 2485 case IB_QP_SQ_PSN: 2486 return 0; 2487 case IB_QP_MAX_DEST_RD_ATOMIC: 2488 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 2489 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 2490 case IB_QP_PATH_MIG_STATE: 2491 return MLX5_QP_OPTPAR_PM_STATE; 2492 case IB_QP_CAP: 2493 return 0; 2494 case IB_QP_DEST_QPN: 2495 return 0; 2496 } 2497 return 0; 2498 } 2499 2500 static int ib_mask_to_mlx5_opt(int ib_mask) 2501 { 2502 int result = 0; 2503 int i; 2504 2505 for (i = 0; i < 8 * sizeof(int); i++) { 2506 if ((1 << i) & ib_mask) 2507 result |= ib_nr_to_mlx5_nr(1 << i); 2508 } 2509 2510 return result; 2511 } 2512 2513 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 2514 struct mlx5_ib_rq *rq, int new_state, 2515 const struct mlx5_modify_raw_qp_param *raw_qp_param) 2516 { 2517 void *in; 2518 void *rqc; 2519 int inlen; 2520 int err; 2521 2522 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 2523 in = mlx5_vzalloc(inlen); 2524 if (!in) 2525 return -ENOMEM; 2526 2527 MLX5_SET(modify_rq_in, in, rqn, rq->base.mqp.qpn); 2528 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 2529 2530 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 2531 MLX5_SET(rqc, rqc, state, new_state); 2532 2533 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 2534 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counters_set_id)) { 2535 MLX5_SET64(modify_rq_in, in, modify_bitmask, 2536 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID); 2537 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 2538 } else 2539 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n", 2540 dev->ib_dev.name); 2541 } 2542 2543 err = mlx5_core_modify_rq(dev->mdev, in, inlen); 2544 if (err) 2545 goto out; 2546 2547 rq->state = new_state; 2548 2549 out: 2550 kvfree(in); 2551 return err; 2552 } 2553 2554 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev, 2555 struct mlx5_ib_sq *sq, int new_state) 2556 { 2557 void *in; 2558 void *sqc; 2559 int inlen; 2560 int err; 2561 2562 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 2563 in = mlx5_vzalloc(inlen); 2564 if (!in) 2565 return -ENOMEM; 2566 2567 MLX5_SET(modify_sq_in, in, sqn, sq->base.mqp.qpn); 2568 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 2569 2570 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 2571 MLX5_SET(sqc, sqc, state, new_state); 2572 2573 err = mlx5_core_modify_sq(dev, in, inlen); 2574 if (err) 2575 goto out; 2576 2577 sq->state = new_state; 2578 2579 out: 2580 kvfree(in); 2581 return err; 2582 } 2583 2584 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2585 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2586 u8 tx_affinity) 2587 { 2588 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 2589 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 2590 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 2591 int rq_state; 2592 int sq_state; 2593 int err; 2594 2595 switch (raw_qp_param->operation) { 2596 case MLX5_CMD_OP_RST2INIT_QP: 2597 rq_state = MLX5_RQC_STATE_RDY; 2598 sq_state = MLX5_SQC_STATE_RDY; 2599 break; 2600 case MLX5_CMD_OP_2ERR_QP: 2601 rq_state = MLX5_RQC_STATE_ERR; 2602 sq_state = MLX5_SQC_STATE_ERR; 2603 break; 2604 case MLX5_CMD_OP_2RST_QP: 2605 rq_state = MLX5_RQC_STATE_RST; 2606 sq_state = MLX5_SQC_STATE_RST; 2607 break; 2608 case MLX5_CMD_OP_INIT2INIT_QP: 2609 case MLX5_CMD_OP_INIT2RTR_QP: 2610 case MLX5_CMD_OP_RTR2RTS_QP: 2611 case MLX5_CMD_OP_RTS2RTS_QP: 2612 if (raw_qp_param->set_mask) 2613 return -EINVAL; 2614 else 2615 return 0; 2616 default: 2617 WARN_ON(1); 2618 return -EINVAL; 2619 } 2620 2621 if (qp->rq.wqe_cnt) { 2622 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param); 2623 if (err) 2624 return err; 2625 } 2626 2627 if (qp->sq.wqe_cnt) { 2628 if (tx_affinity) { 2629 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 2630 tx_affinity); 2631 if (err) 2632 return err; 2633 } 2634 2635 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state); 2636 } 2637 2638 return 0; 2639 } 2640 2641 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 2642 const struct ib_qp_attr *attr, int attr_mask, 2643 enum ib_qp_state cur_state, enum ib_qp_state new_state) 2644 { 2645 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 2646 [MLX5_QP_STATE_RST] = { 2647 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2648 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2649 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 2650 }, 2651 [MLX5_QP_STATE_INIT] = { 2652 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2653 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2654 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 2655 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 2656 }, 2657 [MLX5_QP_STATE_RTR] = { 2658 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2659 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2660 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 2661 }, 2662 [MLX5_QP_STATE_RTS] = { 2663 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2664 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2665 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 2666 }, 2667 [MLX5_QP_STATE_SQD] = { 2668 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2669 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2670 }, 2671 [MLX5_QP_STATE_SQER] = { 2672 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2673 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2674 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 2675 }, 2676 [MLX5_QP_STATE_ERR] = { 2677 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2678 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2679 } 2680 }; 2681 2682 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2683 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2684 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 2685 struct mlx5_ib_cq *send_cq, *recv_cq; 2686 struct mlx5_qp_context *context; 2687 struct mlx5_ib_pd *pd; 2688 struct mlx5_ib_port *mibport = NULL; 2689 enum mlx5_qp_state mlx5_cur, mlx5_new; 2690 enum mlx5_qp_optpar optpar; 2691 int sqd_event; 2692 int mlx5_st; 2693 int err; 2694 u16 op; 2695 2696 context = kzalloc(sizeof(*context), GFP_KERNEL); 2697 if (!context) 2698 return -ENOMEM; 2699 2700 err = to_mlx5_st(ibqp->qp_type); 2701 if (err < 0) { 2702 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type); 2703 goto out; 2704 } 2705 2706 context->flags = cpu_to_be32(err << 16); 2707 2708 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 2709 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2710 } else { 2711 switch (attr->path_mig_state) { 2712 case IB_MIG_MIGRATED: 2713 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2714 break; 2715 case IB_MIG_REARM: 2716 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 2717 break; 2718 case IB_MIG_ARMED: 2719 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 2720 break; 2721 } 2722 } 2723 2724 if (is_sqp(ibqp->qp_type)) { 2725 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 2726 } else if (ibqp->qp_type == IB_QPT_UD || 2727 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 2728 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 2729 } else if (attr_mask & IB_QP_PATH_MTU) { 2730 if (attr->path_mtu < IB_MTU_256 || 2731 attr->path_mtu > IB_MTU_4096) { 2732 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 2733 err = -EINVAL; 2734 goto out; 2735 } 2736 context->mtu_msgmax = (attr->path_mtu << 5) | 2737 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); 2738 } 2739 2740 if (attr_mask & IB_QP_DEST_QPN) 2741 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 2742 2743 if (attr_mask & IB_QP_PKEY_INDEX) 2744 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index); 2745 2746 /* todo implement counter_index functionality */ 2747 2748 if (is_sqp(ibqp->qp_type)) 2749 context->pri_path.port = qp->port; 2750 2751 if (attr_mask & IB_QP_PORT) 2752 context->pri_path.port = attr->port_num; 2753 2754 if (attr_mask & IB_QP_AV) { 2755 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, 2756 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 2757 attr_mask, 0, attr, false); 2758 if (err) 2759 goto out; 2760 } 2761 2762 if (attr_mask & IB_QP_TIMEOUT) 2763 context->pri_path.ackto_lt |= attr->timeout << 3; 2764 2765 if (attr_mask & IB_QP_ALT_PATH) { 2766 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, 2767 &context->alt_path, 2768 attr->alt_port_num, 2769 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT, 2770 0, attr, true); 2771 if (err) 2772 goto out; 2773 } 2774 2775 pd = get_pd(qp); 2776 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2777 &send_cq, &recv_cq); 2778 2779 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 2780 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 2781 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 2782 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 2783 2784 if (attr_mask & IB_QP_RNR_RETRY) 2785 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 2786 2787 if (attr_mask & IB_QP_RETRY_CNT) 2788 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 2789 2790 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2791 if (attr->max_rd_atomic) 2792 context->params1 |= 2793 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 2794 } 2795 2796 if (attr_mask & IB_QP_SQ_PSN) 2797 context->next_send_psn = cpu_to_be32(attr->sq_psn); 2798 2799 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2800 if (attr->max_dest_rd_atomic) 2801 context->params2 |= 2802 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 2803 } 2804 2805 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 2806 __be32 access_flags; 2807 2808 err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags); 2809 if (err) 2810 goto out; 2811 2812 context->params2 |= access_flags; 2813 } 2814 2815 if (attr_mask & IB_QP_MIN_RNR_TIMER) 2816 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 2817 2818 if (attr_mask & IB_QP_RQ_PSN) 2819 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 2820 2821 if (attr_mask & IB_QP_QKEY) 2822 context->qkey = cpu_to_be32(attr->qkey); 2823 2824 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2825 context->db_rec_addr = cpu_to_be64(qp->db.dma); 2826 2827 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && 2828 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify) 2829 sqd_event = 1; 2830 else 2831 sqd_event = 0; 2832 2833 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2834 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 2835 qp->port) - 1; 2836 mibport = &dev->port[port_num]; 2837 context->qp_counter_set_usr_page |= 2838 cpu_to_be32((u32)(mibport->q_cnt_id) << 24); 2839 } 2840 2841 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2842 context->sq_crq_size |= cpu_to_be16(1 << 4); 2843 2844 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 2845 context->deth_sqpn = cpu_to_be32(1); 2846 2847 mlx5_cur = to_mlx5_state(cur_state); 2848 mlx5_new = to_mlx5_state(new_state); 2849 mlx5_st = to_mlx5_st(ibqp->qp_type); 2850 if (mlx5_st < 0) 2851 goto out; 2852 2853 /* If moving to a reset or error state, we must disable page faults on 2854 * this QP and flush all current page faults. Otherwise a stale page 2855 * fault may attempt to work on this QP after it is reset and moved 2856 * again to RTS, and may cause the driver and the device to get out of 2857 * sync. */ 2858 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR && 2859 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) && 2860 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET)) 2861 mlx5_ib_qp_disable_pagefaults(qp); 2862 2863 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 2864 !optab[mlx5_cur][mlx5_new]) 2865 goto out; 2866 2867 op = optab[mlx5_cur][mlx5_new]; 2868 optpar = ib_mask_to_mlx5_opt(attr_mask); 2869 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 2870 2871 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 2872 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 2873 2874 raw_qp_param.operation = op; 2875 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2876 raw_qp_param.rq_q_ctr_id = mibport->q_cnt_id; 2877 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 2878 } 2879 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2880 } else { 2881 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context, 2882 &base->mqp); 2883 } 2884 2885 if (err) 2886 goto out; 2887 2888 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT && 2889 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET)) 2890 mlx5_ib_qp_enable_pagefaults(qp); 2891 2892 qp->state = new_state; 2893 2894 if (attr_mask & IB_QP_ACCESS_FLAGS) 2895 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 2896 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2897 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 2898 if (attr_mask & IB_QP_PORT) 2899 qp->port = attr->port_num; 2900 if (attr_mask & IB_QP_ALT_PATH) 2901 qp->trans_qp.alt_port = attr->alt_port_num; 2902 2903 /* 2904 * If we moved a kernel QP to RESET, clean up all old CQ 2905 * entries and reinitialize the QP. 2906 */ 2907 if (new_state == IB_QPS_RESET && !ibqp->uobject) { 2908 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2909 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 2910 if (send_cq != recv_cq) 2911 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 2912 2913 qp->rq.head = 0; 2914 qp->rq.tail = 0; 2915 qp->sq.head = 0; 2916 qp->sq.tail = 0; 2917 qp->sq.cur_post = 0; 2918 qp->sq.last_poll = 0; 2919 qp->db.db[MLX5_RCV_DBR] = 0; 2920 qp->db.db[MLX5_SND_DBR] = 0; 2921 } 2922 2923 out: 2924 kfree(context); 2925 return err; 2926 } 2927 2928 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2929 int attr_mask, struct ib_udata *udata) 2930 { 2931 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2932 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2933 enum ib_qp_type qp_type; 2934 enum ib_qp_state cur_state, new_state; 2935 int err = -EINVAL; 2936 int port; 2937 2938 if (ibqp->rwq_ind_tbl) 2939 return -ENOSYS; 2940 2941 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 2942 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 2943 2944 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? 2945 IB_QPT_GSI : ibqp->qp_type; 2946 2947 mutex_lock(&qp->mutex); 2948 2949 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 2950 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 2951 2952 if (qp_type != MLX5_IB_QPT_REG_UMR && 2953 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask)) { 2954 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 2955 cur_state, new_state, ibqp->qp_type, attr_mask); 2956 goto out; 2957 } 2958 2959 if ((attr_mask & IB_QP_PORT) && 2960 (attr->port_num == 0 || 2961 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) { 2962 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 2963 attr->port_num, dev->num_ports); 2964 goto out; 2965 } 2966 2967 if (attr_mask & IB_QP_PKEY_INDEX) { 2968 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2969 if (attr->pkey_index >= 2970 dev->mdev->port_caps[port - 1].pkey_table_len) { 2971 mlx5_ib_dbg(dev, "invalid pkey index %d\n", 2972 attr->pkey_index); 2973 goto out; 2974 } 2975 } 2976 2977 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 2978 attr->max_rd_atomic > 2979 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 2980 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 2981 attr->max_rd_atomic); 2982 goto out; 2983 } 2984 2985 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 2986 attr->max_dest_rd_atomic > 2987 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 2988 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 2989 attr->max_dest_rd_atomic); 2990 goto out; 2991 } 2992 2993 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 2994 err = 0; 2995 goto out; 2996 } 2997 2998 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state); 2999 3000 out: 3001 mutex_unlock(&qp->mutex); 3002 return err; 3003 } 3004 3005 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 3006 { 3007 struct mlx5_ib_cq *cq; 3008 unsigned cur; 3009 3010 cur = wq->head - wq->tail; 3011 if (likely(cur + nreq < wq->max_post)) 3012 return 0; 3013 3014 cq = to_mcq(ib_cq); 3015 spin_lock(&cq->lock); 3016 cur = wq->head - wq->tail; 3017 spin_unlock(&cq->lock); 3018 3019 return cur + nreq >= wq->max_post; 3020 } 3021 3022 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 3023 u64 remote_addr, u32 rkey) 3024 { 3025 rseg->raddr = cpu_to_be64(remote_addr); 3026 rseg->rkey = cpu_to_be32(rkey); 3027 rseg->reserved = 0; 3028 } 3029 3030 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg, 3031 const struct ib_send_wr *wr, void *qend, 3032 struct mlx5_ib_qp *qp, int *size) 3033 { 3034 void *seg = eseg; 3035 3036 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); 3037 3038 if (wr->send_flags & IB_SEND_IP_CSUM) 3039 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | 3040 MLX5_ETH_WQE_L4_CSUM; 3041 3042 seg += sizeof(struct mlx5_wqe_eth_seg); 3043 *size += sizeof(struct mlx5_wqe_eth_seg) / 16; 3044 3045 if (wr->opcode == IB_WR_LSO) { 3046 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr); 3047 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start); 3048 u64 left, leftlen, copysz; 3049 void *pdata = ud_wr->header; 3050 3051 left = ud_wr->hlen; 3052 eseg->mss = cpu_to_be16(ud_wr->mss); 3053 eseg->inline_hdr_sz = cpu_to_be16(left); 3054 3055 /* 3056 * check if there is space till the end of queue, if yes, 3057 * copy all in one shot, otherwise copy till the end of queue, 3058 * rollback and than the copy the left 3059 */ 3060 leftlen = qend - (void *)eseg->inline_hdr_start; 3061 copysz = min_t(u64, leftlen, left); 3062 3063 memcpy(seg - size_of_inl_hdr_start, pdata, copysz); 3064 3065 if (likely(copysz > size_of_inl_hdr_start)) { 3066 seg += ALIGN(copysz - size_of_inl_hdr_start, 16); 3067 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16; 3068 } 3069 3070 if (unlikely(copysz < left)) { /* the last wqe in the queue */ 3071 seg = mlx5_get_send_wqe(qp, 0); 3072 left -= copysz; 3073 pdata += copysz; 3074 memcpy(seg, pdata, left); 3075 seg += ALIGN(left, 16); 3076 *size += ALIGN(left, 16) / 16; 3077 } 3078 } 3079 3080 return seg; 3081 } 3082 3083 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 3084 const struct ib_send_wr *wr) 3085 { 3086 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); 3087 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); 3088 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); 3089 } 3090 3091 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 3092 { 3093 dseg->byte_count = cpu_to_be32(sg->length); 3094 dseg->lkey = cpu_to_be32(sg->lkey); 3095 dseg->addr = cpu_to_be64(sg->addr); 3096 } 3097 3098 static __be16 get_klm_octo(int npages) 3099 { 3100 return cpu_to_be16(ALIGN(npages, 8) / 2); 3101 } 3102 3103 static __be64 frwr_mkey_mask(void) 3104 { 3105 u64 result; 3106 3107 result = MLX5_MKEY_MASK_LEN | 3108 MLX5_MKEY_MASK_PAGE_SIZE | 3109 MLX5_MKEY_MASK_START_ADDR | 3110 MLX5_MKEY_MASK_EN_RINVAL | 3111 MLX5_MKEY_MASK_KEY | 3112 MLX5_MKEY_MASK_LR | 3113 MLX5_MKEY_MASK_LW | 3114 MLX5_MKEY_MASK_RR | 3115 MLX5_MKEY_MASK_RW | 3116 MLX5_MKEY_MASK_A | 3117 MLX5_MKEY_MASK_SMALL_FENCE | 3118 MLX5_MKEY_MASK_FREE; 3119 3120 return cpu_to_be64(result); 3121 } 3122 3123 static __be64 sig_mkey_mask(void) 3124 { 3125 u64 result; 3126 3127 result = MLX5_MKEY_MASK_LEN | 3128 MLX5_MKEY_MASK_PAGE_SIZE | 3129 MLX5_MKEY_MASK_START_ADDR | 3130 MLX5_MKEY_MASK_EN_SIGERR | 3131 MLX5_MKEY_MASK_EN_RINVAL | 3132 MLX5_MKEY_MASK_KEY | 3133 MLX5_MKEY_MASK_LR | 3134 MLX5_MKEY_MASK_LW | 3135 MLX5_MKEY_MASK_RR | 3136 MLX5_MKEY_MASK_RW | 3137 MLX5_MKEY_MASK_SMALL_FENCE | 3138 MLX5_MKEY_MASK_FREE | 3139 MLX5_MKEY_MASK_BSF_EN; 3140 3141 return cpu_to_be64(result); 3142 } 3143 3144 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, 3145 struct mlx5_ib_mr *mr) 3146 { 3147 int ndescs = mr->ndescs; 3148 3149 memset(umr, 0, sizeof(*umr)); 3150 3151 if (mr->access_mode == MLX5_ACCESS_MODE_KLM) 3152 /* KLMs take twice the size of MTTs */ 3153 ndescs *= 2; 3154 3155 umr->flags = MLX5_UMR_CHECK_NOT_FREE; 3156 umr->klm_octowords = get_klm_octo(ndescs); 3157 umr->mkey_mask = frwr_mkey_mask(); 3158 } 3159 3160 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) 3161 { 3162 memset(umr, 0, sizeof(*umr)); 3163 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 3164 umr->flags = 1 << 7; 3165 } 3166 3167 static __be64 get_umr_reg_mr_mask(void) 3168 { 3169 u64 result; 3170 3171 result = MLX5_MKEY_MASK_LEN | 3172 MLX5_MKEY_MASK_PAGE_SIZE | 3173 MLX5_MKEY_MASK_START_ADDR | 3174 MLX5_MKEY_MASK_PD | 3175 MLX5_MKEY_MASK_LR | 3176 MLX5_MKEY_MASK_LW | 3177 MLX5_MKEY_MASK_KEY | 3178 MLX5_MKEY_MASK_RR | 3179 MLX5_MKEY_MASK_RW | 3180 MLX5_MKEY_MASK_A | 3181 MLX5_MKEY_MASK_FREE; 3182 3183 return cpu_to_be64(result); 3184 } 3185 3186 static __be64 get_umr_unreg_mr_mask(void) 3187 { 3188 u64 result; 3189 3190 result = MLX5_MKEY_MASK_FREE; 3191 3192 return cpu_to_be64(result); 3193 } 3194 3195 static __be64 get_umr_update_mtt_mask(void) 3196 { 3197 u64 result; 3198 3199 result = MLX5_MKEY_MASK_FREE; 3200 3201 return cpu_to_be64(result); 3202 } 3203 3204 static __be64 get_umr_update_translation_mask(void) 3205 { 3206 u64 result; 3207 3208 result = MLX5_MKEY_MASK_LEN | 3209 MLX5_MKEY_MASK_PAGE_SIZE | 3210 MLX5_MKEY_MASK_START_ADDR | 3211 MLX5_MKEY_MASK_KEY | 3212 MLX5_MKEY_MASK_FREE; 3213 3214 return cpu_to_be64(result); 3215 } 3216 3217 static __be64 get_umr_update_access_mask(void) 3218 { 3219 u64 result; 3220 3221 result = MLX5_MKEY_MASK_LW | 3222 MLX5_MKEY_MASK_RR | 3223 MLX5_MKEY_MASK_RW | 3224 MLX5_MKEY_MASK_A | 3225 MLX5_MKEY_MASK_KEY | 3226 MLX5_MKEY_MASK_FREE; 3227 3228 return cpu_to_be64(result); 3229 } 3230 3231 static __be64 get_umr_update_pd_mask(void) 3232 { 3233 u64 result; 3234 3235 result = MLX5_MKEY_MASK_PD | 3236 MLX5_MKEY_MASK_KEY | 3237 MLX5_MKEY_MASK_FREE; 3238 3239 return cpu_to_be64(result); 3240 } 3241 3242 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 3243 const struct ib_send_wr *wr) 3244 { 3245 const struct mlx5_umr_wr *umrwr = umr_wr(wr); 3246 3247 memset(umr, 0, sizeof(*umr)); 3248 3249 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) 3250 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */ 3251 else 3252 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */ 3253 3254 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) { 3255 umr->klm_octowords = get_klm_octo(umrwr->npages); 3256 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) { 3257 umr->mkey_mask = get_umr_update_mtt_mask(); 3258 umr->bsf_octowords = get_klm_octo(umrwr->target.offset); 3259 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 3260 } 3261 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION) 3262 umr->mkey_mask |= get_umr_update_translation_mask(); 3263 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_ACCESS) 3264 umr->mkey_mask |= get_umr_update_access_mask(); 3265 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD) 3266 umr->mkey_mask |= get_umr_update_pd_mask(); 3267 if (!umr->mkey_mask) 3268 umr->mkey_mask = get_umr_reg_mr_mask(); 3269 } else { 3270 umr->mkey_mask = get_umr_unreg_mr_mask(); 3271 } 3272 3273 if (!wr->num_sge) 3274 umr->flags |= MLX5_UMR_INLINE; 3275 } 3276 3277 static u8 get_umr_flags(int acc) 3278 { 3279 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 3280 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 3281 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 3282 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 3283 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 3284 } 3285 3286 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, 3287 struct mlx5_ib_mr *mr, 3288 u32 key, int access) 3289 { 3290 int ndescs = ALIGN(mr->ndescs, 8) >> 1; 3291 3292 memset(seg, 0, sizeof(*seg)); 3293 3294 if (mr->access_mode == MLX5_ACCESS_MODE_MTT) 3295 seg->log2_page_size = ilog2(mr->ibmr.page_size); 3296 else if (mr->access_mode == MLX5_ACCESS_MODE_KLM) 3297 /* KLMs take twice the size of MTTs */ 3298 ndescs *= 2; 3299 3300 seg->flags = get_umr_flags(access) | mr->access_mode; 3301 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); 3302 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 3303 seg->start_addr = cpu_to_be64(mr->ibmr.iova); 3304 seg->len = cpu_to_be64(mr->ibmr.length); 3305 seg->xlt_oct_size = cpu_to_be32(ndescs); 3306 } 3307 3308 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) 3309 { 3310 memset(seg, 0, sizeof(*seg)); 3311 seg->status = MLX5_MKEY_STATUS_FREE; 3312 } 3313 3314 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, const struct ib_send_wr *wr) 3315 { 3316 const struct mlx5_umr_wr *umrwr = umr_wr(wr); 3317 3318 memset(seg, 0, sizeof(*seg)); 3319 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) { 3320 seg->status = MLX5_MKEY_STATUS_FREE; 3321 return; 3322 } 3323 3324 seg->flags = convert_access(umrwr->access_flags); 3325 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) { 3326 if (umrwr->pd) 3327 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); 3328 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr); 3329 } 3330 seg->len = cpu_to_be64(umrwr->length); 3331 seg->log2_page_size = umrwr->page_shift; 3332 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 3333 mlx5_mkey_variant(umrwr->mkey)); 3334 } 3335 3336 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, 3337 struct mlx5_ib_mr *mr, 3338 struct mlx5_ib_pd *pd) 3339 { 3340 int bcount = mr->desc_size * mr->ndescs; 3341 3342 dseg->addr = cpu_to_be64(mr->desc_map); 3343 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); 3344 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); 3345 } 3346 3347 static __be32 send_ieth(const struct ib_send_wr *wr) 3348 { 3349 switch (wr->opcode) { 3350 case IB_WR_SEND_WITH_IMM: 3351 case IB_WR_RDMA_WRITE_WITH_IMM: 3352 return wr->ex.imm_data; 3353 3354 case IB_WR_SEND_WITH_INV: 3355 return cpu_to_be32(wr->ex.invalidate_rkey); 3356 3357 default: 3358 return 0; 3359 } 3360 } 3361 3362 static u8 calc_sig(void *wqe, int size) 3363 { 3364 u8 *p = wqe; 3365 u8 res = 0; 3366 int i; 3367 3368 for (i = 0; i < size; i++) 3369 res ^= p[i]; 3370 3371 return ~res; 3372 } 3373 3374 static u8 wq_sig(void *wqe) 3375 { 3376 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 3377 } 3378 3379 static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr, 3380 void *wqe, int *sz) 3381 { 3382 struct mlx5_wqe_inline_seg *seg; 3383 void *qend = qp->sq.qend; 3384 void *addr; 3385 int inl = 0; 3386 int copy; 3387 int len; 3388 int i; 3389 3390 seg = wqe; 3391 wqe += sizeof(*seg); 3392 for (i = 0; i < wr->num_sge; i++) { 3393 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 3394 len = wr->sg_list[i].length; 3395 inl += len; 3396 3397 if (unlikely(inl > qp->max_inline_data)) 3398 return -ENOMEM; 3399 3400 if (unlikely(wqe + len > qend)) { 3401 copy = qend - wqe; 3402 memcpy(wqe, addr, copy); 3403 addr += copy; 3404 len -= copy; 3405 wqe = mlx5_get_send_wqe(qp, 0); 3406 } 3407 memcpy(wqe, addr, len); 3408 wqe += len; 3409 } 3410 3411 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 3412 3413 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 3414 3415 return 0; 3416 } 3417 3418 static u16 prot_field_size(enum ib_signature_type type) 3419 { 3420 switch (type) { 3421 case IB_SIG_TYPE_T10_DIF: 3422 return MLX5_DIF_SIZE; 3423 default: 3424 return 0; 3425 } 3426 } 3427 3428 static u8 bs_selector(int block_size) 3429 { 3430 switch (block_size) { 3431 case 512: return 0x1; 3432 case 520: return 0x2; 3433 case 4096: return 0x3; 3434 case 4160: return 0x4; 3435 case 1073741824: return 0x5; 3436 default: return 0; 3437 } 3438 } 3439 3440 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, 3441 struct mlx5_bsf_inl *inl) 3442 { 3443 /* Valid inline section and allow BSF refresh */ 3444 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | 3445 MLX5_BSF_REFRESH_DIF); 3446 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); 3447 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); 3448 /* repeating block */ 3449 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; 3450 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? 3451 MLX5_DIF_CRC : MLX5_DIF_IPCS; 3452 3453 if (domain->sig.dif.ref_remap) 3454 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; 3455 3456 if (domain->sig.dif.app_escape) { 3457 if (domain->sig.dif.ref_escape) 3458 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; 3459 else 3460 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; 3461 } 3462 3463 inl->dif_app_bitmask_check = 3464 cpu_to_be16(domain->sig.dif.apptag_check_mask); 3465 } 3466 3467 static int mlx5_set_bsf(struct ib_mr *sig_mr, 3468 struct ib_sig_attrs *sig_attrs, 3469 struct mlx5_bsf *bsf, u32 data_size) 3470 { 3471 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 3472 struct mlx5_bsf_basic *basic = &bsf->basic; 3473 struct ib_sig_domain *mem = &sig_attrs->mem; 3474 struct ib_sig_domain *wire = &sig_attrs->wire; 3475 3476 memset(bsf, 0, sizeof(*bsf)); 3477 3478 /* Basic + Extended + Inline */ 3479 basic->bsf_size_sbs = 1 << 7; 3480 /* Input domain check byte mask */ 3481 basic->check_byte_mask = sig_attrs->check_mask; 3482 basic->raw_data_size = cpu_to_be32(data_size); 3483 3484 /* Memory domain */ 3485 switch (sig_attrs->mem.sig_type) { 3486 case IB_SIG_TYPE_NONE: 3487 break; 3488 case IB_SIG_TYPE_T10_DIF: 3489 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 3490 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); 3491 mlx5_fill_inl_bsf(mem, &bsf->m_inl); 3492 break; 3493 default: 3494 return -EINVAL; 3495 } 3496 3497 /* Wire domain */ 3498 switch (sig_attrs->wire.sig_type) { 3499 case IB_SIG_TYPE_NONE: 3500 break; 3501 case IB_SIG_TYPE_T10_DIF: 3502 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 3503 mem->sig_type == wire->sig_type) { 3504 /* Same block structure */ 3505 basic->bsf_size_sbs |= 1 << 4; 3506 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 3507 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 3508 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 3509 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; 3510 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) 3511 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; 3512 } else 3513 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 3514 3515 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); 3516 mlx5_fill_inl_bsf(wire, &bsf->w_inl); 3517 break; 3518 default: 3519 return -EINVAL; 3520 } 3521 3522 return 0; 3523 } 3524 3525 static int set_sig_data_segment(const struct ib_sig_handover_wr *wr, 3526 struct mlx5_ib_qp *qp, void **seg, int *size) 3527 { 3528 struct ib_sig_attrs *sig_attrs = wr->sig_attrs; 3529 struct ib_mr *sig_mr = wr->sig_mr; 3530 struct mlx5_bsf *bsf; 3531 u32 data_len = wr->wr.sg_list->length; 3532 u32 data_key = wr->wr.sg_list->lkey; 3533 u64 data_va = wr->wr.sg_list->addr; 3534 int ret; 3535 int wqe_size; 3536 3537 if (!wr->prot || 3538 (data_key == wr->prot->lkey && 3539 data_va == wr->prot->addr && 3540 data_len == wr->prot->length)) { 3541 /** 3542 * Source domain doesn't contain signature information 3543 * or data and protection are interleaved in memory. 3544 * So need construct: 3545 * ------------------ 3546 * | data_klm | 3547 * ------------------ 3548 * | BSF | 3549 * ------------------ 3550 **/ 3551 struct mlx5_klm *data_klm = *seg; 3552 3553 data_klm->bcount = cpu_to_be32(data_len); 3554 data_klm->key = cpu_to_be32(data_key); 3555 data_klm->va = cpu_to_be64(data_va); 3556 wqe_size = ALIGN(sizeof(*data_klm), 64); 3557 } else { 3558 /** 3559 * Source domain contains signature information 3560 * So need construct a strided block format: 3561 * --------------------------- 3562 * | stride_block_ctrl | 3563 * --------------------------- 3564 * | data_klm | 3565 * --------------------------- 3566 * | prot_klm | 3567 * --------------------------- 3568 * | BSF | 3569 * --------------------------- 3570 **/ 3571 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 3572 struct mlx5_stride_block_entry *data_sentry; 3573 struct mlx5_stride_block_entry *prot_sentry; 3574 u32 prot_key = wr->prot->lkey; 3575 u64 prot_va = wr->prot->addr; 3576 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 3577 int prot_size; 3578 3579 sblock_ctrl = *seg; 3580 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 3581 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 3582 3583 prot_size = prot_field_size(sig_attrs->mem.sig_type); 3584 if (!prot_size) { 3585 pr_err("Bad block size given: %u\n", block_size); 3586 return -EINVAL; 3587 } 3588 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 3589 prot_size); 3590 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 3591 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 3592 sblock_ctrl->num_entries = cpu_to_be16(2); 3593 3594 data_sentry->bcount = cpu_to_be16(block_size); 3595 data_sentry->key = cpu_to_be32(data_key); 3596 data_sentry->va = cpu_to_be64(data_va); 3597 data_sentry->stride = cpu_to_be16(block_size); 3598 3599 prot_sentry->bcount = cpu_to_be16(prot_size); 3600 prot_sentry->key = cpu_to_be32(prot_key); 3601 prot_sentry->va = cpu_to_be64(prot_va); 3602 prot_sentry->stride = cpu_to_be16(prot_size); 3603 3604 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 3605 sizeof(*prot_sentry), 64); 3606 } 3607 3608 *seg += wqe_size; 3609 *size += wqe_size / 16; 3610 if (unlikely((*seg == qp->sq.qend))) 3611 *seg = mlx5_get_send_wqe(qp, 0); 3612 3613 bsf = *seg; 3614 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 3615 if (ret) 3616 return -EINVAL; 3617 3618 *seg += sizeof(*bsf); 3619 *size += sizeof(*bsf) / 16; 3620 if (unlikely((*seg == qp->sq.qend))) 3621 *seg = mlx5_get_send_wqe(qp, 0); 3622 3623 return 0; 3624 } 3625 3626 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 3627 const struct ib_sig_handover_wr *wr, u32 nelements, 3628 u32 length, u32 pdn) 3629 { 3630 struct ib_mr *sig_mr = wr->sig_mr; 3631 u32 sig_key = sig_mr->rkey; 3632 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 3633 3634 memset(seg, 0, sizeof(*seg)); 3635 3636 seg->flags = get_umr_flags(wr->access_flags) | 3637 MLX5_ACCESS_MODE_KLM; 3638 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 3639 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 3640 MLX5_MKEY_BSF_EN | pdn); 3641 seg->len = cpu_to_be64(length); 3642 seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements))); 3643 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 3644 } 3645 3646 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 3647 u32 nelements) 3648 { 3649 memset(umr, 0, sizeof(*umr)); 3650 3651 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 3652 umr->klm_octowords = get_klm_octo(nelements); 3653 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 3654 umr->mkey_mask = sig_mkey_mask(); 3655 } 3656 3657 3658 static int set_sig_umr_wr(const struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp, 3659 void **seg, int *size) 3660 { 3661 const struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr); 3662 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr); 3663 u32 pdn = get_pd(qp)->pdn; 3664 u32 klm_oct_size; 3665 int region_len, ret; 3666 3667 if (unlikely(wr->wr.num_sge != 1) || 3668 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) || 3669 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || 3670 unlikely(!sig_mr->sig->sig_status_checked)) 3671 return -EINVAL; 3672 3673 /* length of the protected region, data + protection */ 3674 region_len = wr->wr.sg_list->length; 3675 if (wr->prot && 3676 (wr->prot->lkey != wr->wr.sg_list->lkey || 3677 wr->prot->addr != wr->wr.sg_list->addr || 3678 wr->prot->length != wr->wr.sg_list->length)) 3679 region_len += wr->prot->length; 3680 3681 /** 3682 * KLM octoword size - if protection was provided 3683 * then we use strided block format (3 octowords), 3684 * else we use single KLM (1 octoword) 3685 **/ 3686 klm_oct_size = wr->prot ? 3 : 1; 3687 3688 set_sig_umr_segment(*seg, klm_oct_size); 3689 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3690 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3691 if (unlikely((*seg == qp->sq.qend))) 3692 *seg = mlx5_get_send_wqe(qp, 0); 3693 3694 set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn); 3695 *seg += sizeof(struct mlx5_mkey_seg); 3696 *size += sizeof(struct mlx5_mkey_seg) / 16; 3697 if (unlikely((*seg == qp->sq.qend))) 3698 *seg = mlx5_get_send_wqe(qp, 0); 3699 3700 ret = set_sig_data_segment(wr, qp, seg, size); 3701 if (ret) 3702 return ret; 3703 3704 sig_mr->sig->sig_status_checked = false; 3705 return 0; 3706 } 3707 3708 static int set_psv_wr(struct ib_sig_domain *domain, 3709 u32 psv_idx, void **seg, int *size) 3710 { 3711 struct mlx5_seg_set_psv *psv_seg = *seg; 3712 3713 memset(psv_seg, 0, sizeof(*psv_seg)); 3714 psv_seg->psv_num = cpu_to_be32(psv_idx); 3715 switch (domain->sig_type) { 3716 case IB_SIG_TYPE_NONE: 3717 break; 3718 case IB_SIG_TYPE_T10_DIF: 3719 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 3720 domain->sig.dif.app_tag); 3721 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 3722 break; 3723 default: 3724 pr_err("Bad signature type given.\n"); 3725 return 1; 3726 } 3727 3728 *seg += sizeof(*psv_seg); 3729 *size += sizeof(*psv_seg) / 16; 3730 3731 return 0; 3732 } 3733 3734 static int set_reg_wr(struct mlx5_ib_qp *qp, 3735 const struct ib_reg_wr *wr, 3736 void **seg, int *size) 3737 { 3738 struct mlx5_ib_mr *mr = to_mmr(wr->mr); 3739 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); 3740 3741 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { 3742 mlx5_ib_warn(to_mdev(qp->ibqp.device), 3743 "Invalid IB_SEND_INLINE send flag\n"); 3744 return -EINVAL; 3745 } 3746 3747 set_reg_umr_seg(*seg, mr); 3748 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3749 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3750 if (unlikely((*seg == qp->sq.qend))) 3751 *seg = mlx5_get_send_wqe(qp, 0); 3752 3753 set_reg_mkey_seg(*seg, mr, wr->key, wr->access); 3754 *seg += sizeof(struct mlx5_mkey_seg); 3755 *size += sizeof(struct mlx5_mkey_seg) / 16; 3756 if (unlikely((*seg == qp->sq.qend))) 3757 *seg = mlx5_get_send_wqe(qp, 0); 3758 3759 set_reg_data_seg(*seg, mr, pd); 3760 *seg += sizeof(struct mlx5_wqe_data_seg); 3761 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 3762 3763 return 0; 3764 } 3765 3766 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size) 3767 { 3768 set_linv_umr_seg(*seg); 3769 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3770 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3771 if (unlikely((*seg == qp->sq.qend))) 3772 *seg = mlx5_get_send_wqe(qp, 0); 3773 set_linv_mkey_seg(*seg); 3774 *seg += sizeof(struct mlx5_mkey_seg); 3775 *size += sizeof(struct mlx5_mkey_seg) / 16; 3776 if (unlikely((*seg == qp->sq.qend))) 3777 *seg = mlx5_get_send_wqe(qp, 0); 3778 } 3779 3780 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16) 3781 { 3782 __be32 *p = NULL; 3783 int tidx = idx; 3784 int i, j; 3785 3786 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx)); 3787 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 3788 if ((i & 0xf) == 0) { 3789 void *buf = mlx5_get_send_wqe(qp, tidx); 3790 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1); 3791 p = buf; 3792 j = 0; 3793 } 3794 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 3795 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 3796 be32_to_cpu(p[j + 3])); 3797 } 3798 } 3799 3800 static u8 get_fence(u8 fence, const struct ib_send_wr *wr) 3801 { 3802 if (unlikely(wr->opcode == IB_WR_LOCAL_INV && 3803 wr->send_flags & IB_SEND_FENCE)) 3804 return MLX5_FENCE_MODE_STRONG_ORDERING; 3805 3806 if (unlikely(fence)) { 3807 if (wr->send_flags & IB_SEND_FENCE) 3808 return MLX5_FENCE_MODE_SMALL_AND_FENCE; 3809 else 3810 return fence; 3811 } else if (unlikely(wr->send_flags & IB_SEND_FENCE)) { 3812 return MLX5_FENCE_MODE_FENCE; 3813 } 3814 3815 return 0; 3816 } 3817 3818 static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg, 3819 struct mlx5_wqe_ctrl_seg **ctrl, 3820 const struct ib_send_wr *wr, unsigned *idx, 3821 int *size, int nreq, bool send_signaled, bool solicited) 3822 { 3823 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) 3824 return -ENOMEM; 3825 3826 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 3827 *seg = mlx5_get_send_wqe(qp, *idx); 3828 *ctrl = *seg; 3829 *(uint32_t *)(*seg + 8) = 0; 3830 (*ctrl)->imm = send_ieth(wr); 3831 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 3832 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) | 3833 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0); 3834 3835 *seg += sizeof(**ctrl); 3836 *size = sizeof(**ctrl) / 16; 3837 3838 return 0; 3839 } 3840 3841 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 3842 struct mlx5_wqe_ctrl_seg **ctrl, 3843 const struct ib_send_wr *wr, unsigned *idx, 3844 int *size, int nreq) 3845 { 3846 return __begin_wqe(qp, seg, ctrl, wr, idx, size, nreq, 3847 wr->send_flags & IB_SEND_SIGNALED, 3848 wr->send_flags & IB_SEND_SOLICITED); 3849 } 3850 3851 static void finish_wqe(struct mlx5_ib_qp *qp, 3852 struct mlx5_wqe_ctrl_seg *ctrl, 3853 u8 size, unsigned idx, u64 wr_id, 3854 int nreq, u8 fence, u8 next_fence, 3855 u32 mlx5_opcode) 3856 { 3857 u8 opmod = 0; 3858 3859 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 3860 mlx5_opcode | ((u32)opmod << 24)); 3861 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); 3862 ctrl->fm_ce_se |= fence; 3863 qp->fm_cache = next_fence; 3864 if (unlikely(qp->wq_sig)) 3865 ctrl->signature = wq_sig(ctrl); 3866 3867 qp->sq.wrid[idx] = wr_id; 3868 qp->sq.w_list[idx].opcode = mlx5_opcode; 3869 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 3870 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 3871 qp->sq.w_list[idx].next = qp->sq.cur_post; 3872 } 3873 3874 3875 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 3876 const struct ib_send_wr **bad_wr) 3877 { 3878 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 3879 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3880 struct mlx5_core_dev *mdev = dev->mdev; 3881 struct mlx5_ib_qp *qp; 3882 struct mlx5_ib_mr *mr; 3883 struct mlx5_wqe_data_seg *dpseg; 3884 struct mlx5_wqe_xrc_seg *xrc; 3885 struct mlx5_bf *bf; 3886 int uninitialized_var(size); 3887 void *qend; 3888 unsigned long flags; 3889 unsigned idx; 3890 int err = 0; 3891 int inl = 0; 3892 int num_sge; 3893 void *seg; 3894 int nreq; 3895 int i; 3896 u8 next_fence = 0; 3897 u8 fence; 3898 3899 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 3900 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr); 3901 3902 qp = to_mqp(ibqp); 3903 bf = &qp->bf; 3904 qend = qp->sq.qend; 3905 3906 spin_lock_irqsave(&qp->sq.lock, flags); 3907 3908 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 3909 err = -EIO; 3910 *bad_wr = wr; 3911 nreq = 0; 3912 goto out; 3913 } 3914 3915 for (nreq = 0; wr; nreq++, wr = wr->next) { 3916 if (unlikely(wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { 3917 mlx5_ib_warn(dev, "\n"); 3918 err = -EINVAL; 3919 *bad_wr = wr; 3920 goto out; 3921 } 3922 3923 fence = qp->fm_cache; 3924 num_sge = wr->num_sge; 3925 if (unlikely(num_sge > qp->sq.max_gs)) { 3926 mlx5_ib_warn(dev, "\n"); 3927 err = -EINVAL; 3928 *bad_wr = wr; 3929 goto out; 3930 } 3931 3932 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq); 3933 if (err) { 3934 mlx5_ib_warn(dev, "\n"); 3935 err = -ENOMEM; 3936 *bad_wr = wr; 3937 goto out; 3938 } 3939 3940 switch (ibqp->qp_type) { 3941 case IB_QPT_XRC_INI: 3942 xrc = seg; 3943 seg += sizeof(*xrc); 3944 size += sizeof(*xrc) / 16; 3945 /* fall through */ 3946 case IB_QPT_RC: 3947 switch (wr->opcode) { 3948 case IB_WR_RDMA_READ: 3949 case IB_WR_RDMA_WRITE: 3950 case IB_WR_RDMA_WRITE_WITH_IMM: 3951 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 3952 rdma_wr(wr)->rkey); 3953 seg += sizeof(struct mlx5_wqe_raddr_seg); 3954 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 3955 break; 3956 3957 case IB_WR_ATOMIC_CMP_AND_SWP: 3958 case IB_WR_ATOMIC_FETCH_AND_ADD: 3959 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 3960 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 3961 err = -ENOSYS; 3962 *bad_wr = wr; 3963 goto out; 3964 3965 case IB_WR_LOCAL_INV: 3966 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 3967 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 3968 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 3969 set_linv_wr(qp, &seg, &size); 3970 num_sge = 0; 3971 break; 3972 3973 case IB_WR_REG_MR: 3974 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 3975 qp->sq.wr_data[idx] = IB_WR_REG_MR; 3976 ctrl->imm = cpu_to_be32(reg_wr(wr)->key); 3977 err = set_reg_wr(qp, reg_wr(wr), &seg, &size); 3978 if (err) { 3979 *bad_wr = wr; 3980 goto out; 3981 } 3982 num_sge = 0; 3983 break; 3984 3985 case IB_WR_REG_SIG_MR: 3986 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; 3987 mr = to_mmr(sig_handover_wr(wr)->sig_mr); 3988 3989 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 3990 err = set_sig_umr_wr(wr, qp, &seg, &size); 3991 if (err) { 3992 mlx5_ib_warn(dev, "\n"); 3993 *bad_wr = wr; 3994 goto out; 3995 } 3996 3997 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 3998 nreq, get_fence(fence, wr), 3999 next_fence, MLX5_OPCODE_UMR); 4000 /* 4001 * SET_PSV WQEs are not signaled and solicited 4002 * on error 4003 */ 4004 err = __begin_wqe(qp, &seg, &ctrl, wr, 4005 &idx, &size, nreq, false, true); 4006 if (err) { 4007 mlx5_ib_warn(dev, "\n"); 4008 err = -ENOMEM; 4009 *bad_wr = wr; 4010 goto out; 4011 } 4012 4013 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem, 4014 mr->sig->psv_memory.psv_idx, &seg, 4015 &size); 4016 if (err) { 4017 mlx5_ib_warn(dev, "\n"); 4018 *bad_wr = wr; 4019 goto out; 4020 } 4021 4022 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 4023 nreq, get_fence(fence, wr), 4024 next_fence, MLX5_OPCODE_SET_PSV); 4025 err = __begin_wqe(qp, &seg, &ctrl, wr, 4026 &idx, &size, nreq, false, true); 4027 if (err) { 4028 mlx5_ib_warn(dev, "\n"); 4029 err = -ENOMEM; 4030 *bad_wr = wr; 4031 goto out; 4032 } 4033 4034 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4035 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire, 4036 mr->sig->psv_wire.psv_idx, &seg, 4037 &size); 4038 if (err) { 4039 mlx5_ib_warn(dev, "\n"); 4040 *bad_wr = wr; 4041 goto out; 4042 } 4043 4044 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 4045 nreq, get_fence(fence, wr), 4046 next_fence, MLX5_OPCODE_SET_PSV); 4047 num_sge = 0; 4048 goto skip_psv; 4049 4050 default: 4051 break; 4052 } 4053 break; 4054 4055 case IB_QPT_UC: 4056 switch (wr->opcode) { 4057 case IB_WR_RDMA_WRITE: 4058 case IB_WR_RDMA_WRITE_WITH_IMM: 4059 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 4060 rdma_wr(wr)->rkey); 4061 seg += sizeof(struct mlx5_wqe_raddr_seg); 4062 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 4063 break; 4064 4065 default: 4066 break; 4067 } 4068 break; 4069 4070 case IB_QPT_SMI: 4071 case MLX5_IB_QPT_HW_GSI: 4072 set_datagram_seg(seg, wr); 4073 seg += sizeof(struct mlx5_wqe_datagram_seg); 4074 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4075 if (unlikely((seg == qend))) 4076 seg = mlx5_get_send_wqe(qp, 0); 4077 break; 4078 case IB_QPT_UD: 4079 set_datagram_seg(seg, wr); 4080 seg += sizeof(struct mlx5_wqe_datagram_seg); 4081 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4082 4083 if (unlikely((seg == qend))) 4084 seg = mlx5_get_send_wqe(qp, 0); 4085 4086 /* handle qp that supports ud offload */ 4087 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) { 4088 struct mlx5_wqe_eth_pad *pad; 4089 4090 pad = seg; 4091 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad)); 4092 seg += sizeof(struct mlx5_wqe_eth_pad); 4093 size += sizeof(struct mlx5_wqe_eth_pad) / 16; 4094 4095 seg = set_eth_seg(seg, wr, qend, qp, &size); 4096 4097 if (unlikely((seg == qend))) 4098 seg = mlx5_get_send_wqe(qp, 0); 4099 } 4100 break; 4101 case MLX5_IB_QPT_REG_UMR: 4102 if (wr->opcode != MLX5_IB_WR_UMR) { 4103 err = -EINVAL; 4104 mlx5_ib_warn(dev, "bad opcode\n"); 4105 goto out; 4106 } 4107 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 4108 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); 4109 set_reg_umr_segment(seg, wr); 4110 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4111 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4112 if (unlikely((seg == qend))) 4113 seg = mlx5_get_send_wqe(qp, 0); 4114 set_reg_mkey_segment(seg, wr); 4115 seg += sizeof(struct mlx5_mkey_seg); 4116 size += sizeof(struct mlx5_mkey_seg) / 16; 4117 if (unlikely((seg == qend))) 4118 seg = mlx5_get_send_wqe(qp, 0); 4119 break; 4120 4121 default: 4122 break; 4123 } 4124 4125 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 4126 int uninitialized_var(sz); 4127 4128 err = set_data_inl_seg(qp, wr, seg, &sz); 4129 if (unlikely(err)) { 4130 mlx5_ib_warn(dev, "\n"); 4131 *bad_wr = wr; 4132 goto out; 4133 } 4134 inl = 1; 4135 size += sz; 4136 } else { 4137 dpseg = seg; 4138 for (i = 0; i < num_sge; i++) { 4139 if (unlikely(dpseg == qend)) { 4140 seg = mlx5_get_send_wqe(qp, 0); 4141 dpseg = seg; 4142 } 4143 if (likely(wr->sg_list[i].length)) { 4144 set_data_ptr_seg(dpseg, wr->sg_list + i); 4145 size += sizeof(struct mlx5_wqe_data_seg) / 16; 4146 dpseg++; 4147 } 4148 } 4149 } 4150 4151 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 4152 get_fence(fence, wr), next_fence, 4153 mlx5_ib_opcode[wr->opcode]); 4154 skip_psv: 4155 if (0) 4156 dump_wqe(qp, idx, size); 4157 } 4158 4159 out: 4160 if (likely(nreq)) { 4161 qp->sq.head += nreq; 4162 4163 /* Make sure that descriptors are written before 4164 * updating doorbell record and ringing the doorbell 4165 */ 4166 wmb(); 4167 4168 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 4169 4170 /* Make sure doorbell record is visible to the HCA before 4171 * we hit doorbell */ 4172 wmb(); 4173 4174 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, 4175 MLX5_GET_DOORBELL_LOCK(&bf->lock32)); 4176 /* Make sure doorbells don't leak out of SQ spinlock 4177 * and reach the HCA out of order. 4178 */ 4179 bf->offset ^= bf->buf_size; 4180 } 4181 4182 spin_unlock_irqrestore(&qp->sq.lock, flags); 4183 4184 return err; 4185 } 4186 4187 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 4188 { 4189 sig->signature = calc_sig(sig, size); 4190 } 4191 4192 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 4193 const struct ib_recv_wr **bad_wr) 4194 { 4195 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4196 struct mlx5_wqe_data_seg *scat; 4197 struct mlx5_rwqe_sig *sig; 4198 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4199 struct mlx5_core_dev *mdev = dev->mdev; 4200 unsigned long flags; 4201 int err = 0; 4202 int nreq; 4203 int ind; 4204 int i; 4205 4206 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4207 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr); 4208 4209 spin_lock_irqsave(&qp->rq.lock, flags); 4210 4211 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 4212 err = -EIO; 4213 *bad_wr = wr; 4214 nreq = 0; 4215 goto out; 4216 } 4217 4218 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 4219 4220 for (nreq = 0; wr; nreq++, wr = wr->next) { 4221 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 4222 err = -ENOMEM; 4223 *bad_wr = wr; 4224 goto out; 4225 } 4226 4227 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 4228 err = -EINVAL; 4229 *bad_wr = wr; 4230 goto out; 4231 } 4232 4233 scat = get_recv_wqe(qp, ind); 4234 if (qp->wq_sig) 4235 scat++; 4236 4237 for (i = 0; i < wr->num_sge; i++) 4238 set_data_ptr_seg(scat + i, wr->sg_list + i); 4239 4240 if (i < qp->rq.max_gs) { 4241 scat[i].byte_count = 0; 4242 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 4243 scat[i].addr = 0; 4244 } 4245 4246 if (qp->wq_sig) { 4247 sig = (struct mlx5_rwqe_sig *)scat; 4248 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 4249 } 4250 4251 qp->rq.wrid[ind] = wr->wr_id; 4252 4253 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 4254 } 4255 4256 out: 4257 if (likely(nreq)) { 4258 qp->rq.head += nreq; 4259 4260 /* Make sure that descriptors are written before 4261 * doorbell record. 4262 */ 4263 wmb(); 4264 4265 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 4266 } 4267 4268 spin_unlock_irqrestore(&qp->rq.lock, flags); 4269 4270 return err; 4271 } 4272 4273 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4274 { 4275 switch (mlx5_state) { 4276 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4277 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4278 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4279 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4280 case MLX5_QP_STATE_SQ_DRAINING: 4281 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4282 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4283 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4284 default: return -1; 4285 } 4286 } 4287 4288 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4289 { 4290 switch (mlx5_mig_state) { 4291 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4292 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4293 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4294 default: return -1; 4295 } 4296 } 4297 4298 static int to_ib_qp_access_flags(int mlx5_flags) 4299 { 4300 int ib_flags = 0; 4301 4302 if (mlx5_flags & MLX5_QP_BIT_RRE) 4303 ib_flags |= IB_ACCESS_REMOTE_READ; 4304 if (mlx5_flags & MLX5_QP_BIT_RWE) 4305 ib_flags |= IB_ACCESS_REMOTE_WRITE; 4306 if (mlx5_flags & MLX5_QP_BIT_RAE) 4307 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 4308 4309 return ib_flags; 4310 } 4311 4312 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr, 4313 struct mlx5_qp_path *path) 4314 { 4315 struct mlx5_core_dev *dev = ibdev->mdev; 4316 4317 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr)); 4318 ib_ah_attr->port_num = path->port; 4319 4320 if (ib_ah_attr->port_num == 0 || 4321 ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports)) 4322 return; 4323 4324 ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf; 4325 4326 ib_ah_attr->dlid = be16_to_cpu(path->rlid); 4327 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f; 4328 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0; 4329 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0; 4330 if (ib_ah_attr->ah_flags) { 4331 ib_ah_attr->grh.sgid_index = path->mgid_index; 4332 ib_ah_attr->grh.hop_limit = path->hop_limit; 4333 ib_ah_attr->grh.traffic_class = 4334 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff; 4335 ib_ah_attr->grh.flow_label = 4336 be32_to_cpu(path->tclass_flowlabel) & 0xfffff; 4337 memcpy(ib_ah_attr->grh.dgid.raw, 4338 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw)); 4339 } 4340 } 4341 4342 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4343 struct mlx5_ib_sq *sq, 4344 u8 *sq_state) 4345 { 4346 void *out; 4347 void *sqc; 4348 int inlen; 4349 int err; 4350 4351 inlen = MLX5_ST_SZ_BYTES(query_sq_out); 4352 out = mlx5_vzalloc(inlen); 4353 if (!out) 4354 return -ENOMEM; 4355 4356 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out); 4357 if (err) 4358 goto out; 4359 4360 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context); 4361 *sq_state = MLX5_GET(sqc, sqc, state); 4362 sq->state = *sq_state; 4363 4364 out: 4365 kvfree(out); 4366 return err; 4367 } 4368 4369 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4370 struct mlx5_ib_rq *rq, 4371 u8 *rq_state) 4372 { 4373 void *out; 4374 void *rqc; 4375 int inlen; 4376 int err; 4377 4378 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4379 out = mlx5_vzalloc(inlen); 4380 if (!out) 4381 return -ENOMEM; 4382 4383 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4384 if (err) 4385 goto out; 4386 4387 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4388 *rq_state = MLX5_GET(rqc, rqc, state); 4389 rq->state = *rq_state; 4390 4391 out: 4392 kvfree(out); 4393 return err; 4394 } 4395 4396 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4397 struct mlx5_ib_qp *qp, u8 *qp_state) 4398 { 4399 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4400 [MLX5_RQC_STATE_RST] = { 4401 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4402 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4403 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4404 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4405 }, 4406 [MLX5_RQC_STATE_RDY] = { 4407 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4408 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4409 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4410 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4411 }, 4412 [MLX5_RQC_STATE_ERR] = { 4413 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4414 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4415 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4416 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4417 }, 4418 [MLX5_RQ_STATE_NA] = { 4419 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4420 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4421 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4422 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4423 }, 4424 }; 4425 4426 *qp_state = sqrq_trans[rq_state][sq_state]; 4427 4428 if (*qp_state == MLX5_QP_STATE_BAD) { 4429 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4430 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4431 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4432 return -EINVAL; 4433 } 4434 4435 if (*qp_state == MLX5_QP_STATE) 4436 *qp_state = qp->state; 4437 4438 return 0; 4439 } 4440 4441 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4442 struct mlx5_ib_qp *qp, 4443 u8 *raw_packet_qp_state) 4444 { 4445 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4446 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4447 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4448 int err; 4449 u8 sq_state = MLX5_SQ_STATE_NA; 4450 u8 rq_state = MLX5_RQ_STATE_NA; 4451 4452 if (qp->sq.wqe_cnt) { 4453 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4454 if (err) 4455 return err; 4456 } 4457 4458 if (qp->rq.wqe_cnt) { 4459 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4460 if (err) 4461 return err; 4462 } 4463 4464 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4465 raw_packet_qp_state); 4466 } 4467 4468 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4469 struct ib_qp_attr *qp_attr) 4470 { 4471 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 4472 struct mlx5_qp_context *context; 4473 int mlx5_state; 4474 u32 *outb; 4475 int err = 0; 4476 4477 outb = kzalloc(outlen, GFP_KERNEL); 4478 if (!outb) 4479 return -ENOMEM; 4480 4481 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, 4482 outlen); 4483 if (err) 4484 goto out; 4485 4486 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */ 4487 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc); 4488 4489 mlx5_state = be32_to_cpu(context->flags) >> 28; 4490 4491 qp->state = to_ib_qp_state(mlx5_state); 4492 qp_attr->path_mtu = context->mtu_msgmax >> 5; 4493 qp_attr->path_mig_state = 4494 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 4495 qp_attr->qkey = be32_to_cpu(context->qkey); 4496 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 4497 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 4498 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 4499 qp_attr->qp_access_flags = 4500 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 4501 4502 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 4503 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 4504 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 4505 qp_attr->alt_pkey_index = 4506 be16_to_cpu(context->alt_path.pkey_index); 4507 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num; 4508 } 4509 4510 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index); 4511 qp_attr->port_num = context->pri_path.port; 4512 4513 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 4514 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 4515 4516 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 4517 4518 qp_attr->max_dest_rd_atomic = 4519 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 4520 qp_attr->min_rnr_timer = 4521 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 4522 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 4523 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 4524 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 4525 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 4526 4527 out: 4528 kfree(outb); 4529 return err; 4530 } 4531 4532 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 4533 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 4534 { 4535 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4536 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4537 int err = 0; 4538 u8 raw_packet_qp_state; 4539 4540 if (ibqp->rwq_ind_tbl) 4541 return -ENOSYS; 4542 4543 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4544 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 4545 qp_init_attr); 4546 4547 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 4548 /* 4549 * Wait for any outstanding page faults, in case the user frees memory 4550 * based upon this query's result. 4551 */ 4552 flush_workqueue(mlx5_ib_page_fault_wq); 4553 #endif 4554 4555 mutex_lock(&qp->mutex); 4556 4557 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 4558 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 4559 if (err) 4560 goto out; 4561 qp->state = raw_packet_qp_state; 4562 qp_attr->port_num = 1; 4563 } else { 4564 err = query_qp_attr(dev, qp, qp_attr); 4565 if (err) 4566 goto out; 4567 } 4568 4569 qp_attr->qp_state = qp->state; 4570 qp_attr->cur_qp_state = qp_attr->qp_state; 4571 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 4572 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 4573 4574 if (!ibqp->uobject) { 4575 qp_attr->cap.max_send_wr = qp->sq.max_post; 4576 qp_attr->cap.max_send_sge = qp->sq.max_gs; 4577 qp_init_attr->qp_context = ibqp->qp_context; 4578 } else { 4579 qp_attr->cap.max_send_wr = 0; 4580 qp_attr->cap.max_send_sge = 0; 4581 } 4582 4583 qp_init_attr->qp_type = ibqp->qp_type; 4584 qp_init_attr->recv_cq = ibqp->recv_cq; 4585 qp_init_attr->send_cq = ibqp->send_cq; 4586 qp_init_attr->srq = ibqp->srq; 4587 qp_attr->cap.max_inline_data = qp->max_inline_data; 4588 4589 qp_init_attr->cap = qp_attr->cap; 4590 4591 qp_init_attr->create_flags = 0; 4592 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 4593 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 4594 4595 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 4596 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; 4597 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 4598 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; 4599 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 4600 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; 4601 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 4602 qp_init_attr->create_flags |= MLX5_IB_QP_CREATE_SQPN_QP1; 4603 4604 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 4605 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 4606 4607 out: 4608 mutex_unlock(&qp->mutex); 4609 return err; 4610 } 4611 4612 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 4613 struct ib_ucontext *context, 4614 struct ib_udata *udata) 4615 { 4616 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4617 struct mlx5_ib_xrcd *xrcd; 4618 int err; 4619 4620 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 4621 return ERR_PTR(-ENOSYS); 4622 4623 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 4624 if (!xrcd) 4625 return ERR_PTR(-ENOMEM); 4626 4627 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn); 4628 if (err) { 4629 kfree(xrcd); 4630 return ERR_PTR(-ENOMEM); 4631 } 4632 4633 return &xrcd->ibxrcd; 4634 } 4635 4636 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd) 4637 { 4638 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 4639 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 4640 int err; 4641 4642 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn); 4643 if (err) { 4644 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 4645 return err; 4646 } 4647 4648 kfree(xrcd); 4649 4650 return 0; 4651 } 4652 4653 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 4654 { 4655 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 4656 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 4657 struct ib_event event; 4658 4659 if (rwq->ibwq.event_handler) { 4660 event.device = rwq->ibwq.device; 4661 event.element.wq = &rwq->ibwq; 4662 switch (type) { 4663 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 4664 event.event = IB_EVENT_WQ_FATAL; 4665 break; 4666 default: 4667 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 4668 return; 4669 } 4670 4671 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 4672 } 4673 } 4674 4675 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 4676 struct ib_wq_init_attr *init_attr) 4677 { 4678 struct mlx5_ib_dev *dev; 4679 __be64 *rq_pas0; 4680 void *in; 4681 void *rqc; 4682 void *wq; 4683 int inlen; 4684 int err; 4685 4686 dev = to_mdev(pd->device); 4687 4688 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 4689 in = mlx5_vzalloc(inlen); 4690 if (!in) 4691 return -ENOMEM; 4692 4693 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 4694 MLX5_SET(rqc, rqc, mem_rq_type, 4695 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE); 4696 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 4697 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 4698 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 4699 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 4700 wq = MLX5_ADDR_OF(rqc, rqc, wq); 4701 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 4702 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 4703 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 4704 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 4705 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 4706 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 4707 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 4708 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 4709 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 4710 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 4711 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); 4712 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp); 4713 kvfree(in); 4714 return err; 4715 } 4716 4717 static int set_user_rq_size(struct mlx5_ib_dev *dev, 4718 struct ib_wq_init_attr *wq_init_attr, 4719 struct mlx5_ib_create_wq *ucmd, 4720 struct mlx5_ib_rwq *rwq) 4721 { 4722 /* Sanity check RQ size before proceeding */ 4723 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 4724 return -EINVAL; 4725 4726 if (!ucmd->rq_wqe_count) 4727 return -EINVAL; 4728 4729 rwq->wqe_count = ucmd->rq_wqe_count; 4730 rwq->wqe_shift = ucmd->rq_wqe_shift; 4731 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift); 4732 rwq->log_rq_stride = rwq->wqe_shift; 4733 rwq->log_rq_size = ilog2(rwq->wqe_count); 4734 return 0; 4735 } 4736 4737 static int prepare_user_rq(struct ib_pd *pd, 4738 struct ib_wq_init_attr *init_attr, 4739 struct ib_udata *udata, 4740 struct mlx5_ib_rwq *rwq) 4741 { 4742 struct mlx5_ib_dev *dev = to_mdev(pd->device); 4743 struct mlx5_ib_create_wq ucmd = {}; 4744 int err; 4745 size_t required_cmd_sz; 4746 4747 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 4748 if (udata->inlen < required_cmd_sz) { 4749 mlx5_ib_dbg(dev, "invalid inlen\n"); 4750 return -EINVAL; 4751 } 4752 4753 if (udata->inlen > sizeof(ucmd) && 4754 !ib_is_udata_cleared(udata, sizeof(ucmd), 4755 udata->inlen - sizeof(ucmd))) { 4756 mlx5_ib_dbg(dev, "inlen is not supported\n"); 4757 return -EOPNOTSUPP; 4758 } 4759 4760 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 4761 mlx5_ib_dbg(dev, "copy failed\n"); 4762 return -EFAULT; 4763 } 4764 4765 if (ucmd.comp_mask) { 4766 mlx5_ib_dbg(dev, "invalid comp mask\n"); 4767 return -EOPNOTSUPP; 4768 } 4769 4770 if (ucmd.reserved) { 4771 mlx5_ib_dbg(dev, "invalid reserved\n"); 4772 return -EOPNOTSUPP; 4773 } 4774 4775 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 4776 if (err) { 4777 mlx5_ib_dbg(dev, "err %d\n", err); 4778 return err; 4779 } 4780 4781 err = create_user_rq(dev, pd, rwq, &ucmd); 4782 if (err) { 4783 mlx5_ib_dbg(dev, "err %d\n", err); 4784 if (err) 4785 return err; 4786 } 4787 4788 rwq->user_index = ucmd.user_index; 4789 return 0; 4790 } 4791 4792 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 4793 struct ib_wq_init_attr *init_attr, 4794 struct ib_udata *udata) 4795 { 4796 struct mlx5_ib_dev *dev; 4797 struct mlx5_ib_rwq *rwq; 4798 struct mlx5_ib_create_wq_resp resp = {}; 4799 size_t min_resp_len; 4800 int err; 4801 4802 if (!udata) 4803 return ERR_PTR(-ENOSYS); 4804 4805 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4806 if (udata->outlen && udata->outlen < min_resp_len) 4807 return ERR_PTR(-EINVAL); 4808 4809 dev = to_mdev(pd->device); 4810 switch (init_attr->wq_type) { 4811 case IB_WQT_RQ: 4812 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 4813 if (!rwq) 4814 return ERR_PTR(-ENOMEM); 4815 err = prepare_user_rq(pd, init_attr, udata, rwq); 4816 if (err) 4817 goto err; 4818 err = create_rq(rwq, pd, init_attr); 4819 if (err) 4820 goto err_user_rq; 4821 break; 4822 default: 4823 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 4824 init_attr->wq_type); 4825 return ERR_PTR(-EINVAL); 4826 } 4827 4828 rwq->ibwq.wq_num = rwq->core_qp.qpn; 4829 rwq->ibwq.state = IB_WQS_RESET; 4830 if (udata->outlen) { 4831 resp.response_length = offsetof(typeof(resp), response_length) + 4832 sizeof(resp.response_length); 4833 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4834 if (err) 4835 goto err_copy; 4836 } 4837 4838 rwq->core_qp.event = mlx5_ib_wq_event; 4839 rwq->ibwq.event_handler = init_attr->event_handler; 4840 return &rwq->ibwq; 4841 4842 err_copy: 4843 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 4844 err_user_rq: 4845 destroy_user_rq(pd, rwq); 4846 err: 4847 kfree(rwq); 4848 return ERR_PTR(err); 4849 } 4850 4851 int mlx5_ib_destroy_wq(struct ib_wq *wq) 4852 { 4853 struct mlx5_ib_dev *dev = to_mdev(wq->device); 4854 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 4855 4856 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 4857 destroy_user_rq(wq->pd, rwq); 4858 kfree(rwq); 4859 4860 return 0; 4861 } 4862 4863 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 4864 struct ib_rwq_ind_table_init_attr *init_attr, 4865 struct ib_udata *udata) 4866 { 4867 struct mlx5_ib_dev *dev = to_mdev(device); 4868 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl; 4869 int sz = 1 << init_attr->log_ind_tbl_size; 4870 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 4871 size_t min_resp_len; 4872 int inlen; 4873 int err; 4874 int i; 4875 u32 *in; 4876 void *rqtc; 4877 4878 if (udata->inlen > 0 && 4879 !ib_is_udata_cleared(udata, 0, 4880 udata->inlen)) 4881 return ERR_PTR(-EOPNOTSUPP); 4882 4883 if (init_attr->log_ind_tbl_size > 4884 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 4885 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 4886 init_attr->log_ind_tbl_size, 4887 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 4888 return ERR_PTR(-EINVAL); 4889 } 4890 4891 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4892 if (udata->outlen && udata->outlen < min_resp_len) 4893 return ERR_PTR(-EINVAL); 4894 4895 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL); 4896 if (!rwq_ind_tbl) 4897 return ERR_PTR(-ENOMEM); 4898 4899 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 4900 in = mlx5_vzalloc(inlen); 4901 if (!in) { 4902 err = -ENOMEM; 4903 goto err; 4904 } 4905 4906 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 4907 4908 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 4909 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 4910 4911 for (i = 0; i < sz; i++) 4912 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 4913 4914 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 4915 kvfree(in); 4916 4917 if (err) 4918 goto err; 4919 4920 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 4921 if (udata->outlen) { 4922 resp.response_length = offsetof(typeof(resp), response_length) + 4923 sizeof(resp.response_length); 4924 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4925 if (err) 4926 goto err_copy; 4927 } 4928 4929 return &rwq_ind_tbl->ib_rwq_ind_tbl; 4930 4931 err_copy: 4932 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn); 4933 err: 4934 kfree(rwq_ind_tbl); 4935 return ERR_PTR(err); 4936 } 4937 4938 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 4939 { 4940 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 4941 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 4942 4943 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn); 4944 4945 kfree(rwq_ind_tbl); 4946 return 0; 4947 } 4948 4949 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 4950 u32 wq_attr_mask, struct ib_udata *udata) 4951 { 4952 struct mlx5_ib_dev *dev = to_mdev(wq->device); 4953 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 4954 struct mlx5_ib_modify_wq ucmd = {}; 4955 size_t required_cmd_sz; 4956 int curr_wq_state; 4957 int wq_state; 4958 int inlen; 4959 int err; 4960 void *rqc; 4961 void *in; 4962 4963 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 4964 if (udata->inlen < required_cmd_sz) 4965 return -EINVAL; 4966 4967 if (udata->inlen > sizeof(ucmd) && 4968 !ib_is_udata_cleared(udata, sizeof(ucmd), 4969 udata->inlen - sizeof(ucmd))) 4970 return -EOPNOTSUPP; 4971 4972 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 4973 return -EFAULT; 4974 4975 if (ucmd.comp_mask || ucmd.reserved) 4976 return -EOPNOTSUPP; 4977 4978 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 4979 in = mlx5_vzalloc(inlen); 4980 if (!in) 4981 return -ENOMEM; 4982 4983 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 4984 4985 MLX5_SET(modify_rq_in, in, rqn, rwq->core_qp.qpn); 4986 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 4987 wq_attr->curr_wq_state : wq->state; 4988 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 4989 wq_attr->wq_state : curr_wq_state; 4990 if (curr_wq_state == IB_WQS_ERR) 4991 curr_wq_state = MLX5_RQC_STATE_ERR; 4992 if (wq_state == IB_WQS_ERR) 4993 wq_state = MLX5_RQC_STATE_ERR; 4994 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 4995 MLX5_SET(rqc, rqc, state, wq_state); 4996 4997 err = mlx5_core_modify_rq(dev->mdev, in, inlen); 4998 kvfree(in); 4999 if (!err) 5000 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 5001 5002 return err; 5003 } 5004