1 /*- 2 * Copyright (c) 2013-2021, Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 #include "opt_rss.h" 27 #include "opt_ratelimit.h" 28 29 #include <linux/module.h> 30 #include <rdma/ib_umem.h> 31 #include <rdma/ib_cache.h> 32 #include <rdma/ib_user_verbs.h> 33 #include <rdma/uverbs_ioctl.h> 34 #include <dev/mlx5/mlx5_ib/mlx5_ib.h> 35 36 /* not supported currently */ 37 static int wq_signature; 38 39 enum { 40 MLX5_IB_ACK_REQ_FREQ = 8, 41 }; 42 43 enum { 44 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 45 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 46 MLX5_IB_LINK_TYPE_IB = 0, 47 MLX5_IB_LINK_TYPE_ETH = 1 48 }; 49 50 enum { 51 MLX5_IB_SQ_STRIDE = 6, 52 }; 53 54 static const u32 mlx5_ib_opcode[] = { 55 [IB_WR_SEND] = MLX5_OPCODE_SEND, 56 [IB_WR_LSO] = MLX5_OPCODE_LSO, 57 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 58 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 59 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 60 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 61 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 62 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 63 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 64 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 65 [IB_WR_REG_MR] = MLX5_OPCODE_UMR, 66 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 67 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 68 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 69 }; 70 71 struct mlx5_wqe_eth_pad { 72 u8 rsvd0[16]; 73 }; 74 75 enum raw_qp_set_mask_map { 76 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 77 }; 78 79 struct mlx5_modify_raw_qp_param { 80 u16 operation; 81 82 u32 set_mask; /* raw_qp_set_mask_map */ 83 u8 rq_q_ctr_id; 84 }; 85 86 static void get_cqs(enum ib_qp_type qp_type, 87 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 88 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 89 90 static int is_qp0(enum ib_qp_type qp_type) 91 { 92 return qp_type == IB_QPT_SMI; 93 } 94 95 static int is_sqp(enum ib_qp_type qp_type) 96 { 97 return is_qp0(qp_type) || is_qp1(qp_type); 98 } 99 100 static void *get_wqe(struct mlx5_ib_qp *qp, int offset) 101 { 102 return mlx5_buf_offset(&qp->buf, offset); 103 } 104 105 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n) 106 { 107 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 108 } 109 110 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n) 111 { 112 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE)); 113 } 114 115 /** 116 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space. 117 * 118 * @qp: QP to copy from. 119 * @send: copy from the send queue when non-zero, use the receive queue 120 * otherwise. 121 * @wqe_index: index to start copying from. For send work queues, the 122 * wqe_index is in units of MLX5_SEND_WQE_BB. 123 * For receive work queue, it is the number of work queue 124 * element in the queue. 125 * @buffer: destination buffer. 126 * @length: maximum number of bytes to copy. 127 * 128 * Copies at least a single WQE, but may copy more data. 129 * 130 * Return: the number of bytes copied, or an error code. 131 */ 132 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 133 void *buffer, u32 length, 134 struct mlx5_ib_qp_base *base) 135 { 136 struct ib_device *ibdev = qp->ibqp.device; 137 struct mlx5_ib_dev *dev = to_mdev(ibdev); 138 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq; 139 size_t offset; 140 size_t wq_end; 141 struct ib_umem *umem = base->ubuffer.umem; 142 u32 first_copy_length; 143 int wqe_length; 144 int ret; 145 146 if (wq->wqe_cnt == 0) { 147 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n", 148 qp->ibqp.qp_type); 149 return -EINVAL; 150 } 151 152 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift); 153 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift); 154 155 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg)) 156 return -EINVAL; 157 158 if (offset > umem->length || 159 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length)) 160 return -EINVAL; 161 162 first_copy_length = min_t(u32, offset + length, wq_end) - offset; 163 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length); 164 if (ret) 165 return ret; 166 167 if (send) { 168 struct mlx5_wqe_ctrl_seg *ctrl = buffer; 169 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 170 171 wqe_length = ds * MLX5_WQE_DS_UNITS; 172 } else { 173 wqe_length = 1 << wq->wqe_shift; 174 } 175 176 if (wqe_length <= first_copy_length) 177 return first_copy_length; 178 179 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset, 180 wqe_length - first_copy_length); 181 if (ret) 182 return ret; 183 184 return wqe_length; 185 } 186 187 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 188 { 189 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 190 struct ib_event event; 191 192 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 193 /* This event is only valid for trans_qps */ 194 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 195 } 196 197 if (ibqp->event_handler) { 198 event.device = ibqp->device; 199 event.element.qp = ibqp; 200 switch (type) { 201 case MLX5_EVENT_TYPE_PATH_MIG: 202 event.event = IB_EVENT_PATH_MIG; 203 break; 204 case MLX5_EVENT_TYPE_COMM_EST: 205 event.event = IB_EVENT_COMM_EST; 206 break; 207 case MLX5_EVENT_TYPE_SQ_DRAINED: 208 event.event = IB_EVENT_SQ_DRAINED; 209 break; 210 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 211 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 212 break; 213 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 214 event.event = IB_EVENT_QP_FATAL; 215 break; 216 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 217 event.event = IB_EVENT_PATH_MIG_ERR; 218 break; 219 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 220 event.event = IB_EVENT_QP_REQ_ERR; 221 break; 222 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 223 event.event = IB_EVENT_QP_ACCESS_ERR; 224 break; 225 default: 226 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 227 return; 228 } 229 230 ibqp->event_handler(&event, ibqp->qp_context); 231 } 232 } 233 234 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 235 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 236 { 237 int wqe_size; 238 int wq_size; 239 240 /* Sanity check RQ size before proceeding */ 241 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 242 return -EINVAL; 243 244 if (!has_rq) { 245 qp->rq.max_gs = 0; 246 qp->rq.wqe_cnt = 0; 247 qp->rq.wqe_shift = 0; 248 cap->max_recv_wr = 0; 249 cap->max_recv_sge = 0; 250 } else { 251 if (ucmd) { 252 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 253 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 254 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 255 qp->rq.max_post = qp->rq.wqe_cnt; 256 } else { 257 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 258 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 259 wqe_size = roundup_pow_of_two(wqe_size); 260 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 261 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 262 qp->rq.wqe_cnt = wq_size / wqe_size; 263 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 264 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 265 wqe_size, 266 MLX5_CAP_GEN(dev->mdev, 267 max_wqe_sz_rq)); 268 return -EINVAL; 269 } 270 qp->rq.wqe_shift = ilog2(wqe_size); 271 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 272 qp->rq.max_post = qp->rq.wqe_cnt; 273 } 274 } 275 276 return 0; 277 } 278 279 static int sq_overhead(struct ib_qp_init_attr *attr) 280 { 281 int size = 0; 282 283 switch (attr->qp_type) { 284 case IB_QPT_XRC_INI: 285 size += sizeof(struct mlx5_wqe_xrc_seg); 286 /* fall through */ 287 case IB_QPT_RC: 288 size += sizeof(struct mlx5_wqe_ctrl_seg) + 289 max(sizeof(struct mlx5_wqe_atomic_seg) + 290 sizeof(struct mlx5_wqe_raddr_seg), 291 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 292 sizeof(struct mlx5_mkey_seg)); 293 break; 294 295 case IB_QPT_XRC_TGT: 296 return 0; 297 298 case IB_QPT_UC: 299 size += sizeof(struct mlx5_wqe_ctrl_seg) + 300 max(sizeof(struct mlx5_wqe_raddr_seg), 301 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 302 sizeof(struct mlx5_mkey_seg)); 303 break; 304 305 case IB_QPT_UD: 306 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 307 size += sizeof(struct mlx5_wqe_eth_pad) + 308 sizeof(struct mlx5_wqe_eth_seg); 309 /* fall through */ 310 case IB_QPT_SMI: 311 case MLX5_IB_QPT_HW_GSI: 312 size += sizeof(struct mlx5_wqe_ctrl_seg) + 313 sizeof(struct mlx5_wqe_datagram_seg); 314 break; 315 316 case MLX5_IB_QPT_REG_UMR: 317 size += sizeof(struct mlx5_wqe_ctrl_seg) + 318 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 319 sizeof(struct mlx5_mkey_seg); 320 break; 321 322 default: 323 return -EINVAL; 324 } 325 326 return size; 327 } 328 329 static int calc_send_wqe(struct ib_qp_init_attr *attr) 330 { 331 int inl_size = 0; 332 int size; 333 334 size = sq_overhead(attr); 335 if (size < 0) 336 return size; 337 338 if (attr->cap.max_inline_data) { 339 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 340 attr->cap.max_inline_data; 341 } 342 343 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 344 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && 345 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 346 return MLX5_SIG_WQE_SIZE; 347 else 348 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 349 } 350 351 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 352 { 353 int max_sge; 354 355 if (attr->qp_type == IB_QPT_RC) 356 max_sge = (min_t(int, wqe_size, 512) - 357 sizeof(struct mlx5_wqe_ctrl_seg) - 358 sizeof(struct mlx5_wqe_raddr_seg)) / 359 sizeof(struct mlx5_wqe_data_seg); 360 else if (attr->qp_type == IB_QPT_XRC_INI) 361 max_sge = (min_t(int, wqe_size, 512) - 362 sizeof(struct mlx5_wqe_ctrl_seg) - 363 sizeof(struct mlx5_wqe_xrc_seg) - 364 sizeof(struct mlx5_wqe_raddr_seg)) / 365 sizeof(struct mlx5_wqe_data_seg); 366 else 367 max_sge = (wqe_size - sq_overhead(attr)) / 368 sizeof(struct mlx5_wqe_data_seg); 369 370 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 371 sizeof(struct mlx5_wqe_data_seg)); 372 } 373 374 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 375 struct mlx5_ib_qp *qp) 376 { 377 int wqe_size; 378 int wq_size; 379 380 if (!attr->cap.max_send_wr) 381 return 0; 382 383 wqe_size = calc_send_wqe(attr); 384 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 385 if (wqe_size < 0) 386 return wqe_size; 387 388 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 389 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 390 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 391 return -EINVAL; 392 } 393 394 qp->max_inline_data = wqe_size - sq_overhead(attr) - 395 sizeof(struct mlx5_wqe_inline_seg); 396 attr->cap.max_inline_data = qp->max_inline_data; 397 398 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) 399 qp->signature_en = true; 400 401 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 402 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 403 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 404 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n", 405 qp->sq.wqe_cnt, 406 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 407 return -ENOMEM; 408 } 409 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 410 qp->sq.max_gs = get_send_sge(attr, wqe_size); 411 if (qp->sq.max_gs < attr->cap.max_send_sge) 412 return -ENOMEM; 413 414 attr->cap.max_send_sge = qp->sq.max_gs; 415 qp->sq.max_post = wq_size / wqe_size; 416 attr->cap.max_send_wr = qp->sq.max_post; 417 418 return wq_size; 419 } 420 421 static int set_user_buf_size(struct mlx5_ib_dev *dev, 422 struct mlx5_ib_qp *qp, 423 struct mlx5_ib_create_qp *ucmd, 424 struct mlx5_ib_qp_base *base, 425 struct ib_qp_init_attr *attr) 426 { 427 int desc_sz = 1 << qp->sq.wqe_shift; 428 429 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 430 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 431 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 432 return -EINVAL; 433 } 434 435 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) { 436 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n", 437 ucmd->sq_wqe_count, ucmd->sq_wqe_count); 438 return -EINVAL; 439 } 440 441 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 442 443 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 444 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 445 qp->sq.wqe_cnt, 446 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 447 return -EINVAL; 448 } 449 450 if (attr->qp_type == IB_QPT_RAW_PACKET) { 451 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 452 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 453 } else { 454 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 455 (qp->sq.wqe_cnt << 6); 456 } 457 458 return 0; 459 } 460 461 static int qp_has_rq(struct ib_qp_init_attr *attr) 462 { 463 if (attr->qp_type == IB_QPT_XRC_INI || 464 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 465 attr->qp_type == MLX5_IB_QPT_REG_UMR || 466 !attr->cap.max_recv_wr) 467 return 0; 468 469 return 1; 470 } 471 472 enum { 473 /* this is the first blue flame register in the array of bfregs assigned 474 * to a processes. Since we do not use it for blue flame but rather 475 * regular 64 bit doorbells, we do not need a lock for maintaiing 476 * "odd/even" order 477 */ 478 NUM_NON_BLUE_FLAME_BFREGS = 1, 479 }; 480 481 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 482 { 483 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; 484 } 485 486 static int num_med_bfreg(struct mlx5_ib_dev *dev, 487 struct mlx5_bfreg_info *bfregi) 488 { 489 int n; 490 491 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 492 NUM_NON_BLUE_FLAME_BFREGS; 493 494 return n >= 0 ? n : 0; 495 } 496 497 static int first_med_bfreg(struct mlx5_ib_dev *dev, 498 struct mlx5_bfreg_info *bfregi) 499 { 500 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; 501 } 502 503 static int first_hi_bfreg(struct mlx5_ib_dev *dev, 504 struct mlx5_bfreg_info *bfregi) 505 { 506 int med; 507 508 med = num_med_bfreg(dev, bfregi); 509 return ++med; 510 } 511 512 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 513 struct mlx5_bfreg_info *bfregi) 514 { 515 int i; 516 517 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 518 if (!bfregi->count[i]) { 519 bfregi->count[i]++; 520 return i; 521 } 522 } 523 524 return -ENOMEM; 525 } 526 527 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 528 struct mlx5_bfreg_info *bfregi) 529 { 530 int minidx = first_med_bfreg(dev, bfregi); 531 int i; 532 533 if (minidx < 0) 534 return minidx; 535 536 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { 537 if (bfregi->count[i] < bfregi->count[minidx]) 538 minidx = i; 539 if (!bfregi->count[minidx]) 540 break; 541 } 542 543 bfregi->count[minidx]++; 544 return minidx; 545 } 546 547 static int alloc_bfreg(struct mlx5_ib_dev *dev, 548 struct mlx5_bfreg_info *bfregi) 549 { 550 int bfregn = -ENOMEM; 551 552 if (bfregi->lib_uar_dyn) 553 return -EINVAL; 554 555 mutex_lock(&bfregi->lock); 556 if (bfregi->ver >= 2) { 557 bfregn = alloc_high_class_bfreg(dev, bfregi); 558 if (bfregn < 0) 559 bfregn = alloc_med_class_bfreg(dev, bfregi); 560 } 561 562 if (bfregn < 0) { 563 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 564 bfregn = 0; 565 bfregi->count[bfregn]++; 566 } 567 mutex_unlock(&bfregi->lock); 568 569 return bfregn; 570 } 571 572 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 573 { 574 mutex_lock(&bfregi->lock); 575 bfregi->count[bfregn]--; 576 mutex_unlock(&bfregi->lock); 577 } 578 579 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 580 { 581 switch (state) { 582 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 583 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 584 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 585 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 586 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 587 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 588 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 589 default: return -1; 590 } 591 } 592 593 static int to_mlx5_st(enum ib_qp_type type) 594 { 595 switch (type) { 596 case IB_QPT_RC: return MLX5_QP_ST_RC; 597 case IB_QPT_UC: return MLX5_QP_ST_UC; 598 case IB_QPT_UD: return MLX5_QP_ST_UD; 599 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 600 case IB_QPT_XRC_INI: 601 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 602 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 603 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 604 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 605 case IB_QPT_RAW_PACKET: 606 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 607 case IB_QPT_MAX: 608 default: return -EINVAL; 609 } 610 } 611 612 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 613 struct mlx5_ib_cq *recv_cq); 614 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 615 struct mlx5_ib_cq *recv_cq); 616 617 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 618 struct mlx5_bfreg_info *bfregi, u32 bfregn, 619 bool dyn_bfreg) 620 { 621 unsigned int bfregs_per_sys_page; 622 u32 index_of_sys_page; 623 u32 offset; 624 625 if (bfregi->lib_uar_dyn) 626 return -EINVAL; 627 628 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 629 MLX5_NON_FP_BFREGS_PER_UAR; 630 index_of_sys_page = bfregn / bfregs_per_sys_page; 631 632 if (dyn_bfreg) { 633 index_of_sys_page += bfregi->num_static_sys_pages; 634 635 if (index_of_sys_page >= bfregi->num_sys_pages) 636 return -EINVAL; 637 638 if (bfregn > bfregi->num_dyn_bfregs || 639 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 640 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 641 return -EINVAL; 642 } 643 } 644 645 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 646 return bfregi->sys_pages[index_of_sys_page] + offset; 647 } 648 649 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, 650 struct ib_pd *pd, 651 unsigned long addr, size_t size, 652 struct ib_umem **umem, 653 int *npages, int *page_shift, int *ncont, 654 u32 *offset) 655 { 656 int err; 657 658 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0); 659 if (IS_ERR(*umem)) { 660 mlx5_ib_dbg(dev, "umem_get failed\n"); 661 return PTR_ERR(*umem); 662 } 663 664 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL); 665 666 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 667 if (err) { 668 mlx5_ib_warn(dev, "bad offset\n"); 669 goto err_umem; 670 } 671 672 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", 673 addr, size, *npages, *page_shift, *ncont, *offset); 674 675 return 0; 676 677 err_umem: 678 ib_umem_release(*umem); 679 *umem = NULL; 680 681 return err; 682 } 683 684 static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq, 685 struct ib_udata *udata) 686 { 687 struct mlx5_ib_ucontext *context = 688 rdma_udata_to_drv_context( 689 udata, 690 struct mlx5_ib_ucontext, 691 ibucontext); 692 693 mlx5_ib_db_unmap_user(context, &rwq->db); 694 if (rwq->umem) 695 ib_umem_release(rwq->umem); 696 } 697 698 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 699 struct mlx5_ib_rwq *rwq, 700 struct mlx5_ib_create_wq *ucmd) 701 { 702 struct mlx5_ib_ucontext *context; 703 int page_shift = 0; 704 int npages; 705 u32 offset = 0; 706 int ncont = 0; 707 int err; 708 709 if (!ucmd->buf_addr) 710 return -EINVAL; 711 712 context = to_mucontext(pd->uobject->context); 713 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr, 714 rwq->buf_size, 0, 0); 715 if (IS_ERR(rwq->umem)) { 716 mlx5_ib_dbg(dev, "umem_get failed\n"); 717 err = PTR_ERR(rwq->umem); 718 return err; 719 } 720 721 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift, 722 &ncont, NULL); 723 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, 724 &rwq->rq_page_offset); 725 if (err) { 726 mlx5_ib_warn(dev, "bad offset\n"); 727 goto err_umem; 728 } 729 730 rwq->rq_num_pas = ncont; 731 rwq->page_shift = page_shift; 732 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; 733 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 734 735 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", 736 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 737 npages, page_shift, ncont, offset); 738 739 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db); 740 if (err) { 741 mlx5_ib_dbg(dev, "map failed\n"); 742 goto err_umem; 743 } 744 745 rwq->create_type = MLX5_WQ_USER; 746 return 0; 747 748 err_umem: 749 ib_umem_release(rwq->umem); 750 return err; 751 } 752 753 static int adjust_bfregn(struct mlx5_ib_dev *dev, 754 struct mlx5_bfreg_info *bfregi, int bfregn) 755 { 756 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 757 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 758 } 759 760 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 761 struct mlx5_ib_qp *qp, struct ib_udata *udata, 762 struct ib_qp_init_attr *attr, 763 u32 **in, 764 struct mlx5_ib_create_qp_resp *resp, int *inlen, 765 struct mlx5_ib_qp_base *base) 766 { 767 struct mlx5_ib_ucontext *context; 768 struct mlx5_ib_create_qp ucmd; 769 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 770 int page_shift = 0; 771 int uar_index = 0; 772 int npages; 773 u32 offset = 0; 774 int bfregn; 775 int ncont = 0; 776 __be64 *pas; 777 void *qpc; 778 int err; 779 u16 uid; 780 u32 uar_flags; 781 782 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 783 if (err) { 784 mlx5_ib_dbg(dev, "copy failed\n"); 785 return err; 786 } 787 788 context = to_mucontext(pd->uobject->context); 789 uar_flags = ucmd.flags & (MLX5_QP_FLAG_UAR_PAGE_INDEX | 790 MLX5_QP_FLAG_BFREG_INDEX); 791 switch (uar_flags) { 792 case MLX5_QP_FLAG_UAR_PAGE_INDEX: 793 uar_index = ucmd.bfreg_index; 794 bfregn = MLX5_IB_INVALID_BFREG; 795 break; 796 case MLX5_QP_FLAG_BFREG_INDEX: 797 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 798 ucmd.bfreg_index, true); 799 if (uar_index < 0) 800 return uar_index; 801 bfregn = MLX5_IB_INVALID_BFREG; 802 break; 803 case 0: 804 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 805 return -EINVAL; 806 bfregn = alloc_bfreg(dev, &context->bfregi); 807 if (bfregn < 0) 808 return bfregn; 809 break; 810 default: 811 return -EINVAL; 812 } 813 814 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 815 if (bfregn != MLX5_IB_INVALID_BFREG) 816 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 817 false); 818 819 qp->rq.offset = 0; 820 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 821 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 822 823 err = set_user_buf_size(dev, qp, &ucmd, base, attr); 824 if (err) 825 goto err_bfreg; 826 827 if (ucmd.buf_addr && ubuffer->buf_size) { 828 ubuffer->buf_addr = ucmd.buf_addr; 829 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, 830 ubuffer->buf_size, 831 &ubuffer->umem, &npages, &page_shift, 832 &ncont, &offset); 833 if (err) 834 goto err_bfreg; 835 } else { 836 ubuffer->umem = NULL; 837 } 838 839 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 840 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 841 *in = mlx5_vzalloc(*inlen); 842 if (!*in) { 843 err = -ENOMEM; 844 goto err_umem; 845 } 846 847 uid = (attr->qp_type != IB_QPT_XRC_TGT && 848 attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0; 849 MLX5_SET(create_qp_in, *in, uid, uid); 850 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 851 if (ubuffer->umem) 852 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0); 853 854 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 855 856 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 857 MLX5_SET(qpc, qpc, page_offset, offset); 858 859 MLX5_SET(qpc, qpc, uar_page, uar_index); 860 if (bfregn != MLX5_IB_INVALID_BFREG) 861 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 862 else 863 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 864 qp->bfregn = bfregn; 865 866 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db); 867 if (err) { 868 mlx5_ib_dbg(dev, "map failed\n"); 869 goto err_free; 870 } 871 872 err = ib_copy_to_udata(udata, resp, sizeof(*resp)); 873 if (err) { 874 mlx5_ib_dbg(dev, "copy failed\n"); 875 goto err_unmap; 876 } 877 qp->create_type = MLX5_QP_USER; 878 879 return 0; 880 881 err_unmap: 882 mlx5_ib_db_unmap_user(context, &qp->db); 883 884 err_free: 885 kvfree(*in); 886 887 err_umem: 888 if (ubuffer->umem) 889 ib_umem_release(ubuffer->umem); 890 891 err_bfreg: 892 if (bfregn != MLX5_IB_INVALID_BFREG) 893 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 894 return err; 895 } 896 897 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd, struct mlx5_ib_qp *qp, 898 struct mlx5_ib_qp_base *base, 899 struct ib_udata *udata) 900 { 901 struct mlx5_ib_ucontext *context = 902 rdma_udata_to_drv_context( 903 udata, 904 struct mlx5_ib_ucontext, 905 ibucontext); 906 907 mlx5_ib_db_unmap_user(context, &qp->db); 908 if (base->ubuffer.umem) 909 ib_umem_release(base->ubuffer.umem); 910 911 /* 912 * Free only the BFREGs which are handled by the kernel. 913 * BFREGs of UARs allocated dynamically are handled by user. 914 */ 915 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 916 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 917 } 918 919 static int create_kernel_qp(struct mlx5_ib_dev *dev, 920 struct ib_qp_init_attr *init_attr, 921 struct mlx5_ib_qp *qp, 922 u32 **in, int *inlen, 923 struct mlx5_ib_qp_base *base) 924 { 925 int uar_index; 926 void *qpc; 927 int err; 928 929 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | 930 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK | 931 IB_QP_CREATE_IPOIB_UD_LSO | 932 MLX5_IB_QP_CREATE_SQPN_QP1 | 933 MLX5_IB_QP_CREATE_WC_TEST)) 934 return -EINVAL; 935 936 spin_lock_init(&qp->bf.lock32); 937 938 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 939 qp->bf.bfreg = &dev->fp_bfreg; 940 else if (init_attr->create_flags & MLX5_IB_QP_CREATE_WC_TEST) 941 qp->bf.bfreg = &dev->wc_bfreg; 942 else 943 qp->bf.bfreg = &dev->bfreg; 944 945 /* We need to divide by two since each register is comprised of 946 * two buffers of identical size, namely odd and even 947 */ 948 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 949 uar_index = qp->bf.bfreg->index; 950 951 err = calc_sq_size(dev, init_attr, qp); 952 if (err < 0) { 953 mlx5_ib_dbg(dev, "err %d\n", err); 954 return err; 955 } 956 957 qp->rq.offset = 0; 958 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 959 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 960 961 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, 962 2 * PAGE_SIZE, &qp->buf); 963 if (err) { 964 mlx5_ib_dbg(dev, "err %d\n", err); 965 return err; 966 } 967 968 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt); 969 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 970 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 971 *in = mlx5_vzalloc(*inlen); 972 if (!*in) { 973 err = -ENOMEM; 974 goto err_buf; 975 } 976 977 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 978 MLX5_SET(qpc, qpc, uar_page, uar_index); 979 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev)); 980 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 981 982 /* Set "fast registration enabled" for all kernel QPs */ 983 MLX5_SET(qpc, qpc, fre, 1); 984 MLX5_SET(qpc, qpc, rlky, 1); 985 986 if (init_attr->create_flags & MLX5_IB_QP_CREATE_SQPN_QP1) { 987 MLX5_SET(qpc, qpc, deth_sqpn, 1); 988 qp->flags |= MLX5_IB_QP_SQPN_QP1; 989 } 990 991 mlx5_fill_page_array(&qp->buf, 992 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas)); 993 994 err = mlx5_db_alloc(dev->mdev, &qp->db); 995 if (err) { 996 mlx5_ib_dbg(dev, "err %d\n", err); 997 goto err_free; 998 } 999 1000 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL); 1001 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL); 1002 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL); 1003 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL); 1004 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1005 1006 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1007 !qp->sq.w_list || !qp->sq.wqe_head) { 1008 err = -ENOMEM; 1009 goto err_wrid; 1010 } 1011 qp->create_type = MLX5_QP_KERNEL; 1012 1013 return 0; 1014 1015 err_wrid: 1016 kfree(qp->sq.wqe_head); 1017 kfree(qp->sq.w_list); 1018 kfree(qp->sq.wrid); 1019 kfree(qp->sq.wr_data); 1020 kfree(qp->rq.wrid); 1021 mlx5_db_free(dev->mdev, &qp->db); 1022 1023 err_free: 1024 kvfree(*in); 1025 1026 err_buf: 1027 mlx5_buf_free(dev->mdev, &qp->buf); 1028 return err; 1029 } 1030 1031 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1032 { 1033 kfree(qp->sq.wqe_head); 1034 kfree(qp->sq.w_list); 1035 kfree(qp->sq.wrid); 1036 kfree(qp->sq.wr_data); 1037 kfree(qp->rq.wrid); 1038 mlx5_db_free(dev->mdev, &qp->db); 1039 mlx5_buf_free(dev->mdev, &qp->buf); 1040 } 1041 1042 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1043 { 1044 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 1045 (attr->qp_type == IB_QPT_XRC_INI)) 1046 return MLX5_SRQ_RQ; 1047 else if (!qp->has_rq) 1048 return MLX5_ZERO_LEN_RQ; 1049 else 1050 return MLX5_NON_ZERO_RQ; 1051 } 1052 1053 static int is_connected(enum ib_qp_type qp_type) 1054 { 1055 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC) 1056 return 1; 1057 1058 return 0; 1059 } 1060 1061 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1062 struct mlx5_ib_sq *sq, u32 tdn, 1063 struct ib_pd *pd) 1064 { 1065 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1066 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1067 1068 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid); 1069 MLX5_SET(tisc, tisc, transport_domain, tdn); 1070 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn); 1071 } 1072 1073 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1074 struct mlx5_ib_sq *sq, struct ib_pd *pd) 1075 { 1076 mlx5_core_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid); 1077 } 1078 1079 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1080 struct mlx5_ib_sq *sq, void *qpin, 1081 struct ib_pd *pd) 1082 { 1083 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1084 __be64 *pas; 1085 void *in; 1086 void *sqc; 1087 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1088 void *wq; 1089 int inlen; 1090 int err; 1091 int page_shift = 0; 1092 int npages; 1093 int ncont = 0; 1094 u32 offset = 0; 1095 u8 ts_format; 1096 1097 ts_format = mlx5_get_sq_default_ts(dev->mdev); 1098 1099 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size, 1100 &sq->ubuffer.umem, &npages, &page_shift, 1101 &ncont, &offset); 1102 if (err) 1103 return err; 1104 1105 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; 1106 in = mlx5_vzalloc(inlen); 1107 if (!in) { 1108 err = -ENOMEM; 1109 goto err_umem; 1110 } 1111 1112 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid); 1113 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1114 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1115 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1116 MLX5_SET(sqc, sqc, ts_format, ts_format); 1117 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1118 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1119 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1120 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1121 1122 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1123 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1124 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1125 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1126 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1127 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1128 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1129 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1130 MLX5_SET(wq, wq, page_offset, offset); 1131 1132 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1133 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); 1134 1135 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); 1136 1137 kvfree(in); 1138 1139 if (err) 1140 goto err_umem; 1141 1142 return 0; 1143 1144 err_umem: 1145 ib_umem_release(sq->ubuffer.umem); 1146 sq->ubuffer.umem = NULL; 1147 1148 return err; 1149 } 1150 1151 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1152 struct mlx5_ib_sq *sq) 1153 { 1154 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1155 ib_umem_release(sq->ubuffer.umem); 1156 } 1157 1158 static int get_rq_pas_size(void *qpc) 1159 { 1160 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; 1161 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); 1162 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); 1163 u32 page_offset = MLX5_GET(qpc, qpc, page_offset); 1164 u32 po_quanta = 1 << (log_page_size - 6); 1165 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); 1166 u32 page_size = 1 << log_page_size; 1167 u32 rq_sz_po = rq_sz + (page_offset * po_quanta); 1168 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; 1169 1170 return rq_num_pas * sizeof(u64); 1171 } 1172 1173 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1174 struct mlx5_ib_rq *rq, void *qpin, 1175 struct ib_pd *pd) 1176 { 1177 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1178 __be64 *pas; 1179 __be64 *qp_pas; 1180 void *in; 1181 void *rqc; 1182 void *wq; 1183 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1184 int inlen; 1185 int err; 1186 u32 rq_pas_size = get_rq_pas_size(qpc); 1187 u8 ts_format; 1188 1189 ts_format = mlx5_get_rq_default_ts(dev->mdev); 1190 1191 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; 1192 in = mlx5_vzalloc(inlen); 1193 if (!in) 1194 return -ENOMEM; 1195 1196 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 1197 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1198 MLX5_SET(rqc, rqc, vlan_strip_disable, 1); 1199 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE); 1200 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1201 MLX5_SET(rqc, rqc, ts_format, ts_format); 1202 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1203 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1204 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1205 1206 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS) 1207 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1208 1209 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1210 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1211 MLX5_SET(wq, wq, end_padding_mode, 1212 MLX5_GET(qpc, qpc, end_padding_mode)); 1213 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1214 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1215 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1216 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1217 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); 1218 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1219 1220 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1221 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); 1222 memcpy(pas, qp_pas, rq_pas_size); 1223 1224 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); 1225 1226 kvfree(in); 1227 1228 return err; 1229 } 1230 1231 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1232 struct mlx5_ib_rq *rq) 1233 { 1234 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); 1235 } 1236 1237 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1238 struct mlx5_ib_rq *rq, u32 tdn, 1239 struct ib_pd *pd) 1240 { 1241 u32 *in; 1242 void *tirc; 1243 int inlen; 1244 int err; 1245 1246 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1247 in = mlx5_vzalloc(inlen); 1248 if (!in) 1249 return -ENOMEM; 1250 1251 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1252 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context); 1253 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1254 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1255 MLX5_SET(tirc, tirc, transport_domain, tdn); 1256 1257 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn); 1258 1259 kvfree(in); 1260 1261 return err; 1262 } 1263 1264 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1265 struct mlx5_ib_rq *rq, 1266 struct ib_pd *pd) 1267 { 1268 mlx5_core_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid); 1269 } 1270 1271 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1272 u32 *in, 1273 struct ib_pd *pd) 1274 { 1275 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1276 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1277 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1278 struct ib_uobject *uobj = pd->uobject; 1279 struct ib_ucontext *ucontext = uobj->context; 1280 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1281 int err; 1282 u32 tdn = mucontext->tdn; 1283 1284 if (qp->sq.wqe_cnt) { 1285 err = create_raw_packet_qp_tis(dev, sq, tdn, pd); 1286 if (err) 1287 return err; 1288 1289 err = create_raw_packet_qp_sq(dev, sq, in, pd); 1290 if (err) 1291 goto err_destroy_tis; 1292 1293 sq->base.container_mibqp = qp; 1294 } 1295 1296 if (qp->rq.wqe_cnt) { 1297 rq->base.container_mibqp = qp; 1298 1299 err = create_raw_packet_qp_rq(dev, rq, in, pd); 1300 if (err) 1301 goto err_destroy_sq; 1302 1303 1304 err = create_raw_packet_qp_tir(dev, rq, tdn, pd); 1305 if (err) 1306 goto err_destroy_rq; 1307 } 1308 1309 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1310 rq->base.mqp.qpn; 1311 1312 return 0; 1313 1314 err_destroy_rq: 1315 destroy_raw_packet_qp_rq(dev, rq); 1316 err_destroy_sq: 1317 if (!qp->sq.wqe_cnt) 1318 return err; 1319 destroy_raw_packet_qp_sq(dev, sq); 1320 err_destroy_tis: 1321 destroy_raw_packet_qp_tis(dev, sq, pd); 1322 1323 return err; 1324 } 1325 1326 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1327 struct mlx5_ib_qp *qp) 1328 { 1329 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1330 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1331 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1332 1333 if (qp->rq.wqe_cnt) { 1334 destroy_raw_packet_qp_tir(dev, rq, qp->ibqp.pd); 1335 destroy_raw_packet_qp_rq(dev, rq); 1336 } 1337 1338 if (qp->sq.wqe_cnt) { 1339 destroy_raw_packet_qp_sq(dev, sq); 1340 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd); 1341 } 1342 } 1343 1344 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1345 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1346 { 1347 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1348 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1349 1350 sq->sq = &qp->sq; 1351 rq->rq = &qp->rq; 1352 sq->doorbell = &qp->db; 1353 rq->doorbell = &qp->db; 1354 } 1355 1356 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1357 { 1358 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1359 to_mpd(qp->ibqp.pd)->uid); 1360 } 1361 1362 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1363 struct ib_pd *pd, 1364 struct ib_qp_init_attr *init_attr, 1365 struct ib_udata *udata) 1366 { 1367 struct ib_uobject *uobj = pd->uobject; 1368 struct ib_ucontext *ucontext = uobj->context; 1369 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1370 struct mlx5_ib_create_qp_resp resp = {}; 1371 int inlen; 1372 int err; 1373 u32 *in; 1374 void *tirc; 1375 void *hfso; 1376 u32 selected_fields = 0; 1377 size_t min_resp_len; 1378 u32 tdn = mucontext->tdn; 1379 struct mlx5_ib_create_qp_rss ucmd = {}; 1380 size_t required_cmd_sz; 1381 1382 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1383 return -EOPNOTSUPP; 1384 1385 if (init_attr->create_flags || init_attr->send_cq) 1386 return -EINVAL; 1387 1388 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index); 1389 if (udata->outlen < min_resp_len) 1390 return -EINVAL; 1391 1392 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1); 1393 if (udata->inlen < required_cmd_sz) { 1394 mlx5_ib_dbg(dev, "invalid inlen\n"); 1395 return -EINVAL; 1396 } 1397 1398 if (udata->inlen > sizeof(ucmd) && 1399 !ib_is_udata_cleared(udata, sizeof(ucmd), 1400 udata->inlen - sizeof(ucmd))) { 1401 mlx5_ib_dbg(dev, "inlen is not supported\n"); 1402 return -EOPNOTSUPP; 1403 } 1404 1405 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 1406 mlx5_ib_dbg(dev, "copy failed\n"); 1407 return -EFAULT; 1408 } 1409 1410 if (ucmd.comp_mask) { 1411 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1412 return -EOPNOTSUPP; 1413 } 1414 1415 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) { 1416 mlx5_ib_dbg(dev, "invalid reserved\n"); 1417 return -EOPNOTSUPP; 1418 } 1419 1420 err = ib_copy_to_udata(udata, &resp, min_resp_len); 1421 if (err) { 1422 mlx5_ib_dbg(dev, "copy failed\n"); 1423 return -EINVAL; 1424 } 1425 1426 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1427 in = mlx5_vzalloc(inlen); 1428 if (!in) 1429 return -ENOMEM; 1430 1431 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1432 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context); 1433 MLX5_SET(tirc, tirc, disp_type, 1434 MLX5_TIRC_DISP_TYPE_INDIRECT); 1435 MLX5_SET(tirc, tirc, indirect_table, 1436 init_attr->rwq_ind_tbl->ind_tbl_num); 1437 MLX5_SET(tirc, tirc, transport_domain, tdn); 1438 1439 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1440 switch (ucmd.rx_hash_function) { 1441 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1442 { 1443 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1444 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1445 1446 if (len != ucmd.rx_key_len) { 1447 err = -EINVAL; 1448 goto err; 1449 } 1450 1451 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FUNC_TOEPLITZ); 1452 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 1453 memcpy(rss_key, ucmd.rx_hash_key, len); 1454 break; 1455 } 1456 default: 1457 err = -EOPNOTSUPP; 1458 goto err; 1459 } 1460 1461 if (!ucmd.rx_hash_fields_mask) { 1462 /* special case when this TIR serves as steering entry without hashing */ 1463 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1464 goto create_tir; 1465 err = -EINVAL; 1466 goto err; 1467 } 1468 1469 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1470 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1471 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1472 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1473 err = -EINVAL; 1474 goto err; 1475 } 1476 1477 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1478 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1479 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1480 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1481 MLX5_L3_PROT_TYPE_IPV4); 1482 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1483 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1484 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1485 MLX5_L3_PROT_TYPE_IPV6); 1486 1487 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1488 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) && 1489 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1490 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) { 1491 err = -EINVAL; 1492 goto err; 1493 } 1494 1495 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1496 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1497 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1498 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1499 MLX5_L4_PROT_TYPE_TCP); 1500 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1501 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1502 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1503 MLX5_L4_PROT_TYPE_UDP); 1504 1505 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1506 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1507 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1508 1509 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1510 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1511 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1512 1513 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1514 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1515 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1516 1517 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1518 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1519 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1520 1521 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1522 1523 create_tir: 1524 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn); 1525 1526 if (err) 1527 goto err; 1528 1529 kvfree(in); 1530 /* qpn is reserved for that QP */ 1531 qp->trans_qp.base.mqp.qpn = 0; 1532 qp->flags |= MLX5_IB_QP_RSS; 1533 return 0; 1534 1535 err: 1536 kvfree(in); 1537 return err; 1538 } 1539 1540 static int atomic_size_to_mode(int size_mask) 1541 { 1542 /* driver does not support atomic_size > 256B 1543 * and does not know how to translate bigger sizes 1544 */ 1545 int supported_size_mask = size_mask & 0x1ff; 1546 int log_max_size; 1547 1548 if (!supported_size_mask) 1549 return -EOPNOTSUPP; 1550 1551 log_max_size = __fls(supported_size_mask); 1552 1553 if (log_max_size > 3) 1554 return log_max_size; 1555 1556 return MLX5_ATOMIC_MODE_8B; 1557 } 1558 1559 static int get_atomic_mode(struct mlx5_ib_dev *dev, 1560 enum ib_qp_type qp_type) 1561 { 1562 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 1563 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic); 1564 int atomic_mode = -EOPNOTSUPP; 1565 int atomic_size_mask; 1566 1567 if (!atomic) 1568 return -EOPNOTSUPP; 1569 1570 if (qp_type == MLX5_IB_QPT_DCT) 1571 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 1572 else 1573 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 1574 1575 if ((atomic_operations & MLX5_ATOMIC_OPS_MASKED_CMP_SWAP) || 1576 (atomic_operations & MLX5_ATOMIC_OPS_MASKED_FETCH_ADD)) 1577 atomic_mode = atomic_size_to_mode(atomic_size_mask); 1578 1579 if (atomic_mode <= 0 && 1580 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP && 1581 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD)) 1582 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP; 1583 1584 return atomic_mode; 1585 } 1586 1587 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1588 struct ib_qp_init_attr *init_attr, 1589 struct ib_udata *udata, struct mlx5_ib_qp *qp) 1590 { 1591 struct mlx5_ib_resources *devr = &dev->devr; 1592 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1593 struct mlx5_core_dev *mdev = dev->mdev; 1594 struct mlx5_ib_create_qp_resp resp; 1595 struct mlx5_ib_cq *send_cq; 1596 struct mlx5_ib_cq *recv_cq; 1597 unsigned long flags; 1598 u32 uidx = MLX5_IB_DEFAULT_UIDX; 1599 struct mlx5_ib_create_qp ucmd; 1600 struct mlx5_ib_qp_base *base; 1601 void *qpc; 1602 u32 *in; 1603 int err; 1604 1605 base = init_attr->qp_type == IB_QPT_RAW_PACKET ? 1606 &qp->raw_packet_qp.rq.base : 1607 &qp->trans_qp.base; 1608 1609 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1610 mlx5_ib_odp_create_qp(qp); 1611 1612 mutex_init(&qp->mutex); 1613 spin_lock_init(&qp->sq.lock); 1614 spin_lock_init(&qp->rq.lock); 1615 1616 if (init_attr->rwq_ind_tbl) { 1617 if (!udata) 1618 return -ENOSYS; 1619 1620 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata); 1621 return err; 1622 } 1623 1624 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 1625 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { 1626 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); 1627 return -EINVAL; 1628 } else { 1629 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1630 } 1631 } 1632 1633 if (init_attr->create_flags & 1634 (IB_QP_CREATE_CROSS_CHANNEL | 1635 IB_QP_CREATE_MANAGED_SEND | 1636 IB_QP_CREATE_MANAGED_RECV)) { 1637 if (!MLX5_CAP_GEN(mdev, cd)) { 1638 mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); 1639 return -EINVAL; 1640 } 1641 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) 1642 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; 1643 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) 1644 qp->flags |= MLX5_IB_QP_MANAGED_SEND; 1645 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) 1646 qp->flags |= MLX5_IB_QP_MANAGED_RECV; 1647 } 1648 1649 if (init_attr->qp_type == IB_QPT_UD && 1650 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) 1651 if (!MLX5_CAP_GEN(mdev, ipoib_ipoib_offloads)) { 1652 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n"); 1653 return -EOPNOTSUPP; 1654 } 1655 1656 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 1657 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1658 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs"); 1659 return -EOPNOTSUPP; 1660 } 1661 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) || 1662 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 1663 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n"); 1664 return -EOPNOTSUPP; 1665 } 1666 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS; 1667 } 1668 1669 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1670 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1671 1672 if (pd && pd->uobject) { 1673 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 1674 mlx5_ib_dbg(dev, "copy failed\n"); 1675 return -EFAULT; 1676 } 1677 1678 err = get_qp_user_index(to_mucontext(pd->uobject->context), 1679 &ucmd, udata->inlen, &uidx); 1680 if (err) 1681 return err; 1682 1683 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 1684 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 1685 } else { 1686 qp->wq_sig = !!wq_signature; 1687 } 1688 1689 qp->has_rq = qp_has_rq(init_attr); 1690 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 1691 qp, (pd && pd->uobject) ? &ucmd : NULL); 1692 if (err) { 1693 mlx5_ib_dbg(dev, "err %d\n", err); 1694 return err; 1695 } 1696 1697 if (pd) { 1698 if (pd->uobject) { 1699 __u32 max_wqes = 1700 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1701 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 1702 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 1703 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 1704 mlx5_ib_dbg(dev, "invalid rq params\n"); 1705 return -EINVAL; 1706 } 1707 if (ucmd.sq_wqe_count > max_wqes) { 1708 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 1709 ucmd.sq_wqe_count, max_wqes); 1710 return -EINVAL; 1711 } 1712 if (init_attr->create_flags & 1713 MLX5_IB_QP_CREATE_SQPN_QP1) { 1714 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n"); 1715 return -EINVAL; 1716 } 1717 err = create_user_qp(dev, pd, qp, udata, init_attr, &in, 1718 &resp, &inlen, base); 1719 if (err) 1720 mlx5_ib_dbg(dev, "err %d\n", err); 1721 } else { 1722 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, 1723 base); 1724 if (err) 1725 mlx5_ib_dbg(dev, "err %d\n", err); 1726 } 1727 1728 if (err) 1729 return err; 1730 } else { 1731 in = mlx5_vzalloc(inlen); 1732 if (!in) 1733 return -ENOMEM; 1734 1735 qp->create_type = MLX5_QP_EMPTY; 1736 } 1737 1738 if (is_sqp(init_attr->qp_type)) 1739 qp->port = init_attr->port_num; 1740 1741 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1742 1743 MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type)); 1744 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1745 1746 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 1747 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 1748 else 1749 MLX5_SET(qpc, qpc, latency_sensitive, 1); 1750 1751 1752 if (qp->wq_sig) 1753 MLX5_SET(qpc, qpc, wq_signature, 1); 1754 1755 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 1756 MLX5_SET(qpc, qpc, block_lb_mc, 1); 1757 1758 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 1759 MLX5_SET(qpc, qpc, cd_master, 1); 1760 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 1761 MLX5_SET(qpc, qpc, cd_slave_send, 1); 1762 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 1763 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 1764 1765 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 1766 int rcqe_sz; 1767 int scqe_sz; 1768 1769 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq); 1770 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq); 1771 1772 if (rcqe_sz == 128) 1773 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 1774 else 1775 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE); 1776 1777 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) { 1778 if (scqe_sz == 128) 1779 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1780 else 1781 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1782 } 1783 } 1784 1785 if (qp->rq.wqe_cnt) { 1786 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 1787 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 1788 } 1789 1790 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1791 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev)); 1792 1793 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 1794 1795 if (qp->sq.wqe_cnt) 1796 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 1797 else 1798 MLX5_SET(qpc, qpc, no_sq, 1); 1799 1800 /* Set default resources */ 1801 switch (init_attr->qp_type) { 1802 case IB_QPT_XRC_TGT: 1803 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1804 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 1805 MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s0)->msrq.srqn); 1806 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn); 1807 break; 1808 case IB_QPT_XRC_INI: 1809 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1810 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1811 MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s0)->msrq.srqn); 1812 break; 1813 default: 1814 if (init_attr->srq) { 1815 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn); 1816 MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(init_attr->srq)->msrq.srqn); 1817 } else { 1818 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1819 MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s1)->msrq.srqn); 1820 } 1821 } 1822 1823 if (init_attr->send_cq) 1824 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 1825 1826 if (init_attr->recv_cq) 1827 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 1828 1829 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 1830 1831 /* 0xffffff means we ask to work with cqe version 0 */ 1832 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 1833 MLX5_SET(qpc, qpc, user_index, uidx); 1834 1835 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 1836 if (init_attr->qp_type == IB_QPT_UD && 1837 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) { 1838 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 1839 qp->flags |= MLX5_IB_QP_LSO; 1840 } 1841 1842 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 1843 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; 1844 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 1845 err = create_raw_packet_qp(dev, qp, in, pd); 1846 } else { 1847 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); 1848 } 1849 1850 if (err) { 1851 mlx5_ib_dbg(dev, "create qp failed\n"); 1852 goto err_create; 1853 } 1854 1855 kvfree(in); 1856 1857 base->container_mibqp = qp; 1858 base->mqp.event = mlx5_ib_qp_event; 1859 1860 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq, 1861 &send_cq, &recv_cq); 1862 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1863 mlx5_ib_lock_cqs(send_cq, recv_cq); 1864 /* Maintain device to QPs access, needed for further handling via reset 1865 * flow 1866 */ 1867 list_add_tail(&qp->qps_list, &dev->qp_list); 1868 /* Maintain CQ to QPs access, needed for further handling via reset flow 1869 */ 1870 if (send_cq) 1871 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 1872 if (recv_cq) 1873 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 1874 mlx5_ib_unlock_cqs(send_cq, recv_cq); 1875 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1876 1877 return 0; 1878 1879 err_create: 1880 if (qp->create_type == MLX5_QP_USER) 1881 destroy_qp_user(dev, pd, qp, base, udata); 1882 else if (qp->create_type == MLX5_QP_KERNEL) 1883 destroy_qp_kernel(dev, qp); 1884 1885 kvfree(in); 1886 return err; 1887 } 1888 1889 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1890 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1891 { 1892 if (send_cq) { 1893 if (recv_cq) { 1894 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1895 spin_lock(&send_cq->lock); 1896 spin_lock_nested(&recv_cq->lock, 1897 SINGLE_DEPTH_NESTING); 1898 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1899 spin_lock(&send_cq->lock); 1900 __acquire(&recv_cq->lock); 1901 } else { 1902 spin_lock(&recv_cq->lock); 1903 spin_lock_nested(&send_cq->lock, 1904 SINGLE_DEPTH_NESTING); 1905 } 1906 } else { 1907 spin_lock(&send_cq->lock); 1908 __acquire(&recv_cq->lock); 1909 } 1910 } else if (recv_cq) { 1911 spin_lock(&recv_cq->lock); 1912 __acquire(&send_cq->lock); 1913 } else { 1914 __acquire(&send_cq->lock); 1915 __acquire(&recv_cq->lock); 1916 } 1917 } 1918 1919 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1920 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1921 { 1922 if (send_cq) { 1923 if (recv_cq) { 1924 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1925 spin_unlock(&recv_cq->lock); 1926 spin_unlock(&send_cq->lock); 1927 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1928 __release(&recv_cq->lock); 1929 spin_unlock(&send_cq->lock); 1930 } else { 1931 spin_unlock(&send_cq->lock); 1932 spin_unlock(&recv_cq->lock); 1933 } 1934 } else { 1935 __release(&recv_cq->lock); 1936 spin_unlock(&send_cq->lock); 1937 } 1938 } else if (recv_cq) { 1939 __release(&send_cq->lock); 1940 spin_unlock(&recv_cq->lock); 1941 } else { 1942 __release(&recv_cq->lock); 1943 __release(&send_cq->lock); 1944 } 1945 } 1946 1947 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 1948 { 1949 return to_mpd(qp->ibqp.pd); 1950 } 1951 1952 static void get_cqs(enum ib_qp_type qp_type, 1953 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 1954 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 1955 { 1956 switch (qp_type) { 1957 case IB_QPT_XRC_TGT: 1958 *send_cq = NULL; 1959 *recv_cq = NULL; 1960 break; 1961 case MLX5_IB_QPT_REG_UMR: 1962 case IB_QPT_XRC_INI: 1963 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 1964 *recv_cq = NULL; 1965 break; 1966 1967 case IB_QPT_SMI: 1968 case MLX5_IB_QPT_HW_GSI: 1969 case IB_QPT_RC: 1970 case IB_QPT_UC: 1971 case IB_QPT_UD: 1972 case IB_QPT_RAW_IPV6: 1973 case IB_QPT_RAW_ETHERTYPE: 1974 case IB_QPT_RAW_PACKET: 1975 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 1976 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 1977 break; 1978 1979 case IB_QPT_MAX: 1980 default: 1981 *send_cq = NULL; 1982 *recv_cq = NULL; 1983 break; 1984 } 1985 } 1986 1987 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1988 const struct mlx5_modify_raw_qp_param *raw_qp_param, 1989 u8 lag_tx_affinity); 1990 1991 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1992 struct ib_udata *udata) 1993 { 1994 struct mlx5_ib_cq *send_cq, *recv_cq; 1995 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 1996 unsigned long flags; 1997 int err; 1998 1999 if (qp->ibqp.rwq_ind_tbl) { 2000 destroy_rss_raw_qp_tir(dev, qp); 2001 return; 2002 } 2003 2004 base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ? 2005 &qp->raw_packet_qp.rq.base : 2006 &qp->trans_qp.base; 2007 2008 if (qp->state != IB_QPS_RESET) { 2009 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) { 2010 mlx5_ib_qp_disable_pagefaults(qp); 2011 err = mlx5_core_qp_modify(dev->mdev, 2012 MLX5_CMD_OP_2RST_QP, 0, 2013 NULL, &base->mqp); 2014 } else { 2015 struct mlx5_modify_raw_qp_param raw_qp_param = { 2016 .operation = MLX5_CMD_OP_2RST_QP 2017 }; 2018 2019 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2020 } 2021 if (err) 2022 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2023 base->mqp.qpn); 2024 } 2025 2026 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2027 &send_cq, &recv_cq); 2028 2029 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2030 mlx5_ib_lock_cqs(send_cq, recv_cq); 2031 /* del from lists under both locks above to protect reset flow paths */ 2032 list_del(&qp->qps_list); 2033 if (send_cq) 2034 list_del(&qp->cq_send_list); 2035 2036 if (recv_cq) 2037 list_del(&qp->cq_recv_list); 2038 2039 if (qp->create_type == MLX5_QP_KERNEL) { 2040 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2041 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2042 if (send_cq != recv_cq) 2043 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2044 NULL); 2045 } 2046 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2047 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2048 2049 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 2050 destroy_raw_packet_qp(dev, qp); 2051 } else { 2052 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); 2053 if (err) 2054 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2055 base->mqp.qpn); 2056 } 2057 2058 if (qp->create_type == MLX5_QP_KERNEL) 2059 destroy_qp_kernel(dev, qp); 2060 else if (qp->create_type == MLX5_QP_USER) 2061 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base, udata); 2062 } 2063 2064 static const char *ib_qp_type_str(enum ib_qp_type type) 2065 { 2066 switch (type) { 2067 case IB_QPT_SMI: 2068 return "IB_QPT_SMI"; 2069 case IB_QPT_GSI: 2070 return "IB_QPT_GSI"; 2071 case IB_QPT_RC: 2072 return "IB_QPT_RC"; 2073 case IB_QPT_UC: 2074 return "IB_QPT_UC"; 2075 case IB_QPT_UD: 2076 return "IB_QPT_UD"; 2077 case IB_QPT_RAW_IPV6: 2078 return "IB_QPT_RAW_IPV6"; 2079 case IB_QPT_RAW_ETHERTYPE: 2080 return "IB_QPT_RAW_ETHERTYPE"; 2081 case IB_QPT_XRC_INI: 2082 return "IB_QPT_XRC_INI"; 2083 case IB_QPT_XRC_TGT: 2084 return "IB_QPT_XRC_TGT"; 2085 case IB_QPT_RAW_PACKET: 2086 return "IB_QPT_RAW_PACKET"; 2087 case MLX5_IB_QPT_REG_UMR: 2088 return "MLX5_IB_QPT_REG_UMR"; 2089 case IB_QPT_MAX: 2090 default: 2091 return "Invalid QP type"; 2092 } 2093 } 2094 2095 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 2096 struct ib_qp_init_attr *init_attr, 2097 struct ib_udata *udata) 2098 { 2099 struct mlx5_ib_dev *dev; 2100 struct mlx5_ib_qp *qp; 2101 u16 xrcdn = 0; 2102 int err; 2103 2104 if (pd) { 2105 dev = to_mdev(pd->device); 2106 2107 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 2108 if (!pd->uobject) { 2109 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); 2110 return ERR_PTR(-EINVAL); 2111 } else if (!to_mucontext(pd->uobject->context)->cqe_version) { 2112 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); 2113 return ERR_PTR(-EINVAL); 2114 } 2115 } 2116 } else { 2117 /* being cautious here */ 2118 if (init_attr->qp_type != IB_QPT_XRC_TGT && 2119 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 2120 pr_warn("%s: no PD for transport %s\n", __func__, 2121 ib_qp_type_str(init_attr->qp_type)); 2122 return ERR_PTR(-EINVAL); 2123 } 2124 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 2125 } 2126 2127 switch (init_attr->qp_type) { 2128 case IB_QPT_XRC_TGT: 2129 case IB_QPT_XRC_INI: 2130 if (!MLX5_CAP_GEN(dev->mdev, xrc)) { 2131 mlx5_ib_dbg(dev, "XRC not supported\n"); 2132 return ERR_PTR(-ENOSYS); 2133 } 2134 init_attr->recv_cq = NULL; 2135 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 2136 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 2137 init_attr->send_cq = NULL; 2138 } 2139 2140 /* fall through */ 2141 case IB_QPT_RAW_PACKET: 2142 case IB_QPT_RC: 2143 case IB_QPT_UC: 2144 case IB_QPT_UD: 2145 case IB_QPT_SMI: 2146 case MLX5_IB_QPT_HW_GSI: 2147 case MLX5_IB_QPT_REG_UMR: 2148 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2149 if (!qp) 2150 return ERR_PTR(-ENOMEM); 2151 2152 err = create_qp_common(dev, pd, init_attr, udata, qp); 2153 if (err) { 2154 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 2155 kfree(qp); 2156 return ERR_PTR(err); 2157 } 2158 2159 if (is_qp0(init_attr->qp_type)) 2160 qp->ibqp.qp_num = 0; 2161 else if (is_qp1(init_attr->qp_type)) 2162 qp->ibqp.qp_num = 1; 2163 else 2164 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2165 2166 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 2167 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2168 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1, 2169 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1); 2170 2171 qp->trans_qp.xrcdn = xrcdn; 2172 2173 break; 2174 2175 case IB_QPT_GSI: 2176 return mlx5_ib_gsi_create_qp(pd, init_attr); 2177 2178 case IB_QPT_RAW_IPV6: 2179 case IB_QPT_RAW_ETHERTYPE: 2180 case IB_QPT_MAX: 2181 default: 2182 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 2183 init_attr->qp_type); 2184 /* Don't support raw QPs */ 2185 return ERR_PTR(-EINVAL); 2186 } 2187 2188 return &qp->ibqp; 2189 } 2190 2191 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 2192 { 2193 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2194 struct mlx5_ib_qp *mqp = to_mqp(qp); 2195 2196 if (unlikely(qp->qp_type == IB_QPT_GSI)) 2197 return mlx5_ib_gsi_destroy_qp(qp); 2198 2199 destroy_qp_common(dev, mqp, udata); 2200 2201 kfree(mqp); 2202 2203 return 0; 2204 } 2205 2206 static int to_mlx5_access_flags(struct mlx5_ib_qp *qp, 2207 const struct ib_qp_attr *attr, 2208 int attr_mask, __be32 *hw_access_flags_be) 2209 { 2210 u8 dest_rd_atomic; 2211 u32 access_flags, hw_access_flags = 0; 2212 2213 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 2214 2215 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2216 dest_rd_atomic = attr->max_dest_rd_atomic; 2217 else 2218 dest_rd_atomic = qp->trans_qp.resp_depth; 2219 2220 if (attr_mask & IB_QP_ACCESS_FLAGS) 2221 access_flags = attr->qp_access_flags; 2222 else 2223 access_flags = qp->trans_qp.atomic_rd_en; 2224 2225 if (!dest_rd_atomic) 2226 access_flags &= IB_ACCESS_REMOTE_WRITE; 2227 2228 if (access_flags & IB_ACCESS_REMOTE_READ) 2229 hw_access_flags |= MLX5_QP_BIT_RRE; 2230 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) { 2231 int atomic_mode; 2232 2233 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type); 2234 if (atomic_mode < 0) 2235 return -EOPNOTSUPP; 2236 2237 hw_access_flags |= MLX5_QP_BIT_RAE; 2238 hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFF; 2239 } 2240 2241 if (access_flags & IB_ACCESS_REMOTE_WRITE) 2242 hw_access_flags |= MLX5_QP_BIT_RWE; 2243 2244 *hw_access_flags_be = cpu_to_be32(hw_access_flags); 2245 2246 return 0; 2247 } 2248 2249 enum { 2250 MLX5_PATH_FLAG_FL = 1 << 0, 2251 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 2252 MLX5_PATH_FLAG_COUNTER = 1 << 2, 2253 }; 2254 2255 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 2256 { 2257 if (rate == IB_RATE_PORT_CURRENT) { 2258 return 0; 2259 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS) { 2260 return -EINVAL; 2261 } else { 2262 while (rate != IB_RATE_2_5_GBPS && 2263 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 2264 MLX5_CAP_GEN(dev->mdev, stat_rate_support))) 2265 --rate; 2266 } 2267 2268 return rate + MLX5_STAT_RATE_OFFSET; 2269 } 2270 2271 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 2272 struct mlx5_ib_sq *sq, u8 sl, 2273 struct ib_pd *pd) 2274 { 2275 void *in; 2276 void *tisc; 2277 int inlen; 2278 int err; 2279 2280 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2281 in = mlx5_vzalloc(inlen); 2282 if (!in) 2283 return -ENOMEM; 2284 2285 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 2286 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 2287 2288 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2289 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 2290 2291 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2292 2293 kvfree(in); 2294 2295 return err; 2296 } 2297 2298 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 2299 struct mlx5_ib_sq *sq, u8 tx_affinity, 2300 struct ib_pd *pd) 2301 { 2302 void *in; 2303 void *tisc; 2304 int inlen; 2305 int err; 2306 2307 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2308 in = mlx5_vzalloc(inlen); 2309 if (!in) 2310 return -ENOMEM; 2311 2312 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 2313 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 2314 2315 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2316 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 2317 2318 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2319 2320 kvfree(in); 2321 2322 return err; 2323 } 2324 2325 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2326 const struct ib_ah_attr *ah, 2327 struct mlx5_qp_path *path, u8 port, int attr_mask, 2328 u32 path_flags, const struct ib_qp_attr *attr, 2329 bool alt) 2330 { 2331 enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port); 2332 int err; 2333 enum ib_gid_type gid_type; 2334 2335 if (attr_mask & IB_QP_PKEY_INDEX) 2336 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index : 2337 attr->pkey_index); 2338 2339 if (ah->ah_flags & IB_AH_GRH) { 2340 if (ah->grh.sgid_index >= 2341 dev->mdev->port_caps[port - 1].gid_table_len) { 2342 pr_err("sgid_index (%u) too large. max is %d\n", 2343 ah->grh.sgid_index, 2344 dev->mdev->port_caps[port - 1].gid_table_len); 2345 return -EINVAL; 2346 } 2347 } 2348 2349 if (ll == IB_LINK_LAYER_ETHERNET) { 2350 if (!(ah->ah_flags & IB_AH_GRH)) 2351 return -EINVAL; 2352 err = mlx5_get_roce_gid_type(dev, port, ah->grh.sgid_index, 2353 &gid_type); 2354 if (err) 2355 return err; 2356 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac)); 2357 path->udp_sport = mlx5_get_roce_udp_sport(dev, port, 2358 ah->grh.sgid_index); 2359 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4; 2360 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 2361 path->ecn_dscp = (ah->grh.traffic_class >> 2) & 0x3f; 2362 } else { 2363 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 2364 path->fl_free_ar |= 2365 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0; 2366 path->rlid = cpu_to_be16(ah->dlid); 2367 path->grh_mlid = ah->src_path_bits & 0x7f; 2368 if (ah->ah_flags & IB_AH_GRH) 2369 path->grh_mlid |= 1 << 7; 2370 path->dci_cfi_prio_sl = ah->sl & 0xf; 2371 } 2372 2373 if (ah->ah_flags & IB_AH_GRH) { 2374 path->mgid_index = ah->grh.sgid_index; 2375 path->hop_limit = ah->grh.hop_limit; 2376 path->tclass_flowlabel = 2377 cpu_to_be32((ah->grh.traffic_class << 20) | 2378 (ah->grh.flow_label)); 2379 memcpy(path->rgid, ah->grh.dgid.raw, 16); 2380 } 2381 2382 err = ib_rate_to_mlx5(dev, ah->static_rate); 2383 if (err < 0) 2384 return err; 2385 path->static_rate = err; 2386 path->port = port; 2387 2388 if (attr_mask & IB_QP_TIMEOUT) 2389 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3; 2390 2391 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 2392 return modify_raw_packet_eth_prio(dev->mdev, 2393 &qp->raw_packet_qp.sq, 2394 ah->sl & 0xf, qp->ibqp.pd); 2395 2396 return 0; 2397 } 2398 2399 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 2400 [MLX5_QP_STATE_INIT] = { 2401 [MLX5_QP_STATE_INIT] = { 2402 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2403 MLX5_QP_OPTPAR_RAE | 2404 MLX5_QP_OPTPAR_RWE | 2405 MLX5_QP_OPTPAR_PKEY_INDEX | 2406 MLX5_QP_OPTPAR_PRI_PORT, 2407 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2408 MLX5_QP_OPTPAR_PKEY_INDEX | 2409 MLX5_QP_OPTPAR_PRI_PORT, 2410 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2411 MLX5_QP_OPTPAR_Q_KEY | 2412 MLX5_QP_OPTPAR_PRI_PORT, 2413 }, 2414 [MLX5_QP_STATE_RTR] = { 2415 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2416 MLX5_QP_OPTPAR_RRE | 2417 MLX5_QP_OPTPAR_RAE | 2418 MLX5_QP_OPTPAR_RWE | 2419 MLX5_QP_OPTPAR_PKEY_INDEX, 2420 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2421 MLX5_QP_OPTPAR_RWE | 2422 MLX5_QP_OPTPAR_PKEY_INDEX, 2423 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2424 MLX5_QP_OPTPAR_Q_KEY, 2425 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 2426 MLX5_QP_OPTPAR_Q_KEY, 2427 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2428 MLX5_QP_OPTPAR_RRE | 2429 MLX5_QP_OPTPAR_RAE | 2430 MLX5_QP_OPTPAR_RWE | 2431 MLX5_QP_OPTPAR_PKEY_INDEX, 2432 }, 2433 }, 2434 [MLX5_QP_STATE_RTR] = { 2435 [MLX5_QP_STATE_RTS] = { 2436 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2437 MLX5_QP_OPTPAR_RRE | 2438 MLX5_QP_OPTPAR_RAE | 2439 MLX5_QP_OPTPAR_RWE | 2440 MLX5_QP_OPTPAR_PM_STATE | 2441 MLX5_QP_OPTPAR_RNR_TIMEOUT, 2442 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2443 MLX5_QP_OPTPAR_RWE | 2444 MLX5_QP_OPTPAR_PM_STATE, 2445 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2446 }, 2447 }, 2448 [MLX5_QP_STATE_RTS] = { 2449 [MLX5_QP_STATE_RTS] = { 2450 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2451 MLX5_QP_OPTPAR_RAE | 2452 MLX5_QP_OPTPAR_RWE | 2453 MLX5_QP_OPTPAR_RNR_TIMEOUT | 2454 MLX5_QP_OPTPAR_PM_STATE | 2455 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2456 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2457 MLX5_QP_OPTPAR_PM_STATE | 2458 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2459 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 2460 MLX5_QP_OPTPAR_SRQN | 2461 MLX5_QP_OPTPAR_CQN_RCV, 2462 }, 2463 }, 2464 [MLX5_QP_STATE_SQER] = { 2465 [MLX5_QP_STATE_RTS] = { 2466 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2467 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 2468 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 2469 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 2470 MLX5_QP_OPTPAR_RWE | 2471 MLX5_QP_OPTPAR_RAE | 2472 MLX5_QP_OPTPAR_RRE, 2473 }, 2474 }, 2475 }; 2476 2477 static int ib_nr_to_mlx5_nr(int ib_mask) 2478 { 2479 switch (ib_mask) { 2480 case IB_QP_STATE: 2481 return 0; 2482 case IB_QP_CUR_STATE: 2483 return 0; 2484 case IB_QP_EN_SQD_ASYNC_NOTIFY: 2485 return 0; 2486 case IB_QP_ACCESS_FLAGS: 2487 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 2488 MLX5_QP_OPTPAR_RAE; 2489 case IB_QP_PKEY_INDEX: 2490 return MLX5_QP_OPTPAR_PKEY_INDEX; 2491 case IB_QP_PORT: 2492 return MLX5_QP_OPTPAR_PRI_PORT; 2493 case IB_QP_QKEY: 2494 return MLX5_QP_OPTPAR_Q_KEY; 2495 case IB_QP_AV: 2496 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 2497 MLX5_QP_OPTPAR_PRI_PORT; 2498 case IB_QP_PATH_MTU: 2499 return 0; 2500 case IB_QP_TIMEOUT: 2501 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 2502 case IB_QP_RETRY_CNT: 2503 return MLX5_QP_OPTPAR_RETRY_COUNT; 2504 case IB_QP_RNR_RETRY: 2505 return MLX5_QP_OPTPAR_RNR_RETRY; 2506 case IB_QP_RQ_PSN: 2507 return 0; 2508 case IB_QP_MAX_QP_RD_ATOMIC: 2509 return MLX5_QP_OPTPAR_SRA_MAX; 2510 case IB_QP_ALT_PATH: 2511 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 2512 case IB_QP_MIN_RNR_TIMER: 2513 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 2514 case IB_QP_SQ_PSN: 2515 return 0; 2516 case IB_QP_MAX_DEST_RD_ATOMIC: 2517 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 2518 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 2519 case IB_QP_PATH_MIG_STATE: 2520 return MLX5_QP_OPTPAR_PM_STATE; 2521 case IB_QP_CAP: 2522 return 0; 2523 case IB_QP_DEST_QPN: 2524 return 0; 2525 } 2526 return 0; 2527 } 2528 2529 static int ib_mask_to_mlx5_opt(int ib_mask) 2530 { 2531 int result = 0; 2532 int i; 2533 2534 for (i = 0; i < 8 * sizeof(int); i++) { 2535 if ((1 << i) & ib_mask) 2536 result |= ib_nr_to_mlx5_nr(1 << i); 2537 } 2538 2539 return result; 2540 } 2541 2542 static int modify_raw_packet_qp_rq( 2543 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state, 2544 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 2545 { 2546 void *in; 2547 void *rqc; 2548 int inlen; 2549 int err; 2550 2551 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 2552 in = mlx5_vzalloc(inlen); 2553 if (!in) 2554 return -ENOMEM; 2555 2556 MLX5_SET(modify_rq_in, in, rqn, rq->base.mqp.qpn); 2557 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 2558 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid); 2559 2560 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 2561 MLX5_SET(rqc, rqc, state, new_state); 2562 2563 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 2564 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counters_set_id)) { 2565 MLX5_SET64(modify_rq_in, in, modify_bitmask, 2566 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID); 2567 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 2568 } else 2569 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n", 2570 dev->ib_dev.name); 2571 } 2572 2573 err = mlx5_core_modify_rq(dev->mdev, in, inlen); 2574 if (err) 2575 goto out; 2576 2577 rq->state = new_state; 2578 2579 out: 2580 kvfree(in); 2581 return err; 2582 } 2583 2584 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev, 2585 struct mlx5_ib_sq *sq, int new_state, 2586 struct ib_pd *pd) 2587 { 2588 void *in; 2589 void *sqc; 2590 int inlen; 2591 int err; 2592 2593 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 2594 in = mlx5_vzalloc(inlen); 2595 if (!in) 2596 return -ENOMEM; 2597 2598 MLX5_SET(modify_sq_in, in, sqn, sq->base.mqp.qpn); 2599 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid); 2600 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 2601 2602 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 2603 MLX5_SET(sqc, sqc, state, new_state); 2604 2605 err = mlx5_core_modify_sq(dev, in, inlen); 2606 if (err) 2607 goto out; 2608 2609 sq->state = new_state; 2610 2611 out: 2612 kvfree(in); 2613 return err; 2614 } 2615 2616 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2617 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2618 u8 tx_affinity) 2619 { 2620 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 2621 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 2622 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 2623 int modify_rq = !!qp->rq.wqe_cnt; 2624 int modify_sq = !!qp->sq.wqe_cnt; 2625 int rq_state; 2626 int sq_state; 2627 int err; 2628 2629 switch (raw_qp_param->operation) { 2630 case MLX5_CMD_OP_RST2INIT_QP: 2631 rq_state = MLX5_RQC_STATE_RDY; 2632 sq_state = MLX5_SQC_STATE_RDY; 2633 break; 2634 case MLX5_CMD_OP_2ERR_QP: 2635 rq_state = MLX5_RQC_STATE_ERR; 2636 sq_state = MLX5_SQC_STATE_ERR; 2637 break; 2638 case MLX5_CMD_OP_2RST_QP: 2639 rq_state = MLX5_RQC_STATE_RST; 2640 sq_state = MLX5_SQC_STATE_RST; 2641 break; 2642 case MLX5_CMD_OP_RTR2RTS_QP: 2643 case MLX5_CMD_OP_RTS2RTS_QP: 2644 return raw_qp_param->set_mask ? -EINVAL : 0; 2645 case MLX5_CMD_OP_INIT2INIT_QP: 2646 case MLX5_CMD_OP_INIT2RTR_QP: 2647 if (raw_qp_param->set_mask) 2648 return -EINVAL; 2649 else 2650 return 0; 2651 default: 2652 WARN_ON(1); 2653 return -EINVAL; 2654 } 2655 2656 if (modify_rq) { 2657 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param, 2658 qp->ibqp.pd); 2659 if (err) 2660 return err; 2661 } 2662 2663 if (modify_sq) { 2664 if (tx_affinity) { 2665 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 2666 tx_affinity, 2667 qp->ibqp.pd); 2668 if (err) 2669 return err; 2670 } 2671 2672 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, qp->ibqp.pd); 2673 } 2674 2675 return 0; 2676 } 2677 2678 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 2679 const struct ib_qp_attr *attr, int attr_mask, 2680 enum ib_qp_state cur_state, enum ib_qp_state new_state) 2681 { 2682 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 2683 [MLX5_QP_STATE_RST] = { 2684 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2685 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2686 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 2687 }, 2688 [MLX5_QP_STATE_INIT] = { 2689 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2690 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2691 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 2692 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 2693 }, 2694 [MLX5_QP_STATE_RTR] = { 2695 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2696 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2697 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 2698 }, 2699 [MLX5_QP_STATE_RTS] = { 2700 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2701 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2702 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 2703 }, 2704 [MLX5_QP_STATE_SQD] = { 2705 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2706 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2707 }, 2708 [MLX5_QP_STATE_SQER] = { 2709 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2710 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2711 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 2712 }, 2713 [MLX5_QP_STATE_ERR] = { 2714 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2715 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2716 } 2717 }; 2718 2719 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2720 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2721 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 2722 struct mlx5_ib_cq *send_cq, *recv_cq; 2723 struct mlx5_qp_context *context; 2724 struct mlx5_ib_pd *pd; 2725 struct mlx5_ib_port *mibport = NULL; 2726 enum mlx5_qp_state mlx5_cur, mlx5_new; 2727 enum mlx5_qp_optpar optpar; 2728 int mlx5_st; 2729 int err; 2730 u16 op; 2731 2732 context = kzalloc(sizeof(*context), GFP_KERNEL); 2733 if (!context) 2734 return -ENOMEM; 2735 2736 err = to_mlx5_st(ibqp->qp_type); 2737 if (err < 0) { 2738 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type); 2739 goto out; 2740 } 2741 2742 context->flags = cpu_to_be32(err << 16); 2743 2744 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 2745 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2746 } else { 2747 switch (attr->path_mig_state) { 2748 case IB_MIG_MIGRATED: 2749 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2750 break; 2751 case IB_MIG_REARM: 2752 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 2753 break; 2754 case IB_MIG_ARMED: 2755 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 2756 break; 2757 } 2758 } 2759 2760 if (is_sqp(ibqp->qp_type)) { 2761 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 2762 } else if (ibqp->qp_type == IB_QPT_UD || 2763 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 2764 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 2765 } else if (attr_mask & IB_QP_PATH_MTU) { 2766 if (attr->path_mtu < IB_MTU_256 || 2767 attr->path_mtu > IB_MTU_4096) { 2768 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 2769 err = -EINVAL; 2770 goto out; 2771 } 2772 context->mtu_msgmax = (attr->path_mtu << 5) | 2773 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); 2774 } 2775 2776 if (attr_mask & IB_QP_DEST_QPN) 2777 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 2778 2779 if (attr_mask & IB_QP_PKEY_INDEX) 2780 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index); 2781 2782 /* todo implement counter_index functionality */ 2783 2784 if (is_sqp(ibqp->qp_type)) 2785 context->pri_path.port = qp->port; 2786 2787 if (attr_mask & IB_QP_PORT) 2788 context->pri_path.port = attr->port_num; 2789 2790 if (attr_mask & IB_QP_AV) { 2791 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, 2792 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 2793 attr_mask, 0, attr, false); 2794 if (err) 2795 goto out; 2796 } 2797 2798 if (attr_mask & IB_QP_TIMEOUT) 2799 context->pri_path.ackto_lt |= attr->timeout << 3; 2800 2801 if (attr_mask & IB_QP_ALT_PATH) { 2802 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, 2803 &context->alt_path, 2804 attr->alt_port_num, 2805 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT, 2806 0, attr, true); 2807 if (err) 2808 goto out; 2809 } 2810 2811 pd = get_pd(qp); 2812 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2813 &send_cq, &recv_cq); 2814 2815 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 2816 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 2817 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 2818 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 2819 2820 if (attr_mask & IB_QP_RNR_RETRY) 2821 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 2822 2823 if (attr_mask & IB_QP_RETRY_CNT) 2824 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 2825 2826 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2827 if (attr->max_rd_atomic) 2828 context->params1 |= 2829 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 2830 } 2831 2832 if (attr_mask & IB_QP_SQ_PSN) 2833 context->next_send_psn = cpu_to_be32(attr->sq_psn); 2834 2835 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2836 if (attr->max_dest_rd_atomic) 2837 context->params2 |= 2838 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 2839 } 2840 2841 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 2842 __be32 access_flags; 2843 2844 err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags); 2845 if (err) 2846 goto out; 2847 2848 context->params2 |= access_flags; 2849 } 2850 2851 if (attr_mask & IB_QP_MIN_RNR_TIMER) 2852 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 2853 2854 if (attr_mask & IB_QP_RQ_PSN) 2855 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 2856 2857 if (attr_mask & IB_QP_QKEY) 2858 context->qkey = cpu_to_be32(attr->qkey); 2859 2860 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2861 context->db_rec_addr = cpu_to_be64(qp->db.dma); 2862 2863 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2864 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 2865 qp->port) - 1; 2866 mibport = &dev->port[port_num]; 2867 context->qp_counter_set_usr_page |= 2868 cpu_to_be32((u32)(mibport->q_cnt_id) << 24); 2869 } 2870 2871 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2872 context->sq_crq_size |= cpu_to_be16(1 << 4); 2873 2874 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 2875 context->deth_sqpn = cpu_to_be32(1); 2876 2877 mlx5_cur = to_mlx5_state(cur_state); 2878 mlx5_new = to_mlx5_state(new_state); 2879 mlx5_st = to_mlx5_st(ibqp->qp_type); 2880 if (mlx5_st < 0) 2881 goto out; 2882 2883 /* If moving to a reset or error state, we must disable page faults on 2884 * this QP and flush all current page faults. Otherwise a stale page 2885 * fault may attempt to work on this QP after it is reset and moved 2886 * again to RTS, and may cause the driver and the device to get out of 2887 * sync. */ 2888 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR && 2889 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) && 2890 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET)) 2891 mlx5_ib_qp_disable_pagefaults(qp); 2892 2893 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 2894 !optab[mlx5_cur][mlx5_new]) 2895 goto out; 2896 2897 op = optab[mlx5_cur][mlx5_new]; 2898 optpar = ib_mask_to_mlx5_opt(attr_mask); 2899 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 2900 2901 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 2902 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 2903 2904 raw_qp_param.operation = op; 2905 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2906 raw_qp_param.rq_q_ctr_id = mibport->q_cnt_id; 2907 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 2908 } 2909 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2910 } else { 2911 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context, 2912 &base->mqp); 2913 } 2914 2915 if (err) 2916 goto out; 2917 2918 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT && 2919 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET)) 2920 mlx5_ib_qp_enable_pagefaults(qp); 2921 2922 qp->state = new_state; 2923 2924 if (attr_mask & IB_QP_ACCESS_FLAGS) 2925 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 2926 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2927 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 2928 if (attr_mask & IB_QP_PORT) 2929 qp->port = attr->port_num; 2930 if (attr_mask & IB_QP_ALT_PATH) 2931 qp->trans_qp.alt_port = attr->alt_port_num; 2932 2933 /* 2934 * If we moved a kernel QP to RESET, clean up all old CQ 2935 * entries and reinitialize the QP. 2936 */ 2937 if (new_state == IB_QPS_RESET && !ibqp->uobject) { 2938 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2939 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 2940 if (send_cq != recv_cq) 2941 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 2942 2943 qp->rq.head = 0; 2944 qp->rq.tail = 0; 2945 qp->sq.head = 0; 2946 qp->sq.tail = 0; 2947 qp->sq.cur_post = 0; 2948 qp->sq.last_poll = 0; 2949 qp->db.db[MLX5_RCV_DBR] = 0; 2950 qp->db.db[MLX5_SND_DBR] = 0; 2951 } 2952 2953 out: 2954 kfree(context); 2955 return err; 2956 } 2957 2958 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2959 int attr_mask, struct ib_udata *udata) 2960 { 2961 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2962 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2963 enum ib_qp_type qp_type; 2964 enum ib_qp_state cur_state, new_state; 2965 int err = -EINVAL; 2966 int port; 2967 2968 if (ibqp->rwq_ind_tbl) 2969 return -ENOSYS; 2970 2971 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 2972 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 2973 2974 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? 2975 IB_QPT_GSI : ibqp->qp_type; 2976 2977 mutex_lock(&qp->mutex); 2978 2979 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 2980 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 2981 2982 if (qp_type != MLX5_IB_QPT_REG_UMR && 2983 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask)) { 2984 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 2985 cur_state, new_state, ibqp->qp_type, attr_mask); 2986 goto out; 2987 } 2988 2989 if ((attr_mask & IB_QP_PORT) && 2990 (attr->port_num == 0 || 2991 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) { 2992 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 2993 attr->port_num, dev->num_ports); 2994 goto out; 2995 } 2996 2997 if (attr_mask & IB_QP_PKEY_INDEX) { 2998 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2999 if (attr->pkey_index >= 3000 dev->mdev->port_caps[port - 1].pkey_table_len) { 3001 mlx5_ib_dbg(dev, "invalid pkey index %d\n", 3002 attr->pkey_index); 3003 goto out; 3004 } 3005 } 3006 3007 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 3008 attr->max_rd_atomic > 3009 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 3010 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 3011 attr->max_rd_atomic); 3012 goto out; 3013 } 3014 3015 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 3016 attr->max_dest_rd_atomic > 3017 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 3018 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 3019 attr->max_dest_rd_atomic); 3020 goto out; 3021 } 3022 3023 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 3024 err = 0; 3025 goto out; 3026 } 3027 3028 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state); 3029 3030 out: 3031 mutex_unlock(&qp->mutex); 3032 return err; 3033 } 3034 3035 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 3036 { 3037 struct mlx5_ib_cq *cq; 3038 unsigned cur; 3039 3040 cur = wq->head - wq->tail; 3041 if (likely(cur + nreq < wq->max_post)) 3042 return 0; 3043 3044 cq = to_mcq(ib_cq); 3045 spin_lock(&cq->lock); 3046 cur = wq->head - wq->tail; 3047 spin_unlock(&cq->lock); 3048 3049 return cur + nreq >= wq->max_post; 3050 } 3051 3052 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 3053 u64 remote_addr, u32 rkey) 3054 { 3055 rseg->raddr = cpu_to_be64(remote_addr); 3056 rseg->rkey = cpu_to_be32(rkey); 3057 rseg->reserved = 0; 3058 } 3059 3060 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg, 3061 const struct ib_send_wr *wr, void *qend, 3062 struct mlx5_ib_qp *qp, int *size) 3063 { 3064 void *seg = eseg; 3065 3066 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); 3067 3068 if (wr->send_flags & IB_SEND_IP_CSUM) 3069 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | 3070 MLX5_ETH_WQE_L4_CSUM; 3071 3072 seg += sizeof(struct mlx5_wqe_eth_seg); 3073 *size += sizeof(struct mlx5_wqe_eth_seg) / 16; 3074 3075 if (wr->opcode == IB_WR_LSO) { 3076 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr); 3077 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start); 3078 u64 left, leftlen, copysz; 3079 void *pdata = ud_wr->header; 3080 3081 left = ud_wr->hlen; 3082 eseg->mss = cpu_to_be16(ud_wr->mss); 3083 eseg->inline_hdr_sz = cpu_to_be16(left); 3084 3085 /* 3086 * check if there is space till the end of queue, if yes, 3087 * copy all in one shot, otherwise copy till the end of queue, 3088 * rollback and than the copy the left 3089 */ 3090 leftlen = qend - (void *)eseg->inline_hdr_start; 3091 copysz = min_t(u64, leftlen, left); 3092 3093 memcpy(seg - size_of_inl_hdr_start, pdata, copysz); 3094 3095 if (likely(copysz > size_of_inl_hdr_start)) { 3096 seg += ALIGN(copysz - size_of_inl_hdr_start, 16); 3097 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16; 3098 } 3099 3100 if (unlikely(copysz < left)) { /* the last wqe in the queue */ 3101 seg = mlx5_get_send_wqe(qp, 0); 3102 left -= copysz; 3103 pdata += copysz; 3104 memcpy(seg, pdata, left); 3105 seg += ALIGN(left, 16); 3106 *size += ALIGN(left, 16) / 16; 3107 } 3108 } 3109 3110 return seg; 3111 } 3112 3113 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 3114 const struct ib_send_wr *wr) 3115 { 3116 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); 3117 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); 3118 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); 3119 } 3120 3121 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 3122 { 3123 dseg->byte_count = cpu_to_be32(sg->length); 3124 dseg->lkey = cpu_to_be32(sg->lkey); 3125 dseg->addr = cpu_to_be64(sg->addr); 3126 } 3127 3128 static __be16 get_klm_octo(int npages) 3129 { 3130 return cpu_to_be16(ALIGN(npages, 8) / 2); 3131 } 3132 3133 static __be64 frwr_mkey_mask(void) 3134 { 3135 u64 result; 3136 3137 result = MLX5_MKEY_MASK_LEN | 3138 MLX5_MKEY_MASK_PAGE_SIZE | 3139 MLX5_MKEY_MASK_START_ADDR | 3140 MLX5_MKEY_MASK_EN_RINVAL | 3141 MLX5_MKEY_MASK_KEY | 3142 MLX5_MKEY_MASK_LR | 3143 MLX5_MKEY_MASK_LW | 3144 MLX5_MKEY_MASK_RR | 3145 MLX5_MKEY_MASK_RW | 3146 MLX5_MKEY_MASK_A | 3147 MLX5_MKEY_MASK_SMALL_FENCE | 3148 MLX5_MKEY_MASK_FREE; 3149 3150 return cpu_to_be64(result); 3151 } 3152 3153 static __be64 sig_mkey_mask(void) 3154 { 3155 u64 result; 3156 3157 result = MLX5_MKEY_MASK_LEN | 3158 MLX5_MKEY_MASK_PAGE_SIZE | 3159 MLX5_MKEY_MASK_START_ADDR | 3160 MLX5_MKEY_MASK_EN_SIGERR | 3161 MLX5_MKEY_MASK_EN_RINVAL | 3162 MLX5_MKEY_MASK_KEY | 3163 MLX5_MKEY_MASK_LR | 3164 MLX5_MKEY_MASK_LW | 3165 MLX5_MKEY_MASK_RR | 3166 MLX5_MKEY_MASK_RW | 3167 MLX5_MKEY_MASK_SMALL_FENCE | 3168 MLX5_MKEY_MASK_FREE | 3169 MLX5_MKEY_MASK_BSF_EN; 3170 3171 return cpu_to_be64(result); 3172 } 3173 3174 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, 3175 struct mlx5_ib_mr *mr) 3176 { 3177 int ndescs = mr->ndescs; 3178 3179 memset(umr, 0, sizeof(*umr)); 3180 3181 if (mr->access_mode == MLX5_ACCESS_MODE_KLM) 3182 /* KLMs take twice the size of MTTs */ 3183 ndescs *= 2; 3184 3185 umr->flags = MLX5_UMR_CHECK_NOT_FREE; 3186 umr->klm_octowords = get_klm_octo(ndescs); 3187 umr->mkey_mask = frwr_mkey_mask(); 3188 } 3189 3190 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) 3191 { 3192 memset(umr, 0, sizeof(*umr)); 3193 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 3194 umr->flags = 1 << 7; 3195 } 3196 3197 static __be64 get_umr_reg_mr_mask(void) 3198 { 3199 u64 result; 3200 3201 result = MLX5_MKEY_MASK_LEN | 3202 MLX5_MKEY_MASK_PAGE_SIZE | 3203 MLX5_MKEY_MASK_START_ADDR | 3204 MLX5_MKEY_MASK_PD | 3205 MLX5_MKEY_MASK_LR | 3206 MLX5_MKEY_MASK_LW | 3207 MLX5_MKEY_MASK_KEY | 3208 MLX5_MKEY_MASK_RR | 3209 MLX5_MKEY_MASK_RW | 3210 MLX5_MKEY_MASK_A | 3211 MLX5_MKEY_MASK_FREE; 3212 3213 return cpu_to_be64(result); 3214 } 3215 3216 static __be64 get_umr_unreg_mr_mask(void) 3217 { 3218 u64 result; 3219 3220 result = MLX5_MKEY_MASK_FREE; 3221 3222 return cpu_to_be64(result); 3223 } 3224 3225 static __be64 get_umr_update_mtt_mask(void) 3226 { 3227 u64 result; 3228 3229 result = MLX5_MKEY_MASK_FREE; 3230 3231 return cpu_to_be64(result); 3232 } 3233 3234 static __be64 get_umr_update_translation_mask(void) 3235 { 3236 u64 result; 3237 3238 result = MLX5_MKEY_MASK_LEN | 3239 MLX5_MKEY_MASK_PAGE_SIZE | 3240 MLX5_MKEY_MASK_START_ADDR | 3241 MLX5_MKEY_MASK_KEY | 3242 MLX5_MKEY_MASK_FREE; 3243 3244 return cpu_to_be64(result); 3245 } 3246 3247 static __be64 get_umr_update_access_mask(void) 3248 { 3249 u64 result; 3250 3251 result = MLX5_MKEY_MASK_LW | 3252 MLX5_MKEY_MASK_RR | 3253 MLX5_MKEY_MASK_RW | 3254 MLX5_MKEY_MASK_A | 3255 MLX5_MKEY_MASK_KEY | 3256 MLX5_MKEY_MASK_FREE; 3257 3258 return cpu_to_be64(result); 3259 } 3260 3261 static __be64 get_umr_update_pd_mask(void) 3262 { 3263 u64 result; 3264 3265 result = MLX5_MKEY_MASK_PD | 3266 MLX5_MKEY_MASK_KEY | 3267 MLX5_MKEY_MASK_FREE; 3268 3269 return cpu_to_be64(result); 3270 } 3271 3272 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 3273 const struct ib_send_wr *wr) 3274 { 3275 const struct mlx5_umr_wr *umrwr = umr_wr(wr); 3276 3277 memset(umr, 0, sizeof(*umr)); 3278 3279 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) 3280 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */ 3281 else 3282 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */ 3283 3284 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) { 3285 umr->klm_octowords = get_klm_octo(umrwr->npages); 3286 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) { 3287 umr->mkey_mask = get_umr_update_mtt_mask(); 3288 umr->bsf_octowords = get_klm_octo(umrwr->target.offset); 3289 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 3290 } 3291 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION) 3292 umr->mkey_mask |= get_umr_update_translation_mask(); 3293 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_ACCESS) 3294 umr->mkey_mask |= get_umr_update_access_mask(); 3295 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD) 3296 umr->mkey_mask |= get_umr_update_pd_mask(); 3297 if (!umr->mkey_mask) 3298 umr->mkey_mask = get_umr_reg_mr_mask(); 3299 } else { 3300 umr->mkey_mask = get_umr_unreg_mr_mask(); 3301 } 3302 3303 if (!wr->num_sge) 3304 umr->flags |= MLX5_UMR_INLINE; 3305 } 3306 3307 static u8 get_umr_flags(int acc) 3308 { 3309 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 3310 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 3311 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 3312 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 3313 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 3314 } 3315 3316 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, 3317 struct mlx5_ib_mr *mr, 3318 u32 key, int access) 3319 { 3320 int ndescs = ALIGN(mr->ndescs, 8) >> 1; 3321 3322 memset(seg, 0, sizeof(*seg)); 3323 3324 if (mr->access_mode == MLX5_ACCESS_MODE_MTT) 3325 seg->log2_page_size = ilog2(mr->ibmr.page_size); 3326 else if (mr->access_mode == MLX5_ACCESS_MODE_KLM) 3327 /* KLMs take twice the size of MTTs */ 3328 ndescs *= 2; 3329 3330 seg->flags = get_umr_flags(access) | mr->access_mode; 3331 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); 3332 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 3333 seg->start_addr = cpu_to_be64(mr->ibmr.iova); 3334 seg->len = cpu_to_be64(mr->ibmr.length); 3335 seg->xlt_oct_size = cpu_to_be32(ndescs); 3336 } 3337 3338 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) 3339 { 3340 memset(seg, 0, sizeof(*seg)); 3341 seg->status = MLX5_MKEY_STATUS_FREE; 3342 } 3343 3344 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, const struct ib_send_wr *wr) 3345 { 3346 const struct mlx5_umr_wr *umrwr = umr_wr(wr); 3347 3348 memset(seg, 0, sizeof(*seg)); 3349 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) { 3350 seg->status = MLX5_MKEY_STATUS_FREE; 3351 return; 3352 } 3353 3354 seg->flags = convert_access(umrwr->access_flags); 3355 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) { 3356 if (umrwr->pd) 3357 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); 3358 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr); 3359 } 3360 seg->len = cpu_to_be64(umrwr->length); 3361 seg->log2_page_size = umrwr->page_shift; 3362 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 3363 mlx5_mkey_variant(umrwr->mkey)); 3364 } 3365 3366 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, 3367 struct mlx5_ib_mr *mr, 3368 struct mlx5_ib_pd *pd) 3369 { 3370 int bcount = mr->desc_size * mr->ndescs; 3371 3372 dseg->addr = cpu_to_be64(mr->desc_map); 3373 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); 3374 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); 3375 } 3376 3377 static __be32 send_ieth(const struct ib_send_wr *wr) 3378 { 3379 switch (wr->opcode) { 3380 case IB_WR_SEND_WITH_IMM: 3381 case IB_WR_RDMA_WRITE_WITH_IMM: 3382 return wr->ex.imm_data; 3383 3384 case IB_WR_SEND_WITH_INV: 3385 return cpu_to_be32(wr->ex.invalidate_rkey); 3386 3387 default: 3388 return 0; 3389 } 3390 } 3391 3392 static u8 calc_sig(void *wqe, int size) 3393 { 3394 u8 *p = wqe; 3395 u8 res = 0; 3396 int i; 3397 3398 for (i = 0; i < size; i++) 3399 res ^= p[i]; 3400 3401 return ~res; 3402 } 3403 3404 static u8 wq_sig(void *wqe) 3405 { 3406 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 3407 } 3408 3409 static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr, 3410 void *wqe, int *sz) 3411 { 3412 struct mlx5_wqe_inline_seg *seg; 3413 void *qend = qp->sq.qend; 3414 void *addr; 3415 int inl = 0; 3416 int copy; 3417 int len; 3418 int i; 3419 3420 seg = wqe; 3421 wqe += sizeof(*seg); 3422 for (i = 0; i < wr->num_sge; i++) { 3423 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 3424 len = wr->sg_list[i].length; 3425 inl += len; 3426 3427 if (unlikely(inl > qp->max_inline_data)) 3428 return -ENOMEM; 3429 3430 if (unlikely(wqe + len > qend)) { 3431 copy = qend - wqe; 3432 memcpy(wqe, addr, copy); 3433 addr += copy; 3434 len -= copy; 3435 wqe = mlx5_get_send_wqe(qp, 0); 3436 } 3437 memcpy(wqe, addr, len); 3438 wqe += len; 3439 } 3440 3441 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 3442 3443 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 3444 3445 return 0; 3446 } 3447 3448 static u16 prot_field_size(enum ib_signature_type type) 3449 { 3450 switch (type) { 3451 case IB_SIG_TYPE_T10_DIF: 3452 return MLX5_DIF_SIZE; 3453 default: 3454 return 0; 3455 } 3456 } 3457 3458 static u8 bs_selector(int block_size) 3459 { 3460 switch (block_size) { 3461 case 512: return 0x1; 3462 case 520: return 0x2; 3463 case 4096: return 0x3; 3464 case 4160: return 0x4; 3465 case 1073741824: return 0x5; 3466 default: return 0; 3467 } 3468 } 3469 3470 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, 3471 struct mlx5_bsf_inl *inl) 3472 { 3473 /* Valid inline section and allow BSF refresh */ 3474 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | 3475 MLX5_BSF_REFRESH_DIF); 3476 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); 3477 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); 3478 /* repeating block */ 3479 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; 3480 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? 3481 MLX5_DIF_CRC : MLX5_DIF_IPCS; 3482 3483 if (domain->sig.dif.ref_remap) 3484 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; 3485 3486 if (domain->sig.dif.app_escape) { 3487 if (domain->sig.dif.ref_escape) 3488 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; 3489 else 3490 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; 3491 } 3492 3493 inl->dif_app_bitmask_check = 3494 cpu_to_be16(domain->sig.dif.apptag_check_mask); 3495 } 3496 3497 static int mlx5_set_bsf(struct ib_mr *sig_mr, 3498 struct ib_sig_attrs *sig_attrs, 3499 struct mlx5_bsf *bsf, u32 data_size) 3500 { 3501 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 3502 struct mlx5_bsf_basic *basic = &bsf->basic; 3503 struct ib_sig_domain *mem = &sig_attrs->mem; 3504 struct ib_sig_domain *wire = &sig_attrs->wire; 3505 3506 memset(bsf, 0, sizeof(*bsf)); 3507 3508 /* Basic + Extended + Inline */ 3509 basic->bsf_size_sbs = 1 << 7; 3510 /* Input domain check byte mask */ 3511 basic->check_byte_mask = sig_attrs->check_mask; 3512 basic->raw_data_size = cpu_to_be32(data_size); 3513 3514 /* Memory domain */ 3515 switch (sig_attrs->mem.sig_type) { 3516 case IB_SIG_TYPE_NONE: 3517 break; 3518 case IB_SIG_TYPE_T10_DIF: 3519 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 3520 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); 3521 mlx5_fill_inl_bsf(mem, &bsf->m_inl); 3522 break; 3523 default: 3524 return -EINVAL; 3525 } 3526 3527 /* Wire domain */ 3528 switch (sig_attrs->wire.sig_type) { 3529 case IB_SIG_TYPE_NONE: 3530 break; 3531 case IB_SIG_TYPE_T10_DIF: 3532 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 3533 mem->sig_type == wire->sig_type) { 3534 /* Same block structure */ 3535 basic->bsf_size_sbs |= 1 << 4; 3536 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 3537 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 3538 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 3539 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; 3540 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) 3541 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; 3542 } else 3543 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 3544 3545 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); 3546 mlx5_fill_inl_bsf(wire, &bsf->w_inl); 3547 break; 3548 default: 3549 return -EINVAL; 3550 } 3551 3552 return 0; 3553 } 3554 3555 static int set_sig_data_segment(const struct ib_sig_handover_wr *wr, 3556 struct mlx5_ib_qp *qp, void **seg, int *size) 3557 { 3558 struct ib_sig_attrs *sig_attrs = wr->sig_attrs; 3559 struct ib_mr *sig_mr = wr->sig_mr; 3560 struct mlx5_bsf *bsf; 3561 u32 data_len = wr->wr.sg_list->length; 3562 u32 data_key = wr->wr.sg_list->lkey; 3563 u64 data_va = wr->wr.sg_list->addr; 3564 int ret; 3565 int wqe_size; 3566 3567 if (!wr->prot || 3568 (data_key == wr->prot->lkey && 3569 data_va == wr->prot->addr && 3570 data_len == wr->prot->length)) { 3571 /** 3572 * Source domain doesn't contain signature information 3573 * or data and protection are interleaved in memory. 3574 * So need construct: 3575 * ------------------ 3576 * | data_klm | 3577 * ------------------ 3578 * | BSF | 3579 * ------------------ 3580 **/ 3581 struct mlx5_klm *data_klm = *seg; 3582 3583 data_klm->bcount = cpu_to_be32(data_len); 3584 data_klm->key = cpu_to_be32(data_key); 3585 data_klm->va = cpu_to_be64(data_va); 3586 wqe_size = ALIGN(sizeof(*data_klm), 64); 3587 } else { 3588 /** 3589 * Source domain contains signature information 3590 * So need construct a strided block format: 3591 * --------------------------- 3592 * | stride_block_ctrl | 3593 * --------------------------- 3594 * | data_klm | 3595 * --------------------------- 3596 * | prot_klm | 3597 * --------------------------- 3598 * | BSF | 3599 * --------------------------- 3600 **/ 3601 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 3602 struct mlx5_stride_block_entry *data_sentry; 3603 struct mlx5_stride_block_entry *prot_sentry; 3604 u32 prot_key = wr->prot->lkey; 3605 u64 prot_va = wr->prot->addr; 3606 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 3607 int prot_size; 3608 3609 sblock_ctrl = *seg; 3610 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 3611 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 3612 3613 prot_size = prot_field_size(sig_attrs->mem.sig_type); 3614 if (!prot_size) { 3615 pr_err("Bad block size given: %u\n", block_size); 3616 return -EINVAL; 3617 } 3618 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 3619 prot_size); 3620 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 3621 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 3622 sblock_ctrl->num_entries = cpu_to_be16(2); 3623 3624 data_sentry->bcount = cpu_to_be16(block_size); 3625 data_sentry->key = cpu_to_be32(data_key); 3626 data_sentry->va = cpu_to_be64(data_va); 3627 data_sentry->stride = cpu_to_be16(block_size); 3628 3629 prot_sentry->bcount = cpu_to_be16(prot_size); 3630 prot_sentry->key = cpu_to_be32(prot_key); 3631 prot_sentry->va = cpu_to_be64(prot_va); 3632 prot_sentry->stride = cpu_to_be16(prot_size); 3633 3634 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 3635 sizeof(*prot_sentry), 64); 3636 } 3637 3638 *seg += wqe_size; 3639 *size += wqe_size / 16; 3640 if (unlikely((*seg == qp->sq.qend))) 3641 *seg = mlx5_get_send_wqe(qp, 0); 3642 3643 bsf = *seg; 3644 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 3645 if (ret) 3646 return -EINVAL; 3647 3648 *seg += sizeof(*bsf); 3649 *size += sizeof(*bsf) / 16; 3650 if (unlikely((*seg == qp->sq.qend))) 3651 *seg = mlx5_get_send_wqe(qp, 0); 3652 3653 return 0; 3654 } 3655 3656 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 3657 const struct ib_sig_handover_wr *wr, u32 nelements, 3658 u32 length, u32 pdn) 3659 { 3660 struct ib_mr *sig_mr = wr->sig_mr; 3661 u32 sig_key = sig_mr->rkey; 3662 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 3663 3664 memset(seg, 0, sizeof(*seg)); 3665 3666 seg->flags = get_umr_flags(wr->access_flags) | 3667 MLX5_ACCESS_MODE_KLM; 3668 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 3669 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 3670 MLX5_MKEY_BSF_EN | pdn); 3671 seg->len = cpu_to_be64(length); 3672 seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements))); 3673 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 3674 } 3675 3676 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 3677 u32 nelements) 3678 { 3679 memset(umr, 0, sizeof(*umr)); 3680 3681 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 3682 umr->klm_octowords = get_klm_octo(nelements); 3683 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 3684 umr->mkey_mask = sig_mkey_mask(); 3685 } 3686 3687 3688 static int set_sig_umr_wr(const struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp, 3689 void **seg, int *size) 3690 { 3691 const struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr); 3692 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr); 3693 u32 pdn = get_pd(qp)->pdn; 3694 u32 klm_oct_size; 3695 int region_len, ret; 3696 3697 if (unlikely(wr->wr.num_sge != 1) || 3698 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) || 3699 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || 3700 unlikely(!sig_mr->sig->sig_status_checked)) 3701 return -EINVAL; 3702 3703 /* length of the protected region, data + protection */ 3704 region_len = wr->wr.sg_list->length; 3705 if (wr->prot && 3706 (wr->prot->lkey != wr->wr.sg_list->lkey || 3707 wr->prot->addr != wr->wr.sg_list->addr || 3708 wr->prot->length != wr->wr.sg_list->length)) 3709 region_len += wr->prot->length; 3710 3711 /** 3712 * KLM octoword size - if protection was provided 3713 * then we use strided block format (3 octowords), 3714 * else we use single KLM (1 octoword) 3715 **/ 3716 klm_oct_size = wr->prot ? 3 : 1; 3717 3718 set_sig_umr_segment(*seg, klm_oct_size); 3719 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3720 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3721 if (unlikely((*seg == qp->sq.qend))) 3722 *seg = mlx5_get_send_wqe(qp, 0); 3723 3724 set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn); 3725 *seg += sizeof(struct mlx5_mkey_seg); 3726 *size += sizeof(struct mlx5_mkey_seg) / 16; 3727 if (unlikely((*seg == qp->sq.qend))) 3728 *seg = mlx5_get_send_wqe(qp, 0); 3729 3730 ret = set_sig_data_segment(wr, qp, seg, size); 3731 if (ret) 3732 return ret; 3733 3734 sig_mr->sig->sig_status_checked = false; 3735 return 0; 3736 } 3737 3738 static int set_psv_wr(struct ib_sig_domain *domain, 3739 u32 psv_idx, void **seg, int *size) 3740 { 3741 struct mlx5_seg_set_psv *psv_seg = *seg; 3742 3743 memset(psv_seg, 0, sizeof(*psv_seg)); 3744 psv_seg->psv_num = cpu_to_be32(psv_idx); 3745 switch (domain->sig_type) { 3746 case IB_SIG_TYPE_NONE: 3747 break; 3748 case IB_SIG_TYPE_T10_DIF: 3749 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 3750 domain->sig.dif.app_tag); 3751 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 3752 break; 3753 default: 3754 pr_err("Bad signature type given.\n"); 3755 return 1; 3756 } 3757 3758 *seg += sizeof(*psv_seg); 3759 *size += sizeof(*psv_seg) / 16; 3760 3761 return 0; 3762 } 3763 3764 static int set_reg_wr(struct mlx5_ib_qp *qp, 3765 const struct ib_reg_wr *wr, 3766 void **seg, int *size) 3767 { 3768 struct mlx5_ib_mr *mr = to_mmr(wr->mr); 3769 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); 3770 3771 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { 3772 mlx5_ib_warn(to_mdev(qp->ibqp.device), 3773 "Invalid IB_SEND_INLINE send flag\n"); 3774 return -EINVAL; 3775 } 3776 3777 set_reg_umr_seg(*seg, mr); 3778 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3779 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3780 if (unlikely((*seg == qp->sq.qend))) 3781 *seg = mlx5_get_send_wqe(qp, 0); 3782 3783 set_reg_mkey_seg(*seg, mr, wr->key, wr->access); 3784 *seg += sizeof(struct mlx5_mkey_seg); 3785 *size += sizeof(struct mlx5_mkey_seg) / 16; 3786 if (unlikely((*seg == qp->sq.qend))) 3787 *seg = mlx5_get_send_wqe(qp, 0); 3788 3789 set_reg_data_seg(*seg, mr, pd); 3790 *seg += sizeof(struct mlx5_wqe_data_seg); 3791 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 3792 3793 return 0; 3794 } 3795 3796 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size) 3797 { 3798 set_linv_umr_seg(*seg); 3799 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3800 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3801 if (unlikely((*seg == qp->sq.qend))) 3802 *seg = mlx5_get_send_wqe(qp, 0); 3803 set_linv_mkey_seg(*seg); 3804 *seg += sizeof(struct mlx5_mkey_seg); 3805 *size += sizeof(struct mlx5_mkey_seg) / 16; 3806 if (unlikely((*seg == qp->sq.qend))) 3807 *seg = mlx5_get_send_wqe(qp, 0); 3808 } 3809 3810 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16) 3811 { 3812 __be32 *p = NULL; 3813 int tidx = idx; 3814 int i, j; 3815 3816 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx)); 3817 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 3818 if ((i & 0xf) == 0) { 3819 void *buf = mlx5_get_send_wqe(qp, tidx); 3820 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1); 3821 p = buf; 3822 j = 0; 3823 } 3824 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 3825 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 3826 be32_to_cpu(p[j + 3])); 3827 } 3828 } 3829 3830 static u8 get_fence(u8 fence, const struct ib_send_wr *wr) 3831 { 3832 if (unlikely(wr->opcode == IB_WR_LOCAL_INV && 3833 wr->send_flags & IB_SEND_FENCE)) 3834 return MLX5_FENCE_MODE_STRONG_ORDERING; 3835 3836 if (unlikely(fence)) { 3837 if (wr->send_flags & IB_SEND_FENCE) 3838 return MLX5_FENCE_MODE_SMALL_AND_FENCE; 3839 else 3840 return fence; 3841 } else if (unlikely(wr->send_flags & IB_SEND_FENCE)) { 3842 return MLX5_FENCE_MODE_FENCE; 3843 } 3844 3845 return 0; 3846 } 3847 3848 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 3849 struct mlx5_wqe_ctrl_seg **ctrl, 3850 const struct ib_send_wr *wr, unsigned *idx, 3851 int *size, int nreq, int send_flags) 3852 { 3853 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) 3854 return -ENOMEM; 3855 3856 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 3857 *seg = mlx5_get_send_wqe(qp, *idx); 3858 *ctrl = *seg; 3859 *(uint32_t *)(*seg + 8) = 0; 3860 (*ctrl)->imm = send_ieth(wr); 3861 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 3862 (send_flags & IB_SEND_SIGNALED ? 3863 MLX5_WQE_CTRL_CQ_UPDATE : 0) | 3864 (send_flags & IB_SEND_SOLICITED ? 3865 MLX5_WQE_CTRL_SOLICITED : 0); 3866 3867 *seg += sizeof(**ctrl); 3868 *size = sizeof(**ctrl) / 16; 3869 3870 return 0; 3871 } 3872 3873 static void finish_wqe(struct mlx5_ib_qp *qp, 3874 struct mlx5_wqe_ctrl_seg *ctrl, 3875 u8 size, unsigned idx, u64 wr_id, 3876 int nreq, u8 fence, u8 next_fence, 3877 u32 mlx5_opcode) 3878 { 3879 u8 opmod = 0; 3880 3881 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 3882 mlx5_opcode | ((u32)opmod << 24)); 3883 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); 3884 ctrl->fm_ce_se |= fence; 3885 qp->fm_cache = next_fence; 3886 if (unlikely(qp->wq_sig)) 3887 ctrl->signature = wq_sig(ctrl); 3888 3889 qp->sq.wrid[idx] = wr_id; 3890 qp->sq.w_list[idx].opcode = mlx5_opcode; 3891 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 3892 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 3893 qp->sq.w_list[idx].next = qp->sq.cur_post; 3894 } 3895 3896 3897 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 3898 const struct ib_send_wr **bad_wr) 3899 { 3900 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 3901 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3902 struct mlx5_core_dev *mdev = dev->mdev; 3903 struct mlx5_ib_qp *qp; 3904 struct mlx5_ib_mr *mr; 3905 struct mlx5_wqe_data_seg *dpseg; 3906 struct mlx5_wqe_xrc_seg *xrc; 3907 struct mlx5_bf *bf; 3908 int uninitialized_var(size); 3909 void *qend; 3910 unsigned long flags; 3911 unsigned idx; 3912 int err = 0; 3913 int num_sge; 3914 void *seg; 3915 int nreq; 3916 int i; 3917 u8 next_fence = 0; 3918 u8 fence; 3919 3920 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 3921 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr); 3922 3923 qp = to_mqp(ibqp); 3924 bf = &qp->bf; 3925 qend = qp->sq.qend; 3926 3927 spin_lock_irqsave(&qp->sq.lock, flags); 3928 3929 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 3930 err = -EIO; 3931 *bad_wr = wr; 3932 nreq = 0; 3933 goto out; 3934 } 3935 3936 for (nreq = 0; wr; nreq++, wr = wr->next) { 3937 if (unlikely(wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { 3938 mlx5_ib_warn(dev, "\n"); 3939 err = -EINVAL; 3940 *bad_wr = wr; 3941 goto out; 3942 } 3943 3944 fence = qp->fm_cache; 3945 num_sge = wr->num_sge; 3946 if (unlikely(num_sge > qp->sq.max_gs)) { 3947 mlx5_ib_warn(dev, "\n"); 3948 err = -EINVAL; 3949 *bad_wr = wr; 3950 goto out; 3951 } 3952 3953 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq, wr->send_flags); 3954 if (err) { 3955 mlx5_ib_warn(dev, "\n"); 3956 err = -ENOMEM; 3957 *bad_wr = wr; 3958 goto out; 3959 } 3960 3961 switch (ibqp->qp_type) { 3962 case IB_QPT_XRC_INI: 3963 xrc = seg; 3964 seg += sizeof(*xrc); 3965 size += sizeof(*xrc) / 16; 3966 /* fall through */ 3967 case IB_QPT_RC: 3968 switch (wr->opcode) { 3969 case IB_WR_RDMA_READ: 3970 case IB_WR_RDMA_WRITE: 3971 case IB_WR_RDMA_WRITE_WITH_IMM: 3972 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 3973 rdma_wr(wr)->rkey); 3974 seg += sizeof(struct mlx5_wqe_raddr_seg); 3975 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 3976 break; 3977 3978 case IB_WR_ATOMIC_CMP_AND_SWP: 3979 case IB_WR_ATOMIC_FETCH_AND_ADD: 3980 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 3981 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 3982 err = -ENOSYS; 3983 *bad_wr = wr; 3984 goto out; 3985 3986 case IB_WR_LOCAL_INV: 3987 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 3988 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 3989 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 3990 set_linv_wr(qp, &seg, &size); 3991 num_sge = 0; 3992 break; 3993 3994 case IB_WR_REG_MR: 3995 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 3996 qp->sq.wr_data[idx] = IB_WR_REG_MR; 3997 ctrl->imm = cpu_to_be32(reg_wr(wr)->key); 3998 err = set_reg_wr(qp, reg_wr(wr), &seg, &size); 3999 if (err) { 4000 *bad_wr = wr; 4001 goto out; 4002 } 4003 num_sge = 0; 4004 break; 4005 4006 case IB_WR_REG_SIG_MR: 4007 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; 4008 mr = to_mmr(sig_handover_wr(wr)->sig_mr); 4009 4010 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 4011 err = set_sig_umr_wr(wr, qp, &seg, &size); 4012 if (err) { 4013 mlx5_ib_warn(dev, "\n"); 4014 *bad_wr = wr; 4015 goto out; 4016 } 4017 4018 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 4019 nreq, get_fence(fence, wr), 4020 next_fence, MLX5_OPCODE_UMR); 4021 /* 4022 * SET_PSV WQEs are not signaled and solicited 4023 * on error 4024 */ 4025 err = begin_wqe(qp, &seg, &ctrl, wr, 4026 &idx, &size, nreq, IB_SEND_SOLICITED); 4027 if (err) { 4028 mlx5_ib_warn(dev, "\n"); 4029 err = -ENOMEM; 4030 *bad_wr = wr; 4031 goto out; 4032 } 4033 4034 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem, 4035 mr->sig->psv_memory.psv_idx, &seg, 4036 &size); 4037 if (err) { 4038 mlx5_ib_warn(dev, "\n"); 4039 *bad_wr = wr; 4040 goto out; 4041 } 4042 4043 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 4044 nreq, get_fence(fence, wr), 4045 next_fence, MLX5_OPCODE_SET_PSV); 4046 err = begin_wqe(qp, &seg, &ctrl, wr, 4047 &idx, &size, nreq, wr->send_flags); 4048 if (err) { 4049 mlx5_ib_warn(dev, "\n"); 4050 err = -ENOMEM; 4051 *bad_wr = wr; 4052 goto out; 4053 } 4054 4055 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4056 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire, 4057 mr->sig->psv_wire.psv_idx, &seg, 4058 &size); 4059 if (err) { 4060 mlx5_ib_warn(dev, "\n"); 4061 *bad_wr = wr; 4062 goto out; 4063 } 4064 4065 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 4066 nreq, get_fence(fence, wr), 4067 next_fence, MLX5_OPCODE_SET_PSV); 4068 num_sge = 0; 4069 goto skip_psv; 4070 4071 default: 4072 break; 4073 } 4074 break; 4075 4076 case IB_QPT_UC: 4077 switch (wr->opcode) { 4078 case IB_WR_RDMA_WRITE: 4079 case IB_WR_RDMA_WRITE_WITH_IMM: 4080 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 4081 rdma_wr(wr)->rkey); 4082 seg += sizeof(struct mlx5_wqe_raddr_seg); 4083 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 4084 break; 4085 4086 default: 4087 break; 4088 } 4089 break; 4090 4091 case IB_QPT_SMI: 4092 case MLX5_IB_QPT_HW_GSI: 4093 set_datagram_seg(seg, wr); 4094 seg += sizeof(struct mlx5_wqe_datagram_seg); 4095 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4096 if (unlikely((seg == qend))) 4097 seg = mlx5_get_send_wqe(qp, 0); 4098 break; 4099 case IB_QPT_UD: 4100 set_datagram_seg(seg, wr); 4101 seg += sizeof(struct mlx5_wqe_datagram_seg); 4102 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4103 4104 if (unlikely((seg == qend))) 4105 seg = mlx5_get_send_wqe(qp, 0); 4106 4107 /* handle qp that supports ud offload */ 4108 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) { 4109 struct mlx5_wqe_eth_pad *pad; 4110 4111 pad = seg; 4112 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad)); 4113 seg += sizeof(struct mlx5_wqe_eth_pad); 4114 size += sizeof(struct mlx5_wqe_eth_pad) / 16; 4115 4116 seg = set_eth_seg(seg, wr, qend, qp, &size); 4117 4118 if (unlikely((seg == qend))) 4119 seg = mlx5_get_send_wqe(qp, 0); 4120 } 4121 break; 4122 case MLX5_IB_QPT_REG_UMR: 4123 if (wr->opcode != MLX5_IB_WR_UMR) { 4124 err = -EINVAL; 4125 mlx5_ib_warn(dev, "bad opcode\n"); 4126 goto out; 4127 } 4128 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 4129 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); 4130 set_reg_umr_segment(seg, wr); 4131 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4132 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4133 if (unlikely((seg == qend))) 4134 seg = mlx5_get_send_wqe(qp, 0); 4135 set_reg_mkey_segment(seg, wr); 4136 seg += sizeof(struct mlx5_mkey_seg); 4137 size += sizeof(struct mlx5_mkey_seg) / 16; 4138 if (unlikely((seg == qend))) 4139 seg = mlx5_get_send_wqe(qp, 0); 4140 break; 4141 4142 default: 4143 break; 4144 } 4145 4146 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 4147 int uninitialized_var(sz); 4148 4149 err = set_data_inl_seg(qp, wr, seg, &sz); 4150 if (unlikely(err)) { 4151 mlx5_ib_warn(dev, "\n"); 4152 *bad_wr = wr; 4153 goto out; 4154 } 4155 size += sz; 4156 } else { 4157 dpseg = seg; 4158 for (i = 0; i < num_sge; i++) { 4159 if (unlikely(dpseg == qend)) { 4160 seg = mlx5_get_send_wqe(qp, 0); 4161 dpseg = seg; 4162 } 4163 if (likely(wr->sg_list[i].length)) { 4164 set_data_ptr_seg(dpseg, wr->sg_list + i); 4165 size += sizeof(struct mlx5_wqe_data_seg) / 16; 4166 dpseg++; 4167 } 4168 } 4169 } 4170 4171 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 4172 get_fence(fence, wr), next_fence, 4173 mlx5_ib_opcode[wr->opcode]); 4174 skip_psv: 4175 if (0) 4176 dump_wqe(qp, idx, size); 4177 } 4178 4179 out: 4180 if (likely(nreq)) { 4181 qp->sq.head += nreq; 4182 4183 /* Make sure that descriptors are written before 4184 * updating doorbell record and ringing the doorbell 4185 */ 4186 wmb(); 4187 4188 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 4189 4190 /* Make sure doorbell record is visible to the HCA before 4191 * we hit doorbell */ 4192 wmb(); 4193 4194 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, 4195 MLX5_GET_DOORBELL_LOCK(&bf->lock32)); 4196 /* Make sure doorbells don't leak out of SQ spinlock 4197 * and reach the HCA out of order. 4198 */ 4199 bf->offset ^= bf->buf_size; 4200 } 4201 4202 spin_unlock_irqrestore(&qp->sq.lock, flags); 4203 4204 return err; 4205 } 4206 4207 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 4208 { 4209 sig->signature = calc_sig(sig, size); 4210 } 4211 4212 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 4213 const struct ib_recv_wr **bad_wr) 4214 { 4215 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4216 struct mlx5_wqe_data_seg *scat; 4217 struct mlx5_rwqe_sig *sig; 4218 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4219 struct mlx5_core_dev *mdev = dev->mdev; 4220 unsigned long flags; 4221 int err = 0; 4222 int nreq; 4223 int ind; 4224 int i; 4225 4226 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4227 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr); 4228 4229 spin_lock_irqsave(&qp->rq.lock, flags); 4230 4231 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 4232 err = -EIO; 4233 *bad_wr = wr; 4234 nreq = 0; 4235 goto out; 4236 } 4237 4238 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 4239 4240 for (nreq = 0; wr; nreq++, wr = wr->next) { 4241 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 4242 err = -ENOMEM; 4243 *bad_wr = wr; 4244 goto out; 4245 } 4246 4247 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 4248 err = -EINVAL; 4249 *bad_wr = wr; 4250 goto out; 4251 } 4252 4253 scat = get_recv_wqe(qp, ind); 4254 if (qp->wq_sig) 4255 scat++; 4256 4257 for (i = 0; i < wr->num_sge; i++) 4258 set_data_ptr_seg(scat + i, wr->sg_list + i); 4259 4260 if (i < qp->rq.max_gs) { 4261 scat[i].byte_count = 0; 4262 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 4263 scat[i].addr = 0; 4264 } 4265 4266 if (qp->wq_sig) { 4267 sig = (struct mlx5_rwqe_sig *)scat; 4268 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 4269 } 4270 4271 qp->rq.wrid[ind] = wr->wr_id; 4272 4273 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 4274 } 4275 4276 out: 4277 if (likely(nreq)) { 4278 qp->rq.head += nreq; 4279 4280 /* Make sure that descriptors are written before 4281 * doorbell record. 4282 */ 4283 wmb(); 4284 4285 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 4286 } 4287 4288 spin_unlock_irqrestore(&qp->rq.lock, flags); 4289 4290 return err; 4291 } 4292 4293 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4294 { 4295 switch (mlx5_state) { 4296 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4297 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4298 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4299 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4300 case MLX5_QP_STATE_SQ_DRAINING: 4301 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4302 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4303 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4304 default: return -1; 4305 } 4306 } 4307 4308 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4309 { 4310 switch (mlx5_mig_state) { 4311 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4312 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4313 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4314 default: return -1; 4315 } 4316 } 4317 4318 static int to_ib_qp_access_flags(int mlx5_flags) 4319 { 4320 int ib_flags = 0; 4321 4322 if (mlx5_flags & MLX5_QP_BIT_RRE) 4323 ib_flags |= IB_ACCESS_REMOTE_READ; 4324 if (mlx5_flags & MLX5_QP_BIT_RWE) 4325 ib_flags |= IB_ACCESS_REMOTE_WRITE; 4326 if (mlx5_flags & MLX5_QP_BIT_RAE) 4327 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 4328 4329 return ib_flags; 4330 } 4331 4332 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr, 4333 struct mlx5_qp_path *path) 4334 { 4335 struct mlx5_core_dev *dev = ibdev->mdev; 4336 4337 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr)); 4338 ib_ah_attr->port_num = path->port; 4339 4340 if (ib_ah_attr->port_num == 0 || 4341 ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports)) 4342 return; 4343 4344 ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf; 4345 4346 ib_ah_attr->dlid = be16_to_cpu(path->rlid); 4347 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f; 4348 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0; 4349 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0; 4350 if (ib_ah_attr->ah_flags) { 4351 ib_ah_attr->grh.sgid_index = path->mgid_index; 4352 ib_ah_attr->grh.hop_limit = path->hop_limit; 4353 ib_ah_attr->grh.traffic_class = 4354 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff; 4355 ib_ah_attr->grh.flow_label = 4356 be32_to_cpu(path->tclass_flowlabel) & 0xfffff; 4357 memcpy(ib_ah_attr->grh.dgid.raw, 4358 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw)); 4359 } 4360 } 4361 4362 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4363 struct mlx5_ib_sq *sq, 4364 u8 *sq_state) 4365 { 4366 void *out; 4367 void *sqc; 4368 int inlen; 4369 int err; 4370 4371 inlen = MLX5_ST_SZ_BYTES(query_sq_out); 4372 out = mlx5_vzalloc(inlen); 4373 if (!out) 4374 return -ENOMEM; 4375 4376 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out); 4377 if (err) 4378 goto out; 4379 4380 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context); 4381 *sq_state = MLX5_GET(sqc, sqc, state); 4382 sq->state = *sq_state; 4383 4384 out: 4385 kvfree(out); 4386 return err; 4387 } 4388 4389 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4390 struct mlx5_ib_rq *rq, 4391 u8 *rq_state) 4392 { 4393 void *out; 4394 void *rqc; 4395 int inlen; 4396 int err; 4397 4398 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4399 out = mlx5_vzalloc(inlen); 4400 if (!out) 4401 return -ENOMEM; 4402 4403 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4404 if (err) 4405 goto out; 4406 4407 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4408 *rq_state = MLX5_GET(rqc, rqc, state); 4409 rq->state = *rq_state; 4410 4411 out: 4412 kvfree(out); 4413 return err; 4414 } 4415 4416 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4417 struct mlx5_ib_qp *qp, u8 *qp_state) 4418 { 4419 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4420 [MLX5_RQC_STATE_RST] = { 4421 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4422 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4423 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4424 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4425 }, 4426 [MLX5_RQC_STATE_RDY] = { 4427 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4428 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4429 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4430 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4431 }, 4432 [MLX5_RQC_STATE_ERR] = { 4433 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4434 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4435 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4436 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4437 }, 4438 [MLX5_RQ_STATE_NA] = { 4439 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4440 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4441 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4442 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4443 }, 4444 }; 4445 4446 *qp_state = sqrq_trans[rq_state][sq_state]; 4447 4448 if (*qp_state == MLX5_QP_STATE_BAD) { 4449 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4450 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4451 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4452 return -EINVAL; 4453 } 4454 4455 if (*qp_state == MLX5_QP_STATE) 4456 *qp_state = qp->state; 4457 4458 return 0; 4459 } 4460 4461 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4462 struct mlx5_ib_qp *qp, 4463 u8 *raw_packet_qp_state) 4464 { 4465 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4466 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4467 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4468 int err; 4469 u8 sq_state = MLX5_SQ_STATE_NA; 4470 u8 rq_state = MLX5_RQ_STATE_NA; 4471 4472 if (qp->sq.wqe_cnt) { 4473 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4474 if (err) 4475 return err; 4476 } 4477 4478 if (qp->rq.wqe_cnt) { 4479 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4480 if (err) 4481 return err; 4482 } 4483 4484 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4485 raw_packet_qp_state); 4486 } 4487 4488 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4489 struct ib_qp_attr *qp_attr) 4490 { 4491 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 4492 struct mlx5_qp_context *context; 4493 int mlx5_state; 4494 u32 *outb; 4495 int err = 0; 4496 4497 outb = kzalloc(outlen, GFP_KERNEL); 4498 if (!outb) 4499 return -ENOMEM; 4500 4501 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, 4502 outlen); 4503 if (err) 4504 goto out; 4505 4506 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */ 4507 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc); 4508 4509 mlx5_state = be32_to_cpu(context->flags) >> 28; 4510 4511 qp->state = to_ib_qp_state(mlx5_state); 4512 qp_attr->path_mtu = context->mtu_msgmax >> 5; 4513 qp_attr->path_mig_state = 4514 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 4515 qp_attr->qkey = be32_to_cpu(context->qkey); 4516 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 4517 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 4518 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 4519 qp_attr->qp_access_flags = 4520 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 4521 4522 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 4523 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 4524 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 4525 qp_attr->alt_pkey_index = 4526 be16_to_cpu(context->alt_path.pkey_index); 4527 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num; 4528 } 4529 4530 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index); 4531 qp_attr->port_num = context->pri_path.port; 4532 4533 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 4534 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 4535 4536 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 4537 4538 qp_attr->max_dest_rd_atomic = 4539 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 4540 qp_attr->min_rnr_timer = 4541 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 4542 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 4543 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 4544 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 4545 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 4546 4547 out: 4548 kfree(outb); 4549 return err; 4550 } 4551 4552 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 4553 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 4554 { 4555 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4556 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4557 int err = 0; 4558 u8 raw_packet_qp_state; 4559 4560 if (ibqp->rwq_ind_tbl) 4561 return -ENOSYS; 4562 4563 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4564 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 4565 qp_init_attr); 4566 4567 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 4568 /* 4569 * Wait for any outstanding page faults, in case the user frees memory 4570 * based upon this query's result. 4571 */ 4572 flush_workqueue(mlx5_ib_page_fault_wq); 4573 #endif 4574 4575 mutex_lock(&qp->mutex); 4576 4577 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 4578 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 4579 if (err) 4580 goto out; 4581 qp->state = raw_packet_qp_state; 4582 qp_attr->port_num = 1; 4583 } else { 4584 err = query_qp_attr(dev, qp, qp_attr); 4585 if (err) 4586 goto out; 4587 } 4588 4589 qp_attr->qp_state = qp->state; 4590 qp_attr->cur_qp_state = qp_attr->qp_state; 4591 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 4592 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 4593 4594 if (!ibqp->uobject) { 4595 qp_attr->cap.max_send_wr = qp->sq.max_post; 4596 qp_attr->cap.max_send_sge = qp->sq.max_gs; 4597 qp_init_attr->qp_context = ibqp->qp_context; 4598 } else { 4599 qp_attr->cap.max_send_wr = 0; 4600 qp_attr->cap.max_send_sge = 0; 4601 } 4602 4603 qp_init_attr->qp_type = ibqp->qp_type; 4604 qp_init_attr->recv_cq = ibqp->recv_cq; 4605 qp_init_attr->send_cq = ibqp->send_cq; 4606 qp_init_attr->srq = ibqp->srq; 4607 qp_attr->cap.max_inline_data = qp->max_inline_data; 4608 4609 qp_init_attr->cap = qp_attr->cap; 4610 4611 qp_init_attr->create_flags = 0; 4612 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 4613 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 4614 4615 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 4616 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; 4617 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 4618 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; 4619 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 4620 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; 4621 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 4622 qp_init_attr->create_flags |= MLX5_IB_QP_CREATE_SQPN_QP1; 4623 4624 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 4625 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 4626 4627 out: 4628 mutex_unlock(&qp->mutex); 4629 return err; 4630 } 4631 4632 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 4633 struct ib_udata *udata) 4634 { 4635 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4636 struct mlx5_ib_xrcd *xrcd; 4637 int err; 4638 4639 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 4640 return ERR_PTR(-ENOSYS); 4641 4642 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 4643 if (!xrcd) 4644 return ERR_PTR(-ENOMEM); 4645 4646 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn); 4647 if (err) { 4648 kfree(xrcd); 4649 return ERR_PTR(-ENOMEM); 4650 } 4651 4652 return &xrcd->ibxrcd; 4653 } 4654 4655 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata) 4656 { 4657 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 4658 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 4659 int err; 4660 4661 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn); 4662 if (err) 4663 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 4664 4665 kfree(xrcd); 4666 return 0; 4667 } 4668 4669 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 4670 { 4671 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 4672 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 4673 struct ib_event event; 4674 4675 if (rwq->ibwq.event_handler) { 4676 event.device = rwq->ibwq.device; 4677 event.element.wq = &rwq->ibwq; 4678 switch (type) { 4679 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 4680 event.event = IB_EVENT_WQ_FATAL; 4681 break; 4682 default: 4683 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 4684 return; 4685 } 4686 4687 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 4688 } 4689 } 4690 4691 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 4692 struct ib_wq_init_attr *init_attr) 4693 { 4694 struct mlx5_ib_dev *dev; 4695 __be64 *rq_pas0; 4696 void *in; 4697 void *rqc; 4698 void *wq; 4699 int inlen; 4700 int err; 4701 4702 dev = to_mdev(pd->device); 4703 4704 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 4705 in = mlx5_vzalloc(inlen); 4706 if (!in) 4707 return -ENOMEM; 4708 4709 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 4710 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 4711 MLX5_SET(rqc, rqc, mem_rq_type, 4712 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE); 4713 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 4714 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 4715 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 4716 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 4717 wq = MLX5_ADDR_OF(rqc, rqc, wq); 4718 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 4719 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 4720 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 4721 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 4722 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 4723 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 4724 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 4725 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 4726 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 4727 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 4728 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); 4729 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp); 4730 kvfree(in); 4731 return err; 4732 } 4733 4734 static int set_user_rq_size(struct mlx5_ib_dev *dev, 4735 struct ib_wq_init_attr *wq_init_attr, 4736 struct mlx5_ib_create_wq *ucmd, 4737 struct mlx5_ib_rwq *rwq) 4738 { 4739 /* Sanity check RQ size before proceeding */ 4740 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 4741 return -EINVAL; 4742 4743 if (!ucmd->rq_wqe_count) 4744 return -EINVAL; 4745 4746 rwq->wqe_count = ucmd->rq_wqe_count; 4747 rwq->wqe_shift = ucmd->rq_wqe_shift; 4748 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift); 4749 rwq->log_rq_stride = rwq->wqe_shift; 4750 rwq->log_rq_size = ilog2(rwq->wqe_count); 4751 return 0; 4752 } 4753 4754 static int prepare_user_rq(struct ib_pd *pd, 4755 struct ib_wq_init_attr *init_attr, 4756 struct ib_udata *udata, 4757 struct mlx5_ib_rwq *rwq) 4758 { 4759 struct mlx5_ib_dev *dev = to_mdev(pd->device); 4760 struct mlx5_ib_create_wq ucmd = {}; 4761 int err; 4762 size_t required_cmd_sz; 4763 4764 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 4765 if (udata->inlen < required_cmd_sz) { 4766 mlx5_ib_dbg(dev, "invalid inlen\n"); 4767 return -EINVAL; 4768 } 4769 4770 if (udata->inlen > sizeof(ucmd) && 4771 !ib_is_udata_cleared(udata, sizeof(ucmd), 4772 udata->inlen - sizeof(ucmd))) { 4773 mlx5_ib_dbg(dev, "inlen is not supported\n"); 4774 return -EOPNOTSUPP; 4775 } 4776 4777 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 4778 mlx5_ib_dbg(dev, "copy failed\n"); 4779 return -EFAULT; 4780 } 4781 4782 if (ucmd.comp_mask) { 4783 mlx5_ib_dbg(dev, "invalid comp mask\n"); 4784 return -EOPNOTSUPP; 4785 } 4786 4787 if (ucmd.reserved) { 4788 mlx5_ib_dbg(dev, "invalid reserved\n"); 4789 return -EOPNOTSUPP; 4790 } 4791 4792 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 4793 if (err) { 4794 mlx5_ib_dbg(dev, "err %d\n", err); 4795 return err; 4796 } 4797 4798 err = create_user_rq(dev, pd, rwq, &ucmd); 4799 if (err) { 4800 mlx5_ib_dbg(dev, "err %d\n", err); 4801 if (err) 4802 return err; 4803 } 4804 4805 rwq->user_index = ucmd.user_index; 4806 return 0; 4807 } 4808 4809 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 4810 struct ib_wq_init_attr *init_attr, 4811 struct ib_udata *udata) 4812 { 4813 struct mlx5_ib_dev *dev; 4814 struct mlx5_ib_rwq *rwq; 4815 struct mlx5_ib_create_wq_resp resp = {}; 4816 size_t min_resp_len; 4817 int err; 4818 4819 if (!udata) 4820 return ERR_PTR(-ENOSYS); 4821 4822 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4823 if (udata->outlen && udata->outlen < min_resp_len) 4824 return ERR_PTR(-EINVAL); 4825 4826 dev = to_mdev(pd->device); 4827 switch (init_attr->wq_type) { 4828 case IB_WQT_RQ: 4829 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 4830 if (!rwq) 4831 return ERR_PTR(-ENOMEM); 4832 err = prepare_user_rq(pd, init_attr, udata, rwq); 4833 if (err) 4834 goto err; 4835 err = create_rq(rwq, pd, init_attr); 4836 if (err) 4837 goto err_user_rq; 4838 break; 4839 default: 4840 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 4841 init_attr->wq_type); 4842 return ERR_PTR(-EINVAL); 4843 } 4844 4845 rwq->ibwq.wq_num = rwq->core_qp.qpn; 4846 rwq->ibwq.state = IB_WQS_RESET; 4847 if (udata->outlen) { 4848 resp.response_length = offsetof(typeof(resp), response_length) + 4849 sizeof(resp.response_length); 4850 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4851 if (err) 4852 goto err_copy; 4853 } 4854 4855 rwq->core_qp.event = mlx5_ib_wq_event; 4856 rwq->ibwq.event_handler = init_attr->event_handler; 4857 return &rwq->ibwq; 4858 4859 err_copy: 4860 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 4861 err_user_rq: 4862 destroy_user_rq(pd, rwq, udata); 4863 err: 4864 kfree(rwq); 4865 return ERR_PTR(err); 4866 } 4867 4868 void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata) 4869 { 4870 struct mlx5_ib_dev *dev = to_mdev(wq->device); 4871 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 4872 4873 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 4874 destroy_user_rq(wq->pd, rwq, udata); 4875 kfree(rwq); 4876 } 4877 4878 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 4879 struct ib_rwq_ind_table_init_attr *init_attr, 4880 struct ib_udata *udata) 4881 { 4882 struct mlx5_ib_dev *dev = to_mdev(device); 4883 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl; 4884 int sz = 1 << init_attr->log_ind_tbl_size; 4885 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 4886 size_t min_resp_len; 4887 int inlen; 4888 int err; 4889 int i; 4890 u32 *in; 4891 void *rqtc; 4892 4893 if (udata->inlen > 0 && 4894 !ib_is_udata_cleared(udata, 0, 4895 udata->inlen)) 4896 return ERR_PTR(-EOPNOTSUPP); 4897 4898 if (init_attr->log_ind_tbl_size > 4899 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 4900 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 4901 init_attr->log_ind_tbl_size, 4902 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 4903 return ERR_PTR(-EINVAL); 4904 } 4905 4906 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4907 if (udata->outlen && udata->outlen < min_resp_len) 4908 return ERR_PTR(-EINVAL); 4909 4910 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL); 4911 if (!rwq_ind_tbl) 4912 return ERR_PTR(-ENOMEM); 4913 4914 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 4915 in = mlx5_vzalloc(inlen); 4916 if (!in) { 4917 err = -ENOMEM; 4918 goto err; 4919 } 4920 4921 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 4922 4923 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 4924 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 4925 4926 for (i = 0; i < sz; i++) 4927 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 4928 4929 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid; 4930 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid); 4931 4932 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 4933 kvfree(in); 4934 4935 if (err) 4936 goto err; 4937 4938 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 4939 if (udata->outlen) { 4940 resp.response_length = offsetof(typeof(resp), response_length) + 4941 sizeof(resp.response_length); 4942 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4943 if (err) 4944 goto err_copy; 4945 } 4946 4947 return &rwq_ind_tbl->ib_rwq_ind_tbl; 4948 4949 err_copy: 4950 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 4951 err: 4952 kfree(rwq_ind_tbl); 4953 return ERR_PTR(err); 4954 } 4955 4956 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 4957 { 4958 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 4959 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 4960 4961 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 4962 4963 kfree(rwq_ind_tbl); 4964 return 0; 4965 } 4966 4967 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 4968 u32 wq_attr_mask, struct ib_udata *udata) 4969 { 4970 struct mlx5_ib_dev *dev = to_mdev(wq->device); 4971 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 4972 struct mlx5_ib_modify_wq ucmd = {}; 4973 size_t required_cmd_sz; 4974 int curr_wq_state; 4975 int wq_state; 4976 int inlen; 4977 int err; 4978 void *rqc; 4979 void *in; 4980 4981 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 4982 if (udata->inlen < required_cmd_sz) 4983 return -EINVAL; 4984 4985 if (udata->inlen > sizeof(ucmd) && 4986 !ib_is_udata_cleared(udata, sizeof(ucmd), 4987 udata->inlen - sizeof(ucmd))) 4988 return -EOPNOTSUPP; 4989 4990 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 4991 return -EFAULT; 4992 4993 if (ucmd.comp_mask || ucmd.reserved) 4994 return -EOPNOTSUPP; 4995 4996 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 4997 in = mlx5_vzalloc(inlen); 4998 if (!in) 4999 return -ENOMEM; 5000 5001 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 5002 5003 MLX5_SET(modify_rq_in, in, rqn, rwq->core_qp.qpn); 5004 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 5005 wq_attr->curr_wq_state : wq->state; 5006 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 5007 wq_attr->wq_state : curr_wq_state; 5008 if (curr_wq_state == IB_WQS_ERR) 5009 curr_wq_state = MLX5_RQC_STATE_ERR; 5010 if (wq_state == IB_WQS_ERR) 5011 wq_state = MLX5_RQC_STATE_ERR; 5012 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 5013 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid); 5014 MLX5_SET(rqc, rqc, state, wq_state); 5015 5016 err = mlx5_core_modify_rq(dev->mdev, in, inlen); 5017 kvfree(in); 5018 if (!err) 5019 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 5020 5021 return err; 5022 } 5023