xref: /freebsd/sys/dev/mlx5/mlx5_ib/mlx5_ib_qp.c (revision 190cef3d52236565eb22e18b33e9e865ec634aa3)
1 /*-
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  * 1. Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  *
13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23  * SUCH DAMAGE.
24  *
25  * $FreeBSD$
26  */
27 
28 #include <linux/module.h>
29 #include <rdma/ib_umem.h>
30 #include <rdma/ib_cache.h>
31 #include <rdma/ib_user_verbs.h>
32 #include "mlx5_ib.h"
33 
34 /* not supported currently */
35 static int wq_signature;
36 
37 enum {
38 	MLX5_IB_ACK_REQ_FREQ	= 8,
39 };
40 
41 enum {
42 	MLX5_IB_DEFAULT_SCHED_QUEUE	= 0x83,
43 	MLX5_IB_DEFAULT_QP0_SCHED_QUEUE	= 0x3f,
44 	MLX5_IB_LINK_TYPE_IB		= 0,
45 	MLX5_IB_LINK_TYPE_ETH		= 1
46 };
47 
48 enum {
49 	MLX5_IB_SQ_STRIDE	= 6,
50 };
51 
52 static const u32 mlx5_ib_opcode[] = {
53 	[IB_WR_SEND]				= MLX5_OPCODE_SEND,
54 	[IB_WR_LSO]				= MLX5_OPCODE_LSO,
55 	[IB_WR_SEND_WITH_IMM]			= MLX5_OPCODE_SEND_IMM,
56 	[IB_WR_RDMA_WRITE]			= MLX5_OPCODE_RDMA_WRITE,
57 	[IB_WR_RDMA_WRITE_WITH_IMM]		= MLX5_OPCODE_RDMA_WRITE_IMM,
58 	[IB_WR_RDMA_READ]			= MLX5_OPCODE_RDMA_READ,
59 	[IB_WR_ATOMIC_CMP_AND_SWP]		= MLX5_OPCODE_ATOMIC_CS,
60 	[IB_WR_ATOMIC_FETCH_AND_ADD]		= MLX5_OPCODE_ATOMIC_FA,
61 	[IB_WR_SEND_WITH_INV]			= MLX5_OPCODE_SEND_INVAL,
62 	[IB_WR_LOCAL_INV]			= MLX5_OPCODE_UMR,
63 	[IB_WR_REG_MR]				= MLX5_OPCODE_UMR,
64 	[IB_WR_MASKED_ATOMIC_CMP_AND_SWP]	= MLX5_OPCODE_ATOMIC_MASKED_CS,
65 	[IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]	= MLX5_OPCODE_ATOMIC_MASKED_FA,
66 	[MLX5_IB_WR_UMR]			= MLX5_OPCODE_UMR,
67 };
68 
69 struct mlx5_wqe_eth_pad {
70 	u8 rsvd0[16];
71 };
72 
73 enum raw_qp_set_mask_map {
74 	MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID		= 1UL << 0,
75 };
76 
77 struct mlx5_modify_raw_qp_param {
78 	u16 operation;
79 
80 	u32 set_mask; /* raw_qp_set_mask_map */
81 	u8 rq_q_ctr_id;
82 };
83 
84 static void get_cqs(enum ib_qp_type qp_type,
85 		    struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
86 		    struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
87 
88 static int is_qp0(enum ib_qp_type qp_type)
89 {
90 	return qp_type == IB_QPT_SMI;
91 }
92 
93 static int is_sqp(enum ib_qp_type qp_type)
94 {
95 	return is_qp0(qp_type) || is_qp1(qp_type);
96 }
97 
98 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
99 {
100 	return mlx5_buf_offset(&qp->buf, offset);
101 }
102 
103 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
104 {
105 	return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
106 }
107 
108 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
109 {
110 	return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
111 }
112 
113 /**
114  * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
115  *
116  * @qp: QP to copy from.
117  * @send: copy from the send queue when non-zero, use the receive queue
118  *	  otherwise.
119  * @wqe_index:  index to start copying from. For send work queues, the
120  *		wqe_index is in units of MLX5_SEND_WQE_BB.
121  *		For receive work queue, it is the number of work queue
122  *		element in the queue.
123  * @buffer: destination buffer.
124  * @length: maximum number of bytes to copy.
125  *
126  * Copies at least a single WQE, but may copy more data.
127  *
128  * Return: the number of bytes copied, or an error code.
129  */
130 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
131 			  void *buffer, u32 length,
132 			  struct mlx5_ib_qp_base *base)
133 {
134 	struct ib_device *ibdev = qp->ibqp.device;
135 	struct mlx5_ib_dev *dev = to_mdev(ibdev);
136 	struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
137 	size_t offset;
138 	size_t wq_end;
139 	struct ib_umem *umem = base->ubuffer.umem;
140 	u32 first_copy_length;
141 	int wqe_length;
142 	int ret;
143 
144 	if (wq->wqe_cnt == 0) {
145 		mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
146 			    qp->ibqp.qp_type);
147 		return -EINVAL;
148 	}
149 
150 	offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
151 	wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
152 
153 	if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
154 		return -EINVAL;
155 
156 	if (offset > umem->length ||
157 	    (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
158 		return -EINVAL;
159 
160 	first_copy_length = min_t(u32, offset + length, wq_end) - offset;
161 	ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
162 	if (ret)
163 		return ret;
164 
165 	if (send) {
166 		struct mlx5_wqe_ctrl_seg *ctrl = buffer;
167 		int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
168 
169 		wqe_length = ds * MLX5_WQE_DS_UNITS;
170 	} else {
171 		wqe_length = 1 << wq->wqe_shift;
172 	}
173 
174 	if (wqe_length <= first_copy_length)
175 		return first_copy_length;
176 
177 	ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
178 				wqe_length - first_copy_length);
179 	if (ret)
180 		return ret;
181 
182 	return wqe_length;
183 }
184 
185 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
186 {
187 	struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
188 	struct ib_event event;
189 
190 	if (type == MLX5_EVENT_TYPE_PATH_MIG) {
191 		/* This event is only valid for trans_qps */
192 		to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
193 	}
194 
195 	if (ibqp->event_handler) {
196 		event.device     = ibqp->device;
197 		event.element.qp = ibqp;
198 		switch (type) {
199 		case MLX5_EVENT_TYPE_PATH_MIG:
200 			event.event = IB_EVENT_PATH_MIG;
201 			break;
202 		case MLX5_EVENT_TYPE_COMM_EST:
203 			event.event = IB_EVENT_COMM_EST;
204 			break;
205 		case MLX5_EVENT_TYPE_SQ_DRAINED:
206 			event.event = IB_EVENT_SQ_DRAINED;
207 			break;
208 		case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
209 			event.event = IB_EVENT_QP_LAST_WQE_REACHED;
210 			break;
211 		case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
212 			event.event = IB_EVENT_QP_FATAL;
213 			break;
214 		case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
215 			event.event = IB_EVENT_PATH_MIG_ERR;
216 			break;
217 		case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
218 			event.event = IB_EVENT_QP_REQ_ERR;
219 			break;
220 		case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
221 			event.event = IB_EVENT_QP_ACCESS_ERR;
222 			break;
223 		default:
224 			pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
225 			return;
226 		}
227 
228 		ibqp->event_handler(&event, ibqp->qp_context);
229 	}
230 }
231 
232 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
233 		       int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
234 {
235 	int wqe_size;
236 	int wq_size;
237 
238 	/* Sanity check RQ size before proceeding */
239 	if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
240 		return -EINVAL;
241 
242 	if (!has_rq) {
243 		qp->rq.max_gs = 0;
244 		qp->rq.wqe_cnt = 0;
245 		qp->rq.wqe_shift = 0;
246 		cap->max_recv_wr = 0;
247 		cap->max_recv_sge = 0;
248 	} else {
249 		if (ucmd) {
250 			qp->rq.wqe_cnt = ucmd->rq_wqe_count;
251 			qp->rq.wqe_shift = ucmd->rq_wqe_shift;
252 			qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
253 			qp->rq.max_post = qp->rq.wqe_cnt;
254 		} else {
255 			wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
256 			wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
257 			wqe_size = roundup_pow_of_two(wqe_size);
258 			wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
259 			wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
260 			qp->rq.wqe_cnt = wq_size / wqe_size;
261 			if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
262 				mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
263 					    wqe_size,
264 					    MLX5_CAP_GEN(dev->mdev,
265 							 max_wqe_sz_rq));
266 				return -EINVAL;
267 			}
268 			qp->rq.wqe_shift = ilog2(wqe_size);
269 			qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
270 			qp->rq.max_post = qp->rq.wqe_cnt;
271 		}
272 	}
273 
274 	return 0;
275 }
276 
277 static int sq_overhead(struct ib_qp_init_attr *attr)
278 {
279 	int size = 0;
280 
281 	switch (attr->qp_type) {
282 	case IB_QPT_XRC_INI:
283 		size += sizeof(struct mlx5_wqe_xrc_seg);
284 		/* fall through */
285 	case IB_QPT_RC:
286 		size += sizeof(struct mlx5_wqe_ctrl_seg) +
287 			max(sizeof(struct mlx5_wqe_atomic_seg) +
288 			    sizeof(struct mlx5_wqe_raddr_seg),
289 			    sizeof(struct mlx5_wqe_umr_ctrl_seg) +
290 			    sizeof(struct mlx5_mkey_seg));
291 		break;
292 
293 	case IB_QPT_XRC_TGT:
294 		return 0;
295 
296 	case IB_QPT_UC:
297 		size += sizeof(struct mlx5_wqe_ctrl_seg) +
298 			max(sizeof(struct mlx5_wqe_raddr_seg),
299 			    sizeof(struct mlx5_wqe_umr_ctrl_seg) +
300 			    sizeof(struct mlx5_mkey_seg));
301 		break;
302 
303 	case IB_QPT_UD:
304 		if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
305 			size += sizeof(struct mlx5_wqe_eth_pad) +
306 				sizeof(struct mlx5_wqe_eth_seg);
307 		/* fall through */
308 	case IB_QPT_SMI:
309 	case MLX5_IB_QPT_HW_GSI:
310 		size += sizeof(struct mlx5_wqe_ctrl_seg) +
311 			sizeof(struct mlx5_wqe_datagram_seg);
312 		break;
313 
314 	case MLX5_IB_QPT_REG_UMR:
315 		size += sizeof(struct mlx5_wqe_ctrl_seg) +
316 			sizeof(struct mlx5_wqe_umr_ctrl_seg) +
317 			sizeof(struct mlx5_mkey_seg);
318 		break;
319 
320 	default:
321 		return -EINVAL;
322 	}
323 
324 	return size;
325 }
326 
327 static int calc_send_wqe(struct ib_qp_init_attr *attr)
328 {
329 	int inl_size = 0;
330 	int size;
331 
332 	size = sq_overhead(attr);
333 	if (size < 0)
334 		return size;
335 
336 	if (attr->cap.max_inline_data) {
337 		inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
338 			attr->cap.max_inline_data;
339 	}
340 
341 	size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
342 	if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
343 	    ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
344 			return MLX5_SIG_WQE_SIZE;
345 	else
346 		return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
347 }
348 
349 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
350 			struct mlx5_ib_qp *qp)
351 {
352 	int wqe_size;
353 	int wq_size;
354 
355 	if (!attr->cap.max_send_wr)
356 		return 0;
357 
358 	wqe_size = calc_send_wqe(attr);
359 	mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
360 	if (wqe_size < 0)
361 		return wqe_size;
362 
363 	if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
364 		mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
365 			    wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
366 		return -EINVAL;
367 	}
368 
369 	qp->max_inline_data = wqe_size - sq_overhead(attr) -
370 			      sizeof(struct mlx5_wqe_inline_seg);
371 	attr->cap.max_inline_data = qp->max_inline_data;
372 
373 	if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
374 		qp->signature_en = true;
375 
376 	wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
377 	qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
378 	if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
379 		mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
380 			    qp->sq.wqe_cnt,
381 			    1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
382 		return -ENOMEM;
383 	}
384 	qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
385 	qp->sq.max_gs = attr->cap.max_send_sge;
386 	qp->sq.max_post = wq_size / wqe_size;
387 	attr->cap.max_send_wr = qp->sq.max_post;
388 
389 	return wq_size;
390 }
391 
392 static int set_user_buf_size(struct mlx5_ib_dev *dev,
393 			    struct mlx5_ib_qp *qp,
394 			    struct mlx5_ib_create_qp *ucmd,
395 			    struct mlx5_ib_qp_base *base,
396 			    struct ib_qp_init_attr *attr)
397 {
398 	int desc_sz = 1 << qp->sq.wqe_shift;
399 
400 	if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
401 		mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
402 			     desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
403 		return -EINVAL;
404 	}
405 
406 	if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
407 		mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
408 			     ucmd->sq_wqe_count, ucmd->sq_wqe_count);
409 		return -EINVAL;
410 	}
411 
412 	qp->sq.wqe_cnt = ucmd->sq_wqe_count;
413 
414 	if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
415 		mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
416 			     qp->sq.wqe_cnt,
417 			     1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
418 		return -EINVAL;
419 	}
420 
421 	if (attr->qp_type == IB_QPT_RAW_PACKET) {
422 		base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
423 		qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
424 	} else {
425 		base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
426 					 (qp->sq.wqe_cnt << 6);
427 	}
428 
429 	return 0;
430 }
431 
432 static int qp_has_rq(struct ib_qp_init_attr *attr)
433 {
434 	if (attr->qp_type == IB_QPT_XRC_INI ||
435 	    attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
436 	    attr->qp_type == MLX5_IB_QPT_REG_UMR ||
437 	    !attr->cap.max_recv_wr)
438 		return 0;
439 
440 	return 1;
441 }
442 
443 static int first_med_uuar(void)
444 {
445 	return 1;
446 }
447 
448 static int next_uuar(int n)
449 {
450 	n++;
451 
452 	while (((n % 4) & 2))
453 		n++;
454 
455 	return n;
456 }
457 
458 static int num_med_uuar(struct mlx5_uuar_info *uuari)
459 {
460 	int n;
461 
462 	n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE -
463 		uuari->num_low_latency_uuars - 1;
464 
465 	return n >= 0 ? n : 0;
466 }
467 
468 static int max_uuari(struct mlx5_uuar_info *uuari)
469 {
470 	return uuari->num_uars * 4;
471 }
472 
473 static int first_hi_uuar(struct mlx5_uuar_info *uuari)
474 {
475 	int med;
476 	int i;
477 	int t;
478 
479 	med = num_med_uuar(uuari);
480 	for (t = 0, i = first_med_uuar();; i = next_uuar(i)) {
481 		t++;
482 		if (t == med)
483 			return next_uuar(i);
484 	}
485 
486 	return 0;
487 }
488 
489 static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
490 {
491 	int i;
492 
493 	for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) {
494 		if (!test_bit(i, uuari->bitmap)) {
495 			set_bit(i, uuari->bitmap);
496 			uuari->count[i]++;
497 			return i;
498 		}
499 	}
500 
501 	return -ENOMEM;
502 }
503 
504 static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
505 {
506 	int minidx = first_med_uuar();
507 	int i;
508 
509 	for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) {
510 		if (uuari->count[i] < uuari->count[minidx])
511 			minidx = i;
512 	}
513 
514 	uuari->count[minidx]++;
515 	return minidx;
516 }
517 
518 static int alloc_uuar(struct mlx5_uuar_info *uuari,
519 		      enum mlx5_ib_latency_class lat)
520 {
521 	int uuarn = -EINVAL;
522 
523 	mutex_lock(&uuari->lock);
524 	switch (lat) {
525 	case MLX5_IB_LATENCY_CLASS_LOW:
526 		uuarn = 0;
527 		uuari->count[uuarn]++;
528 		break;
529 
530 	case MLX5_IB_LATENCY_CLASS_MEDIUM:
531 		if (uuari->ver < 2)
532 			uuarn = -ENOMEM;
533 		else
534 			uuarn = alloc_med_class_uuar(uuari);
535 		break;
536 
537 	case MLX5_IB_LATENCY_CLASS_HIGH:
538 		if (uuari->ver < 2)
539 			uuarn = -ENOMEM;
540 		else
541 			uuarn = alloc_high_class_uuar(uuari);
542 		break;
543 
544 	case MLX5_IB_LATENCY_CLASS_FAST_PATH:
545 		uuarn = 2;
546 		break;
547 	}
548 	mutex_unlock(&uuari->lock);
549 
550 	return uuarn;
551 }
552 
553 static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
554 {
555 	clear_bit(uuarn, uuari->bitmap);
556 	--uuari->count[uuarn];
557 }
558 
559 static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
560 {
561 	clear_bit(uuarn, uuari->bitmap);
562 	--uuari->count[uuarn];
563 }
564 
565 static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
566 {
567 	int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
568 	int high_uuar = nuuars - uuari->num_low_latency_uuars;
569 
570 	mutex_lock(&uuari->lock);
571 	if (uuarn == 0) {
572 		--uuari->count[uuarn];
573 		goto out;
574 	}
575 
576 	if (uuarn < high_uuar) {
577 		free_med_class_uuar(uuari, uuarn);
578 		goto out;
579 	}
580 
581 	free_high_class_uuar(uuari, uuarn);
582 
583 out:
584 	mutex_unlock(&uuari->lock);
585 }
586 
587 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
588 {
589 	switch (state) {
590 	case IB_QPS_RESET:	return MLX5_QP_STATE_RST;
591 	case IB_QPS_INIT:	return MLX5_QP_STATE_INIT;
592 	case IB_QPS_RTR:	return MLX5_QP_STATE_RTR;
593 	case IB_QPS_RTS:	return MLX5_QP_STATE_RTS;
594 	case IB_QPS_SQD:	return MLX5_QP_STATE_SQD;
595 	case IB_QPS_SQE:	return MLX5_QP_STATE_SQER;
596 	case IB_QPS_ERR:	return MLX5_QP_STATE_ERR;
597 	default:		return -1;
598 	}
599 }
600 
601 static int to_mlx5_st(enum ib_qp_type type)
602 {
603 	switch (type) {
604 	case IB_QPT_RC:			return MLX5_QP_ST_RC;
605 	case IB_QPT_UC:			return MLX5_QP_ST_UC;
606 	case IB_QPT_UD:			return MLX5_QP_ST_UD;
607 	case MLX5_IB_QPT_REG_UMR:	return MLX5_QP_ST_REG_UMR;
608 	case IB_QPT_XRC_INI:
609 	case IB_QPT_XRC_TGT:		return MLX5_QP_ST_XRC;
610 	case IB_QPT_SMI:		return MLX5_QP_ST_QP0;
611 	case MLX5_IB_QPT_HW_GSI:	return MLX5_QP_ST_QP1;
612 	case IB_QPT_RAW_IPV6:		return MLX5_QP_ST_RAW_IPV6;
613 	case IB_QPT_RAW_PACKET:
614 	case IB_QPT_RAW_ETHERTYPE:	return MLX5_QP_ST_RAW_ETHERTYPE;
615 	case IB_QPT_MAX:
616 	default:		return -EINVAL;
617 	}
618 }
619 
620 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
621 			     struct mlx5_ib_cq *recv_cq);
622 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
623 			       struct mlx5_ib_cq *recv_cq);
624 
625 static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
626 {
627 	return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
628 }
629 
630 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
631 			    struct ib_pd *pd,
632 			    unsigned long addr, size_t size,
633 			    struct ib_umem **umem,
634 			    int *npages, int *page_shift, int *ncont,
635 			    u32 *offset)
636 {
637 	int err;
638 
639 	*umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
640 	if (IS_ERR(*umem)) {
641 		mlx5_ib_dbg(dev, "umem_get failed\n");
642 		return PTR_ERR(*umem);
643 	}
644 
645 	mlx5_ib_cont_pages(*umem, addr, npages, page_shift, ncont, NULL);
646 
647 	err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
648 	if (err) {
649 		mlx5_ib_warn(dev, "bad offset\n");
650 		goto err_umem;
651 	}
652 
653 	mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
654 		    addr, size, *npages, *page_shift, *ncont, *offset);
655 
656 	return 0;
657 
658 err_umem:
659 	ib_umem_release(*umem);
660 	*umem = NULL;
661 
662 	return err;
663 }
664 
665 static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq)
666 {
667 	struct mlx5_ib_ucontext *context;
668 
669 	context = to_mucontext(pd->uobject->context);
670 	mlx5_ib_db_unmap_user(context, &rwq->db);
671 	if (rwq->umem)
672 		ib_umem_release(rwq->umem);
673 }
674 
675 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
676 			  struct mlx5_ib_rwq *rwq,
677 			  struct mlx5_ib_create_wq *ucmd)
678 {
679 	struct mlx5_ib_ucontext *context;
680 	int page_shift = 0;
681 	int npages;
682 	u32 offset = 0;
683 	int ncont = 0;
684 	int err;
685 
686 	if (!ucmd->buf_addr)
687 		return -EINVAL;
688 
689 	context = to_mucontext(pd->uobject->context);
690 	rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
691 			       rwq->buf_size, 0, 0);
692 	if (IS_ERR(rwq->umem)) {
693 		mlx5_ib_dbg(dev, "umem_get failed\n");
694 		err = PTR_ERR(rwq->umem);
695 		return err;
696 	}
697 
698 	mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, &npages, &page_shift,
699 			   &ncont, NULL);
700 	err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
701 				     &rwq->rq_page_offset);
702 	if (err) {
703 		mlx5_ib_warn(dev, "bad offset\n");
704 		goto err_umem;
705 	}
706 
707 	rwq->rq_num_pas = ncont;
708 	rwq->page_shift = page_shift;
709 	rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
710 	rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
711 
712 	mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
713 		    (unsigned long long)ucmd->buf_addr, rwq->buf_size,
714 		    npages, page_shift, ncont, offset);
715 
716 	err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
717 	if (err) {
718 		mlx5_ib_dbg(dev, "map failed\n");
719 		goto err_umem;
720 	}
721 
722 	rwq->create_type = MLX5_WQ_USER;
723 	return 0;
724 
725 err_umem:
726 	ib_umem_release(rwq->umem);
727 	return err;
728 }
729 
730 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
731 			  struct mlx5_ib_qp *qp, struct ib_udata *udata,
732 			  struct ib_qp_init_attr *attr,
733 			  u32 **in,
734 			  struct mlx5_ib_create_qp_resp *resp, int *inlen,
735 			  struct mlx5_ib_qp_base *base)
736 {
737 	struct mlx5_ib_ucontext *context;
738 	struct mlx5_ib_create_qp ucmd;
739 	struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
740 	int page_shift = 0;
741 	int uar_index;
742 	int npages;
743 	u32 offset = 0;
744 	int uuarn;
745 	int ncont = 0;
746 	__be64 *pas;
747 	void *qpc;
748 	int err;
749 
750 	err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
751 	if (err) {
752 		mlx5_ib_dbg(dev, "copy failed\n");
753 		return err;
754 	}
755 
756 	context = to_mucontext(pd->uobject->context);
757 	/*
758 	 * TBD: should come from the verbs when we have the API
759 	 */
760 	if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
761 		/* In CROSS_CHANNEL CQ and QP must use the same UAR */
762 		uuarn = MLX5_CROSS_CHANNEL_UUAR;
763 	else {
764 		uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
765 		if (uuarn < 0) {
766 			mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
767 			mlx5_ib_dbg(dev, "reverting to medium latency\n");
768 			uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM);
769 			if (uuarn < 0) {
770 				mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n");
771 				mlx5_ib_dbg(dev, "reverting to high latency\n");
772 				uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
773 				if (uuarn < 0) {
774 					mlx5_ib_warn(dev, "uuar allocation failed\n");
775 					return uuarn;
776 				}
777 			}
778 		}
779 	}
780 
781 	uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
782 	mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
783 
784 	qp->rq.offset = 0;
785 	qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
786 	qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
787 
788 	err = set_user_buf_size(dev, qp, &ucmd, base, attr);
789 	if (err)
790 		goto err_uuar;
791 
792 	if (ucmd.buf_addr && ubuffer->buf_size) {
793 		ubuffer->buf_addr = ucmd.buf_addr;
794 		err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
795 				       ubuffer->buf_size,
796 				       &ubuffer->umem, &npages, &page_shift,
797 				       &ncont, &offset);
798 		if (err)
799 			goto err_uuar;
800 	} else {
801 		ubuffer->umem = NULL;
802 	}
803 
804 	*inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
805 		 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
806 	*in = mlx5_vzalloc(*inlen);
807 	if (!*in) {
808 		err = -ENOMEM;
809 		goto err_umem;
810 	}
811 
812 	pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
813 	if (ubuffer->umem)
814 		mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
815 
816 	qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
817 
818 	MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
819 	MLX5_SET(qpc, qpc, page_offset, offset);
820 
821 	MLX5_SET(qpc, qpc, uar_page, uar_index);
822 	resp->uuar_index = uuarn;
823 	qp->uuarn = uuarn;
824 
825 	err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
826 	if (err) {
827 		mlx5_ib_dbg(dev, "map failed\n");
828 		goto err_free;
829 	}
830 
831 	err = ib_copy_to_udata(udata, resp, sizeof(*resp));
832 	if (err) {
833 		mlx5_ib_dbg(dev, "copy failed\n");
834 		goto err_unmap;
835 	}
836 	qp->create_type = MLX5_QP_USER;
837 
838 	return 0;
839 
840 err_unmap:
841 	mlx5_ib_db_unmap_user(context, &qp->db);
842 
843 err_free:
844 	kvfree(*in);
845 
846 err_umem:
847 	if (ubuffer->umem)
848 		ib_umem_release(ubuffer->umem);
849 
850 err_uuar:
851 	free_uuar(&context->uuari, uuarn);
852 	return err;
853 }
854 
855 static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp,
856 			    struct mlx5_ib_qp_base *base)
857 {
858 	struct mlx5_ib_ucontext *context;
859 
860 	context = to_mucontext(pd->uobject->context);
861 	mlx5_ib_db_unmap_user(context, &qp->db);
862 	if (base->ubuffer.umem)
863 		ib_umem_release(base->ubuffer.umem);
864 	free_uuar(&context->uuari, qp->uuarn);
865 }
866 
867 static int create_kernel_qp(struct mlx5_ib_dev *dev,
868 			    struct ib_qp_init_attr *init_attr,
869 			    struct mlx5_ib_qp *qp,
870 			    u32 **in, int *inlen,
871 			    struct mlx5_ib_qp_base *base)
872 {
873 	enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
874 	struct mlx5_uuar_info *uuari;
875 	int uar_index;
876 	void *qpc;
877 	int uuarn;
878 	int err;
879 
880 	uuari = &dev->mdev->priv.uuari;
881 	if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
882 					IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
883 					IB_QP_CREATE_IPOIB_UD_LSO |
884 					mlx5_ib_create_qp_sqpn_qp1()))
885 		return -EINVAL;
886 
887 	if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
888 		lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
889 
890 	uuarn = alloc_uuar(uuari, lc);
891 	if (uuarn < 0) {
892 		mlx5_ib_dbg(dev, "\n");
893 		return -ENOMEM;
894 	}
895 
896 	qp->bf = &uuari->bfs[uuarn];
897 	uar_index = qp->bf->uar->index;
898 
899 	err = calc_sq_size(dev, init_attr, qp);
900 	if (err < 0) {
901 		mlx5_ib_dbg(dev, "err %d\n", err);
902 		goto err_uuar;
903 	}
904 
905 	qp->rq.offset = 0;
906 	qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
907 	base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
908 
909 	err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size,
910 	    2 * PAGE_SIZE, &qp->buf);
911 	if (err) {
912 		mlx5_ib_dbg(dev, "err %d\n", err);
913 		goto err_uuar;
914 	}
915 
916 	qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
917 	*inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
918 		 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
919 	*in = mlx5_vzalloc(*inlen);
920 	if (!*in) {
921 		err = -ENOMEM;
922 		goto err_buf;
923 	}
924 
925 	qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
926 	MLX5_SET(qpc, qpc, uar_page, uar_index);
927 	MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
928 
929 	/* Set "fast registration enabled" for all kernel QPs */
930 	MLX5_SET(qpc, qpc, fre, 1);
931 	MLX5_SET(qpc, qpc, rlky, 1);
932 
933 	if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
934 		MLX5_SET(qpc, qpc, deth_sqpn, 1);
935 		qp->flags |= MLX5_IB_QP_SQPN_QP1;
936 	}
937 
938 	mlx5_fill_page_array(&qp->buf,
939 			     (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
940 
941 	err = mlx5_db_alloc(dev->mdev, &qp->db);
942 	if (err) {
943 		mlx5_ib_dbg(dev, "err %d\n", err);
944 		goto err_free;
945 	}
946 
947 	qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
948 	qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
949 	qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
950 	qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
951 	qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
952 
953 	if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
954 	    !qp->sq.w_list || !qp->sq.wqe_head) {
955 		err = -ENOMEM;
956 		goto err_wrid;
957 	}
958 	qp->create_type = MLX5_QP_KERNEL;
959 
960 	return 0;
961 
962 err_wrid:
963 	mlx5_db_free(dev->mdev, &qp->db);
964 	kfree(qp->sq.wqe_head);
965 	kfree(qp->sq.w_list);
966 	kfree(qp->sq.wrid);
967 	kfree(qp->sq.wr_data);
968 	kfree(qp->rq.wrid);
969 
970 err_free:
971 	kvfree(*in);
972 
973 err_buf:
974 	mlx5_buf_free(dev->mdev, &qp->buf);
975 
976 err_uuar:
977 	free_uuar(&dev->mdev->priv.uuari, uuarn);
978 	return err;
979 }
980 
981 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
982 {
983 	mlx5_db_free(dev->mdev, &qp->db);
984 	kfree(qp->sq.wqe_head);
985 	kfree(qp->sq.w_list);
986 	kfree(qp->sq.wrid);
987 	kfree(qp->sq.wr_data);
988 	kfree(qp->rq.wrid);
989 	mlx5_buf_free(dev->mdev, &qp->buf);
990 	free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn);
991 }
992 
993 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
994 {
995 	if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
996 	    (attr->qp_type == IB_QPT_XRC_INI))
997 		return MLX5_SRQ_RQ;
998 	else if (!qp->has_rq)
999 		return MLX5_ZERO_LEN_RQ;
1000 	else
1001 		return MLX5_NON_ZERO_RQ;
1002 }
1003 
1004 static int is_connected(enum ib_qp_type qp_type)
1005 {
1006 	if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1007 		return 1;
1008 
1009 	return 0;
1010 }
1011 
1012 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1013 				    struct mlx5_ib_sq *sq, u32 tdn)
1014 {
1015 	u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1016 	void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1017 
1018 	MLX5_SET(tisc, tisc, transport_domain, tdn);
1019 	return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1020 }
1021 
1022 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1023 				      struct mlx5_ib_sq *sq)
1024 {
1025 	mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1026 }
1027 
1028 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1029 				   struct mlx5_ib_sq *sq, void *qpin,
1030 				   struct ib_pd *pd)
1031 {
1032 	struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1033 	__be64 *pas;
1034 	void *in;
1035 	void *sqc;
1036 	void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1037 	void *wq;
1038 	int inlen;
1039 	int err;
1040 	int page_shift = 0;
1041 	int npages;
1042 	int ncont = 0;
1043 	u32 offset = 0;
1044 
1045 	err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1046 			       &sq->ubuffer.umem, &npages, &page_shift,
1047 			       &ncont, &offset);
1048 	if (err)
1049 		return err;
1050 
1051 	inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1052 	in = mlx5_vzalloc(inlen);
1053 	if (!in) {
1054 		err = -ENOMEM;
1055 		goto err_umem;
1056 	}
1057 
1058 	sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1059 	MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1060 	MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1061 	MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1062 	MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1063 	MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1064 	MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1065 
1066 	wq = MLX5_ADDR_OF(sqc, sqc, wq);
1067 	MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1068 	MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1069 	MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1070 	MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1071 	MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1072 	MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1073 	MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1074 	MLX5_SET(wq, wq, page_offset, offset);
1075 
1076 	pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1077 	mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1078 
1079 	err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1080 
1081 	kvfree(in);
1082 
1083 	if (err)
1084 		goto err_umem;
1085 
1086 	return 0;
1087 
1088 err_umem:
1089 	ib_umem_release(sq->ubuffer.umem);
1090 	sq->ubuffer.umem = NULL;
1091 
1092 	return err;
1093 }
1094 
1095 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1096 				     struct mlx5_ib_sq *sq)
1097 {
1098 	mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1099 	ib_umem_release(sq->ubuffer.umem);
1100 }
1101 
1102 static int get_rq_pas_size(void *qpc)
1103 {
1104 	u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1105 	u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1106 	u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1107 	u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1108 	u32 po_quanta	  = 1 << (log_page_size - 6);
1109 	u32 rq_sz	  = 1 << (log_rq_size + 4 + log_rq_stride);
1110 	u32 page_size	  = 1 << log_page_size;
1111 	u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1112 	u32 rq_num_pas	  = (rq_sz_po + page_size - 1) / page_size;
1113 
1114 	return rq_num_pas * sizeof(u64);
1115 }
1116 
1117 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1118 				   struct mlx5_ib_rq *rq, void *qpin)
1119 {
1120 	struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1121 	__be64 *pas;
1122 	__be64 *qp_pas;
1123 	void *in;
1124 	void *rqc;
1125 	void *wq;
1126 	void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1127 	int inlen;
1128 	int err;
1129 	u32 rq_pas_size = get_rq_pas_size(qpc);
1130 
1131 	inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1132 	in = mlx5_vzalloc(inlen);
1133 	if (!in)
1134 		return -ENOMEM;
1135 
1136 	rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1137 	MLX5_SET(rqc, rqc, vlan_strip_disable, 1);
1138 	MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE);
1139 	MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1140 	MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1141 	MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1142 	MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1143 
1144 	if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1145 		MLX5_SET(rqc, rqc, scatter_fcs, 1);
1146 
1147 	wq = MLX5_ADDR_OF(rqc, rqc, wq);
1148 	MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1149 	MLX5_SET(wq, wq, end_padding_mode,
1150 		 MLX5_GET(qpc, qpc, end_padding_mode));
1151 	MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1152 	MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1153 	MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1154 	MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1155 	MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1156 	MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1157 
1158 	pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1159 	qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1160 	memcpy(pas, qp_pas, rq_pas_size);
1161 
1162 	err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1163 
1164 	kvfree(in);
1165 
1166 	return err;
1167 }
1168 
1169 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1170 				     struct mlx5_ib_rq *rq)
1171 {
1172 	mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1173 }
1174 
1175 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1176 				    struct mlx5_ib_rq *rq, u32 tdn)
1177 {
1178 	u32 *in;
1179 	void *tirc;
1180 	int inlen;
1181 	int err;
1182 
1183 	inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1184 	in = mlx5_vzalloc(inlen);
1185 	if (!in)
1186 		return -ENOMEM;
1187 
1188 	tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
1189 	MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1190 	MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1191 	MLX5_SET(tirc, tirc, transport_domain, tdn);
1192 
1193 	err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1194 
1195 	kvfree(in);
1196 
1197 	return err;
1198 }
1199 
1200 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1201 				      struct mlx5_ib_rq *rq)
1202 {
1203 	mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1204 }
1205 
1206 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1207 				u32 *in,
1208 				struct ib_pd *pd)
1209 {
1210 	struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1211 	struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1212 	struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1213 	struct ib_uobject *uobj = pd->uobject;
1214 	struct ib_ucontext *ucontext = uobj->context;
1215 	struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1216 	int err;
1217 	u32 tdn = mucontext->tdn;
1218 
1219 	if (qp->sq.wqe_cnt) {
1220 		err = create_raw_packet_qp_tis(dev, sq, tdn);
1221 		if (err)
1222 			return err;
1223 
1224 		err = create_raw_packet_qp_sq(dev, sq, in, pd);
1225 		if (err)
1226 			goto err_destroy_tis;
1227 
1228 		sq->base.container_mibqp = qp;
1229 	}
1230 
1231 	if (qp->rq.wqe_cnt) {
1232 		rq->base.container_mibqp = qp;
1233 
1234 		err = create_raw_packet_qp_rq(dev, rq, in);
1235 		if (err)
1236 			goto err_destroy_sq;
1237 
1238 
1239 		err = create_raw_packet_qp_tir(dev, rq, tdn);
1240 		if (err)
1241 			goto err_destroy_rq;
1242 	}
1243 
1244 	qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1245 						     rq->base.mqp.qpn;
1246 
1247 	return 0;
1248 
1249 err_destroy_rq:
1250 	destroy_raw_packet_qp_rq(dev, rq);
1251 err_destroy_sq:
1252 	if (!qp->sq.wqe_cnt)
1253 		return err;
1254 	destroy_raw_packet_qp_sq(dev, sq);
1255 err_destroy_tis:
1256 	destroy_raw_packet_qp_tis(dev, sq);
1257 
1258 	return err;
1259 }
1260 
1261 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1262 				  struct mlx5_ib_qp *qp)
1263 {
1264 	struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1265 	struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1266 	struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1267 
1268 	if (qp->rq.wqe_cnt) {
1269 		destroy_raw_packet_qp_tir(dev, rq);
1270 		destroy_raw_packet_qp_rq(dev, rq);
1271 	}
1272 
1273 	if (qp->sq.wqe_cnt) {
1274 		destroy_raw_packet_qp_sq(dev, sq);
1275 		destroy_raw_packet_qp_tis(dev, sq);
1276 	}
1277 }
1278 
1279 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1280 				    struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1281 {
1282 	struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1283 	struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1284 
1285 	sq->sq = &qp->sq;
1286 	rq->rq = &qp->rq;
1287 	sq->doorbell = &qp->db;
1288 	rq->doorbell = &qp->db;
1289 }
1290 
1291 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1292 {
1293 	mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1294 }
1295 
1296 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1297 				 struct ib_pd *pd,
1298 				 struct ib_qp_init_attr *init_attr,
1299 				 struct ib_udata *udata)
1300 {
1301 	struct ib_uobject *uobj = pd->uobject;
1302 	struct ib_ucontext *ucontext = uobj->context;
1303 	struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1304 	struct mlx5_ib_create_qp_resp resp = {};
1305 	int inlen;
1306 	int err;
1307 	u32 *in;
1308 	void *tirc;
1309 	void *hfso;
1310 	u32 selected_fields = 0;
1311 	size_t min_resp_len;
1312 	u32 tdn = mucontext->tdn;
1313 	struct mlx5_ib_create_qp_rss ucmd = {};
1314 	size_t required_cmd_sz;
1315 
1316 	if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1317 		return -EOPNOTSUPP;
1318 
1319 	if (init_attr->create_flags || init_attr->send_cq)
1320 		return -EINVAL;
1321 
1322 	min_resp_len = offsetof(typeof(resp), uuar_index) + sizeof(resp.uuar_index);
1323 	if (udata->outlen < min_resp_len)
1324 		return -EINVAL;
1325 
1326 	required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1);
1327 	if (udata->inlen < required_cmd_sz) {
1328 		mlx5_ib_dbg(dev, "invalid inlen\n");
1329 		return -EINVAL;
1330 	}
1331 
1332 	if (udata->inlen > sizeof(ucmd) &&
1333 	    !ib_is_udata_cleared(udata, sizeof(ucmd),
1334 				 udata->inlen - sizeof(ucmd))) {
1335 		mlx5_ib_dbg(dev, "inlen is not supported\n");
1336 		return -EOPNOTSUPP;
1337 	}
1338 
1339 	if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1340 		mlx5_ib_dbg(dev, "copy failed\n");
1341 		return -EFAULT;
1342 	}
1343 
1344 	if (ucmd.comp_mask) {
1345 		mlx5_ib_dbg(dev, "invalid comp mask\n");
1346 		return -EOPNOTSUPP;
1347 	}
1348 
1349 	if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) {
1350 		mlx5_ib_dbg(dev, "invalid reserved\n");
1351 		return -EOPNOTSUPP;
1352 	}
1353 
1354 	err = ib_copy_to_udata(udata, &resp, min_resp_len);
1355 	if (err) {
1356 		mlx5_ib_dbg(dev, "copy failed\n");
1357 		return -EINVAL;
1358 	}
1359 
1360 	inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1361 	in = mlx5_vzalloc(inlen);
1362 	if (!in)
1363 		return -ENOMEM;
1364 
1365 	tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
1366 	MLX5_SET(tirc, tirc, disp_type,
1367 		 MLX5_TIRC_DISP_TYPE_INDIRECT);
1368 	MLX5_SET(tirc, tirc, indirect_table,
1369 		 init_attr->rwq_ind_tbl->ind_tbl_num);
1370 	MLX5_SET(tirc, tirc, transport_domain, tdn);
1371 
1372 	hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1373 	switch (ucmd.rx_hash_function) {
1374 	case MLX5_RX_HASH_FUNC_TOEPLITZ:
1375 	{
1376 		void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1377 		size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1378 
1379 		if (len != ucmd.rx_key_len) {
1380 			err = -EINVAL;
1381 			goto err;
1382 		}
1383 
1384 		MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FUNC_TOEPLITZ);
1385 		MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1386 		memcpy(rss_key, ucmd.rx_hash_key, len);
1387 		break;
1388 	}
1389 	default:
1390 		err = -EOPNOTSUPP;
1391 		goto err;
1392 	}
1393 
1394 	if (!ucmd.rx_hash_fields_mask) {
1395 		/* special case when this TIR serves as steering entry without hashing */
1396 		if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1397 			goto create_tir;
1398 		err = -EINVAL;
1399 		goto err;
1400 	}
1401 
1402 	if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1403 	     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1404 	     ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1405 	     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1406 		err = -EINVAL;
1407 		goto err;
1408 	}
1409 
1410 	/* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1411 	if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1412 	    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1413 		MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1414 			 MLX5_L3_PROT_TYPE_IPV4);
1415 	else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1416 		 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1417 		MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1418 			 MLX5_L3_PROT_TYPE_IPV6);
1419 
1420 	if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1421 	     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1422 	     ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1423 	     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1424 		err = -EINVAL;
1425 		goto err;
1426 	}
1427 
1428 	/* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1429 	if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1430 	    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1431 		MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1432 			 MLX5_L4_PROT_TYPE_TCP);
1433 	else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1434 		 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1435 		MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1436 			 MLX5_L4_PROT_TYPE_UDP);
1437 
1438 	if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1439 	    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1440 		selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1441 
1442 	if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1443 	    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1444 		selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1445 
1446 	if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1447 	    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1448 		selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1449 
1450 	if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1451 	    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1452 		selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1453 
1454 	MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1455 
1456 create_tir:
1457 	err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1458 
1459 	if (err)
1460 		goto err;
1461 
1462 	kvfree(in);
1463 	/* qpn is reserved for that QP */
1464 	qp->trans_qp.base.mqp.qpn = 0;
1465 	qp->flags |= MLX5_IB_QP_RSS;
1466 	return 0;
1467 
1468 err:
1469 	kvfree(in);
1470 	return err;
1471 }
1472 
1473 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1474 			    struct ib_qp_init_attr *init_attr,
1475 			    struct ib_udata *udata, struct mlx5_ib_qp *qp)
1476 {
1477 	struct mlx5_ib_resources *devr = &dev->devr;
1478 	int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1479 	struct mlx5_core_dev *mdev = dev->mdev;
1480 	struct mlx5_ib_create_qp_resp resp;
1481 	struct mlx5_ib_cq *send_cq;
1482 	struct mlx5_ib_cq *recv_cq;
1483 	unsigned long flags;
1484 	u32 uidx = MLX5_IB_DEFAULT_UIDX;
1485 	struct mlx5_ib_create_qp ucmd;
1486 	struct mlx5_ib_qp_base *base;
1487 	void *qpc;
1488 	u32 *in;
1489 	int err;
1490 
1491 	base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1492 	       &qp->raw_packet_qp.rq.base :
1493 	       &qp->trans_qp.base;
1494 
1495 	if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1496 		mlx5_ib_odp_create_qp(qp);
1497 
1498 	mutex_init(&qp->mutex);
1499 	spin_lock_init(&qp->sq.lock);
1500 	spin_lock_init(&qp->rq.lock);
1501 
1502 	if (init_attr->rwq_ind_tbl) {
1503 		if (!udata)
1504 			return -ENOSYS;
1505 
1506 		err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1507 		return err;
1508 	}
1509 
1510 	if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1511 		if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1512 			mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1513 			return -EINVAL;
1514 		} else {
1515 			qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1516 		}
1517 	}
1518 
1519 	if (init_attr->create_flags &
1520 			(IB_QP_CREATE_CROSS_CHANNEL |
1521 			 IB_QP_CREATE_MANAGED_SEND |
1522 			 IB_QP_CREATE_MANAGED_RECV)) {
1523 		if (!MLX5_CAP_GEN(mdev, cd)) {
1524 			mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1525 			return -EINVAL;
1526 		}
1527 		if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1528 			qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1529 		if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1530 			qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1531 		if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1532 			qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1533 	}
1534 
1535 	if (init_attr->qp_type == IB_QPT_UD &&
1536 	    (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1537 		if (!MLX5_CAP_GEN(mdev, ipoib_ipoib_offloads)) {
1538 			mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1539 			return -EOPNOTSUPP;
1540 		}
1541 
1542 	if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1543 		if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1544 			mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1545 			return -EOPNOTSUPP;
1546 		}
1547 		if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1548 		    !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1549 			mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1550 			return -EOPNOTSUPP;
1551 		}
1552 		qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1553 	}
1554 
1555 	if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1556 		qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1557 
1558 	if (pd && pd->uobject) {
1559 		if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1560 			mlx5_ib_dbg(dev, "copy failed\n");
1561 			return -EFAULT;
1562 		}
1563 
1564 		err = get_qp_user_index(to_mucontext(pd->uobject->context),
1565 					&ucmd, udata->inlen, &uidx);
1566 		if (err)
1567 			return err;
1568 
1569 		qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1570 		qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1571 	} else {
1572 		qp->wq_sig = !!wq_signature;
1573 	}
1574 
1575 	qp->has_rq = qp_has_rq(init_attr);
1576 	err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1577 			  qp, (pd && pd->uobject) ? &ucmd : NULL);
1578 	if (err) {
1579 		mlx5_ib_dbg(dev, "err %d\n", err);
1580 		return err;
1581 	}
1582 
1583 	if (pd) {
1584 		if (pd->uobject) {
1585 			__u32 max_wqes =
1586 				1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1587 			mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1588 			if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1589 			    ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1590 				mlx5_ib_dbg(dev, "invalid rq params\n");
1591 				return -EINVAL;
1592 			}
1593 			if (ucmd.sq_wqe_count > max_wqes) {
1594 				mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1595 					    ucmd.sq_wqe_count, max_wqes);
1596 				return -EINVAL;
1597 			}
1598 			if (init_attr->create_flags &
1599 			    mlx5_ib_create_qp_sqpn_qp1()) {
1600 				mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1601 				return -EINVAL;
1602 			}
1603 			err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1604 					     &resp, &inlen, base);
1605 			if (err)
1606 				mlx5_ib_dbg(dev, "err %d\n", err);
1607 		} else {
1608 			err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1609 					       base);
1610 			if (err)
1611 				mlx5_ib_dbg(dev, "err %d\n", err);
1612 		}
1613 
1614 		if (err)
1615 			return err;
1616 	} else {
1617 		in = mlx5_vzalloc(inlen);
1618 		if (!in)
1619 			return -ENOMEM;
1620 
1621 		qp->create_type = MLX5_QP_EMPTY;
1622 	}
1623 
1624 	if (is_sqp(init_attr->qp_type))
1625 		qp->port = init_attr->port_num;
1626 
1627 	qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1628 
1629 	MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type));
1630 	MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1631 
1632 	if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1633 		MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1634 	else
1635 		MLX5_SET(qpc, qpc, latency_sensitive, 1);
1636 
1637 
1638 	if (qp->wq_sig)
1639 		MLX5_SET(qpc, qpc, wq_signature, 1);
1640 
1641 	if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1642 		MLX5_SET(qpc, qpc, block_lb_mc, 1);
1643 
1644 	if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1645 		MLX5_SET(qpc, qpc, cd_master, 1);
1646 	if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1647 		MLX5_SET(qpc, qpc, cd_slave_send, 1);
1648 	if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1649 		MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1650 
1651 	if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1652 		int rcqe_sz;
1653 		int scqe_sz;
1654 
1655 		rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1656 		scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1657 
1658 		if (rcqe_sz == 128)
1659 			MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1660 		else
1661 			MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1662 
1663 		if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1664 			if (scqe_sz == 128)
1665 				MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1666 			else
1667 				MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1668 		}
1669 	}
1670 
1671 	if (qp->rq.wqe_cnt) {
1672 		MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1673 		MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1674 	}
1675 
1676 	MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1677 
1678 	if (qp->sq.wqe_cnt)
1679 		MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1680 	else
1681 		MLX5_SET(qpc, qpc, no_sq, 1);
1682 
1683 	/* Set default resources */
1684 	switch (init_attr->qp_type) {
1685 	case IB_QPT_XRC_TGT:
1686 		MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1687 		MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1688 		MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s0)->msrq.srqn);
1689 		MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1690 		break;
1691 	case IB_QPT_XRC_INI:
1692 		MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1693 		MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1694 		MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s0)->msrq.srqn);
1695 		break;
1696 	default:
1697 		if (init_attr->srq) {
1698 			MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1699 			MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(init_attr->srq)->msrq.srqn);
1700 		} else {
1701 			MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1702 			MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s1)->msrq.srqn);
1703 		}
1704 	}
1705 
1706 	if (init_attr->send_cq)
1707 		MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1708 
1709 	if (init_attr->recv_cq)
1710 		MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1711 
1712 	MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1713 
1714 	/* 0xffffff means we ask to work with cqe version 0 */
1715 	if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1716 		MLX5_SET(qpc, qpc, user_index, uidx);
1717 
1718 	/* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1719 	if (init_attr->qp_type == IB_QPT_UD &&
1720 	    (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1721 		MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1722 		qp->flags |= MLX5_IB_QP_LSO;
1723 	}
1724 
1725 	if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1726 		qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1727 		raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1728 		err = create_raw_packet_qp(dev, qp, in, pd);
1729 	} else {
1730 		err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1731 	}
1732 
1733 	if (err) {
1734 		mlx5_ib_dbg(dev, "create qp failed\n");
1735 		goto err_create;
1736 	}
1737 
1738 	kvfree(in);
1739 
1740 	base->container_mibqp = qp;
1741 	base->mqp.event = mlx5_ib_qp_event;
1742 
1743 	get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1744 		&send_cq, &recv_cq);
1745 	spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1746 	mlx5_ib_lock_cqs(send_cq, recv_cq);
1747 	/* Maintain device to QPs access, needed for further handling via reset
1748 	 * flow
1749 	 */
1750 	list_add_tail(&qp->qps_list, &dev->qp_list);
1751 	/* Maintain CQ to QPs access, needed for further handling via reset flow
1752 	 */
1753 	if (send_cq)
1754 		list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1755 	if (recv_cq)
1756 		list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1757 	mlx5_ib_unlock_cqs(send_cq, recv_cq);
1758 	spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1759 
1760 	return 0;
1761 
1762 err_create:
1763 	if (qp->create_type == MLX5_QP_USER)
1764 		destroy_qp_user(pd, qp, base);
1765 	else if (qp->create_type == MLX5_QP_KERNEL)
1766 		destroy_qp_kernel(dev, qp);
1767 
1768 	kvfree(in);
1769 	return err;
1770 }
1771 
1772 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1773 	__acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1774 {
1775 	if (send_cq) {
1776 		if (recv_cq) {
1777 			if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1778 				spin_lock(&send_cq->lock);
1779 				spin_lock_nested(&recv_cq->lock,
1780 						 SINGLE_DEPTH_NESTING);
1781 			} else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1782 				spin_lock(&send_cq->lock);
1783 				__acquire(&recv_cq->lock);
1784 			} else {
1785 				spin_lock(&recv_cq->lock);
1786 				spin_lock_nested(&send_cq->lock,
1787 						 SINGLE_DEPTH_NESTING);
1788 			}
1789 		} else {
1790 			spin_lock(&send_cq->lock);
1791 			__acquire(&recv_cq->lock);
1792 		}
1793 	} else if (recv_cq) {
1794 		spin_lock(&recv_cq->lock);
1795 		__acquire(&send_cq->lock);
1796 	} else {
1797 		__acquire(&send_cq->lock);
1798 		__acquire(&recv_cq->lock);
1799 	}
1800 }
1801 
1802 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1803 	__releases(&send_cq->lock) __releases(&recv_cq->lock)
1804 {
1805 	if (send_cq) {
1806 		if (recv_cq) {
1807 			if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
1808 				spin_unlock(&recv_cq->lock);
1809 				spin_unlock(&send_cq->lock);
1810 			} else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1811 				__release(&recv_cq->lock);
1812 				spin_unlock(&send_cq->lock);
1813 			} else {
1814 				spin_unlock(&send_cq->lock);
1815 				spin_unlock(&recv_cq->lock);
1816 			}
1817 		} else {
1818 			__release(&recv_cq->lock);
1819 			spin_unlock(&send_cq->lock);
1820 		}
1821 	} else if (recv_cq) {
1822 		__release(&send_cq->lock);
1823 		spin_unlock(&recv_cq->lock);
1824 	} else {
1825 		__release(&recv_cq->lock);
1826 		__release(&send_cq->lock);
1827 	}
1828 }
1829 
1830 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1831 {
1832 	return to_mpd(qp->ibqp.pd);
1833 }
1834 
1835 static void get_cqs(enum ib_qp_type qp_type,
1836 		    struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
1837 		    struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1838 {
1839 	switch (qp_type) {
1840 	case IB_QPT_XRC_TGT:
1841 		*send_cq = NULL;
1842 		*recv_cq = NULL;
1843 		break;
1844 	case MLX5_IB_QPT_REG_UMR:
1845 	case IB_QPT_XRC_INI:
1846 		*send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1847 		*recv_cq = NULL;
1848 		break;
1849 
1850 	case IB_QPT_SMI:
1851 	case MLX5_IB_QPT_HW_GSI:
1852 	case IB_QPT_RC:
1853 	case IB_QPT_UC:
1854 	case IB_QPT_UD:
1855 	case IB_QPT_RAW_IPV6:
1856 	case IB_QPT_RAW_ETHERTYPE:
1857 	case IB_QPT_RAW_PACKET:
1858 		*send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1859 		*recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
1860 		break;
1861 
1862 	case IB_QPT_MAX:
1863 	default:
1864 		*send_cq = NULL;
1865 		*recv_cq = NULL;
1866 		break;
1867 	}
1868 }
1869 
1870 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1871 				const struct mlx5_modify_raw_qp_param *raw_qp_param,
1872 				u8 lag_tx_affinity);
1873 
1874 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1875 {
1876 	struct mlx5_ib_cq *send_cq, *recv_cq;
1877 	struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
1878 	unsigned long flags;
1879 	int err;
1880 
1881 	if (qp->ibqp.rwq_ind_tbl) {
1882 		destroy_rss_raw_qp_tir(dev, qp);
1883 		return;
1884 	}
1885 
1886 	base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1887 	       &qp->raw_packet_qp.rq.base :
1888 	       &qp->trans_qp.base;
1889 
1890 	if (qp->state != IB_QPS_RESET) {
1891 		if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
1892 			mlx5_ib_qp_disable_pagefaults(qp);
1893 			err = mlx5_core_qp_modify(dev->mdev,
1894 						  MLX5_CMD_OP_2RST_QP, 0,
1895 						  NULL, &base->mqp);
1896 		} else {
1897 			struct mlx5_modify_raw_qp_param raw_qp_param = {
1898 				.operation = MLX5_CMD_OP_2RST_QP
1899 			};
1900 
1901 			err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
1902 		}
1903 		if (err)
1904 			mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
1905 				     base->mqp.qpn);
1906 	}
1907 
1908 	get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
1909 		&send_cq, &recv_cq);
1910 
1911 	spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1912 	mlx5_ib_lock_cqs(send_cq, recv_cq);
1913 	/* del from lists under both locks above to protect reset flow paths */
1914 	list_del(&qp->qps_list);
1915 	if (send_cq)
1916 		list_del(&qp->cq_send_list);
1917 
1918 	if (recv_cq)
1919 		list_del(&qp->cq_recv_list);
1920 
1921 	if (qp->create_type == MLX5_QP_KERNEL) {
1922 		__mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
1923 				   qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1924 		if (send_cq != recv_cq)
1925 			__mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1926 					   NULL);
1927 	}
1928 	mlx5_ib_unlock_cqs(send_cq, recv_cq);
1929 	spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1930 
1931 	if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1932 		destroy_raw_packet_qp(dev, qp);
1933 	} else {
1934 		err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1935 		if (err)
1936 			mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1937 				     base->mqp.qpn);
1938 	}
1939 
1940 	if (qp->create_type == MLX5_QP_KERNEL)
1941 		destroy_qp_kernel(dev, qp);
1942 	else if (qp->create_type == MLX5_QP_USER)
1943 		destroy_qp_user(&get_pd(qp)->ibpd, qp, base);
1944 }
1945 
1946 static const char *ib_qp_type_str(enum ib_qp_type type)
1947 {
1948 	switch (type) {
1949 	case IB_QPT_SMI:
1950 		return "IB_QPT_SMI";
1951 	case IB_QPT_GSI:
1952 		return "IB_QPT_GSI";
1953 	case IB_QPT_RC:
1954 		return "IB_QPT_RC";
1955 	case IB_QPT_UC:
1956 		return "IB_QPT_UC";
1957 	case IB_QPT_UD:
1958 		return "IB_QPT_UD";
1959 	case IB_QPT_RAW_IPV6:
1960 		return "IB_QPT_RAW_IPV6";
1961 	case IB_QPT_RAW_ETHERTYPE:
1962 		return "IB_QPT_RAW_ETHERTYPE";
1963 	case IB_QPT_XRC_INI:
1964 		return "IB_QPT_XRC_INI";
1965 	case IB_QPT_XRC_TGT:
1966 		return "IB_QPT_XRC_TGT";
1967 	case IB_QPT_RAW_PACKET:
1968 		return "IB_QPT_RAW_PACKET";
1969 	case MLX5_IB_QPT_REG_UMR:
1970 		return "MLX5_IB_QPT_REG_UMR";
1971 	case IB_QPT_MAX:
1972 	default:
1973 		return "Invalid QP type";
1974 	}
1975 }
1976 
1977 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1978 				struct ib_qp_init_attr *init_attr,
1979 				struct ib_udata *udata)
1980 {
1981 	struct mlx5_ib_dev *dev;
1982 	struct mlx5_ib_qp *qp;
1983 	u16 xrcdn = 0;
1984 	int err;
1985 
1986 	if (pd) {
1987 		dev = to_mdev(pd->device);
1988 
1989 		if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1990 			if (!pd->uobject) {
1991 				mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
1992 				return ERR_PTR(-EINVAL);
1993 			} else if (!to_mucontext(pd->uobject->context)->cqe_version) {
1994 				mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
1995 				return ERR_PTR(-EINVAL);
1996 			}
1997 		}
1998 	} else {
1999 		/* being cautious here */
2000 		if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2001 		    init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2002 			pr_warn("%s: no PD for transport %s\n", __func__,
2003 				ib_qp_type_str(init_attr->qp_type));
2004 			return ERR_PTR(-EINVAL);
2005 		}
2006 		dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2007 	}
2008 
2009 	switch (init_attr->qp_type) {
2010 	case IB_QPT_XRC_TGT:
2011 	case IB_QPT_XRC_INI:
2012 		if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2013 			mlx5_ib_dbg(dev, "XRC not supported\n");
2014 			return ERR_PTR(-ENOSYS);
2015 		}
2016 		init_attr->recv_cq = NULL;
2017 		if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2018 			xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2019 			init_attr->send_cq = NULL;
2020 		}
2021 
2022 		/* fall through */
2023 	case IB_QPT_RAW_PACKET:
2024 	case IB_QPT_RC:
2025 	case IB_QPT_UC:
2026 	case IB_QPT_UD:
2027 	case IB_QPT_SMI:
2028 	case MLX5_IB_QPT_HW_GSI:
2029 	case MLX5_IB_QPT_REG_UMR:
2030 		qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2031 		if (!qp)
2032 			return ERR_PTR(-ENOMEM);
2033 
2034 		err = create_qp_common(dev, pd, init_attr, udata, qp);
2035 		if (err) {
2036 			mlx5_ib_dbg(dev, "create_qp_common failed\n");
2037 			kfree(qp);
2038 			return ERR_PTR(err);
2039 		}
2040 
2041 		if (is_qp0(init_attr->qp_type))
2042 			qp->ibqp.qp_num = 0;
2043 		else if (is_qp1(init_attr->qp_type))
2044 			qp->ibqp.qp_num = 1;
2045 		else
2046 			qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2047 
2048 		mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2049 			    qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2050 			    init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2051 			    init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2052 
2053 		qp->trans_qp.xrcdn = xrcdn;
2054 
2055 		break;
2056 
2057 	case IB_QPT_GSI:
2058 		return mlx5_ib_gsi_create_qp(pd, init_attr);
2059 
2060 	case IB_QPT_RAW_IPV6:
2061 	case IB_QPT_RAW_ETHERTYPE:
2062 	case IB_QPT_MAX:
2063 	default:
2064 		mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2065 			    init_attr->qp_type);
2066 		/* Don't support raw QPs */
2067 		return ERR_PTR(-EINVAL);
2068 	}
2069 
2070 	return &qp->ibqp;
2071 }
2072 
2073 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2074 {
2075 	struct mlx5_ib_dev *dev = to_mdev(qp->device);
2076 	struct mlx5_ib_qp *mqp = to_mqp(qp);
2077 
2078 	if (unlikely(qp->qp_type == IB_QPT_GSI))
2079 		return mlx5_ib_gsi_destroy_qp(qp);
2080 
2081 	destroy_qp_common(dev, mqp);
2082 
2083 	kfree(mqp);
2084 
2085 	return 0;
2086 }
2087 
2088 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2089 				   int attr_mask)
2090 {
2091 	u32 hw_access_flags = 0;
2092 	u8 dest_rd_atomic;
2093 	u32 access_flags;
2094 
2095 	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2096 		dest_rd_atomic = attr->max_dest_rd_atomic;
2097 	else
2098 		dest_rd_atomic = qp->trans_qp.resp_depth;
2099 
2100 	if (attr_mask & IB_QP_ACCESS_FLAGS)
2101 		access_flags = attr->qp_access_flags;
2102 	else
2103 		access_flags = qp->trans_qp.atomic_rd_en;
2104 
2105 	if (!dest_rd_atomic)
2106 		access_flags &= IB_ACCESS_REMOTE_WRITE;
2107 
2108 	if (access_flags & IB_ACCESS_REMOTE_READ)
2109 		hw_access_flags |= MLX5_QP_BIT_RRE;
2110 	if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2111 		hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2112 	if (access_flags & IB_ACCESS_REMOTE_WRITE)
2113 		hw_access_flags |= MLX5_QP_BIT_RWE;
2114 
2115 	return cpu_to_be32(hw_access_flags);
2116 }
2117 
2118 enum {
2119 	MLX5_PATH_FLAG_FL	= 1 << 0,
2120 	MLX5_PATH_FLAG_FREE_AR	= 1 << 1,
2121 	MLX5_PATH_FLAG_COUNTER	= 1 << 2,
2122 };
2123 
2124 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2125 {
2126 	if (rate == IB_RATE_PORT_CURRENT) {
2127 		return 0;
2128 	} else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2129 		return -EINVAL;
2130 	} else {
2131 		while (rate != IB_RATE_2_5_GBPS &&
2132 		       !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2133 			 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2134 			--rate;
2135 	}
2136 
2137 	return rate + MLX5_STAT_RATE_OFFSET;
2138 }
2139 
2140 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2141 				      struct mlx5_ib_sq *sq, u8 sl)
2142 {
2143 	void *in;
2144 	void *tisc;
2145 	int inlen;
2146 	int err;
2147 
2148 	inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2149 	in = mlx5_vzalloc(inlen);
2150 	if (!in)
2151 		return -ENOMEM;
2152 
2153 	MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2154 
2155 	tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2156 	MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2157 
2158 	err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2159 
2160 	kvfree(in);
2161 
2162 	return err;
2163 }
2164 
2165 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2166 					 struct mlx5_ib_sq *sq, u8 tx_affinity)
2167 {
2168 	void *in;
2169 	void *tisc;
2170 	int inlen;
2171 	int err;
2172 
2173 	inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2174 	in = mlx5_vzalloc(inlen);
2175 	if (!in)
2176 		return -ENOMEM;
2177 
2178 	MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2179 
2180 	tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2181 	MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2182 
2183 	err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2184 
2185 	kvfree(in);
2186 
2187 	return err;
2188 }
2189 
2190 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2191 			 const struct ib_ah_attr *ah,
2192 			 struct mlx5_qp_path *path, u8 port, int attr_mask,
2193 			 u32 path_flags, const struct ib_qp_attr *attr,
2194 			 bool alt)
2195 {
2196 	enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2197 	int err;
2198 	enum ib_gid_type gid_type;
2199 
2200 	if (attr_mask & IB_QP_PKEY_INDEX)
2201 		path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2202 						     attr->pkey_index);
2203 
2204 	if (ah->ah_flags & IB_AH_GRH) {
2205 		if (ah->grh.sgid_index >=
2206 		    dev->mdev->port_caps[port - 1].gid_table_len) {
2207 			pr_err("sgid_index (%u) too large. max is %d\n",
2208 			       ah->grh.sgid_index,
2209 			       dev->mdev->port_caps[port - 1].gid_table_len);
2210 			return -EINVAL;
2211 		}
2212 	}
2213 
2214 	if (ll == IB_LINK_LAYER_ETHERNET) {
2215 		if (!(ah->ah_flags & IB_AH_GRH))
2216 			return -EINVAL;
2217 		err = mlx5_get_roce_gid_type(dev, port, ah->grh.sgid_index,
2218 					     &gid_type);
2219 		if (err)
2220 			return err;
2221 		memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));
2222 		path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2223 							  ah->grh.sgid_index);
2224 		path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;
2225 		if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2226 			path->ecn_dscp = (ah->grh.traffic_class >> 2) & 0x3f;
2227 	} else {
2228 		path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2229 		path->fl_free_ar |=
2230 			(path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2231 		path->rlid = cpu_to_be16(ah->dlid);
2232 		path->grh_mlid = ah->src_path_bits & 0x7f;
2233 		if (ah->ah_flags & IB_AH_GRH)
2234 			path->grh_mlid	|= 1 << 7;
2235 		path->dci_cfi_prio_sl = ah->sl & 0xf;
2236 	}
2237 
2238 	if (ah->ah_flags & IB_AH_GRH) {
2239 		path->mgid_index = ah->grh.sgid_index;
2240 		path->hop_limit  = ah->grh.hop_limit;
2241 		path->tclass_flowlabel =
2242 			cpu_to_be32((ah->grh.traffic_class << 20) |
2243 				    (ah->grh.flow_label));
2244 		memcpy(path->rgid, ah->grh.dgid.raw, 16);
2245 	}
2246 
2247 	err = ib_rate_to_mlx5(dev, ah->static_rate);
2248 	if (err < 0)
2249 		return err;
2250 	path->static_rate = err;
2251 	path->port = port;
2252 
2253 	if (attr_mask & IB_QP_TIMEOUT)
2254 		path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2255 
2256 	if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2257 		return modify_raw_packet_eth_prio(dev->mdev,
2258 						  &qp->raw_packet_qp.sq,
2259 						  ah->sl & 0xf);
2260 
2261 	return 0;
2262 }
2263 
2264 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2265 	[MLX5_QP_STATE_INIT] = {
2266 		[MLX5_QP_STATE_INIT] = {
2267 			[MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE		|
2268 					  MLX5_QP_OPTPAR_RAE		|
2269 					  MLX5_QP_OPTPAR_RWE		|
2270 					  MLX5_QP_OPTPAR_PKEY_INDEX	|
2271 					  MLX5_QP_OPTPAR_PRI_PORT,
2272 			[MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE		|
2273 					  MLX5_QP_OPTPAR_PKEY_INDEX	|
2274 					  MLX5_QP_OPTPAR_PRI_PORT,
2275 			[MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX	|
2276 					  MLX5_QP_OPTPAR_Q_KEY		|
2277 					  MLX5_QP_OPTPAR_PRI_PORT,
2278 		},
2279 		[MLX5_QP_STATE_RTR] = {
2280 			[MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2281 					  MLX5_QP_OPTPAR_RRE            |
2282 					  MLX5_QP_OPTPAR_RAE            |
2283 					  MLX5_QP_OPTPAR_RWE            |
2284 					  MLX5_QP_OPTPAR_PKEY_INDEX,
2285 			[MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2286 					  MLX5_QP_OPTPAR_RWE            |
2287 					  MLX5_QP_OPTPAR_PKEY_INDEX,
2288 			[MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2289 					  MLX5_QP_OPTPAR_Q_KEY,
2290 			[MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX	|
2291 					   MLX5_QP_OPTPAR_Q_KEY,
2292 			[MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2293 					  MLX5_QP_OPTPAR_RRE            |
2294 					  MLX5_QP_OPTPAR_RAE            |
2295 					  MLX5_QP_OPTPAR_RWE            |
2296 					  MLX5_QP_OPTPAR_PKEY_INDEX,
2297 		},
2298 	},
2299 	[MLX5_QP_STATE_RTR] = {
2300 		[MLX5_QP_STATE_RTS] = {
2301 			[MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH	|
2302 					  MLX5_QP_OPTPAR_RRE		|
2303 					  MLX5_QP_OPTPAR_RAE		|
2304 					  MLX5_QP_OPTPAR_RWE		|
2305 					  MLX5_QP_OPTPAR_PM_STATE	|
2306 					  MLX5_QP_OPTPAR_RNR_TIMEOUT,
2307 			[MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH	|
2308 					  MLX5_QP_OPTPAR_RWE		|
2309 					  MLX5_QP_OPTPAR_PM_STATE,
2310 			[MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2311 		},
2312 	},
2313 	[MLX5_QP_STATE_RTS] = {
2314 		[MLX5_QP_STATE_RTS] = {
2315 			[MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE		|
2316 					  MLX5_QP_OPTPAR_RAE		|
2317 					  MLX5_QP_OPTPAR_RWE		|
2318 					  MLX5_QP_OPTPAR_RNR_TIMEOUT	|
2319 					  MLX5_QP_OPTPAR_PM_STATE	|
2320 					  MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2321 			[MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE		|
2322 					  MLX5_QP_OPTPAR_PM_STATE	|
2323 					  MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2324 			[MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY		|
2325 					  MLX5_QP_OPTPAR_SRQN		|
2326 					  MLX5_QP_OPTPAR_CQN_RCV,
2327 		},
2328 	},
2329 	[MLX5_QP_STATE_SQER] = {
2330 		[MLX5_QP_STATE_RTS] = {
2331 			[MLX5_QP_ST_UD]	 = MLX5_QP_OPTPAR_Q_KEY,
2332 			[MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2333 			[MLX5_QP_ST_UC]	 = MLX5_QP_OPTPAR_RWE,
2334 			[MLX5_QP_ST_RC]	 = MLX5_QP_OPTPAR_RNR_TIMEOUT	|
2335 					   MLX5_QP_OPTPAR_RWE		|
2336 					   MLX5_QP_OPTPAR_RAE		|
2337 					   MLX5_QP_OPTPAR_RRE,
2338 		},
2339 	},
2340 };
2341 
2342 static int ib_nr_to_mlx5_nr(int ib_mask)
2343 {
2344 	switch (ib_mask) {
2345 	case IB_QP_STATE:
2346 		return 0;
2347 	case IB_QP_CUR_STATE:
2348 		return 0;
2349 	case IB_QP_EN_SQD_ASYNC_NOTIFY:
2350 		return 0;
2351 	case IB_QP_ACCESS_FLAGS:
2352 		return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2353 			MLX5_QP_OPTPAR_RAE;
2354 	case IB_QP_PKEY_INDEX:
2355 		return MLX5_QP_OPTPAR_PKEY_INDEX;
2356 	case IB_QP_PORT:
2357 		return MLX5_QP_OPTPAR_PRI_PORT;
2358 	case IB_QP_QKEY:
2359 		return MLX5_QP_OPTPAR_Q_KEY;
2360 	case IB_QP_AV:
2361 		return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2362 			MLX5_QP_OPTPAR_PRI_PORT;
2363 	case IB_QP_PATH_MTU:
2364 		return 0;
2365 	case IB_QP_TIMEOUT:
2366 		return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2367 	case IB_QP_RETRY_CNT:
2368 		return MLX5_QP_OPTPAR_RETRY_COUNT;
2369 	case IB_QP_RNR_RETRY:
2370 		return MLX5_QP_OPTPAR_RNR_RETRY;
2371 	case IB_QP_RQ_PSN:
2372 		return 0;
2373 	case IB_QP_MAX_QP_RD_ATOMIC:
2374 		return MLX5_QP_OPTPAR_SRA_MAX;
2375 	case IB_QP_ALT_PATH:
2376 		return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2377 	case IB_QP_MIN_RNR_TIMER:
2378 		return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2379 	case IB_QP_SQ_PSN:
2380 		return 0;
2381 	case IB_QP_MAX_DEST_RD_ATOMIC:
2382 		return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2383 			MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2384 	case IB_QP_PATH_MIG_STATE:
2385 		return MLX5_QP_OPTPAR_PM_STATE;
2386 	case IB_QP_CAP:
2387 		return 0;
2388 	case IB_QP_DEST_QPN:
2389 		return 0;
2390 	}
2391 	return 0;
2392 }
2393 
2394 static int ib_mask_to_mlx5_opt(int ib_mask)
2395 {
2396 	int result = 0;
2397 	int i;
2398 
2399 	for (i = 0; i < 8 * sizeof(int); i++) {
2400 		if ((1 << i) & ib_mask)
2401 			result |= ib_nr_to_mlx5_nr(1 << i);
2402 	}
2403 
2404 	return result;
2405 }
2406 
2407 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2408 				   struct mlx5_ib_rq *rq, int new_state,
2409 				   const struct mlx5_modify_raw_qp_param *raw_qp_param)
2410 {
2411 	void *in;
2412 	void *rqc;
2413 	int inlen;
2414 	int err;
2415 
2416 	inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2417 	in = mlx5_vzalloc(inlen);
2418 	if (!in)
2419 		return -ENOMEM;
2420 
2421 	MLX5_SET(modify_rq_in, in, rqn, rq->base.mqp.qpn);
2422 	MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2423 
2424 	rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2425 	MLX5_SET(rqc, rqc, state, new_state);
2426 
2427 	if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2428 		if (MLX5_CAP_GEN(dev->mdev, modify_rq_counters_set_id)) {
2429 			MLX5_SET64(modify_rq_in, in, modify_bitmask,
2430 				   MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID);
2431 			MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2432 		} else
2433 			pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2434 				     dev->ib_dev.name);
2435 	}
2436 
2437 	err = mlx5_core_modify_rq(dev->mdev, in, inlen);
2438 	if (err)
2439 		goto out;
2440 
2441 	rq->state = new_state;
2442 
2443 out:
2444 	kvfree(in);
2445 	return err;
2446 }
2447 
2448 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2449 				   struct mlx5_ib_sq *sq, int new_state)
2450 {
2451 	void *in;
2452 	void *sqc;
2453 	int inlen;
2454 	int err;
2455 
2456 	inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2457 	in = mlx5_vzalloc(inlen);
2458 	if (!in)
2459 		return -ENOMEM;
2460 
2461 	MLX5_SET(modify_sq_in, in, sqn, sq->base.mqp.qpn);
2462 	MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2463 
2464 	sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2465 	MLX5_SET(sqc, sqc, state, new_state);
2466 
2467 	err = mlx5_core_modify_sq(dev, in, inlen);
2468 	if (err)
2469 		goto out;
2470 
2471 	sq->state = new_state;
2472 
2473 out:
2474 	kvfree(in);
2475 	return err;
2476 }
2477 
2478 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2479 				const struct mlx5_modify_raw_qp_param *raw_qp_param,
2480 				u8 tx_affinity)
2481 {
2482 	struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2483 	struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2484 	struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2485 	int rq_state;
2486 	int sq_state;
2487 	int err;
2488 
2489 	switch (raw_qp_param->operation) {
2490 	case MLX5_CMD_OP_RST2INIT_QP:
2491 		rq_state = MLX5_RQC_STATE_RDY;
2492 		sq_state = MLX5_SQC_STATE_RDY;
2493 		break;
2494 	case MLX5_CMD_OP_2ERR_QP:
2495 		rq_state = MLX5_RQC_STATE_ERR;
2496 		sq_state = MLX5_SQC_STATE_ERR;
2497 		break;
2498 	case MLX5_CMD_OP_2RST_QP:
2499 		rq_state = MLX5_RQC_STATE_RST;
2500 		sq_state = MLX5_SQC_STATE_RST;
2501 		break;
2502 	case MLX5_CMD_OP_INIT2INIT_QP:
2503 	case MLX5_CMD_OP_INIT2RTR_QP:
2504 	case MLX5_CMD_OP_RTR2RTS_QP:
2505 	case MLX5_CMD_OP_RTS2RTS_QP:
2506 		if (raw_qp_param->set_mask)
2507 			return -EINVAL;
2508 		else
2509 			return 0;
2510 	default:
2511 		WARN_ON(1);
2512 		return -EINVAL;
2513 	}
2514 
2515 	if (qp->rq.wqe_cnt) {
2516 		err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
2517 		if (err)
2518 			return err;
2519 	}
2520 
2521 	if (qp->sq.wqe_cnt) {
2522 		if (tx_affinity) {
2523 			err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2524 							    tx_affinity);
2525 			if (err)
2526 				return err;
2527 		}
2528 
2529 		return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state);
2530 	}
2531 
2532 	return 0;
2533 }
2534 
2535 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2536 			       const struct ib_qp_attr *attr, int attr_mask,
2537 			       enum ib_qp_state cur_state, enum ib_qp_state new_state)
2538 {
2539 	static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2540 		[MLX5_QP_STATE_RST] = {
2541 			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
2542 			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
2543 			[MLX5_QP_STATE_INIT]	= MLX5_CMD_OP_RST2INIT_QP,
2544 		},
2545 		[MLX5_QP_STATE_INIT]  = {
2546 			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
2547 			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
2548 			[MLX5_QP_STATE_INIT]	= MLX5_CMD_OP_INIT2INIT_QP,
2549 			[MLX5_QP_STATE_RTR]	= MLX5_CMD_OP_INIT2RTR_QP,
2550 		},
2551 		[MLX5_QP_STATE_RTR]   = {
2552 			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
2553 			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
2554 			[MLX5_QP_STATE_RTS]	= MLX5_CMD_OP_RTR2RTS_QP,
2555 		},
2556 		[MLX5_QP_STATE_RTS]   = {
2557 			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
2558 			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
2559 			[MLX5_QP_STATE_RTS]	= MLX5_CMD_OP_RTS2RTS_QP,
2560 		},
2561 		[MLX5_QP_STATE_SQD] = {
2562 			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
2563 			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
2564 		},
2565 		[MLX5_QP_STATE_SQER] = {
2566 			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
2567 			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
2568 			[MLX5_QP_STATE_RTS]	= MLX5_CMD_OP_SQERR2RTS_QP,
2569 		},
2570 		[MLX5_QP_STATE_ERR] = {
2571 			[MLX5_QP_STATE_RST]	= MLX5_CMD_OP_2RST_QP,
2572 			[MLX5_QP_STATE_ERR]	= MLX5_CMD_OP_2ERR_QP,
2573 		}
2574 	};
2575 
2576 	struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2577 	struct mlx5_ib_qp *qp = to_mqp(ibqp);
2578 	struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2579 	struct mlx5_ib_cq *send_cq, *recv_cq;
2580 	struct mlx5_qp_context *context;
2581 	struct mlx5_ib_pd *pd;
2582 	struct mlx5_ib_port *mibport = NULL;
2583 	enum mlx5_qp_state mlx5_cur, mlx5_new;
2584 	enum mlx5_qp_optpar optpar;
2585 	int sqd_event;
2586 	int mlx5_st;
2587 	int err;
2588 	u16 op;
2589 
2590 	context = kzalloc(sizeof(*context), GFP_KERNEL);
2591 	if (!context)
2592 		return -ENOMEM;
2593 
2594 	err = to_mlx5_st(ibqp->qp_type);
2595 	if (err < 0) {
2596 		mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
2597 		goto out;
2598 	}
2599 
2600 	context->flags = cpu_to_be32(err << 16);
2601 
2602 	if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2603 		context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2604 	} else {
2605 		switch (attr->path_mig_state) {
2606 		case IB_MIG_MIGRATED:
2607 			context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2608 			break;
2609 		case IB_MIG_REARM:
2610 			context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2611 			break;
2612 		case IB_MIG_ARMED:
2613 			context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2614 			break;
2615 		}
2616 	}
2617 
2618 	if (is_sqp(ibqp->qp_type)) {
2619 		context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2620 	} else if (ibqp->qp_type == IB_QPT_UD ||
2621 		   ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2622 		context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2623 	} else if (attr_mask & IB_QP_PATH_MTU) {
2624 		if (attr->path_mtu < IB_MTU_256 ||
2625 		    attr->path_mtu > IB_MTU_4096) {
2626 			mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2627 			err = -EINVAL;
2628 			goto out;
2629 		}
2630 		context->mtu_msgmax = (attr->path_mtu << 5) |
2631 				      (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
2632 	}
2633 
2634 	if (attr_mask & IB_QP_DEST_QPN)
2635 		context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2636 
2637 	if (attr_mask & IB_QP_PKEY_INDEX)
2638 		context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
2639 
2640 	/* todo implement counter_index functionality */
2641 
2642 	if (is_sqp(ibqp->qp_type))
2643 		context->pri_path.port = qp->port;
2644 
2645 	if (attr_mask & IB_QP_PORT)
2646 		context->pri_path.port = attr->port_num;
2647 
2648 	if (attr_mask & IB_QP_AV) {
2649 		err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
2650 				    attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
2651 				    attr_mask, 0, attr, false);
2652 		if (err)
2653 			goto out;
2654 	}
2655 
2656 	if (attr_mask & IB_QP_TIMEOUT)
2657 		context->pri_path.ackto_lt |= attr->timeout << 3;
2658 
2659 	if (attr_mask & IB_QP_ALT_PATH) {
2660 		err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2661 				    &context->alt_path,
2662 				    attr->alt_port_num,
2663 				    attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2664 				    0, attr, true);
2665 		if (err)
2666 			goto out;
2667 	}
2668 
2669 	pd = get_pd(qp);
2670 	get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2671 		&send_cq, &recv_cq);
2672 
2673 	context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2674 	context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2675 	context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2676 	context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2677 
2678 	if (attr_mask & IB_QP_RNR_RETRY)
2679 		context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2680 
2681 	if (attr_mask & IB_QP_RETRY_CNT)
2682 		context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2683 
2684 	if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2685 		if (attr->max_rd_atomic)
2686 			context->params1 |=
2687 				cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2688 	}
2689 
2690 	if (attr_mask & IB_QP_SQ_PSN)
2691 		context->next_send_psn = cpu_to_be32(attr->sq_psn);
2692 
2693 	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2694 		if (attr->max_dest_rd_atomic)
2695 			context->params2 |=
2696 				cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2697 	}
2698 
2699 	if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2700 		context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2701 
2702 	if (attr_mask & IB_QP_MIN_RNR_TIMER)
2703 		context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2704 
2705 	if (attr_mask & IB_QP_RQ_PSN)
2706 		context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2707 
2708 	if (attr_mask & IB_QP_QKEY)
2709 		context->qkey = cpu_to_be32(attr->qkey);
2710 
2711 	if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2712 		context->db_rec_addr = cpu_to_be64(qp->db.dma);
2713 
2714 	if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD	&&
2715 	    attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2716 		sqd_event = 1;
2717 	else
2718 		sqd_event = 0;
2719 
2720 	if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2721 		u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2722 			       qp->port) - 1;
2723 		mibport = &dev->port[port_num];
2724 		context->qp_counter_set_usr_page |=
2725 			cpu_to_be32((u32)(mibport->q_cnt_id) << 24);
2726 	}
2727 
2728 	if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2729 		context->sq_crq_size |= cpu_to_be16(1 << 4);
2730 
2731 	if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2732 		context->deth_sqpn = cpu_to_be32(1);
2733 
2734 	mlx5_cur = to_mlx5_state(cur_state);
2735 	mlx5_new = to_mlx5_state(new_state);
2736 	mlx5_st = to_mlx5_st(ibqp->qp_type);
2737 	if (mlx5_st < 0)
2738 		goto out;
2739 
2740 	/* If moving to a reset or error state, we must disable page faults on
2741 	 * this QP and flush all current page faults. Otherwise a stale page
2742 	 * fault may attempt to work on this QP after it is reset and moved
2743 	 * again to RTS, and may cause the driver and the device to get out of
2744 	 * sync. */
2745 	if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2746 	    (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) &&
2747 	    (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2748 		mlx5_ib_qp_disable_pagefaults(qp);
2749 
2750 	if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2751 	    !optab[mlx5_cur][mlx5_new])
2752 		goto out;
2753 
2754 	op = optab[mlx5_cur][mlx5_new];
2755 	optpar = ib_mask_to_mlx5_opt(attr_mask);
2756 	optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2757 
2758 	if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
2759 		struct mlx5_modify_raw_qp_param raw_qp_param = {};
2760 
2761 		raw_qp_param.operation = op;
2762 		if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2763 			raw_qp_param.rq_q_ctr_id = mibport->q_cnt_id;
2764 			raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
2765 		}
2766 		err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2767 	} else {
2768 		err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
2769 					  &base->mqp);
2770 	}
2771 
2772 	if (err)
2773 		goto out;
2774 
2775 	if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT &&
2776 	    (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2777 		mlx5_ib_qp_enable_pagefaults(qp);
2778 
2779 	qp->state = new_state;
2780 
2781 	if (attr_mask & IB_QP_ACCESS_FLAGS)
2782 		qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
2783 	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2784 		qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
2785 	if (attr_mask & IB_QP_PORT)
2786 		qp->port = attr->port_num;
2787 	if (attr_mask & IB_QP_ALT_PATH)
2788 		qp->trans_qp.alt_port = attr->alt_port_num;
2789 
2790 	/*
2791 	 * If we moved a kernel QP to RESET, clean up all old CQ
2792 	 * entries and reinitialize the QP.
2793 	 */
2794 	if (new_state == IB_QPS_RESET && !ibqp->uobject) {
2795 		mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2796 				 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2797 		if (send_cq != recv_cq)
2798 			mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
2799 
2800 		qp->rq.head = 0;
2801 		qp->rq.tail = 0;
2802 		qp->sq.head = 0;
2803 		qp->sq.tail = 0;
2804 		qp->sq.cur_post = 0;
2805 		qp->sq.last_poll = 0;
2806 		qp->db.db[MLX5_RCV_DBR] = 0;
2807 		qp->db.db[MLX5_SND_DBR] = 0;
2808 	}
2809 
2810 out:
2811 	kfree(context);
2812 	return err;
2813 }
2814 
2815 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2816 		      int attr_mask, struct ib_udata *udata)
2817 {
2818 	struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2819 	struct mlx5_ib_qp *qp = to_mqp(ibqp);
2820 	enum ib_qp_type qp_type;
2821 	enum ib_qp_state cur_state, new_state;
2822 	int err = -EINVAL;
2823 	int port;
2824 	enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
2825 
2826 	if (ibqp->rwq_ind_tbl)
2827 		return -ENOSYS;
2828 
2829 	if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2830 		return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2831 
2832 	qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2833 		IB_QPT_GSI : ibqp->qp_type;
2834 
2835 	mutex_lock(&qp->mutex);
2836 
2837 	cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2838 	new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2839 
2840 	if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2841 		port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2842 		ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2843 	}
2844 
2845 	if (qp_type != MLX5_IB_QPT_REG_UMR &&
2846 	    !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
2847 		mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2848 			    cur_state, new_state, ibqp->qp_type, attr_mask);
2849 		goto out;
2850 	}
2851 
2852 	if ((attr_mask & IB_QP_PORT) &&
2853 	    (attr->port_num == 0 ||
2854 	     attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2855 		mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2856 			    attr->port_num, dev->num_ports);
2857 		goto out;
2858 	}
2859 
2860 	if (attr_mask & IB_QP_PKEY_INDEX) {
2861 		port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2862 		if (attr->pkey_index >=
2863 		    dev->mdev->port_caps[port - 1].pkey_table_len) {
2864 			mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2865 				    attr->pkey_index);
2866 			goto out;
2867 		}
2868 	}
2869 
2870 	if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2871 	    attr->max_rd_atomic >
2872 	    (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
2873 		mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
2874 			    attr->max_rd_atomic);
2875 		goto out;
2876 	}
2877 
2878 	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2879 	    attr->max_dest_rd_atomic >
2880 	    (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
2881 		mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
2882 			    attr->max_dest_rd_atomic);
2883 		goto out;
2884 	}
2885 
2886 	if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2887 		err = 0;
2888 		goto out;
2889 	}
2890 
2891 	err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2892 
2893 out:
2894 	mutex_unlock(&qp->mutex);
2895 	return err;
2896 }
2897 
2898 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2899 {
2900 	struct mlx5_ib_cq *cq;
2901 	unsigned cur;
2902 
2903 	cur = wq->head - wq->tail;
2904 	if (likely(cur + nreq < wq->max_post))
2905 		return 0;
2906 
2907 	cq = to_mcq(ib_cq);
2908 	spin_lock(&cq->lock);
2909 	cur = wq->head - wq->tail;
2910 	spin_unlock(&cq->lock);
2911 
2912 	return cur + nreq >= wq->max_post;
2913 }
2914 
2915 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
2916 					  u64 remote_addr, u32 rkey)
2917 {
2918 	rseg->raddr    = cpu_to_be64(remote_addr);
2919 	rseg->rkey     = cpu_to_be32(rkey);
2920 	rseg->reserved = 0;
2921 }
2922 
2923 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
2924 			 struct ib_send_wr *wr, void *qend,
2925 			 struct mlx5_ib_qp *qp, int *size)
2926 {
2927 	void *seg = eseg;
2928 
2929 	memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
2930 
2931 	if (wr->send_flags & IB_SEND_IP_CSUM)
2932 		eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
2933 				 MLX5_ETH_WQE_L4_CSUM;
2934 
2935 	seg += sizeof(struct mlx5_wqe_eth_seg);
2936 	*size += sizeof(struct mlx5_wqe_eth_seg) / 16;
2937 
2938 	if (wr->opcode == IB_WR_LSO) {
2939 		struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2940 		int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start);
2941 		u64 left, leftlen, copysz;
2942 		void *pdata = ud_wr->header;
2943 
2944 		left = ud_wr->hlen;
2945 		eseg->mss = cpu_to_be16(ud_wr->mss);
2946 		eseg->inline_hdr_sz = cpu_to_be16(left);
2947 
2948 		/*
2949 		 * check if there is space till the end of queue, if yes,
2950 		 * copy all in one shot, otherwise copy till the end of queue,
2951 		 * rollback and than the copy the left
2952 		 */
2953 		leftlen = qend - (void *)eseg->inline_hdr_start;
2954 		copysz = min_t(u64, leftlen, left);
2955 
2956 		memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
2957 
2958 		if (likely(copysz > size_of_inl_hdr_start)) {
2959 			seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
2960 			*size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
2961 		}
2962 
2963 		if (unlikely(copysz < left)) { /* the last wqe in the queue */
2964 			seg = mlx5_get_send_wqe(qp, 0);
2965 			left -= copysz;
2966 			pdata += copysz;
2967 			memcpy(seg, pdata, left);
2968 			seg += ALIGN(left, 16);
2969 			*size += ALIGN(left, 16) / 16;
2970 		}
2971 	}
2972 
2973 	return seg;
2974 }
2975 
2976 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
2977 			     struct ib_send_wr *wr)
2978 {
2979 	memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
2980 	dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
2981 	dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
2982 }
2983 
2984 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
2985 {
2986 	dseg->byte_count = cpu_to_be32(sg->length);
2987 	dseg->lkey       = cpu_to_be32(sg->lkey);
2988 	dseg->addr       = cpu_to_be64(sg->addr);
2989 }
2990 
2991 static __be16 get_klm_octo(int npages)
2992 {
2993 	return cpu_to_be16(ALIGN(npages, 8) / 2);
2994 }
2995 
2996 static __be64 frwr_mkey_mask(void)
2997 {
2998 	u64 result;
2999 
3000 	result = MLX5_MKEY_MASK_LEN		|
3001 		MLX5_MKEY_MASK_PAGE_SIZE	|
3002 		MLX5_MKEY_MASK_START_ADDR	|
3003 		MLX5_MKEY_MASK_EN_RINVAL	|
3004 		MLX5_MKEY_MASK_KEY		|
3005 		MLX5_MKEY_MASK_LR		|
3006 		MLX5_MKEY_MASK_LW		|
3007 		MLX5_MKEY_MASK_RR		|
3008 		MLX5_MKEY_MASK_RW		|
3009 		MLX5_MKEY_MASK_A		|
3010 		MLX5_MKEY_MASK_SMALL_FENCE	|
3011 		MLX5_MKEY_MASK_FREE;
3012 
3013 	return cpu_to_be64(result);
3014 }
3015 
3016 static __be64 sig_mkey_mask(void)
3017 {
3018 	u64 result;
3019 
3020 	result = MLX5_MKEY_MASK_LEN		|
3021 		MLX5_MKEY_MASK_PAGE_SIZE	|
3022 		MLX5_MKEY_MASK_START_ADDR	|
3023 		MLX5_MKEY_MASK_EN_SIGERR	|
3024 		MLX5_MKEY_MASK_EN_RINVAL	|
3025 		MLX5_MKEY_MASK_KEY		|
3026 		MLX5_MKEY_MASK_LR		|
3027 		MLX5_MKEY_MASK_LW		|
3028 		MLX5_MKEY_MASK_RR		|
3029 		MLX5_MKEY_MASK_RW		|
3030 		MLX5_MKEY_MASK_SMALL_FENCE	|
3031 		MLX5_MKEY_MASK_FREE		|
3032 		MLX5_MKEY_MASK_BSF_EN;
3033 
3034 	return cpu_to_be64(result);
3035 }
3036 
3037 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3038 				struct mlx5_ib_mr *mr)
3039 {
3040 	int ndescs = mr->ndescs;
3041 
3042 	memset(umr, 0, sizeof(*umr));
3043 
3044 	if (mr->access_mode == MLX5_ACCESS_MODE_KLM)
3045 		/* KLMs take twice the size of MTTs */
3046 		ndescs *= 2;
3047 
3048 	umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3049 	umr->klm_octowords = get_klm_octo(ndescs);
3050 	umr->mkey_mask = frwr_mkey_mask();
3051 }
3052 
3053 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
3054 {
3055 	memset(umr, 0, sizeof(*umr));
3056 	umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
3057 	umr->flags = 1 << 7;
3058 }
3059 
3060 static __be64 get_umr_reg_mr_mask(void)
3061 {
3062 	u64 result;
3063 
3064 	result = MLX5_MKEY_MASK_LEN		|
3065 		 MLX5_MKEY_MASK_PAGE_SIZE	|
3066 		 MLX5_MKEY_MASK_START_ADDR	|
3067 		 MLX5_MKEY_MASK_PD		|
3068 		 MLX5_MKEY_MASK_LR		|
3069 		 MLX5_MKEY_MASK_LW		|
3070 		 MLX5_MKEY_MASK_KEY		|
3071 		 MLX5_MKEY_MASK_RR		|
3072 		 MLX5_MKEY_MASK_RW		|
3073 		 MLX5_MKEY_MASK_A		|
3074 		 MLX5_MKEY_MASK_FREE;
3075 
3076 	return cpu_to_be64(result);
3077 }
3078 
3079 static __be64 get_umr_unreg_mr_mask(void)
3080 {
3081 	u64 result;
3082 
3083 	result = MLX5_MKEY_MASK_FREE;
3084 
3085 	return cpu_to_be64(result);
3086 }
3087 
3088 static __be64 get_umr_update_mtt_mask(void)
3089 {
3090 	u64 result;
3091 
3092 	result = MLX5_MKEY_MASK_FREE;
3093 
3094 	return cpu_to_be64(result);
3095 }
3096 
3097 static __be64 get_umr_update_translation_mask(void)
3098 {
3099 	u64 result;
3100 
3101 	result = MLX5_MKEY_MASK_LEN |
3102 		 MLX5_MKEY_MASK_PAGE_SIZE |
3103 		 MLX5_MKEY_MASK_START_ADDR |
3104 		 MLX5_MKEY_MASK_KEY |
3105 		 MLX5_MKEY_MASK_FREE;
3106 
3107 	return cpu_to_be64(result);
3108 }
3109 
3110 static __be64 get_umr_update_access_mask(void)
3111 {
3112 	u64 result;
3113 
3114 	result = MLX5_MKEY_MASK_LW |
3115 		 MLX5_MKEY_MASK_RR |
3116 		 MLX5_MKEY_MASK_RW |
3117 		 MLX5_MKEY_MASK_A |
3118 		 MLX5_MKEY_MASK_KEY |
3119 		 MLX5_MKEY_MASK_FREE;
3120 
3121 	return cpu_to_be64(result);
3122 }
3123 
3124 static __be64 get_umr_update_pd_mask(void)
3125 {
3126 	u64 result;
3127 
3128 	result = MLX5_MKEY_MASK_PD |
3129 		 MLX5_MKEY_MASK_KEY |
3130 		 MLX5_MKEY_MASK_FREE;
3131 
3132 	return cpu_to_be64(result);
3133 }
3134 
3135 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3136 				struct ib_send_wr *wr)
3137 {
3138 	struct mlx5_umr_wr *umrwr = umr_wr(wr);
3139 
3140 	memset(umr, 0, sizeof(*umr));
3141 
3142 	if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3143 		umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3144 	else
3145 		umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3146 
3147 	if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
3148 		umr->klm_octowords = get_klm_octo(umrwr->npages);
3149 		if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) {
3150 			umr->mkey_mask = get_umr_update_mtt_mask();
3151 			umr->bsf_octowords = get_klm_octo(umrwr->target.offset);
3152 			umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3153 		}
3154 		if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3155 			umr->mkey_mask |= get_umr_update_translation_mask();
3156 		if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_ACCESS)
3157 			umr->mkey_mask |= get_umr_update_access_mask();
3158 		if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD)
3159 			umr->mkey_mask |= get_umr_update_pd_mask();
3160 		if (!umr->mkey_mask)
3161 			umr->mkey_mask = get_umr_reg_mr_mask();
3162 	} else {
3163 		umr->mkey_mask = get_umr_unreg_mr_mask();
3164 	}
3165 
3166 	if (!wr->num_sge)
3167 		umr->flags |= MLX5_UMR_INLINE;
3168 }
3169 
3170 static u8 get_umr_flags(int acc)
3171 {
3172 	return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
3173 	       (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
3174 	       (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
3175 	       (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
3176 		MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3177 }
3178 
3179 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3180 			     struct mlx5_ib_mr *mr,
3181 			     u32 key, int access)
3182 {
3183 	int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3184 
3185 	memset(seg, 0, sizeof(*seg));
3186 
3187 	if (mr->access_mode == MLX5_ACCESS_MODE_MTT)
3188 		seg->log2_page_size = ilog2(mr->ibmr.page_size);
3189 	else if (mr->access_mode == MLX5_ACCESS_MODE_KLM)
3190 		/* KLMs take twice the size of MTTs */
3191 		ndescs *= 2;
3192 
3193 	seg->flags = get_umr_flags(access) | mr->access_mode;
3194 	seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3195 	seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3196 	seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3197 	seg->len = cpu_to_be64(mr->ibmr.length);
3198 	seg->xlt_oct_size = cpu_to_be32(ndescs);
3199 }
3200 
3201 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3202 {
3203 	memset(seg, 0, sizeof(*seg));
3204 	seg->status = MLX5_MKEY_STATUS_FREE;
3205 }
3206 
3207 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3208 {
3209 	struct mlx5_umr_wr *umrwr = umr_wr(wr);
3210 
3211 	memset(seg, 0, sizeof(*seg));
3212 	if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
3213 		seg->status = MLX5_MKEY_STATUS_FREE;
3214 		return;
3215 	}
3216 
3217 	seg->flags = convert_access(umrwr->access_flags);
3218 	if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) {
3219 		if (umrwr->pd)
3220 			seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3221 		seg->start_addr = cpu_to_be64(umrwr->target.virt_addr);
3222 	}
3223 	seg->len = cpu_to_be64(umrwr->length);
3224 	seg->log2_page_size = umrwr->page_shift;
3225 	seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3226 				       mlx5_mkey_variant(umrwr->mkey));
3227 }
3228 
3229 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3230 			     struct mlx5_ib_mr *mr,
3231 			     struct mlx5_ib_pd *pd)
3232 {
3233 	int bcount = mr->desc_size * mr->ndescs;
3234 
3235 	dseg->addr = cpu_to_be64(mr->desc_map);
3236 	dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3237 	dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3238 }
3239 
3240 static __be32 send_ieth(struct ib_send_wr *wr)
3241 {
3242 	switch (wr->opcode) {
3243 	case IB_WR_SEND_WITH_IMM:
3244 	case IB_WR_RDMA_WRITE_WITH_IMM:
3245 		return wr->ex.imm_data;
3246 
3247 	case IB_WR_SEND_WITH_INV:
3248 		return cpu_to_be32(wr->ex.invalidate_rkey);
3249 
3250 	default:
3251 		return 0;
3252 	}
3253 }
3254 
3255 static u8 calc_sig(void *wqe, int size)
3256 {
3257 	u8 *p = wqe;
3258 	u8 res = 0;
3259 	int i;
3260 
3261 	for (i = 0; i < size; i++)
3262 		res ^= p[i];
3263 
3264 	return ~res;
3265 }
3266 
3267 static u8 wq_sig(void *wqe)
3268 {
3269 	return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3270 }
3271 
3272 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3273 			    void *wqe, int *sz)
3274 {
3275 	struct mlx5_wqe_inline_seg *seg;
3276 	void *qend = qp->sq.qend;
3277 	void *addr;
3278 	int inl = 0;
3279 	int copy;
3280 	int len;
3281 	int i;
3282 
3283 	seg = wqe;
3284 	wqe += sizeof(*seg);
3285 	for (i = 0; i < wr->num_sge; i++) {
3286 		addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3287 		len  = wr->sg_list[i].length;
3288 		inl += len;
3289 
3290 		if (unlikely(inl > qp->max_inline_data))
3291 			return -ENOMEM;
3292 
3293 		if (unlikely(wqe + len > qend)) {
3294 			copy = qend - wqe;
3295 			memcpy(wqe, addr, copy);
3296 			addr += copy;
3297 			len -= copy;
3298 			wqe = mlx5_get_send_wqe(qp, 0);
3299 		}
3300 		memcpy(wqe, addr, len);
3301 		wqe += len;
3302 	}
3303 
3304 	seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3305 
3306 	*sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3307 
3308 	return 0;
3309 }
3310 
3311 static u16 prot_field_size(enum ib_signature_type type)
3312 {
3313 	switch (type) {
3314 	case IB_SIG_TYPE_T10_DIF:
3315 		return MLX5_DIF_SIZE;
3316 	default:
3317 		return 0;
3318 	}
3319 }
3320 
3321 static u8 bs_selector(int block_size)
3322 {
3323 	switch (block_size) {
3324 	case 512:	    return 0x1;
3325 	case 520:	    return 0x2;
3326 	case 4096:	    return 0x3;
3327 	case 4160:	    return 0x4;
3328 	case 1073741824:    return 0x5;
3329 	default:	    return 0;
3330 	}
3331 }
3332 
3333 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3334 			      struct mlx5_bsf_inl *inl)
3335 {
3336 	/* Valid inline section and allow BSF refresh */
3337 	inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3338 				       MLX5_BSF_REFRESH_DIF);
3339 	inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3340 	inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
3341 	/* repeating block */
3342 	inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3343 	inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3344 			MLX5_DIF_CRC : MLX5_DIF_IPCS;
3345 
3346 	if (domain->sig.dif.ref_remap)
3347 		inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
3348 
3349 	if (domain->sig.dif.app_escape) {
3350 		if (domain->sig.dif.ref_escape)
3351 			inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3352 		else
3353 			inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
3354 	}
3355 
3356 	inl->dif_app_bitmask_check =
3357 		cpu_to_be16(domain->sig.dif.apptag_check_mask);
3358 }
3359 
3360 static int mlx5_set_bsf(struct ib_mr *sig_mr,
3361 			struct ib_sig_attrs *sig_attrs,
3362 			struct mlx5_bsf *bsf, u32 data_size)
3363 {
3364 	struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3365 	struct mlx5_bsf_basic *basic = &bsf->basic;
3366 	struct ib_sig_domain *mem = &sig_attrs->mem;
3367 	struct ib_sig_domain *wire = &sig_attrs->wire;
3368 
3369 	memset(bsf, 0, sizeof(*bsf));
3370 
3371 	/* Basic + Extended + Inline */
3372 	basic->bsf_size_sbs = 1 << 7;
3373 	/* Input domain check byte mask */
3374 	basic->check_byte_mask = sig_attrs->check_mask;
3375 	basic->raw_data_size = cpu_to_be32(data_size);
3376 
3377 	/* Memory domain */
3378 	switch (sig_attrs->mem.sig_type) {
3379 	case IB_SIG_TYPE_NONE:
3380 		break;
3381 	case IB_SIG_TYPE_T10_DIF:
3382 		basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3383 		basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3384 		mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3385 		break;
3386 	default:
3387 		return -EINVAL;
3388 	}
3389 
3390 	/* Wire domain */
3391 	switch (sig_attrs->wire.sig_type) {
3392 	case IB_SIG_TYPE_NONE:
3393 		break;
3394 	case IB_SIG_TYPE_T10_DIF:
3395 		if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
3396 		    mem->sig_type == wire->sig_type) {
3397 			/* Same block structure */
3398 			basic->bsf_size_sbs |= 1 << 4;
3399 			if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
3400 				basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
3401 			if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
3402 				basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
3403 			if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
3404 				basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
3405 		} else
3406 			basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3407 
3408 		basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
3409 		mlx5_fill_inl_bsf(wire, &bsf->w_inl);
3410 		break;
3411 	default:
3412 		return -EINVAL;
3413 	}
3414 
3415 	return 0;
3416 }
3417 
3418 static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3419 				struct mlx5_ib_qp *qp, void **seg, int *size)
3420 {
3421 	struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3422 	struct ib_mr *sig_mr = wr->sig_mr;
3423 	struct mlx5_bsf *bsf;
3424 	u32 data_len = wr->wr.sg_list->length;
3425 	u32 data_key = wr->wr.sg_list->lkey;
3426 	u64 data_va = wr->wr.sg_list->addr;
3427 	int ret;
3428 	int wqe_size;
3429 
3430 	if (!wr->prot ||
3431 	    (data_key == wr->prot->lkey &&
3432 	     data_va == wr->prot->addr &&
3433 	     data_len == wr->prot->length)) {
3434 		/**
3435 		 * Source domain doesn't contain signature information
3436 		 * or data and protection are interleaved in memory.
3437 		 * So need construct:
3438 		 *                  ------------------
3439 		 *                 |     data_klm     |
3440 		 *                  ------------------
3441 		 *                 |       BSF        |
3442 		 *                  ------------------
3443 		 **/
3444 		struct mlx5_klm *data_klm = *seg;
3445 
3446 		data_klm->bcount = cpu_to_be32(data_len);
3447 		data_klm->key = cpu_to_be32(data_key);
3448 		data_klm->va = cpu_to_be64(data_va);
3449 		wqe_size = ALIGN(sizeof(*data_klm), 64);
3450 	} else {
3451 		/**
3452 		 * Source domain contains signature information
3453 		 * So need construct a strided block format:
3454 		 *               ---------------------------
3455 		 *              |     stride_block_ctrl     |
3456 		 *               ---------------------------
3457 		 *              |          data_klm         |
3458 		 *               ---------------------------
3459 		 *              |          prot_klm         |
3460 		 *               ---------------------------
3461 		 *              |             BSF           |
3462 		 *               ---------------------------
3463 		 **/
3464 		struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3465 		struct mlx5_stride_block_entry *data_sentry;
3466 		struct mlx5_stride_block_entry *prot_sentry;
3467 		u32 prot_key = wr->prot->lkey;
3468 		u64 prot_va = wr->prot->addr;
3469 		u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3470 		int prot_size;
3471 
3472 		sblock_ctrl = *seg;
3473 		data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3474 		prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3475 
3476 		prot_size = prot_field_size(sig_attrs->mem.sig_type);
3477 		if (!prot_size) {
3478 			pr_err("Bad block size given: %u\n", block_size);
3479 			return -EINVAL;
3480 		}
3481 		sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3482 							    prot_size);
3483 		sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3484 		sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3485 		sblock_ctrl->num_entries = cpu_to_be16(2);
3486 
3487 		data_sentry->bcount = cpu_to_be16(block_size);
3488 		data_sentry->key = cpu_to_be32(data_key);
3489 		data_sentry->va = cpu_to_be64(data_va);
3490 		data_sentry->stride = cpu_to_be16(block_size);
3491 
3492 		prot_sentry->bcount = cpu_to_be16(prot_size);
3493 		prot_sentry->key = cpu_to_be32(prot_key);
3494 		prot_sentry->va = cpu_to_be64(prot_va);
3495 		prot_sentry->stride = cpu_to_be16(prot_size);
3496 
3497 		wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3498 				 sizeof(*prot_sentry), 64);
3499 	}
3500 
3501 	*seg += wqe_size;
3502 	*size += wqe_size / 16;
3503 	if (unlikely((*seg == qp->sq.qend)))
3504 		*seg = mlx5_get_send_wqe(qp, 0);
3505 
3506 	bsf = *seg;
3507 	ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3508 	if (ret)
3509 		return -EINVAL;
3510 
3511 	*seg += sizeof(*bsf);
3512 	*size += sizeof(*bsf) / 16;
3513 	if (unlikely((*seg == qp->sq.qend)))
3514 		*seg = mlx5_get_send_wqe(qp, 0);
3515 
3516 	return 0;
3517 }
3518 
3519 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
3520 				 struct ib_sig_handover_wr *wr, u32 nelements,
3521 				 u32 length, u32 pdn)
3522 {
3523 	struct ib_mr *sig_mr = wr->sig_mr;
3524 	u32 sig_key = sig_mr->rkey;
3525 	u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
3526 
3527 	memset(seg, 0, sizeof(*seg));
3528 
3529 	seg->flags = get_umr_flags(wr->access_flags) |
3530 				   MLX5_ACCESS_MODE_KLM;
3531 	seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
3532 	seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
3533 				    MLX5_MKEY_BSF_EN | pdn);
3534 	seg->len = cpu_to_be64(length);
3535 	seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements)));
3536 	seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3537 }
3538 
3539 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3540 				u32 nelements)
3541 {
3542 	memset(umr, 0, sizeof(*umr));
3543 
3544 	umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
3545 	umr->klm_octowords = get_klm_octo(nelements);
3546 	umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3547 	umr->mkey_mask = sig_mkey_mask();
3548 }
3549 
3550 
3551 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
3552 			  void **seg, int *size)
3553 {
3554 	struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3555 	struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
3556 	u32 pdn = get_pd(qp)->pdn;
3557 	u32 klm_oct_size;
3558 	int region_len, ret;
3559 
3560 	if (unlikely(wr->wr.num_sge != 1) ||
3561 	    unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
3562 	    unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3563 	    unlikely(!sig_mr->sig->sig_status_checked))
3564 		return -EINVAL;
3565 
3566 	/* length of the protected region, data + protection */
3567 	region_len = wr->wr.sg_list->length;
3568 	if (wr->prot &&
3569 	    (wr->prot->lkey != wr->wr.sg_list->lkey  ||
3570 	     wr->prot->addr != wr->wr.sg_list->addr  ||
3571 	     wr->prot->length != wr->wr.sg_list->length))
3572 		region_len += wr->prot->length;
3573 
3574 	/**
3575 	 * KLM octoword size - if protection was provided
3576 	 * then we use strided block format (3 octowords),
3577 	 * else we use single KLM (1 octoword)
3578 	 **/
3579 	klm_oct_size = wr->prot ? 3 : 1;
3580 
3581 	set_sig_umr_segment(*seg, klm_oct_size);
3582 	*seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3583 	*size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3584 	if (unlikely((*seg == qp->sq.qend)))
3585 		*seg = mlx5_get_send_wqe(qp, 0);
3586 
3587 	set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn);
3588 	*seg += sizeof(struct mlx5_mkey_seg);
3589 	*size += sizeof(struct mlx5_mkey_seg) / 16;
3590 	if (unlikely((*seg == qp->sq.qend)))
3591 		*seg = mlx5_get_send_wqe(qp, 0);
3592 
3593 	ret = set_sig_data_segment(wr, qp, seg, size);
3594 	if (ret)
3595 		return ret;
3596 
3597 	sig_mr->sig->sig_status_checked = false;
3598 	return 0;
3599 }
3600 
3601 static int set_psv_wr(struct ib_sig_domain *domain,
3602 		      u32 psv_idx, void **seg, int *size)
3603 {
3604 	struct mlx5_seg_set_psv *psv_seg = *seg;
3605 
3606 	memset(psv_seg, 0, sizeof(*psv_seg));
3607 	psv_seg->psv_num = cpu_to_be32(psv_idx);
3608 	switch (domain->sig_type) {
3609 	case IB_SIG_TYPE_NONE:
3610 		break;
3611 	case IB_SIG_TYPE_T10_DIF:
3612 		psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3613 						     domain->sig.dif.app_tag);
3614 		psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
3615 		break;
3616 	default:
3617 		pr_err("Bad signature type given.\n");
3618 		return 1;
3619 	}
3620 
3621 	*seg += sizeof(*psv_seg);
3622 	*size += sizeof(*psv_seg) / 16;
3623 
3624 	return 0;
3625 }
3626 
3627 static int set_reg_wr(struct mlx5_ib_qp *qp,
3628 		      struct ib_reg_wr *wr,
3629 		      void **seg, int *size)
3630 {
3631 	struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3632 	struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3633 
3634 	if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3635 		mlx5_ib_warn(to_mdev(qp->ibqp.device),
3636 			     "Invalid IB_SEND_INLINE send flag\n");
3637 		return -EINVAL;
3638 	}
3639 
3640 	set_reg_umr_seg(*seg, mr);
3641 	*seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3642 	*size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3643 	if (unlikely((*seg == qp->sq.qend)))
3644 		*seg = mlx5_get_send_wqe(qp, 0);
3645 
3646 	set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3647 	*seg += sizeof(struct mlx5_mkey_seg);
3648 	*size += sizeof(struct mlx5_mkey_seg) / 16;
3649 	if (unlikely((*seg == qp->sq.qend)))
3650 		*seg = mlx5_get_send_wqe(qp, 0);
3651 
3652 	set_reg_data_seg(*seg, mr, pd);
3653 	*seg += sizeof(struct mlx5_wqe_data_seg);
3654 	*size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3655 
3656 	return 0;
3657 }
3658 
3659 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
3660 {
3661 	set_linv_umr_seg(*seg);
3662 	*seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3663 	*size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3664 	if (unlikely((*seg == qp->sq.qend)))
3665 		*seg = mlx5_get_send_wqe(qp, 0);
3666 	set_linv_mkey_seg(*seg);
3667 	*seg += sizeof(struct mlx5_mkey_seg);
3668 	*size += sizeof(struct mlx5_mkey_seg) / 16;
3669 	if (unlikely((*seg == qp->sq.qend)))
3670 		*seg = mlx5_get_send_wqe(qp, 0);
3671 }
3672 
3673 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3674 {
3675 	__be32 *p = NULL;
3676 	int tidx = idx;
3677 	int i, j;
3678 
3679 	pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3680 	for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3681 		if ((i & 0xf) == 0) {
3682 			void *buf = mlx5_get_send_wqe(qp, tidx);
3683 			tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3684 			p = buf;
3685 			j = 0;
3686 		}
3687 		pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3688 			 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3689 			 be32_to_cpu(p[j + 3]));
3690 	}
3691 }
3692 
3693 static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
3694 			 unsigned bytecnt, struct mlx5_ib_qp *qp)
3695 {
3696 	while (bytecnt > 0) {
3697 		__iowrite64_copy(dst++, src++, 8);
3698 		__iowrite64_copy(dst++, src++, 8);
3699 		__iowrite64_copy(dst++, src++, 8);
3700 		__iowrite64_copy(dst++, src++, 8);
3701 		__iowrite64_copy(dst++, src++, 8);
3702 		__iowrite64_copy(dst++, src++, 8);
3703 		__iowrite64_copy(dst++, src++, 8);
3704 		__iowrite64_copy(dst++, src++, 8);
3705 		bytecnt -= 64;
3706 		if (unlikely(src == qp->sq.qend))
3707 			src = mlx5_get_send_wqe(qp, 0);
3708 	}
3709 }
3710 
3711 static u8 get_fence(u8 fence, struct ib_send_wr *wr)
3712 {
3713 	if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
3714 		     wr->send_flags & IB_SEND_FENCE))
3715 		return MLX5_FENCE_MODE_STRONG_ORDERING;
3716 
3717 	if (unlikely(fence)) {
3718 		if (wr->send_flags & IB_SEND_FENCE)
3719 			return MLX5_FENCE_MODE_SMALL_AND_FENCE;
3720 		else
3721 			return fence;
3722 	} else if (unlikely(wr->send_flags & IB_SEND_FENCE)) {
3723 		return MLX5_FENCE_MODE_FENCE;
3724 	}
3725 
3726 	return 0;
3727 }
3728 
3729 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3730 		     struct mlx5_wqe_ctrl_seg **ctrl,
3731 		     struct ib_send_wr *wr, unsigned *idx,
3732 		     int *size, int nreq)
3733 {
3734 	if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
3735 		return -ENOMEM;
3736 
3737 	*idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3738 	*seg = mlx5_get_send_wqe(qp, *idx);
3739 	*ctrl = *seg;
3740 	*(uint32_t *)(*seg + 8) = 0;
3741 	(*ctrl)->imm = send_ieth(wr);
3742 	(*ctrl)->fm_ce_se = qp->sq_signal_bits |
3743 		(wr->send_flags & IB_SEND_SIGNALED ?
3744 		 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3745 		(wr->send_flags & IB_SEND_SOLICITED ?
3746 		 MLX5_WQE_CTRL_SOLICITED : 0);
3747 
3748 	*seg += sizeof(**ctrl);
3749 	*size = sizeof(**ctrl) / 16;
3750 
3751 	return 0;
3752 }
3753 
3754 static void finish_wqe(struct mlx5_ib_qp *qp,
3755 		       struct mlx5_wqe_ctrl_seg *ctrl,
3756 		       u8 size, unsigned idx, u64 wr_id,
3757 		       int nreq, u8 fence, u8 next_fence,
3758 		       u32 mlx5_opcode)
3759 {
3760 	u8 opmod = 0;
3761 
3762 	ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3763 					     mlx5_opcode | ((u32)opmod << 24));
3764 	ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
3765 	ctrl->fm_ce_se |= fence;
3766 	qp->fm_cache = next_fence;
3767 	if (unlikely(qp->wq_sig))
3768 		ctrl->signature = wq_sig(ctrl);
3769 
3770 	qp->sq.wrid[idx] = wr_id;
3771 	qp->sq.w_list[idx].opcode = mlx5_opcode;
3772 	qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3773 	qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3774 	qp->sq.w_list[idx].next = qp->sq.cur_post;
3775 }
3776 
3777 
3778 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3779 		      struct ib_send_wr **bad_wr)
3780 {
3781 	struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
3782 	struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3783 	struct mlx5_core_dev *mdev = dev->mdev;
3784 	struct mlx5_ib_qp *qp;
3785 	struct mlx5_ib_mr *mr;
3786 	struct mlx5_wqe_data_seg *dpseg;
3787 	struct mlx5_wqe_xrc_seg *xrc;
3788 	struct mlx5_bf *bf;
3789 	int uninitialized_var(size);
3790 	void *qend;
3791 	unsigned long flags;
3792 	unsigned idx;
3793 	int err = 0;
3794 	int inl = 0;
3795 	int num_sge;
3796 	void *seg;
3797 	int nreq;
3798 	int i;
3799 	u8 next_fence = 0;
3800 	u8 fence;
3801 
3802 	if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3803 		return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3804 
3805 	qp = to_mqp(ibqp);
3806 	bf = qp->bf;
3807 	qend = qp->sq.qend;
3808 
3809 	spin_lock_irqsave(&qp->sq.lock, flags);
3810 
3811 	if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
3812 		err = -EIO;
3813 		*bad_wr = wr;
3814 		nreq = 0;
3815 		goto out;
3816 	}
3817 
3818 	for (nreq = 0; wr; nreq++, wr = wr->next) {
3819 		if (unlikely(wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
3820 			mlx5_ib_warn(dev, "\n");
3821 			err = -EINVAL;
3822 			*bad_wr = wr;
3823 			goto out;
3824 		}
3825 
3826 		fence = qp->fm_cache;
3827 		num_sge = wr->num_sge;
3828 		if (unlikely(num_sge > qp->sq.max_gs)) {
3829 			mlx5_ib_warn(dev, "\n");
3830 			err = -EINVAL;
3831 			*bad_wr = wr;
3832 			goto out;
3833 		}
3834 
3835 		err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3836 		if (err) {
3837 			mlx5_ib_warn(dev, "\n");
3838 			err = -ENOMEM;
3839 			*bad_wr = wr;
3840 			goto out;
3841 		}
3842 
3843 		switch (ibqp->qp_type) {
3844 		case IB_QPT_XRC_INI:
3845 			xrc = seg;
3846 			seg += sizeof(*xrc);
3847 			size += sizeof(*xrc) / 16;
3848 			/* fall through */
3849 		case IB_QPT_RC:
3850 			switch (wr->opcode) {
3851 			case IB_WR_RDMA_READ:
3852 			case IB_WR_RDMA_WRITE:
3853 			case IB_WR_RDMA_WRITE_WITH_IMM:
3854 				set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3855 					      rdma_wr(wr)->rkey);
3856 				seg += sizeof(struct mlx5_wqe_raddr_seg);
3857 				size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3858 				break;
3859 
3860 			case IB_WR_ATOMIC_CMP_AND_SWP:
3861 			case IB_WR_ATOMIC_FETCH_AND_ADD:
3862 			case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3863 				mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3864 				err = -ENOSYS;
3865 				*bad_wr = wr;
3866 				goto out;
3867 
3868 			case IB_WR_LOCAL_INV:
3869 				next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3870 				qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3871 				ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
3872 				set_linv_wr(qp, &seg, &size);
3873 				num_sge = 0;
3874 				break;
3875 
3876 			case IB_WR_REG_MR:
3877 				next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3878 				qp->sq.wr_data[idx] = IB_WR_REG_MR;
3879 				ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3880 				err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3881 				if (err) {
3882 					*bad_wr = wr;
3883 					goto out;
3884 				}
3885 				num_sge = 0;
3886 				break;
3887 
3888 			case IB_WR_REG_SIG_MR:
3889 				qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
3890 				mr = to_mmr(sig_handover_wr(wr)->sig_mr);
3891 
3892 				ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3893 				err = set_sig_umr_wr(wr, qp, &seg, &size);
3894 				if (err) {
3895 					mlx5_ib_warn(dev, "\n");
3896 					*bad_wr = wr;
3897 					goto out;
3898 				}
3899 
3900 				finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3901 					   nreq, get_fence(fence, wr),
3902 					   next_fence, MLX5_OPCODE_UMR);
3903 				/*
3904 				 * SET_PSV WQEs are not signaled and solicited
3905 				 * on error
3906 				 */
3907 				wr->send_flags &= ~IB_SEND_SIGNALED;
3908 				wr->send_flags |= IB_SEND_SOLICITED;
3909 				err = begin_wqe(qp, &seg, &ctrl, wr,
3910 						&idx, &size, nreq);
3911 				if (err) {
3912 					mlx5_ib_warn(dev, "\n");
3913 					err = -ENOMEM;
3914 					*bad_wr = wr;
3915 					goto out;
3916 				}
3917 
3918 				err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
3919 						 mr->sig->psv_memory.psv_idx, &seg,
3920 						 &size);
3921 				if (err) {
3922 					mlx5_ib_warn(dev, "\n");
3923 					*bad_wr = wr;
3924 					goto out;
3925 				}
3926 
3927 				finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3928 					   nreq, get_fence(fence, wr),
3929 					   next_fence, MLX5_OPCODE_SET_PSV);
3930 				err = begin_wqe(qp, &seg, &ctrl, wr,
3931 						&idx, &size, nreq);
3932 				if (err) {
3933 					mlx5_ib_warn(dev, "\n");
3934 					err = -ENOMEM;
3935 					*bad_wr = wr;
3936 					goto out;
3937 				}
3938 
3939 				next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3940 				err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
3941 						 mr->sig->psv_wire.psv_idx, &seg,
3942 						 &size);
3943 				if (err) {
3944 					mlx5_ib_warn(dev, "\n");
3945 					*bad_wr = wr;
3946 					goto out;
3947 				}
3948 
3949 				finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3950 					   nreq, get_fence(fence, wr),
3951 					   next_fence, MLX5_OPCODE_SET_PSV);
3952 				num_sge = 0;
3953 				goto skip_psv;
3954 
3955 			default:
3956 				break;
3957 			}
3958 			break;
3959 
3960 		case IB_QPT_UC:
3961 			switch (wr->opcode) {
3962 			case IB_WR_RDMA_WRITE:
3963 			case IB_WR_RDMA_WRITE_WITH_IMM:
3964 				set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3965 					      rdma_wr(wr)->rkey);
3966 				seg  += sizeof(struct mlx5_wqe_raddr_seg);
3967 				size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3968 				break;
3969 
3970 			default:
3971 				break;
3972 			}
3973 			break;
3974 
3975 		case IB_QPT_SMI:
3976 		case MLX5_IB_QPT_HW_GSI:
3977 			set_datagram_seg(seg, wr);
3978 			seg += sizeof(struct mlx5_wqe_datagram_seg);
3979 			size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3980 			if (unlikely((seg == qend)))
3981 				seg = mlx5_get_send_wqe(qp, 0);
3982 			break;
3983 		case IB_QPT_UD:
3984 			set_datagram_seg(seg, wr);
3985 			seg += sizeof(struct mlx5_wqe_datagram_seg);
3986 			size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3987 
3988 			if (unlikely((seg == qend)))
3989 				seg = mlx5_get_send_wqe(qp, 0);
3990 
3991 			/* handle qp that supports ud offload */
3992 			if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
3993 				struct mlx5_wqe_eth_pad *pad;
3994 
3995 				pad = seg;
3996 				memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
3997 				seg += sizeof(struct mlx5_wqe_eth_pad);
3998 				size += sizeof(struct mlx5_wqe_eth_pad) / 16;
3999 
4000 				seg = set_eth_seg(seg, wr, qend, qp, &size);
4001 
4002 				if (unlikely((seg == qend)))
4003 					seg = mlx5_get_send_wqe(qp, 0);
4004 			}
4005 			break;
4006 		case MLX5_IB_QPT_REG_UMR:
4007 			if (wr->opcode != MLX5_IB_WR_UMR) {
4008 				err = -EINVAL;
4009 				mlx5_ib_warn(dev, "bad opcode\n");
4010 				goto out;
4011 			}
4012 			qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4013 			ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4014 			set_reg_umr_segment(seg, wr);
4015 			seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4016 			size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4017 			if (unlikely((seg == qend)))
4018 				seg = mlx5_get_send_wqe(qp, 0);
4019 			set_reg_mkey_segment(seg, wr);
4020 			seg += sizeof(struct mlx5_mkey_seg);
4021 			size += sizeof(struct mlx5_mkey_seg) / 16;
4022 			if (unlikely((seg == qend)))
4023 				seg = mlx5_get_send_wqe(qp, 0);
4024 			break;
4025 
4026 		default:
4027 			break;
4028 		}
4029 
4030 		if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4031 			int uninitialized_var(sz);
4032 
4033 			err = set_data_inl_seg(qp, wr, seg, &sz);
4034 			if (unlikely(err)) {
4035 				mlx5_ib_warn(dev, "\n");
4036 				*bad_wr = wr;
4037 				goto out;
4038 			}
4039 			inl = 1;
4040 			size += sz;
4041 		} else {
4042 			dpseg = seg;
4043 			for (i = 0; i < num_sge; i++) {
4044 				if (unlikely(dpseg == qend)) {
4045 					seg = mlx5_get_send_wqe(qp, 0);
4046 					dpseg = seg;
4047 				}
4048 				if (likely(wr->sg_list[i].length)) {
4049 					set_data_ptr_seg(dpseg, wr->sg_list + i);
4050 					size += sizeof(struct mlx5_wqe_data_seg) / 16;
4051 					dpseg++;
4052 				}
4053 			}
4054 		}
4055 
4056 		finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4057 			   get_fence(fence, wr), next_fence,
4058 			   mlx5_ib_opcode[wr->opcode]);
4059 skip_psv:
4060 		if (0)
4061 			dump_wqe(qp, idx, size);
4062 	}
4063 
4064 out:
4065 	if (likely(nreq)) {
4066 		qp->sq.head += nreq;
4067 
4068 		/* Make sure that descriptors are written before
4069 		 * updating doorbell record and ringing the doorbell
4070 		 */
4071 		wmb();
4072 
4073 		qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4074 
4075 		/* Make sure doorbell record is visible to the HCA before
4076 		 * we hit doorbell */
4077 		wmb();
4078 
4079 		if (bf->need_lock)
4080 			spin_lock(&bf->lock);
4081 		else
4082 			__acquire(&bf->lock);
4083 
4084 		/* TBD enable WC */
4085 		if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
4086 			mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
4087 			/* wc_wmb(); */
4088 		} else {
4089 			mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
4090 				     MLX5_GET_DOORBELL_LOCK(&bf->lock32));
4091 			/* Make sure doorbells don't leak out of SQ spinlock
4092 			 * and reach the HCA out of order.
4093 			 */
4094 			mmiowb();
4095 		}
4096 		bf->offset ^= bf->buf_size;
4097 		if (bf->need_lock)
4098 			spin_unlock(&bf->lock);
4099 		else
4100 			__release(&bf->lock);
4101 	}
4102 
4103 	spin_unlock_irqrestore(&qp->sq.lock, flags);
4104 
4105 	return err;
4106 }
4107 
4108 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4109 {
4110 	sig->signature = calc_sig(sig, size);
4111 }
4112 
4113 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4114 		      struct ib_recv_wr **bad_wr)
4115 {
4116 	struct mlx5_ib_qp *qp = to_mqp(ibqp);
4117 	struct mlx5_wqe_data_seg *scat;
4118 	struct mlx5_rwqe_sig *sig;
4119 	struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4120 	struct mlx5_core_dev *mdev = dev->mdev;
4121 	unsigned long flags;
4122 	int err = 0;
4123 	int nreq;
4124 	int ind;
4125 	int i;
4126 
4127 	if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4128 		return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4129 
4130 	spin_lock_irqsave(&qp->rq.lock, flags);
4131 
4132 	if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4133 		err = -EIO;
4134 		*bad_wr = wr;
4135 		nreq = 0;
4136 		goto out;
4137 	}
4138 
4139 	ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4140 
4141 	for (nreq = 0; wr; nreq++, wr = wr->next) {
4142 		if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4143 			err = -ENOMEM;
4144 			*bad_wr = wr;
4145 			goto out;
4146 		}
4147 
4148 		if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4149 			err = -EINVAL;
4150 			*bad_wr = wr;
4151 			goto out;
4152 		}
4153 
4154 		scat = get_recv_wqe(qp, ind);
4155 		if (qp->wq_sig)
4156 			scat++;
4157 
4158 		for (i = 0; i < wr->num_sge; i++)
4159 			set_data_ptr_seg(scat + i, wr->sg_list + i);
4160 
4161 		if (i < qp->rq.max_gs) {
4162 			scat[i].byte_count = 0;
4163 			scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
4164 			scat[i].addr       = 0;
4165 		}
4166 
4167 		if (qp->wq_sig) {
4168 			sig = (struct mlx5_rwqe_sig *)scat;
4169 			set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4170 		}
4171 
4172 		qp->rq.wrid[ind] = wr->wr_id;
4173 
4174 		ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4175 	}
4176 
4177 out:
4178 	if (likely(nreq)) {
4179 		qp->rq.head += nreq;
4180 
4181 		/* Make sure that descriptors are written before
4182 		 * doorbell record.
4183 		 */
4184 		wmb();
4185 
4186 		*qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4187 	}
4188 
4189 	spin_unlock_irqrestore(&qp->rq.lock, flags);
4190 
4191 	return err;
4192 }
4193 
4194 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4195 {
4196 	switch (mlx5_state) {
4197 	case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
4198 	case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
4199 	case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
4200 	case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
4201 	case MLX5_QP_STATE_SQ_DRAINING:
4202 	case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
4203 	case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
4204 	case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
4205 	default:		     return -1;
4206 	}
4207 }
4208 
4209 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4210 {
4211 	switch (mlx5_mig_state) {
4212 	case MLX5_QP_PM_ARMED:		return IB_MIG_ARMED;
4213 	case MLX5_QP_PM_REARM:		return IB_MIG_REARM;
4214 	case MLX5_QP_PM_MIGRATED:	return IB_MIG_MIGRATED;
4215 	default: return -1;
4216 	}
4217 }
4218 
4219 static int to_ib_qp_access_flags(int mlx5_flags)
4220 {
4221 	int ib_flags = 0;
4222 
4223 	if (mlx5_flags & MLX5_QP_BIT_RRE)
4224 		ib_flags |= IB_ACCESS_REMOTE_READ;
4225 	if (mlx5_flags & MLX5_QP_BIT_RWE)
4226 		ib_flags |= IB_ACCESS_REMOTE_WRITE;
4227 	if (mlx5_flags & MLX5_QP_BIT_RAE)
4228 		ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4229 
4230 	return ib_flags;
4231 }
4232 
4233 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
4234 				struct mlx5_qp_path *path)
4235 {
4236 	struct mlx5_core_dev *dev = ibdev->mdev;
4237 
4238 	memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
4239 	ib_ah_attr->port_num	  = path->port;
4240 
4241 	if (ib_ah_attr->port_num == 0 ||
4242 	    ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports))
4243 		return;
4244 
4245 	ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf;
4246 
4247 	ib_ah_attr->dlid	  = be16_to_cpu(path->rlid);
4248 	ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
4249 	ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
4250 	ib_ah_attr->ah_flags      = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
4251 	if (ib_ah_attr->ah_flags) {
4252 		ib_ah_attr->grh.sgid_index = path->mgid_index;
4253 		ib_ah_attr->grh.hop_limit  = path->hop_limit;
4254 		ib_ah_attr->grh.traffic_class =
4255 			(be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
4256 		ib_ah_attr->grh.flow_label =
4257 			be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
4258 		memcpy(ib_ah_attr->grh.dgid.raw,
4259 		       path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
4260 	}
4261 }
4262 
4263 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4264 					struct mlx5_ib_sq *sq,
4265 					u8 *sq_state)
4266 {
4267 	void *out;
4268 	void *sqc;
4269 	int inlen;
4270 	int err;
4271 
4272 	inlen = MLX5_ST_SZ_BYTES(query_sq_out);
4273 	out = mlx5_vzalloc(inlen);
4274 	if (!out)
4275 		return -ENOMEM;
4276 
4277 	err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4278 	if (err)
4279 		goto out;
4280 
4281 	sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4282 	*sq_state = MLX5_GET(sqc, sqc, state);
4283 	sq->state = *sq_state;
4284 
4285 out:
4286 	kvfree(out);
4287 	return err;
4288 }
4289 
4290 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4291 					struct mlx5_ib_rq *rq,
4292 					u8 *rq_state)
4293 {
4294 	void *out;
4295 	void *rqc;
4296 	int inlen;
4297 	int err;
4298 
4299 	inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4300 	out = mlx5_vzalloc(inlen);
4301 	if (!out)
4302 		return -ENOMEM;
4303 
4304 	err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4305 	if (err)
4306 		goto out;
4307 
4308 	rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4309 	*rq_state = MLX5_GET(rqc, rqc, state);
4310 	rq->state = *rq_state;
4311 
4312 out:
4313 	kvfree(out);
4314 	return err;
4315 }
4316 
4317 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4318 				  struct mlx5_ib_qp *qp, u8 *qp_state)
4319 {
4320 	static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4321 		[MLX5_RQC_STATE_RST] = {
4322 			[MLX5_SQC_STATE_RST]	= IB_QPS_RESET,
4323 			[MLX5_SQC_STATE_RDY]	= MLX5_QP_STATE_BAD,
4324 			[MLX5_SQC_STATE_ERR]	= MLX5_QP_STATE_BAD,
4325 			[MLX5_SQ_STATE_NA]	= IB_QPS_RESET,
4326 		},
4327 		[MLX5_RQC_STATE_RDY] = {
4328 			[MLX5_SQC_STATE_RST]	= MLX5_QP_STATE_BAD,
4329 			[MLX5_SQC_STATE_RDY]	= MLX5_QP_STATE,
4330 			[MLX5_SQC_STATE_ERR]	= IB_QPS_SQE,
4331 			[MLX5_SQ_STATE_NA]	= MLX5_QP_STATE,
4332 		},
4333 		[MLX5_RQC_STATE_ERR] = {
4334 			[MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
4335 			[MLX5_SQC_STATE_RDY]	= MLX5_QP_STATE_BAD,
4336 			[MLX5_SQC_STATE_ERR]	= IB_QPS_ERR,
4337 			[MLX5_SQ_STATE_NA]	= IB_QPS_ERR,
4338 		},
4339 		[MLX5_RQ_STATE_NA] = {
4340 			[MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
4341 			[MLX5_SQC_STATE_RDY]	= MLX5_QP_STATE,
4342 			[MLX5_SQC_STATE_ERR]	= MLX5_QP_STATE,
4343 			[MLX5_SQ_STATE_NA]	= MLX5_QP_STATE_BAD,
4344 		},
4345 	};
4346 
4347 	*qp_state = sqrq_trans[rq_state][sq_state];
4348 
4349 	if (*qp_state == MLX5_QP_STATE_BAD) {
4350 		WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4351 		     qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4352 		     qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4353 		return -EINVAL;
4354 	}
4355 
4356 	if (*qp_state == MLX5_QP_STATE)
4357 		*qp_state = qp->state;
4358 
4359 	return 0;
4360 }
4361 
4362 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4363 				     struct mlx5_ib_qp *qp,
4364 				     u8 *raw_packet_qp_state)
4365 {
4366 	struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4367 	struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4368 	struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4369 	int err;
4370 	u8 sq_state = MLX5_SQ_STATE_NA;
4371 	u8 rq_state = MLX5_RQ_STATE_NA;
4372 
4373 	if (qp->sq.wqe_cnt) {
4374 		err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4375 		if (err)
4376 			return err;
4377 	}
4378 
4379 	if (qp->rq.wqe_cnt) {
4380 		err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4381 		if (err)
4382 			return err;
4383 	}
4384 
4385 	return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4386 				      raw_packet_qp_state);
4387 }
4388 
4389 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4390 			 struct ib_qp_attr *qp_attr)
4391 {
4392 	int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
4393 	struct mlx5_qp_context *context;
4394 	int mlx5_state;
4395 	u32 *outb;
4396 	int err = 0;
4397 
4398 	outb = kzalloc(outlen, GFP_KERNEL);
4399 	if (!outb)
4400 		return -ENOMEM;
4401 
4402 	err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
4403 				 outlen);
4404 	if (err)
4405 		goto out;
4406 
4407 	/* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4408 	context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4409 
4410 	mlx5_state = be32_to_cpu(context->flags) >> 28;
4411 
4412 	qp->state		     = to_ib_qp_state(mlx5_state);
4413 	qp_attr->path_mtu	     = context->mtu_msgmax >> 5;
4414 	qp_attr->path_mig_state	     =
4415 		to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4416 	qp_attr->qkey		     = be32_to_cpu(context->qkey);
4417 	qp_attr->rq_psn		     = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4418 	qp_attr->sq_psn		     = be32_to_cpu(context->next_send_psn) & 0xffffff;
4419 	qp_attr->dest_qp_num	     = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4420 	qp_attr->qp_access_flags     =
4421 		to_ib_qp_access_flags(be32_to_cpu(context->params2));
4422 
4423 	if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4424 		to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4425 		to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
4426 		qp_attr->alt_pkey_index =
4427 			be16_to_cpu(context->alt_path.pkey_index);
4428 		qp_attr->alt_port_num	= qp_attr->alt_ah_attr.port_num;
4429 	}
4430 
4431 	qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
4432 	qp_attr->port_num = context->pri_path.port;
4433 
4434 	/* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4435 	qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4436 
4437 	qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4438 
4439 	qp_attr->max_dest_rd_atomic =
4440 		1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4441 	qp_attr->min_rnr_timer	    =
4442 		(be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4443 	qp_attr->timeout	    = context->pri_path.ackto_lt >> 3;
4444 	qp_attr->retry_cnt	    = (be32_to_cpu(context->params1) >> 16) & 0x7;
4445 	qp_attr->rnr_retry	    = (be32_to_cpu(context->params1) >> 13) & 0x7;
4446 	qp_attr->alt_timeout	    = context->alt_path.ackto_lt >> 3;
4447 
4448 out:
4449 	kfree(outb);
4450 	return err;
4451 }
4452 
4453 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4454 		     int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4455 {
4456 	struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4457 	struct mlx5_ib_qp *qp = to_mqp(ibqp);
4458 	int err = 0;
4459 	u8 raw_packet_qp_state;
4460 
4461 	if (ibqp->rwq_ind_tbl)
4462 		return -ENOSYS;
4463 
4464 	if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4465 		return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4466 					    qp_init_attr);
4467 
4468 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4469 	/*
4470 	 * Wait for any outstanding page faults, in case the user frees memory
4471 	 * based upon this query's result.
4472 	 */
4473 	flush_workqueue(mlx5_ib_page_fault_wq);
4474 #endif
4475 
4476 	mutex_lock(&qp->mutex);
4477 
4478 	if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
4479 		err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4480 		if (err)
4481 			goto out;
4482 		qp->state = raw_packet_qp_state;
4483 		qp_attr->port_num = 1;
4484 	} else {
4485 		err = query_qp_attr(dev, qp, qp_attr);
4486 		if (err)
4487 			goto out;
4488 	}
4489 
4490 	qp_attr->qp_state	     = qp->state;
4491 	qp_attr->cur_qp_state	     = qp_attr->qp_state;
4492 	qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
4493 	qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
4494 
4495 	if (!ibqp->uobject) {
4496 		qp_attr->cap.max_send_wr  = qp->sq.max_post;
4497 		qp_attr->cap.max_send_sge = qp->sq.max_gs;
4498 		qp_init_attr->qp_context = ibqp->qp_context;
4499 	} else {
4500 		qp_attr->cap.max_send_wr  = 0;
4501 		qp_attr->cap.max_send_sge = 0;
4502 	}
4503 
4504 	qp_init_attr->qp_type = ibqp->qp_type;
4505 	qp_init_attr->recv_cq = ibqp->recv_cq;
4506 	qp_init_attr->send_cq = ibqp->send_cq;
4507 	qp_init_attr->srq = ibqp->srq;
4508 	qp_attr->cap.max_inline_data = qp->max_inline_data;
4509 
4510 	qp_init_attr->cap	     = qp_attr->cap;
4511 
4512 	qp_init_attr->create_flags = 0;
4513 	if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4514 		qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4515 
4516 	if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4517 		qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4518 	if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4519 		qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4520 	if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4521 		qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
4522 	if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4523 		qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
4524 
4525 	qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4526 		IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4527 
4528 out:
4529 	mutex_unlock(&qp->mutex);
4530 	return err;
4531 }
4532 
4533 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4534 					  struct ib_ucontext *context,
4535 					  struct ib_udata *udata)
4536 {
4537 	struct mlx5_ib_dev *dev = to_mdev(ibdev);
4538 	struct mlx5_ib_xrcd *xrcd;
4539 	int err;
4540 
4541 	if (!MLX5_CAP_GEN(dev->mdev, xrc))
4542 		return ERR_PTR(-ENOSYS);
4543 
4544 	xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4545 	if (!xrcd)
4546 		return ERR_PTR(-ENOMEM);
4547 
4548 	err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
4549 	if (err) {
4550 		kfree(xrcd);
4551 		return ERR_PTR(-ENOMEM);
4552 	}
4553 
4554 	return &xrcd->ibxrcd;
4555 }
4556 
4557 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4558 {
4559 	struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4560 	u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4561 	int err;
4562 
4563 	err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
4564 	if (err) {
4565 		mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4566 		return err;
4567 	}
4568 
4569 	kfree(xrcd);
4570 
4571 	return 0;
4572 }
4573 
4574 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4575 {
4576 	struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4577 	struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4578 	struct ib_event event;
4579 
4580 	if (rwq->ibwq.event_handler) {
4581 		event.device     = rwq->ibwq.device;
4582 		event.element.wq = &rwq->ibwq;
4583 		switch (type) {
4584 		case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4585 			event.event = IB_EVENT_WQ_FATAL;
4586 			break;
4587 		default:
4588 			mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4589 			return;
4590 		}
4591 
4592 		rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4593 	}
4594 }
4595 
4596 static int  create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4597 		      struct ib_wq_init_attr *init_attr)
4598 {
4599 	struct mlx5_ib_dev *dev;
4600 	__be64 *rq_pas0;
4601 	void *in;
4602 	void *rqc;
4603 	void *wq;
4604 	int inlen;
4605 	int err;
4606 
4607 	dev = to_mdev(pd->device);
4608 
4609 	inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4610 	in = mlx5_vzalloc(inlen);
4611 	if (!in)
4612 		return -ENOMEM;
4613 
4614 	rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4615 	MLX5_SET(rqc,  rqc, mem_rq_type,
4616 		 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE);
4617 	MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4618 	MLX5_SET(rqc,  rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4619 	MLX5_SET(rqc,  rqc, state, MLX5_RQC_STATE_RST);
4620 	MLX5_SET(rqc,  rqc, flush_in_error_en, 1);
4621 	wq = MLX5_ADDR_OF(rqc, rqc, wq);
4622 	MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
4623 	MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4624 	MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4625 	MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4626 	MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4627 	MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4628 	MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4629 	MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4630 	MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4631 	rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4632 	mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
4633 	err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
4634 	kvfree(in);
4635 	return err;
4636 }
4637 
4638 static int set_user_rq_size(struct mlx5_ib_dev *dev,
4639 			    struct ib_wq_init_attr *wq_init_attr,
4640 			    struct mlx5_ib_create_wq *ucmd,
4641 			    struct mlx5_ib_rwq *rwq)
4642 {
4643 	/* Sanity check RQ size before proceeding */
4644 	if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4645 		return -EINVAL;
4646 
4647 	if (!ucmd->rq_wqe_count)
4648 		return -EINVAL;
4649 
4650 	rwq->wqe_count = ucmd->rq_wqe_count;
4651 	rwq->wqe_shift = ucmd->rq_wqe_shift;
4652 	rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4653 	rwq->log_rq_stride = rwq->wqe_shift;
4654 	rwq->log_rq_size = ilog2(rwq->wqe_count);
4655 	return 0;
4656 }
4657 
4658 static int prepare_user_rq(struct ib_pd *pd,
4659 			   struct ib_wq_init_attr *init_attr,
4660 			   struct ib_udata *udata,
4661 			   struct mlx5_ib_rwq *rwq)
4662 {
4663 	struct mlx5_ib_dev *dev = to_mdev(pd->device);
4664 	struct mlx5_ib_create_wq ucmd = {};
4665 	int err;
4666 	size_t required_cmd_sz;
4667 
4668 	required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4669 	if (udata->inlen < required_cmd_sz) {
4670 		mlx5_ib_dbg(dev, "invalid inlen\n");
4671 		return -EINVAL;
4672 	}
4673 
4674 	if (udata->inlen > sizeof(ucmd) &&
4675 	    !ib_is_udata_cleared(udata, sizeof(ucmd),
4676 				 udata->inlen - sizeof(ucmd))) {
4677 		mlx5_ib_dbg(dev, "inlen is not supported\n");
4678 		return -EOPNOTSUPP;
4679 	}
4680 
4681 	if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4682 		mlx5_ib_dbg(dev, "copy failed\n");
4683 		return -EFAULT;
4684 	}
4685 
4686 	if (ucmd.comp_mask) {
4687 		mlx5_ib_dbg(dev, "invalid comp mask\n");
4688 		return -EOPNOTSUPP;
4689 	}
4690 
4691 	if (ucmd.reserved) {
4692 		mlx5_ib_dbg(dev, "invalid reserved\n");
4693 		return -EOPNOTSUPP;
4694 	}
4695 
4696 	err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4697 	if (err) {
4698 		mlx5_ib_dbg(dev, "err %d\n", err);
4699 		return err;
4700 	}
4701 
4702 	err = create_user_rq(dev, pd, rwq, &ucmd);
4703 	if (err) {
4704 		mlx5_ib_dbg(dev, "err %d\n", err);
4705 		if (err)
4706 			return err;
4707 	}
4708 
4709 	rwq->user_index = ucmd.user_index;
4710 	return 0;
4711 }
4712 
4713 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4714 				struct ib_wq_init_attr *init_attr,
4715 				struct ib_udata *udata)
4716 {
4717 	struct mlx5_ib_dev *dev;
4718 	struct mlx5_ib_rwq *rwq;
4719 	struct mlx5_ib_create_wq_resp resp = {};
4720 	size_t min_resp_len;
4721 	int err;
4722 
4723 	if (!udata)
4724 		return ERR_PTR(-ENOSYS);
4725 
4726 	min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4727 	if (udata->outlen && udata->outlen < min_resp_len)
4728 		return ERR_PTR(-EINVAL);
4729 
4730 	dev = to_mdev(pd->device);
4731 	switch (init_attr->wq_type) {
4732 	case IB_WQT_RQ:
4733 		rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4734 		if (!rwq)
4735 			return ERR_PTR(-ENOMEM);
4736 		err = prepare_user_rq(pd, init_attr, udata, rwq);
4737 		if (err)
4738 			goto err;
4739 		err = create_rq(rwq, pd, init_attr);
4740 		if (err)
4741 			goto err_user_rq;
4742 		break;
4743 	default:
4744 		mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4745 			    init_attr->wq_type);
4746 		return ERR_PTR(-EINVAL);
4747 	}
4748 
4749 	rwq->ibwq.wq_num = rwq->core_qp.qpn;
4750 	rwq->ibwq.state = IB_WQS_RESET;
4751 	if (udata->outlen) {
4752 		resp.response_length = offsetof(typeof(resp), response_length) +
4753 				sizeof(resp.response_length);
4754 		err = ib_copy_to_udata(udata, &resp, resp.response_length);
4755 		if (err)
4756 			goto err_copy;
4757 	}
4758 
4759 	rwq->core_qp.event = mlx5_ib_wq_event;
4760 	rwq->ibwq.event_handler = init_attr->event_handler;
4761 	return &rwq->ibwq;
4762 
4763 err_copy:
4764 	mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4765 err_user_rq:
4766 	destroy_user_rq(pd, rwq);
4767 err:
4768 	kfree(rwq);
4769 	return ERR_PTR(err);
4770 }
4771 
4772 int mlx5_ib_destroy_wq(struct ib_wq *wq)
4773 {
4774 	struct mlx5_ib_dev *dev = to_mdev(wq->device);
4775 	struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4776 
4777 	mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4778 	destroy_user_rq(wq->pd, rwq);
4779 	kfree(rwq);
4780 
4781 	return 0;
4782 }
4783 
4784 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
4785 						      struct ib_rwq_ind_table_init_attr *init_attr,
4786 						      struct ib_udata *udata)
4787 {
4788 	struct mlx5_ib_dev *dev = to_mdev(device);
4789 	struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
4790 	int sz = 1 << init_attr->log_ind_tbl_size;
4791 	struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
4792 	size_t min_resp_len;
4793 	int inlen;
4794 	int err;
4795 	int i;
4796 	u32 *in;
4797 	void *rqtc;
4798 
4799 	if (udata->inlen > 0 &&
4800 	    !ib_is_udata_cleared(udata, 0,
4801 				 udata->inlen))
4802 		return ERR_PTR(-EOPNOTSUPP);
4803 
4804 	if (init_attr->log_ind_tbl_size >
4805 	    MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
4806 		mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
4807 			    init_attr->log_ind_tbl_size,
4808 			    MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
4809 		return ERR_PTR(-EINVAL);
4810 	}
4811 
4812 	min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4813 	if (udata->outlen && udata->outlen < min_resp_len)
4814 		return ERR_PTR(-EINVAL);
4815 
4816 	rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
4817 	if (!rwq_ind_tbl)
4818 		return ERR_PTR(-ENOMEM);
4819 
4820 	inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
4821 	in = mlx5_vzalloc(inlen);
4822 	if (!in) {
4823 		err = -ENOMEM;
4824 		goto err;
4825 	}
4826 
4827 	rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
4828 
4829 	MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
4830 	MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
4831 
4832 	for (i = 0; i < sz; i++)
4833 		MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
4834 
4835 	err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
4836 	kvfree(in);
4837 
4838 	if (err)
4839 		goto err;
4840 
4841 	rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
4842 	if (udata->outlen) {
4843 		resp.response_length = offsetof(typeof(resp), response_length) +
4844 					sizeof(resp.response_length);
4845 		err = ib_copy_to_udata(udata, &resp, resp.response_length);
4846 		if (err)
4847 			goto err_copy;
4848 	}
4849 
4850 	return &rwq_ind_tbl->ib_rwq_ind_tbl;
4851 
4852 err_copy:
4853 	mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4854 err:
4855 	kfree(rwq_ind_tbl);
4856 	return ERR_PTR(err);
4857 }
4858 
4859 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4860 {
4861 	struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
4862 	struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
4863 
4864 	mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4865 
4866 	kfree(rwq_ind_tbl);
4867 	return 0;
4868 }
4869 
4870 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
4871 		      u32 wq_attr_mask, struct ib_udata *udata)
4872 {
4873 	struct mlx5_ib_dev *dev = to_mdev(wq->device);
4874 	struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4875 	struct mlx5_ib_modify_wq ucmd = {};
4876 	size_t required_cmd_sz;
4877 	int curr_wq_state;
4878 	int wq_state;
4879 	int inlen;
4880 	int err;
4881 	void *rqc;
4882 	void *in;
4883 
4884 	required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4885 	if (udata->inlen < required_cmd_sz)
4886 		return -EINVAL;
4887 
4888 	if (udata->inlen > sizeof(ucmd) &&
4889 	    !ib_is_udata_cleared(udata, sizeof(ucmd),
4890 				 udata->inlen - sizeof(ucmd)))
4891 		return -EOPNOTSUPP;
4892 
4893 	if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4894 		return -EFAULT;
4895 
4896 	if (ucmd.comp_mask || ucmd.reserved)
4897 		return -EOPNOTSUPP;
4898 
4899 	inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
4900 	in = mlx5_vzalloc(inlen);
4901 	if (!in)
4902 		return -ENOMEM;
4903 
4904 	rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
4905 
4906 	MLX5_SET(modify_rq_in, in, rqn, rwq->core_qp.qpn);
4907 	curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
4908 		wq_attr->curr_wq_state : wq->state;
4909 	wq_state = (wq_attr_mask & IB_WQ_STATE) ?
4910 		wq_attr->wq_state : curr_wq_state;
4911 	if (curr_wq_state == IB_WQS_ERR)
4912 		curr_wq_state = MLX5_RQC_STATE_ERR;
4913 	if (wq_state == IB_WQS_ERR)
4914 		wq_state = MLX5_RQC_STATE_ERR;
4915 	MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
4916 	MLX5_SET(rqc, rqc, state, wq_state);
4917 
4918 	err = mlx5_core_modify_rq(dev->mdev, in, inlen);
4919 	kvfree(in);
4920 	if (!err)
4921 		rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
4922 
4923 	return err;
4924 }
4925