1 /*- 2 * Copyright (c) 2013-2021, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include "opt_rss.h" 29 #include "opt_ratelimit.h" 30 31 #include <linux/module.h> 32 #include <linux/errno.h> 33 #include <linux/pci.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/slab.h> 36 #if defined(CONFIG_X86) 37 #include <asm/pat.h> 38 #endif 39 #include <linux/sched.h> 40 #include <linux/delay.h> 41 #include <linux/fs.h> 42 #undef inode 43 #include <rdma/ib_user_verbs.h> 44 #include <rdma/ib_addr.h> 45 #include <rdma/ib_cache.h> 46 #include <dev/mlx5/port.h> 47 #include <dev/mlx5/vport.h> 48 #include <linux/list.h> 49 #include <rdma/ib_smi.h> 50 #include <rdma/ib_umem.h> 51 #include <rdma/uverbs_ioctl.h> 52 #include <linux/in.h> 53 #include <linux/etherdevice.h> 54 #include <dev/mlx5/fs.h> 55 #include <dev/mlx5/mlx5_ib/mlx5_ib.h> 56 57 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 58 MODULE_LICENSE("Dual BSD/GPL"); 59 MODULE_DEPEND(mlx5ib, linuxkpi, 1, 1, 1); 60 MODULE_DEPEND(mlx5ib, mlx5, 1, 1, 1); 61 MODULE_DEPEND(mlx5ib, ibcore, 1, 1, 1); 62 MODULE_VERSION(mlx5ib, 1); 63 64 enum { 65 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 66 }; 67 68 static enum rdma_link_layer 69 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 70 { 71 switch (port_type_cap) { 72 case MLX5_CAP_PORT_TYPE_IB: 73 return IB_LINK_LAYER_INFINIBAND; 74 case MLX5_CAP_PORT_TYPE_ETH: 75 return IB_LINK_LAYER_ETHERNET; 76 default: 77 return IB_LINK_LAYER_UNSPECIFIED; 78 } 79 } 80 81 static enum rdma_link_layer 82 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 83 { 84 struct mlx5_ib_dev *dev = to_mdev(device); 85 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 86 87 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 88 } 89 90 static bool mlx5_netdev_match(struct ifnet *ndev, 91 struct mlx5_core_dev *mdev, 92 const char *dname) 93 { 94 return ndev->if_type == IFT_ETHER && 95 ndev->if_dname != NULL && 96 strcmp(ndev->if_dname, dname) == 0 && 97 ndev->if_softc != NULL && 98 *(struct mlx5_core_dev **)ndev->if_softc == mdev; 99 } 100 101 static int mlx5_netdev_event(struct notifier_block *this, 102 unsigned long event, void *ptr) 103 { 104 struct ifnet *ndev = netdev_notifier_info_to_ifp(ptr); 105 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev, 106 roce.nb); 107 108 switch (event) { 109 case NETDEV_REGISTER: 110 case NETDEV_UNREGISTER: 111 write_lock(&ibdev->roce.netdev_lock); 112 /* check if network interface belongs to mlx5en */ 113 if (mlx5_netdev_match(ndev, ibdev->mdev, "mce")) 114 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? 115 NULL : ndev; 116 write_unlock(&ibdev->roce.netdev_lock); 117 break; 118 119 case NETDEV_UP: 120 case NETDEV_DOWN: { 121 struct ifnet *upper = NULL; 122 123 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev)) 124 && ibdev->ib_active) { 125 struct ib_event ibev = {0}; 126 127 ibev.device = &ibdev->ib_dev; 128 ibev.event = (event == NETDEV_UP) ? 129 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 130 ibev.element.port_num = 1; 131 ib_dispatch_event(&ibev); 132 } 133 break; 134 } 135 136 default: 137 break; 138 } 139 140 return NOTIFY_DONE; 141 } 142 143 static struct ifnet *mlx5_ib_get_netdev(struct ib_device *device, 144 u8 port_num) 145 { 146 struct mlx5_ib_dev *ibdev = to_mdev(device); 147 struct ifnet *ndev; 148 149 /* Ensure ndev does not disappear before we invoke if_ref() 150 */ 151 read_lock(&ibdev->roce.netdev_lock); 152 ndev = ibdev->roce.netdev; 153 if (ndev) 154 if_ref(ndev); 155 read_unlock(&ibdev->roce.netdev_lock); 156 157 return ndev; 158 } 159 160 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 161 u8 *active_width) 162 { 163 switch (eth_proto_oper) { 164 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 165 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 166 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 167 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 168 *active_width = IB_WIDTH_1X; 169 *active_speed = IB_SPEED_SDR; 170 break; 171 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 172 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 173 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 174 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 175 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 176 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 177 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER_LR): 178 *active_width = IB_WIDTH_1X; 179 *active_speed = IB_SPEED_QDR; 180 break; 181 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 182 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 183 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 184 *active_width = IB_WIDTH_1X; 185 *active_speed = IB_SPEED_EDR; 186 break; 187 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 188 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 189 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 190 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4_ER4): 191 *active_width = IB_WIDTH_4X; 192 *active_speed = IB_SPEED_QDR; 193 break; 194 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 195 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 196 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR4): 197 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 198 *active_width = IB_WIDTH_1X; 199 *active_speed = IB_SPEED_HDR; 200 break; 201 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 202 *active_width = IB_WIDTH_4X; 203 *active_speed = IB_SPEED_FDR; 204 break; 205 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 206 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 207 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 208 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 209 *active_width = IB_WIDTH_4X; 210 *active_speed = IB_SPEED_EDR; 211 break; 212 default: 213 *active_width = IB_WIDTH_4X; 214 *active_speed = IB_SPEED_QDR; 215 return -EINVAL; 216 } 217 218 return 0; 219 } 220 221 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed, 222 u8 *active_width) 223 { 224 switch (eth_proto_oper) { 225 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 226 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 227 *active_width = IB_WIDTH_1X; 228 *active_speed = IB_SPEED_SDR; 229 break; 230 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 231 *active_width = IB_WIDTH_1X; 232 *active_speed = IB_SPEED_DDR; 233 break; 234 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 235 *active_width = IB_WIDTH_1X; 236 *active_speed = IB_SPEED_QDR; 237 break; 238 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 239 *active_width = IB_WIDTH_4X; 240 *active_speed = IB_SPEED_QDR; 241 break; 242 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 243 *active_width = IB_WIDTH_1X; 244 *active_speed = IB_SPEED_EDR; 245 break; 246 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 247 *active_width = IB_WIDTH_2X; 248 *active_speed = IB_SPEED_EDR; 249 break; 250 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 251 *active_width = IB_WIDTH_1X; 252 *active_speed = IB_SPEED_HDR; 253 break; 254 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 255 *active_width = IB_WIDTH_4X; 256 *active_speed = IB_SPEED_EDR; 257 break; 258 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 259 *active_width = IB_WIDTH_2X; 260 *active_speed = IB_SPEED_HDR; 261 break; 262 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 263 *active_width = IB_WIDTH_4X; 264 *active_speed = IB_SPEED_HDR; 265 break; 266 default: 267 *active_width = IB_WIDTH_4X; 268 *active_speed = IB_SPEED_QDR; 269 return -EINVAL; 270 } 271 272 return 0; 273 } 274 275 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 276 struct ib_port_attr *props) 277 { 278 struct mlx5_ib_dev *dev = to_mdev(device); 279 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {}; 280 struct ifnet *ndev; 281 enum ib_mtu ndev_ib_mtu; 282 u16 qkey_viol_cntr; 283 u32 eth_prot_oper; 284 bool ext; 285 int err; 286 287 memset(props, 0, sizeof(*props)); 288 289 /* Possible bad flows are checked before filling out props so in case 290 * of an error it will still be zeroed out. 291 */ 292 err = mlx5_query_port_ptys(dev->mdev, out, sizeof(out), MLX5_PTYS_EN, 293 port_num); 294 if (err) 295 return err; 296 297 ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet); 298 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 299 300 if (ext) 301 translate_eth_ext_proto_oper(eth_prot_oper, &props->active_speed, 302 &props->active_width); 303 else 304 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 305 &props->active_width); 306 307 props->port_cap_flags |= IB_PORT_CM_SUP; 308 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 309 310 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 311 roce_address_table_size); 312 props->max_mtu = IB_MTU_4096; 313 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 314 props->pkey_tbl_len = 1; 315 props->state = IB_PORT_DOWN; 316 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 317 318 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr); 319 props->qkey_viol_cntr = qkey_viol_cntr; 320 321 ndev = mlx5_ib_get_netdev(device, port_num); 322 if (!ndev) 323 return 0; 324 325 if (ndev->if_drv_flags & IFF_DRV_RUNNING && 326 ndev->if_link_state == LINK_STATE_UP) { 327 props->state = IB_PORT_ACTIVE; 328 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 329 } 330 331 ndev_ib_mtu = iboe_get_mtu(ndev->if_mtu); 332 333 if_rele(ndev); 334 335 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 336 return 0; 337 } 338 339 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid, 340 const struct ib_gid_attr *attr, 341 void *mlx5_addr) 342 { 343 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v) 344 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 345 source_l3_address); 346 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 347 source_mac_47_32); 348 u16 vlan_id; 349 350 if (!gid) 351 return; 352 ether_addr_copy(mlx5_addr_mac, IF_LLADDR(attr->ndev)); 353 354 vlan_id = rdma_vlan_dev_vlan_id(attr->ndev); 355 if (vlan_id != 0xffff) { 356 MLX5_SET_RA(mlx5_addr, vlan_valid, 1); 357 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_id); 358 } 359 360 switch (attr->gid_type) { 361 case IB_GID_TYPE_IB: 362 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1); 363 break; 364 case IB_GID_TYPE_ROCE_UDP_ENCAP: 365 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2); 366 break; 367 368 default: 369 WARN_ON(true); 370 } 371 372 if (attr->gid_type != IB_GID_TYPE_IB) { 373 if (ipv6_addr_v4mapped((void *)gid)) 374 MLX5_SET_RA(mlx5_addr, roce_l3_type, 375 MLX5_ROCE_L3_TYPE_IPV4); 376 else 377 MLX5_SET_RA(mlx5_addr, roce_l3_type, 378 MLX5_ROCE_L3_TYPE_IPV6); 379 } 380 381 if ((attr->gid_type == IB_GID_TYPE_IB) || 382 !ipv6_addr_v4mapped((void *)gid)) 383 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid)); 384 else 385 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4); 386 } 387 388 static int set_roce_addr(struct ib_device *device, u8 port_num, 389 unsigned int index, 390 const union ib_gid *gid, 391 const struct ib_gid_attr *attr) 392 { 393 struct mlx5_ib_dev *dev = to_mdev(device); 394 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0}; 395 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0}; 396 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address); 397 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num); 398 399 if (ll != IB_LINK_LAYER_ETHERNET) 400 return -EINVAL; 401 402 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr); 403 404 MLX5_SET(set_roce_address_in, in, roce_address_index, index); 405 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS); 406 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out)); 407 } 408 409 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, 410 unsigned int index, const union ib_gid *gid, 411 const struct ib_gid_attr *attr, 412 __always_unused void **context) 413 { 414 return set_roce_addr(device, port_num, index, gid, attr); 415 } 416 417 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, 418 unsigned int index, __always_unused void **context) 419 { 420 return set_roce_addr(device, port_num, index, NULL, NULL); 421 } 422 423 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 424 int index) 425 { 426 struct ib_gid_attr attr; 427 union ib_gid gid; 428 429 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) 430 return 0; 431 432 if (!attr.ndev) 433 return 0; 434 435 if_rele(attr.ndev); 436 437 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 438 return 0; 439 440 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 441 } 442 443 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, 444 int index, enum ib_gid_type *gid_type) 445 { 446 struct ib_gid_attr attr; 447 union ib_gid gid; 448 int ret; 449 450 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr); 451 if (ret) 452 return ret; 453 454 if (!attr.ndev) 455 return -ENODEV; 456 457 if_rele(attr.ndev); 458 459 *gid_type = attr.gid_type; 460 461 return 0; 462 } 463 464 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 465 { 466 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 467 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 468 return 0; 469 } 470 471 enum { 472 MLX5_VPORT_ACCESS_METHOD_MAD, 473 MLX5_VPORT_ACCESS_METHOD_HCA, 474 MLX5_VPORT_ACCESS_METHOD_NIC, 475 }; 476 477 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 478 { 479 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 480 return MLX5_VPORT_ACCESS_METHOD_MAD; 481 482 if (mlx5_ib_port_link_layer(ibdev, 1) == 483 IB_LINK_LAYER_ETHERNET) 484 return MLX5_VPORT_ACCESS_METHOD_NIC; 485 486 return MLX5_VPORT_ACCESS_METHOD_HCA; 487 } 488 489 static void get_atomic_caps(struct mlx5_ib_dev *dev, 490 struct ib_device_attr *props) 491 { 492 u8 tmp; 493 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 494 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 495 u8 atomic_req_8B_endianness_mode = 496 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode); 497 498 /* Check if HW supports 8 bytes standard atomic operations and capable 499 * of host endianness respond 500 */ 501 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 502 if (((atomic_operations & tmp) == tmp) && 503 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 504 (atomic_req_8B_endianness_mode)) { 505 props->atomic_cap = IB_ATOMIC_HCA; 506 } else { 507 props->atomic_cap = IB_ATOMIC_NONE; 508 } 509 } 510 511 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 512 __be64 *sys_image_guid) 513 { 514 struct mlx5_ib_dev *dev = to_mdev(ibdev); 515 struct mlx5_core_dev *mdev = dev->mdev; 516 u64 tmp; 517 int err; 518 519 switch (mlx5_get_vport_access_method(ibdev)) { 520 case MLX5_VPORT_ACCESS_METHOD_MAD: 521 return mlx5_query_mad_ifc_system_image_guid(ibdev, 522 sys_image_guid); 523 524 case MLX5_VPORT_ACCESS_METHOD_HCA: 525 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 526 break; 527 528 case MLX5_VPORT_ACCESS_METHOD_NIC: 529 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 530 break; 531 532 default: 533 return -EINVAL; 534 } 535 536 if (!err) 537 *sys_image_guid = cpu_to_be64(tmp); 538 539 return err; 540 541 } 542 543 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 544 u16 *max_pkeys) 545 { 546 struct mlx5_ib_dev *dev = to_mdev(ibdev); 547 struct mlx5_core_dev *mdev = dev->mdev; 548 549 switch (mlx5_get_vport_access_method(ibdev)) { 550 case MLX5_VPORT_ACCESS_METHOD_MAD: 551 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 552 553 case MLX5_VPORT_ACCESS_METHOD_HCA: 554 case MLX5_VPORT_ACCESS_METHOD_NIC: 555 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 556 pkey_table_size)); 557 return 0; 558 559 default: 560 return -EINVAL; 561 } 562 } 563 564 static int mlx5_query_vendor_id(struct ib_device *ibdev, 565 u32 *vendor_id) 566 { 567 struct mlx5_ib_dev *dev = to_mdev(ibdev); 568 569 switch (mlx5_get_vport_access_method(ibdev)) { 570 case MLX5_VPORT_ACCESS_METHOD_MAD: 571 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 572 573 case MLX5_VPORT_ACCESS_METHOD_HCA: 574 case MLX5_VPORT_ACCESS_METHOD_NIC: 575 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 576 577 default: 578 return -EINVAL; 579 } 580 } 581 582 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 583 __be64 *node_guid) 584 { 585 u64 tmp; 586 int err; 587 588 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 589 case MLX5_VPORT_ACCESS_METHOD_MAD: 590 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 591 592 case MLX5_VPORT_ACCESS_METHOD_HCA: 593 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 594 break; 595 596 case MLX5_VPORT_ACCESS_METHOD_NIC: 597 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 598 break; 599 600 default: 601 return -EINVAL; 602 } 603 604 if (!err) 605 *node_guid = cpu_to_be64(tmp); 606 607 return err; 608 } 609 610 struct mlx5_reg_node_desc { 611 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 612 }; 613 614 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 615 { 616 struct mlx5_reg_node_desc in; 617 618 if (mlx5_use_mad_ifc(dev)) 619 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 620 621 memset(&in, 0, sizeof(in)); 622 623 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 624 sizeof(struct mlx5_reg_node_desc), 625 MLX5_REG_NODE_DESC, 0, 0); 626 } 627 628 static int mlx5_ib_query_device(struct ib_device *ibdev, 629 struct ib_device_attr *props, 630 struct ib_udata *uhw) 631 { 632 struct mlx5_ib_dev *dev = to_mdev(ibdev); 633 struct mlx5_core_dev *mdev = dev->mdev; 634 int err = -ENOMEM; 635 int max_sq_desc; 636 int max_rq_sg; 637 int max_sq_sg; 638 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 639 struct mlx5_ib_query_device_resp resp = {}; 640 size_t resp_len; 641 u64 max_tso; 642 643 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 644 if (uhw->outlen && uhw->outlen < resp_len) 645 return -EINVAL; 646 else 647 resp.response_length = resp_len; 648 649 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 650 return -EINVAL; 651 652 memset(props, 0, sizeof(*props)); 653 err = mlx5_query_system_image_guid(ibdev, 654 &props->sys_image_guid); 655 if (err) 656 return err; 657 658 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 659 if (err) 660 return err; 661 662 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 663 if (err) 664 return err; 665 666 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 667 ((u32)fw_rev_min(dev->mdev) << 16) | 668 fw_rev_sub(dev->mdev); 669 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 670 IB_DEVICE_PORT_ACTIVE_EVENT | 671 IB_DEVICE_SYS_IMAGE_GUID | 672 IB_DEVICE_RC_RNR_NAK_GEN; 673 674 if (MLX5_CAP_GEN(mdev, pkv)) 675 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 676 if (MLX5_CAP_GEN(mdev, qkv)) 677 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 678 if (MLX5_CAP_GEN(mdev, apm)) 679 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 680 if (MLX5_CAP_GEN(mdev, xrc)) 681 props->device_cap_flags |= IB_DEVICE_XRC; 682 if (MLX5_CAP_GEN(mdev, imaicl)) { 683 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 684 IB_DEVICE_MEM_WINDOW_TYPE_2B; 685 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 686 /* We support 'Gappy' memory registration too */ 687 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 688 } 689 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 690 if (MLX5_CAP_GEN(mdev, sho)) { 691 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 692 /* At this stage no support for signature handover */ 693 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 694 IB_PROT_T10DIF_TYPE_2 | 695 IB_PROT_T10DIF_TYPE_3; 696 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 697 IB_GUARD_T10DIF_CSUM; 698 } 699 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 700 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 701 702 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) { 703 if (MLX5_CAP_ETH(mdev, csum_cap)) 704 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 705 706 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 707 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 708 if (max_tso) { 709 resp.tso_caps.max_tso = 1 << max_tso; 710 resp.tso_caps.supported_qpts |= 711 1 << IB_QPT_RAW_PACKET; 712 resp.response_length += sizeof(resp.tso_caps); 713 } 714 } 715 716 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 717 resp.rss_caps.rx_hash_function = 718 MLX5_RX_HASH_FUNC_TOEPLITZ; 719 resp.rss_caps.rx_hash_fields_mask = 720 MLX5_RX_HASH_SRC_IPV4 | 721 MLX5_RX_HASH_DST_IPV4 | 722 MLX5_RX_HASH_SRC_IPV6 | 723 MLX5_RX_HASH_DST_IPV6 | 724 MLX5_RX_HASH_SRC_PORT_TCP | 725 MLX5_RX_HASH_DST_PORT_TCP | 726 MLX5_RX_HASH_SRC_PORT_UDP | 727 MLX5_RX_HASH_DST_PORT_UDP; 728 resp.response_length += sizeof(resp.rss_caps); 729 } 730 } else { 731 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 732 resp.response_length += sizeof(resp.tso_caps); 733 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 734 resp.response_length += sizeof(resp.rss_caps); 735 } 736 737 if (MLX5_CAP_GEN(mdev, ipoib_ipoib_offloads)) { 738 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 739 props->device_cap_flags |= IB_DEVICE_UD_TSO; 740 } 741 742 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 743 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) 744 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 745 746 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 747 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 748 749 props->vendor_part_id = mdev->pdev->device; 750 props->hw_ver = mdev->pdev->revision; 751 752 props->max_mr_size = ~0ull; 753 props->page_size_cap = ~(min_page_size - 1); 754 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 755 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 756 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 757 sizeof(struct mlx5_wqe_data_seg); 758 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 759 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 760 sizeof(struct mlx5_wqe_raddr_seg)) / 761 sizeof(struct mlx5_wqe_data_seg); 762 props->max_sge = min(max_rq_sg, max_sq_sg); 763 props->max_sge_rd = MLX5_MAX_SGE_RD; 764 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 765 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 766 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 767 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 768 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 769 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 770 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 771 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 772 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 773 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 774 props->max_srq_sge = max_rq_sg - 1; 775 props->max_fast_reg_page_list_len = 776 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 777 get_atomic_caps(dev, props); 778 props->masked_atomic_cap = IB_ATOMIC_NONE; 779 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 780 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 781 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 782 props->max_mcast_grp; 783 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 784 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 785 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 786 787 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 788 if (MLX5_CAP_GEN(mdev, pg)) 789 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 790 props->odp_caps = dev->odp_caps; 791 #endif 792 793 if (MLX5_CAP_GEN(mdev, cd)) 794 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 795 796 if (!mlx5_core_is_pf(mdev)) 797 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 798 799 if (mlx5_ib_port_link_layer(ibdev, 1) == 800 IB_LINK_LAYER_ETHERNET) { 801 props->rss_caps.max_rwq_indirection_tables = 802 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 803 props->rss_caps.max_rwq_indirection_table_size = 804 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 805 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 806 props->max_wq_type_rq = 807 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 808 } 809 810 if (uhw->outlen) { 811 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 812 813 if (err) 814 return err; 815 } 816 817 return 0; 818 } 819 820 enum mlx5_ib_width { 821 MLX5_IB_WIDTH_1X = 1 << 0, 822 MLX5_IB_WIDTH_2X = 1 << 1, 823 MLX5_IB_WIDTH_4X = 1 << 2, 824 MLX5_IB_WIDTH_8X = 1 << 3, 825 MLX5_IB_WIDTH_12X = 1 << 4 826 }; 827 828 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 829 u8 *ib_width) 830 { 831 struct mlx5_ib_dev *dev = to_mdev(ibdev); 832 int err = 0; 833 834 if (active_width & MLX5_IB_WIDTH_1X) { 835 *ib_width = IB_WIDTH_1X; 836 } else if (active_width & MLX5_IB_WIDTH_2X) { 837 *ib_width = IB_WIDTH_2X; 838 } else if (active_width & MLX5_IB_WIDTH_4X) { 839 *ib_width = IB_WIDTH_4X; 840 } else if (active_width & MLX5_IB_WIDTH_8X) { 841 *ib_width = IB_WIDTH_8X; 842 } else if (active_width & MLX5_IB_WIDTH_12X) { 843 *ib_width = IB_WIDTH_12X; 844 } else { 845 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 846 (int)active_width); 847 err = -EINVAL; 848 } 849 850 return err; 851 } 852 853 enum ib_max_vl_num { 854 __IB_MAX_VL_0 = 1, 855 __IB_MAX_VL_0_1 = 2, 856 __IB_MAX_VL_0_3 = 3, 857 __IB_MAX_VL_0_7 = 4, 858 __IB_MAX_VL_0_14 = 5, 859 }; 860 861 enum mlx5_vl_hw_cap { 862 MLX5_VL_HW_0 = 1, 863 MLX5_VL_HW_0_1 = 2, 864 MLX5_VL_HW_0_2 = 3, 865 MLX5_VL_HW_0_3 = 4, 866 MLX5_VL_HW_0_4 = 5, 867 MLX5_VL_HW_0_5 = 6, 868 MLX5_VL_HW_0_6 = 7, 869 MLX5_VL_HW_0_7 = 8, 870 MLX5_VL_HW_0_14 = 15 871 }; 872 873 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 874 u8 *max_vl_num) 875 { 876 switch (vl_hw_cap) { 877 case MLX5_VL_HW_0: 878 *max_vl_num = __IB_MAX_VL_0; 879 break; 880 case MLX5_VL_HW_0_1: 881 *max_vl_num = __IB_MAX_VL_0_1; 882 break; 883 case MLX5_VL_HW_0_3: 884 *max_vl_num = __IB_MAX_VL_0_3; 885 break; 886 case MLX5_VL_HW_0_7: 887 *max_vl_num = __IB_MAX_VL_0_7; 888 break; 889 case MLX5_VL_HW_0_14: 890 *max_vl_num = __IB_MAX_VL_0_14; 891 break; 892 893 default: 894 return -EINVAL; 895 } 896 897 return 0; 898 } 899 900 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 901 struct ib_port_attr *props) 902 { 903 struct mlx5_ib_dev *dev = to_mdev(ibdev); 904 struct mlx5_core_dev *mdev = dev->mdev; 905 u32 *rep; 906 int replen = MLX5_ST_SZ_BYTES(query_hca_vport_context_out); 907 struct mlx5_ptys_reg *ptys; 908 struct mlx5_pmtu_reg *pmtu; 909 struct mlx5_pvlc_reg pvlc; 910 void *ctx; 911 int err; 912 913 rep = mlx5_vzalloc(replen); 914 ptys = kzalloc(sizeof(*ptys), GFP_KERNEL); 915 pmtu = kzalloc(sizeof(*pmtu), GFP_KERNEL); 916 if (!rep || !ptys || !pmtu) { 917 err = -ENOMEM; 918 goto out; 919 } 920 921 memset(props, 0, sizeof(*props)); 922 923 err = mlx5_query_hca_vport_context(mdev, port, 0, rep, replen); 924 if (err) 925 goto out; 926 927 ctx = MLX5_ADDR_OF(query_hca_vport_context_out, rep, hca_vport_context); 928 929 props->lid = MLX5_GET(hca_vport_context, ctx, lid); 930 props->lmc = MLX5_GET(hca_vport_context, ctx, lmc); 931 props->sm_lid = MLX5_GET(hca_vport_context, ctx, sm_lid); 932 props->sm_sl = MLX5_GET(hca_vport_context, ctx, sm_sl); 933 props->state = MLX5_GET(hca_vport_context, ctx, vport_state); 934 props->phys_state = MLX5_GET(hca_vport_context, ctx, 935 port_physical_state); 936 props->port_cap_flags = MLX5_GET(hca_vport_context, ctx, cap_mask1); 937 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 938 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 939 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 940 props->bad_pkey_cntr = MLX5_GET(hca_vport_context, ctx, 941 pkey_violation_counter); 942 props->qkey_viol_cntr = MLX5_GET(hca_vport_context, ctx, 943 qkey_violation_counter); 944 props->subnet_timeout = MLX5_GET(hca_vport_context, ctx, 945 subnet_timeout); 946 props->init_type_reply = MLX5_GET(hca_vport_context, ctx, 947 init_type_reply); 948 props->grh_required = MLX5_GET(hca_vport_context, ctx, grh_required); 949 950 ptys->proto_mask |= MLX5_PTYS_IB; 951 ptys->local_port = port; 952 err = mlx5_core_access_ptys(mdev, ptys, 0); 953 if (err) 954 goto out; 955 956 err = translate_active_width(ibdev, ptys->ib_link_width_oper, 957 &props->active_width); 958 if (err) 959 goto out; 960 961 props->active_speed = (u8)ptys->ib_proto_oper; 962 963 pmtu->local_port = port; 964 err = mlx5_core_access_pmtu(mdev, pmtu, 0); 965 if (err) 966 goto out; 967 968 props->max_mtu = pmtu->max_mtu; 969 props->active_mtu = pmtu->oper_mtu; 970 971 memset(&pvlc, 0, sizeof(pvlc)); 972 pvlc.local_port = port; 973 err = mlx5_core_access_pvlc(mdev, &pvlc, 0); 974 if (err) 975 goto out; 976 977 err = translate_max_vl_num(ibdev, pvlc.vl_hw_cap, 978 &props->max_vl_num); 979 out: 980 kvfree(rep); 981 kfree(ptys); 982 kfree(pmtu); 983 return err; 984 } 985 986 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 987 struct ib_port_attr *props) 988 { 989 switch (mlx5_get_vport_access_method(ibdev)) { 990 case MLX5_VPORT_ACCESS_METHOD_MAD: 991 return mlx5_query_mad_ifc_port(ibdev, port, props); 992 993 case MLX5_VPORT_ACCESS_METHOD_HCA: 994 return mlx5_query_hca_port(ibdev, port, props); 995 996 case MLX5_VPORT_ACCESS_METHOD_NIC: 997 return mlx5_query_port_roce(ibdev, port, props); 998 999 default: 1000 return -EINVAL; 1001 } 1002 } 1003 1004 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1005 union ib_gid *gid) 1006 { 1007 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1008 struct mlx5_core_dev *mdev = dev->mdev; 1009 1010 switch (mlx5_get_vport_access_method(ibdev)) { 1011 case MLX5_VPORT_ACCESS_METHOD_MAD: 1012 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1013 1014 case MLX5_VPORT_ACCESS_METHOD_HCA: 1015 return mlx5_query_hca_vport_gid(mdev, port, 0, index, gid); 1016 1017 default: 1018 return -EINVAL; 1019 } 1020 1021 } 1022 1023 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1024 u16 *pkey) 1025 { 1026 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1027 struct mlx5_core_dev *mdev = dev->mdev; 1028 1029 switch (mlx5_get_vport_access_method(ibdev)) { 1030 case MLX5_VPORT_ACCESS_METHOD_MAD: 1031 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1032 1033 case MLX5_VPORT_ACCESS_METHOD_HCA: 1034 case MLX5_VPORT_ACCESS_METHOD_NIC: 1035 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index, 1036 pkey); 1037 default: 1038 return -EINVAL; 1039 } 1040 } 1041 1042 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1043 struct ib_device_modify *props) 1044 { 1045 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1046 struct mlx5_reg_node_desc in; 1047 struct mlx5_reg_node_desc out; 1048 int err; 1049 1050 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1051 return -EOPNOTSUPP; 1052 1053 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1054 return 0; 1055 1056 /* 1057 * If possible, pass node desc to FW, so it can generate 1058 * a 144 trap. If cmd fails, just ignore. 1059 */ 1060 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1061 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1062 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1063 if (err) 1064 return err; 1065 1066 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1067 1068 return err; 1069 } 1070 1071 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1072 struct ib_port_modify *props) 1073 { 1074 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1075 struct ib_port_attr attr; 1076 u32 tmp; 1077 int err; 1078 1079 /* 1080 * CM layer calls ib_modify_port() regardless of the link 1081 * layer. For Ethernet ports, qkey violation and Port 1082 * capabilities are meaningless. 1083 */ 1084 if (mlx5_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_ETHERNET) 1085 return 0; 1086 1087 mutex_lock(&dev->cap_mask_mutex); 1088 1089 err = mlx5_ib_query_port(ibdev, port, &attr); 1090 if (err) 1091 goto out; 1092 1093 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1094 ~props->clr_port_cap_mask; 1095 1096 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1097 1098 out: 1099 mutex_unlock(&dev->cap_mask_mutex); 1100 return err; 1101 } 1102 1103 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1104 { 1105 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1106 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1107 } 1108 1109 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1110 { 1111 /* Large page with non 4k uar support might limit the dynamic size */ 1112 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1113 return MLX5_MIN_DYN_BFREGS; 1114 1115 return MLX5_MAX_DYN_BFREGS; 1116 } 1117 1118 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1119 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1120 struct mlx5_bfreg_info *bfregi) 1121 { 1122 int uars_per_sys_page; 1123 int bfregs_per_sys_page; 1124 int ref_bfregs = req->total_num_bfregs; 1125 1126 if (req->total_num_bfregs == 0) 1127 return -EINVAL; 1128 1129 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1130 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1131 1132 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1133 return -ENOMEM; 1134 1135 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1136 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1137 /* This holds the required static allocation asked by the user */ 1138 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1139 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1140 return -EINVAL; 1141 1142 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1143 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1144 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1145 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1146 1147 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1148 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1149 lib_uar_4k ? "yes" : "no", ref_bfregs, 1150 req->total_num_bfregs, bfregi->total_num_bfregs, 1151 bfregi->num_sys_pages); 1152 1153 return 0; 1154 } 1155 1156 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1157 { 1158 struct mlx5_bfreg_info *bfregi; 1159 int err; 1160 int i; 1161 1162 bfregi = &context->bfregi; 1163 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1164 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]); 1165 if (err) 1166 goto error; 1167 1168 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1169 } 1170 1171 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1172 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1173 1174 return 0; 1175 1176 error: 1177 for (--i; i >= 0; i--) 1178 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i])) 1179 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1180 1181 return err; 1182 } 1183 1184 static void deallocate_uars(struct mlx5_ib_dev *dev, 1185 struct mlx5_ib_ucontext *context) 1186 { 1187 struct mlx5_bfreg_info *bfregi; 1188 int i; 1189 1190 bfregi = &context->bfregi; 1191 for (i = 0; i < bfregi->num_sys_pages; i++) 1192 if (i < bfregi->num_static_sys_pages || 1193 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1194 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]); 1195 } 1196 1197 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1198 u16 uid) 1199 { 1200 int err; 1201 1202 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1203 return 0; 1204 1205 err = mlx5_alloc_transport_domain(dev->mdev, tdn, uid); 1206 if (err) 1207 return err; 1208 1209 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1210 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1211 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1212 return 0; 1213 1214 mutex_lock(&dev->lb_mutex); 1215 dev->user_td++; 1216 1217 if (dev->user_td == 2) 1218 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1219 1220 mutex_unlock(&dev->lb_mutex); 1221 1222 if (err != 0) 1223 mlx5_dealloc_transport_domain(dev->mdev, *tdn, uid); 1224 return err; 1225 } 1226 1227 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1228 u16 uid) 1229 { 1230 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1231 return; 1232 1233 mlx5_dealloc_transport_domain(dev->mdev, tdn, uid); 1234 1235 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1236 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1237 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1238 return; 1239 1240 mutex_lock(&dev->lb_mutex); 1241 dev->user_td--; 1242 1243 if (dev->user_td < 2) 1244 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1245 1246 mutex_unlock(&dev->lb_mutex); 1247 } 1248 1249 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 1250 struct ib_udata *udata) 1251 { 1252 struct ib_device *ibdev = uctx->device; 1253 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1254 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1255 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1256 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1257 struct mlx5_bfreg_info *bfregi; 1258 int ver; 1259 int err; 1260 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1261 max_cqe_version); 1262 bool lib_uar_4k; 1263 bool lib_uar_dyn; 1264 1265 if (!dev->ib_active) 1266 return -EAGAIN; 1267 1268 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1269 ver = 0; 1270 else if (udata->inlen >= min_req_v2) 1271 ver = 2; 1272 else 1273 return -EINVAL; 1274 1275 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1276 if (err) 1277 return err; 1278 1279 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1280 return -EOPNOTSUPP; 1281 1282 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1283 return -EOPNOTSUPP; 1284 1285 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1286 MLX5_NON_FP_BFREGS_PER_UAR); 1287 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1288 return -EINVAL; 1289 1290 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1291 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1292 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1293 resp.cache_line_size = cache_line_size(); 1294 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1295 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1296 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1297 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1298 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1299 resp.cqe_version = min_t(__u8, 1300 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1301 req.max_cqe_version); 1302 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1303 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1304 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1305 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1; 1306 resp.response_length = min(offsetof(typeof(resp), response_length) + 1307 sizeof(resp.response_length), udata->outlen); 1308 1309 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1310 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 1311 bfregi = &context->bfregi; 1312 1313 if (lib_uar_dyn) { 1314 bfregi->lib_uar_dyn = lib_uar_dyn; 1315 goto uar_done; 1316 } 1317 1318 /* updates req->total_num_bfregs */ 1319 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1320 if (err) 1321 goto out_ctx; 1322 1323 mutex_init(&bfregi->lock); 1324 bfregi->lib_uar_4k = lib_uar_4k; 1325 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1326 GFP_KERNEL); 1327 if (!bfregi->count) { 1328 err = -ENOMEM; 1329 goto out_ctx; 1330 } 1331 1332 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1333 sizeof(*bfregi->sys_pages), 1334 GFP_KERNEL); 1335 if (!bfregi->sys_pages) { 1336 err = -ENOMEM; 1337 goto out_count; 1338 } 1339 1340 err = allocate_uars(dev, context); 1341 if (err) 1342 goto out_sys_pages; 1343 1344 uar_done: 1345 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1346 err = mlx5_ib_devx_create(dev, true); 1347 if (err < 0) 1348 goto out_uars; 1349 context->devx_uid = err; 1350 } 1351 1352 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 1353 context->devx_uid); 1354 if (err) 1355 goto out_devx; 1356 1357 INIT_LIST_HEAD(&context->db_page_list); 1358 mutex_init(&context->db_page_mutex); 1359 1360 resp.tot_bfregs = lib_uar_dyn ? 0 : req.total_num_bfregs; 1361 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports); 1362 1363 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1364 resp.response_length += sizeof(resp.cqe_version); 1365 1366 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1367 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1368 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1369 resp.response_length += sizeof(resp.cmds_supp_uhw); 1370 } 1371 1372 /* 1373 * We don't want to expose information from the PCI bar that is located 1374 * after 4096 bytes, so if the arch only supports larger pages, let's 1375 * pretend we don't support reading the HCA's core clock. This is also 1376 * forced by mmap function. 1377 */ 1378 if (offsetofend(typeof(resp), hca_core_clock_offset) <= udata->outlen) { 1379 if (PAGE_SIZE <= 4096) { 1380 resp.comp_mask |= 1381 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1382 resp.hca_core_clock_offset = 1383 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE; 1384 } 1385 resp.response_length += sizeof(resp.hca_core_clock_offset); 1386 } 1387 1388 if (offsetofend(typeof(resp), log_uar_size) <= udata->outlen) 1389 resp.response_length += sizeof(resp.log_uar_size); 1390 1391 if (offsetofend(typeof(resp), num_uars_per_page) <= udata->outlen) 1392 resp.response_length += sizeof(resp.num_uars_per_page); 1393 1394 if (offsetofend(typeof(resp), num_dyn_bfregs) <= udata->outlen) { 1395 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs; 1396 resp.response_length += sizeof(resp.num_dyn_bfregs); 1397 } 1398 1399 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1400 if (err) 1401 goto out_mdev; 1402 1403 bfregi->ver = ver; 1404 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1405 context->cqe_version = resp.cqe_version; 1406 context->lib_caps = req.lib_caps; 1407 print_lib_caps(dev, context->lib_caps); 1408 1409 return 0; 1410 1411 out_mdev: 1412 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1413 out_devx: 1414 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 1415 mlx5_ib_devx_destroy(dev, context->devx_uid); 1416 1417 out_uars: 1418 deallocate_uars(dev, context); 1419 1420 out_sys_pages: 1421 kfree(bfregi->sys_pages); 1422 1423 out_count: 1424 kfree(bfregi->count); 1425 1426 out_ctx: 1427 return err; 1428 } 1429 1430 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1431 { 1432 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1433 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1434 struct mlx5_bfreg_info *bfregi; 1435 1436 bfregi = &context->bfregi; 1437 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1438 1439 if (context->devx_uid) 1440 mlx5_ib_devx_destroy(dev, context->devx_uid); 1441 1442 deallocate_uars(dev, context); 1443 kfree(bfregi->sys_pages); 1444 kfree(bfregi->count); 1445 } 1446 1447 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 1448 int uar_idx) 1449 { 1450 int fw_uars_per_page; 1451 1452 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 1453 1454 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 1455 } 1456 1457 static int get_command(unsigned long offset) 1458 { 1459 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1460 } 1461 1462 static int get_arg(unsigned long offset) 1463 { 1464 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1465 } 1466 1467 static int get_index(unsigned long offset) 1468 { 1469 return get_arg(offset); 1470 } 1471 1472 /* Index resides in an extra byte to enable larger values than 255 */ 1473 static int get_extended_index(unsigned long offset) 1474 { 1475 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 1476 } 1477 1478 1479 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1480 { 1481 } 1482 1483 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1484 { 1485 switch (cmd) { 1486 case MLX5_IB_MMAP_WC_PAGE: 1487 return "WC"; 1488 case MLX5_IB_MMAP_REGULAR_PAGE: 1489 return "best effort WC"; 1490 case MLX5_IB_MMAP_NC_PAGE: 1491 return "NC"; 1492 default: 1493 return NULL; 1494 } 1495 } 1496 1497 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 1498 struct vm_area_struct *vma, 1499 struct mlx5_ib_ucontext *context) 1500 { 1501 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 1502 !(vma->vm_flags & VM_SHARED)) 1503 return -EINVAL; 1504 1505 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 1506 return -EOPNOTSUPP; 1507 1508 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 1509 return -EPERM; 1510 1511 return -EOPNOTSUPP; 1512 } 1513 1514 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 1515 { 1516 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 1517 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 1518 1519 switch (mentry->mmap_flag) { 1520 case MLX5_IB_MMAP_TYPE_UAR_WC: 1521 case MLX5_IB_MMAP_TYPE_UAR_NC: 1522 mlx5_cmd_free_uar(dev->mdev, mentry->page_idx); 1523 kfree(mentry); 1524 break; 1525 default: 1526 WARN_ON(true); 1527 } 1528 } 1529 1530 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 1531 struct vm_area_struct *vma, 1532 struct mlx5_ib_ucontext *context) 1533 { 1534 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1535 int err; 1536 unsigned long idx; 1537 phys_addr_t pfn; 1538 pgprot_t prot; 1539 u32 bfreg_dyn_idx = 0; 1540 u32 uar_index; 1541 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 1542 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 1543 bfregi->num_static_sys_pages; 1544 1545 if (bfregi->lib_uar_dyn) 1546 return -EINVAL; 1547 1548 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1549 return -EINVAL; 1550 1551 if (dyn_uar) 1552 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 1553 else 1554 idx = get_index(vma->vm_pgoff); 1555 1556 if (idx >= max_valid_idx) { 1557 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 1558 idx, max_valid_idx); 1559 return -EINVAL; 1560 } 1561 1562 switch (cmd) { 1563 case MLX5_IB_MMAP_WC_PAGE: 1564 case MLX5_IB_MMAP_ALLOC_WC: 1565 case MLX5_IB_MMAP_REGULAR_PAGE: 1566 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 1567 prot = pgprot_writecombine(vma->vm_page_prot); 1568 break; 1569 case MLX5_IB_MMAP_NC_PAGE: 1570 prot = pgprot_noncached(vma->vm_page_prot); 1571 break; 1572 default: 1573 return -EINVAL; 1574 } 1575 1576 if (dyn_uar) { 1577 int uars_per_page; 1578 1579 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 1580 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 1581 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 1582 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 1583 bfreg_dyn_idx, bfregi->total_num_bfregs); 1584 return -EINVAL; 1585 } 1586 1587 mutex_lock(&bfregi->lock); 1588 /* Fail if uar already allocated, first bfreg index of each 1589 * page holds its count. 1590 */ 1591 if (bfregi->count[bfreg_dyn_idx]) { 1592 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 1593 mutex_unlock(&bfregi->lock); 1594 return -EINVAL; 1595 } 1596 1597 bfregi->count[bfreg_dyn_idx]++; 1598 mutex_unlock(&bfregi->lock); 1599 1600 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index); 1601 if (err) { 1602 mlx5_ib_warn(dev, "UAR alloc failed\n"); 1603 goto free_bfreg; 1604 } 1605 } else { 1606 uar_index = bfregi->sys_pages[idx]; 1607 } 1608 1609 pfn = uar_index2pfn(dev, uar_index); 1610 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 1611 1612 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 1613 prot, NULL); 1614 if (err) { 1615 mlx5_ib_err(dev, 1616 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 1617 err, mmap_cmd2str(cmd)); 1618 goto err; 1619 } 1620 1621 if (dyn_uar) 1622 bfregi->sys_pages[idx] = uar_index; 1623 return 0; 1624 1625 err: 1626 if (!dyn_uar) 1627 return err; 1628 1629 mlx5_cmd_free_uar(dev->mdev, idx); 1630 1631 free_bfreg: 1632 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 1633 1634 return err; 1635 } 1636 1637 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 1638 { 1639 unsigned long idx; 1640 u8 command; 1641 1642 command = get_command(vma->vm_pgoff); 1643 idx = get_extended_index(vma->vm_pgoff); 1644 1645 return (command << 16 | idx); 1646 } 1647 1648 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 1649 struct vm_area_struct *vma, 1650 struct ib_ucontext *ucontext) 1651 { 1652 struct mlx5_user_mmap_entry *mentry; 1653 struct rdma_user_mmap_entry *entry; 1654 unsigned long pgoff; 1655 pgprot_t prot; 1656 phys_addr_t pfn; 1657 int ret; 1658 1659 pgoff = mlx5_vma_to_pgoff(vma); 1660 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 1661 if (!entry) 1662 return -EINVAL; 1663 1664 mentry = to_mmmap(entry); 1665 pfn = (mentry->address >> PAGE_SHIFT); 1666 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 1667 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 1668 prot = pgprot_noncached(vma->vm_page_prot); 1669 else 1670 prot = pgprot_writecombine(vma->vm_page_prot); 1671 ret = rdma_user_mmap_io(ucontext, vma, pfn, 1672 entry->npages * PAGE_SIZE, 1673 prot, 1674 entry); 1675 rdma_user_mmap_entry_put(&mentry->rdma_entry); 1676 return ret; 1677 } 1678 1679 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 1680 { 1681 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1682 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1683 unsigned long command; 1684 phys_addr_t pfn; 1685 1686 command = get_command(vma->vm_pgoff); 1687 switch (command) { 1688 case MLX5_IB_MMAP_WC_PAGE: 1689 case MLX5_IB_MMAP_ALLOC_WC: 1690 if (!dev->wc_support) 1691 return -EPERM; 1692 /* FALLTHROUGH */ 1693 case MLX5_IB_MMAP_NC_PAGE: 1694 case MLX5_IB_MMAP_REGULAR_PAGE: 1695 return uar_mmap(dev, command, vma, context); 1696 1697 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 1698 return -ENOSYS; 1699 1700 case MLX5_IB_MMAP_CORE_CLOCK: 1701 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1702 return -EINVAL; 1703 1704 if (vma->vm_flags & VM_WRITE) 1705 return -EPERM; 1706 1707 /* Don't expose to user-space information it shouldn't have */ 1708 if (PAGE_SIZE > 4096) 1709 return -EOPNOTSUPP; 1710 1711 pfn = (dev->mdev->iseg_base + 1712 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 1713 PAGE_SHIFT; 1714 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 1715 PAGE_SIZE, 1716 pgprot_noncached(vma->vm_page_prot), 1717 NULL); 1718 case MLX5_IB_MMAP_CLOCK_INFO: 1719 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 1720 1721 default: 1722 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 1723 } 1724 1725 return 0; 1726 } 1727 1728 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 1729 { 1730 struct mlx5_ib_pd *pd = to_mpd(ibpd); 1731 struct ib_device *ibdev = ibpd->device; 1732 struct mlx5_ib_alloc_pd_resp resp; 1733 int err; 1734 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 1735 udata, struct mlx5_ib_ucontext, ibucontext); 1736 u16 uid = context ? context->devx_uid : 0; 1737 1738 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn, uid); 1739 if (err) 1740 return (err); 1741 1742 pd->uid = uid; 1743 if (udata) { 1744 resp.pdn = pd->pdn; 1745 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 1746 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 1747 return -EFAULT; 1748 } 1749 } 1750 1751 return 0; 1752 } 1753 1754 static void mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 1755 { 1756 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 1757 struct mlx5_ib_pd *mpd = to_mpd(pd); 1758 1759 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 1760 } 1761 1762 enum { 1763 MATCH_CRITERIA_ENABLE_OUTER_BIT, 1764 MATCH_CRITERIA_ENABLE_MISC_BIT, 1765 MATCH_CRITERIA_ENABLE_INNER_BIT 1766 }; 1767 1768 #define HEADER_IS_ZERO(match_criteria, headers) \ 1769 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 1770 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 1771 1772 static u8 get_match_criteria_enable(u32 *match_criteria) 1773 { 1774 u8 match_criteria_enable; 1775 1776 match_criteria_enable = 1777 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 1778 MATCH_CRITERIA_ENABLE_OUTER_BIT; 1779 match_criteria_enable |= 1780 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 1781 MATCH_CRITERIA_ENABLE_MISC_BIT; 1782 match_criteria_enable |= 1783 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 1784 MATCH_CRITERIA_ENABLE_INNER_BIT; 1785 1786 return match_criteria_enable; 1787 } 1788 1789 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 1790 { 1791 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 1792 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 1793 } 1794 1795 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 1796 { 1797 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 1798 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 1799 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 1800 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 1801 } 1802 1803 #define LAST_ETH_FIELD vlan_tag 1804 #define LAST_IB_FIELD sl 1805 #define LAST_IPV4_FIELD tos 1806 #define LAST_IPV6_FIELD traffic_class 1807 #define LAST_TCP_UDP_FIELD src_port 1808 1809 /* Field is the last supported field */ 1810 #define FIELDS_NOT_SUPPORTED(filter, field)\ 1811 memchr_inv((void *)&filter.field +\ 1812 sizeof(filter.field), 0,\ 1813 sizeof(filter) -\ 1814 offsetof(typeof(filter), field) -\ 1815 sizeof(filter.field)) 1816 1817 static int parse_flow_attr(u32 *match_c, u32 *match_v, 1818 const union ib_flow_spec *ib_spec) 1819 { 1820 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1821 outer_headers); 1822 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1823 outer_headers); 1824 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 1825 misc_parameters); 1826 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 1827 misc_parameters); 1828 1829 switch (ib_spec->type) { 1830 case IB_FLOW_SPEC_ETH: 1831 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1832 return -ENOTSUPP; 1833 1834 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1835 dmac_47_16), 1836 ib_spec->eth.mask.dst_mac); 1837 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1838 dmac_47_16), 1839 ib_spec->eth.val.dst_mac); 1840 1841 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1842 smac_47_16), 1843 ib_spec->eth.mask.src_mac); 1844 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1845 smac_47_16), 1846 ib_spec->eth.val.src_mac); 1847 1848 if (ib_spec->eth.mask.vlan_tag) { 1849 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1850 cvlan_tag, 1); 1851 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1852 cvlan_tag, 1); 1853 1854 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1855 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 1856 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1857 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 1858 1859 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1860 first_cfi, 1861 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 1862 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1863 first_cfi, 1864 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 1865 1866 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1867 first_prio, 1868 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 1869 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1870 first_prio, 1871 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 1872 } 1873 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1874 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 1875 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1876 ethertype, ntohs(ib_spec->eth.val.ether_type)); 1877 break; 1878 case IB_FLOW_SPEC_IPV4: 1879 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 1880 return -ENOTSUPP; 1881 1882 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1883 ethertype, 0xffff); 1884 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1885 ethertype, ETH_P_IP); 1886 1887 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1888 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1889 &ib_spec->ipv4.mask.src_ip, 1890 sizeof(ib_spec->ipv4.mask.src_ip)); 1891 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1892 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1893 &ib_spec->ipv4.val.src_ip, 1894 sizeof(ib_spec->ipv4.val.src_ip)); 1895 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1896 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1897 &ib_spec->ipv4.mask.dst_ip, 1898 sizeof(ib_spec->ipv4.mask.dst_ip)); 1899 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1900 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1901 &ib_spec->ipv4.val.dst_ip, 1902 sizeof(ib_spec->ipv4.val.dst_ip)); 1903 1904 set_tos(outer_headers_c, outer_headers_v, 1905 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 1906 1907 set_proto(outer_headers_c, outer_headers_v, 1908 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 1909 break; 1910 case IB_FLOW_SPEC_IPV6: 1911 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 1912 return -ENOTSUPP; 1913 1914 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1915 ethertype, 0xffff); 1916 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1917 ethertype, IPPROTO_IPV6); 1918 1919 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1920 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1921 &ib_spec->ipv6.mask.src_ip, 1922 sizeof(ib_spec->ipv6.mask.src_ip)); 1923 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1924 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1925 &ib_spec->ipv6.val.src_ip, 1926 sizeof(ib_spec->ipv6.val.src_ip)); 1927 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1928 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1929 &ib_spec->ipv6.mask.dst_ip, 1930 sizeof(ib_spec->ipv6.mask.dst_ip)); 1931 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1932 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1933 &ib_spec->ipv6.val.dst_ip, 1934 sizeof(ib_spec->ipv6.val.dst_ip)); 1935 1936 set_tos(outer_headers_c, outer_headers_v, 1937 ib_spec->ipv6.mask.traffic_class, 1938 ib_spec->ipv6.val.traffic_class); 1939 1940 set_proto(outer_headers_c, outer_headers_v, 1941 ib_spec->ipv6.mask.next_hdr, 1942 ib_spec->ipv6.val.next_hdr); 1943 1944 MLX5_SET(fte_match_set_misc, misc_params_c, 1945 outer_ipv6_flow_label, 1946 ntohl(ib_spec->ipv6.mask.flow_label)); 1947 MLX5_SET(fte_match_set_misc, misc_params_v, 1948 outer_ipv6_flow_label, 1949 ntohl(ib_spec->ipv6.val.flow_label)); 1950 break; 1951 case IB_FLOW_SPEC_TCP: 1952 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 1953 LAST_TCP_UDP_FIELD)) 1954 return -ENOTSUPP; 1955 1956 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1957 0xff); 1958 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1959 IPPROTO_TCP); 1960 1961 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport, 1962 ntohs(ib_spec->tcp_udp.mask.src_port)); 1963 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport, 1964 ntohs(ib_spec->tcp_udp.val.src_port)); 1965 1966 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport, 1967 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1968 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport, 1969 ntohs(ib_spec->tcp_udp.val.dst_port)); 1970 break; 1971 case IB_FLOW_SPEC_UDP: 1972 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 1973 LAST_TCP_UDP_FIELD)) 1974 return -ENOTSUPP; 1975 1976 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1977 0xff); 1978 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1979 IPPROTO_UDP); 1980 1981 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport, 1982 ntohs(ib_spec->tcp_udp.mask.src_port)); 1983 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport, 1984 ntohs(ib_spec->tcp_udp.val.src_port)); 1985 1986 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport, 1987 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1988 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport, 1989 ntohs(ib_spec->tcp_udp.val.dst_port)); 1990 break; 1991 default: 1992 return -EINVAL; 1993 } 1994 1995 return 0; 1996 } 1997 1998 /* If a flow could catch both multicast and unicast packets, 1999 * it won't fall into the multicast flow steering table and this rule 2000 * could steal other multicast packets. 2001 */ 2002 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr) 2003 { 2004 struct ib_flow_spec_eth *eth_spec; 2005 2006 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 2007 ib_attr->size < sizeof(struct ib_flow_attr) + 2008 sizeof(struct ib_flow_spec_eth) || 2009 ib_attr->num_of_specs < 1) 2010 return false; 2011 2012 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1); 2013 if (eth_spec->type != IB_FLOW_SPEC_ETH || 2014 eth_spec->size != sizeof(*eth_spec)) 2015 return false; 2016 2017 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 2018 is_multicast_ether_addr(eth_spec->val.dst_mac); 2019 } 2020 2021 static bool is_valid_attr(const struct ib_flow_attr *flow_attr) 2022 { 2023 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 2024 bool has_ipv4_spec = false; 2025 bool eth_type_ipv4 = true; 2026 unsigned int spec_index; 2027 2028 /* Validate that ethertype is correct */ 2029 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2030 if (ib_spec->type == IB_FLOW_SPEC_ETH && 2031 ib_spec->eth.mask.ether_type) { 2032 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) && 2033 ib_spec->eth.val.ether_type == htons(ETH_P_IP))) 2034 eth_type_ipv4 = false; 2035 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) { 2036 has_ipv4_spec = true; 2037 } 2038 ib_spec = (void *)ib_spec + ib_spec->size; 2039 } 2040 return !has_ipv4_spec || eth_type_ipv4; 2041 } 2042 2043 static void put_flow_table(struct mlx5_ib_dev *dev, 2044 struct mlx5_ib_flow_prio *prio, bool ft_added) 2045 { 2046 prio->refcount -= !!ft_added; 2047 if (!prio->refcount) { 2048 mlx5_destroy_flow_table(prio->flow_table); 2049 prio->flow_table = NULL; 2050 } 2051 } 2052 2053 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 2054 { 2055 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 2056 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 2057 struct mlx5_ib_flow_handler, 2058 ibflow); 2059 struct mlx5_ib_flow_handler *iter, *tmp; 2060 2061 mutex_lock(&dev->flow_db.lock); 2062 2063 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 2064 mlx5_del_flow_rule(iter->rule); 2065 put_flow_table(dev, iter->prio, true); 2066 list_del(&iter->list); 2067 kfree(iter); 2068 } 2069 2070 mlx5_del_flow_rule(handler->rule); 2071 put_flow_table(dev, handler->prio, true); 2072 mutex_unlock(&dev->flow_db.lock); 2073 2074 kfree(handler); 2075 2076 return 0; 2077 } 2078 2079 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 2080 { 2081 priority *= 2; 2082 if (!dont_trap) 2083 priority++; 2084 return priority; 2085 } 2086 2087 enum flow_table_type { 2088 MLX5_IB_FT_RX, 2089 MLX5_IB_FT_TX 2090 }; 2091 2092 #define MLX5_FS_MAX_TYPES 10 2093 #define MLX5_FS_MAX_ENTRIES 32000UL 2094 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 2095 struct ib_flow_attr *flow_attr, 2096 enum flow_table_type ft_type) 2097 { 2098 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 2099 struct mlx5_flow_namespace *ns = NULL; 2100 struct mlx5_ib_flow_prio *prio; 2101 struct mlx5_flow_table *ft; 2102 int num_entries; 2103 int num_groups; 2104 int priority; 2105 int err = 0; 2106 2107 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2108 if (flow_is_multicast_only(flow_attr) && 2109 !dont_trap) 2110 priority = MLX5_IB_FLOW_MCAST_PRIO; 2111 else 2112 priority = ib_prio_to_core_prio(flow_attr->priority, 2113 dont_trap); 2114 ns = mlx5_get_flow_namespace(dev->mdev, 2115 MLX5_FLOW_NAMESPACE_BYPASS); 2116 num_entries = MLX5_FS_MAX_ENTRIES; 2117 num_groups = MLX5_FS_MAX_TYPES; 2118 prio = &dev->flow_db.prios[priority]; 2119 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2120 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2121 ns = mlx5_get_flow_namespace(dev->mdev, 2122 MLX5_FLOW_NAMESPACE_LEFTOVERS); 2123 build_leftovers_ft_param("bypass", &priority, 2124 &num_entries, 2125 &num_groups); 2126 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 2127 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2128 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 2129 allow_sniffer_and_nic_rx_shared_tir)) 2130 return ERR_PTR(-ENOTSUPP); 2131 2132 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 2133 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 2134 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 2135 2136 prio = &dev->flow_db.sniffer[ft_type]; 2137 priority = 0; 2138 num_entries = 1; 2139 num_groups = 1; 2140 } 2141 2142 if (!ns) 2143 return ERR_PTR(-ENOTSUPP); 2144 2145 ft = prio->flow_table; 2146 if (!ft) { 2147 ft = mlx5_create_auto_grouped_flow_table(ns, priority, "bypass", 2148 num_entries, 2149 num_groups); 2150 2151 if (!IS_ERR(ft)) { 2152 prio->refcount = 0; 2153 prio->flow_table = ft; 2154 } else { 2155 err = PTR_ERR(ft); 2156 } 2157 } 2158 2159 return err ? ERR_PTR(err) : prio; 2160 } 2161 2162 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 2163 struct mlx5_ib_flow_prio *ft_prio, 2164 const struct ib_flow_attr *flow_attr, 2165 struct mlx5_flow_destination *dst) 2166 { 2167 struct mlx5_flow_table *ft = ft_prio->flow_table; 2168 struct mlx5_ib_flow_handler *handler; 2169 struct mlx5_flow_spec *spec; 2170 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 2171 unsigned int spec_index; 2172 u32 action; 2173 int err = 0; 2174 2175 if (!is_valid_attr(flow_attr)) 2176 return ERR_PTR(-EINVAL); 2177 2178 spec = mlx5_vzalloc(sizeof(*spec)); 2179 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 2180 if (!handler || !spec) { 2181 err = -ENOMEM; 2182 goto free; 2183 } 2184 2185 INIT_LIST_HEAD(&handler->list); 2186 2187 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2188 err = parse_flow_attr(spec->match_criteria, 2189 spec->match_value, ib_flow); 2190 if (err < 0) 2191 goto free; 2192 2193 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 2194 } 2195 2196 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 2197 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 2198 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 2199 handler->rule = mlx5_add_flow_rule(ft, spec->match_criteria_enable, 2200 spec->match_criteria, 2201 spec->match_value, 2202 action, 2203 MLX5_FS_DEFAULT_FLOW_TAG, 2204 dst); 2205 2206 if (IS_ERR(handler->rule)) { 2207 err = PTR_ERR(handler->rule); 2208 goto free; 2209 } 2210 2211 ft_prio->refcount++; 2212 handler->prio = ft_prio; 2213 2214 ft_prio->flow_table = ft; 2215 free: 2216 if (err) 2217 kfree(handler); 2218 kvfree(spec); 2219 return err ? ERR_PTR(err) : handler; 2220 } 2221 2222 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 2223 struct mlx5_ib_flow_prio *ft_prio, 2224 struct ib_flow_attr *flow_attr, 2225 struct mlx5_flow_destination *dst) 2226 { 2227 struct mlx5_ib_flow_handler *handler_dst = NULL; 2228 struct mlx5_ib_flow_handler *handler = NULL; 2229 2230 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 2231 if (!IS_ERR(handler)) { 2232 handler_dst = create_flow_rule(dev, ft_prio, 2233 flow_attr, dst); 2234 if (IS_ERR(handler_dst)) { 2235 mlx5_del_flow_rule(handler->rule); 2236 ft_prio->refcount--; 2237 kfree(handler); 2238 handler = handler_dst; 2239 } else { 2240 list_add(&handler_dst->list, &handler->list); 2241 } 2242 } 2243 2244 return handler; 2245 } 2246 enum { 2247 LEFTOVERS_MC, 2248 LEFTOVERS_UC, 2249 }; 2250 2251 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 2252 struct mlx5_ib_flow_prio *ft_prio, 2253 struct ib_flow_attr *flow_attr, 2254 struct mlx5_flow_destination *dst) 2255 { 2256 struct mlx5_ib_flow_handler *handler_ucast = NULL; 2257 struct mlx5_ib_flow_handler *handler = NULL; 2258 2259 static struct { 2260 struct ib_flow_attr flow_attr; 2261 struct ib_flow_spec_eth eth_flow; 2262 } leftovers_specs[] = { 2263 [LEFTOVERS_MC] = { 2264 .flow_attr = { 2265 .num_of_specs = 1, 2266 .size = sizeof(leftovers_specs[0]) 2267 }, 2268 .eth_flow = { 2269 .type = IB_FLOW_SPEC_ETH, 2270 .size = sizeof(struct ib_flow_spec_eth), 2271 .mask = {.dst_mac = {0x1} }, 2272 .val = {.dst_mac = {0x1} } 2273 } 2274 }, 2275 [LEFTOVERS_UC] = { 2276 .flow_attr = { 2277 .num_of_specs = 1, 2278 .size = sizeof(leftovers_specs[0]) 2279 }, 2280 .eth_flow = { 2281 .type = IB_FLOW_SPEC_ETH, 2282 .size = sizeof(struct ib_flow_spec_eth), 2283 .mask = {.dst_mac = {0x1} }, 2284 .val = {.dst_mac = {} } 2285 } 2286 } 2287 }; 2288 2289 handler = create_flow_rule(dev, ft_prio, 2290 &leftovers_specs[LEFTOVERS_MC].flow_attr, 2291 dst); 2292 if (!IS_ERR(handler) && 2293 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 2294 handler_ucast = create_flow_rule(dev, ft_prio, 2295 &leftovers_specs[LEFTOVERS_UC].flow_attr, 2296 dst); 2297 if (IS_ERR(handler_ucast)) { 2298 mlx5_del_flow_rule(handler->rule); 2299 ft_prio->refcount--; 2300 kfree(handler); 2301 handler = handler_ucast; 2302 } else { 2303 list_add(&handler_ucast->list, &handler->list); 2304 } 2305 } 2306 2307 return handler; 2308 } 2309 2310 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 2311 struct mlx5_ib_flow_prio *ft_rx, 2312 struct mlx5_ib_flow_prio *ft_tx, 2313 struct mlx5_flow_destination *dst) 2314 { 2315 struct mlx5_ib_flow_handler *handler_rx; 2316 struct mlx5_ib_flow_handler *handler_tx; 2317 int err; 2318 static const struct ib_flow_attr flow_attr = { 2319 .num_of_specs = 0, 2320 .type = IB_FLOW_ATTR_SNIFFER, 2321 .size = sizeof(flow_attr) 2322 }; 2323 2324 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 2325 if (IS_ERR(handler_rx)) { 2326 err = PTR_ERR(handler_rx); 2327 goto err; 2328 } 2329 2330 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 2331 if (IS_ERR(handler_tx)) { 2332 err = PTR_ERR(handler_tx); 2333 goto err_tx; 2334 } 2335 2336 list_add(&handler_tx->list, &handler_rx->list); 2337 2338 return handler_rx; 2339 2340 err_tx: 2341 mlx5_del_flow_rule(handler_rx->rule); 2342 ft_rx->refcount--; 2343 kfree(handler_rx); 2344 err: 2345 return ERR_PTR(err); 2346 } 2347 2348 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 2349 struct ib_flow_attr *flow_attr, 2350 int domain, 2351 struct ib_udata *udata) 2352 { 2353 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2354 struct mlx5_ib_qp *mqp = to_mqp(qp); 2355 struct mlx5_ib_flow_handler *handler = NULL; 2356 struct mlx5_flow_destination *dst = NULL; 2357 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 2358 struct mlx5_ib_flow_prio *ft_prio; 2359 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr; 2360 size_t min_ucmd_sz, required_ucmd_sz; 2361 int err; 2362 2363 if (udata && udata->inlen) { 2364 min_ucmd_sz = offsetofend(struct mlx5_ib_create_flow, reserved); 2365 if (udata->inlen < min_ucmd_sz) 2366 return ERR_PTR(-EOPNOTSUPP); 2367 2368 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz); 2369 if (err) 2370 return ERR_PTR(err); 2371 2372 /* currently supports only one counters data */ 2373 if (ucmd_hdr.ncounters_data > 1) 2374 return ERR_PTR(-EINVAL); 2375 2376 required_ucmd_sz = min_ucmd_sz + 2377 sizeof(struct mlx5_ib_flow_counters_data) * 2378 ucmd_hdr.ncounters_data; 2379 if (udata->inlen > required_ucmd_sz && 2380 !ib_is_udata_cleared(udata, required_ucmd_sz, 2381 udata->inlen - required_ucmd_sz)) 2382 return ERR_PTR(-EOPNOTSUPP); 2383 2384 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL); 2385 if (!ucmd) 2386 return ERR_PTR(-ENOMEM); 2387 2388 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz); 2389 if (err) 2390 goto free_ucmd; 2391 } 2392 2393 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) { 2394 err = -ENOMEM; 2395 goto free_ucmd; 2396 } 2397 2398 if (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 2399 err = -EINVAL; 2400 goto free_ucmd; 2401 } 2402 2403 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 2404 if (!dst) { 2405 err = -ENOMEM; 2406 goto free_ucmd; 2407 } 2408 2409 mutex_lock(&dev->flow_db.lock); 2410 2411 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX); 2412 if (IS_ERR(ft_prio)) { 2413 err = PTR_ERR(ft_prio); 2414 goto unlock; 2415 } 2416 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2417 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 2418 if (IS_ERR(ft_prio_tx)) { 2419 err = PTR_ERR(ft_prio_tx); 2420 ft_prio_tx = NULL; 2421 goto destroy_ft; 2422 } 2423 } 2424 2425 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 2426 if (mqp->flags & MLX5_IB_QP_RSS) 2427 dst->tir_num = mqp->rss_qp.tirn; 2428 else 2429 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 2430 2431 switch (flow_attr->type) { 2432 case IB_FLOW_ATTR_NORMAL: 2433 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) { 2434 err = -EOPNOTSUPP; 2435 goto destroy_ft; 2436 } 2437 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 2438 handler = create_dont_trap_rule(dev, ft_prio, flow_attr, dst); 2439 } else { 2440 handler = create_flow_rule(dev, ft_prio, flow_attr, dst); 2441 } 2442 break; 2443 case IB_FLOW_ATTR_ALL_DEFAULT: 2444 case IB_FLOW_ATTR_MC_DEFAULT: 2445 handler = create_leftovers_rule(dev, ft_prio, flow_attr, dst); 2446 break; 2447 case IB_FLOW_ATTR_SNIFFER: 2448 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 2449 break; 2450 default: 2451 err = -EINVAL; 2452 goto destroy_ft; 2453 } 2454 2455 if (IS_ERR(handler)) { 2456 err = PTR_ERR(handler); 2457 handler = NULL; 2458 goto destroy_ft; 2459 } 2460 2461 mutex_unlock(&dev->flow_db.lock); 2462 kfree(dst); 2463 kfree(ucmd); 2464 2465 return &handler->ibflow; 2466 2467 destroy_ft: 2468 put_flow_table(dev, ft_prio, false); 2469 if (ft_prio_tx) 2470 put_flow_table(dev, ft_prio_tx, false); 2471 unlock: 2472 mutex_unlock(&dev->flow_db.lock); 2473 kfree(dst); 2474 free_ucmd: 2475 kfree(ucmd); 2476 return ERR_PTR(err); 2477 } 2478 2479 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2480 { 2481 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2482 int err; 2483 2484 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 2485 if (err) 2486 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2487 ibqp->qp_num, gid->raw); 2488 2489 return err; 2490 } 2491 2492 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2493 { 2494 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2495 int err; 2496 2497 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 2498 if (err) 2499 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2500 ibqp->qp_num, gid->raw); 2501 2502 return err; 2503 } 2504 2505 static int init_node_data(struct mlx5_ib_dev *dev) 2506 { 2507 int err; 2508 2509 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2510 if (err) 2511 return err; 2512 2513 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2514 } 2515 2516 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 2517 char *buf) 2518 { 2519 struct mlx5_ib_dev *dev = 2520 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2521 2522 return sprintf(buf, "%lld\n", (long long)dev->mdev->priv.fw_pages); 2523 } 2524 2525 static ssize_t show_reg_pages(struct device *device, 2526 struct device_attribute *attr, char *buf) 2527 { 2528 struct mlx5_ib_dev *dev = 2529 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2530 2531 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2532 } 2533 2534 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 2535 char *buf) 2536 { 2537 struct mlx5_ib_dev *dev = 2538 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2539 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 2540 } 2541 2542 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 2543 char *buf) 2544 { 2545 struct mlx5_ib_dev *dev = 2546 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2547 return sprintf(buf, "%x\n", dev->mdev->pdev->revision); 2548 } 2549 2550 static ssize_t show_board(struct device *device, struct device_attribute *attr, 2551 char *buf) 2552 { 2553 struct mlx5_ib_dev *dev = 2554 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2555 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2556 dev->mdev->board_id); 2557 } 2558 2559 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 2560 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 2561 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 2562 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 2563 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 2564 2565 static struct device_attribute *mlx5_class_attributes[] = { 2566 &dev_attr_hw_rev, 2567 &dev_attr_hca_type, 2568 &dev_attr_board_id, 2569 &dev_attr_fw_pages, 2570 &dev_attr_reg_pages, 2571 }; 2572 2573 static void pkey_change_handler(struct work_struct *work) 2574 { 2575 struct mlx5_ib_port_resources *ports = 2576 container_of(work, struct mlx5_ib_port_resources, 2577 pkey_change_work); 2578 2579 mutex_lock(&ports->devr->mutex); 2580 mlx5_ib_gsi_pkey_change(ports->gsi); 2581 mutex_unlock(&ports->devr->mutex); 2582 } 2583 2584 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2585 { 2586 struct mlx5_ib_qp *mqp; 2587 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2588 struct mlx5_core_cq *mcq; 2589 struct list_head cq_armed_list; 2590 unsigned long flags_qp; 2591 unsigned long flags_cq; 2592 unsigned long flags; 2593 2594 INIT_LIST_HEAD(&cq_armed_list); 2595 2596 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2597 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2598 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2599 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2600 if (mqp->sq.tail != mqp->sq.head) { 2601 send_mcq = to_mcq(mqp->ibqp.send_cq); 2602 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2603 if (send_mcq->mcq.comp && 2604 mqp->ibqp.send_cq->comp_handler) { 2605 if (!send_mcq->mcq.reset_notify_added) { 2606 send_mcq->mcq.reset_notify_added = 1; 2607 list_add_tail(&send_mcq->mcq.reset_notify, 2608 &cq_armed_list); 2609 } 2610 } 2611 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2612 } 2613 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2614 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2615 /* no handling is needed for SRQ */ 2616 if (!mqp->ibqp.srq) { 2617 if (mqp->rq.tail != mqp->rq.head) { 2618 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2619 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2620 if (recv_mcq->mcq.comp && 2621 mqp->ibqp.recv_cq->comp_handler) { 2622 if (!recv_mcq->mcq.reset_notify_added) { 2623 recv_mcq->mcq.reset_notify_added = 1; 2624 list_add_tail(&recv_mcq->mcq.reset_notify, 2625 &cq_armed_list); 2626 } 2627 } 2628 spin_unlock_irqrestore(&recv_mcq->lock, 2629 flags_cq); 2630 } 2631 } 2632 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2633 } 2634 /*At that point all inflight post send were put to be executed as of we 2635 * lock/unlock above locks Now need to arm all involved CQs. 2636 */ 2637 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2638 mcq->comp(mcq, NULL); 2639 } 2640 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2641 } 2642 2643 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 2644 enum mlx5_dev_event event, unsigned long param) 2645 { 2646 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; 2647 struct ib_event ibev; 2648 bool fatal = false; 2649 u8 port = (u8)param; 2650 2651 switch (event) { 2652 case MLX5_DEV_EVENT_SYS_ERROR: 2653 ibev.event = IB_EVENT_DEVICE_FATAL; 2654 mlx5_ib_handle_internal_error(ibdev); 2655 fatal = true; 2656 break; 2657 2658 case MLX5_DEV_EVENT_PORT_UP: 2659 case MLX5_DEV_EVENT_PORT_DOWN: 2660 case MLX5_DEV_EVENT_PORT_INITIALIZED: 2661 /* In RoCE, port up/down events are handled in 2662 * mlx5_netdev_event(). 2663 */ 2664 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2665 IB_LINK_LAYER_ETHERNET) 2666 return; 2667 2668 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ? 2669 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2670 break; 2671 2672 case MLX5_DEV_EVENT_LID_CHANGE: 2673 ibev.event = IB_EVENT_LID_CHANGE; 2674 break; 2675 2676 case MLX5_DEV_EVENT_PKEY_CHANGE: 2677 ibev.event = IB_EVENT_PKEY_CHANGE; 2678 2679 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2680 break; 2681 2682 case MLX5_DEV_EVENT_GUID_CHANGE: 2683 ibev.event = IB_EVENT_GID_CHANGE; 2684 break; 2685 2686 case MLX5_DEV_EVENT_CLIENT_REREG: 2687 ibev.event = IB_EVENT_CLIENT_REREGISTER; 2688 break; 2689 2690 default: 2691 /* unsupported event */ 2692 return; 2693 } 2694 2695 ibev.device = &ibdev->ib_dev; 2696 ibev.element.port_num = port; 2697 2698 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) { 2699 mlx5_ib_warn(ibdev, "warning: event(%d) on port %d\n", event, port); 2700 return; 2701 } 2702 2703 if (ibdev->ib_active) 2704 ib_dispatch_event(&ibev); 2705 2706 if (fatal) 2707 ibdev->ib_active = false; 2708 } 2709 2710 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2711 { 2712 int port; 2713 2714 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) 2715 mlx5_query_ext_port_caps(dev, port); 2716 } 2717 2718 static int get_port_caps(struct mlx5_ib_dev *dev) 2719 { 2720 struct ib_device_attr *dprops = NULL; 2721 struct ib_port_attr *pprops = NULL; 2722 int err = -ENOMEM; 2723 int port; 2724 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 2725 2726 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 2727 if (!pprops) 2728 goto out; 2729 2730 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 2731 if (!dprops) 2732 goto out; 2733 2734 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 2735 if (err) { 2736 mlx5_ib_warn(dev, "query_device failed %d\n", err); 2737 goto out; 2738 } 2739 2740 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 2741 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 2742 if (err) { 2743 mlx5_ib_warn(dev, "query_port %d failed %d\n", 2744 port, err); 2745 break; 2746 } 2747 dev->mdev->port_caps[port - 1].pkey_table_len = 2748 dprops->max_pkeys; 2749 dev->mdev->port_caps[port - 1].gid_table_len = 2750 pprops->gid_tbl_len; 2751 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n", 2752 dprops->max_pkeys, pprops->gid_tbl_len); 2753 } 2754 2755 out: 2756 kfree(pprops); 2757 kfree(dprops); 2758 2759 return err; 2760 } 2761 2762 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 2763 { 2764 int err; 2765 2766 err = mlx5_mr_cache_cleanup(dev); 2767 if (err) 2768 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 2769 2770 if (dev->umrc.qp) 2771 mlx5_ib_destroy_qp(dev->umrc.qp, NULL); 2772 if (dev->umrc.cq) 2773 ib_free_cq(dev->umrc.cq); 2774 if (dev->umrc.pd) 2775 ib_dealloc_pd(dev->umrc.pd); 2776 } 2777 2778 enum { 2779 MAX_UMR_WR = 128, 2780 }; 2781 2782 static int create_umr_res(struct mlx5_ib_dev *dev) 2783 { 2784 struct ib_qp_init_attr *init_attr = NULL; 2785 struct ib_qp_attr *attr = NULL; 2786 struct ib_pd *pd; 2787 struct ib_cq *cq; 2788 struct ib_qp *qp; 2789 int ret; 2790 2791 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 2792 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 2793 if (!attr || !init_attr) { 2794 ret = -ENOMEM; 2795 goto error_0; 2796 } 2797 2798 pd = ib_alloc_pd(&dev->ib_dev, 0); 2799 if (IS_ERR(pd)) { 2800 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 2801 ret = PTR_ERR(pd); 2802 goto error_0; 2803 } 2804 2805 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 2806 if (IS_ERR(cq)) { 2807 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 2808 ret = PTR_ERR(cq); 2809 goto error_2; 2810 } 2811 2812 init_attr->send_cq = cq; 2813 init_attr->recv_cq = cq; 2814 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 2815 init_attr->cap.max_send_wr = MAX_UMR_WR; 2816 init_attr->cap.max_send_sge = 1; 2817 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 2818 init_attr->port_num = 1; 2819 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 2820 if (IS_ERR(qp)) { 2821 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 2822 ret = PTR_ERR(qp); 2823 goto error_3; 2824 } 2825 qp->device = &dev->ib_dev; 2826 qp->real_qp = qp; 2827 qp->uobject = NULL; 2828 qp->qp_type = MLX5_IB_QPT_REG_UMR; 2829 2830 attr->qp_state = IB_QPS_INIT; 2831 attr->port_num = 1; 2832 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 2833 IB_QP_PORT, NULL); 2834 if (ret) { 2835 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 2836 goto error_4; 2837 } 2838 2839 memset(attr, 0, sizeof(*attr)); 2840 attr->qp_state = IB_QPS_RTR; 2841 attr->path_mtu = IB_MTU_256; 2842 2843 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2844 if (ret) { 2845 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 2846 goto error_4; 2847 } 2848 2849 memset(attr, 0, sizeof(*attr)); 2850 attr->qp_state = IB_QPS_RTS; 2851 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2852 if (ret) { 2853 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 2854 goto error_4; 2855 } 2856 2857 dev->umrc.qp = qp; 2858 dev->umrc.cq = cq; 2859 dev->umrc.pd = pd; 2860 2861 sema_init(&dev->umrc.sem, MAX_UMR_WR); 2862 ret = mlx5_mr_cache_init(dev); 2863 if (ret) { 2864 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 2865 goto error_4; 2866 } 2867 2868 kfree(attr); 2869 kfree(init_attr); 2870 2871 return 0; 2872 2873 error_4: 2874 mlx5_ib_destroy_qp(qp, NULL); 2875 dev->umrc.qp = NULL; 2876 2877 error_3: 2878 ib_free_cq(cq); 2879 dev->umrc.cq = NULL; 2880 2881 error_2: 2882 ib_dealloc_pd(pd); 2883 dev->umrc.pd = NULL; 2884 2885 error_0: 2886 kfree(attr); 2887 kfree(init_attr); 2888 return ret; 2889 } 2890 2891 static int create_dev_resources(struct mlx5_ib_resources *devr) 2892 { 2893 struct ib_srq_init_attr attr; 2894 struct mlx5_ib_dev *dev; 2895 struct ib_device *ibdev; 2896 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2897 int port; 2898 int ret = 0; 2899 2900 dev = container_of(devr, struct mlx5_ib_dev, devr); 2901 ibdev = &dev->ib_dev; 2902 2903 mutex_init(&devr->mutex); 2904 2905 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd); 2906 if (!devr->p0) 2907 return -ENOMEM; 2908 2909 devr->p0->device = ibdev; 2910 devr->p0->uobject = NULL; 2911 atomic_set(&devr->p0->usecnt, 0); 2912 2913 ret = mlx5_ib_alloc_pd(devr->p0, NULL); 2914 if (ret) 2915 goto error0; 2916 2917 devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq); 2918 if (!devr->c0) { 2919 ret = -ENOMEM; 2920 goto error1; 2921 } 2922 2923 devr->c0->device = &dev->ib_dev; 2924 atomic_set(&devr->c0->usecnt, 0); 2925 2926 ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL); 2927 if (ret) 2928 goto err_create_cq; 2929 2930 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL); 2931 if (IS_ERR(devr->x0)) { 2932 ret = PTR_ERR(devr->x0); 2933 goto error2; 2934 } 2935 devr->x0->device = &dev->ib_dev; 2936 devr->x0->inode = NULL; 2937 atomic_set(&devr->x0->usecnt, 0); 2938 mutex_init(&devr->x0->tgt_qp_mutex); 2939 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 2940 2941 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL); 2942 if (IS_ERR(devr->x1)) { 2943 ret = PTR_ERR(devr->x1); 2944 goto error3; 2945 } 2946 devr->x1->device = &dev->ib_dev; 2947 devr->x1->inode = NULL; 2948 atomic_set(&devr->x1->usecnt, 0); 2949 mutex_init(&devr->x1->tgt_qp_mutex); 2950 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 2951 2952 memset(&attr, 0, sizeof(attr)); 2953 attr.attr.max_sge = 1; 2954 attr.attr.max_wr = 1; 2955 attr.srq_type = IB_SRQT_XRC; 2956 attr.ext.cq = devr->c0; 2957 attr.ext.xrc.xrcd = devr->x0; 2958 2959 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq); 2960 if (!devr->s0) { 2961 ret = -ENOMEM; 2962 goto error4; 2963 } 2964 2965 devr->s0->device = &dev->ib_dev; 2966 devr->s0->pd = devr->p0; 2967 devr->s0->srq_type = IB_SRQT_XRC; 2968 devr->s0->ext.xrc.xrcd = devr->x0; 2969 devr->s0->ext.cq = devr->c0; 2970 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL); 2971 if (ret) 2972 goto err_create; 2973 2974 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 2975 atomic_inc(&devr->s0->ext.cq->usecnt); 2976 atomic_inc(&devr->p0->usecnt); 2977 atomic_set(&devr->s0->usecnt, 0); 2978 2979 memset(&attr, 0, sizeof(attr)); 2980 attr.attr.max_sge = 1; 2981 attr.attr.max_wr = 1; 2982 attr.srq_type = IB_SRQT_BASIC; 2983 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq); 2984 if (!devr->s1) { 2985 ret = -ENOMEM; 2986 goto error5; 2987 } 2988 2989 devr->s1->device = &dev->ib_dev; 2990 devr->s1->pd = devr->p0; 2991 devr->s1->srq_type = IB_SRQT_BASIC; 2992 devr->s1->ext.cq = devr->c0; 2993 2994 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL); 2995 if (ret) 2996 goto error6; 2997 2998 atomic_inc(&devr->p0->usecnt); 2999 atomic_set(&devr->s1->usecnt, 0); 3000 3001 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 3002 INIT_WORK(&devr->ports[port].pkey_change_work, 3003 pkey_change_handler); 3004 devr->ports[port].devr = devr; 3005 } 3006 3007 return 0; 3008 3009 error6: 3010 kfree(devr->s1); 3011 error5: 3012 mlx5_ib_destroy_srq(devr->s0, NULL); 3013 err_create: 3014 kfree(devr->s0); 3015 error4: 3016 mlx5_ib_dealloc_xrcd(devr->x1, NULL); 3017 error3: 3018 mlx5_ib_dealloc_xrcd(devr->x0, NULL); 3019 error2: 3020 mlx5_ib_destroy_cq(devr->c0, NULL); 3021 err_create_cq: 3022 kfree(devr->c0); 3023 error1: 3024 mlx5_ib_dealloc_pd(devr->p0, NULL); 3025 error0: 3026 kfree(devr->p0); 3027 return ret; 3028 } 3029 3030 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 3031 { 3032 int port; 3033 3034 mlx5_ib_destroy_srq(devr->s1, NULL); 3035 kfree(devr->s1); 3036 mlx5_ib_destroy_srq(devr->s0, NULL); 3037 kfree(devr->s0); 3038 mlx5_ib_dealloc_xrcd(devr->x0, NULL); 3039 mlx5_ib_dealloc_xrcd(devr->x1, NULL); 3040 mlx5_ib_destroy_cq(devr->c0, NULL); 3041 kfree(devr->c0); 3042 mlx5_ib_dealloc_pd(devr->p0, NULL); 3043 kfree(devr->p0); 3044 3045 /* Make sure no change P_Key work items are still executing */ 3046 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 3047 cancel_work_sync(&devr->ports[port].pkey_change_work); 3048 } 3049 3050 static u32 get_core_cap_flags(struct ib_device *ibdev) 3051 { 3052 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3053 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3054 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3055 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3056 u32 ret = 0; 3057 3058 if (ll == IB_LINK_LAYER_INFINIBAND) 3059 return RDMA_CORE_PORT_IBA_IB; 3060 3061 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3062 return 0; 3063 3064 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3065 return 0; 3066 3067 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3068 ret |= RDMA_CORE_PORT_IBA_ROCE; 3069 3070 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3071 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3072 3073 return ret; 3074 } 3075 3076 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 3077 struct ib_port_immutable *immutable) 3078 { 3079 struct ib_port_attr attr; 3080 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3081 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3082 int err; 3083 3084 err = mlx5_ib_query_port(ibdev, port_num, &attr); 3085 if (err) 3086 return err; 3087 3088 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3089 immutable->gid_tbl_len = attr.gid_tbl_len; 3090 immutable->core_cap_flags = get_core_cap_flags(ibdev); 3091 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce)) 3092 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3093 3094 return 0; 3095 } 3096 3097 static void get_dev_fw_str(struct ib_device *ibdev, char *str, 3098 size_t str_len) 3099 { 3100 struct mlx5_ib_dev *dev = 3101 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3102 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev), 3103 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev)); 3104 } 3105 3106 static int mlx5_roce_lag_init(struct mlx5_ib_dev *dev) 3107 { 3108 return 0; 3109 } 3110 3111 static void mlx5_roce_lag_cleanup(struct mlx5_ib_dev *dev) 3112 { 3113 } 3114 3115 static void mlx5_remove_roce_notifier(struct mlx5_ib_dev *dev) 3116 { 3117 if (dev->roce.nb.notifier_call) { 3118 unregister_netdevice_notifier(&dev->roce.nb); 3119 dev->roce.nb.notifier_call = NULL; 3120 } 3121 } 3122 3123 static int mlx5_enable_roce(struct mlx5_ib_dev *dev) 3124 { 3125 VNET_ITERATOR_DECL(vnet_iter); 3126 struct ifnet *idev; 3127 int err; 3128 3129 /* Check if mlx5en net device already exists */ 3130 VNET_LIST_RLOCK(); 3131 VNET_FOREACH(vnet_iter) { 3132 IFNET_RLOCK(); 3133 CURVNET_SET_QUIET(vnet_iter); 3134 CK_STAILQ_FOREACH(idev, &V_ifnet, if_link) { 3135 /* check if network interface belongs to mlx5en */ 3136 if (!mlx5_netdev_match(idev, dev->mdev, "mce")) 3137 continue; 3138 write_lock(&dev->roce.netdev_lock); 3139 dev->roce.netdev = idev; 3140 write_unlock(&dev->roce.netdev_lock); 3141 } 3142 CURVNET_RESTORE(); 3143 IFNET_RUNLOCK(); 3144 } 3145 VNET_LIST_RUNLOCK(); 3146 3147 dev->roce.nb.notifier_call = mlx5_netdev_event; 3148 err = register_netdevice_notifier(&dev->roce.nb); 3149 if (err) { 3150 dev->roce.nb.notifier_call = NULL; 3151 return err; 3152 } 3153 3154 if (MLX5_CAP_GEN(dev->mdev, roce)) { 3155 err = mlx5_nic_vport_enable_roce(dev->mdev); 3156 if (err) 3157 goto err_unregister_netdevice_notifier; 3158 } 3159 3160 err = mlx5_roce_lag_init(dev); 3161 if (err) 3162 goto err_disable_roce; 3163 3164 return 0; 3165 3166 err_disable_roce: 3167 if (MLX5_CAP_GEN(dev->mdev, roce)) 3168 mlx5_nic_vport_disable_roce(dev->mdev); 3169 3170 err_unregister_netdevice_notifier: 3171 mlx5_remove_roce_notifier(dev); 3172 return err; 3173 } 3174 3175 static void mlx5_disable_roce(struct mlx5_ib_dev *dev) 3176 { 3177 mlx5_roce_lag_cleanup(dev); 3178 if (MLX5_CAP_GEN(dev->mdev, roce)) 3179 mlx5_nic_vport_disable_roce(dev->mdev); 3180 } 3181 3182 static void mlx5_ib_dealloc_q_port_counter(struct mlx5_ib_dev *dev, u8 port_num) 3183 { 3184 mlx5_vport_dealloc_q_counter(dev->mdev, 3185 MLX5_INTERFACE_PROTOCOL_IB, 3186 dev->port[port_num].q_cnt_id); 3187 dev->port[port_num].q_cnt_id = 0; 3188 } 3189 3190 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev) 3191 { 3192 unsigned int i; 3193 3194 for (i = 0; i < dev->num_ports; i++) 3195 mlx5_ib_dealloc_q_port_counter(dev, i); 3196 } 3197 3198 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev) 3199 { 3200 int i; 3201 int ret; 3202 3203 for (i = 0; i < dev->num_ports; i++) { 3204 ret = mlx5_vport_alloc_q_counter(dev->mdev, 3205 MLX5_INTERFACE_PROTOCOL_IB, 3206 &dev->port[i].q_cnt_id); 3207 if (ret) { 3208 mlx5_ib_warn(dev, 3209 "couldn't allocate queue counter for port %d, err %d\n", 3210 i + 1, ret); 3211 goto dealloc_counters; 3212 } 3213 } 3214 3215 return 0; 3216 3217 dealloc_counters: 3218 while (--i >= 0) 3219 mlx5_ib_dealloc_q_port_counter(dev, i); 3220 3221 return ret; 3222 } 3223 3224 static const char * const names[] = { 3225 "rx_write_requests", 3226 "rx_read_requests", 3227 "rx_atomic_requests", 3228 "out_of_buffer", 3229 "out_of_sequence", 3230 "duplicate_request", 3231 "rnr_nak_retry_err", 3232 "packet_seq_err", 3233 "implied_nak_seq_err", 3234 "local_ack_timeout_err", 3235 }; 3236 3237 static const size_t stats_offsets[] = { 3238 MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests), 3239 MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests), 3240 MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests), 3241 MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer), 3242 MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence), 3243 MLX5_BYTE_OFF(query_q_counter_out, duplicate_request), 3244 MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err), 3245 MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err), 3246 MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err), 3247 MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err), 3248 }; 3249 3250 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 3251 u8 port_num) 3252 { 3253 BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets)); 3254 3255 /* We support only per port stats */ 3256 if (port_num == 0) 3257 return NULL; 3258 3259 return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names), 3260 RDMA_HW_STATS_DEFAULT_LIFESPAN); 3261 } 3262 3263 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 3264 struct rdma_hw_stats *stats, 3265 u8 port, int index) 3266 { 3267 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3268 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 3269 void *out; 3270 __be32 val; 3271 int ret; 3272 int i; 3273 3274 if (!port || !stats) 3275 return -ENOSYS; 3276 3277 out = mlx5_vzalloc(outlen); 3278 if (!out) 3279 return -ENOMEM; 3280 3281 ret = mlx5_vport_query_q_counter(dev->mdev, 3282 dev->port[port - 1].q_cnt_id, 0, 3283 out, outlen); 3284 if (ret) 3285 goto free; 3286 3287 for (i = 0; i < ARRAY_SIZE(names); i++) { 3288 val = *(__be32 *)(out + stats_offsets[i]); 3289 stats->value[i] = (u64)be32_to_cpu(val); 3290 } 3291 free: 3292 kvfree(out); 3293 return ARRAY_SIZE(names); 3294 } 3295 3296 static int mlx5_ib_stage_bfreg_init(struct mlx5_ib_dev *dev) 3297 { 3298 int err; 3299 3300 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 3301 if (err) 3302 return err; 3303 3304 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 3305 if (err) { 3306 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 3307 return err; 3308 } 3309 3310 err = mlx5_alloc_bfreg(dev->mdev, &dev->wc_bfreg, true, false); 3311 if (err) { 3312 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 3313 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 3314 } 3315 3316 return err; 3317 } 3318 3319 static void mlx5_ib_stage_bfreg_cleanup(struct mlx5_ib_dev *dev) 3320 { 3321 mlx5_free_bfreg(dev->mdev, &dev->wc_bfreg); 3322 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 3323 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 3324 } 3325 3326 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 3327 { 3328 struct mlx5_ib_dev *dev; 3329 enum rdma_link_layer ll; 3330 int port_type_cap; 3331 int err; 3332 int i; 3333 3334 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3335 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3336 3337 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 3338 if (!dev) 3339 return NULL; 3340 3341 dev->mdev = mdev; 3342 3343 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port), 3344 GFP_KERNEL); 3345 if (!dev->port) 3346 goto err_dealloc; 3347 3348 rwlock_init(&dev->roce.netdev_lock); 3349 err = get_port_caps(dev); 3350 if (err) 3351 goto err_free_port; 3352 3353 if (mlx5_use_mad_ifc(dev)) 3354 get_ext_port_caps(dev); 3355 3356 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock); 3357 3358 mutex_init(&dev->lb_mutex); 3359 3360 INIT_IB_DEVICE_OPS(&dev->ib_dev.ops, mlx5, MLX5); 3361 snprintf(dev->ib_dev.name, IB_DEVICE_NAME_MAX, "mlx5_%d", device_get_unit(mdev->pdev->dev.bsddev)); 3362 dev->ib_dev.owner = THIS_MODULE; 3363 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3364 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3365 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports); 3366 dev->ib_dev.phys_port_cnt = dev->num_ports; 3367 dev->ib_dev.num_comp_vectors = 3368 dev->mdev->priv.eq_table.num_comp_vectors; 3369 dev->ib_dev.dma_device = &mdev->pdev->dev; 3370 3371 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 3372 dev->ib_dev.uverbs_cmd_mask = 3373 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 3374 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 3375 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 3376 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 3377 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 3378 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 3379 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 3380 (1ull << IB_USER_VERBS_CMD_REG_MR) | 3381 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 3382 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 3383 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 3384 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 3385 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 3386 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 3387 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 3388 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 3389 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 3390 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 3391 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 3392 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 3393 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 3394 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 3395 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 3396 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 3397 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 3398 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 3399 dev->ib_dev.uverbs_ex_cmd_mask = 3400 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 3401 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 3402 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP); 3403 3404 dev->ib_dev.query_device = mlx5_ib_query_device; 3405 dev->ib_dev.query_port = mlx5_ib_query_port; 3406 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 3407 if (ll == IB_LINK_LAYER_ETHERNET) 3408 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 3409 dev->ib_dev.query_gid = mlx5_ib_query_gid; 3410 dev->ib_dev.add_gid = mlx5_ib_add_gid; 3411 dev->ib_dev.del_gid = mlx5_ib_del_gid; 3412 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 3413 dev->ib_dev.modify_device = mlx5_ib_modify_device; 3414 dev->ib_dev.modify_port = mlx5_ib_modify_port; 3415 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 3416 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 3417 dev->ib_dev.mmap = mlx5_ib_mmap; 3418 dev->ib_dev.mmap_free = mlx5_ib_mmap_free; 3419 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 3420 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 3421 dev->ib_dev.create_ah = mlx5_ib_create_ah; 3422 dev->ib_dev.query_ah = mlx5_ib_query_ah; 3423 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 3424 dev->ib_dev.create_srq = mlx5_ib_create_srq; 3425 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 3426 dev->ib_dev.query_srq = mlx5_ib_query_srq; 3427 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 3428 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 3429 dev->ib_dev.create_qp = mlx5_ib_create_qp; 3430 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 3431 dev->ib_dev.query_qp = mlx5_ib_query_qp; 3432 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 3433 dev->ib_dev.post_send = mlx5_ib_post_send; 3434 dev->ib_dev.post_recv = mlx5_ib_post_recv; 3435 dev->ib_dev.create_cq = mlx5_ib_create_cq; 3436 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 3437 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 3438 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 3439 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 3440 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 3441 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 3442 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 3443 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 3444 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 3445 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 3446 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 3447 dev->ib_dev.process_mad = mlx5_ib_process_mad; 3448 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 3449 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 3450 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 3451 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 3452 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 3453 if (mlx5_core_is_pf(mdev)) { 3454 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 3455 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 3456 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 3457 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 3458 } 3459 3460 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 3461 3462 mlx5_ib_internal_fill_odp_caps(dev); 3463 3464 if (MLX5_CAP_GEN(mdev, imaicl)) { 3465 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 3466 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 3467 dev->ib_dev.uverbs_cmd_mask |= 3468 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 3469 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 3470 } 3471 3472 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) && 3473 MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 3474 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 3475 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 3476 } 3477 3478 if (MLX5_CAP_GEN(mdev, xrc)) { 3479 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 3480 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 3481 dev->ib_dev.uverbs_cmd_mask |= 3482 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 3483 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 3484 } 3485 3486 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) == 3487 IB_LINK_LAYER_ETHERNET) { 3488 dev->ib_dev.create_flow = mlx5_ib_create_flow; 3489 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 3490 dev->ib_dev.create_wq = mlx5_ib_create_wq; 3491 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 3492 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 3493 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 3494 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 3495 dev->ib_dev.uverbs_ex_cmd_mask |= 3496 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 3497 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) | 3498 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 3499 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 3500 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 3501 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 3502 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 3503 } 3504 err = init_node_data(dev); 3505 if (err) 3506 goto err_free_port; 3507 3508 mutex_init(&dev->flow_db.lock); 3509 mutex_init(&dev->cap_mask_mutex); 3510 INIT_LIST_HEAD(&dev->qp_list); 3511 spin_lock_init(&dev->reset_flow_resource_lock); 3512 3513 if (ll == IB_LINK_LAYER_ETHERNET) { 3514 err = mlx5_enable_roce(dev); 3515 if (err) 3516 goto err_free_port; 3517 } 3518 3519 err = create_dev_resources(&dev->devr); 3520 if (err) 3521 goto err_disable_roce; 3522 3523 err = mlx5_ib_odp_init_one(dev); 3524 if (err) 3525 goto err_rsrc; 3526 3527 err = mlx5_ib_alloc_q_counters(dev); 3528 if (err) 3529 goto err_odp; 3530 3531 err = mlx5_ib_stage_bfreg_init(dev); 3532 if (err) 3533 goto err_q_cnt; 3534 3535 err = ib_register_device(&dev->ib_dev, NULL); 3536 if (err) 3537 goto err_bfreg; 3538 3539 err = create_umr_res(dev); 3540 if (err) 3541 goto err_dev; 3542 3543 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 3544 err = device_create_file(&dev->ib_dev.dev, 3545 mlx5_class_attributes[i]); 3546 if (err) 3547 goto err_umrc; 3548 } 3549 3550 err = mlx5_ib_init_congestion(dev); 3551 if (err) 3552 goto err_umrc; 3553 3554 dev->ib_active = true; 3555 3556 return dev; 3557 3558 err_umrc: 3559 destroy_umrc_res(dev); 3560 3561 err_dev: 3562 ib_unregister_device(&dev->ib_dev); 3563 3564 err_bfreg: 3565 mlx5_ib_stage_bfreg_cleanup(dev); 3566 3567 err_q_cnt: 3568 mlx5_ib_dealloc_q_counters(dev); 3569 3570 err_odp: 3571 mlx5_ib_odp_remove_one(dev); 3572 3573 err_rsrc: 3574 destroy_dev_resources(&dev->devr); 3575 3576 err_disable_roce: 3577 if (ll == IB_LINK_LAYER_ETHERNET) { 3578 mlx5_disable_roce(dev); 3579 mlx5_remove_roce_notifier(dev); 3580 } 3581 3582 err_free_port: 3583 kfree(dev->port); 3584 3585 err_dealloc: 3586 ib_dealloc_device((struct ib_device *)dev); 3587 3588 return NULL; 3589 } 3590 3591 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 3592 { 3593 struct mlx5_ib_dev *dev = context; 3594 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); 3595 3596 mlx5_ib_cleanup_congestion(dev); 3597 mlx5_remove_roce_notifier(dev); 3598 ib_unregister_device(&dev->ib_dev); 3599 mlx5_ib_stage_bfreg_cleanup(dev); 3600 mlx5_ib_dealloc_q_counters(dev); 3601 destroy_umrc_res(dev); 3602 mlx5_ib_odp_remove_one(dev); 3603 destroy_dev_resources(&dev->devr); 3604 if (ll == IB_LINK_LAYER_ETHERNET) 3605 mlx5_disable_roce(dev); 3606 kfree(dev->port); 3607 ib_dealloc_device(&dev->ib_dev); 3608 } 3609 3610 static struct mlx5_interface mlx5_ib_interface = { 3611 .add = mlx5_ib_add, 3612 .remove = mlx5_ib_remove, 3613 .event = mlx5_ib_event, 3614 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 3615 }; 3616 3617 static int __init mlx5_ib_init(void) 3618 { 3619 int err; 3620 3621 err = mlx5_ib_odp_init(); 3622 if (err) 3623 return err; 3624 3625 err = mlx5_register_interface(&mlx5_ib_interface); 3626 if (err) 3627 goto clean_odp; 3628 3629 return err; 3630 3631 clean_odp: 3632 mlx5_ib_odp_cleanup(); 3633 return err; 3634 } 3635 3636 static void __exit mlx5_ib_cleanup(void) 3637 { 3638 mlx5_unregister_interface(&mlx5_ib_interface); 3639 mlx5_ib_odp_cleanup(); 3640 } 3641 3642 module_init_order(mlx5_ib_init, SI_ORDER_SEVENTH); 3643 module_exit_order(mlx5_ib_cleanup, SI_ORDER_SEVENTH); 3644