1 /*- 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include <linux/module.h> 29 #include <linux/errno.h> 30 #include <linux/pci.h> 31 #include <linux/dma-mapping.h> 32 #include <linux/slab.h> 33 #if defined(CONFIG_X86) 34 #include <asm/pat.h> 35 #endif 36 #include <linux/sched.h> 37 #include <linux/delay.h> 38 #include <linux/fs.h> 39 #undef inode 40 #include <rdma/ib_user_verbs.h> 41 #include <rdma/ib_addr.h> 42 #include <rdma/ib_cache.h> 43 #include <dev/mlx5/port.h> 44 #include <dev/mlx5/vport.h> 45 #include <linux/list.h> 46 #include <rdma/ib_smi.h> 47 #include <rdma/ib_umem.h> 48 #include <linux/in.h> 49 #include <linux/etherdevice.h> 50 #include <dev/mlx5/fs.h> 51 #include "mlx5_ib.h" 52 53 #define DRIVER_NAME "mlx5ib" 54 #ifndef DRIVER_VERSION 55 #define DRIVER_VERSION "3.5.1" 56 #endif 57 #define DRIVER_RELDATE "April 2019" 58 59 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 60 MODULE_LICENSE("Dual BSD/GPL"); 61 MODULE_DEPEND(mlx5ib, linuxkpi, 1, 1, 1); 62 MODULE_DEPEND(mlx5ib, mlx5, 1, 1, 1); 63 MODULE_DEPEND(mlx5ib, ibcore, 1, 1, 1); 64 MODULE_VERSION(mlx5ib, 1); 65 66 static const char mlx5_version[] = 67 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver " 68 DRIVER_VERSION " (" DRIVER_RELDATE ")\n"; 69 70 enum { 71 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 72 }; 73 74 static enum rdma_link_layer 75 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 76 { 77 switch (port_type_cap) { 78 case MLX5_CAP_PORT_TYPE_IB: 79 return IB_LINK_LAYER_INFINIBAND; 80 case MLX5_CAP_PORT_TYPE_ETH: 81 return IB_LINK_LAYER_ETHERNET; 82 default: 83 return IB_LINK_LAYER_UNSPECIFIED; 84 } 85 } 86 87 static enum rdma_link_layer 88 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 89 { 90 struct mlx5_ib_dev *dev = to_mdev(device); 91 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 92 93 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 94 } 95 96 static bool mlx5_netdev_match(struct net_device *ndev, 97 struct mlx5_core_dev *mdev, 98 const char *dname) 99 { 100 return ndev->if_type == IFT_ETHER && 101 ndev->if_dname != NULL && 102 strcmp(ndev->if_dname, dname) == 0 && 103 ndev->if_softc != NULL && 104 *(struct mlx5_core_dev **)ndev->if_softc == mdev; 105 } 106 107 static int mlx5_netdev_event(struct notifier_block *this, 108 unsigned long event, void *ptr) 109 { 110 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 111 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev, 112 roce.nb); 113 114 switch (event) { 115 case NETDEV_REGISTER: 116 case NETDEV_UNREGISTER: 117 write_lock(&ibdev->roce.netdev_lock); 118 /* check if network interface belongs to mlx5en */ 119 if (mlx5_netdev_match(ndev, ibdev->mdev, "mce")) 120 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? 121 NULL : ndev; 122 write_unlock(&ibdev->roce.netdev_lock); 123 break; 124 125 case NETDEV_UP: 126 case NETDEV_DOWN: { 127 struct net_device *upper = NULL; 128 129 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev)) 130 && ibdev->ib_active) { 131 struct ib_event ibev = {0}; 132 133 ibev.device = &ibdev->ib_dev; 134 ibev.event = (event == NETDEV_UP) ? 135 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 136 ibev.element.port_num = 1; 137 ib_dispatch_event(&ibev); 138 } 139 break; 140 } 141 142 default: 143 break; 144 } 145 146 return NOTIFY_DONE; 147 } 148 149 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 150 u8 port_num) 151 { 152 struct mlx5_ib_dev *ibdev = to_mdev(device); 153 struct net_device *ndev; 154 155 /* Ensure ndev does not disappear before we invoke dev_hold() 156 */ 157 read_lock(&ibdev->roce.netdev_lock); 158 ndev = ibdev->roce.netdev; 159 if (ndev) 160 dev_hold(ndev); 161 read_unlock(&ibdev->roce.netdev_lock); 162 163 return ndev; 164 } 165 166 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 167 u8 *active_width) 168 { 169 switch (eth_proto_oper) { 170 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 171 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 172 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 173 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 174 *active_width = IB_WIDTH_1X; 175 *active_speed = IB_SPEED_SDR; 176 break; 177 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 178 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 179 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 180 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 181 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 182 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 183 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER_LR): 184 *active_width = IB_WIDTH_1X; 185 *active_speed = IB_SPEED_QDR; 186 break; 187 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 188 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 189 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 190 *active_width = IB_WIDTH_1X; 191 *active_speed = IB_SPEED_EDR; 192 break; 193 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 194 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 195 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 196 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4_ER4): 197 *active_width = IB_WIDTH_4X; 198 *active_speed = IB_SPEED_QDR; 199 break; 200 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 201 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 202 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 203 *active_width = IB_WIDTH_1X; 204 *active_speed = IB_SPEED_HDR; 205 break; 206 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 207 *active_width = IB_WIDTH_4X; 208 *active_speed = IB_SPEED_FDR; 209 break; 210 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 211 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 212 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 213 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 214 *active_width = IB_WIDTH_4X; 215 *active_speed = IB_SPEED_EDR; 216 break; 217 default: 218 *active_width = IB_WIDTH_4X; 219 *active_speed = IB_SPEED_QDR; 220 return -EINVAL; 221 } 222 223 return 0; 224 } 225 226 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed, 227 u8 *active_width) 228 { 229 switch (eth_proto_oper) { 230 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 231 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 232 *active_width = IB_WIDTH_1X; 233 *active_speed = IB_SPEED_SDR; 234 break; 235 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 236 *active_width = IB_WIDTH_1X; 237 *active_speed = IB_SPEED_DDR; 238 break; 239 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 240 *active_width = IB_WIDTH_1X; 241 *active_speed = IB_SPEED_QDR; 242 break; 243 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 244 *active_width = IB_WIDTH_4X; 245 *active_speed = IB_SPEED_QDR; 246 break; 247 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 248 *active_width = IB_WIDTH_1X; 249 *active_speed = IB_SPEED_EDR; 250 break; 251 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 252 *active_width = IB_WIDTH_2X; 253 *active_speed = IB_SPEED_EDR; 254 break; 255 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 256 *active_width = IB_WIDTH_1X; 257 *active_speed = IB_SPEED_HDR; 258 break; 259 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 260 *active_width = IB_WIDTH_4X; 261 *active_speed = IB_SPEED_EDR; 262 break; 263 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 264 *active_width = IB_WIDTH_2X; 265 *active_speed = IB_SPEED_HDR; 266 break; 267 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 268 *active_width = IB_WIDTH_4X; 269 *active_speed = IB_SPEED_HDR; 270 break; 271 default: 272 *active_width = IB_WIDTH_4X; 273 *active_speed = IB_SPEED_QDR; 274 return -EINVAL; 275 } 276 277 return 0; 278 } 279 280 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 281 struct ib_port_attr *props) 282 { 283 struct mlx5_ib_dev *dev = to_mdev(device); 284 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {}; 285 struct net_device *ndev; 286 enum ib_mtu ndev_ib_mtu; 287 u16 qkey_viol_cntr; 288 u32 eth_prot_oper; 289 bool ext; 290 int err; 291 292 memset(props, 0, sizeof(*props)); 293 294 /* Possible bad flows are checked before filling out props so in case 295 * of an error it will still be zeroed out. 296 */ 297 err = mlx5_query_port_ptys(dev->mdev, out, sizeof(out), MLX5_PTYS_EN, 298 port_num); 299 if (err) 300 return err; 301 302 ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet); 303 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 304 305 if (ext) 306 translate_eth_ext_proto_oper(eth_prot_oper, &props->active_speed, 307 &props->active_width); 308 else 309 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 310 &props->active_width); 311 312 props->port_cap_flags |= IB_PORT_CM_SUP; 313 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 314 315 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 316 roce_address_table_size); 317 props->max_mtu = IB_MTU_4096; 318 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 319 props->pkey_tbl_len = 1; 320 props->state = IB_PORT_DOWN; 321 props->phys_state = 3; 322 323 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr); 324 props->qkey_viol_cntr = qkey_viol_cntr; 325 326 ndev = mlx5_ib_get_netdev(device, port_num); 327 if (!ndev) 328 return 0; 329 330 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 331 props->state = IB_PORT_ACTIVE; 332 props->phys_state = 5; 333 } 334 335 ndev_ib_mtu = iboe_get_mtu(ndev->if_mtu); 336 337 dev_put(ndev); 338 339 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 340 return 0; 341 } 342 343 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid, 344 const struct ib_gid_attr *attr, 345 void *mlx5_addr) 346 { 347 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v) 348 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 349 source_l3_address); 350 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 351 source_mac_47_32); 352 u16 vlan_id; 353 354 if (!gid) 355 return; 356 ether_addr_copy(mlx5_addr_mac, IF_LLADDR(attr->ndev)); 357 358 vlan_id = rdma_vlan_dev_vlan_id(attr->ndev); 359 if (vlan_id != 0xffff) { 360 MLX5_SET_RA(mlx5_addr, vlan_valid, 1); 361 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_id); 362 } 363 364 switch (attr->gid_type) { 365 case IB_GID_TYPE_IB: 366 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1); 367 break; 368 case IB_GID_TYPE_ROCE_UDP_ENCAP: 369 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2); 370 break; 371 372 default: 373 WARN_ON(true); 374 } 375 376 if (attr->gid_type != IB_GID_TYPE_IB) { 377 if (ipv6_addr_v4mapped((void *)gid)) 378 MLX5_SET_RA(mlx5_addr, roce_l3_type, 379 MLX5_ROCE_L3_TYPE_IPV4); 380 else 381 MLX5_SET_RA(mlx5_addr, roce_l3_type, 382 MLX5_ROCE_L3_TYPE_IPV6); 383 } 384 385 if ((attr->gid_type == IB_GID_TYPE_IB) || 386 !ipv6_addr_v4mapped((void *)gid)) 387 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid)); 388 else 389 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4); 390 } 391 392 static int set_roce_addr(struct ib_device *device, u8 port_num, 393 unsigned int index, 394 const union ib_gid *gid, 395 const struct ib_gid_attr *attr) 396 { 397 struct mlx5_ib_dev *dev = to_mdev(device); 398 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0}; 399 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0}; 400 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address); 401 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num); 402 403 if (ll != IB_LINK_LAYER_ETHERNET) 404 return -EINVAL; 405 406 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr); 407 408 MLX5_SET(set_roce_address_in, in, roce_address_index, index); 409 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS); 410 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out)); 411 } 412 413 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, 414 unsigned int index, const union ib_gid *gid, 415 const struct ib_gid_attr *attr, 416 __always_unused void **context) 417 { 418 return set_roce_addr(device, port_num, index, gid, attr); 419 } 420 421 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, 422 unsigned int index, __always_unused void **context) 423 { 424 return set_roce_addr(device, port_num, index, NULL, NULL); 425 } 426 427 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 428 int index) 429 { 430 struct ib_gid_attr attr; 431 union ib_gid gid; 432 433 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) 434 return 0; 435 436 if (!attr.ndev) 437 return 0; 438 439 dev_put(attr.ndev); 440 441 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 442 return 0; 443 444 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 445 } 446 447 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, 448 int index, enum ib_gid_type *gid_type) 449 { 450 struct ib_gid_attr attr; 451 union ib_gid gid; 452 int ret; 453 454 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr); 455 if (ret) 456 return ret; 457 458 if (!attr.ndev) 459 return -ENODEV; 460 461 dev_put(attr.ndev); 462 463 *gid_type = attr.gid_type; 464 465 return 0; 466 } 467 468 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 469 { 470 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 471 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 472 return 0; 473 } 474 475 enum { 476 MLX5_VPORT_ACCESS_METHOD_MAD, 477 MLX5_VPORT_ACCESS_METHOD_HCA, 478 MLX5_VPORT_ACCESS_METHOD_NIC, 479 }; 480 481 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 482 { 483 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 484 return MLX5_VPORT_ACCESS_METHOD_MAD; 485 486 if (mlx5_ib_port_link_layer(ibdev, 1) == 487 IB_LINK_LAYER_ETHERNET) 488 return MLX5_VPORT_ACCESS_METHOD_NIC; 489 490 return MLX5_VPORT_ACCESS_METHOD_HCA; 491 } 492 493 static void get_atomic_caps(struct mlx5_ib_dev *dev, 494 struct ib_device_attr *props) 495 { 496 u8 tmp; 497 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 498 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 499 u8 atomic_req_8B_endianness_mode = 500 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode); 501 502 /* Check if HW supports 8 bytes standard atomic operations and capable 503 * of host endianness respond 504 */ 505 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 506 if (((atomic_operations & tmp) == tmp) && 507 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 508 (atomic_req_8B_endianness_mode)) { 509 props->atomic_cap = IB_ATOMIC_HCA; 510 } else { 511 props->atomic_cap = IB_ATOMIC_NONE; 512 } 513 } 514 515 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 516 __be64 *sys_image_guid) 517 { 518 struct mlx5_ib_dev *dev = to_mdev(ibdev); 519 struct mlx5_core_dev *mdev = dev->mdev; 520 u64 tmp; 521 int err; 522 523 switch (mlx5_get_vport_access_method(ibdev)) { 524 case MLX5_VPORT_ACCESS_METHOD_MAD: 525 return mlx5_query_mad_ifc_system_image_guid(ibdev, 526 sys_image_guid); 527 528 case MLX5_VPORT_ACCESS_METHOD_HCA: 529 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 530 break; 531 532 case MLX5_VPORT_ACCESS_METHOD_NIC: 533 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 534 break; 535 536 default: 537 return -EINVAL; 538 } 539 540 if (!err) 541 *sys_image_guid = cpu_to_be64(tmp); 542 543 return err; 544 545 } 546 547 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 548 u16 *max_pkeys) 549 { 550 struct mlx5_ib_dev *dev = to_mdev(ibdev); 551 struct mlx5_core_dev *mdev = dev->mdev; 552 553 switch (mlx5_get_vport_access_method(ibdev)) { 554 case MLX5_VPORT_ACCESS_METHOD_MAD: 555 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 556 557 case MLX5_VPORT_ACCESS_METHOD_HCA: 558 case MLX5_VPORT_ACCESS_METHOD_NIC: 559 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 560 pkey_table_size)); 561 return 0; 562 563 default: 564 return -EINVAL; 565 } 566 } 567 568 static int mlx5_query_vendor_id(struct ib_device *ibdev, 569 u32 *vendor_id) 570 { 571 struct mlx5_ib_dev *dev = to_mdev(ibdev); 572 573 switch (mlx5_get_vport_access_method(ibdev)) { 574 case MLX5_VPORT_ACCESS_METHOD_MAD: 575 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 576 577 case MLX5_VPORT_ACCESS_METHOD_HCA: 578 case MLX5_VPORT_ACCESS_METHOD_NIC: 579 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 580 581 default: 582 return -EINVAL; 583 } 584 } 585 586 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 587 __be64 *node_guid) 588 { 589 u64 tmp; 590 int err; 591 592 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 593 case MLX5_VPORT_ACCESS_METHOD_MAD: 594 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 595 596 case MLX5_VPORT_ACCESS_METHOD_HCA: 597 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 598 break; 599 600 case MLX5_VPORT_ACCESS_METHOD_NIC: 601 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 602 break; 603 604 default: 605 return -EINVAL; 606 } 607 608 if (!err) 609 *node_guid = cpu_to_be64(tmp); 610 611 return err; 612 } 613 614 struct mlx5_reg_node_desc { 615 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 616 }; 617 618 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 619 { 620 struct mlx5_reg_node_desc in; 621 622 if (mlx5_use_mad_ifc(dev)) 623 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 624 625 memset(&in, 0, sizeof(in)); 626 627 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 628 sizeof(struct mlx5_reg_node_desc), 629 MLX5_REG_NODE_DESC, 0, 0); 630 } 631 632 static int mlx5_ib_query_device(struct ib_device *ibdev, 633 struct ib_device_attr *props, 634 struct ib_udata *uhw) 635 { 636 struct mlx5_ib_dev *dev = to_mdev(ibdev); 637 struct mlx5_core_dev *mdev = dev->mdev; 638 int err = -ENOMEM; 639 int max_rq_sg; 640 int max_sq_sg; 641 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 642 struct mlx5_ib_query_device_resp resp = {}; 643 size_t resp_len; 644 u64 max_tso; 645 646 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 647 if (uhw->outlen && uhw->outlen < resp_len) 648 return -EINVAL; 649 else 650 resp.response_length = resp_len; 651 652 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 653 return -EINVAL; 654 655 memset(props, 0, sizeof(*props)); 656 err = mlx5_query_system_image_guid(ibdev, 657 &props->sys_image_guid); 658 if (err) 659 return err; 660 661 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 662 if (err) 663 return err; 664 665 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 666 if (err) 667 return err; 668 669 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 670 ((u32)fw_rev_min(dev->mdev) << 16) | 671 fw_rev_sub(dev->mdev); 672 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 673 IB_DEVICE_PORT_ACTIVE_EVENT | 674 IB_DEVICE_SYS_IMAGE_GUID | 675 IB_DEVICE_RC_RNR_NAK_GEN; 676 677 if (MLX5_CAP_GEN(mdev, pkv)) 678 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 679 if (MLX5_CAP_GEN(mdev, qkv)) 680 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 681 if (MLX5_CAP_GEN(mdev, apm)) 682 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 683 if (MLX5_CAP_GEN(mdev, xrc)) 684 props->device_cap_flags |= IB_DEVICE_XRC; 685 if (MLX5_CAP_GEN(mdev, imaicl)) { 686 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 687 IB_DEVICE_MEM_WINDOW_TYPE_2B; 688 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 689 /* We support 'Gappy' memory registration too */ 690 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 691 } 692 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 693 if (MLX5_CAP_GEN(mdev, sho)) { 694 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 695 /* At this stage no support for signature handover */ 696 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 697 IB_PROT_T10DIF_TYPE_2 | 698 IB_PROT_T10DIF_TYPE_3; 699 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 700 IB_GUARD_T10DIF_CSUM; 701 } 702 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 703 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 704 705 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) { 706 if (MLX5_CAP_ETH(mdev, csum_cap)) 707 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 708 709 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 710 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 711 if (max_tso) { 712 resp.tso_caps.max_tso = 1 << max_tso; 713 resp.tso_caps.supported_qpts |= 714 1 << IB_QPT_RAW_PACKET; 715 resp.response_length += sizeof(resp.tso_caps); 716 } 717 } 718 719 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 720 resp.rss_caps.rx_hash_function = 721 MLX5_RX_HASH_FUNC_TOEPLITZ; 722 resp.rss_caps.rx_hash_fields_mask = 723 MLX5_RX_HASH_SRC_IPV4 | 724 MLX5_RX_HASH_DST_IPV4 | 725 MLX5_RX_HASH_SRC_IPV6 | 726 MLX5_RX_HASH_DST_IPV6 | 727 MLX5_RX_HASH_SRC_PORT_TCP | 728 MLX5_RX_HASH_DST_PORT_TCP | 729 MLX5_RX_HASH_SRC_PORT_UDP | 730 MLX5_RX_HASH_DST_PORT_UDP; 731 resp.response_length += sizeof(resp.rss_caps); 732 } 733 } else { 734 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 735 resp.response_length += sizeof(resp.tso_caps); 736 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 737 resp.response_length += sizeof(resp.rss_caps); 738 } 739 740 if (MLX5_CAP_GEN(mdev, ipoib_ipoib_offloads)) { 741 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 742 props->device_cap_flags |= IB_DEVICE_UD_TSO; 743 } 744 745 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 746 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) 747 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 748 749 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 750 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 751 752 props->vendor_part_id = mdev->pdev->device; 753 props->hw_ver = mdev->pdev->revision; 754 755 props->max_mr_size = ~0ull; 756 props->page_size_cap = ~(min_page_size - 1); 757 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 758 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 759 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 760 sizeof(struct mlx5_wqe_data_seg); 761 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) - 762 sizeof(struct mlx5_wqe_ctrl_seg)) / 763 sizeof(struct mlx5_wqe_data_seg); 764 props->max_sge = min(max_rq_sg, max_sq_sg); 765 props->max_sge_rd = MLX5_MAX_SGE_RD; 766 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 767 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 768 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 769 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 770 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 771 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 772 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 773 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 774 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 775 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 776 props->max_srq_sge = max_rq_sg - 1; 777 props->max_fast_reg_page_list_len = 778 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 779 get_atomic_caps(dev, props); 780 props->masked_atomic_cap = IB_ATOMIC_NONE; 781 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 782 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 783 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 784 props->max_mcast_grp; 785 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 786 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 787 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 788 789 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 790 if (MLX5_CAP_GEN(mdev, pg)) 791 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 792 props->odp_caps = dev->odp_caps; 793 #endif 794 795 if (MLX5_CAP_GEN(mdev, cd)) 796 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 797 798 if (!mlx5_core_is_pf(mdev)) 799 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 800 801 if (mlx5_ib_port_link_layer(ibdev, 1) == 802 IB_LINK_LAYER_ETHERNET) { 803 props->rss_caps.max_rwq_indirection_tables = 804 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 805 props->rss_caps.max_rwq_indirection_table_size = 806 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 807 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 808 props->max_wq_type_rq = 809 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 810 } 811 812 if (uhw->outlen) { 813 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 814 815 if (err) 816 return err; 817 } 818 819 return 0; 820 } 821 822 enum mlx5_ib_width { 823 MLX5_IB_WIDTH_1X = 1 << 0, 824 MLX5_IB_WIDTH_2X = 1 << 1, 825 MLX5_IB_WIDTH_4X = 1 << 2, 826 MLX5_IB_WIDTH_8X = 1 << 3, 827 MLX5_IB_WIDTH_12X = 1 << 4 828 }; 829 830 static int translate_active_width(struct ib_device *ibdev, u8 active_width, 831 u8 *ib_width) 832 { 833 struct mlx5_ib_dev *dev = to_mdev(ibdev); 834 int err = 0; 835 836 if (active_width & MLX5_IB_WIDTH_1X) { 837 *ib_width = IB_WIDTH_1X; 838 } else if (active_width & MLX5_IB_WIDTH_2X) { 839 *ib_width = IB_WIDTH_2X; 840 } else if (active_width & MLX5_IB_WIDTH_4X) { 841 *ib_width = IB_WIDTH_4X; 842 } else if (active_width & MLX5_IB_WIDTH_8X) { 843 *ib_width = IB_WIDTH_8X; 844 } else if (active_width & MLX5_IB_WIDTH_12X) { 845 *ib_width = IB_WIDTH_12X; 846 } else { 847 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 848 (int)active_width); 849 err = -EINVAL; 850 } 851 852 return err; 853 } 854 855 enum ib_max_vl_num { 856 __IB_MAX_VL_0 = 1, 857 __IB_MAX_VL_0_1 = 2, 858 __IB_MAX_VL_0_3 = 3, 859 __IB_MAX_VL_0_7 = 4, 860 __IB_MAX_VL_0_14 = 5, 861 }; 862 863 enum mlx5_vl_hw_cap { 864 MLX5_VL_HW_0 = 1, 865 MLX5_VL_HW_0_1 = 2, 866 MLX5_VL_HW_0_2 = 3, 867 MLX5_VL_HW_0_3 = 4, 868 MLX5_VL_HW_0_4 = 5, 869 MLX5_VL_HW_0_5 = 6, 870 MLX5_VL_HW_0_6 = 7, 871 MLX5_VL_HW_0_7 = 8, 872 MLX5_VL_HW_0_14 = 15 873 }; 874 875 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 876 u8 *max_vl_num) 877 { 878 switch (vl_hw_cap) { 879 case MLX5_VL_HW_0: 880 *max_vl_num = __IB_MAX_VL_0; 881 break; 882 case MLX5_VL_HW_0_1: 883 *max_vl_num = __IB_MAX_VL_0_1; 884 break; 885 case MLX5_VL_HW_0_3: 886 *max_vl_num = __IB_MAX_VL_0_3; 887 break; 888 case MLX5_VL_HW_0_7: 889 *max_vl_num = __IB_MAX_VL_0_7; 890 break; 891 case MLX5_VL_HW_0_14: 892 *max_vl_num = __IB_MAX_VL_0_14; 893 break; 894 895 default: 896 return -EINVAL; 897 } 898 899 return 0; 900 } 901 902 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 903 struct ib_port_attr *props) 904 { 905 struct mlx5_ib_dev *dev = to_mdev(ibdev); 906 struct mlx5_core_dev *mdev = dev->mdev; 907 u32 *rep; 908 int replen = MLX5_ST_SZ_BYTES(query_hca_vport_context_out); 909 struct mlx5_ptys_reg *ptys; 910 struct mlx5_pmtu_reg *pmtu; 911 struct mlx5_pvlc_reg pvlc; 912 void *ctx; 913 int err; 914 915 rep = mlx5_vzalloc(replen); 916 ptys = kzalloc(sizeof(*ptys), GFP_KERNEL); 917 pmtu = kzalloc(sizeof(*pmtu), GFP_KERNEL); 918 if (!rep || !ptys || !pmtu) { 919 err = -ENOMEM; 920 goto out; 921 } 922 923 memset(props, 0, sizeof(*props)); 924 925 err = mlx5_query_hca_vport_context(mdev, port, 0, rep, replen); 926 if (err) 927 goto out; 928 929 ctx = MLX5_ADDR_OF(query_hca_vport_context_out, rep, hca_vport_context); 930 931 props->lid = MLX5_GET(hca_vport_context, ctx, lid); 932 props->lmc = MLX5_GET(hca_vport_context, ctx, lmc); 933 props->sm_lid = MLX5_GET(hca_vport_context, ctx, sm_lid); 934 props->sm_sl = MLX5_GET(hca_vport_context, ctx, sm_sl); 935 props->state = MLX5_GET(hca_vport_context, ctx, vport_state); 936 props->phys_state = MLX5_GET(hca_vport_context, ctx, 937 port_physical_state); 938 props->port_cap_flags = MLX5_GET(hca_vport_context, ctx, cap_mask1); 939 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 940 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 941 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 942 props->bad_pkey_cntr = MLX5_GET(hca_vport_context, ctx, 943 pkey_violation_counter); 944 props->qkey_viol_cntr = MLX5_GET(hca_vport_context, ctx, 945 qkey_violation_counter); 946 props->subnet_timeout = MLX5_GET(hca_vport_context, ctx, 947 subnet_timeout); 948 props->init_type_reply = MLX5_GET(hca_vport_context, ctx, 949 init_type_reply); 950 props->grh_required = MLX5_GET(hca_vport_context, ctx, grh_required); 951 952 ptys->proto_mask |= MLX5_PTYS_IB; 953 ptys->local_port = port; 954 err = mlx5_core_access_ptys(mdev, ptys, 0); 955 if (err) 956 goto out; 957 958 err = translate_active_width(ibdev, ptys->ib_link_width_oper, 959 &props->active_width); 960 if (err) 961 goto out; 962 963 props->active_speed = (u8)ptys->ib_proto_oper; 964 965 pmtu->local_port = port; 966 err = mlx5_core_access_pmtu(mdev, pmtu, 0); 967 if (err) 968 goto out; 969 970 props->max_mtu = pmtu->max_mtu; 971 props->active_mtu = pmtu->oper_mtu; 972 973 memset(&pvlc, 0, sizeof(pvlc)); 974 pvlc.local_port = port; 975 err = mlx5_core_access_pvlc(mdev, &pvlc, 0); 976 if (err) 977 goto out; 978 979 err = translate_max_vl_num(ibdev, pvlc.vl_hw_cap, 980 &props->max_vl_num); 981 out: 982 kvfree(rep); 983 kfree(ptys); 984 kfree(pmtu); 985 return err; 986 } 987 988 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 989 struct ib_port_attr *props) 990 { 991 switch (mlx5_get_vport_access_method(ibdev)) { 992 case MLX5_VPORT_ACCESS_METHOD_MAD: 993 return mlx5_query_mad_ifc_port(ibdev, port, props); 994 995 case MLX5_VPORT_ACCESS_METHOD_HCA: 996 return mlx5_query_hca_port(ibdev, port, props); 997 998 case MLX5_VPORT_ACCESS_METHOD_NIC: 999 return mlx5_query_port_roce(ibdev, port, props); 1000 1001 default: 1002 return -EINVAL; 1003 } 1004 } 1005 1006 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1007 union ib_gid *gid) 1008 { 1009 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1010 struct mlx5_core_dev *mdev = dev->mdev; 1011 1012 switch (mlx5_get_vport_access_method(ibdev)) { 1013 case MLX5_VPORT_ACCESS_METHOD_MAD: 1014 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1015 1016 case MLX5_VPORT_ACCESS_METHOD_HCA: 1017 return mlx5_query_hca_vport_gid(mdev, port, 0, index, gid); 1018 1019 default: 1020 return -EINVAL; 1021 } 1022 1023 } 1024 1025 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1026 u16 *pkey) 1027 { 1028 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1029 struct mlx5_core_dev *mdev = dev->mdev; 1030 1031 switch (mlx5_get_vport_access_method(ibdev)) { 1032 case MLX5_VPORT_ACCESS_METHOD_MAD: 1033 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1034 1035 case MLX5_VPORT_ACCESS_METHOD_HCA: 1036 case MLX5_VPORT_ACCESS_METHOD_NIC: 1037 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index, 1038 pkey); 1039 default: 1040 return -EINVAL; 1041 } 1042 } 1043 1044 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1045 struct ib_device_modify *props) 1046 { 1047 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1048 struct mlx5_reg_node_desc in; 1049 struct mlx5_reg_node_desc out; 1050 int err; 1051 1052 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1053 return -EOPNOTSUPP; 1054 1055 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1056 return 0; 1057 1058 /* 1059 * If possible, pass node desc to FW, so it can generate 1060 * a 144 trap. If cmd fails, just ignore. 1061 */ 1062 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1063 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1064 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1065 if (err) 1066 return err; 1067 1068 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1069 1070 return err; 1071 } 1072 1073 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1074 struct ib_port_modify *props) 1075 { 1076 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1077 struct ib_port_attr attr; 1078 u32 tmp; 1079 int err; 1080 1081 /* 1082 * CM layer calls ib_modify_port() regardless of the link 1083 * layer. For Ethernet ports, qkey violation and Port 1084 * capabilities are meaningless. 1085 */ 1086 if (mlx5_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_ETHERNET) 1087 return 0; 1088 1089 mutex_lock(&dev->cap_mask_mutex); 1090 1091 err = mlx5_ib_query_port(ibdev, port, &attr); 1092 if (err) 1093 goto out; 1094 1095 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1096 ~props->clr_port_cap_mask; 1097 1098 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1099 1100 out: 1101 mutex_unlock(&dev->cap_mask_mutex); 1102 return err; 1103 } 1104 1105 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 1106 struct ib_udata *udata) 1107 { 1108 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1109 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1110 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1111 struct mlx5_ib_ucontext *context; 1112 struct mlx5_uuar_info *uuari; 1113 struct mlx5_uar *uars; 1114 int gross_uuars; 1115 int num_uars; 1116 int ver; 1117 int uuarn; 1118 int err; 1119 int i; 1120 size_t reqlen; 1121 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1122 max_cqe_version); 1123 1124 if (!dev->ib_active) 1125 return ERR_PTR(-EAGAIN); 1126 1127 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr)) 1128 return ERR_PTR(-EINVAL); 1129 1130 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr); 1131 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1132 ver = 0; 1133 else if (reqlen >= min_req_v2) 1134 ver = 2; 1135 else 1136 return ERR_PTR(-EINVAL); 1137 1138 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req))); 1139 if (err) 1140 return ERR_PTR(err); 1141 1142 if (req.flags) 1143 return ERR_PTR(-EINVAL); 1144 1145 if (req.total_num_uuars > MLX5_MAX_UUARS) 1146 return ERR_PTR(-ENOMEM); 1147 1148 if (req.total_num_uuars == 0) 1149 return ERR_PTR(-EINVAL); 1150 1151 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1152 return ERR_PTR(-EOPNOTSUPP); 1153 1154 if (reqlen > sizeof(req) && 1155 !ib_is_udata_cleared(udata, sizeof(req), 1156 reqlen - sizeof(req))) 1157 return ERR_PTR(-EOPNOTSUPP); 1158 1159 req.total_num_uuars = ALIGN(req.total_num_uuars, 1160 MLX5_NON_FP_BF_REGS_PER_PAGE); 1161 if (req.num_low_latency_uuars > req.total_num_uuars - 1) 1162 return ERR_PTR(-EINVAL); 1163 1164 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE; 1165 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE; 1166 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1167 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1168 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1169 resp.cache_line_size = cache_line_size(); 1170 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1171 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1172 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1173 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1174 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1175 resp.cqe_version = min_t(__u8, 1176 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1177 req.max_cqe_version); 1178 resp.response_length = min(offsetof(typeof(resp), response_length) + 1179 sizeof(resp.response_length), udata->outlen); 1180 1181 context = kzalloc(sizeof(*context), GFP_KERNEL); 1182 if (!context) 1183 return ERR_PTR(-ENOMEM); 1184 1185 uuari = &context->uuari; 1186 mutex_init(&uuari->lock); 1187 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL); 1188 if (!uars) { 1189 err = -ENOMEM; 1190 goto out_ctx; 1191 } 1192 1193 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars), 1194 sizeof(*uuari->bitmap), 1195 GFP_KERNEL); 1196 if (!uuari->bitmap) { 1197 err = -ENOMEM; 1198 goto out_uar_ctx; 1199 } 1200 /* 1201 * clear all fast path uuars 1202 */ 1203 for (i = 0; i < gross_uuars; i++) { 1204 uuarn = i & 3; 1205 if (uuarn == 2 || uuarn == 3) 1206 set_bit(i, uuari->bitmap); 1207 } 1208 1209 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL); 1210 if (!uuari->count) { 1211 err = -ENOMEM; 1212 goto out_bitmap; 1213 } 1214 1215 for (i = 0; i < num_uars; i++) { 1216 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index); 1217 if (err) 1218 goto out_count; 1219 } 1220 1221 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1222 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 1223 #endif 1224 1225 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { 1226 err = mlx5_alloc_transport_domain(dev->mdev, 1227 &context->tdn); 1228 if (err) 1229 goto out_uars; 1230 } 1231 1232 INIT_LIST_HEAD(&context->vma_private_list); 1233 INIT_LIST_HEAD(&context->db_page_list); 1234 mutex_init(&context->db_page_mutex); 1235 1236 resp.tot_uuars = req.total_num_uuars; 1237 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports); 1238 1239 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1240 resp.response_length += sizeof(resp.cqe_version); 1241 1242 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1243 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1244 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1245 resp.response_length += sizeof(resp.cmds_supp_uhw); 1246 } 1247 1248 /* 1249 * We don't want to expose information from the PCI bar that is located 1250 * after 4096 bytes, so if the arch only supports larger pages, let's 1251 * pretend we don't support reading the HCA's core clock. This is also 1252 * forced by mmap function. 1253 */ 1254 if (PAGE_SIZE <= 4096 && 1255 field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1256 resp.comp_mask |= 1257 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1258 resp.hca_core_clock_offset = 1259 offsetof(struct mlx5_init_seg, internal_timer_h) % 1260 PAGE_SIZE; 1261 resp.response_length += sizeof(resp.hca_core_clock_offset) + 1262 sizeof(resp.reserved2); 1263 } 1264 1265 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1266 if (err) 1267 goto out_td; 1268 1269 uuari->ver = ver; 1270 uuari->num_low_latency_uuars = req.num_low_latency_uuars; 1271 uuari->uars = uars; 1272 uuari->num_uars = num_uars; 1273 context->cqe_version = resp.cqe_version; 1274 1275 return &context->ibucontext; 1276 1277 out_td: 1278 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1279 mlx5_dealloc_transport_domain(dev->mdev, context->tdn); 1280 1281 out_uars: 1282 for (i--; i >= 0; i--) 1283 mlx5_cmd_free_uar(dev->mdev, uars[i].index); 1284 out_count: 1285 kfree(uuari->count); 1286 1287 out_bitmap: 1288 kfree(uuari->bitmap); 1289 1290 out_uar_ctx: 1291 kfree(uars); 1292 1293 out_ctx: 1294 kfree(context); 1295 return ERR_PTR(err); 1296 } 1297 1298 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1299 { 1300 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1301 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1302 struct mlx5_uuar_info *uuari = &context->uuari; 1303 int i; 1304 1305 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1306 mlx5_dealloc_transport_domain(dev->mdev, context->tdn); 1307 1308 for (i = 0; i < uuari->num_uars; i++) { 1309 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index)) 1310 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index); 1311 } 1312 1313 kfree(uuari->count); 1314 kfree(uuari->bitmap); 1315 kfree(uuari->uars); 1316 kfree(context); 1317 1318 return 0; 1319 } 1320 1321 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index) 1322 { 1323 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index; 1324 } 1325 1326 static int get_command(unsigned long offset) 1327 { 1328 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1329 } 1330 1331 static int get_arg(unsigned long offset) 1332 { 1333 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1334 } 1335 1336 static int get_index(unsigned long offset) 1337 { 1338 return get_arg(offset); 1339 } 1340 1341 static void mlx5_ib_vma_open(struct vm_area_struct *area) 1342 { 1343 /* vma_open is called when a new VMA is created on top of our VMA. This 1344 * is done through either mremap flow or split_vma (usually due to 1345 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA, 1346 * as this VMA is strongly hardware related. Therefore we set the 1347 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1348 * calling us again and trying to do incorrect actions. We assume that 1349 * the original VMA size is exactly a single page, and therefore all 1350 * "splitting" operation will not happen to it. 1351 */ 1352 area->vm_ops = NULL; 1353 } 1354 1355 static void mlx5_ib_vma_close(struct vm_area_struct *area) 1356 { 1357 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data; 1358 1359 /* It's guaranteed that all VMAs opened on a FD are closed before the 1360 * file itself is closed, therefore no sync is needed with the regular 1361 * closing flow. (e.g. mlx5 ib_dealloc_ucontext) 1362 * However need a sync with accessing the vma as part of 1363 * mlx5_ib_disassociate_ucontext. 1364 * The close operation is usually called under mm->mmap_sem except when 1365 * process is exiting. 1366 * The exiting case is handled explicitly as part of 1367 * mlx5_ib_disassociate_ucontext. 1368 */ 1369 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data; 1370 1371 /* setting the vma context pointer to null in the mlx5_ib driver's 1372 * private data, to protect a race condition in 1373 * mlx5_ib_disassociate_ucontext(). 1374 */ 1375 mlx5_ib_vma_priv_data->vma = NULL; 1376 list_del(&mlx5_ib_vma_priv_data->list); 1377 kfree(mlx5_ib_vma_priv_data); 1378 } 1379 1380 static const struct vm_operations_struct mlx5_ib_vm_ops = { 1381 .open = mlx5_ib_vma_open, 1382 .close = mlx5_ib_vma_close 1383 }; 1384 1385 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma, 1386 struct mlx5_ib_ucontext *ctx) 1387 { 1388 struct mlx5_ib_vma_private_data *vma_prv; 1389 struct list_head *vma_head = &ctx->vma_private_list; 1390 1391 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL); 1392 if (!vma_prv) 1393 return -ENOMEM; 1394 1395 vma_prv->vma = vma; 1396 vma->vm_private_data = vma_prv; 1397 vma->vm_ops = &mlx5_ib_vm_ops; 1398 1399 list_add(&vma_prv->list, vma_head); 1400 1401 return 0; 1402 } 1403 1404 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1405 { 1406 int ret; 1407 struct vm_area_struct *vma; 1408 struct mlx5_ib_vma_private_data *vma_private, *n; 1409 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1410 struct task_struct *owning_process = NULL; 1411 struct mm_struct *owning_mm = NULL; 1412 1413 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID); 1414 if (!owning_process) 1415 return; 1416 1417 owning_mm = get_task_mm(owning_process); 1418 if (!owning_mm) { 1419 pr_info("no mm, disassociate ucontext is pending task termination\n"); 1420 while (1) { 1421 put_task_struct(owning_process); 1422 usleep_range(1000, 2000); 1423 owning_process = get_pid_task(ibcontext->tgid, 1424 PIDTYPE_PID); 1425 if (!owning_process || owning_process->task_thread-> 1426 td_proc->p_state == PRS_ZOMBIE) { 1427 pr_info("disassociate ucontext done, task was terminated\n"); 1428 /* in case task was dead need to release the 1429 * task struct. 1430 */ 1431 if (owning_process) 1432 put_task_struct(owning_process); 1433 return; 1434 } 1435 } 1436 } 1437 1438 /* need to protect from a race on closing the vma as part of 1439 * mlx5_ib_vma_close. 1440 */ 1441 down_write(&owning_mm->mmap_sem); 1442 list_for_each_entry_safe(vma_private, n, &context->vma_private_list, 1443 list) { 1444 vma = vma_private->vma; 1445 ret = zap_vma_ptes(vma, vma->vm_start, 1446 PAGE_SIZE); 1447 if (ret == -ENOTSUP) { 1448 if (bootverbose) 1449 WARN_ONCE( 1450 "%s: zap_vma_ptes not implemented for unmanaged mappings", __func__); 1451 } else { 1452 WARN(ret, "%s: zap_vma_ptes failed, error %d", 1453 __func__, -ret); 1454 } 1455 /* context going to be destroyed, should 1456 * not access ops any more. 1457 */ 1458 /* XXXKIB vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE); */ 1459 vma->vm_ops = NULL; 1460 list_del(&vma_private->list); 1461 kfree(vma_private); 1462 } 1463 up_write(&owning_mm->mmap_sem); 1464 mmput(owning_mm); 1465 put_task_struct(owning_process); 1466 } 1467 1468 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1469 { 1470 switch (cmd) { 1471 case MLX5_IB_MMAP_WC_PAGE: 1472 return "WC"; 1473 case MLX5_IB_MMAP_REGULAR_PAGE: 1474 return "best effort WC"; 1475 case MLX5_IB_MMAP_NC_PAGE: 1476 return "NC"; 1477 default: 1478 return NULL; 1479 } 1480 } 1481 1482 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 1483 struct vm_area_struct *vma, 1484 struct mlx5_ib_ucontext *context) 1485 { 1486 struct mlx5_uuar_info *uuari = &context->uuari; 1487 int err; 1488 unsigned long idx; 1489 phys_addr_t pfn, pa; 1490 pgprot_t prot; 1491 1492 switch (cmd) { 1493 case MLX5_IB_MMAP_WC_PAGE: 1494 /* Some architectures don't support WC memory */ 1495 #if defined(CONFIG_X86) 1496 if (!pat_enabled()) 1497 return -EPERM; 1498 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 1499 return -EPERM; 1500 #endif 1501 /* fall through */ 1502 case MLX5_IB_MMAP_REGULAR_PAGE: 1503 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 1504 prot = pgprot_writecombine(vma->vm_page_prot); 1505 break; 1506 case MLX5_IB_MMAP_NC_PAGE: 1507 prot = pgprot_noncached(vma->vm_page_prot); 1508 break; 1509 default: 1510 return -EINVAL; 1511 } 1512 1513 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1514 return -EINVAL; 1515 1516 idx = get_index(vma->vm_pgoff); 1517 if (idx >= uuari->num_uars) 1518 return -EINVAL; 1519 1520 pfn = uar_index2pfn(dev, uuari->uars[idx].index); 1521 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 1522 1523 vma->vm_page_prot = prot; 1524 err = io_remap_pfn_range(vma, vma->vm_start, pfn, 1525 PAGE_SIZE, vma->vm_page_prot); 1526 if (err) { 1527 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%llx, pfn=%pa, mmap_cmd=%s\n", 1528 err, (unsigned long long)vma->vm_start, &pfn, mmap_cmd2str(cmd)); 1529 return -EAGAIN; 1530 } 1531 1532 pa = pfn << PAGE_SHIFT; 1533 mlx5_ib_dbg(dev, "mapped %s at 0x%llx, PA %pa\n", mmap_cmd2str(cmd), 1534 (unsigned long long)vma->vm_start, &pa); 1535 1536 return mlx5_ib_set_vma_data(vma, context); 1537 } 1538 1539 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 1540 { 1541 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1542 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1543 unsigned long command; 1544 phys_addr_t pfn; 1545 1546 command = get_command(vma->vm_pgoff); 1547 switch (command) { 1548 case MLX5_IB_MMAP_WC_PAGE: 1549 case MLX5_IB_MMAP_NC_PAGE: 1550 case MLX5_IB_MMAP_REGULAR_PAGE: 1551 return uar_mmap(dev, command, vma, context); 1552 1553 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 1554 return -ENOSYS; 1555 1556 case MLX5_IB_MMAP_CORE_CLOCK: 1557 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1558 return -EINVAL; 1559 1560 if (vma->vm_flags & VM_WRITE) 1561 return -EPERM; 1562 1563 /* Don't expose to user-space information it shouldn't have */ 1564 if (PAGE_SIZE > 4096) 1565 return -EOPNOTSUPP; 1566 1567 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1568 pfn = (dev->mdev->iseg_base + 1569 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 1570 PAGE_SHIFT; 1571 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 1572 PAGE_SIZE, vma->vm_page_prot)) 1573 return -EAGAIN; 1574 1575 mlx5_ib_dbg(dev, "mapped internal timer at 0x%llx, PA 0x%llx\n", 1576 (unsigned long long)vma->vm_start, 1577 (unsigned long long)pfn << PAGE_SHIFT); 1578 break; 1579 1580 default: 1581 return -EINVAL; 1582 } 1583 1584 return 0; 1585 } 1586 1587 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 1588 struct ib_ucontext *context, 1589 struct ib_udata *udata) 1590 { 1591 struct mlx5_ib_alloc_pd_resp resp; 1592 struct mlx5_ib_pd *pd; 1593 int err; 1594 1595 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 1596 if (!pd) 1597 return ERR_PTR(-ENOMEM); 1598 1599 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 1600 if (err) { 1601 kfree(pd); 1602 return ERR_PTR(err); 1603 } 1604 1605 if (context) { 1606 resp.pdn = pd->pdn; 1607 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 1608 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 1609 kfree(pd); 1610 return ERR_PTR(-EFAULT); 1611 } 1612 } 1613 1614 return &pd->ibpd; 1615 } 1616 1617 static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 1618 { 1619 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 1620 struct mlx5_ib_pd *mpd = to_mpd(pd); 1621 1622 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 1623 kfree(mpd); 1624 1625 return 0; 1626 } 1627 1628 enum { 1629 MATCH_CRITERIA_ENABLE_OUTER_BIT, 1630 MATCH_CRITERIA_ENABLE_MISC_BIT, 1631 MATCH_CRITERIA_ENABLE_INNER_BIT 1632 }; 1633 1634 #define HEADER_IS_ZERO(match_criteria, headers) \ 1635 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 1636 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 1637 1638 static u8 get_match_criteria_enable(u32 *match_criteria) 1639 { 1640 u8 match_criteria_enable; 1641 1642 match_criteria_enable = 1643 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 1644 MATCH_CRITERIA_ENABLE_OUTER_BIT; 1645 match_criteria_enable |= 1646 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 1647 MATCH_CRITERIA_ENABLE_MISC_BIT; 1648 match_criteria_enable |= 1649 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 1650 MATCH_CRITERIA_ENABLE_INNER_BIT; 1651 1652 return match_criteria_enable; 1653 } 1654 1655 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 1656 { 1657 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 1658 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 1659 } 1660 1661 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 1662 { 1663 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 1664 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 1665 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 1666 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 1667 } 1668 1669 #define LAST_ETH_FIELD vlan_tag 1670 #define LAST_IB_FIELD sl 1671 #define LAST_IPV4_FIELD tos 1672 #define LAST_IPV6_FIELD traffic_class 1673 #define LAST_TCP_UDP_FIELD src_port 1674 1675 /* Field is the last supported field */ 1676 #define FIELDS_NOT_SUPPORTED(filter, field)\ 1677 memchr_inv((void *)&filter.field +\ 1678 sizeof(filter.field), 0,\ 1679 sizeof(filter) -\ 1680 offsetof(typeof(filter), field) -\ 1681 sizeof(filter.field)) 1682 1683 static int parse_flow_attr(u32 *match_c, u32 *match_v, 1684 const union ib_flow_spec *ib_spec) 1685 { 1686 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1687 outer_headers); 1688 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1689 outer_headers); 1690 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 1691 misc_parameters); 1692 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 1693 misc_parameters); 1694 1695 switch (ib_spec->type) { 1696 case IB_FLOW_SPEC_ETH: 1697 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1698 return -ENOTSUPP; 1699 1700 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1701 dmac_47_16), 1702 ib_spec->eth.mask.dst_mac); 1703 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1704 dmac_47_16), 1705 ib_spec->eth.val.dst_mac); 1706 1707 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1708 smac_47_16), 1709 ib_spec->eth.mask.src_mac); 1710 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1711 smac_47_16), 1712 ib_spec->eth.val.src_mac); 1713 1714 if (ib_spec->eth.mask.vlan_tag) { 1715 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1716 cvlan_tag, 1); 1717 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1718 cvlan_tag, 1); 1719 1720 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1721 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 1722 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1723 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 1724 1725 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1726 first_cfi, 1727 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 1728 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1729 first_cfi, 1730 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 1731 1732 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1733 first_prio, 1734 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 1735 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1736 first_prio, 1737 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 1738 } 1739 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1740 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 1741 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1742 ethertype, ntohs(ib_spec->eth.val.ether_type)); 1743 break; 1744 case IB_FLOW_SPEC_IPV4: 1745 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 1746 return -ENOTSUPP; 1747 1748 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1749 ethertype, 0xffff); 1750 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1751 ethertype, ETH_P_IP); 1752 1753 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1754 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1755 &ib_spec->ipv4.mask.src_ip, 1756 sizeof(ib_spec->ipv4.mask.src_ip)); 1757 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1758 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1759 &ib_spec->ipv4.val.src_ip, 1760 sizeof(ib_spec->ipv4.val.src_ip)); 1761 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1762 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1763 &ib_spec->ipv4.mask.dst_ip, 1764 sizeof(ib_spec->ipv4.mask.dst_ip)); 1765 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1766 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1767 &ib_spec->ipv4.val.dst_ip, 1768 sizeof(ib_spec->ipv4.val.dst_ip)); 1769 1770 set_tos(outer_headers_c, outer_headers_v, 1771 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 1772 1773 set_proto(outer_headers_c, outer_headers_v, 1774 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 1775 break; 1776 case IB_FLOW_SPEC_IPV6: 1777 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 1778 return -ENOTSUPP; 1779 1780 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1781 ethertype, 0xffff); 1782 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1783 ethertype, IPPROTO_IPV6); 1784 1785 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1786 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1787 &ib_spec->ipv6.mask.src_ip, 1788 sizeof(ib_spec->ipv6.mask.src_ip)); 1789 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1790 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1791 &ib_spec->ipv6.val.src_ip, 1792 sizeof(ib_spec->ipv6.val.src_ip)); 1793 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1794 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1795 &ib_spec->ipv6.mask.dst_ip, 1796 sizeof(ib_spec->ipv6.mask.dst_ip)); 1797 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1798 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1799 &ib_spec->ipv6.val.dst_ip, 1800 sizeof(ib_spec->ipv6.val.dst_ip)); 1801 1802 set_tos(outer_headers_c, outer_headers_v, 1803 ib_spec->ipv6.mask.traffic_class, 1804 ib_spec->ipv6.val.traffic_class); 1805 1806 set_proto(outer_headers_c, outer_headers_v, 1807 ib_spec->ipv6.mask.next_hdr, 1808 ib_spec->ipv6.val.next_hdr); 1809 1810 MLX5_SET(fte_match_set_misc, misc_params_c, 1811 outer_ipv6_flow_label, 1812 ntohl(ib_spec->ipv6.mask.flow_label)); 1813 MLX5_SET(fte_match_set_misc, misc_params_v, 1814 outer_ipv6_flow_label, 1815 ntohl(ib_spec->ipv6.val.flow_label)); 1816 break; 1817 case IB_FLOW_SPEC_TCP: 1818 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 1819 LAST_TCP_UDP_FIELD)) 1820 return -ENOTSUPP; 1821 1822 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1823 0xff); 1824 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1825 IPPROTO_TCP); 1826 1827 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport, 1828 ntohs(ib_spec->tcp_udp.mask.src_port)); 1829 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport, 1830 ntohs(ib_spec->tcp_udp.val.src_port)); 1831 1832 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport, 1833 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1834 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport, 1835 ntohs(ib_spec->tcp_udp.val.dst_port)); 1836 break; 1837 case IB_FLOW_SPEC_UDP: 1838 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 1839 LAST_TCP_UDP_FIELD)) 1840 return -ENOTSUPP; 1841 1842 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1843 0xff); 1844 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1845 IPPROTO_UDP); 1846 1847 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport, 1848 ntohs(ib_spec->tcp_udp.mask.src_port)); 1849 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport, 1850 ntohs(ib_spec->tcp_udp.val.src_port)); 1851 1852 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport, 1853 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1854 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport, 1855 ntohs(ib_spec->tcp_udp.val.dst_port)); 1856 break; 1857 default: 1858 return -EINVAL; 1859 } 1860 1861 return 0; 1862 } 1863 1864 /* If a flow could catch both multicast and unicast packets, 1865 * it won't fall into the multicast flow steering table and this rule 1866 * could steal other multicast packets. 1867 */ 1868 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr) 1869 { 1870 struct ib_flow_spec_eth *eth_spec; 1871 1872 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 1873 ib_attr->size < sizeof(struct ib_flow_attr) + 1874 sizeof(struct ib_flow_spec_eth) || 1875 ib_attr->num_of_specs < 1) 1876 return false; 1877 1878 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1); 1879 if (eth_spec->type != IB_FLOW_SPEC_ETH || 1880 eth_spec->size != sizeof(*eth_spec)) 1881 return false; 1882 1883 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 1884 is_multicast_ether_addr(eth_spec->val.dst_mac); 1885 } 1886 1887 static bool is_valid_attr(const struct ib_flow_attr *flow_attr) 1888 { 1889 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 1890 bool has_ipv4_spec = false; 1891 bool eth_type_ipv4 = true; 1892 unsigned int spec_index; 1893 1894 /* Validate that ethertype is correct */ 1895 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 1896 if (ib_spec->type == IB_FLOW_SPEC_ETH && 1897 ib_spec->eth.mask.ether_type) { 1898 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) && 1899 ib_spec->eth.val.ether_type == htons(ETH_P_IP))) 1900 eth_type_ipv4 = false; 1901 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) { 1902 has_ipv4_spec = true; 1903 } 1904 ib_spec = (void *)ib_spec + ib_spec->size; 1905 } 1906 return !has_ipv4_spec || eth_type_ipv4; 1907 } 1908 1909 static void put_flow_table(struct mlx5_ib_dev *dev, 1910 struct mlx5_ib_flow_prio *prio, bool ft_added) 1911 { 1912 prio->refcount -= !!ft_added; 1913 if (!prio->refcount) { 1914 mlx5_destroy_flow_table(prio->flow_table); 1915 prio->flow_table = NULL; 1916 } 1917 } 1918 1919 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 1920 { 1921 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 1922 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 1923 struct mlx5_ib_flow_handler, 1924 ibflow); 1925 struct mlx5_ib_flow_handler *iter, *tmp; 1926 1927 mutex_lock(&dev->flow_db.lock); 1928 1929 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 1930 mlx5_del_flow_rule(iter->rule); 1931 put_flow_table(dev, iter->prio, true); 1932 list_del(&iter->list); 1933 kfree(iter); 1934 } 1935 1936 mlx5_del_flow_rule(handler->rule); 1937 put_flow_table(dev, handler->prio, true); 1938 mutex_unlock(&dev->flow_db.lock); 1939 1940 kfree(handler); 1941 1942 return 0; 1943 } 1944 1945 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 1946 { 1947 priority *= 2; 1948 if (!dont_trap) 1949 priority++; 1950 return priority; 1951 } 1952 1953 enum flow_table_type { 1954 MLX5_IB_FT_RX, 1955 MLX5_IB_FT_TX 1956 }; 1957 1958 #define MLX5_FS_MAX_TYPES 10 1959 #define MLX5_FS_MAX_ENTRIES 32000UL 1960 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 1961 struct ib_flow_attr *flow_attr, 1962 enum flow_table_type ft_type) 1963 { 1964 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 1965 struct mlx5_flow_namespace *ns = NULL; 1966 struct mlx5_ib_flow_prio *prio; 1967 struct mlx5_flow_table *ft; 1968 int num_entries; 1969 int num_groups; 1970 int priority; 1971 int err = 0; 1972 1973 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1974 if (flow_is_multicast_only(flow_attr) && 1975 !dont_trap) 1976 priority = MLX5_IB_FLOW_MCAST_PRIO; 1977 else 1978 priority = ib_prio_to_core_prio(flow_attr->priority, 1979 dont_trap); 1980 ns = mlx5_get_flow_namespace(dev->mdev, 1981 MLX5_FLOW_NAMESPACE_BYPASS); 1982 num_entries = MLX5_FS_MAX_ENTRIES; 1983 num_groups = MLX5_FS_MAX_TYPES; 1984 prio = &dev->flow_db.prios[priority]; 1985 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 1986 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 1987 ns = mlx5_get_flow_namespace(dev->mdev, 1988 MLX5_FLOW_NAMESPACE_LEFTOVERS); 1989 build_leftovers_ft_param("bypass", &priority, 1990 &num_entries, 1991 &num_groups); 1992 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 1993 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 1994 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 1995 allow_sniffer_and_nic_rx_shared_tir)) 1996 return ERR_PTR(-ENOTSUPP); 1997 1998 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 1999 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 2000 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 2001 2002 prio = &dev->flow_db.sniffer[ft_type]; 2003 priority = 0; 2004 num_entries = 1; 2005 num_groups = 1; 2006 } 2007 2008 if (!ns) 2009 return ERR_PTR(-ENOTSUPP); 2010 2011 ft = prio->flow_table; 2012 if (!ft) { 2013 ft = mlx5_create_auto_grouped_flow_table(ns, priority, "bypass", 2014 num_entries, 2015 num_groups); 2016 2017 if (!IS_ERR(ft)) { 2018 prio->refcount = 0; 2019 prio->flow_table = ft; 2020 } else { 2021 err = PTR_ERR(ft); 2022 } 2023 } 2024 2025 return err ? ERR_PTR(err) : prio; 2026 } 2027 2028 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 2029 struct mlx5_ib_flow_prio *ft_prio, 2030 const struct ib_flow_attr *flow_attr, 2031 struct mlx5_flow_destination *dst) 2032 { 2033 struct mlx5_flow_table *ft = ft_prio->flow_table; 2034 struct mlx5_ib_flow_handler *handler; 2035 struct mlx5_flow_spec *spec; 2036 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 2037 unsigned int spec_index; 2038 u32 action; 2039 int err = 0; 2040 2041 if (!is_valid_attr(flow_attr)) 2042 return ERR_PTR(-EINVAL); 2043 2044 spec = mlx5_vzalloc(sizeof(*spec)); 2045 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 2046 if (!handler || !spec) { 2047 err = -ENOMEM; 2048 goto free; 2049 } 2050 2051 INIT_LIST_HEAD(&handler->list); 2052 2053 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2054 err = parse_flow_attr(spec->match_criteria, 2055 spec->match_value, ib_flow); 2056 if (err < 0) 2057 goto free; 2058 2059 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 2060 } 2061 2062 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 2063 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 2064 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 2065 handler->rule = mlx5_add_flow_rule(ft, spec->match_criteria_enable, 2066 spec->match_criteria, 2067 spec->match_value, 2068 action, 2069 MLX5_FS_DEFAULT_FLOW_TAG, 2070 dst); 2071 2072 if (IS_ERR(handler->rule)) { 2073 err = PTR_ERR(handler->rule); 2074 goto free; 2075 } 2076 2077 ft_prio->refcount++; 2078 handler->prio = ft_prio; 2079 2080 ft_prio->flow_table = ft; 2081 free: 2082 if (err) 2083 kfree(handler); 2084 kvfree(spec); 2085 return err ? ERR_PTR(err) : handler; 2086 } 2087 2088 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 2089 struct mlx5_ib_flow_prio *ft_prio, 2090 struct ib_flow_attr *flow_attr, 2091 struct mlx5_flow_destination *dst) 2092 { 2093 struct mlx5_ib_flow_handler *handler_dst = NULL; 2094 struct mlx5_ib_flow_handler *handler = NULL; 2095 2096 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 2097 if (!IS_ERR(handler)) { 2098 handler_dst = create_flow_rule(dev, ft_prio, 2099 flow_attr, dst); 2100 if (IS_ERR(handler_dst)) { 2101 mlx5_del_flow_rule(handler->rule); 2102 ft_prio->refcount--; 2103 kfree(handler); 2104 handler = handler_dst; 2105 } else { 2106 list_add(&handler_dst->list, &handler->list); 2107 } 2108 } 2109 2110 return handler; 2111 } 2112 enum { 2113 LEFTOVERS_MC, 2114 LEFTOVERS_UC, 2115 }; 2116 2117 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 2118 struct mlx5_ib_flow_prio *ft_prio, 2119 struct ib_flow_attr *flow_attr, 2120 struct mlx5_flow_destination *dst) 2121 { 2122 struct mlx5_ib_flow_handler *handler_ucast = NULL; 2123 struct mlx5_ib_flow_handler *handler = NULL; 2124 2125 static struct { 2126 struct ib_flow_attr flow_attr; 2127 struct ib_flow_spec_eth eth_flow; 2128 } leftovers_specs[] = { 2129 [LEFTOVERS_MC] = { 2130 .flow_attr = { 2131 .num_of_specs = 1, 2132 .size = sizeof(leftovers_specs[0]) 2133 }, 2134 .eth_flow = { 2135 .type = IB_FLOW_SPEC_ETH, 2136 .size = sizeof(struct ib_flow_spec_eth), 2137 .mask = {.dst_mac = {0x1} }, 2138 .val = {.dst_mac = {0x1} } 2139 } 2140 }, 2141 [LEFTOVERS_UC] = { 2142 .flow_attr = { 2143 .num_of_specs = 1, 2144 .size = sizeof(leftovers_specs[0]) 2145 }, 2146 .eth_flow = { 2147 .type = IB_FLOW_SPEC_ETH, 2148 .size = sizeof(struct ib_flow_spec_eth), 2149 .mask = {.dst_mac = {0x1} }, 2150 .val = {.dst_mac = {} } 2151 } 2152 } 2153 }; 2154 2155 handler = create_flow_rule(dev, ft_prio, 2156 &leftovers_specs[LEFTOVERS_MC].flow_attr, 2157 dst); 2158 if (!IS_ERR(handler) && 2159 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 2160 handler_ucast = create_flow_rule(dev, ft_prio, 2161 &leftovers_specs[LEFTOVERS_UC].flow_attr, 2162 dst); 2163 if (IS_ERR(handler_ucast)) { 2164 mlx5_del_flow_rule(handler->rule); 2165 ft_prio->refcount--; 2166 kfree(handler); 2167 handler = handler_ucast; 2168 } else { 2169 list_add(&handler_ucast->list, &handler->list); 2170 } 2171 } 2172 2173 return handler; 2174 } 2175 2176 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 2177 struct mlx5_ib_flow_prio *ft_rx, 2178 struct mlx5_ib_flow_prio *ft_tx, 2179 struct mlx5_flow_destination *dst) 2180 { 2181 struct mlx5_ib_flow_handler *handler_rx; 2182 struct mlx5_ib_flow_handler *handler_tx; 2183 int err; 2184 static const struct ib_flow_attr flow_attr = { 2185 .num_of_specs = 0, 2186 .size = sizeof(flow_attr) 2187 }; 2188 2189 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 2190 if (IS_ERR(handler_rx)) { 2191 err = PTR_ERR(handler_rx); 2192 goto err; 2193 } 2194 2195 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 2196 if (IS_ERR(handler_tx)) { 2197 err = PTR_ERR(handler_tx); 2198 goto err_tx; 2199 } 2200 2201 list_add(&handler_tx->list, &handler_rx->list); 2202 2203 return handler_rx; 2204 2205 err_tx: 2206 mlx5_del_flow_rule(handler_rx->rule); 2207 ft_rx->refcount--; 2208 kfree(handler_rx); 2209 err: 2210 return ERR_PTR(err); 2211 } 2212 2213 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 2214 struct ib_flow_attr *flow_attr, 2215 int domain) 2216 { 2217 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2218 struct mlx5_ib_qp *mqp = to_mqp(qp); 2219 struct mlx5_ib_flow_handler *handler = NULL; 2220 struct mlx5_flow_destination *dst = NULL; 2221 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 2222 struct mlx5_ib_flow_prio *ft_prio; 2223 int err; 2224 2225 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) 2226 return ERR_PTR(-ENOSPC); 2227 2228 if (domain != IB_FLOW_DOMAIN_USER || 2229 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) || 2230 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)) 2231 return ERR_PTR(-EINVAL); 2232 2233 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 2234 if (!dst) 2235 return ERR_PTR(-ENOMEM); 2236 2237 mutex_lock(&dev->flow_db.lock); 2238 2239 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX); 2240 if (IS_ERR(ft_prio)) { 2241 err = PTR_ERR(ft_prio); 2242 goto unlock; 2243 } 2244 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2245 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 2246 if (IS_ERR(ft_prio_tx)) { 2247 err = PTR_ERR(ft_prio_tx); 2248 ft_prio_tx = NULL; 2249 goto destroy_ft; 2250 } 2251 } 2252 2253 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 2254 if (mqp->flags & MLX5_IB_QP_RSS) 2255 dst->tir_num = mqp->rss_qp.tirn; 2256 else 2257 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 2258 2259 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2260 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 2261 handler = create_dont_trap_rule(dev, ft_prio, 2262 flow_attr, dst); 2263 } else { 2264 handler = create_flow_rule(dev, ft_prio, flow_attr, 2265 dst); 2266 } 2267 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2268 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2269 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 2270 dst); 2271 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2272 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 2273 } else { 2274 err = -EINVAL; 2275 goto destroy_ft; 2276 } 2277 2278 if (IS_ERR(handler)) { 2279 err = PTR_ERR(handler); 2280 handler = NULL; 2281 goto destroy_ft; 2282 } 2283 2284 mutex_unlock(&dev->flow_db.lock); 2285 kfree(dst); 2286 2287 return &handler->ibflow; 2288 2289 destroy_ft: 2290 put_flow_table(dev, ft_prio, false); 2291 if (ft_prio_tx) 2292 put_flow_table(dev, ft_prio_tx, false); 2293 unlock: 2294 mutex_unlock(&dev->flow_db.lock); 2295 kfree(dst); 2296 kfree(handler); 2297 return ERR_PTR(err); 2298 } 2299 2300 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2301 { 2302 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2303 int err; 2304 2305 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 2306 if (err) 2307 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2308 ibqp->qp_num, gid->raw); 2309 2310 return err; 2311 } 2312 2313 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2314 { 2315 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2316 int err; 2317 2318 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 2319 if (err) 2320 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2321 ibqp->qp_num, gid->raw); 2322 2323 return err; 2324 } 2325 2326 static int init_node_data(struct mlx5_ib_dev *dev) 2327 { 2328 int err; 2329 2330 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2331 if (err) 2332 return err; 2333 2334 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2335 } 2336 2337 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 2338 char *buf) 2339 { 2340 struct mlx5_ib_dev *dev = 2341 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2342 2343 return sprintf(buf, "%lld\n", (long long)dev->mdev->priv.fw_pages); 2344 } 2345 2346 static ssize_t show_reg_pages(struct device *device, 2347 struct device_attribute *attr, char *buf) 2348 { 2349 struct mlx5_ib_dev *dev = 2350 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2351 2352 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2353 } 2354 2355 static ssize_t show_hca(struct device *device, struct device_attribute *attr, 2356 char *buf) 2357 { 2358 struct mlx5_ib_dev *dev = 2359 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2360 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 2361 } 2362 2363 static ssize_t show_rev(struct device *device, struct device_attribute *attr, 2364 char *buf) 2365 { 2366 struct mlx5_ib_dev *dev = 2367 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2368 return sprintf(buf, "%x\n", dev->mdev->pdev->revision); 2369 } 2370 2371 static ssize_t show_board(struct device *device, struct device_attribute *attr, 2372 char *buf) 2373 { 2374 struct mlx5_ib_dev *dev = 2375 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2376 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2377 dev->mdev->board_id); 2378 } 2379 2380 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 2381 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 2382 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 2383 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 2384 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 2385 2386 static struct device_attribute *mlx5_class_attributes[] = { 2387 &dev_attr_hw_rev, 2388 &dev_attr_hca_type, 2389 &dev_attr_board_id, 2390 &dev_attr_fw_pages, 2391 &dev_attr_reg_pages, 2392 }; 2393 2394 static void pkey_change_handler(struct work_struct *work) 2395 { 2396 struct mlx5_ib_port_resources *ports = 2397 container_of(work, struct mlx5_ib_port_resources, 2398 pkey_change_work); 2399 2400 mutex_lock(&ports->devr->mutex); 2401 mlx5_ib_gsi_pkey_change(ports->gsi); 2402 mutex_unlock(&ports->devr->mutex); 2403 } 2404 2405 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2406 { 2407 struct mlx5_ib_qp *mqp; 2408 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2409 struct mlx5_core_cq *mcq; 2410 struct list_head cq_armed_list; 2411 unsigned long flags_qp; 2412 unsigned long flags_cq; 2413 unsigned long flags; 2414 2415 INIT_LIST_HEAD(&cq_armed_list); 2416 2417 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2418 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2419 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2420 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2421 if (mqp->sq.tail != mqp->sq.head) { 2422 send_mcq = to_mcq(mqp->ibqp.send_cq); 2423 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2424 if (send_mcq->mcq.comp && 2425 mqp->ibqp.send_cq->comp_handler) { 2426 if (!send_mcq->mcq.reset_notify_added) { 2427 send_mcq->mcq.reset_notify_added = 1; 2428 list_add_tail(&send_mcq->mcq.reset_notify, 2429 &cq_armed_list); 2430 } 2431 } 2432 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2433 } 2434 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2435 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2436 /* no handling is needed for SRQ */ 2437 if (!mqp->ibqp.srq) { 2438 if (mqp->rq.tail != mqp->rq.head) { 2439 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2440 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2441 if (recv_mcq->mcq.comp && 2442 mqp->ibqp.recv_cq->comp_handler) { 2443 if (!recv_mcq->mcq.reset_notify_added) { 2444 recv_mcq->mcq.reset_notify_added = 1; 2445 list_add_tail(&recv_mcq->mcq.reset_notify, 2446 &cq_armed_list); 2447 } 2448 } 2449 spin_unlock_irqrestore(&recv_mcq->lock, 2450 flags_cq); 2451 } 2452 } 2453 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2454 } 2455 /*At that point all inflight post send were put to be executed as of we 2456 * lock/unlock above locks Now need to arm all involved CQs. 2457 */ 2458 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2459 mcq->comp(mcq); 2460 } 2461 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2462 } 2463 2464 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 2465 enum mlx5_dev_event event, unsigned long param) 2466 { 2467 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; 2468 struct ib_event ibev; 2469 bool fatal = false; 2470 u8 port = (u8)param; 2471 2472 switch (event) { 2473 case MLX5_DEV_EVENT_SYS_ERROR: 2474 ibev.event = IB_EVENT_DEVICE_FATAL; 2475 mlx5_ib_handle_internal_error(ibdev); 2476 fatal = true; 2477 break; 2478 2479 case MLX5_DEV_EVENT_PORT_UP: 2480 case MLX5_DEV_EVENT_PORT_DOWN: 2481 case MLX5_DEV_EVENT_PORT_INITIALIZED: 2482 /* In RoCE, port up/down events are handled in 2483 * mlx5_netdev_event(). 2484 */ 2485 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2486 IB_LINK_LAYER_ETHERNET) 2487 return; 2488 2489 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ? 2490 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2491 break; 2492 2493 case MLX5_DEV_EVENT_LID_CHANGE: 2494 ibev.event = IB_EVENT_LID_CHANGE; 2495 break; 2496 2497 case MLX5_DEV_EVENT_PKEY_CHANGE: 2498 ibev.event = IB_EVENT_PKEY_CHANGE; 2499 2500 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2501 break; 2502 2503 case MLX5_DEV_EVENT_GUID_CHANGE: 2504 ibev.event = IB_EVENT_GID_CHANGE; 2505 break; 2506 2507 case MLX5_DEV_EVENT_CLIENT_REREG: 2508 ibev.event = IB_EVENT_CLIENT_REREGISTER; 2509 break; 2510 2511 default: 2512 /* unsupported event */ 2513 return; 2514 } 2515 2516 ibev.device = &ibdev->ib_dev; 2517 ibev.element.port_num = port; 2518 2519 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) { 2520 mlx5_ib_warn(ibdev, "warning: event(%d) on port %d\n", event, port); 2521 return; 2522 } 2523 2524 if (ibdev->ib_active) 2525 ib_dispatch_event(&ibev); 2526 2527 if (fatal) 2528 ibdev->ib_active = false; 2529 } 2530 2531 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2532 { 2533 int port; 2534 2535 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) 2536 mlx5_query_ext_port_caps(dev, port); 2537 } 2538 2539 static int get_port_caps(struct mlx5_ib_dev *dev) 2540 { 2541 struct ib_device_attr *dprops = NULL; 2542 struct ib_port_attr *pprops = NULL; 2543 int err = -ENOMEM; 2544 int port; 2545 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 2546 2547 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 2548 if (!pprops) 2549 goto out; 2550 2551 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 2552 if (!dprops) 2553 goto out; 2554 2555 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 2556 if (err) { 2557 mlx5_ib_warn(dev, "query_device failed %d\n", err); 2558 goto out; 2559 } 2560 2561 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 2562 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 2563 if (err) { 2564 mlx5_ib_warn(dev, "query_port %d failed %d\n", 2565 port, err); 2566 break; 2567 } 2568 dev->mdev->port_caps[port - 1].pkey_table_len = 2569 dprops->max_pkeys; 2570 dev->mdev->port_caps[port - 1].gid_table_len = 2571 pprops->gid_tbl_len; 2572 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n", 2573 dprops->max_pkeys, pprops->gid_tbl_len); 2574 } 2575 2576 out: 2577 kfree(pprops); 2578 kfree(dprops); 2579 2580 return err; 2581 } 2582 2583 static void destroy_umrc_res(struct mlx5_ib_dev *dev) 2584 { 2585 int err; 2586 2587 err = mlx5_mr_cache_cleanup(dev); 2588 if (err) 2589 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 2590 2591 mlx5_ib_destroy_qp(dev->umrc.qp); 2592 ib_free_cq(dev->umrc.cq); 2593 ib_dealloc_pd(dev->umrc.pd); 2594 } 2595 2596 enum { 2597 MAX_UMR_WR = 128, 2598 }; 2599 2600 static int create_umr_res(struct mlx5_ib_dev *dev) 2601 { 2602 struct ib_qp_init_attr *init_attr = NULL; 2603 struct ib_qp_attr *attr = NULL; 2604 struct ib_pd *pd; 2605 struct ib_cq *cq; 2606 struct ib_qp *qp; 2607 int ret; 2608 2609 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 2610 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 2611 if (!attr || !init_attr) { 2612 ret = -ENOMEM; 2613 goto error_0; 2614 } 2615 2616 pd = ib_alloc_pd(&dev->ib_dev, 0); 2617 if (IS_ERR(pd)) { 2618 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 2619 ret = PTR_ERR(pd); 2620 goto error_0; 2621 } 2622 2623 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 2624 if (IS_ERR(cq)) { 2625 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 2626 ret = PTR_ERR(cq); 2627 goto error_2; 2628 } 2629 2630 init_attr->send_cq = cq; 2631 init_attr->recv_cq = cq; 2632 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 2633 init_attr->cap.max_send_wr = MAX_UMR_WR; 2634 init_attr->cap.max_send_sge = 1; 2635 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 2636 init_attr->port_num = 1; 2637 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 2638 if (IS_ERR(qp)) { 2639 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 2640 ret = PTR_ERR(qp); 2641 goto error_3; 2642 } 2643 qp->device = &dev->ib_dev; 2644 qp->real_qp = qp; 2645 qp->uobject = NULL; 2646 qp->qp_type = MLX5_IB_QPT_REG_UMR; 2647 2648 attr->qp_state = IB_QPS_INIT; 2649 attr->port_num = 1; 2650 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 2651 IB_QP_PORT, NULL); 2652 if (ret) { 2653 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 2654 goto error_4; 2655 } 2656 2657 memset(attr, 0, sizeof(*attr)); 2658 attr->qp_state = IB_QPS_RTR; 2659 attr->path_mtu = IB_MTU_256; 2660 2661 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2662 if (ret) { 2663 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 2664 goto error_4; 2665 } 2666 2667 memset(attr, 0, sizeof(*attr)); 2668 attr->qp_state = IB_QPS_RTS; 2669 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2670 if (ret) { 2671 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 2672 goto error_4; 2673 } 2674 2675 dev->umrc.qp = qp; 2676 dev->umrc.cq = cq; 2677 dev->umrc.pd = pd; 2678 2679 sema_init(&dev->umrc.sem, MAX_UMR_WR); 2680 ret = mlx5_mr_cache_init(dev); 2681 if (ret) { 2682 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 2683 goto error_4; 2684 } 2685 2686 kfree(attr); 2687 kfree(init_attr); 2688 2689 return 0; 2690 2691 error_4: 2692 mlx5_ib_destroy_qp(qp); 2693 2694 error_3: 2695 ib_free_cq(cq); 2696 2697 error_2: 2698 ib_dealloc_pd(pd); 2699 2700 error_0: 2701 kfree(attr); 2702 kfree(init_attr); 2703 return ret; 2704 } 2705 2706 static int create_dev_resources(struct mlx5_ib_resources *devr) 2707 { 2708 struct ib_srq_init_attr attr; 2709 struct mlx5_ib_dev *dev; 2710 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2711 int port; 2712 int ret = 0; 2713 2714 dev = container_of(devr, struct mlx5_ib_dev, devr); 2715 2716 mutex_init(&devr->mutex); 2717 2718 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 2719 if (IS_ERR(devr->p0)) { 2720 ret = PTR_ERR(devr->p0); 2721 goto error0; 2722 } 2723 devr->p0->device = &dev->ib_dev; 2724 devr->p0->uobject = NULL; 2725 atomic_set(&devr->p0->usecnt, 0); 2726 2727 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 2728 if (IS_ERR(devr->c0)) { 2729 ret = PTR_ERR(devr->c0); 2730 goto error1; 2731 } 2732 devr->c0->device = &dev->ib_dev; 2733 devr->c0->uobject = NULL; 2734 devr->c0->comp_handler = NULL; 2735 devr->c0->event_handler = NULL; 2736 devr->c0->cq_context = NULL; 2737 atomic_set(&devr->c0->usecnt, 0); 2738 2739 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 2740 if (IS_ERR(devr->x0)) { 2741 ret = PTR_ERR(devr->x0); 2742 goto error2; 2743 } 2744 devr->x0->device = &dev->ib_dev; 2745 devr->x0->inode = NULL; 2746 atomic_set(&devr->x0->usecnt, 0); 2747 mutex_init(&devr->x0->tgt_qp_mutex); 2748 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 2749 2750 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 2751 if (IS_ERR(devr->x1)) { 2752 ret = PTR_ERR(devr->x1); 2753 goto error3; 2754 } 2755 devr->x1->device = &dev->ib_dev; 2756 devr->x1->inode = NULL; 2757 atomic_set(&devr->x1->usecnt, 0); 2758 mutex_init(&devr->x1->tgt_qp_mutex); 2759 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 2760 2761 memset(&attr, 0, sizeof(attr)); 2762 attr.attr.max_sge = 1; 2763 attr.attr.max_wr = 1; 2764 attr.srq_type = IB_SRQT_XRC; 2765 attr.ext.xrc.cq = devr->c0; 2766 attr.ext.xrc.xrcd = devr->x0; 2767 2768 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 2769 if (IS_ERR(devr->s0)) { 2770 ret = PTR_ERR(devr->s0); 2771 goto error4; 2772 } 2773 devr->s0->device = &dev->ib_dev; 2774 devr->s0->pd = devr->p0; 2775 devr->s0->uobject = NULL; 2776 devr->s0->event_handler = NULL; 2777 devr->s0->srq_context = NULL; 2778 devr->s0->srq_type = IB_SRQT_XRC; 2779 devr->s0->ext.xrc.xrcd = devr->x0; 2780 devr->s0->ext.xrc.cq = devr->c0; 2781 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 2782 atomic_inc(&devr->s0->ext.xrc.cq->usecnt); 2783 atomic_inc(&devr->p0->usecnt); 2784 atomic_set(&devr->s0->usecnt, 0); 2785 2786 memset(&attr, 0, sizeof(attr)); 2787 attr.attr.max_sge = 1; 2788 attr.attr.max_wr = 1; 2789 attr.srq_type = IB_SRQT_BASIC; 2790 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 2791 if (IS_ERR(devr->s1)) { 2792 ret = PTR_ERR(devr->s1); 2793 goto error5; 2794 } 2795 devr->s1->device = &dev->ib_dev; 2796 devr->s1->pd = devr->p0; 2797 devr->s1->uobject = NULL; 2798 devr->s1->event_handler = NULL; 2799 devr->s1->srq_context = NULL; 2800 devr->s1->srq_type = IB_SRQT_BASIC; 2801 devr->s1->ext.xrc.cq = devr->c0; 2802 atomic_inc(&devr->p0->usecnt); 2803 atomic_set(&devr->s0->usecnt, 0); 2804 2805 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 2806 INIT_WORK(&devr->ports[port].pkey_change_work, 2807 pkey_change_handler); 2808 devr->ports[port].devr = devr; 2809 } 2810 2811 return 0; 2812 2813 error5: 2814 mlx5_ib_destroy_srq(devr->s0); 2815 error4: 2816 mlx5_ib_dealloc_xrcd(devr->x1); 2817 error3: 2818 mlx5_ib_dealloc_xrcd(devr->x0); 2819 error2: 2820 mlx5_ib_destroy_cq(devr->c0); 2821 error1: 2822 mlx5_ib_dealloc_pd(devr->p0); 2823 error0: 2824 return ret; 2825 } 2826 2827 static void destroy_dev_resources(struct mlx5_ib_resources *devr) 2828 { 2829 struct mlx5_ib_dev *dev = 2830 container_of(devr, struct mlx5_ib_dev, devr); 2831 int port; 2832 2833 mlx5_ib_destroy_srq(devr->s1); 2834 mlx5_ib_destroy_srq(devr->s0); 2835 mlx5_ib_dealloc_xrcd(devr->x0); 2836 mlx5_ib_dealloc_xrcd(devr->x1); 2837 mlx5_ib_destroy_cq(devr->c0); 2838 mlx5_ib_dealloc_pd(devr->p0); 2839 2840 /* Make sure no change P_Key work items are still executing */ 2841 for (port = 0; port < dev->num_ports; ++port) 2842 cancel_work_sync(&devr->ports[port].pkey_change_work); 2843 } 2844 2845 static u32 get_core_cap_flags(struct ib_device *ibdev) 2846 { 2847 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2848 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 2849 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 2850 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 2851 u32 ret = 0; 2852 2853 if (ll == IB_LINK_LAYER_INFINIBAND) 2854 return RDMA_CORE_PORT_IBA_IB; 2855 2856 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 2857 return 0; 2858 2859 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 2860 return 0; 2861 2862 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 2863 ret |= RDMA_CORE_PORT_IBA_ROCE; 2864 2865 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 2866 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2867 2868 return ret; 2869 } 2870 2871 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 2872 struct ib_port_immutable *immutable) 2873 { 2874 struct ib_port_attr attr; 2875 int err; 2876 2877 err = mlx5_ib_query_port(ibdev, port_num, &attr); 2878 if (err) 2879 return err; 2880 2881 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2882 immutable->gid_tbl_len = attr.gid_tbl_len; 2883 immutable->core_cap_flags = get_core_cap_flags(ibdev); 2884 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2885 2886 return 0; 2887 } 2888 2889 static void get_dev_fw_str(struct ib_device *ibdev, char *str, 2890 size_t str_len) 2891 { 2892 struct mlx5_ib_dev *dev = 2893 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 2894 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev), 2895 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev)); 2896 } 2897 2898 static int mlx5_roce_lag_init(struct mlx5_ib_dev *dev) 2899 { 2900 return 0; 2901 } 2902 2903 static void mlx5_roce_lag_cleanup(struct mlx5_ib_dev *dev) 2904 { 2905 } 2906 2907 static void mlx5_remove_roce_notifier(struct mlx5_ib_dev *dev) 2908 { 2909 if (dev->roce.nb.notifier_call) { 2910 unregister_netdevice_notifier(&dev->roce.nb); 2911 dev->roce.nb.notifier_call = NULL; 2912 } 2913 } 2914 2915 static int mlx5_enable_roce(struct mlx5_ib_dev *dev) 2916 { 2917 VNET_ITERATOR_DECL(vnet_iter); 2918 struct net_device *idev; 2919 int err; 2920 2921 /* Check if mlx5en net device already exists */ 2922 VNET_LIST_RLOCK(); 2923 VNET_FOREACH(vnet_iter) { 2924 IFNET_RLOCK(); 2925 CURVNET_SET_QUIET(vnet_iter); 2926 CK_STAILQ_FOREACH(idev, &V_ifnet, if_link) { 2927 /* check if network interface belongs to mlx5en */ 2928 if (!mlx5_netdev_match(idev, dev->mdev, "mce")) 2929 continue; 2930 write_lock(&dev->roce.netdev_lock); 2931 dev->roce.netdev = idev; 2932 write_unlock(&dev->roce.netdev_lock); 2933 } 2934 CURVNET_RESTORE(); 2935 IFNET_RUNLOCK(); 2936 } 2937 VNET_LIST_RUNLOCK(); 2938 2939 dev->roce.nb.notifier_call = mlx5_netdev_event; 2940 err = register_netdevice_notifier(&dev->roce.nb); 2941 if (err) { 2942 dev->roce.nb.notifier_call = NULL; 2943 return err; 2944 } 2945 2946 err = mlx5_nic_vport_enable_roce(dev->mdev); 2947 if (err) 2948 goto err_unregister_netdevice_notifier; 2949 2950 err = mlx5_roce_lag_init(dev); 2951 if (err) 2952 goto err_disable_roce; 2953 2954 return 0; 2955 2956 err_disable_roce: 2957 mlx5_nic_vport_disable_roce(dev->mdev); 2958 2959 err_unregister_netdevice_notifier: 2960 mlx5_remove_roce_notifier(dev); 2961 return err; 2962 } 2963 2964 static void mlx5_disable_roce(struct mlx5_ib_dev *dev) 2965 { 2966 mlx5_roce_lag_cleanup(dev); 2967 mlx5_nic_vport_disable_roce(dev->mdev); 2968 } 2969 2970 static void mlx5_ib_dealloc_q_port_counter(struct mlx5_ib_dev *dev, u8 port_num) 2971 { 2972 mlx5_vport_dealloc_q_counter(dev->mdev, 2973 MLX5_INTERFACE_PROTOCOL_IB, 2974 dev->port[port_num].q_cnt_id); 2975 dev->port[port_num].q_cnt_id = 0; 2976 } 2977 2978 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev) 2979 { 2980 unsigned int i; 2981 2982 for (i = 0; i < dev->num_ports; i++) 2983 mlx5_ib_dealloc_q_port_counter(dev, i); 2984 } 2985 2986 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev) 2987 { 2988 int i; 2989 int ret; 2990 2991 for (i = 0; i < dev->num_ports; i++) { 2992 ret = mlx5_vport_alloc_q_counter(dev->mdev, 2993 MLX5_INTERFACE_PROTOCOL_IB, 2994 &dev->port[i].q_cnt_id); 2995 if (ret) { 2996 mlx5_ib_warn(dev, 2997 "couldn't allocate queue counter for port %d, err %d\n", 2998 i + 1, ret); 2999 goto dealloc_counters; 3000 } 3001 } 3002 3003 return 0; 3004 3005 dealloc_counters: 3006 while (--i >= 0) 3007 mlx5_ib_dealloc_q_port_counter(dev, i); 3008 3009 return ret; 3010 } 3011 3012 static const char * const names[] = { 3013 "rx_write_requests", 3014 "rx_read_requests", 3015 "rx_atomic_requests", 3016 "out_of_buffer", 3017 "out_of_sequence", 3018 "duplicate_request", 3019 "rnr_nak_retry_err", 3020 "packet_seq_err", 3021 "implied_nak_seq_err", 3022 "local_ack_timeout_err", 3023 }; 3024 3025 static const size_t stats_offsets[] = { 3026 MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests), 3027 MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests), 3028 MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests), 3029 MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer), 3030 MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence), 3031 MLX5_BYTE_OFF(query_q_counter_out, duplicate_request), 3032 MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err), 3033 MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err), 3034 MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err), 3035 MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err), 3036 }; 3037 3038 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 3039 u8 port_num) 3040 { 3041 BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets)); 3042 3043 /* We support only per port stats */ 3044 if (port_num == 0) 3045 return NULL; 3046 3047 return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names), 3048 RDMA_HW_STATS_DEFAULT_LIFESPAN); 3049 } 3050 3051 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 3052 struct rdma_hw_stats *stats, 3053 u8 port, int index) 3054 { 3055 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3056 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 3057 void *out; 3058 __be32 val; 3059 int ret; 3060 int i; 3061 3062 if (!port || !stats) 3063 return -ENOSYS; 3064 3065 out = mlx5_vzalloc(outlen); 3066 if (!out) 3067 return -ENOMEM; 3068 3069 ret = mlx5_vport_query_q_counter(dev->mdev, 3070 dev->port[port - 1].q_cnt_id, 0, 3071 out, outlen); 3072 if (ret) 3073 goto free; 3074 3075 for (i = 0; i < ARRAY_SIZE(names); i++) { 3076 val = *(__be32 *)(out + stats_offsets[i]); 3077 stats->value[i] = (u64)be32_to_cpu(val); 3078 } 3079 free: 3080 kvfree(out); 3081 return ARRAY_SIZE(names); 3082 } 3083 3084 static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 3085 { 3086 struct mlx5_ib_dev *dev; 3087 enum rdma_link_layer ll; 3088 int port_type_cap; 3089 int err; 3090 int i; 3091 3092 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3093 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3094 3095 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce)) 3096 return NULL; 3097 3098 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 3099 if (!dev) 3100 return NULL; 3101 3102 dev->mdev = mdev; 3103 3104 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port), 3105 GFP_KERNEL); 3106 if (!dev->port) 3107 goto err_dealloc; 3108 3109 rwlock_init(&dev->roce.netdev_lock); 3110 err = get_port_caps(dev); 3111 if (err) 3112 goto err_free_port; 3113 3114 if (mlx5_use_mad_ifc(dev)) 3115 get_ext_port_caps(dev); 3116 3117 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock); 3118 3119 snprintf(dev->ib_dev.name, IB_DEVICE_NAME_MAX, "mlx5_%d", device_get_unit(mdev->pdev->dev.bsddev)); 3120 dev->ib_dev.owner = THIS_MODULE; 3121 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3122 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3123 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports); 3124 dev->ib_dev.phys_port_cnt = dev->num_ports; 3125 dev->ib_dev.num_comp_vectors = 3126 dev->mdev->priv.eq_table.num_comp_vectors; 3127 dev->ib_dev.dma_device = &mdev->pdev->dev; 3128 3129 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 3130 dev->ib_dev.uverbs_cmd_mask = 3131 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 3132 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 3133 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 3134 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 3135 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 3136 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 3137 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 3138 (1ull << IB_USER_VERBS_CMD_REG_MR) | 3139 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 3140 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 3141 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 3142 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 3143 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 3144 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 3145 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 3146 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 3147 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 3148 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 3149 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 3150 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 3151 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 3152 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 3153 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 3154 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 3155 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 3156 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 3157 dev->ib_dev.uverbs_ex_cmd_mask = 3158 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 3159 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 3160 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP); 3161 3162 dev->ib_dev.query_device = mlx5_ib_query_device; 3163 dev->ib_dev.query_port = mlx5_ib_query_port; 3164 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 3165 if (ll == IB_LINK_LAYER_ETHERNET) 3166 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 3167 dev->ib_dev.query_gid = mlx5_ib_query_gid; 3168 dev->ib_dev.add_gid = mlx5_ib_add_gid; 3169 dev->ib_dev.del_gid = mlx5_ib_del_gid; 3170 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 3171 dev->ib_dev.modify_device = mlx5_ib_modify_device; 3172 dev->ib_dev.modify_port = mlx5_ib_modify_port; 3173 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 3174 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 3175 dev->ib_dev.mmap = mlx5_ib_mmap; 3176 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 3177 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 3178 dev->ib_dev.create_ah = mlx5_ib_create_ah; 3179 dev->ib_dev.query_ah = mlx5_ib_query_ah; 3180 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 3181 dev->ib_dev.create_srq = mlx5_ib_create_srq; 3182 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 3183 dev->ib_dev.query_srq = mlx5_ib_query_srq; 3184 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 3185 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 3186 dev->ib_dev.create_qp = mlx5_ib_create_qp; 3187 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 3188 dev->ib_dev.query_qp = mlx5_ib_query_qp; 3189 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 3190 dev->ib_dev.post_send = mlx5_ib_post_send; 3191 dev->ib_dev.post_recv = mlx5_ib_post_recv; 3192 dev->ib_dev.create_cq = mlx5_ib_create_cq; 3193 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 3194 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 3195 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 3196 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 3197 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 3198 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 3199 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 3200 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 3201 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 3202 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 3203 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 3204 dev->ib_dev.process_mad = mlx5_ib_process_mad; 3205 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 3206 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 3207 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 3208 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 3209 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 3210 if (mlx5_core_is_pf(mdev)) { 3211 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 3212 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 3213 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 3214 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 3215 } 3216 3217 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 3218 3219 mlx5_ib_internal_fill_odp_caps(dev); 3220 3221 if (MLX5_CAP_GEN(mdev, imaicl)) { 3222 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 3223 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 3224 dev->ib_dev.uverbs_cmd_mask |= 3225 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 3226 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 3227 } 3228 3229 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) && 3230 MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 3231 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 3232 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 3233 } 3234 3235 if (MLX5_CAP_GEN(mdev, xrc)) { 3236 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 3237 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 3238 dev->ib_dev.uverbs_cmd_mask |= 3239 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 3240 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 3241 } 3242 3243 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) == 3244 IB_LINK_LAYER_ETHERNET) { 3245 dev->ib_dev.create_flow = mlx5_ib_create_flow; 3246 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 3247 dev->ib_dev.create_wq = mlx5_ib_create_wq; 3248 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 3249 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 3250 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 3251 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 3252 dev->ib_dev.uverbs_ex_cmd_mask |= 3253 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 3254 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) | 3255 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 3256 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 3257 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 3258 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 3259 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 3260 } 3261 err = init_node_data(dev); 3262 if (err) 3263 goto err_free_port; 3264 3265 mutex_init(&dev->flow_db.lock); 3266 mutex_init(&dev->cap_mask_mutex); 3267 INIT_LIST_HEAD(&dev->qp_list); 3268 spin_lock_init(&dev->reset_flow_resource_lock); 3269 3270 if (ll == IB_LINK_LAYER_ETHERNET) { 3271 err = mlx5_enable_roce(dev); 3272 if (err) 3273 goto err_free_port; 3274 } 3275 3276 err = create_dev_resources(&dev->devr); 3277 if (err) 3278 goto err_disable_roce; 3279 3280 err = mlx5_ib_odp_init_one(dev); 3281 if (err) 3282 goto err_rsrc; 3283 3284 err = mlx5_ib_alloc_q_counters(dev); 3285 if (err) 3286 goto err_odp; 3287 3288 err = ib_register_device(&dev->ib_dev, NULL); 3289 if (err) 3290 goto err_q_cnt; 3291 3292 err = create_umr_res(dev); 3293 if (err) 3294 goto err_dev; 3295 3296 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 3297 err = device_create_file(&dev->ib_dev.dev, 3298 mlx5_class_attributes[i]); 3299 if (err) 3300 goto err_umrc; 3301 } 3302 3303 err = mlx5_ib_init_congestion(dev); 3304 if (err) 3305 goto err_umrc; 3306 3307 dev->ib_active = true; 3308 3309 return dev; 3310 3311 err_umrc: 3312 destroy_umrc_res(dev); 3313 3314 err_dev: 3315 ib_unregister_device(&dev->ib_dev); 3316 3317 err_q_cnt: 3318 mlx5_ib_dealloc_q_counters(dev); 3319 3320 err_odp: 3321 mlx5_ib_odp_remove_one(dev); 3322 3323 err_rsrc: 3324 destroy_dev_resources(&dev->devr); 3325 3326 err_disable_roce: 3327 if (ll == IB_LINK_LAYER_ETHERNET) { 3328 mlx5_disable_roce(dev); 3329 mlx5_remove_roce_notifier(dev); 3330 } 3331 3332 err_free_port: 3333 kfree(dev->port); 3334 3335 err_dealloc: 3336 ib_dealloc_device((struct ib_device *)dev); 3337 3338 return NULL; 3339 } 3340 3341 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 3342 { 3343 struct mlx5_ib_dev *dev = context; 3344 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); 3345 3346 mlx5_ib_cleanup_congestion(dev); 3347 mlx5_remove_roce_notifier(dev); 3348 ib_unregister_device(&dev->ib_dev); 3349 mlx5_ib_dealloc_q_counters(dev); 3350 destroy_umrc_res(dev); 3351 mlx5_ib_odp_remove_one(dev); 3352 destroy_dev_resources(&dev->devr); 3353 if (ll == IB_LINK_LAYER_ETHERNET) 3354 mlx5_disable_roce(dev); 3355 kfree(dev->port); 3356 ib_dealloc_device(&dev->ib_dev); 3357 } 3358 3359 static struct mlx5_interface mlx5_ib_interface = { 3360 .add = mlx5_ib_add, 3361 .remove = mlx5_ib_remove, 3362 .event = mlx5_ib_event, 3363 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 3364 }; 3365 3366 static int __init mlx5_ib_init(void) 3367 { 3368 int err; 3369 3370 err = mlx5_ib_odp_init(); 3371 if (err) 3372 return err; 3373 3374 err = mlx5_register_interface(&mlx5_ib_interface); 3375 if (err) 3376 goto clean_odp; 3377 3378 return err; 3379 3380 clean_odp: 3381 mlx5_ib_odp_cleanup(); 3382 return err; 3383 } 3384 3385 static void __exit mlx5_ib_cleanup(void) 3386 { 3387 mlx5_unregister_interface(&mlx5_ib_interface); 3388 mlx5_ib_odp_cleanup(); 3389 } 3390 3391 static void 3392 mlx5_ib_show_version(void __unused *arg) 3393 { 3394 3395 printf("%s", mlx5_version); 3396 } 3397 SYSINIT(mlx5_ib_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5_ib_show_version, NULL); 3398 3399 module_init_order(mlx5_ib_init, SI_ORDER_THIRD); 3400 module_exit_order(mlx5_ib_cleanup, SI_ORDER_THIRD); 3401