1 /*- 2 * Copyright (c) 2018-2020, Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 #include "opt_rss.h" 27 #include "opt_ratelimit.h" 28 29 #include <rdma/ib_user_verbs.h> 30 #include <rdma/ib_verbs.h> 31 #include <rdma/uverbs_types.h> 32 #include <rdma/uverbs_ioctl.h> 33 #include <rdma/mlx5_user_ioctl_cmds.h> 34 #include <rdma/mlx5_user_ioctl_verbs.h> 35 #include <rdma/ib_umem.h> 36 #include <rdma/uverbs_std_types.h> 37 #include <dev/mlx5/driver.h> 38 #include <dev/mlx5/fs.h> 39 #include <dev/mlx5/mlx5_ib/mlx5_ib.h> 40 41 #include <sys/priv.h> 42 43 #include <linux/bitops.h> 44 #include <linux/overflow.h> 45 #include <linux/xarray.h> 46 #include <linux/rculist.h> 47 #include <linux/srcu.h> 48 #include <linux/file.h> 49 #include <linux/eventfd.h> 50 #include <linux/poll.h> 51 #include <linux/wait.h> 52 53 #define UVERBS_MODULE_NAME mlx5_ib 54 #include <rdma/uverbs_named_ioctl.h> 55 56 static void dispatch_event_fd(struct list_head *fd_list, const void *data); 57 58 enum devx_obj_flags { 59 DEVX_OBJ_FLAGS_DCT = 1 << 1, 60 DEVX_OBJ_FLAGS_CQ = 1 << 2, 61 }; 62 63 struct devx_async_data { 64 struct mlx5_ib_dev *mdev; 65 struct list_head list; 66 struct devx_async_cmd_event_file *ev_file; 67 struct mlx5_async_work cb_work; 68 u16 cmd_out_len; 69 /* must be last field in this structure */ 70 struct mlx5_ib_uapi_devx_async_cmd_hdr hdr; 71 }; 72 73 struct devx_async_event_data { 74 struct list_head list; /* headed in ev_file->event_list */ 75 struct mlx5_ib_uapi_devx_async_event_hdr hdr; 76 }; 77 78 /* first level XA value data structure */ 79 struct devx_event { 80 struct xarray object_ids; /* second XA level, Key = object id */ 81 struct list_head unaffiliated_list; 82 }; 83 84 /* second level XA value data structure */ 85 struct devx_obj_event { 86 struct rcu_head rcu; 87 struct list_head obj_sub_list; 88 }; 89 90 struct devx_event_subscription { 91 struct list_head file_list; /* headed in ev_file-> 92 * subscribed_events_list 93 */ 94 struct list_head xa_list; /* headed in devx_event->unaffiliated_list or 95 * devx_obj_event->obj_sub_list 96 */ 97 struct list_head obj_list; /* headed in devx_object */ 98 struct list_head event_list; /* headed in ev_file->event_list or in 99 * temp list via subscription 100 */ 101 102 u8 is_cleaned:1; 103 u32 xa_key_level1; 104 u32 xa_key_level2; 105 struct rcu_head rcu; 106 u64 cookie; 107 struct devx_async_event_file *ev_file; 108 struct eventfd_ctx *eventfd; 109 }; 110 111 struct devx_async_event_file { 112 struct ib_uobject uobj; 113 /* Head of events that are subscribed to this FD */ 114 struct list_head subscribed_events_list; 115 spinlock_t lock; 116 wait_queue_head_t poll_wait; 117 struct list_head event_list; 118 struct mlx5_ib_dev *dev; 119 u8 omit_data:1; 120 u8 is_overflow_err:1; 121 u8 is_destroyed:1; 122 }; 123 124 #define MLX5_MAX_DESTROY_INBOX_SIZE_DW MLX5_ST_SZ_DW(delete_fte_in) 125 struct devx_obj { 126 struct mlx5_ib_dev *ib_dev; 127 u64 obj_id; 128 u32 dinlen; /* destroy inbox length */ 129 u32 dinbox[MLX5_MAX_DESTROY_INBOX_SIZE_DW]; 130 u32 flags; 131 union { 132 struct mlx5_ib_devx_mr devx_mr; 133 struct mlx5_core_dct core_dct; 134 struct mlx5_core_cq core_cq; 135 u32 flow_counter_bulk_size; 136 }; 137 struct list_head event_sub; /* holds devx_event_subscription entries */ 138 }; 139 140 struct devx_umem { 141 struct mlx5_core_dev *mdev; 142 struct ib_umem *umem; 143 u32 page_offset; 144 int page_shift; 145 int ncont; 146 u32 dinlen; 147 u32 dinbox[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)]; 148 }; 149 150 struct devx_umem_reg_cmd { 151 void *in; 152 u32 inlen; 153 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 154 }; 155 156 static struct mlx5_ib_ucontext * 157 devx_ufile2uctx(const struct uverbs_attr_bundle *attrs) 158 { 159 return to_mucontext(ib_uverbs_get_ucontext(attrs)); 160 } 161 162 int mlx5_ib_devx_create(struct mlx5_ib_dev *dev, bool is_user) 163 { 164 u32 in[MLX5_ST_SZ_DW(create_uctx_in)] = {0}; 165 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 166 void *uctx; 167 int err; 168 u16 uid; 169 u32 cap = 0; 170 171 /* 0 means not supported */ 172 if (!MLX5_CAP_GEN(dev->mdev, log_max_uctx)) 173 return -EINVAL; 174 175 uctx = MLX5_ADDR_OF(create_uctx_in, in, uctx); 176 if (is_user && priv_check(curthread, PRIV_NET_RAW) == 0 && 177 (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RAW_TX)) 178 cap |= MLX5_UCTX_CAP_RAW_TX; 179 if (is_user && priv_check(curthread, PRIV_DRIVER) == 0 && 180 (MLX5_CAP_GEN(dev->mdev, uctx_cap) & 181 MLX5_UCTX_CAP_INTERNAL_DEV_RES)) 182 cap |= MLX5_UCTX_CAP_INTERNAL_DEV_RES; 183 184 MLX5_SET(create_uctx_in, in, opcode, MLX5_CMD_OP_CREATE_UCTX); 185 MLX5_SET(uctx, uctx, cap, cap); 186 187 err = mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out)); 188 if (err) 189 return err; 190 191 uid = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 192 return uid; 193 } 194 195 void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid) 196 { 197 u32 in[MLX5_ST_SZ_DW(destroy_uctx_in)] = {0}; 198 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 199 200 MLX5_SET(destroy_uctx_in, in, opcode, MLX5_CMD_OP_DESTROY_UCTX); 201 MLX5_SET(destroy_uctx_in, in, uid, uid); 202 203 mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out)); 204 } 205 206 bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id, int *dest_type) 207 { 208 struct devx_obj *devx_obj = obj; 209 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, devx_obj->dinbox, opcode); 210 211 switch (opcode) { 212 case MLX5_CMD_OP_DESTROY_TIR: 213 *dest_type = MLX5_FLOW_DESTINATION_TYPE_TIR; 214 *dest_id = MLX5_GET(general_obj_in_cmd_hdr, devx_obj->dinbox, 215 obj_id); 216 return true; 217 218 case MLX5_CMD_OP_DESTROY_FLOW_TABLE: 219 *dest_type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; 220 *dest_id = MLX5_GET(destroy_flow_table_in, devx_obj->dinbox, 221 table_id); 222 return true; 223 default: 224 return false; 225 } 226 } 227 228 bool mlx5_ib_devx_is_flow_counter(void *obj, u32 offset, u32 *counter_id) 229 { 230 struct devx_obj *devx_obj = obj; 231 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, devx_obj->dinbox, opcode); 232 233 if (opcode == MLX5_CMD_OP_DEALLOC_FLOW_COUNTER) { 234 235 if (offset && offset >= devx_obj->flow_counter_bulk_size) 236 return false; 237 238 *counter_id = MLX5_GET(dealloc_flow_counter_in, 239 devx_obj->dinbox, 240 flow_counter_id); 241 *counter_id += offset; 242 return true; 243 } 244 245 return false; 246 } 247 248 static bool is_legacy_unaffiliated_event_num(u16 event_num) 249 { 250 switch (event_num) { 251 case MLX5_EVENT_TYPE_PORT_CHANGE: 252 return true; 253 default: 254 return false; 255 } 256 } 257 258 static bool is_legacy_obj_event_num(u16 event_num) 259 { 260 switch (event_num) { 261 case MLX5_EVENT_TYPE_PATH_MIG: 262 case MLX5_EVENT_TYPE_COMM_EST: 263 case MLX5_EVENT_TYPE_SQ_DRAINED: 264 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 265 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 266 case MLX5_EVENT_TYPE_CQ_ERROR: 267 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 268 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 269 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 270 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 271 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 272 case MLX5_EVENT_TYPE_DCT_DRAINED: 273 case MLX5_EVENT_TYPE_COMP: 274 case MLX5_EVENT_TYPE_DCT_KEY_VIOLATION: 275 case MLX5_EVENT_TYPE_XRQ_ERROR: 276 return true; 277 default: 278 return false; 279 } 280 } 281 282 static u16 get_legacy_obj_type(u16 opcode) 283 { 284 switch (opcode) { 285 case MLX5_CMD_OP_CREATE_RQ: 286 return MLX5_EVENT_QUEUE_TYPE_RQ; 287 case MLX5_CMD_OP_CREATE_QP: 288 return MLX5_EVENT_QUEUE_TYPE_QP; 289 case MLX5_CMD_OP_CREATE_SQ: 290 return MLX5_EVENT_QUEUE_TYPE_SQ; 291 case MLX5_CMD_OP_CREATE_DCT: 292 return MLX5_EVENT_QUEUE_TYPE_DCT; 293 default: 294 return 0; 295 } 296 } 297 298 static u16 get_dec_obj_type(struct devx_obj *obj, u16 event_num) 299 { 300 u16 opcode; 301 302 opcode = (obj->obj_id >> 32) & 0xffff; 303 304 if (is_legacy_obj_event_num(event_num)) 305 return get_legacy_obj_type(opcode); 306 307 switch (opcode) { 308 case MLX5_CMD_OP_CREATE_GENERAL_OBJ: 309 return (obj->obj_id >> 48); 310 case MLX5_CMD_OP_CREATE_RQ: 311 return MLX5_OBJ_TYPE_RQ; 312 case MLX5_CMD_OP_CREATE_QP: 313 return MLX5_OBJ_TYPE_QP; 314 case MLX5_CMD_OP_CREATE_SQ: 315 return MLX5_OBJ_TYPE_SQ; 316 case MLX5_CMD_OP_CREATE_DCT: 317 return MLX5_OBJ_TYPE_DCT; 318 case MLX5_CMD_OP_CREATE_TIR: 319 return MLX5_OBJ_TYPE_TIR; 320 case MLX5_CMD_OP_CREATE_TIS: 321 return MLX5_OBJ_TYPE_TIS; 322 case MLX5_CMD_OP_CREATE_PSV: 323 return MLX5_OBJ_TYPE_PSV; 324 case MLX5_OBJ_TYPE_MKEY: 325 return MLX5_OBJ_TYPE_MKEY; 326 case MLX5_CMD_OP_CREATE_RMP: 327 return MLX5_OBJ_TYPE_RMP; 328 case MLX5_CMD_OP_CREATE_XRC_SRQ: 329 return MLX5_OBJ_TYPE_XRC_SRQ; 330 case MLX5_CMD_OP_CREATE_XRQ: 331 return MLX5_OBJ_TYPE_XRQ; 332 case MLX5_CMD_OP_CREATE_RQT: 333 return MLX5_OBJ_TYPE_RQT; 334 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER: 335 return MLX5_OBJ_TYPE_FLOW_COUNTER; 336 case MLX5_CMD_OP_CREATE_CQ: 337 return MLX5_OBJ_TYPE_CQ; 338 default: 339 return 0; 340 } 341 } 342 343 static u16 get_event_obj_type(unsigned long event_type, struct mlx5_eqe *eqe) 344 { 345 switch (event_type) { 346 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 347 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 348 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 349 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 350 case MLX5_EVENT_TYPE_PATH_MIG: 351 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 352 case MLX5_EVENT_TYPE_COMM_EST: 353 case MLX5_EVENT_TYPE_SQ_DRAINED: 354 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 355 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 356 return eqe->data.qp_srq.type; 357 case MLX5_EVENT_TYPE_CQ_ERROR: 358 case MLX5_EVENT_TYPE_XRQ_ERROR: 359 return 0; 360 case MLX5_EVENT_TYPE_DCT_DRAINED: 361 case MLX5_EVENT_TYPE_DCT_KEY_VIOLATION: 362 return MLX5_EVENT_QUEUE_TYPE_DCT; 363 default: 364 return MLX5_GET(affiliated_event_header, &eqe->data, obj_type); 365 } 366 } 367 368 static u32 get_dec_obj_id(u64 obj_id) 369 { 370 return (obj_id & 0xffffffff); 371 } 372 373 /* 374 * As the obj_id in the firmware is not globally unique the object type 375 * must be considered upon checking for a valid object id. 376 * For that the opcode of the creator command is encoded as part of the obj_id. 377 */ 378 static u64 get_enc_obj_id(u32 opcode, u32 obj_id) 379 { 380 return ((u64)opcode << 32) | obj_id; 381 } 382 383 static u64 devx_get_obj_id(const void *in) 384 { 385 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode); 386 u64 obj_id; 387 388 switch (opcode) { 389 case MLX5_CMD_OP_MODIFY_GENERAL_OBJ: 390 case MLX5_CMD_OP_QUERY_GENERAL_OBJ: 391 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_GENERAL_OBJ | 392 MLX5_GET(general_obj_in_cmd_hdr, in, 393 obj_type) << 16, 394 MLX5_GET(general_obj_in_cmd_hdr, in, 395 obj_id)); 396 break; 397 case MLX5_CMD_OP_QUERY_MKEY: 398 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_MKEY, 399 MLX5_GET(query_mkey_in, in, 400 mkey_index)); 401 break; 402 case MLX5_CMD_OP_QUERY_CQ: 403 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_CQ, 404 MLX5_GET(query_cq_in, in, cqn)); 405 break; 406 case MLX5_CMD_OP_MODIFY_CQ: 407 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_CQ, 408 MLX5_GET(modify_cq_in, in, cqn)); 409 break; 410 case MLX5_CMD_OP_QUERY_SQ: 411 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_SQ, 412 MLX5_GET(query_sq_in, in, sqn)); 413 break; 414 case MLX5_CMD_OP_MODIFY_SQ: 415 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_SQ, 416 MLX5_GET(modify_sq_in, in, sqn)); 417 break; 418 case MLX5_CMD_OP_QUERY_RQ: 419 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RQ, 420 MLX5_GET(query_rq_in, in, rqn)); 421 break; 422 case MLX5_CMD_OP_MODIFY_RQ: 423 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RQ, 424 MLX5_GET(modify_rq_in, in, rqn)); 425 break; 426 case MLX5_CMD_OP_QUERY_RMP: 427 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RMP, 428 MLX5_GET(query_rmp_in, in, rmpn)); 429 break; 430 case MLX5_CMD_OP_MODIFY_RMP: 431 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RMP, 432 MLX5_GET(modify_rmp_in, in, rmpn)); 433 break; 434 case MLX5_CMD_OP_QUERY_RQT: 435 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RQT, 436 MLX5_GET(query_rqt_in, in, rqtn)); 437 break; 438 case MLX5_CMD_OP_MODIFY_RQT: 439 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RQT, 440 MLX5_GET(modify_rqt_in, in, rqtn)); 441 break; 442 case MLX5_CMD_OP_QUERY_TIR: 443 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_TIR, 444 MLX5_GET(query_tir_in, in, tirn)); 445 break; 446 case MLX5_CMD_OP_MODIFY_TIR: 447 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_TIR, 448 MLX5_GET(modify_tir_in, in, tirn)); 449 break; 450 case MLX5_CMD_OP_QUERY_TIS: 451 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_TIS, 452 MLX5_GET(query_tis_in, in, tisn)); 453 break; 454 case MLX5_CMD_OP_MODIFY_TIS: 455 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_TIS, 456 MLX5_GET(modify_tis_in, in, tisn)); 457 break; 458 case MLX5_CMD_OP_QUERY_FLOW_TABLE: 459 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_FLOW_TABLE, 460 MLX5_GET(query_flow_table_in, in, 461 table_id)); 462 break; 463 case MLX5_CMD_OP_MODIFY_FLOW_TABLE: 464 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_FLOW_TABLE, 465 MLX5_GET(modify_flow_table_in, in, 466 table_id)); 467 break; 468 case MLX5_CMD_OP_QUERY_FLOW_GROUP: 469 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_FLOW_GROUP, 470 MLX5_GET(query_flow_group_in, in, 471 group_id)); 472 break; 473 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY: 474 obj_id = get_enc_obj_id(MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY, 475 MLX5_GET(query_fte_in, in, 476 flow_index)); 477 break; 478 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY: 479 obj_id = get_enc_obj_id(MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY, 480 MLX5_GET(set_fte_in, in, flow_index)); 481 break; 482 case MLX5_CMD_OP_QUERY_Q_COUNTER: 483 obj_id = get_enc_obj_id(MLX5_CMD_OP_ALLOC_Q_COUNTER, 484 MLX5_GET(query_q_counter_in, in, 485 counter_set_id)); 486 break; 487 case MLX5_CMD_OP_QUERY_FLOW_COUNTER: 488 obj_id = get_enc_obj_id(MLX5_CMD_OP_ALLOC_FLOW_COUNTER, 489 MLX5_GET(query_flow_counter_in, in, 490 flow_counter_id)); 491 break; 492 case MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT: 493 obj_id = get_enc_obj_id(MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT, 494 MLX5_GET(general_obj_in_cmd_hdr, in, 495 obj_id)); 496 break; 497 case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT: 498 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT, 499 MLX5_GET(query_scheduling_element_in, 500 in, scheduling_element_id)); 501 break; 502 case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT: 503 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT, 504 MLX5_GET(modify_scheduling_element_in, 505 in, scheduling_element_id)); 506 break; 507 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT: 508 obj_id = get_enc_obj_id(MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT, 509 MLX5_GET(add_vxlan_udp_dport_in, in, 510 vxlan_udp_port)); 511 break; 512 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY: 513 obj_id = get_enc_obj_id(MLX5_CMD_OP_SET_L2_TABLE_ENTRY, 514 MLX5_GET(query_l2_table_entry_in, in, 515 table_index)); 516 break; 517 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY: 518 obj_id = get_enc_obj_id(MLX5_CMD_OP_SET_L2_TABLE_ENTRY, 519 MLX5_GET(set_l2_table_entry_in, in, 520 table_index)); 521 break; 522 case MLX5_CMD_OP_QUERY_QP: 523 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 524 MLX5_GET(query_qp_in, in, qpn)); 525 break; 526 case MLX5_CMD_OP_RST2INIT_QP: 527 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 528 MLX5_GET(rst2init_qp_in, in, qpn)); 529 break; 530 case MLX5_CMD_OP_INIT2RTR_QP: 531 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 532 MLX5_GET(init2rtr_qp_in, in, qpn)); 533 break; 534 case MLX5_CMD_OP_RTR2RTS_QP: 535 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 536 MLX5_GET(rtr2rts_qp_in, in, qpn)); 537 break; 538 case MLX5_CMD_OP_RTS2RTS_QP: 539 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 540 MLX5_GET(rts2rts_qp_in, in, qpn)); 541 break; 542 case MLX5_CMD_OP_SQERR2RTS_QP: 543 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 544 MLX5_GET(sqerr2rts_qp_in, in, qpn)); 545 break; 546 case MLX5_CMD_OP_2ERR_QP: 547 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 548 MLX5_GET(qp_2err_in, in, qpn)); 549 break; 550 case MLX5_CMD_OP_2RST_QP: 551 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 552 MLX5_GET(qp_2rst_in, in, qpn)); 553 break; 554 case MLX5_CMD_OP_QUERY_DCT: 555 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_DCT, 556 MLX5_GET(query_dct_in, in, dctn)); 557 break; 558 case MLX5_CMD_OP_QUERY_XRQ: 559 case MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY: 560 case MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS: 561 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_XRQ, 562 MLX5_GET(query_xrq_in, in, xrqn)); 563 break; 564 case MLX5_CMD_OP_QUERY_XRC_SRQ: 565 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_XRC_SRQ, 566 MLX5_GET(query_xrc_srq_in, in, 567 xrc_srqn)); 568 break; 569 case MLX5_CMD_OP_ARM_XRC_SRQ: 570 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_XRC_SRQ, 571 MLX5_GET(arm_xrc_srq_in, in, xrc_srqn)); 572 break; 573 case MLX5_CMD_OP_QUERY_SRQ: 574 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_SRQ, 575 MLX5_GET(query_srq_in, in, srqn)); 576 break; 577 case MLX5_CMD_OP_ARM_RQ: 578 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_RQ, 579 MLX5_GET(arm_rq_in, in, srq_number)); 580 break; 581 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION: 582 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_DCT, 583 MLX5_GET(drain_dct_in, in, dctn)); 584 break; 585 case MLX5_CMD_OP_ARM_XRQ: 586 case MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY: 587 case MLX5_CMD_OP_RELEASE_XRQ_ERROR: 588 case MLX5_CMD_OP_MODIFY_XRQ: 589 obj_id = get_enc_obj_id(MLX5_CMD_OP_CREATE_XRQ, 590 MLX5_GET(arm_xrq_in, in, xrqn)); 591 break; 592 case MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT: 593 obj_id = get_enc_obj_id 594 (MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT, 595 MLX5_GET(query_packet_reformat_context_in, 596 in, packet_reformat_id)); 597 break; 598 default: 599 obj_id = 0; 600 } 601 602 return obj_id; 603 } 604 605 static bool devx_is_valid_obj_id(struct uverbs_attr_bundle *attrs, 606 struct ib_uobject *uobj, const void *in) 607 { 608 struct mlx5_ib_dev *dev = mlx5_udata_to_mdev(&attrs->driver_udata); 609 u64 obj_id = devx_get_obj_id(in); 610 611 if (!obj_id) 612 return false; 613 614 switch (uobj_get_object_id(uobj)) { 615 case UVERBS_OBJECT_CQ: 616 return get_enc_obj_id(MLX5_CMD_OP_CREATE_CQ, 617 to_mcq(uobj->object)->mcq.cqn) == 618 obj_id; 619 620 case UVERBS_OBJECT_SRQ: 621 { 622 struct mlx5_core_srq *srq = &(to_msrq(uobj->object)->msrq); 623 u16 opcode; 624 625 switch (srq->common.res) { 626 case MLX5_RES_XSRQ: 627 opcode = MLX5_CMD_OP_CREATE_XRC_SRQ; 628 break; 629 case MLX5_RES_XRQ: 630 opcode = MLX5_CMD_OP_CREATE_XRQ; 631 break; 632 default: 633 if (!dev->mdev->issi) 634 opcode = MLX5_CMD_OP_CREATE_SRQ; 635 else 636 opcode = MLX5_CMD_OP_CREATE_RMP; 637 } 638 639 return get_enc_obj_id(opcode, 640 to_msrq(uobj->object)->msrq.srqn) == 641 obj_id; 642 } 643 644 case UVERBS_OBJECT_QP: 645 { 646 struct mlx5_ib_qp *qp = to_mqp(uobj->object); 647 enum ib_qp_type qp_type = qp->ibqp.qp_type; 648 649 if (qp_type == IB_QPT_RAW_PACKET || 650 (qp->flags & MLX5_IB_QP_UNDERLAY)) { 651 struct mlx5_ib_raw_packet_qp *raw_packet_qp = 652 &qp->raw_packet_qp; 653 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 654 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 655 656 return (get_enc_obj_id(MLX5_CMD_OP_CREATE_RQ, 657 rq->base.mqp.qpn) == obj_id || 658 get_enc_obj_id(MLX5_CMD_OP_CREATE_SQ, 659 sq->base.mqp.qpn) == obj_id || 660 get_enc_obj_id(MLX5_CMD_OP_CREATE_TIR, 661 rq->tirn) == obj_id || 662 get_enc_obj_id(MLX5_CMD_OP_CREATE_TIS, 663 sq->tisn) == obj_id); 664 } 665 666 if (qp_type == MLX5_IB_QPT_DCT) 667 return get_enc_obj_id(MLX5_CMD_OP_CREATE_DCT, 668 qp->dct.mdct.dctn) == obj_id; 669 670 return get_enc_obj_id(MLX5_CMD_OP_CREATE_QP, 671 qp->ibqp.qp_num) == obj_id; 672 } 673 674 case UVERBS_OBJECT_WQ: 675 return get_enc_obj_id(MLX5_CMD_OP_CREATE_RQ, 676 to_mrwq(uobj->object)->core_qp.qpn) == 677 obj_id; 678 679 case UVERBS_OBJECT_RWQ_IND_TBL: 680 return get_enc_obj_id(MLX5_CMD_OP_CREATE_RQT, 681 to_mrwq_ind_table(uobj->object)->rqtn) == 682 obj_id; 683 684 case MLX5_IB_OBJECT_DEVX_OBJ: 685 return ((struct devx_obj *)uobj->object)->obj_id == obj_id; 686 687 default: 688 return false; 689 } 690 } 691 692 static void devx_set_umem_valid(const void *in) 693 { 694 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode); 695 696 switch (opcode) { 697 case MLX5_CMD_OP_CREATE_MKEY: 698 MLX5_SET(create_mkey_in, in, mkey_umem_valid, 1); 699 break; 700 case MLX5_CMD_OP_CREATE_CQ: 701 { 702 void *cqc; 703 704 MLX5_SET(create_cq_in, in, cq_umem_valid, 1); 705 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); 706 MLX5_SET(cqc, cqc, dbr_umem_valid, 1); 707 break; 708 } 709 case MLX5_CMD_OP_CREATE_QP: 710 { 711 void *qpc; 712 713 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 714 MLX5_SET(qpc, qpc, dbr_umem_valid, 1); 715 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 716 break; 717 } 718 719 case MLX5_CMD_OP_CREATE_RQ: 720 { 721 void *rqc, *wq; 722 723 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 724 wq = MLX5_ADDR_OF(rqc, rqc, wq); 725 MLX5_SET(wq, wq, dbr_umem_valid, 1); 726 MLX5_SET(wq, wq, wq_umem_valid, 1); 727 break; 728 } 729 730 case MLX5_CMD_OP_CREATE_SQ: 731 { 732 void *sqc, *wq; 733 734 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 735 wq = MLX5_ADDR_OF(sqc, sqc, wq); 736 MLX5_SET(wq, wq, dbr_umem_valid, 1); 737 MLX5_SET(wq, wq, wq_umem_valid, 1); 738 break; 739 } 740 741 case MLX5_CMD_OP_MODIFY_CQ: 742 MLX5_SET(modify_cq_in, in, cq_umem_valid, 1); 743 break; 744 745 case MLX5_CMD_OP_CREATE_RMP: 746 { 747 void *rmpc, *wq; 748 749 rmpc = MLX5_ADDR_OF(create_rmp_in, in, ctx); 750 wq = MLX5_ADDR_OF(rmpc, rmpc, wq); 751 MLX5_SET(wq, wq, dbr_umem_valid, 1); 752 MLX5_SET(wq, wq, wq_umem_valid, 1); 753 break; 754 } 755 756 case MLX5_CMD_OP_CREATE_XRQ: 757 { 758 void *xrqc, *wq; 759 760 xrqc = MLX5_ADDR_OF(create_xrq_in, in, xrq_context); 761 wq = MLX5_ADDR_OF(xrqc, xrqc, wq); 762 MLX5_SET(wq, wq, dbr_umem_valid, 1); 763 MLX5_SET(wq, wq, wq_umem_valid, 1); 764 break; 765 } 766 767 case MLX5_CMD_OP_CREATE_XRC_SRQ: 768 { 769 void *xrc_srqc; 770 771 MLX5_SET(create_xrc_srq_in, in, xrc_srq_umem_valid, 1); 772 xrc_srqc = MLX5_ADDR_OF(create_xrc_srq_in, in, 773 xrc_srq_context_entry); 774 MLX5_SET(xrc_srqc, xrc_srqc, dbr_umem_valid, 1); 775 break; 776 } 777 778 default: 779 return; 780 } 781 } 782 783 static bool devx_is_obj_create_cmd(const void *in, u16 *opcode) 784 { 785 *opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode); 786 787 switch (*opcode) { 788 case MLX5_CMD_OP_CREATE_GENERAL_OBJ: 789 case MLX5_CMD_OP_CREATE_MKEY: 790 case MLX5_CMD_OP_CREATE_CQ: 791 case MLX5_CMD_OP_ALLOC_PD: 792 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN: 793 case MLX5_CMD_OP_CREATE_RMP: 794 case MLX5_CMD_OP_CREATE_SQ: 795 case MLX5_CMD_OP_CREATE_RQ: 796 case MLX5_CMD_OP_CREATE_RQT: 797 case MLX5_CMD_OP_CREATE_TIR: 798 case MLX5_CMD_OP_CREATE_TIS: 799 case MLX5_CMD_OP_ALLOC_Q_COUNTER: 800 case MLX5_CMD_OP_CREATE_FLOW_TABLE: 801 case MLX5_CMD_OP_CREATE_FLOW_GROUP: 802 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER: 803 case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT: 804 case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT: 805 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT: 806 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT: 807 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY: 808 case MLX5_CMD_OP_CREATE_QP: 809 case MLX5_CMD_OP_CREATE_SRQ: 810 case MLX5_CMD_OP_CREATE_XRC_SRQ: 811 case MLX5_CMD_OP_CREATE_DCT: 812 case MLX5_CMD_OP_CREATE_XRQ: 813 case MLX5_CMD_OP_ATTACH_TO_MCG: 814 case MLX5_CMD_OP_ALLOC_XRCD: 815 return true; 816 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY: 817 { 818 u16 op_mod = MLX5_GET(set_fte_in, in, op_mod); 819 if (op_mod == 0) 820 return true; 821 return false; 822 } 823 case MLX5_CMD_OP_CREATE_PSV: 824 { 825 u8 num_psv = MLX5_GET(create_psv_in, in, num_psv); 826 827 if (num_psv == 1) 828 return true; 829 return false; 830 } 831 default: 832 return false; 833 } 834 } 835 836 static bool devx_is_obj_modify_cmd(const void *in) 837 { 838 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode); 839 840 switch (opcode) { 841 case MLX5_CMD_OP_MODIFY_GENERAL_OBJ: 842 case MLX5_CMD_OP_MODIFY_CQ: 843 case MLX5_CMD_OP_MODIFY_RMP: 844 case MLX5_CMD_OP_MODIFY_SQ: 845 case MLX5_CMD_OP_MODIFY_RQ: 846 case MLX5_CMD_OP_MODIFY_RQT: 847 case MLX5_CMD_OP_MODIFY_TIR: 848 case MLX5_CMD_OP_MODIFY_TIS: 849 case MLX5_CMD_OP_MODIFY_FLOW_TABLE: 850 case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT: 851 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT: 852 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY: 853 case MLX5_CMD_OP_RST2INIT_QP: 854 case MLX5_CMD_OP_INIT2RTR_QP: 855 case MLX5_CMD_OP_RTR2RTS_QP: 856 case MLX5_CMD_OP_RTS2RTS_QP: 857 case MLX5_CMD_OP_SQERR2RTS_QP: 858 case MLX5_CMD_OP_2ERR_QP: 859 case MLX5_CMD_OP_2RST_QP: 860 case MLX5_CMD_OP_ARM_XRC_SRQ: 861 case MLX5_CMD_OP_ARM_RQ: 862 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION: 863 case MLX5_CMD_OP_ARM_XRQ: 864 case MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY: 865 case MLX5_CMD_OP_RELEASE_XRQ_ERROR: 866 case MLX5_CMD_OP_MODIFY_XRQ: 867 return true; 868 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY: 869 { 870 u16 op_mod = MLX5_GET(set_fte_in, in, op_mod); 871 872 if (op_mod == 1) 873 return true; 874 return false; 875 } 876 default: 877 return false; 878 } 879 } 880 881 static bool devx_is_obj_query_cmd(const void *in) 882 { 883 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode); 884 885 switch (opcode) { 886 case MLX5_CMD_OP_QUERY_GENERAL_OBJ: 887 case MLX5_CMD_OP_QUERY_MKEY: 888 case MLX5_CMD_OP_QUERY_CQ: 889 case MLX5_CMD_OP_QUERY_RMP: 890 case MLX5_CMD_OP_QUERY_SQ: 891 case MLX5_CMD_OP_QUERY_RQ: 892 case MLX5_CMD_OP_QUERY_RQT: 893 case MLX5_CMD_OP_QUERY_TIR: 894 case MLX5_CMD_OP_QUERY_TIS: 895 case MLX5_CMD_OP_QUERY_Q_COUNTER: 896 case MLX5_CMD_OP_QUERY_FLOW_TABLE: 897 case MLX5_CMD_OP_QUERY_FLOW_GROUP: 898 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY: 899 case MLX5_CMD_OP_QUERY_FLOW_COUNTER: 900 case MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT: 901 case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT: 902 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY: 903 case MLX5_CMD_OP_QUERY_QP: 904 case MLX5_CMD_OP_QUERY_SRQ: 905 case MLX5_CMD_OP_QUERY_XRC_SRQ: 906 case MLX5_CMD_OP_QUERY_DCT: 907 case MLX5_CMD_OP_QUERY_XRQ: 908 case MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY: 909 case MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS: 910 case MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT: 911 return true; 912 default: 913 return false; 914 } 915 } 916 917 static bool devx_is_whitelist_cmd(void *in) 918 { 919 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode); 920 921 switch (opcode) { 922 case MLX5_CMD_OP_QUERY_HCA_CAP: 923 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT: 924 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT: 925 return true; 926 default: 927 return false; 928 } 929 } 930 931 static int devx_get_uid(struct mlx5_ib_ucontext *c, void *cmd_in) 932 { 933 if (devx_is_whitelist_cmd(cmd_in)) { 934 if (c->devx_uid) 935 return c->devx_uid; 936 937 return -EOPNOTSUPP; 938 } 939 940 if (!c->devx_uid) 941 return -EINVAL; 942 943 return c->devx_uid; 944 } 945 946 static bool devx_is_general_cmd(void *in, struct mlx5_ib_dev *dev) 947 { 948 u16 opcode = MLX5_GET(general_obj_in_cmd_hdr, in, opcode); 949 950 /* Pass all cmds for vhca_tunnel as general, tracking is done in FW */ 951 if ((MLX5_CAP_GEN_64(dev->mdev, vhca_tunnel_commands) && 952 MLX5_GET(general_obj_in_cmd_hdr, in, vhca_tunnel_id)) || 953 (opcode >= MLX5_CMD_OP_GENERAL_START && 954 opcode < MLX5_CMD_OP_GENERAL_END)) 955 return true; 956 957 switch (opcode) { 958 case MLX5_CMD_OP_QUERY_HCA_CAP: 959 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT: 960 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT: 961 case MLX5_CMD_OP_QUERY_VPORT_STATE: 962 case MLX5_CMD_OP_QUERY_ADAPTER: 963 case MLX5_CMD_OP_QUERY_ISSI: 964 case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT: 965 case MLX5_CMD_OP_QUERY_ROCE_ADDRESS: 966 case MLX5_CMD_OP_QUERY_VNIC_ENV: 967 case MLX5_CMD_OP_QUERY_VPORT_COUNTER: 968 case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG: 969 case MLX5_CMD_OP_NOP: 970 case MLX5_CMD_OP_QUERY_CONG_STATUS: 971 case MLX5_CMD_OP_QUERY_CONG_PARAMS: 972 case MLX5_CMD_OP_QUERY_CONG_STATISTICS: 973 case MLX5_CMD_OP_QUERY_LAG: 974 return true; 975 default: 976 return false; 977 } 978 } 979 980 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_QUERY_EQN)( 981 struct uverbs_attr_bundle *attrs) 982 { 983 struct mlx5_ib_ucontext *c; 984 struct mlx5_ib_dev *dev; 985 int user_vector; 986 int dev_eqn; 987 unsigned int irqn; 988 int err; 989 990 if (uverbs_copy_from(&user_vector, attrs, 991 MLX5_IB_ATTR_DEVX_QUERY_EQN_USER_VEC)) 992 return -EFAULT; 993 994 c = devx_ufile2uctx(attrs); 995 if (IS_ERR(c)) 996 return PTR_ERR(c); 997 dev = to_mdev(c->ibucontext.device); 998 999 err = mlx5_vector2eqn(dev->mdev, user_vector, &dev_eqn, &irqn); 1000 if (err < 0) 1001 return err; 1002 1003 if (uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_QUERY_EQN_DEV_EQN, 1004 &dev_eqn, sizeof(dev_eqn))) 1005 return -EFAULT; 1006 1007 return 0; 1008 } 1009 1010 /* 1011 *Security note: 1012 * The hardware protection mechanism works like this: Each device object that 1013 * is subject to UAR doorbells (QP/SQ/CQ) gets a UAR ID (called uar_page in 1014 * the device specification manual) upon its creation. Then upon doorbell, 1015 * hardware fetches the object context for which the doorbell was rang, and 1016 * validates that the UAR through which the DB was rang matches the UAR ID 1017 * of the object. 1018 * If no match the doorbell is silently ignored by the hardware. Of course, 1019 * the user cannot ring a doorbell on a UAR that was not mapped to it. 1020 * Now in devx, as the devx kernel does not manipulate the QP/SQ/CQ command 1021 * mailboxes (except tagging them with UID), we expose to the user its UAR 1022 * ID, so it can embed it in these objects in the expected specification 1023 * format. So the only thing the user can do is hurt itself by creating a 1024 * QP/SQ/CQ with a UAR ID other than his, and then in this case other users 1025 * may ring a doorbell on its objects. 1026 * The consequence of that will be that another user can schedule a QP/SQ 1027 * of the buggy user for execution (just insert it to the hardware schedule 1028 * queue or arm its CQ for event generation), no further harm is expected. 1029 */ 1030 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_QUERY_UAR)( 1031 struct uverbs_attr_bundle *attrs) 1032 { 1033 struct mlx5_ib_ucontext *c; 1034 struct mlx5_ib_dev *dev; 1035 u32 user_idx; 1036 s32 dev_idx; 1037 1038 c = devx_ufile2uctx(attrs); 1039 if (IS_ERR(c)) 1040 return PTR_ERR(c); 1041 dev = to_mdev(c->ibucontext.device); 1042 1043 if (uverbs_copy_from(&user_idx, attrs, 1044 MLX5_IB_ATTR_DEVX_QUERY_UAR_USER_IDX)) 1045 return -EFAULT; 1046 1047 dev_idx = bfregn_to_uar_index(dev, &c->bfregi, user_idx, true); 1048 if (dev_idx < 0) 1049 return dev_idx; 1050 1051 if (uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_QUERY_UAR_DEV_IDX, 1052 &dev_idx, sizeof(dev_idx))) 1053 return -EFAULT; 1054 1055 return 0; 1056 } 1057 1058 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_OTHER)( 1059 struct uverbs_attr_bundle *attrs) 1060 { 1061 struct mlx5_ib_ucontext *c; 1062 struct mlx5_ib_dev *dev; 1063 void *cmd_in = uverbs_attr_get_alloced_ptr( 1064 attrs, MLX5_IB_ATTR_DEVX_OTHER_CMD_IN); 1065 int cmd_out_len = uverbs_attr_get_len(attrs, 1066 MLX5_IB_ATTR_DEVX_OTHER_CMD_OUT); 1067 void *cmd_out; 1068 int err; 1069 int uid; 1070 1071 c = devx_ufile2uctx(attrs); 1072 if (IS_ERR(c)) 1073 return PTR_ERR(c); 1074 dev = to_mdev(c->ibucontext.device); 1075 1076 uid = devx_get_uid(c, cmd_in); 1077 if (uid < 0) 1078 return uid; 1079 1080 /* Only white list of some general HCA commands are allowed for this method. */ 1081 if (!devx_is_general_cmd(cmd_in, dev)) 1082 return -EINVAL; 1083 1084 cmd_out = uverbs_zalloc(attrs, cmd_out_len); 1085 if (IS_ERR(cmd_out)) 1086 return PTR_ERR(cmd_out); 1087 1088 MLX5_SET(general_obj_in_cmd_hdr, cmd_in, uid, uid); 1089 err = mlx5_cmd_exec(dev->mdev, cmd_in, 1090 uverbs_attr_get_len(attrs, MLX5_IB_ATTR_DEVX_OTHER_CMD_IN), 1091 cmd_out, cmd_out_len); 1092 if (err) 1093 return err; 1094 1095 return uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_OTHER_CMD_OUT, cmd_out, 1096 cmd_out_len); 1097 } 1098 1099 static void devx_obj_build_destroy_cmd(void *in, void *out, void *din, 1100 u32 *dinlen, 1101 u32 *obj_id) 1102 { 1103 u16 obj_type = MLX5_GET(general_obj_in_cmd_hdr, in, obj_type); 1104 u16 uid = MLX5_GET(general_obj_in_cmd_hdr, in, uid); 1105 1106 *obj_id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 1107 *dinlen = MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr); 1108 1109 MLX5_SET(general_obj_in_cmd_hdr, din, obj_id, *obj_id); 1110 MLX5_SET(general_obj_in_cmd_hdr, din, uid, uid); 1111 1112 switch (MLX5_GET(general_obj_in_cmd_hdr, in, opcode)) { 1113 case MLX5_CMD_OP_CREATE_GENERAL_OBJ: 1114 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, MLX5_CMD_OP_DESTROY_GENERAL_OBJ); 1115 MLX5_SET(general_obj_in_cmd_hdr, din, obj_type, obj_type); 1116 break; 1117 1118 case MLX5_CMD_OP_CREATE_UMEM: 1119 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, 1120 MLX5_CMD_OP_DESTROY_UMEM); 1121 break; 1122 case MLX5_CMD_OP_CREATE_MKEY: 1123 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, MLX5_CMD_OP_DESTROY_MKEY); 1124 break; 1125 case MLX5_CMD_OP_CREATE_CQ: 1126 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, MLX5_CMD_OP_DESTROY_CQ); 1127 break; 1128 case MLX5_CMD_OP_ALLOC_PD: 1129 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, MLX5_CMD_OP_DEALLOC_PD); 1130 break; 1131 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN: 1132 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, 1133 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN); 1134 break; 1135 case MLX5_CMD_OP_CREATE_RMP: 1136 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, MLX5_CMD_OP_DESTROY_RMP); 1137 break; 1138 case MLX5_CMD_OP_CREATE_SQ: 1139 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, MLX5_CMD_OP_DESTROY_SQ); 1140 break; 1141 case MLX5_CMD_OP_CREATE_RQ: 1142 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, MLX5_CMD_OP_DESTROY_RQ); 1143 break; 1144 case MLX5_CMD_OP_CREATE_RQT: 1145 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, MLX5_CMD_OP_DESTROY_RQT); 1146 break; 1147 case MLX5_CMD_OP_CREATE_TIR: 1148 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, MLX5_CMD_OP_DESTROY_TIR); 1149 break; 1150 case MLX5_CMD_OP_CREATE_TIS: 1151 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, MLX5_CMD_OP_DESTROY_TIS); 1152 break; 1153 case MLX5_CMD_OP_ALLOC_Q_COUNTER: 1154 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, 1155 MLX5_CMD_OP_DEALLOC_Q_COUNTER); 1156 break; 1157 case MLX5_CMD_OP_CREATE_FLOW_TABLE: 1158 *dinlen = MLX5_ST_SZ_BYTES(destroy_flow_table_in); 1159 *obj_id = MLX5_GET(create_flow_table_out, out, table_id); 1160 MLX5_SET(destroy_flow_table_in, din, other_vport, 1161 MLX5_GET(create_flow_table_in, in, other_vport)); 1162 MLX5_SET(destroy_flow_table_in, din, vport_number, 1163 MLX5_GET(create_flow_table_in, in, vport_number)); 1164 MLX5_SET(destroy_flow_table_in, din, table_type, 1165 MLX5_GET(create_flow_table_in, in, table_type)); 1166 MLX5_SET(destroy_flow_table_in, din, table_id, *obj_id); 1167 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, 1168 MLX5_CMD_OP_DESTROY_FLOW_TABLE); 1169 break; 1170 case MLX5_CMD_OP_CREATE_FLOW_GROUP: 1171 *dinlen = MLX5_ST_SZ_BYTES(destroy_flow_group_in); 1172 *obj_id = MLX5_GET(create_flow_group_out, out, group_id); 1173 MLX5_SET(destroy_flow_group_in, din, other_vport, 1174 MLX5_GET(create_flow_group_in, in, other_vport)); 1175 MLX5_SET(destroy_flow_group_in, din, vport_number, 1176 MLX5_GET(create_flow_group_in, in, vport_number)); 1177 MLX5_SET(destroy_flow_group_in, din, table_type, 1178 MLX5_GET(create_flow_group_in, in, table_type)); 1179 MLX5_SET(destroy_flow_group_in, din, table_id, 1180 MLX5_GET(create_flow_group_in, in, table_id)); 1181 MLX5_SET(destroy_flow_group_in, din, group_id, *obj_id); 1182 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, 1183 MLX5_CMD_OP_DESTROY_FLOW_GROUP); 1184 break; 1185 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY: 1186 *dinlen = MLX5_ST_SZ_BYTES(delete_fte_in); 1187 *obj_id = MLX5_GET(set_fte_in, in, flow_index); 1188 MLX5_SET(delete_fte_in, din, other_vport, 1189 MLX5_GET(set_fte_in, in, other_vport)); 1190 MLX5_SET(delete_fte_in, din, vport_number, 1191 MLX5_GET(set_fte_in, in, vport_number)); 1192 MLX5_SET(delete_fte_in, din, table_type, 1193 MLX5_GET(set_fte_in, in, table_type)); 1194 MLX5_SET(delete_fte_in, din, table_id, 1195 MLX5_GET(set_fte_in, in, table_id)); 1196 MLX5_SET(delete_fte_in, din, flow_index, *obj_id); 1197 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, 1198 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY); 1199 break; 1200 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER: 1201 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, 1202 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER); 1203 break; 1204 case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT: 1205 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, 1206 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT); 1207 break; 1208 case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT: 1209 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, 1210 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT); 1211 break; 1212 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT: 1213 *dinlen = MLX5_ST_SZ_BYTES(destroy_scheduling_element_in); 1214 *obj_id = MLX5_GET(create_scheduling_element_out, out, 1215 scheduling_element_id); 1216 MLX5_SET(destroy_scheduling_element_in, din, 1217 scheduling_hierarchy, 1218 MLX5_GET(create_scheduling_element_in, in, 1219 scheduling_hierarchy)); 1220 MLX5_SET(destroy_scheduling_element_in, din, 1221 scheduling_element_id, *obj_id); 1222 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, 1223 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT); 1224 break; 1225 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT: 1226 *dinlen = MLX5_ST_SZ_BYTES(delete_vxlan_udp_dport_in); 1227 *obj_id = MLX5_GET(add_vxlan_udp_dport_in, in, vxlan_udp_port); 1228 MLX5_SET(delete_vxlan_udp_dport_in, din, vxlan_udp_port, *obj_id); 1229 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, 1230 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT); 1231 break; 1232 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY: 1233 *dinlen = MLX5_ST_SZ_BYTES(delete_l2_table_entry_in); 1234 *obj_id = MLX5_GET(set_l2_table_entry_in, in, table_index); 1235 MLX5_SET(delete_l2_table_entry_in, din, table_index, *obj_id); 1236 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, 1237 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY); 1238 break; 1239 case MLX5_CMD_OP_CREATE_QP: 1240 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, MLX5_CMD_OP_DESTROY_QP); 1241 break; 1242 case MLX5_CMD_OP_CREATE_SRQ: 1243 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, MLX5_CMD_OP_DESTROY_SRQ); 1244 break; 1245 case MLX5_CMD_OP_CREATE_XRC_SRQ: 1246 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, 1247 MLX5_CMD_OP_DESTROY_XRC_SRQ); 1248 break; 1249 case MLX5_CMD_OP_CREATE_DCT: 1250 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, MLX5_CMD_OP_DESTROY_DCT); 1251 break; 1252 case MLX5_CMD_OP_CREATE_XRQ: 1253 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, MLX5_CMD_OP_DESTROY_XRQ); 1254 break; 1255 case MLX5_CMD_OP_ATTACH_TO_MCG: 1256 *dinlen = MLX5_ST_SZ_BYTES(detach_from_mcg_in); 1257 MLX5_SET(detach_from_mcg_in, din, qpn, 1258 MLX5_GET(attach_to_mcg_in, in, qpn)); 1259 memcpy(MLX5_ADDR_OF(detach_from_mcg_in, din, multicast_gid), 1260 MLX5_ADDR_OF(attach_to_mcg_in, in, multicast_gid), 1261 MLX5_FLD_SZ_BYTES(attach_to_mcg_in, multicast_gid)); 1262 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, MLX5_CMD_OP_DETACH_FROM_MCG); 1263 break; 1264 case MLX5_CMD_OP_ALLOC_XRCD: 1265 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, MLX5_CMD_OP_DEALLOC_XRCD); 1266 break; 1267 case MLX5_CMD_OP_CREATE_PSV: 1268 MLX5_SET(general_obj_in_cmd_hdr, din, opcode, 1269 MLX5_CMD_OP_DESTROY_PSV); 1270 MLX5_SET(destroy_psv_in, din, psvn, 1271 MLX5_GET(create_psv_out, out, psv0_index)); 1272 break; 1273 default: 1274 /* The entry must match to one of the devx_is_obj_create_cmd */ 1275 WARN_ON(true); 1276 break; 1277 } 1278 } 1279 1280 static int devx_handle_mkey_create(struct mlx5_ib_dev *dev, 1281 struct devx_obj *obj, 1282 void *in, int in_len) 1283 { 1284 int min_len = MLX5_BYTE_OFF(create_mkey_in, memory_key_mkey_entry) + 1285 MLX5_FLD_SZ_BYTES(create_mkey_in, 1286 memory_key_mkey_entry); 1287 void *mkc; 1288 u8 access_mode; 1289 1290 if (in_len < min_len) 1291 return -EINVAL; 1292 1293 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 1294 1295 access_mode = MLX5_GET(mkc, mkc, access_mode); 1296 access_mode |= MLX5_GET(mkc, mkc, access_mode_4_2) << 2; 1297 1298 if (access_mode == MLX5_ACCESS_MODE_KLM || 1299 access_mode == MLX5_ACCESS_MODE_KSM) { 1300 return 0; 1301 } 1302 1303 MLX5_SET(create_mkey_in, in, mkey_umem_valid, 1); 1304 return 0; 1305 } 1306 1307 static void devx_cleanup_subscription(struct mlx5_ib_dev *dev, 1308 struct devx_event_subscription *sub) 1309 { 1310 struct devx_event *event; 1311 struct devx_obj_event *xa_val_level2; 1312 1313 if (sub->is_cleaned) 1314 return; 1315 1316 sub->is_cleaned = 1; 1317 list_del_rcu(&sub->xa_list); 1318 1319 if (list_empty(&sub->obj_list)) 1320 return; 1321 1322 list_del_rcu(&sub->obj_list); 1323 /* check whether key level 1 for this obj_sub_list is empty */ 1324 event = xa_load(&dev->devx_event_table.event_xa, 1325 sub->xa_key_level1); 1326 WARN_ON(!event); 1327 1328 xa_val_level2 = xa_load(&event->object_ids, sub->xa_key_level2); 1329 if (list_empty(&xa_val_level2->obj_sub_list)) { 1330 xa_erase(&event->object_ids, 1331 sub->xa_key_level2); 1332 kfree_rcu(xa_val_level2, rcu); 1333 } 1334 } 1335 1336 static int devx_obj_cleanup(struct ib_uobject *uobject, 1337 enum rdma_remove_reason why, 1338 struct uverbs_attr_bundle *attrs) 1339 { 1340 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 1341 struct mlx5_devx_event_table *devx_event_table; 1342 struct devx_obj *obj = uobject->object; 1343 struct devx_event_subscription *sub_entry, *tmp; 1344 struct mlx5_ib_dev *dev; 1345 int ret; 1346 1347 dev = mlx5_udata_to_mdev(&attrs->driver_udata); 1348 if (obj->flags & DEVX_OBJ_FLAGS_DCT) 1349 ret = mlx5_core_destroy_dct(obj->ib_dev->mdev, &obj->core_dct); 1350 else if (obj->flags & DEVX_OBJ_FLAGS_CQ) 1351 ret = mlx5_core_destroy_cq(obj->ib_dev->mdev, &obj->core_cq); 1352 else 1353 ret = mlx5_cmd_exec(obj->ib_dev->mdev, obj->dinbox, 1354 obj->dinlen, out, sizeof(out)); 1355 if (ib_is_destroy_retryable(ret, why, uobject)) 1356 return ret; 1357 1358 devx_event_table = &dev->devx_event_table; 1359 1360 mutex_lock(&devx_event_table->event_xa_lock); 1361 list_for_each_entry_safe(sub_entry, tmp, &obj->event_sub, obj_list) 1362 devx_cleanup_subscription(dev, sub_entry); 1363 mutex_unlock(&devx_event_table->event_xa_lock); 1364 1365 kfree(obj); 1366 return ret; 1367 } 1368 1369 static void devx_cq_comp(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe) 1370 { 1371 struct devx_obj *obj = container_of(mcq, struct devx_obj, core_cq); 1372 struct mlx5_devx_event_table *table; 1373 struct devx_event *event; 1374 struct devx_obj_event *obj_event; 1375 u32 obj_id = mcq->cqn; 1376 1377 table = &obj->ib_dev->devx_event_table; 1378 rcu_read_lock(); 1379 event = xa_load(&table->event_xa, MLX5_EVENT_TYPE_COMP); 1380 if (!event) 1381 goto out; 1382 1383 obj_event = xa_load(&event->object_ids, obj_id); 1384 if (!obj_event) 1385 goto out; 1386 1387 dispatch_event_fd(&obj_event->obj_sub_list, eqe); 1388 out: 1389 rcu_read_unlock(); 1390 } 1391 1392 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_OBJ_CREATE)( 1393 struct uverbs_attr_bundle *attrs) 1394 { 1395 void *cmd_in = uverbs_attr_get_alloced_ptr(attrs, MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_IN); 1396 int cmd_out_len = uverbs_attr_get_len(attrs, 1397 MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_OUT); 1398 int cmd_in_len = uverbs_attr_get_len(attrs, 1399 MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_IN); 1400 void *cmd_out; 1401 struct ib_uobject *uobj = uverbs_attr_get_uobject( 1402 attrs, MLX5_IB_ATTR_DEVX_OBJ_CREATE_HANDLE); 1403 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context( 1404 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 1405 struct mlx5_ib_dev *dev = to_mdev(c->ibucontext.device); 1406 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 1407 struct devx_obj *obj; 1408 u16 obj_type = 0; 1409 int err; 1410 int uid; 1411 u32 obj_id; 1412 u16 opcode; 1413 1414 if (MLX5_GET(general_obj_in_cmd_hdr, cmd_in, vhca_tunnel_id)) 1415 return -EINVAL; 1416 1417 uid = devx_get_uid(c, cmd_in); 1418 if (uid < 0) 1419 return uid; 1420 1421 if (!devx_is_obj_create_cmd(cmd_in, &opcode)) 1422 return -EINVAL; 1423 1424 cmd_out = uverbs_zalloc(attrs, cmd_out_len); 1425 if (IS_ERR(cmd_out)) 1426 return PTR_ERR(cmd_out); 1427 1428 obj = kzalloc(sizeof(struct devx_obj), GFP_KERNEL); 1429 if (!obj) 1430 return -ENOMEM; 1431 1432 MLX5_SET(general_obj_in_cmd_hdr, cmd_in, uid, uid); 1433 if (opcode == MLX5_CMD_OP_CREATE_MKEY) { 1434 err = devx_handle_mkey_create(dev, obj, cmd_in, cmd_in_len); 1435 if (err) 1436 goto obj_free; 1437 } else { 1438 devx_set_umem_valid(cmd_in); 1439 } 1440 1441 if (opcode == MLX5_CMD_OP_CREATE_DCT) { 1442 obj->flags |= DEVX_OBJ_FLAGS_DCT; 1443 err = mlx5_core_create_dct(dev->mdev, &obj->core_dct, 1444 cmd_in, cmd_in_len, 1445 cmd_out, cmd_out_len); 1446 } else if (opcode == MLX5_CMD_OP_CREATE_CQ) { 1447 obj->flags |= DEVX_OBJ_FLAGS_CQ; 1448 obj->core_cq.comp = devx_cq_comp; 1449 err = mlx5_core_create_cq(dev->mdev, &obj->core_cq, 1450 cmd_in, cmd_in_len, cmd_out, 1451 cmd_out_len); 1452 } else { 1453 err = mlx5_cmd_exec(dev->mdev, cmd_in, 1454 cmd_in_len, 1455 cmd_out, cmd_out_len); 1456 } 1457 1458 if (err) 1459 goto obj_free; 1460 1461 if (opcode == MLX5_CMD_OP_ALLOC_FLOW_COUNTER) { 1462 u8 bulk = MLX5_GET(alloc_flow_counter_in, 1463 cmd_in, 1464 flow_counter_bulk); 1465 obj->flow_counter_bulk_size = 128UL * bulk; 1466 } 1467 1468 uobj->object = obj; 1469 INIT_LIST_HEAD(&obj->event_sub); 1470 obj->ib_dev = dev; 1471 devx_obj_build_destroy_cmd(cmd_in, cmd_out, obj->dinbox, &obj->dinlen, 1472 &obj_id); 1473 WARN_ON(obj->dinlen > MLX5_MAX_DESTROY_INBOX_SIZE_DW * sizeof(u32)); 1474 1475 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_OUT, cmd_out, cmd_out_len); 1476 if (err) 1477 goto obj_destroy; 1478 1479 if (opcode == MLX5_CMD_OP_CREATE_GENERAL_OBJ) 1480 obj_type = MLX5_GET(general_obj_in_cmd_hdr, cmd_in, obj_type); 1481 obj->obj_id = get_enc_obj_id(opcode | obj_type << 16, obj_id); 1482 1483 return 0; 1484 1485 obj_destroy: 1486 if (obj->flags & DEVX_OBJ_FLAGS_DCT) 1487 mlx5_core_destroy_dct(obj->ib_dev->mdev, &obj->core_dct); 1488 else if (obj->flags & DEVX_OBJ_FLAGS_CQ) 1489 mlx5_core_destroy_cq(obj->ib_dev->mdev, &obj->core_cq); 1490 else 1491 mlx5_cmd_exec(obj->ib_dev->mdev, obj->dinbox, obj->dinlen, out, 1492 sizeof(out)); 1493 obj_free: 1494 kfree(obj); 1495 return err; 1496 } 1497 1498 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_OBJ_MODIFY)( 1499 struct uverbs_attr_bundle *attrs) 1500 { 1501 void *cmd_in = uverbs_attr_get_alloced_ptr(attrs, MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_IN); 1502 int cmd_out_len = uverbs_attr_get_len(attrs, 1503 MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_OUT); 1504 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, 1505 MLX5_IB_ATTR_DEVX_OBJ_MODIFY_HANDLE); 1506 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context( 1507 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 1508 struct mlx5_ib_dev *mdev = to_mdev(c->ibucontext.device); 1509 void *cmd_out; 1510 int err; 1511 int uid; 1512 1513 if (MLX5_GET(general_obj_in_cmd_hdr, cmd_in, vhca_tunnel_id)) 1514 return -EINVAL; 1515 1516 uid = devx_get_uid(c, cmd_in); 1517 if (uid < 0) 1518 return uid; 1519 1520 if (!devx_is_obj_modify_cmd(cmd_in)) 1521 return -EINVAL; 1522 1523 if (!devx_is_valid_obj_id(attrs, uobj, cmd_in)) 1524 return -EINVAL; 1525 1526 cmd_out = uverbs_zalloc(attrs, cmd_out_len); 1527 if (IS_ERR(cmd_out)) 1528 return PTR_ERR(cmd_out); 1529 1530 MLX5_SET(general_obj_in_cmd_hdr, cmd_in, uid, uid); 1531 devx_set_umem_valid(cmd_in); 1532 1533 err = mlx5_cmd_exec(mdev->mdev, cmd_in, 1534 uverbs_attr_get_len(attrs, MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_IN), 1535 cmd_out, cmd_out_len); 1536 if (err) 1537 return err; 1538 1539 return uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_OUT, 1540 cmd_out, cmd_out_len); 1541 } 1542 1543 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_OBJ_QUERY)( 1544 struct uverbs_attr_bundle *attrs) 1545 { 1546 void *cmd_in = uverbs_attr_get_alloced_ptr(attrs, MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_IN); 1547 int cmd_out_len = uverbs_attr_get_len(attrs, 1548 MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_OUT); 1549 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, 1550 MLX5_IB_ATTR_DEVX_OBJ_QUERY_HANDLE); 1551 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context( 1552 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 1553 void *cmd_out; 1554 int err; 1555 int uid; 1556 struct mlx5_ib_dev *mdev = to_mdev(c->ibucontext.device); 1557 1558 if (MLX5_GET(general_obj_in_cmd_hdr, cmd_in, vhca_tunnel_id)) 1559 return -EINVAL; 1560 1561 uid = devx_get_uid(c, cmd_in); 1562 if (uid < 0) 1563 return uid; 1564 1565 if (!devx_is_obj_query_cmd(cmd_in)) 1566 return -EINVAL; 1567 1568 if (!devx_is_valid_obj_id(attrs, uobj, cmd_in)) 1569 return -EINVAL; 1570 1571 cmd_out = uverbs_zalloc(attrs, cmd_out_len); 1572 if (IS_ERR(cmd_out)) 1573 return PTR_ERR(cmd_out); 1574 1575 MLX5_SET(general_obj_in_cmd_hdr, cmd_in, uid, uid); 1576 err = mlx5_cmd_exec(mdev->mdev, cmd_in, 1577 uverbs_attr_get_len(attrs, MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_IN), 1578 cmd_out, cmd_out_len); 1579 if (err) 1580 return err; 1581 1582 return uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_OUT, 1583 cmd_out, cmd_out_len); 1584 } 1585 1586 struct devx_async_event_queue { 1587 spinlock_t lock; 1588 wait_queue_head_t poll_wait; 1589 struct list_head event_list; 1590 atomic_t bytes_in_use; 1591 u8 is_destroyed:1; 1592 }; 1593 1594 struct devx_async_cmd_event_file { 1595 struct ib_uobject uobj; 1596 struct devx_async_event_queue ev_queue; 1597 struct mlx5_async_ctx async_ctx; 1598 }; 1599 1600 static void devx_init_event_queue(struct devx_async_event_queue *ev_queue) 1601 { 1602 spin_lock_init(&ev_queue->lock); 1603 INIT_LIST_HEAD(&ev_queue->event_list); 1604 init_waitqueue_head(&ev_queue->poll_wait); 1605 atomic_set(&ev_queue->bytes_in_use, 0); 1606 ev_queue->is_destroyed = 0; 1607 } 1608 1609 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_ASYNC_CMD_FD_ALLOC)( 1610 struct uverbs_attr_bundle *attrs) 1611 { 1612 struct devx_async_cmd_event_file *ev_file; 1613 1614 struct ib_uobject *uobj = uverbs_attr_get_uobject( 1615 attrs, MLX5_IB_ATTR_DEVX_ASYNC_CMD_FD_ALLOC_HANDLE); 1616 struct mlx5_ib_dev *mdev = mlx5_udata_to_mdev(&attrs->driver_udata); 1617 1618 ev_file = container_of(uobj, struct devx_async_cmd_event_file, 1619 uobj); 1620 devx_init_event_queue(&ev_file->ev_queue); 1621 mlx5_cmd_init_async_ctx(mdev->mdev, &ev_file->async_ctx); 1622 return 0; 1623 } 1624 1625 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_ASYNC_EVENT_FD_ALLOC)( 1626 struct uverbs_attr_bundle *attrs) 1627 { 1628 struct ib_uobject *uobj = uverbs_attr_get_uobject( 1629 attrs, MLX5_IB_ATTR_DEVX_ASYNC_EVENT_FD_ALLOC_HANDLE); 1630 struct devx_async_event_file *ev_file; 1631 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context( 1632 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 1633 struct mlx5_ib_dev *dev = to_mdev(c->ibucontext.device); 1634 u32 flags; 1635 int err; 1636 1637 err = uverbs_get_flags32(&flags, attrs, 1638 MLX5_IB_ATTR_DEVX_ASYNC_EVENT_FD_ALLOC_FLAGS, 1639 MLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA); 1640 1641 if (err) 1642 return err; 1643 1644 ev_file = container_of(uobj, struct devx_async_event_file, 1645 uobj); 1646 spin_lock_init(&ev_file->lock); 1647 INIT_LIST_HEAD(&ev_file->event_list); 1648 init_waitqueue_head(&ev_file->poll_wait); 1649 if (flags & MLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA) 1650 ev_file->omit_data = 1; 1651 INIT_LIST_HEAD(&ev_file->subscribed_events_list); 1652 ev_file->dev = dev; 1653 get_device(&dev->ib_dev.dev); 1654 return 0; 1655 } 1656 1657 static void devx_query_callback(int status, struct mlx5_async_work *context) 1658 { 1659 struct devx_async_data *async_data = 1660 container_of(context, struct devx_async_data, cb_work); 1661 struct devx_async_cmd_event_file *ev_file = async_data->ev_file; 1662 struct devx_async_event_queue *ev_queue = &ev_file->ev_queue; 1663 unsigned long flags; 1664 1665 /* 1666 * Note that if the struct devx_async_cmd_event_file uobj begins to be 1667 * destroyed it will block at mlx5_cmd_cleanup_async_ctx() until this 1668 * routine returns, ensuring that it always remains valid here. 1669 */ 1670 spin_lock_irqsave(&ev_queue->lock, flags); 1671 list_add_tail(&async_data->list, &ev_queue->event_list); 1672 spin_unlock_irqrestore(&ev_queue->lock, flags); 1673 1674 wake_up_interruptible(&ev_queue->poll_wait); 1675 } 1676 1677 #define MAX_ASYNC_BYTES_IN_USE (1024 * 1024) /* 1MB */ 1678 1679 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_OBJ_ASYNC_QUERY)( 1680 struct uverbs_attr_bundle *attrs) 1681 { 1682 void *cmd_in = uverbs_attr_get_alloced_ptr(attrs, 1683 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_CMD_IN); 1684 struct ib_uobject *uobj = uverbs_attr_get_uobject( 1685 attrs, 1686 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_HANDLE); 1687 u16 cmd_out_len; 1688 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context( 1689 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 1690 struct ib_uobject *fd_uobj; 1691 int err; 1692 int uid; 1693 struct mlx5_ib_dev *mdev = to_mdev(c->ibucontext.device); 1694 struct devx_async_cmd_event_file *ev_file; 1695 struct devx_async_data *async_data; 1696 1697 if (MLX5_GET(general_obj_in_cmd_hdr, cmd_in, vhca_tunnel_id)) 1698 return -EINVAL; 1699 1700 uid = devx_get_uid(c, cmd_in); 1701 if (uid < 0) 1702 return uid; 1703 1704 if (!devx_is_obj_query_cmd(cmd_in)) 1705 return -EINVAL; 1706 1707 err = uverbs_get_const(&cmd_out_len, attrs, 1708 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_OUT_LEN); 1709 if (err) 1710 return err; 1711 1712 if (!devx_is_valid_obj_id(attrs, uobj, cmd_in)) 1713 return -EINVAL; 1714 1715 fd_uobj = uverbs_attr_get_uobject(attrs, 1716 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_FD); 1717 if (IS_ERR(fd_uobj)) 1718 return PTR_ERR(fd_uobj); 1719 1720 ev_file = container_of(fd_uobj, struct devx_async_cmd_event_file, 1721 uobj); 1722 1723 if (atomic_add_return(cmd_out_len, &ev_file->ev_queue.bytes_in_use) > 1724 MAX_ASYNC_BYTES_IN_USE) { 1725 atomic_sub(cmd_out_len, &ev_file->ev_queue.bytes_in_use); 1726 return -EAGAIN; 1727 } 1728 1729 async_data = kvzalloc(struct_size(async_data, hdr.out_data, 1730 cmd_out_len), GFP_KERNEL); 1731 if (!async_data) { 1732 err = -ENOMEM; 1733 goto sub_bytes; 1734 } 1735 1736 err = uverbs_copy_from(&async_data->hdr.wr_id, attrs, 1737 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_WR_ID); 1738 if (err) 1739 goto free_async; 1740 1741 async_data->cmd_out_len = cmd_out_len; 1742 async_data->mdev = mdev; 1743 async_data->ev_file = ev_file; 1744 1745 MLX5_SET(general_obj_in_cmd_hdr, cmd_in, uid, uid); 1746 err = mlx5_cmd_exec_cb(&ev_file->async_ctx, cmd_in, 1747 uverbs_attr_get_len(attrs, 1748 MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_CMD_IN), 1749 async_data->hdr.out_data, 1750 async_data->cmd_out_len, 1751 devx_query_callback, &async_data->cb_work); 1752 1753 if (err) 1754 goto free_async; 1755 1756 return 0; 1757 1758 free_async: 1759 kvfree(async_data); 1760 sub_bytes: 1761 atomic_sub(cmd_out_len, &ev_file->ev_queue.bytes_in_use); 1762 return err; 1763 } 1764 1765 static void 1766 subscribe_event_xa_dealloc(struct mlx5_devx_event_table *devx_event_table, 1767 u32 key_level1, 1768 bool is_level2, 1769 u32 key_level2) 1770 { 1771 struct devx_event *event; 1772 struct devx_obj_event *xa_val_level2; 1773 1774 /* Level 1 is valid for future use, no need to free */ 1775 if (!is_level2) 1776 return; 1777 1778 event = xa_load(&devx_event_table->event_xa, key_level1); 1779 WARN_ON(!event); 1780 1781 xa_val_level2 = xa_load(&event->object_ids, 1782 key_level2); 1783 if (list_empty(&xa_val_level2->obj_sub_list)) { 1784 xa_erase(&event->object_ids, 1785 key_level2); 1786 kfree_rcu(xa_val_level2, rcu); 1787 } 1788 } 1789 1790 static int 1791 subscribe_event_xa_alloc(struct mlx5_devx_event_table *devx_event_table, 1792 u32 key_level1, 1793 bool is_level2, 1794 u32 key_level2) 1795 { 1796 struct devx_obj_event *obj_event; 1797 struct devx_event *event; 1798 int err; 1799 1800 event = xa_load(&devx_event_table->event_xa, key_level1); 1801 if (!event) { 1802 event = kzalloc(sizeof(*event), GFP_KERNEL); 1803 if (!event) 1804 return -ENOMEM; 1805 1806 INIT_LIST_HEAD(&event->unaffiliated_list); 1807 xa_init_flags(&event->object_ids, 0); 1808 1809 err = xa_insert(&devx_event_table->event_xa, 1810 key_level1, 1811 event, 1812 GFP_KERNEL); 1813 if (err) { 1814 kfree(event); 1815 return err; 1816 } 1817 } 1818 1819 if (!is_level2) 1820 return 0; 1821 1822 obj_event = xa_load(&event->object_ids, key_level2); 1823 if (!obj_event) { 1824 obj_event = kzalloc(sizeof(*obj_event), GFP_KERNEL); 1825 if (!obj_event) 1826 /* Level1 is valid for future use, no need to free */ 1827 return -ENOMEM; 1828 1829 err = xa_insert(&event->object_ids, 1830 key_level2, 1831 obj_event, 1832 GFP_KERNEL); 1833 if (err) 1834 return err; 1835 INIT_LIST_HEAD(&obj_event->obj_sub_list); 1836 } 1837 1838 return 0; 1839 } 1840 1841 static bool is_valid_events_legacy(int num_events, u16 *event_type_num_list, 1842 struct devx_obj *obj) 1843 { 1844 int i; 1845 1846 for (i = 0; i < num_events; i++) { 1847 if (obj) { 1848 if (!is_legacy_obj_event_num(event_type_num_list[i])) 1849 return false; 1850 } else if (!is_legacy_unaffiliated_event_num( 1851 event_type_num_list[i])) { 1852 return false; 1853 } 1854 } 1855 1856 return true; 1857 } 1858 1859 #define MAX_SUPP_EVENT_NUM 255 1860 static bool is_valid_events(struct mlx5_core_dev *dev, 1861 int num_events, u16 *event_type_num_list, 1862 struct devx_obj *obj) 1863 { 1864 __be64 *aff_events; 1865 __be64 *unaff_events; 1866 int mask_entry; 1867 int mask_bit; 1868 int i; 1869 1870 if (MLX5_CAP_GEN(dev, event_cap)) { 1871 aff_events = (__be64 *)MLX5_CAP_DEV_EVENT(dev, 1872 user_affiliated_events); 1873 unaff_events = (__be64 *)MLX5_CAP_DEV_EVENT(dev, 1874 user_unaffiliated_events); 1875 } else { 1876 return is_valid_events_legacy(num_events, event_type_num_list, 1877 obj); 1878 } 1879 1880 for (i = 0; i < num_events; i++) { 1881 if (event_type_num_list[i] > MAX_SUPP_EVENT_NUM) 1882 return false; 1883 1884 mask_entry = event_type_num_list[i] / 64; 1885 mask_bit = event_type_num_list[i] % 64; 1886 1887 if (obj) { 1888 /* CQ completion */ 1889 if (event_type_num_list[i] == 0) 1890 continue; 1891 1892 if (!(be64_to_cpu(aff_events[mask_entry]) & 1893 (1ull << mask_bit))) 1894 return false; 1895 1896 continue; 1897 } 1898 1899 if (!(be64_to_cpu(unaff_events[mask_entry]) & 1900 (1ull << mask_bit))) 1901 return false; 1902 } 1903 1904 return true; 1905 } 1906 1907 #define MAX_NUM_EVENTS 16 1908 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_SUBSCRIBE_EVENT)( 1909 struct uverbs_attr_bundle *attrs) 1910 { 1911 struct ib_uobject *devx_uobj = uverbs_attr_get_uobject( 1912 attrs, 1913 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_OBJ_HANDLE); 1914 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context( 1915 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 1916 struct mlx5_ib_dev *dev = to_mdev(c->ibucontext.device); 1917 struct ib_uobject *fd_uobj; 1918 struct devx_obj *obj = NULL; 1919 struct devx_async_event_file *ev_file; 1920 struct mlx5_devx_event_table *devx_event_table = &dev->devx_event_table; 1921 u16 *event_type_num_list; 1922 struct devx_event_subscription *event_sub, *tmp_sub; 1923 struct list_head sub_list; 1924 int redirect_fd; 1925 bool use_eventfd = false; 1926 int num_events; 1927 u16 obj_type = 0; 1928 u64 cookie = 0; 1929 u32 obj_id = 0; 1930 int err; 1931 int i; 1932 1933 if (!c->devx_uid) 1934 return -EINVAL; 1935 1936 if (!IS_ERR(devx_uobj)) { 1937 obj = (struct devx_obj *)devx_uobj->object; 1938 if (obj) 1939 obj_id = get_dec_obj_id(obj->obj_id); 1940 } 1941 1942 fd_uobj = uverbs_attr_get_uobject(attrs, 1943 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_HANDLE); 1944 if (IS_ERR(fd_uobj)) 1945 return PTR_ERR(fd_uobj); 1946 1947 ev_file = container_of(fd_uobj, struct devx_async_event_file, 1948 uobj); 1949 1950 if (uverbs_attr_is_valid(attrs, 1951 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_NUM)) { 1952 err = uverbs_copy_from(&redirect_fd, attrs, 1953 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_NUM); 1954 if (err) 1955 return err; 1956 1957 use_eventfd = true; 1958 } 1959 1960 if (uverbs_attr_is_valid(attrs, 1961 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_COOKIE)) { 1962 if (use_eventfd) 1963 return -EINVAL; 1964 1965 err = uverbs_copy_from(&cookie, attrs, 1966 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_COOKIE); 1967 if (err) 1968 return err; 1969 } 1970 1971 num_events = uverbs_attr_ptr_get_array_size( 1972 attrs, MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_TYPE_NUM_LIST, 1973 sizeof(u16)); 1974 1975 if (num_events < 0) 1976 return num_events; 1977 1978 if (num_events > MAX_NUM_EVENTS) 1979 return -EINVAL; 1980 1981 event_type_num_list = uverbs_attr_get_alloced_ptr(attrs, 1982 MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_TYPE_NUM_LIST); 1983 1984 if (!is_valid_events(dev->mdev, num_events, event_type_num_list, obj)) 1985 return -EINVAL; 1986 1987 INIT_LIST_HEAD(&sub_list); 1988 1989 /* Protect from concurrent subscriptions to same XA entries to allow 1990 * both to succeed 1991 */ 1992 mutex_lock(&devx_event_table->event_xa_lock); 1993 for (i = 0; i < num_events; i++) { 1994 u32 key_level1; 1995 1996 if (obj) 1997 obj_type = get_dec_obj_type(obj, 1998 event_type_num_list[i]); 1999 key_level1 = event_type_num_list[i] | obj_type << 16; 2000 2001 err = subscribe_event_xa_alloc(devx_event_table, 2002 key_level1, 2003 obj, 2004 obj_id); 2005 if (err) 2006 goto err; 2007 2008 event_sub = kzalloc(sizeof(*event_sub), GFP_KERNEL); 2009 if (!event_sub) 2010 goto err; 2011 2012 event_sub->cookie = cookie; 2013 event_sub->ev_file = ev_file; 2014 event_sub->xa_key_level1 = key_level1; 2015 event_sub->xa_key_level2 = obj_id; 2016 INIT_LIST_HEAD(&event_sub->obj_list); 2017 2018 list_add_tail(&event_sub->event_list, &sub_list); 2019 uverbs_uobject_get(&ev_file->uobj); 2020 if (use_eventfd) { 2021 event_sub->eventfd = 2022 eventfd_ctx_fdget(redirect_fd); 2023 2024 if (IS_ERR(event_sub->eventfd)) { 2025 err = PTR_ERR(event_sub->eventfd); 2026 event_sub->eventfd = NULL; 2027 goto err; 2028 } 2029 } 2030 } 2031 2032 /* Once all the allocations and the XA data insertions were done we 2033 * can go ahead and add all the subscriptions to the relevant lists 2034 * without concern of a failure. 2035 */ 2036 list_for_each_entry_safe(event_sub, tmp_sub, &sub_list, event_list) { 2037 struct devx_event *event; 2038 struct devx_obj_event *obj_event; 2039 2040 list_del_init(&event_sub->event_list); 2041 2042 spin_lock_irq(&ev_file->lock); 2043 list_add_tail_rcu(&event_sub->file_list, 2044 &ev_file->subscribed_events_list); 2045 spin_unlock_irq(&ev_file->lock); 2046 2047 event = xa_load(&devx_event_table->event_xa, 2048 event_sub->xa_key_level1); 2049 WARN_ON(!event); 2050 2051 if (!obj) { 2052 list_add_tail_rcu(&event_sub->xa_list, 2053 &event->unaffiliated_list); 2054 continue; 2055 } 2056 2057 obj_event = xa_load(&event->object_ids, obj_id); 2058 WARN_ON(!obj_event); 2059 list_add_tail_rcu(&event_sub->xa_list, 2060 &obj_event->obj_sub_list); 2061 list_add_tail_rcu(&event_sub->obj_list, 2062 &obj->event_sub); 2063 } 2064 2065 mutex_unlock(&devx_event_table->event_xa_lock); 2066 return 0; 2067 2068 err: 2069 list_for_each_entry_safe(event_sub, tmp_sub, &sub_list, event_list) { 2070 list_del(&event_sub->event_list); 2071 2072 subscribe_event_xa_dealloc(devx_event_table, 2073 event_sub->xa_key_level1, 2074 obj, 2075 obj_id); 2076 2077 if (event_sub->eventfd) 2078 eventfd_ctx_put(event_sub->eventfd); 2079 uverbs_uobject_put(&event_sub->ev_file->uobj); 2080 kfree(event_sub); 2081 } 2082 2083 mutex_unlock(&devx_event_table->event_xa_lock); 2084 return err; 2085 } 2086 2087 /* 2088 * A DevX UMEM is mapped at an IOVA equal to the DMA address of its first 2089 * byte, the UMEM VA plays no part in choosing its page size or MTT list. 2090 */ 2091 static u64 devx_umem_start_dma_addr(struct ib_umem *umem) 2092 { 2093 return sg_dma_address(umem->sg_head.sgl) + ib_umem_offset(umem); 2094 } 2095 2096 static u64 devx_umem_dma_offset(struct ib_umem *umem, u64 pgsz) 2097 { 2098 return devx_umem_start_dma_addr(umem) & (pgsz - 1); 2099 } 2100 2101 static size_t devx_umem_num_dma_blocks(struct ib_umem *umem, u64 pgsz) 2102 { 2103 u64 iova = devx_umem_start_dma_addr(umem); 2104 2105 return (ALIGN(iova + umem->length, pgsz) - ALIGN_DOWN(iova, pgsz)) / 2106 pgsz; 2107 } 2108 2109 static u64 devx_umem_find_best_pgoff(struct ib_umem *umem, u64 pgsz_bitmap) 2110 { 2111 u64 iova = devx_umem_start_dma_addr(umem); 2112 u64 pgoff = ib_umem_offset(umem); 2113 u64 curr_base = ~0ULL; 2114 u64 curr_len = 0; 2115 u64 mask = 0; 2116 struct scatterlist *sg; 2117 unsigned int bits; 2118 u64 last_iova; 2119 u64 end; 2120 int i; 2121 2122 /* The best result is the smallest page size that results in the minimum 2123 * number of required pages. Compute the largest page size that could 2124 * work based on IOVA bits that don't change. 2125 */ 2126 if (check_add_overflow(umem->length - 1, iova, &last_iova)) 2127 return 0; 2128 bits = fls64(iova ^ last_iova); 2129 if (bits < 64) 2130 mask = pgsz_bitmap & GENMASK_ULL(63, bits); 2131 2132 for_each_sg(umem->sg_head.sgl, sg, umem->nmap, i) { 2133 /* If the current entry is physically contiguous with the 2134 * previous one, no need to take its start addresses into 2135 * consideration. 2136 */ 2137 if (check_add_overflow(curr_base, curr_len, &end) || 2138 end != sg_dma_address(sg)) { 2139 curr_base = sg_dma_address(sg); 2140 curr_len = 0; 2141 2142 /* Reduce max page size if IOVA/DMA bits differ */ 2143 mask |= (curr_base + pgoff) ^ iova; 2144 2145 /* The alignment of any IOVA matching a discontinuity 2146 * point in the DMA list sets the maximum possible page 2147 * size as this must be a starting point of a new page 2148 * that needs to be aligned. 2149 */ 2150 if (i != 0) 2151 mask |= iova; 2152 } 2153 2154 curr_len += sg_dma_len(sg); 2155 iova += sg_dma_len(sg) - pgoff; 2156 2157 pgoff = 0; 2158 } 2159 2160 /* The mask accumulates 1's in each position where the IOVA and DMA 2161 * address differ, thus the length of trailing 0 is the largest page 2162 * size that can pass the IOVA through to the DMA address. 2163 */ 2164 if (mask) 2165 pgsz_bitmap &= GENMASK_ULL(__ffs64(mask), 0); 2166 return pgsz_bitmap ? rounddown_pow_of_two(pgsz_bitmap) : 0; 2167 } 2168 2169 static u64 devx_umem_find_best_pgsize(struct ib_umem *umem, u64 pgsz_bitmap) 2170 { 2171 u64 page_size; 2172 2173 /* Don't bother checking larger page sizes as offset must be zero and 2174 * total DEVX umem length must be equal to total umem length. 2175 */ 2176 pgsz_bitmap &= GENMASK_ULL(max_t(u64, order_base_2(umem->length), 2177 PAGE_SHIFT), 2178 MLX5_ADAPTER_PAGE_SHIFT); 2179 if (!pgsz_bitmap) 2180 return 0; 2181 2182 page_size = devx_umem_find_best_pgoff(umem, pgsz_bitmap); 2183 if (!page_size) 2184 return 0; 2185 2186 /* If the page_size is less than the CPU page size then we can use the 2187 * offset and create a umem which is a subset of the page list. 2188 * For larger page sizes we can't be sure the DMA list reflects the 2189 * VA so we must ensure that the umem extent is exactly equal to the 2190 * page list. Reduce the page size until one of these cases is true. 2191 */ 2192 while ((devx_umem_dma_offset(umem, page_size) != 0 || 2193 (umem->length % page_size) != 0) && 2194 page_size > PAGE_SIZE) 2195 page_size /= 2; 2196 2197 return page_size; 2198 } 2199 2200 static int devx_umem_get(struct mlx5_ib_dev *dev, struct ib_ucontext *ucontext, 2201 struct uverbs_attr_bundle *attrs, 2202 struct devx_umem *obj) 2203 { 2204 u64 pgsz_bitmap; 2205 u64 page_size; 2206 u64 addr; 2207 size_t size; 2208 u32 access; 2209 int err; 2210 2211 if (uverbs_copy_from(&addr, attrs, MLX5_IB_ATTR_DEVX_UMEM_REG_ADDR) || 2212 uverbs_copy_from(&size, attrs, MLX5_IB_ATTR_DEVX_UMEM_REG_LEN)) 2213 return -EFAULT; 2214 2215 /* 2216 * If the user does not pass in pgsz_bitmap then the user promises not 2217 * to use umem_offset!=0 in any commands that allocate on top of the 2218 * umem. 2219 * 2220 * If the user wants to use a umem_offset then it must pass in 2221 * pgsz_bitmap which guides the maximum page size and thus maximum 2222 * object alignment inside the umem. See the PRM. 2223 * 2224 * Users are not allowed to use IOVA here, mkeys are not supported on 2225 * umem. 2226 */ 2227 pgsz_bitmap = GENMASK_ULL(63, min(PAGE_SHIFT, MLX5_ADAPTER_PAGE_SHIFT)); 2228 if (uverbs_attr_is_valid(attrs, 2229 MLX5_IB_ATTR_DEVX_UMEM_REG_PGSZ_BITMAP) && 2230 uverbs_copy_from(&pgsz_bitmap, attrs, 2231 MLX5_IB_ATTR_DEVX_UMEM_REG_PGSZ_BITMAP)) 2232 return -EFAULT; 2233 2234 err = uverbs_get_flags32(&access, attrs, 2235 MLX5_IB_ATTR_DEVX_UMEM_REG_ACCESS, 2236 IB_ACCESS_LOCAL_WRITE | 2237 IB_ACCESS_REMOTE_WRITE | 2238 IB_ACCESS_REMOTE_READ); 2239 if (err) 2240 return err; 2241 2242 err = ib_check_mr_access(access); 2243 if (err) 2244 return err; 2245 2246 obj->umem = ib_umem_get(ucontext, addr, size, access, 0); 2247 if (IS_ERR(obj->umem)) 2248 return PTR_ERR(obj->umem); 2249 2250 page_size = devx_umem_find_best_pgsize(obj->umem, pgsz_bitmap); 2251 if (!page_size) { 2252 ib_umem_release(obj->umem); 2253 return -EINVAL; 2254 } 2255 2256 obj->page_shift = order_base_2(page_size); 2257 obj->page_offset = devx_umem_dma_offset(obj->umem, page_size); 2258 obj->ncont = devx_umem_num_dma_blocks(obj->umem, page_size); 2259 2260 return 0; 2261 } 2262 2263 static int devx_umem_reg_cmd_alloc(struct uverbs_attr_bundle *attrs, 2264 struct devx_umem *obj, 2265 struct devx_umem_reg_cmd *cmd) 2266 { 2267 cmd->inlen = MLX5_ST_SZ_BYTES(create_umem_in) + 2268 (MLX5_ST_SZ_BYTES(mtt) * obj->ncont); 2269 cmd->in = uverbs_zalloc(attrs, cmd->inlen); 2270 return PTR_ERR_OR_ZERO(cmd->in); 2271 } 2272 2273 static void devx_umem_reg_cmd_build(struct mlx5_ib_dev *dev, 2274 struct devx_umem *obj, 2275 struct devx_umem_reg_cmd *cmd) 2276 { 2277 void *umem; 2278 __be64 *mtt; 2279 2280 umem = MLX5_ADDR_OF(create_umem_in, cmd->in, umem); 2281 mtt = (__be64 *)MLX5_ADDR_OF(umem, umem, mtt); 2282 2283 MLX5_SET(create_umem_in, cmd->in, opcode, MLX5_CMD_OP_CREATE_UMEM); 2284 MLX5_SET64(umem, umem, num_of_mtt, obj->ncont); 2285 MLX5_SET(umem, umem, log_page_size, obj->page_shift - 2286 MLX5_ADAPTER_PAGE_SHIFT); 2287 MLX5_SET(umem, umem, page_offset, obj->page_offset); 2288 mlx5_ib_populate_pas(dev, obj->umem, obj->page_shift, mtt, 2289 (obj->umem->writable ? MLX5_IB_MTT_WRITE : 0) | 2290 MLX5_IB_MTT_READ); 2291 } 2292 2293 static int UVERBS_HANDLER(MLX5_IB_METHOD_DEVX_UMEM_REG)( 2294 struct uverbs_attr_bundle *attrs) 2295 { 2296 struct devx_umem_reg_cmd cmd; 2297 struct devx_umem *obj; 2298 struct ib_uobject *uobj = uverbs_attr_get_uobject( 2299 attrs, MLX5_IB_ATTR_DEVX_UMEM_REG_HANDLE); 2300 u32 obj_id; 2301 struct mlx5_ib_ucontext *c = rdma_udata_to_drv_context( 2302 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext); 2303 struct mlx5_ib_dev *dev = to_mdev(c->ibucontext.device); 2304 int err; 2305 2306 if (!c->devx_uid) 2307 return -EINVAL; 2308 2309 obj = kzalloc(sizeof(struct devx_umem), GFP_KERNEL); 2310 if (!obj) 2311 return -ENOMEM; 2312 2313 err = devx_umem_get(dev, &c->ibucontext, attrs, obj); 2314 if (err) 2315 goto err_obj_free; 2316 2317 err = devx_umem_reg_cmd_alloc(attrs, obj, &cmd); 2318 if (err) 2319 goto err_umem_release; 2320 2321 devx_umem_reg_cmd_build(dev, obj, &cmd); 2322 2323 MLX5_SET(create_umem_in, cmd.in, uid, c->devx_uid); 2324 err = mlx5_cmd_exec(dev->mdev, cmd.in, cmd.inlen, cmd.out, 2325 sizeof(cmd.out)); 2326 if (err) 2327 goto err_umem_release; 2328 2329 obj->mdev = dev->mdev; 2330 uobj->object = obj; 2331 devx_obj_build_destroy_cmd(cmd.in, cmd.out, obj->dinbox, &obj->dinlen, &obj_id); 2332 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_DEVX_UMEM_REG_OUT_ID, &obj_id, sizeof(obj_id)); 2333 if (err) 2334 goto err_umem_destroy; 2335 2336 return 0; 2337 2338 err_umem_destroy: 2339 mlx5_cmd_exec(obj->mdev, obj->dinbox, obj->dinlen, cmd.out, sizeof(cmd.out)); 2340 err_umem_release: 2341 ib_umem_release(obj->umem); 2342 err_obj_free: 2343 kfree(obj); 2344 return err; 2345 } 2346 2347 static int devx_umem_cleanup(struct ib_uobject *uobject, 2348 enum rdma_remove_reason why, 2349 struct uverbs_attr_bundle *attrs) 2350 { 2351 struct devx_umem *obj = uobject->object; 2352 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2353 int err; 2354 2355 err = mlx5_cmd_exec(obj->mdev, obj->dinbox, obj->dinlen, out, sizeof(out)); 2356 if (ib_is_destroy_retryable(err, why, uobject)) 2357 return err; 2358 2359 ib_umem_release(obj->umem); 2360 kfree(obj); 2361 return 0; 2362 } 2363 2364 static bool is_unaffiliated_event(struct mlx5_core_dev *dev, 2365 unsigned long event_type) 2366 { 2367 __be64 *unaff_events; 2368 int mask_entry; 2369 int mask_bit; 2370 2371 if (!MLX5_CAP_GEN(dev, event_cap)) 2372 return is_legacy_unaffiliated_event_num(event_type); 2373 2374 unaff_events = (__be64 *)MLX5_CAP_DEV_EVENT(dev, 2375 user_unaffiliated_events); 2376 WARN_ON(event_type > MAX_SUPP_EVENT_NUM); 2377 2378 mask_entry = event_type / 64; 2379 mask_bit = event_type % 64; 2380 2381 if (!(be64_to_cpu(unaff_events[mask_entry]) & (1ull << mask_bit))) 2382 return false; 2383 2384 return true; 2385 } 2386 2387 static u32 devx_get_obj_id_from_event(unsigned long event_type, void *data) 2388 { 2389 struct mlx5_eqe *eqe = data; 2390 u32 obj_id = 0; 2391 2392 switch (event_type) { 2393 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 2394 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 2395 case MLX5_EVENT_TYPE_PATH_MIG: 2396 case MLX5_EVENT_TYPE_COMM_EST: 2397 case MLX5_EVENT_TYPE_SQ_DRAINED: 2398 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 2399 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 2400 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 2401 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 2402 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 2403 obj_id = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; 2404 break; 2405 case MLX5_EVENT_TYPE_XRQ_ERROR: 2406 obj_id = be32_to_cpu(eqe->data.xrq_err.type_xrqn) & 0xffffff; 2407 break; 2408 case MLX5_EVENT_TYPE_DCT_DRAINED: 2409 case MLX5_EVENT_TYPE_DCT_KEY_VIOLATION: 2410 obj_id = be32_to_cpu(eqe->data.dct.dctn) & 0xffffff; 2411 break; 2412 case MLX5_EVENT_TYPE_CQ_ERROR: 2413 obj_id = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff; 2414 break; 2415 default: 2416 obj_id = MLX5_GET(affiliated_event_header, &eqe->data, obj_id); 2417 break; 2418 } 2419 2420 return obj_id; 2421 } 2422 2423 static int deliver_event(struct devx_event_subscription *event_sub, 2424 const void *data) 2425 { 2426 struct devx_async_event_file *ev_file; 2427 struct devx_async_event_data *event_data; 2428 unsigned long flags; 2429 2430 ev_file = event_sub->ev_file; 2431 2432 if (ev_file->omit_data) { 2433 spin_lock_irqsave(&ev_file->lock, flags); 2434 if (!list_empty(&event_sub->event_list) || 2435 ev_file->is_destroyed) { 2436 spin_unlock_irqrestore(&ev_file->lock, flags); 2437 return 0; 2438 } 2439 2440 list_add_tail(&event_sub->event_list, &ev_file->event_list); 2441 spin_unlock_irqrestore(&ev_file->lock, flags); 2442 wake_up_interruptible(&ev_file->poll_wait); 2443 return 0; 2444 } 2445 2446 event_data = kzalloc(sizeof(*event_data) + sizeof(struct mlx5_eqe), 2447 GFP_ATOMIC); 2448 if (!event_data) { 2449 spin_lock_irqsave(&ev_file->lock, flags); 2450 ev_file->is_overflow_err = 1; 2451 spin_unlock_irqrestore(&ev_file->lock, flags); 2452 return -ENOMEM; 2453 } 2454 2455 event_data->hdr.cookie = event_sub->cookie; 2456 memcpy(event_data->hdr.out_data, data, sizeof(struct mlx5_eqe)); 2457 2458 spin_lock_irqsave(&ev_file->lock, flags); 2459 if (!ev_file->is_destroyed) 2460 list_add_tail(&event_data->list, &ev_file->event_list); 2461 else 2462 kfree(event_data); 2463 spin_unlock_irqrestore(&ev_file->lock, flags); 2464 wake_up_interruptible(&ev_file->poll_wait); 2465 2466 return 0; 2467 } 2468 2469 static void dispatch_event_fd(struct list_head *fd_list, 2470 const void *data) 2471 { 2472 struct devx_event_subscription *item; 2473 2474 list_for_each_entry_rcu(item, fd_list, xa_list) { 2475 if (item->eventfd != NULL) 2476 eventfd_signal(item->eventfd); 2477 else 2478 deliver_event(item, data); 2479 } 2480 } 2481 2482 static bool mlx5_devx_event_notifier(struct mlx5_core_dev *mdev, 2483 uint8_t event_type, void *data) 2484 { 2485 struct mlx5_ib_dev *dev; 2486 struct mlx5_devx_event_table *table; 2487 struct devx_event *event; 2488 struct devx_obj_event *obj_event; 2489 u16 obj_type = 0; 2490 bool is_unaffiliated; 2491 u32 obj_id; 2492 2493 /* 2494 * Command completions and page requests must be processed by the 2495 * mlx5_core default EQ handler. Returning true here tells 2496 * mlx5_eq_int() the event was consumed and skips core processing, 2497 * which stalls the firmware command interface and page supply and 2498 * wedges the device. Return false so the core handler runs for 2499 * these frequent kernel events. 2500 */ 2501 if (event_type == MLX5_EVENT_TYPE_CMD || 2502 event_type == MLX5_EVENT_TYPE_PAGE_REQUEST) 2503 return false; 2504 2505 dev = READ_ONCE(mdev->priv.eq_table.dev); 2506 if (dev == NULL) 2507 return false; 2508 table = &dev->devx_event_table; 2509 is_unaffiliated = is_unaffiliated_event(dev->mdev, event_type); 2510 2511 if (!is_unaffiliated) 2512 obj_type = get_event_obj_type(event_type, data); 2513 2514 rcu_read_lock(); 2515 event = xa_load(&table->event_xa, event_type | (obj_type << 16)); 2516 if (!event) { 2517 rcu_read_unlock(); 2518 return false; 2519 } 2520 2521 if (is_unaffiliated) { 2522 dispatch_event_fd(&event->unaffiliated_list, data); 2523 rcu_read_unlock(); 2524 return true; 2525 } 2526 2527 obj_id = devx_get_obj_id_from_event(event_type, data); 2528 obj_event = xa_load(&event->object_ids, obj_id); 2529 if (!obj_event) { 2530 rcu_read_unlock(); 2531 return false; 2532 } 2533 2534 dispatch_event_fd(&obj_event->obj_sub_list, data); 2535 2536 rcu_read_unlock(); 2537 return true; 2538 } 2539 2540 void mlx5_ib_devx_init_event_table(struct mlx5_ib_dev *dev) 2541 { 2542 struct mlx5_devx_event_table *table = &dev->devx_event_table; 2543 2544 xa_init_flags(&table->event_xa, 0); 2545 mutex_init(&table->event_xa_lock); 2546 /* 2547 * Publish dev before cb. The EQ interrupt handler loads cb with 2548 * acquire semantics and the notifier then dereferences eq_table.dev, 2549 * so dev must be visible to that handler once cb is observed. 2550 */ 2551 WRITE_ONCE(dev->mdev->priv.eq_table.dev, dev); 2552 smp_store_release(&dev->mdev->priv.eq_table.cb, 2553 mlx5_devx_event_notifier); 2554 } 2555 2556 void mlx5_ib_devx_cleanup_event_table(struct mlx5_ib_dev *dev) 2557 { 2558 struct mlx5_devx_event_table *table = &dev->devx_event_table; 2559 struct devx_event_subscription *sub, *tmp; 2560 struct devx_event *event; 2561 void *entry; 2562 unsigned long id; 2563 2564 /* 2565 * Stop new dispatch by clearing cb, then wait for any in-flight EQ 2566 * callback to finish its RCU read section before clearing dev and 2567 * tearing down the event table. 2568 */ 2569 WRITE_ONCE(dev->mdev->priv.eq_table.cb, NULL); 2570 synchronize_rcu(); 2571 WRITE_ONCE(dev->mdev->priv.eq_table.dev, NULL); 2572 mutex_lock(&dev->devx_event_table.event_xa_lock); 2573 xa_for_each(&table->event_xa, id, entry) { 2574 event = entry; 2575 list_for_each_entry_safe(sub, tmp, &event->unaffiliated_list, 2576 xa_list) 2577 devx_cleanup_subscription(dev, sub); 2578 kfree(entry); 2579 } 2580 mutex_unlock(&dev->devx_event_table.event_xa_lock); 2581 xa_destroy(&table->event_xa); 2582 } 2583 2584 static ssize_t devx_async_cmd_event_read(struct file *filp, char __user *buf, 2585 size_t count, loff_t *pos) 2586 { 2587 struct devx_async_cmd_event_file *comp_ev_file = filp->private_data; 2588 struct devx_async_event_queue *ev_queue = &comp_ev_file->ev_queue; 2589 struct devx_async_data *event; 2590 int ret = 0; 2591 size_t eventsz; 2592 2593 spin_lock_irq(&ev_queue->lock); 2594 2595 while (list_empty(&ev_queue->event_list)) { 2596 spin_unlock_irq(&ev_queue->lock); 2597 2598 if (filp->f_flags & O_NONBLOCK) 2599 return -EAGAIN; 2600 2601 if (wait_event_interruptible( 2602 ev_queue->poll_wait, 2603 (!list_empty(&ev_queue->event_list) || 2604 ev_queue->is_destroyed))) { 2605 return -ERESTARTSYS; 2606 } 2607 2608 spin_lock_irq(&ev_queue->lock); 2609 if (ev_queue->is_destroyed) { 2610 spin_unlock_irq(&ev_queue->lock); 2611 return -EIO; 2612 } 2613 } 2614 2615 event = list_entry(ev_queue->event_list.next, 2616 struct devx_async_data, list); 2617 eventsz = event->cmd_out_len + 2618 sizeof(struct mlx5_ib_uapi_devx_async_cmd_hdr); 2619 2620 if (eventsz > count) { 2621 spin_unlock_irq(&ev_queue->lock); 2622 return -ENOSPC; 2623 } 2624 2625 list_del(ev_queue->event_list.next); 2626 spin_unlock_irq(&ev_queue->lock); 2627 2628 if (copy_to_user(buf, &event->hdr, eventsz)) 2629 ret = -EFAULT; 2630 else 2631 ret = eventsz; 2632 2633 atomic_sub(event->cmd_out_len, &ev_queue->bytes_in_use); 2634 kvfree(event); 2635 return ret; 2636 } 2637 2638 static __poll_t devx_async_cmd_event_poll(struct file *filp, 2639 struct poll_table_struct *wait) 2640 { 2641 struct devx_async_cmd_event_file *comp_ev_file = filp->private_data; 2642 struct devx_async_event_queue *ev_queue = &comp_ev_file->ev_queue; 2643 __poll_t pollflags = 0; 2644 2645 poll_wait(filp, &ev_queue->poll_wait, wait); 2646 2647 spin_lock_irq(&ev_queue->lock); 2648 if (ev_queue->is_destroyed) 2649 pollflags = POLLIN | POLLRDNORM | POLLHUP; 2650 else if (!list_empty(&ev_queue->event_list)) 2651 pollflags = POLLIN | POLLRDNORM; 2652 spin_unlock_irq(&ev_queue->lock); 2653 2654 return pollflags; 2655 } 2656 2657 static const struct file_operations devx_async_cmd_event_fops = { 2658 .owner = THIS_MODULE, 2659 .read = devx_async_cmd_event_read, 2660 .poll = devx_async_cmd_event_poll, 2661 .release = uverbs_uobject_fd_release, 2662 .llseek = no_llseek, 2663 }; 2664 2665 static ssize_t devx_async_event_read(struct file *filp, char __user *buf, 2666 size_t count, loff_t *pos) 2667 { 2668 struct devx_async_event_file *ev_file = filp->private_data; 2669 struct devx_event_subscription *event_sub; 2670 struct devx_async_event_data *uninitialized_var(event); 2671 int ret = 0; 2672 size_t eventsz; 2673 bool omit_data; 2674 void *event_data; 2675 2676 omit_data = ev_file->omit_data; 2677 2678 spin_lock_irq(&ev_file->lock); 2679 2680 if (ev_file->is_overflow_err) { 2681 ev_file->is_overflow_err = 0; 2682 spin_unlock_irq(&ev_file->lock); 2683 return -EOVERFLOW; 2684 } 2685 2686 2687 while (list_empty(&ev_file->event_list)) { 2688 spin_unlock_irq(&ev_file->lock); 2689 2690 if (filp->f_flags & O_NONBLOCK) 2691 return -EAGAIN; 2692 2693 if (wait_event_interruptible(ev_file->poll_wait, 2694 (!list_empty(&ev_file->event_list) || 2695 ev_file->is_destroyed))) { 2696 return -ERESTARTSYS; 2697 } 2698 2699 spin_lock_irq(&ev_file->lock); 2700 if (ev_file->is_destroyed) { 2701 spin_unlock_irq(&ev_file->lock); 2702 return -EIO; 2703 } 2704 } 2705 2706 if (omit_data) { 2707 event_sub = list_first_entry(&ev_file->event_list, 2708 struct devx_event_subscription, 2709 event_list); 2710 eventsz = sizeof(event_sub->cookie); 2711 event_data = &event_sub->cookie; 2712 } else { 2713 event = list_first_entry(&ev_file->event_list, 2714 struct devx_async_event_data, list); 2715 eventsz = sizeof(struct mlx5_eqe) + 2716 sizeof(struct mlx5_ib_uapi_devx_async_event_hdr); 2717 event_data = &event->hdr; 2718 } 2719 2720 if (eventsz > count) { 2721 spin_unlock_irq(&ev_file->lock); 2722 return -EINVAL; 2723 } 2724 2725 if (omit_data) 2726 list_del_init(&event_sub->event_list); 2727 else 2728 list_del(&event->list); 2729 2730 spin_unlock_irq(&ev_file->lock); 2731 2732 if (copy_to_user(buf, event_data, eventsz)) 2733 /* This points to an application issue, not a kernel concern */ 2734 ret = -EFAULT; 2735 else 2736 ret = eventsz; 2737 2738 if (!omit_data) 2739 kfree(event); 2740 return ret; 2741 } 2742 2743 static __poll_t devx_async_event_poll(struct file *filp, 2744 struct poll_table_struct *wait) 2745 { 2746 struct devx_async_event_file *ev_file = filp->private_data; 2747 __poll_t pollflags = 0; 2748 2749 poll_wait(filp, &ev_file->poll_wait, wait); 2750 2751 spin_lock_irq(&ev_file->lock); 2752 if (ev_file->is_destroyed) 2753 pollflags = POLLIN | POLLRDNORM | POLLHUP; 2754 else if (!list_empty(&ev_file->event_list)) 2755 pollflags = POLLIN | POLLRDNORM; 2756 spin_unlock_irq(&ev_file->lock); 2757 2758 return pollflags; 2759 } 2760 2761 static void devx_free_subscription(struct rcu_head *rcu) 2762 { 2763 struct devx_event_subscription *event_sub = 2764 container_of(rcu, struct devx_event_subscription, rcu); 2765 2766 if (event_sub->eventfd) 2767 eventfd_ctx_put(event_sub->eventfd); 2768 uverbs_uobject_put(&event_sub->ev_file->uobj); 2769 kfree(event_sub); 2770 } 2771 2772 static const struct file_operations devx_async_event_fops = { 2773 .owner = THIS_MODULE, 2774 .read = devx_async_event_read, 2775 .poll = devx_async_event_poll, 2776 .release = uverbs_uobject_fd_release, 2777 .llseek = no_llseek, 2778 }; 2779 2780 static int devx_async_cmd_event_destroy_uobj(struct ib_uobject *uobj, 2781 enum rdma_remove_reason why) 2782 { 2783 struct devx_async_cmd_event_file *comp_ev_file = 2784 container_of(uobj, struct devx_async_cmd_event_file, 2785 uobj); 2786 struct devx_async_event_queue *ev_queue = &comp_ev_file->ev_queue; 2787 struct devx_async_data *entry, *tmp; 2788 2789 spin_lock_irq(&ev_queue->lock); 2790 ev_queue->is_destroyed = 1; 2791 spin_unlock_irq(&ev_queue->lock); 2792 wake_up_interruptible(&ev_queue->poll_wait); 2793 2794 mlx5_cmd_cleanup_async_ctx(&comp_ev_file->async_ctx); 2795 2796 spin_lock_irq(&comp_ev_file->ev_queue.lock); 2797 list_for_each_entry_safe(entry, tmp, 2798 &comp_ev_file->ev_queue.event_list, list) { 2799 list_del(&entry->list); 2800 kvfree(entry); 2801 } 2802 spin_unlock_irq(&comp_ev_file->ev_queue.lock); 2803 return 0; 2804 }; 2805 2806 static int devx_async_event_destroy_uobj(struct ib_uobject *uobj, 2807 enum rdma_remove_reason why) 2808 { 2809 struct devx_async_event_file *ev_file = 2810 container_of(uobj, struct devx_async_event_file, 2811 uobj); 2812 struct devx_event_subscription *event_sub, *event_sub_tmp; 2813 struct mlx5_ib_dev *dev = ev_file->dev; 2814 2815 spin_lock_irq(&ev_file->lock); 2816 ev_file->is_destroyed = 1; 2817 2818 /* free the pending events allocation */ 2819 if (ev_file->omit_data) { 2820 struct devx_event_subscription *event_sub, *tmp; 2821 2822 list_for_each_entry_safe(event_sub, tmp, &ev_file->event_list, 2823 event_list) 2824 list_del_init(&event_sub->event_list); 2825 2826 } else { 2827 struct devx_async_event_data *entry, *tmp; 2828 2829 list_for_each_entry_safe(entry, tmp, &ev_file->event_list, 2830 list) { 2831 list_del(&entry->list); 2832 kfree(entry); 2833 } 2834 } 2835 2836 spin_unlock_irq(&ev_file->lock); 2837 wake_up_interruptible(&ev_file->poll_wait); 2838 2839 mutex_lock(&dev->devx_event_table.event_xa_lock); 2840 /* delete the subscriptions which are related to this FD */ 2841 list_for_each_entry_safe(event_sub, event_sub_tmp, 2842 &ev_file->subscribed_events_list, file_list) { 2843 devx_cleanup_subscription(dev, event_sub); 2844 list_del_rcu(&event_sub->file_list); 2845 /* subscription may not be used by the read API any more */ 2846 call_rcu(&event_sub->rcu, devx_free_subscription); 2847 } 2848 mutex_unlock(&dev->devx_event_table.event_xa_lock); 2849 2850 put_device(&dev->ib_dev.dev); 2851 return 0; 2852 }; 2853 2854 DECLARE_UVERBS_NAMED_METHOD( 2855 MLX5_IB_METHOD_DEVX_UMEM_REG, 2856 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_UMEM_REG_HANDLE, 2857 MLX5_IB_OBJECT_DEVX_UMEM, 2858 UVERBS_ACCESS_NEW, 2859 UA_MANDATORY), 2860 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_UMEM_REG_ADDR, 2861 UVERBS_ATTR_TYPE(u64), 2862 UA_MANDATORY), 2863 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_UMEM_REG_LEN, 2864 UVERBS_ATTR_TYPE(u64), 2865 UA_MANDATORY), 2866 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_DEVX_UMEM_REG_ACCESS, 2867 enum ib_access_flags), 2868 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_DEVX_UMEM_REG_PGSZ_BITMAP, 2869 u64), 2870 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_DEVX_UMEM_REG_OUT_ID, 2871 UVERBS_ATTR_TYPE(u32), 2872 UA_MANDATORY)); 2873 2874 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 2875 MLX5_IB_METHOD_DEVX_UMEM_DEREG, 2876 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_UMEM_DEREG_HANDLE, 2877 MLX5_IB_OBJECT_DEVX_UMEM, 2878 UVERBS_ACCESS_DESTROY, 2879 UA_MANDATORY)); 2880 2881 DECLARE_UVERBS_NAMED_METHOD( 2882 MLX5_IB_METHOD_DEVX_QUERY_EQN, 2883 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_QUERY_EQN_USER_VEC, 2884 UVERBS_ATTR_TYPE(u32), 2885 UA_MANDATORY), 2886 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_DEVX_QUERY_EQN_DEV_EQN, 2887 UVERBS_ATTR_TYPE(u32), 2888 UA_MANDATORY)); 2889 2890 DECLARE_UVERBS_NAMED_METHOD( 2891 MLX5_IB_METHOD_DEVX_QUERY_UAR, 2892 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_QUERY_UAR_USER_IDX, 2893 UVERBS_ATTR_TYPE(u32), 2894 UA_MANDATORY), 2895 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_DEVX_QUERY_UAR_DEV_IDX, 2896 UVERBS_ATTR_TYPE(u32), 2897 UA_MANDATORY)); 2898 2899 DECLARE_UVERBS_NAMED_METHOD( 2900 MLX5_IB_METHOD_DEVX_OTHER, 2901 UVERBS_ATTR_PTR_IN( 2902 MLX5_IB_ATTR_DEVX_OTHER_CMD_IN, 2903 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr)), 2904 UA_MANDATORY, 2905 UA_ALLOC_AND_COPY), 2906 UVERBS_ATTR_PTR_OUT( 2907 MLX5_IB_ATTR_DEVX_OTHER_CMD_OUT, 2908 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_out_cmd_hdr)), 2909 UA_MANDATORY)); 2910 2911 DECLARE_UVERBS_NAMED_METHOD( 2912 MLX5_IB_METHOD_DEVX_OBJ_CREATE, 2913 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_OBJ_CREATE_HANDLE, 2914 MLX5_IB_OBJECT_DEVX_OBJ, 2915 UVERBS_ACCESS_NEW, 2916 UA_MANDATORY), 2917 UVERBS_ATTR_PTR_IN( 2918 MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_IN, 2919 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr)), 2920 UA_MANDATORY, 2921 UA_ALLOC_AND_COPY), 2922 UVERBS_ATTR_PTR_OUT( 2923 MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_OUT, 2924 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_out_cmd_hdr)), 2925 UA_MANDATORY)); 2926 2927 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 2928 MLX5_IB_METHOD_DEVX_OBJ_DESTROY, 2929 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_OBJ_DESTROY_HANDLE, 2930 MLX5_IB_OBJECT_DEVX_OBJ, 2931 UVERBS_ACCESS_DESTROY, 2932 UA_MANDATORY)); 2933 2934 DECLARE_UVERBS_NAMED_METHOD( 2935 MLX5_IB_METHOD_DEVX_OBJ_MODIFY, 2936 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_OBJ_MODIFY_HANDLE, 2937 UVERBS_IDR_ANY_OBJECT, 2938 UVERBS_ACCESS_WRITE, 2939 UA_MANDATORY), 2940 UVERBS_ATTR_PTR_IN( 2941 MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_IN, 2942 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr)), 2943 UA_MANDATORY, 2944 UA_ALLOC_AND_COPY), 2945 UVERBS_ATTR_PTR_OUT( 2946 MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_OUT, 2947 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_out_cmd_hdr)), 2948 UA_MANDATORY)); 2949 2950 DECLARE_UVERBS_NAMED_METHOD( 2951 MLX5_IB_METHOD_DEVX_OBJ_QUERY, 2952 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_OBJ_QUERY_HANDLE, 2953 UVERBS_IDR_ANY_OBJECT, 2954 UVERBS_ACCESS_READ, 2955 UA_MANDATORY), 2956 UVERBS_ATTR_PTR_IN( 2957 MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_IN, 2958 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr)), 2959 UA_MANDATORY, 2960 UA_ALLOC_AND_COPY), 2961 UVERBS_ATTR_PTR_OUT( 2962 MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_OUT, 2963 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_out_cmd_hdr)), 2964 UA_MANDATORY)); 2965 2966 DECLARE_UVERBS_NAMED_METHOD( 2967 MLX5_IB_METHOD_DEVX_OBJ_ASYNC_QUERY, 2968 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_OBJ_QUERY_HANDLE, 2969 UVERBS_IDR_ANY_OBJECT, 2970 UVERBS_ACCESS_READ, 2971 UA_MANDATORY), 2972 UVERBS_ATTR_PTR_IN( 2973 MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_IN, 2974 UVERBS_ATTR_MIN_SIZE(MLX5_ST_SZ_BYTES(general_obj_in_cmd_hdr)), 2975 UA_MANDATORY, 2976 UA_ALLOC_AND_COPY), 2977 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_OUT_LEN, 2978 u16, UA_MANDATORY), 2979 UVERBS_ATTR_FD(MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_FD, 2980 MLX5_IB_OBJECT_DEVX_ASYNC_CMD_FD, 2981 UVERBS_ACCESS_READ, 2982 UA_MANDATORY), 2983 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_WR_ID, 2984 UVERBS_ATTR_TYPE(u64), 2985 UA_MANDATORY)); 2986 2987 DECLARE_UVERBS_NAMED_METHOD( 2988 MLX5_IB_METHOD_DEVX_SUBSCRIBE_EVENT, 2989 UVERBS_ATTR_FD(MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_HANDLE, 2990 MLX5_IB_OBJECT_DEVX_ASYNC_EVENT_FD, 2991 UVERBS_ACCESS_READ, 2992 UA_MANDATORY), 2993 UVERBS_ATTR_IDR(MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_OBJ_HANDLE, 2994 MLX5_IB_OBJECT_DEVX_OBJ, 2995 UVERBS_ACCESS_READ, 2996 UA_OPTIONAL), 2997 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_TYPE_NUM_LIST, 2998 UVERBS_ATTR_MIN_SIZE(sizeof(u16)), 2999 UA_MANDATORY, 3000 UA_ALLOC_AND_COPY), 3001 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_COOKIE, 3002 UVERBS_ATTR_TYPE(u64), 3003 UA_OPTIONAL), 3004 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_NUM, 3005 UVERBS_ATTR_TYPE(u32), 3006 UA_OPTIONAL)); 3007 3008 DECLARE_UVERBS_GLOBAL_METHODS(MLX5_IB_OBJECT_DEVX, 3009 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OTHER), 3010 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_QUERY_UAR), 3011 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_QUERY_EQN), 3012 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_SUBSCRIBE_EVENT)); 3013 3014 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_DEVX_OBJ, 3015 UVERBS_TYPE_ALLOC_IDR(devx_obj_cleanup), 3016 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OBJ_CREATE), 3017 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OBJ_DESTROY), 3018 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OBJ_MODIFY), 3019 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OBJ_QUERY), 3020 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_OBJ_ASYNC_QUERY)); 3021 3022 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_DEVX_UMEM, 3023 UVERBS_TYPE_ALLOC_IDR(devx_umem_cleanup), 3024 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_UMEM_REG), 3025 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_UMEM_DEREG)); 3026 3027 3028 DECLARE_UVERBS_NAMED_METHOD( 3029 MLX5_IB_METHOD_DEVX_ASYNC_CMD_FD_ALLOC, 3030 UVERBS_ATTR_FD(MLX5_IB_ATTR_DEVX_ASYNC_CMD_FD_ALLOC_HANDLE, 3031 MLX5_IB_OBJECT_DEVX_ASYNC_CMD_FD, 3032 UVERBS_ACCESS_NEW, 3033 UA_MANDATORY)); 3034 3035 DECLARE_UVERBS_NAMED_OBJECT( 3036 MLX5_IB_OBJECT_DEVX_ASYNC_CMD_FD, 3037 UVERBS_TYPE_ALLOC_FD(sizeof(struct devx_async_cmd_event_file), 3038 devx_async_cmd_event_destroy_uobj, 3039 &devx_async_cmd_event_fops, "[devx_async_cmd]", 3040 FMODE_READ), 3041 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_ASYNC_CMD_FD_ALLOC)); 3042 3043 DECLARE_UVERBS_NAMED_METHOD( 3044 MLX5_IB_METHOD_DEVX_ASYNC_EVENT_FD_ALLOC, 3045 UVERBS_ATTR_FD(MLX5_IB_ATTR_DEVX_ASYNC_EVENT_FD_ALLOC_HANDLE, 3046 MLX5_IB_OBJECT_DEVX_ASYNC_EVENT_FD, 3047 UVERBS_ACCESS_NEW, 3048 UA_MANDATORY), 3049 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_DEVX_ASYNC_EVENT_FD_ALLOC_FLAGS, 3050 enum mlx5_ib_uapi_devx_create_event_channel_flags, 3051 UA_MANDATORY)); 3052 3053 DECLARE_UVERBS_NAMED_OBJECT( 3054 MLX5_IB_OBJECT_DEVX_ASYNC_EVENT_FD, 3055 UVERBS_TYPE_ALLOC_FD(sizeof(struct devx_async_event_file), 3056 devx_async_event_destroy_uobj, 3057 &devx_async_event_fops, "[devx_async_event]", 3058 FMODE_READ), 3059 &UVERBS_METHOD(MLX5_IB_METHOD_DEVX_ASYNC_EVENT_FD_ALLOC)); 3060 3061 static bool devx_is_supported(struct ib_device *device) 3062 { 3063 struct mlx5_ib_dev *dev = to_mdev(device); 3064 3065 return MLX5_CAP_GEN(dev->mdev, log_max_uctx); 3066 } 3067 3068 const struct uapi_definition mlx5_ib_devx_defs[] = { 3069 UAPI_DEF_CHAIN_OBJ_TREE_NAMED( 3070 MLX5_IB_OBJECT_DEVX, 3071 UAPI_DEF_IS_OBJ_SUPPORTED(devx_is_supported)), 3072 UAPI_DEF_CHAIN_OBJ_TREE_NAMED( 3073 MLX5_IB_OBJECT_DEVX_OBJ, 3074 UAPI_DEF_IS_OBJ_SUPPORTED(devx_is_supported)), 3075 UAPI_DEF_CHAIN_OBJ_TREE_NAMED( 3076 MLX5_IB_OBJECT_DEVX_UMEM, 3077 UAPI_DEF_IS_OBJ_SUPPORTED(devx_is_supported)), 3078 UAPI_DEF_CHAIN_OBJ_TREE_NAMED( 3079 MLX5_IB_OBJECT_DEVX_ASYNC_CMD_FD, 3080 UAPI_DEF_IS_OBJ_SUPPORTED(devx_is_supported)), 3081 UAPI_DEF_CHAIN_OBJ_TREE_NAMED( 3082 MLX5_IB_OBJECT_DEVX_ASYNC_EVENT_FD, 3083 UAPI_DEF_IS_OBJ_SUPPORTED(devx_is_supported)), 3084 {}, 3085 }; 3086