1 /*- 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include <linux/kref.h> 29 #include <rdma/ib_umem.h> 30 #include <rdma/ib_user_verbs.h> 31 #include <rdma/ib_cache.h> 32 #include "mlx5_ib.h" 33 34 static void mlx5_ib_cq_comp(struct mlx5_core_cq *cq, struct mlx5_eqe *eqe __unused) 35 { 36 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq; 37 38 ibcq->comp_handler(ibcq, ibcq->cq_context); 39 } 40 41 static void mlx5_ib_cq_event(struct mlx5_core_cq *mcq, int type) 42 { 43 struct mlx5_ib_cq *cq = container_of(mcq, struct mlx5_ib_cq, mcq); 44 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 45 struct ib_cq *ibcq = &cq->ibcq; 46 struct ib_event event; 47 48 if (type != MLX5_EVENT_TYPE_CQ_ERROR) { 49 mlx5_ib_warn(dev, "Unexpected event type %d on CQ %06x\n", 50 type, mcq->cqn); 51 return; 52 } 53 54 if (ibcq->event_handler) { 55 event.device = &dev->ib_dev; 56 event.event = IB_EVENT_CQ_ERR; 57 event.element.cq = ibcq; 58 ibcq->event_handler(&event, ibcq->cq_context); 59 } 60 } 61 62 static void *get_cqe_from_buf(struct mlx5_ib_cq_buf *buf, int n, int size) 63 { 64 return mlx5_buf_offset(&buf->buf, n * size); 65 } 66 67 static void *get_cqe(struct mlx5_ib_cq *cq, int n) 68 { 69 return get_cqe_from_buf(&cq->buf, n, cq->mcq.cqe_sz); 70 } 71 72 static u8 sw_ownership_bit(int n, int nent) 73 { 74 return (n & nent) ? 1 : 0; 75 } 76 77 static void *get_sw_cqe(struct mlx5_ib_cq *cq, int n) 78 { 79 void *cqe = get_cqe(cq, n & cq->ibcq.cqe); 80 struct mlx5_cqe64 *cqe64; 81 82 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64; 83 84 if (likely((cqe64->op_own) >> 4 != MLX5_CQE_INVALID) && 85 !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ibcq.cqe + 1)))) { 86 return cqe; 87 } else { 88 return NULL; 89 } 90 } 91 92 static void *next_cqe_sw(struct mlx5_ib_cq *cq) 93 { 94 return get_sw_cqe(cq, cq->mcq.cons_index); 95 } 96 97 static enum ib_wc_opcode get_umr_comp(struct mlx5_ib_wq *wq, int idx) 98 { 99 switch (wq->wr_data[idx]) { 100 case MLX5_IB_WR_UMR: 101 return 0; 102 103 case IB_WR_LOCAL_INV: 104 return IB_WC_LOCAL_INV; 105 106 case IB_WR_REG_MR: 107 return IB_WC_REG_MR; 108 109 default: 110 pr_warn("unknown completion status\n"); 111 return 0; 112 } 113 } 114 115 static void handle_good_req(struct ib_wc *wc, struct mlx5_cqe64 *cqe, 116 struct mlx5_ib_wq *wq, int idx) 117 { 118 wc->wc_flags = 0; 119 switch (be32_to_cpu(cqe->sop_drop_qpn) >> 24) { 120 case MLX5_OPCODE_RDMA_WRITE_IMM: 121 wc->wc_flags |= IB_WC_WITH_IMM; 122 case MLX5_OPCODE_RDMA_WRITE: 123 wc->opcode = IB_WC_RDMA_WRITE; 124 break; 125 case MLX5_OPCODE_SEND_IMM: 126 wc->wc_flags |= IB_WC_WITH_IMM; 127 case MLX5_OPCODE_SEND: 128 case MLX5_OPCODE_SEND_INVAL: 129 wc->opcode = IB_WC_SEND; 130 break; 131 case MLX5_OPCODE_RDMA_READ: 132 wc->opcode = IB_WC_RDMA_READ; 133 wc->byte_len = be32_to_cpu(cqe->byte_cnt); 134 break; 135 case MLX5_OPCODE_ATOMIC_CS: 136 wc->opcode = IB_WC_COMP_SWAP; 137 wc->byte_len = 8; 138 break; 139 case MLX5_OPCODE_ATOMIC_FA: 140 wc->opcode = IB_WC_FETCH_ADD; 141 wc->byte_len = 8; 142 break; 143 case MLX5_OPCODE_ATOMIC_MASKED_CS: 144 wc->opcode = IB_WC_MASKED_COMP_SWAP; 145 wc->byte_len = 8; 146 break; 147 case MLX5_OPCODE_ATOMIC_MASKED_FA: 148 wc->opcode = IB_WC_MASKED_FETCH_ADD; 149 wc->byte_len = 8; 150 break; 151 case MLX5_OPCODE_UMR: 152 wc->opcode = get_umr_comp(wq, idx); 153 break; 154 } 155 } 156 157 enum { 158 MLX5_GRH_IN_BUFFER = 1, 159 MLX5_GRH_IN_CQE = 2, 160 }; 161 162 static void handle_responder(struct ib_wc *wc, struct mlx5_cqe64 *cqe, 163 struct mlx5_ib_qp *qp) 164 { 165 enum rdma_link_layer ll = rdma_port_get_link_layer(qp->ibqp.device, 1); 166 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 167 struct mlx5_ib_srq *srq; 168 struct mlx5_ib_wq *wq; 169 u16 wqe_ctr; 170 u8 roce_packet_type; 171 bool vlan_present; 172 u8 g; 173 174 if (qp->ibqp.srq || qp->ibqp.xrcd) { 175 struct mlx5_core_srq *msrq = NULL; 176 177 if (qp->ibqp.xrcd) { 178 msrq = mlx5_core_get_srq(dev->mdev, 179 be32_to_cpu(cqe->srqn)); 180 srq = to_mibsrq(msrq); 181 } else { 182 srq = to_msrq(qp->ibqp.srq); 183 } 184 if (srq) { 185 wqe_ctr = be16_to_cpu(cqe->wqe_counter); 186 wc->wr_id = srq->wrid[wqe_ctr]; 187 mlx5_ib_free_srq_wqe(srq, wqe_ctr); 188 if (msrq && atomic_dec_and_test(&msrq->refcount)) 189 complete(&msrq->free); 190 } 191 } else { 192 wq = &qp->rq; 193 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 194 ++wq->tail; 195 } 196 wc->byte_len = be32_to_cpu(cqe->byte_cnt); 197 198 switch (cqe->op_own >> 4) { 199 case MLX5_CQE_RESP_WR_IMM: 200 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 201 wc->wc_flags = IB_WC_WITH_IMM; 202 wc->ex.imm_data = cqe->imm_inval_pkey; 203 break; 204 case MLX5_CQE_RESP_SEND: 205 wc->opcode = IB_WC_RECV; 206 wc->wc_flags = IB_WC_IP_CSUM_OK; 207 if (unlikely(!((cqe->hds_ip_ext & CQE_L3_OK) && 208 (cqe->hds_ip_ext & CQE_L4_OK)))) 209 wc->wc_flags = 0; 210 break; 211 case MLX5_CQE_RESP_SEND_IMM: 212 wc->opcode = IB_WC_RECV; 213 wc->wc_flags = IB_WC_WITH_IMM; 214 wc->ex.imm_data = cqe->imm_inval_pkey; 215 break; 216 case MLX5_CQE_RESP_SEND_INV: 217 wc->opcode = IB_WC_RECV; 218 wc->wc_flags = IB_WC_WITH_INVALIDATE; 219 wc->ex.invalidate_rkey = be32_to_cpu(cqe->imm_inval_pkey); 220 break; 221 } 222 wc->src_qp = be32_to_cpu(cqe->flags_rqpn) & 0xffffff; 223 wc->dlid_path_bits = cqe->ml_path; 224 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3; 225 wc->wc_flags |= g ? IB_WC_GRH : 0; 226 if (unlikely(is_qp1(qp->ibqp.qp_type))) { 227 u16 pkey = be32_to_cpu(cqe->imm_inval_pkey) & 0xffff; 228 229 ib_find_cached_pkey(&dev->ib_dev, qp->port, pkey, 230 &wc->pkey_index); 231 } else { 232 wc->pkey_index = 0; 233 } 234 235 if (ll != IB_LINK_LAYER_ETHERNET) { 236 wc->slid = be16_to_cpu(cqe->slid); 237 wc->sl = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0xf; 238 return; 239 } 240 241 wc->slid = 0; 242 vlan_present = cqe_has_vlan(cqe); 243 roce_packet_type = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0x3; 244 if (vlan_present) { 245 wc->vlan_id = (be16_to_cpu(cqe->vlan_info)) & 0xfff; 246 wc->sl = (be16_to_cpu(cqe->vlan_info) >> 13) & 0x7; 247 wc->wc_flags |= IB_WC_WITH_VLAN; 248 } else { 249 wc->sl = 0; 250 } 251 252 switch (roce_packet_type) { 253 case MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH: 254 wc->network_hdr_type = RDMA_NETWORK_IB; 255 break; 256 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6: 257 wc->network_hdr_type = RDMA_NETWORK_IPV6; 258 break; 259 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4: 260 wc->network_hdr_type = RDMA_NETWORK_IPV4; 261 break; 262 } 263 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 264 } 265 266 static void dump_cqe(struct mlx5_ib_dev *dev, struct mlx5_err_cqe *cqe) 267 { 268 __be32 *p = (__be32 *)cqe; 269 int i; 270 271 mlx5_ib_warn(dev, "dump error cqe\n"); 272 for (i = 0; i < sizeof(*cqe) / 16; i++, p += 4) 273 pr_info("%08x %08x %08x %08x\n", be32_to_cpu(p[0]), 274 be32_to_cpu(p[1]), be32_to_cpu(p[2]), 275 be32_to_cpu(p[3])); 276 } 277 278 static void mlx5_handle_error_cqe(struct mlx5_ib_dev *dev, 279 struct mlx5_err_cqe *cqe, 280 struct ib_wc *wc) 281 { 282 int dump = 1; 283 284 switch (cqe->syndrome) { 285 case MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR: 286 wc->status = IB_WC_LOC_LEN_ERR; 287 break; 288 case MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR: 289 wc->status = IB_WC_LOC_QP_OP_ERR; 290 break; 291 case MLX5_CQE_SYNDROME_LOCAL_PROT_ERR: 292 wc->status = IB_WC_LOC_PROT_ERR; 293 break; 294 case MLX5_CQE_SYNDROME_WR_FLUSH_ERR: 295 dump = 0; 296 wc->status = IB_WC_WR_FLUSH_ERR; 297 break; 298 case MLX5_CQE_SYNDROME_MW_BIND_ERR: 299 wc->status = IB_WC_MW_BIND_ERR; 300 break; 301 case MLX5_CQE_SYNDROME_BAD_RESP_ERR: 302 wc->status = IB_WC_BAD_RESP_ERR; 303 break; 304 case MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR: 305 wc->status = IB_WC_LOC_ACCESS_ERR; 306 break; 307 case MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR: 308 wc->status = IB_WC_REM_INV_REQ_ERR; 309 break; 310 case MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR: 311 wc->status = IB_WC_REM_ACCESS_ERR; 312 break; 313 case MLX5_CQE_SYNDROME_REMOTE_OP_ERR: 314 wc->status = IB_WC_REM_OP_ERR; 315 break; 316 case MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR: 317 wc->status = IB_WC_RETRY_EXC_ERR; 318 dump = 0; 319 break; 320 case MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR: 321 wc->status = IB_WC_RNR_RETRY_EXC_ERR; 322 dump = 0; 323 break; 324 case MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR: 325 wc->status = IB_WC_REM_ABORT_ERR; 326 break; 327 default: 328 wc->status = IB_WC_GENERAL_ERR; 329 break; 330 } 331 332 wc->vendor_err = cqe->vendor_err_synd; 333 if (dump) 334 dump_cqe(dev, cqe); 335 } 336 337 static int is_atomic_response(struct mlx5_ib_qp *qp, uint16_t idx) 338 { 339 /* TBD: waiting decision 340 */ 341 return 0; 342 } 343 344 static void *mlx5_get_atomic_laddr(struct mlx5_ib_qp *qp, uint16_t idx) 345 { 346 struct mlx5_wqe_data_seg *dpseg; 347 void *addr; 348 349 dpseg = mlx5_get_send_wqe(qp, idx) + sizeof(struct mlx5_wqe_ctrl_seg) + 350 sizeof(struct mlx5_wqe_raddr_seg) + 351 sizeof(struct mlx5_wqe_atomic_seg); 352 addr = (void *)(unsigned long)be64_to_cpu(dpseg->addr); 353 return addr; 354 } 355 356 static void handle_atomic(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64, 357 uint16_t idx) 358 { 359 void *addr; 360 int byte_count; 361 int i; 362 363 if (!is_atomic_response(qp, idx)) 364 return; 365 366 byte_count = be32_to_cpu(cqe64->byte_cnt); 367 addr = mlx5_get_atomic_laddr(qp, idx); 368 369 if (byte_count == 4) { 370 *(uint32_t *)addr = be32_to_cpu(*((__be32 *)addr)); 371 } else { 372 for (i = 0; i < byte_count; i += 8) { 373 *(uint64_t *)addr = be64_to_cpu(*((__be64 *)addr)); 374 addr += 8; 375 } 376 } 377 378 return; 379 } 380 381 static void handle_atomics(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64, 382 u16 tail, u16 head) 383 { 384 u16 idx; 385 386 do { 387 idx = tail & (qp->sq.wqe_cnt - 1); 388 handle_atomic(qp, cqe64, idx); 389 if (idx == head) 390 break; 391 392 tail = qp->sq.w_list[idx].next; 393 } while (1); 394 tail = qp->sq.w_list[idx].next; 395 qp->sq.last_poll = tail; 396 } 397 398 static void free_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf) 399 { 400 mlx5_buf_free(dev->mdev, &buf->buf); 401 } 402 403 static void get_sig_err_item(struct mlx5_sig_err_cqe *cqe, 404 struct ib_sig_err *item) 405 { 406 u16 syndrome = be16_to_cpu(cqe->syndrome); 407 408 #define GUARD_ERR (1 << 13) 409 #define APPTAG_ERR (1 << 12) 410 #define REFTAG_ERR (1 << 11) 411 412 if (syndrome & GUARD_ERR) { 413 item->err_type = IB_SIG_BAD_GUARD; 414 item->expected = be32_to_cpu(cqe->expected_trans_sig) >> 16; 415 item->actual = be32_to_cpu(cqe->actual_trans_sig) >> 16; 416 } else 417 if (syndrome & REFTAG_ERR) { 418 item->err_type = IB_SIG_BAD_REFTAG; 419 item->expected = be32_to_cpu(cqe->expected_reftag); 420 item->actual = be32_to_cpu(cqe->actual_reftag); 421 } else 422 if (syndrome & APPTAG_ERR) { 423 item->err_type = IB_SIG_BAD_APPTAG; 424 item->expected = be32_to_cpu(cqe->expected_trans_sig) & 0xffff; 425 item->actual = be32_to_cpu(cqe->actual_trans_sig) & 0xffff; 426 } else { 427 pr_err("Got signature completion error with bad syndrome %04x\n", 428 syndrome); 429 } 430 431 item->sig_err_offset = be64_to_cpu(cqe->err_offset); 432 item->key = be32_to_cpu(cqe->mkey); 433 } 434 435 static void sw_send_comp(struct mlx5_ib_qp *qp, int num_entries, 436 struct ib_wc *wc, int *npolled) 437 { 438 struct mlx5_ib_wq *wq; 439 unsigned int cur; 440 unsigned int idx; 441 int np; 442 int i; 443 444 wq = &qp->sq; 445 cur = wq->head - wq->tail; 446 np = *npolled; 447 448 if (cur == 0) 449 return; 450 451 for (i = 0; i < cur && np < num_entries; i++) { 452 idx = wq->last_poll & (wq->wqe_cnt - 1); 453 wc->wr_id = wq->wrid[idx]; 454 wc->status = IB_WC_WR_FLUSH_ERR; 455 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR; 456 wq->tail++; 457 np++; 458 wc->qp = &qp->ibqp; 459 wc++; 460 wq->last_poll = wq->w_list[idx].next; 461 } 462 *npolled = np; 463 } 464 465 static void sw_recv_comp(struct mlx5_ib_qp *qp, int num_entries, 466 struct ib_wc *wc, int *npolled) 467 { 468 struct mlx5_ib_wq *wq; 469 unsigned int cur; 470 int np; 471 int i; 472 473 wq = &qp->rq; 474 cur = wq->head - wq->tail; 475 np = *npolled; 476 477 if (cur == 0) 478 return; 479 480 for (i = 0; i < cur && np < num_entries; i++) { 481 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 482 wc->status = IB_WC_WR_FLUSH_ERR; 483 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR; 484 wq->tail++; 485 np++; 486 wc->qp = &qp->ibqp; 487 wc++; 488 } 489 *npolled = np; 490 } 491 492 static void mlx5_ib_poll_sw_comp(struct mlx5_ib_cq *cq, int num_entries, 493 struct ib_wc *wc, int *npolled) 494 { 495 struct mlx5_ib_qp *qp; 496 497 *npolled = 0; 498 /* Find uncompleted WQEs belonging to that cq and retrun mmics ones */ 499 list_for_each_entry(qp, &cq->list_send_qp, cq_send_list) { 500 sw_send_comp(qp, num_entries, wc + *npolled, npolled); 501 if (*npolled >= num_entries) 502 return; 503 } 504 505 list_for_each_entry(qp, &cq->list_recv_qp, cq_recv_list) { 506 sw_recv_comp(qp, num_entries, wc + *npolled, npolled); 507 if (*npolled >= num_entries) 508 return; 509 } 510 } 511 512 static int mlx5_poll_one(struct mlx5_ib_cq *cq, 513 struct mlx5_ib_qp **cur_qp, 514 struct ib_wc *wc) 515 { 516 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 517 struct mlx5_err_cqe *err_cqe; 518 struct mlx5_cqe64 *cqe64; 519 struct mlx5_core_qp *mqp; 520 struct mlx5_ib_wq *wq; 521 struct mlx5_sig_err_cqe *sig_err_cqe; 522 struct mlx5_core_mr *mmkey; 523 struct mlx5_ib_mr *mr; 524 unsigned long flags; 525 uint8_t opcode; 526 uint32_t qpn; 527 u16 wqe_ctr; 528 void *cqe; 529 int idx; 530 531 repoll: 532 cqe = next_cqe_sw(cq); 533 if (!cqe) 534 return -EAGAIN; 535 536 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64; 537 538 ++cq->mcq.cons_index; 539 540 /* Make sure we read CQ entry contents after we've checked the 541 * ownership bit. 542 */ 543 rmb(); 544 545 opcode = cqe64->op_own >> 4; 546 if (unlikely(opcode == MLX5_CQE_RESIZE_CQ)) { 547 if (likely(cq->resize_buf)) { 548 free_cq_buf(dev, &cq->buf); 549 cq->buf = *cq->resize_buf; 550 kfree(cq->resize_buf); 551 cq->resize_buf = NULL; 552 goto repoll; 553 } else { 554 mlx5_ib_warn(dev, "unexpected resize cqe\n"); 555 } 556 } 557 558 qpn = ntohl(cqe64->sop_drop_qpn) & 0xffffff; 559 if (!*cur_qp || (qpn != (*cur_qp)->ibqp.qp_num)) { 560 /* We do not have to take the QP table lock here, 561 * because CQs will be locked while QPs are removed 562 * from the table. 563 */ 564 mqp = __mlx5_qp_lookup(dev->mdev, qpn); 565 *cur_qp = to_mibqp(mqp); 566 } 567 568 wc->qp = &(*cur_qp)->ibqp; 569 switch (opcode) { 570 case MLX5_CQE_REQ: 571 wq = &(*cur_qp)->sq; 572 wqe_ctr = be16_to_cpu(cqe64->wqe_counter); 573 idx = wqe_ctr & (wq->wqe_cnt - 1); 574 handle_good_req(wc, cqe64, wq, idx); 575 handle_atomics(*cur_qp, cqe64, wq->last_poll, idx); 576 wc->wr_id = wq->wrid[idx]; 577 wq->tail = wq->wqe_head[idx] + 1; 578 wc->status = IB_WC_SUCCESS; 579 break; 580 case MLX5_CQE_RESP_WR_IMM: 581 case MLX5_CQE_RESP_SEND: 582 case MLX5_CQE_RESP_SEND_IMM: 583 case MLX5_CQE_RESP_SEND_INV: 584 handle_responder(wc, cqe64, *cur_qp); 585 wc->status = IB_WC_SUCCESS; 586 break; 587 case MLX5_CQE_RESIZE_CQ: 588 break; 589 case MLX5_CQE_REQ_ERR: 590 case MLX5_CQE_RESP_ERR: 591 err_cqe = (struct mlx5_err_cqe *)cqe64; 592 mlx5_handle_error_cqe(dev, err_cqe, wc); 593 mlx5_ib_dbg(dev, "%s error cqe on cqn 0x%x:\n", 594 opcode == MLX5_CQE_REQ_ERR ? 595 "Requestor" : "Responder", cq->mcq.cqn); 596 mlx5_ib_dbg(dev, "syndrome 0x%x, vendor syndrome 0x%x\n", 597 err_cqe->syndrome, err_cqe->vendor_err_synd); 598 if (opcode == MLX5_CQE_REQ_ERR) { 599 wq = &(*cur_qp)->sq; 600 wqe_ctr = be16_to_cpu(cqe64->wqe_counter); 601 idx = wqe_ctr & (wq->wqe_cnt - 1); 602 wc->wr_id = wq->wrid[idx]; 603 wq->tail = wq->wqe_head[idx] + 1; 604 } else { 605 struct mlx5_ib_srq *srq; 606 607 if ((*cur_qp)->ibqp.srq) { 608 srq = to_msrq((*cur_qp)->ibqp.srq); 609 wqe_ctr = be16_to_cpu(cqe64->wqe_counter); 610 wc->wr_id = srq->wrid[wqe_ctr]; 611 mlx5_ib_free_srq_wqe(srq, wqe_ctr); 612 } else { 613 wq = &(*cur_qp)->rq; 614 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 615 ++wq->tail; 616 } 617 } 618 break; 619 case MLX5_CQE_SIG_ERR: 620 sig_err_cqe = (struct mlx5_sig_err_cqe *)cqe64; 621 622 spin_lock_irqsave(&dev->mdev->priv.mr_table.lock, flags); 623 mmkey = __mlx5_mr_lookup(dev->mdev, 624 mlx5_base_mkey(be32_to_cpu(sig_err_cqe->mkey))); 625 mr = to_mibmr(mmkey); 626 get_sig_err_item(sig_err_cqe, &mr->sig->err_item); 627 mr->sig->sig_err_exists = true; 628 mr->sig->sigerr_count++; 629 630 mlx5_ib_warn(dev, "CQN: 0x%x Got SIGERR on key: 0x%x err_type %x err_offset %llx expected %x actual %x\n", 631 cq->mcq.cqn, mr->sig->err_item.key, 632 mr->sig->err_item.err_type, 633 (long long)mr->sig->err_item.sig_err_offset, 634 mr->sig->err_item.expected, 635 mr->sig->err_item.actual); 636 637 spin_unlock_irqrestore(&dev->mdev->priv.mr_table.lock, flags); 638 goto repoll; 639 } 640 641 return 0; 642 } 643 644 static int poll_soft_wc(struct mlx5_ib_cq *cq, int num_entries, 645 struct ib_wc *wc) 646 { 647 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 648 struct mlx5_ib_wc *soft_wc, *next; 649 int npolled = 0; 650 651 list_for_each_entry_safe(soft_wc, next, &cq->wc_list, list) { 652 if (npolled >= num_entries) 653 break; 654 655 mlx5_ib_dbg(dev, "polled software generated completion on CQ 0x%x\n", 656 cq->mcq.cqn); 657 658 wc[npolled++] = soft_wc->wc; 659 list_del(&soft_wc->list); 660 kfree(soft_wc); 661 } 662 663 return npolled; 664 } 665 666 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc) 667 { 668 struct mlx5_ib_cq *cq = to_mcq(ibcq); 669 struct mlx5_ib_qp *cur_qp = NULL; 670 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 671 struct mlx5_core_dev *mdev = dev->mdev; 672 unsigned long flags; 673 int soft_polled = 0; 674 int npolled; 675 676 spin_lock_irqsave(&cq->lock, flags); 677 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)) { 678 mlx5_ib_poll_sw_comp(cq, num_entries, wc, &npolled); 679 goto out; 680 } 681 682 if (unlikely(!list_empty(&cq->wc_list))) 683 soft_polled = poll_soft_wc(cq, num_entries, wc); 684 685 for (npolled = 0; npolled < num_entries - soft_polled; npolled++) { 686 if (mlx5_poll_one(cq, &cur_qp, wc + soft_polled + npolled)) 687 break; 688 } 689 690 if (npolled) 691 mlx5_cq_set_ci(&cq->mcq); 692 out: 693 spin_unlock_irqrestore(&cq->lock, flags); 694 695 return soft_polled + npolled; 696 } 697 698 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) 699 { 700 struct mlx5_core_dev *mdev = to_mdev(ibcq->device)->mdev; 701 struct mlx5_ib_cq *cq = to_mcq(ibcq); 702 void __iomem *uar_page = mdev->priv.uar->map; 703 unsigned long irq_flags; 704 int ret = 0; 705 706 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)) 707 return -1; 708 709 spin_lock_irqsave(&cq->lock, irq_flags); 710 if (cq->notify_flags != IB_CQ_NEXT_COMP) 711 cq->notify_flags = flags & IB_CQ_SOLICITED_MASK; 712 713 if ((flags & IB_CQ_REPORT_MISSED_EVENTS) && !list_empty(&cq->wc_list)) 714 ret = 1; 715 spin_unlock_irqrestore(&cq->lock, irq_flags); 716 717 mlx5_cq_arm(&cq->mcq, 718 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 719 MLX5_CQ_DB_REQ_NOT_SOL : MLX5_CQ_DB_REQ_NOT, 720 uar_page, 721 MLX5_GET_DOORBELL_LOCK(&mdev->priv.cq_uar_lock), 722 cq->mcq.cons_index); 723 724 return ret; 725 } 726 727 static int alloc_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf, 728 int nent, int cqe_size) 729 { 730 int err; 731 732 err = mlx5_buf_alloc(dev->mdev, nent * cqe_size, 733 2 * PAGE_SIZE, &buf->buf); 734 if (err) 735 return err; 736 737 buf->cqe_size = cqe_size; 738 buf->nent = nent; 739 740 return 0; 741 } 742 743 static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata, 744 struct ib_ucontext *context, struct mlx5_ib_cq *cq, 745 int entries, u32 **cqb, 746 int *cqe_size, int *index, int *inlen) 747 { 748 struct mlx5_ib_create_cq ucmd; 749 size_t ucmdlen; 750 int page_shift; 751 __be64 *pas; 752 int npages; 753 int ncont; 754 void *cqc; 755 int err; 756 757 ucmdlen = min(udata->inlen, sizeof(ucmd)); 758 if (ucmdlen < offsetof(struct mlx5_ib_create_cq, flags)) 759 return -EINVAL; 760 761 if (ib_copy_from_udata(&ucmd, udata, ucmdlen)) 762 return -EFAULT; 763 764 if ((ucmd.flags & ~(MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX))) 765 return -EINVAL; 766 767 if (ucmd.cqe_size != 64 && ucmd.cqe_size != 128) 768 return -EINVAL; 769 770 *cqe_size = ucmd.cqe_size; 771 772 cq->buf.umem = ib_umem_get(context, ucmd.buf_addr, 773 entries * ucmd.cqe_size, 774 IB_ACCESS_LOCAL_WRITE, 1); 775 if (IS_ERR(cq->buf.umem)) { 776 err = PTR_ERR(cq->buf.umem); 777 return err; 778 } 779 780 err = mlx5_ib_db_map_user(to_mucontext(context), ucmd.db_addr, 781 &cq->db); 782 if (err) 783 goto err_umem; 784 785 mlx5_ib_cont_pages(cq->buf.umem, ucmd.buf_addr, 0, &npages, &page_shift, 786 &ncont, NULL); 787 mlx5_ib_dbg(dev, "addr 0x%llx, size %u, npages %d, page_shift %d, ncont %d\n", 788 (long long)ucmd.buf_addr, entries * ucmd.cqe_size, npages, page_shift, ncont); 789 790 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 791 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * ncont; 792 *cqb = mlx5_vzalloc(*inlen); 793 if (!*cqb) { 794 err = -ENOMEM; 795 goto err_db; 796 } 797 798 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas); 799 mlx5_ib_populate_pas(dev, cq->buf.umem, page_shift, pas, 0); 800 801 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context); 802 MLX5_SET(cqc, cqc, log_page_size, 803 page_shift - MLX5_ADAPTER_PAGE_SHIFT); 804 805 if (ucmd.flags & MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX) { 806 *index = ucmd.uar_page_index; 807 } else if (to_mucontext(context)->bfregi.lib_uar_dyn) { 808 err = -EINVAL; 809 goto err_cqb; 810 } else { 811 *index = to_mucontext(context)->bfregi.sys_pages[0]; 812 } 813 814 return 0; 815 816 err_cqb: 817 kvfree(*cqb); 818 819 err_db: 820 mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db); 821 822 err_umem: 823 ib_umem_release(cq->buf.umem); 824 return err; 825 } 826 827 static void destroy_cq_user(struct mlx5_ib_cq *cq, struct ib_ucontext *context) 828 { 829 mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db); 830 ib_umem_release(cq->buf.umem); 831 } 832 833 static void init_cq_buf(struct mlx5_ib_cq *cq, struct mlx5_ib_cq_buf *buf) 834 { 835 int i; 836 void *cqe; 837 struct mlx5_cqe64 *cqe64; 838 839 for (i = 0; i < buf->nent; i++) { 840 cqe = get_cqe_from_buf(buf, i, buf->cqe_size); 841 cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64; 842 cqe64->op_own = MLX5_CQE_INVALID << 4; 843 } 844 } 845 846 static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, 847 int entries, int cqe_size, 848 u32 **cqb, int *index, int *inlen) 849 { 850 __be64 *pas; 851 void *cqc; 852 int err; 853 854 err = mlx5_db_alloc(dev->mdev, &cq->db); 855 if (err) 856 return err; 857 858 cq->mcq.set_ci_db = cq->db.db; 859 cq->mcq.arm_db = cq->db.db + 1; 860 cq->mcq.cqe_sz = cqe_size; 861 862 err = alloc_cq_buf(dev, &cq->buf, entries, cqe_size); 863 if (err) 864 goto err_db; 865 866 init_cq_buf(cq, &cq->buf); 867 868 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 869 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * cq->buf.buf.npages; 870 *cqb = mlx5_vzalloc(*inlen); 871 if (!*cqb) { 872 err = -ENOMEM; 873 goto err_buf; 874 } 875 876 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas); 877 mlx5_fill_page_array(&cq->buf.buf, pas); 878 879 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context); 880 MLX5_SET(cqc, cqc, log_page_size, 881 cq->buf.buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 882 883 *index = dev->mdev->priv.uar->index; 884 885 return 0; 886 887 err_buf: 888 free_cq_buf(dev, &cq->buf); 889 890 err_db: 891 mlx5_db_free(dev->mdev, &cq->db); 892 return err; 893 } 894 895 static void destroy_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq) 896 { 897 free_cq_buf(dev, &cq->buf); 898 mlx5_db_free(dev->mdev, &cq->db); 899 } 900 901 static void notify_soft_wc_handler(struct work_struct *work) 902 { 903 struct mlx5_ib_cq *cq = container_of(work, struct mlx5_ib_cq, 904 notify_work); 905 906 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context); 907 } 908 909 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, 910 const struct ib_cq_init_attr *attr, 911 struct ib_ucontext *context, 912 struct ib_udata *udata) 913 { 914 int entries = attr->cqe; 915 int vector = attr->comp_vector; 916 struct mlx5_ib_dev *dev = to_mdev(ibdev); 917 u32 out[MLX5_ST_SZ_DW(create_cq_out)]; 918 struct mlx5_ib_cq *cq; 919 int uninitialized_var(index); 920 int uninitialized_var(inlen); 921 u32 *cqb = NULL; 922 void *cqc; 923 int cqe_size; 924 unsigned int irqn; 925 int eqn; 926 int err; 927 928 if (entries < 0 || 929 (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)))) 930 return ERR_PTR(-EINVAL); 931 932 if (check_cq_create_flags(attr->flags)) 933 return ERR_PTR(-EOPNOTSUPP); 934 935 entries = roundup_pow_of_two(entries + 1); 936 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) 937 return ERR_PTR(-EINVAL); 938 939 cq = kzalloc(sizeof(*cq), GFP_KERNEL); 940 if (!cq) 941 return ERR_PTR(-ENOMEM); 942 943 cq->ibcq.cqe = entries - 1; 944 mutex_init(&cq->resize_mutex); 945 spin_lock_init(&cq->lock); 946 cq->resize_buf = NULL; 947 cq->resize_umem = NULL; 948 cq->create_flags = attr->flags; 949 INIT_LIST_HEAD(&cq->list_send_qp); 950 INIT_LIST_HEAD(&cq->list_recv_qp); 951 952 if (context) { 953 err = create_cq_user(dev, udata, context, cq, entries, 954 &cqb, &cqe_size, &index, &inlen); 955 if (err) 956 goto err_create; 957 } else { 958 cqe_size = cache_line_size() == 128 ? 128 : 64; 959 err = create_cq_kernel(dev, cq, entries, cqe_size, &cqb, 960 &index, &inlen); 961 if (err) 962 goto err_create; 963 964 INIT_WORK(&cq->notify_work, notify_soft_wc_handler); 965 } 966 967 err = mlx5_vector2eqn(dev->mdev, vector, &eqn, &irqn); 968 if (err) 969 goto err_cqb; 970 971 cq->cqe_size = cqe_size; 972 973 cqc = MLX5_ADDR_OF(create_cq_in, cqb, cq_context); 974 MLX5_SET(cqc, cqc, cqe_sz, cqe_sz_to_mlx_sz(cqe_size)); 975 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries)); 976 MLX5_SET(cqc, cqc, uar_page, index); 977 MLX5_SET(cqc, cqc, c_eqn, eqn); 978 MLX5_SET64(cqc, cqc, dbr_addr, cq->db.dma); 979 if (cq->create_flags & IB_CQ_FLAGS_IGNORE_OVERRUN) 980 MLX5_SET(cqc, cqc, oi, 1); 981 982 err = mlx5_core_create_cq(dev->mdev, &cq->mcq, cqb, inlen, out, sizeof(out)); 983 if (err) 984 goto err_cqb; 985 986 mlx5_ib_dbg(dev, "cqn 0x%x\n", cq->mcq.cqn); 987 cq->mcq.irqn = irqn; 988 cq->mcq.comp = mlx5_ib_cq_comp; 989 cq->mcq.event = mlx5_ib_cq_event; 990 991 INIT_LIST_HEAD(&cq->wc_list); 992 993 if (context) 994 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof(__u32))) { 995 err = -EFAULT; 996 goto err_cmd; 997 } 998 999 1000 kvfree(cqb); 1001 return &cq->ibcq; 1002 1003 err_cmd: 1004 mlx5_core_destroy_cq(dev->mdev, &cq->mcq); 1005 1006 err_cqb: 1007 kvfree(cqb); 1008 if (context) 1009 destroy_cq_user(cq, context); 1010 else 1011 destroy_cq_kernel(dev, cq); 1012 1013 err_create: 1014 kfree(cq); 1015 1016 return ERR_PTR(err); 1017 } 1018 1019 1020 int mlx5_ib_destroy_cq(struct ib_cq *cq) 1021 { 1022 struct mlx5_ib_dev *dev = to_mdev(cq->device); 1023 struct mlx5_ib_cq *mcq = to_mcq(cq); 1024 struct ib_ucontext *context = NULL; 1025 1026 if (cq->uobject) 1027 context = cq->uobject->context; 1028 1029 mlx5_core_destroy_cq(dev->mdev, &mcq->mcq); 1030 if (context) 1031 destroy_cq_user(mcq, context); 1032 else 1033 destroy_cq_kernel(dev, mcq); 1034 1035 kfree(mcq); 1036 1037 return 0; 1038 } 1039 1040 static int is_equal_rsn(struct mlx5_cqe64 *cqe64, u32 rsn) 1041 { 1042 return rsn == (ntohl(cqe64->sop_drop_qpn) & 0xffffff); 1043 } 1044 1045 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 rsn, struct mlx5_ib_srq *srq) 1046 { 1047 struct mlx5_cqe64 *cqe64, *dest64; 1048 void *cqe, *dest; 1049 u32 prod_index; 1050 int nfreed = 0; 1051 u8 owner_bit; 1052 1053 if (!cq) 1054 return; 1055 1056 /* First we need to find the current producer index, so we 1057 * know where to start cleaning from. It doesn't matter if HW 1058 * adds new entries after this loop -- the QP we're worried 1059 * about is already in RESET, so the new entries won't come 1060 * from our QP and therefore don't need to be checked. 1061 */ 1062 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); prod_index++) 1063 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe) 1064 break; 1065 1066 /* Now sweep backwards through the CQ, removing CQ entries 1067 * that match our QP by copying older entries on top of them. 1068 */ 1069 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) { 1070 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe); 1071 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64; 1072 if (is_equal_rsn(cqe64, rsn)) { 1073 if (srq && (ntohl(cqe64->srqn) & 0xffffff)) 1074 mlx5_ib_free_srq_wqe(srq, be16_to_cpu(cqe64->wqe_counter)); 1075 ++nfreed; 1076 } else if (nfreed) { 1077 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe); 1078 dest64 = (cq->mcq.cqe_sz == 64) ? dest : dest + 64; 1079 owner_bit = dest64->op_own & MLX5_CQE_OWNER_MASK; 1080 memcpy(dest, cqe, cq->mcq.cqe_sz); 1081 dest64->op_own = owner_bit | 1082 (dest64->op_own & ~MLX5_CQE_OWNER_MASK); 1083 } 1084 } 1085 1086 if (nfreed) { 1087 cq->mcq.cons_index += nfreed; 1088 /* Make sure update of buffer contents is done before 1089 * updating consumer index. 1090 */ 1091 wmb(); 1092 mlx5_cq_set_ci(&cq->mcq); 1093 } 1094 } 1095 1096 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq) 1097 { 1098 if (!cq) 1099 return; 1100 1101 spin_lock_irq(&cq->lock); 1102 __mlx5_ib_cq_clean(cq, qpn, srq); 1103 spin_unlock_irq(&cq->lock); 1104 } 1105 1106 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 1107 { 1108 struct mlx5_ib_dev *dev = to_mdev(cq->device); 1109 struct mlx5_ib_cq *mcq = to_mcq(cq); 1110 int err; 1111 1112 if (!MLX5_CAP_GEN(dev->mdev, cq_moderation)) 1113 return -ENOSYS; 1114 1115 err = mlx5_core_modify_cq_moderation(dev->mdev, &mcq->mcq, 1116 cq_period, cq_count); 1117 if (err) 1118 mlx5_ib_warn(dev, "modify cq 0x%x failed\n", mcq->mcq.cqn); 1119 1120 return err; 1121 } 1122 1123 static int resize_user(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, 1124 int entries, struct ib_udata *udata, int *npas, 1125 int *page_shift, int *cqe_size) 1126 { 1127 struct mlx5_ib_resize_cq ucmd; 1128 struct ib_umem *umem; 1129 int err; 1130 int npages; 1131 struct ib_ucontext *context = cq->buf.umem->context; 1132 1133 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 1134 if (err) 1135 return err; 1136 1137 if (ucmd.reserved0 || ucmd.reserved1) 1138 return -EINVAL; 1139 1140 /* check multiplication overflow */ 1141 if (ucmd.cqe_size && SIZE_MAX / ucmd.cqe_size <= entries - 1) 1142 return -EINVAL; 1143 1144 umem = ib_umem_get(context, ucmd.buf_addr, 1145 (size_t)ucmd.cqe_size * entries, 1146 IB_ACCESS_LOCAL_WRITE, 1); 1147 if (IS_ERR(umem)) { 1148 err = PTR_ERR(umem); 1149 return err; 1150 } 1151 1152 mlx5_ib_cont_pages(umem, ucmd.buf_addr, 0, &npages, page_shift, 1153 npas, NULL); 1154 1155 cq->resize_umem = umem; 1156 *cqe_size = ucmd.cqe_size; 1157 1158 return 0; 1159 } 1160 1161 static void un_resize_user(struct mlx5_ib_cq *cq) 1162 { 1163 ib_umem_release(cq->resize_umem); 1164 } 1165 1166 static int resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq, 1167 int entries, int cqe_size) 1168 { 1169 int err; 1170 1171 cq->resize_buf = kzalloc(sizeof(*cq->resize_buf), GFP_KERNEL); 1172 if (!cq->resize_buf) 1173 return -ENOMEM; 1174 1175 err = alloc_cq_buf(dev, cq->resize_buf, entries, cqe_size); 1176 if (err) 1177 goto ex; 1178 1179 init_cq_buf(cq, cq->resize_buf); 1180 1181 return 0; 1182 1183 ex: 1184 kfree(cq->resize_buf); 1185 return err; 1186 } 1187 1188 static void un_resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq) 1189 { 1190 free_cq_buf(dev, cq->resize_buf); 1191 cq->resize_buf = NULL; 1192 } 1193 1194 static int copy_resize_cqes(struct mlx5_ib_cq *cq) 1195 { 1196 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device); 1197 struct mlx5_cqe64 *scqe64; 1198 struct mlx5_cqe64 *dcqe64; 1199 void *start_cqe; 1200 void *scqe; 1201 void *dcqe; 1202 int ssize; 1203 int dsize; 1204 int i; 1205 u8 sw_own; 1206 1207 ssize = cq->buf.cqe_size; 1208 dsize = cq->resize_buf->cqe_size; 1209 if (ssize != dsize) { 1210 mlx5_ib_warn(dev, "resize from different cqe size is not supported\n"); 1211 return -EINVAL; 1212 } 1213 1214 i = cq->mcq.cons_index; 1215 scqe = get_sw_cqe(cq, i); 1216 scqe64 = ssize == 64 ? scqe : scqe + 64; 1217 start_cqe = scqe; 1218 if (!scqe) { 1219 mlx5_ib_warn(dev, "expected cqe in sw ownership\n"); 1220 return -EINVAL; 1221 } 1222 1223 while ((scqe64->op_own >> 4) != MLX5_CQE_RESIZE_CQ) { 1224 dcqe = get_cqe_from_buf(cq->resize_buf, 1225 (i + 1) & (cq->resize_buf->nent), 1226 dsize); 1227 dcqe64 = dsize == 64 ? dcqe : dcqe + 64; 1228 sw_own = sw_ownership_bit(i + 1, cq->resize_buf->nent); 1229 memcpy(dcqe, scqe, dsize); 1230 dcqe64->op_own = (dcqe64->op_own & ~MLX5_CQE_OWNER_MASK) | sw_own; 1231 1232 ++i; 1233 scqe = get_sw_cqe(cq, i); 1234 scqe64 = ssize == 64 ? scqe : scqe + 64; 1235 if (!scqe) { 1236 mlx5_ib_warn(dev, "expected cqe in sw ownership\n"); 1237 return -EINVAL; 1238 } 1239 1240 if (scqe == start_cqe) { 1241 pr_warn("resize CQ failed to get resize CQE, CQN 0x%x\n", 1242 cq->mcq.cqn); 1243 return -ENOMEM; 1244 } 1245 } 1246 ++cq->mcq.cons_index; 1247 return 0; 1248 } 1249 1250 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata) 1251 { 1252 struct mlx5_ib_dev *dev = to_mdev(ibcq->device); 1253 struct mlx5_ib_cq *cq = to_mcq(ibcq); 1254 void *cqc; 1255 u32 *in; 1256 int err; 1257 int npas; 1258 __be64 *pas; 1259 int page_shift; 1260 int inlen; 1261 int uninitialized_var(cqe_size); 1262 unsigned long flags; 1263 1264 if (!MLX5_CAP_GEN(dev->mdev, cq_resize)) { 1265 pr_info("Firmware does not support resize CQ\n"); 1266 return -ENOSYS; 1267 } 1268 1269 if (entries < 1 || 1270 entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) { 1271 mlx5_ib_warn(dev, "wrong entries number %d, max %d\n", 1272 entries, 1273 1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)); 1274 return -EINVAL; 1275 } 1276 1277 entries = roundup_pow_of_two(entries + 1); 1278 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)) + 1) 1279 return -EINVAL; 1280 1281 if (entries == ibcq->cqe + 1) 1282 return 0; 1283 1284 mutex_lock(&cq->resize_mutex); 1285 if (udata) { 1286 err = resize_user(dev, cq, entries, udata, &npas, &page_shift, 1287 &cqe_size); 1288 } else { 1289 cqe_size = 64; 1290 err = resize_kernel(dev, cq, entries, cqe_size); 1291 if (!err) { 1292 npas = cq->resize_buf->buf.npages; 1293 page_shift = cq->resize_buf->buf.page_shift; 1294 } 1295 } 1296 1297 if (err) 1298 goto ex; 1299 1300 inlen = MLX5_ST_SZ_BYTES(modify_cq_in) + 1301 MLX5_FLD_SZ_BYTES(modify_cq_in, pas[0]) * npas; 1302 1303 in = mlx5_vzalloc(inlen); 1304 if (!in) { 1305 err = -ENOMEM; 1306 goto ex_resize; 1307 } 1308 1309 pas = (__be64 *)MLX5_ADDR_OF(modify_cq_in, in, pas); 1310 if (udata) 1311 mlx5_ib_populate_pas(dev, cq->resize_umem, page_shift, 1312 pas, 0); 1313 else 1314 mlx5_fill_page_array(&cq->resize_buf->buf, pas); 1315 1316 MLX5_SET(modify_cq_in, in, 1317 modify_field_select_resize_field_select.resize_field_select.resize_field_select, 1318 MLX5_MODIFY_CQ_MASK_LOG_SIZE | 1319 MLX5_MODIFY_CQ_MASK_PG_OFFSET | 1320 MLX5_MODIFY_CQ_MASK_PG_SIZE); 1321 1322 cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context); 1323 1324 MLX5_SET(cqc, cqc, log_page_size, 1325 page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1326 MLX5_SET(cqc, cqc, cqe_sz, cqe_sz_to_mlx_sz(cqe_size)); 1327 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries)); 1328 1329 MLX5_SET(modify_cq_in, in, op_mod, MLX5_CQ_OPMOD_RESIZE); 1330 MLX5_SET(modify_cq_in, in, cqn, cq->mcq.cqn); 1331 1332 err = mlx5_core_modify_cq(dev->mdev, &cq->mcq, in, inlen); 1333 if (err) 1334 goto ex_alloc; 1335 1336 if (udata) { 1337 cq->ibcq.cqe = entries - 1; 1338 ib_umem_release(cq->buf.umem); 1339 cq->buf.umem = cq->resize_umem; 1340 cq->resize_umem = NULL; 1341 } else { 1342 struct mlx5_ib_cq_buf tbuf; 1343 int resized = 0; 1344 1345 spin_lock_irqsave(&cq->lock, flags); 1346 if (cq->resize_buf) { 1347 err = copy_resize_cqes(cq); 1348 if (!err) { 1349 tbuf = cq->buf; 1350 cq->buf = *cq->resize_buf; 1351 kfree(cq->resize_buf); 1352 cq->resize_buf = NULL; 1353 resized = 1; 1354 } 1355 } 1356 cq->ibcq.cqe = entries - 1; 1357 spin_unlock_irqrestore(&cq->lock, flags); 1358 if (resized) 1359 free_cq_buf(dev, &tbuf); 1360 } 1361 mutex_unlock(&cq->resize_mutex); 1362 1363 kvfree(in); 1364 return 0; 1365 1366 ex_alloc: 1367 kvfree(in); 1368 1369 ex_resize: 1370 if (udata) 1371 un_resize_user(cq); 1372 else 1373 un_resize_kernel(dev, cq); 1374 ex: 1375 mutex_unlock(&cq->resize_mutex); 1376 return err; 1377 } 1378 1379 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq) 1380 { 1381 struct mlx5_ib_cq *cq; 1382 1383 if (!ibcq) 1384 return 128; 1385 1386 cq = to_mcq(ibcq); 1387 return cq->cqe_size; 1388 } 1389 1390 /* Called from atomic context */ 1391 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc) 1392 { 1393 struct mlx5_ib_wc *soft_wc; 1394 struct mlx5_ib_cq *cq = to_mcq(ibcq); 1395 unsigned long flags; 1396 1397 soft_wc = kmalloc(sizeof(*soft_wc), GFP_ATOMIC); 1398 if (!soft_wc) 1399 return -ENOMEM; 1400 1401 soft_wc->wc = *wc; 1402 spin_lock_irqsave(&cq->lock, flags); 1403 list_add_tail(&soft_wc->list, &cq->wc_list); 1404 if (cq->notify_flags == IB_CQ_NEXT_COMP || 1405 wc->status != IB_WC_SUCCESS) { 1406 cq->notify_flags = 0; 1407 schedule_work(&cq->notify_work); 1408 } 1409 spin_unlock_irqrestore(&cq->lock, flags); 1410 1411 return 0; 1412 } 1413