1 /*- 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_IB_H 29 #define MLX5_IB_H 30 31 #include <linux/kernel.h> 32 #include <linux/sched.h> 33 #include <linux/printk.h> 34 #include <linux/netdevice.h> 35 #include <rdma/ib_verbs.h> 36 #include <rdma/ib_smi.h> 37 #include <dev/mlx5/cq.h> 38 #include <dev/mlx5/qp.h> 39 #include <dev/mlx5/srq.h> 40 #include <linux/types.h> 41 #include <dev/mlx5/mlx5_core/transobj.h> 42 #include <rdma/ib_user_verbs.h> 43 #include <rdma/mlx5-abi.h> 44 45 #define mlx5_ib_dbg(dev, format, arg...) \ 46 pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 47 __LINE__, current->pid, ##arg) 48 49 #define mlx5_ib_err(dev, format, arg...) \ 50 pr_err("%s: ERR: %s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 51 __LINE__, current->pid, ##arg) 52 53 #define mlx5_ib_warn(dev, format, arg...) \ 54 pr_warn("%s: WARN: %s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 55 __LINE__, current->pid, ##arg) 56 57 #define field_avail(type, fld, sz) (offsetof(type, fld) + \ 58 sizeof(((type *)0)->fld) <= (sz)) 59 #define MLX5_IB_DEFAULT_UIDX 0xffffff 60 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 61 62 enum { 63 MLX5_IB_MMAP_CMD_SHIFT = 8, 64 MLX5_IB_MMAP_CMD_MASK = 0xff, 65 }; 66 67 enum mlx5_ib_mmap_cmd { 68 MLX5_IB_MMAP_REGULAR_PAGE = 0, 69 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, 70 MLX5_IB_MMAP_WC_PAGE = 2, 71 MLX5_IB_MMAP_NC_PAGE = 3, 72 /* 5 is chosen in order to be compatible with old versions of libmlx5 */ 73 MLX5_IB_MMAP_CORE_CLOCK = 5, 74 }; 75 76 enum { 77 MLX5_RES_SCAT_DATA32_CQE = 0x1, 78 MLX5_RES_SCAT_DATA64_CQE = 0x2, 79 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 80 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 81 }; 82 83 enum mlx5_ib_latency_class { 84 MLX5_IB_LATENCY_CLASS_LOW, 85 MLX5_IB_LATENCY_CLASS_MEDIUM, 86 MLX5_IB_LATENCY_CLASS_HIGH, 87 MLX5_IB_LATENCY_CLASS_FAST_PATH 88 }; 89 90 enum mlx5_ib_mad_ifc_flags { 91 MLX5_MAD_IFC_IGNORE_MKEY = 1, 92 MLX5_MAD_IFC_IGNORE_BKEY = 2, 93 MLX5_MAD_IFC_NET_VIEW = 4, 94 }; 95 96 enum { 97 MLX5_CROSS_CHANNEL_BFREG = 0, 98 }; 99 100 enum { 101 MLX5_CQE_VERSION_V0, 102 MLX5_CQE_VERSION_V1, 103 }; 104 105 enum { 106 MLX5_IB_INVALID_UAR_INDEX = BIT(31), 107 MLX5_IB_INVALID_BFREG = BIT(31), 108 }; 109 110 struct mlx5_ib_vma_private_data { 111 struct list_head list; 112 struct vm_area_struct *vma; 113 }; 114 115 struct mlx5_bfreg_info { 116 u32 *sys_pages; 117 int num_low_latency_bfregs; 118 unsigned int *count; 119 120 /* 121 * protect bfreg allocation data structs 122 */ 123 struct mutex lock; 124 u32 ver; 125 u8 lib_uar_4k : 1; 126 u8 lib_uar_dyn : 1; 127 u32 num_sys_pages; 128 u32 num_static_sys_pages; 129 u32 total_num_bfregs; 130 u32 num_dyn_bfregs; 131 }; 132 133 struct mlx5_ib_ucontext { 134 struct ib_ucontext ibucontext; 135 struct list_head db_page_list; 136 137 /* protect doorbell record alloc/free 138 */ 139 struct mutex db_page_mutex; 140 struct mlx5_bfreg_info bfregi; 141 u8 cqe_version; 142 /* Transport Domain number */ 143 u32 tdn; 144 struct list_head vma_private_list; 145 }; 146 147 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 148 { 149 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 150 } 151 152 struct mlx5_ib_pd { 153 struct ib_pd ibpd; 154 u32 pdn; 155 }; 156 157 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 158 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 159 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 160 #error "Invalid number of bypass priorities" 161 #endif 162 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 163 164 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 165 #define MLX5_IB_NUM_SNIFFER_FTS 2 166 struct mlx5_ib_flow_prio { 167 struct mlx5_flow_table *flow_table; 168 unsigned int refcount; 169 }; 170 171 struct mlx5_ib_flow_handler { 172 struct list_head list; 173 struct ib_flow ibflow; 174 struct mlx5_ib_flow_prio *prio; 175 struct mlx5_flow_rule *rule; 176 }; 177 178 struct mlx5_ib_flow_db { 179 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 180 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 181 struct mlx5_flow_table *lag_demux_ft; 182 /* Protect flow steering bypass flow tables 183 * when add/del flow rules. 184 * only single add/removal of flow steering rule could be done 185 * simultaneously. 186 */ 187 struct mutex lock; 188 }; 189 190 /* Use macros here so that don't have to duplicate 191 * enum ib_send_flags and enum ib_qp_type for low-level driver 192 */ 193 194 #define MLX5_IB_SEND_UMR_UNREG IB_SEND_RESERVED_START 195 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 1) 196 #define MLX5_IB_SEND_UMR_UPDATE_MTT (IB_SEND_RESERVED_START << 2) 197 198 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 3) 199 #define MLX5_IB_SEND_UMR_UPDATE_PD (IB_SEND_RESERVED_START << 4) 200 #define MLX5_IB_SEND_UMR_UPDATE_ACCESS IB_SEND_RESERVED_END 201 202 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 203 /* 204 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 205 * creates the actual hardware QP. 206 */ 207 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 208 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 209 210 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 211 * 212 * These flags are intended for internal use by the mlx5_ib driver, and they 213 * rely on the range reserved for that use in the ib_qp_create_flags enum. 214 */ 215 #define MLX5_IB_QP_CREATE_SQPN_QP1 IB_QP_CREATE_RESERVED_START 216 #define MLX5_IB_QP_CREATE_WC_TEST (IB_QP_CREATE_RESERVED_START << 1) 217 218 struct wr_list { 219 u16 opcode; 220 u16 next; 221 }; 222 223 struct mlx5_ib_wq { 224 u64 *wrid; 225 u32 *wr_data; 226 struct wr_list *w_list; 227 unsigned *wqe_head; 228 u16 unsig_count; 229 230 /* serialize post to the work queue 231 */ 232 spinlock_t lock; 233 int wqe_cnt; 234 int max_post; 235 int max_gs; 236 int offset; 237 int wqe_shift; 238 unsigned head; 239 unsigned tail; 240 u16 cur_post; 241 u16 last_poll; 242 void *qend; 243 }; 244 245 struct mlx5_ib_rwq { 246 struct ib_wq ibwq; 247 struct mlx5_core_qp core_qp; 248 u32 rq_num_pas; 249 u32 log_rq_stride; 250 u32 log_rq_size; 251 u32 rq_page_offset; 252 u32 log_page_size; 253 struct ib_umem *umem; 254 size_t buf_size; 255 unsigned int page_shift; 256 int create_type; 257 struct mlx5_db db; 258 u32 user_index; 259 u32 wqe_count; 260 u32 wqe_shift; 261 int wq_sig; 262 }; 263 264 enum { 265 MLX5_QP_USER, 266 MLX5_QP_KERNEL, 267 MLX5_QP_EMPTY 268 }; 269 270 enum { 271 MLX5_WQ_USER, 272 MLX5_WQ_KERNEL 273 }; 274 275 struct mlx5_ib_rwq_ind_table { 276 struct ib_rwq_ind_table ib_rwq_ind_tbl; 277 u32 rqtn; 278 }; 279 280 /* 281 * Connect-IB can trigger up to four concurrent pagefaults 282 * per-QP. 283 */ 284 enum mlx5_ib_pagefault_context { 285 MLX5_IB_PAGEFAULT_RESPONDER_READ, 286 MLX5_IB_PAGEFAULT_REQUESTOR_READ, 287 MLX5_IB_PAGEFAULT_RESPONDER_WRITE, 288 MLX5_IB_PAGEFAULT_REQUESTOR_WRITE, 289 MLX5_IB_PAGEFAULT_CONTEXTS 290 }; 291 292 static inline enum mlx5_ib_pagefault_context 293 mlx5_ib_get_pagefault_context(struct mlx5_pagefault *pagefault) 294 { 295 return pagefault->flags & (MLX5_PFAULT_REQUESTOR | MLX5_PFAULT_WRITE); 296 } 297 298 struct mlx5_ib_pfault { 299 struct work_struct work; 300 struct mlx5_pagefault mpfault; 301 }; 302 303 struct mlx5_ib_ubuffer { 304 struct ib_umem *umem; 305 int buf_size; 306 u64 buf_addr; 307 }; 308 309 struct mlx5_ib_qp_base { 310 struct mlx5_ib_qp *container_mibqp; 311 struct mlx5_core_qp mqp; 312 struct mlx5_ib_ubuffer ubuffer; 313 }; 314 315 struct mlx5_ib_qp_trans { 316 struct mlx5_ib_qp_base base; 317 u16 xrcdn; 318 u8 alt_port; 319 u8 atomic_rd_en; 320 u8 resp_depth; 321 }; 322 323 struct mlx5_ib_rss_qp { 324 u32 tirn; 325 }; 326 327 struct mlx5_ib_rq { 328 struct mlx5_ib_qp_base base; 329 struct mlx5_ib_wq *rq; 330 struct mlx5_ib_ubuffer ubuffer; 331 struct mlx5_db *doorbell; 332 u32 tirn; 333 u8 state; 334 }; 335 336 struct mlx5_ib_sq { 337 struct mlx5_ib_qp_base base; 338 struct mlx5_ib_wq *sq; 339 struct mlx5_ib_ubuffer ubuffer; 340 struct mlx5_db *doorbell; 341 u32 tisn; 342 u8 state; 343 }; 344 345 struct mlx5_ib_raw_packet_qp { 346 struct mlx5_ib_sq sq; 347 struct mlx5_ib_rq rq; 348 }; 349 350 struct mlx5_bf { 351 int buf_size; 352 unsigned long offset; 353 struct mlx5_sq_bfreg *bfreg; 354 spinlock_t lock32; 355 }; 356 357 struct mlx5_ib_qp { 358 struct ib_qp ibqp; 359 union { 360 struct mlx5_ib_qp_trans trans_qp; 361 struct mlx5_ib_raw_packet_qp raw_packet_qp; 362 struct mlx5_ib_rss_qp rss_qp; 363 }; 364 struct mlx5_buf buf; 365 366 struct mlx5_db db; 367 struct mlx5_ib_wq rq; 368 369 u8 sq_signal_bits; 370 u8 fm_cache; 371 struct mlx5_ib_wq sq; 372 373 /* serialize qp state modifications 374 */ 375 struct mutex mutex; 376 u32 flags; 377 u8 port; 378 u8 state; 379 int wq_sig; 380 int scat_cqe; 381 int max_inline_data; 382 struct mlx5_bf bf; 383 int has_rq; 384 385 /* only for user space QPs. For kernel 386 * we have it from the bf object 387 */ 388 int bfregn; 389 390 int create_type; 391 392 /* Store signature errors */ 393 bool signature_en; 394 395 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 396 /* 397 * A flag that is true for QP's that are in a state that doesn't 398 * allow page faults, and shouldn't schedule any more faults. 399 */ 400 int disable_page_faults; 401 /* 402 * The disable_page_faults_lock protects a QP's disable_page_faults 403 * field, allowing for a thread to atomically check whether the QP 404 * allows page faults, and if so schedule a page fault. 405 */ 406 spinlock_t disable_page_faults_lock; 407 struct mlx5_ib_pfault pagefaults[MLX5_IB_PAGEFAULT_CONTEXTS]; 408 #endif 409 struct list_head qps_list; 410 struct list_head cq_recv_list; 411 struct list_head cq_send_list; 412 }; 413 414 struct mlx5_ib_cq_buf { 415 struct mlx5_buf buf; 416 struct ib_umem *umem; 417 int cqe_size; 418 int nent; 419 }; 420 421 enum mlx5_ib_qp_flags { 422 MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO, 423 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 424 MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL, 425 MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND, 426 MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV, 427 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5, 428 /* QP uses 1 as its source QP number */ 429 MLX5_IB_QP_SQPN_QP1 = 1 << 6, 430 MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7, 431 MLX5_IB_QP_RSS = 1 << 8, 432 }; 433 434 struct mlx5_umr_wr { 435 struct ib_send_wr wr; 436 union { 437 u64 virt_addr; 438 u64 offset; 439 } target; 440 struct ib_pd *pd; 441 unsigned int page_shift; 442 unsigned int npages; 443 u32 length; 444 int access_flags; 445 u32 mkey; 446 }; 447 448 static inline struct mlx5_umr_wr *umr_wr(struct ib_send_wr *wr) 449 { 450 return container_of(wr, struct mlx5_umr_wr, wr); 451 } 452 453 struct mlx5_shared_mr_info { 454 int mr_id; 455 struct ib_umem *umem; 456 }; 457 458 struct mlx5_ib_cq { 459 struct ib_cq ibcq; 460 struct mlx5_core_cq mcq; 461 struct mlx5_ib_cq_buf buf; 462 struct mlx5_db db; 463 464 /* serialize access to the CQ 465 */ 466 spinlock_t lock; 467 468 /* protect resize cq 469 */ 470 struct mutex resize_mutex; 471 struct mlx5_ib_cq_buf *resize_buf; 472 struct ib_umem *resize_umem; 473 int cqe_size; 474 struct list_head list_send_qp; 475 struct list_head list_recv_qp; 476 u32 create_flags; 477 struct list_head wc_list; 478 enum ib_cq_notify_flags notify_flags; 479 struct work_struct notify_work; 480 }; 481 482 struct mlx5_ib_wc { 483 struct ib_wc wc; 484 struct list_head list; 485 }; 486 487 struct mlx5_ib_srq { 488 struct ib_srq ibsrq; 489 struct mlx5_core_srq msrq; 490 struct mlx5_buf buf; 491 struct mlx5_db db; 492 u64 *wrid; 493 /* protect SRQ hanlding 494 */ 495 spinlock_t lock; 496 int head; 497 int tail; 498 u16 wqe_ctr; 499 struct ib_umem *umem; 500 /* serialize arming a SRQ 501 */ 502 struct mutex mutex; 503 int wq_sig; 504 }; 505 506 struct mlx5_ib_xrcd { 507 struct ib_xrcd ibxrcd; 508 u32 xrcdn; 509 }; 510 511 enum mlx5_ib_mtt_access_flags { 512 MLX5_IB_MTT_READ = (1 << 0), 513 MLX5_IB_MTT_WRITE = (1 << 1), 514 }; 515 516 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 517 518 struct mlx5_ib_mr { 519 struct ib_mr ibmr; 520 void *descs; 521 dma_addr_t desc_map; 522 int ndescs; 523 int max_descs; 524 int desc_size; 525 int access_mode; 526 struct mlx5_core_mr mmkey; 527 struct ib_umem *umem; 528 struct mlx5_shared_mr_info *smr_info; 529 struct list_head list; 530 int order; 531 int umred; 532 int npages; 533 struct mlx5_ib_dev *dev; 534 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 535 struct mlx5_core_sig_ctx *sig; 536 int live; 537 void *descs_alloc; 538 int access_flags; /* Needed for rereg MR */ 539 struct mlx5_async_work cb_work; 540 }; 541 542 struct mlx5_ib_mw { 543 struct ib_mw ibmw; 544 struct mlx5_core_mr mmkey; 545 }; 546 547 struct mlx5_ib_umr_context { 548 struct ib_cqe cqe; 549 enum ib_wc_status status; 550 struct completion done; 551 }; 552 553 struct umr_common { 554 struct ib_pd *pd; 555 struct ib_cq *cq; 556 struct ib_qp *qp; 557 /* control access to UMR QP 558 */ 559 struct semaphore sem; 560 }; 561 562 enum { 563 MLX5_FMR_INVALID, 564 MLX5_FMR_VALID, 565 MLX5_FMR_BUSY, 566 }; 567 568 struct mlx5_cache_ent { 569 struct list_head head; 570 /* sync access to the cahce entry 571 */ 572 spinlock_t lock; 573 574 575 struct dentry *dir; 576 char name[4]; 577 u32 order; 578 u32 size; 579 u32 cur; 580 u32 miss; 581 u32 limit; 582 583 struct dentry *fsize; 584 struct dentry *fcur; 585 struct dentry *fmiss; 586 struct dentry *flimit; 587 588 struct mlx5_ib_dev *dev; 589 struct work_struct work; 590 struct delayed_work dwork; 591 int pending; 592 }; 593 594 struct mlx5_mr_cache { 595 struct workqueue_struct *wq; 596 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; 597 int stopped; 598 struct dentry *root; 599 unsigned long last_add; 600 }; 601 602 struct mlx5_ib_gsi_qp; 603 604 struct mlx5_ib_port_resources { 605 struct mlx5_ib_resources *devr; 606 struct mlx5_ib_gsi_qp *gsi; 607 struct work_struct pkey_change_work; 608 }; 609 610 struct mlx5_ib_resources { 611 struct ib_cq *c0; 612 struct ib_xrcd *x0; 613 struct ib_xrcd *x1; 614 struct ib_pd *p0; 615 struct ib_srq *s0; 616 struct ib_srq *s1; 617 struct mlx5_ib_port_resources ports[2]; 618 /* Protects changes to the port resources */ 619 struct mutex mutex; 620 }; 621 622 struct mlx5_ib_port { 623 u16 q_cnt_id; 624 }; 625 626 struct mlx5_roce { 627 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 628 * netdev pointer 629 */ 630 rwlock_t netdev_lock; 631 struct ifnet *netdev; 632 struct notifier_block nb; 633 atomic_t next_port; 634 }; 635 636 #define MLX5_IB_STATS_COUNT(a,b,c,d) a 637 #define MLX5_IB_STATS_VAR(a,b,c,d) b; 638 #define MLX5_IB_STATS_DESC(a,b,c,d) c, d, 639 640 #define MLX5_IB_CONG_PARAMS(m) \ 641 /* ECN RP */ \ 642 m(+1, u64 rp_clamp_tgt_rate, "rp_clamp_tgt_rate", "If set, whenever a CNP is processed, the target rate is updated to be the current rate") \ 643 m(+1, u64 rp_clamp_tgt_rate_ati, "rp_clamp_tgt_rate_ati", "If set, when receiving a CNP, the target rate should be updated if the transission rate was increased due to the timer, and not only due to the byte counter") \ 644 m(+1, u64 rp_time_reset, "rp_time_reset", "Time in microseconds between rate increases if no CNPs are received") \ 645 m(+1, u64 rp_byte_reset, "rp_byte_reset", "Transmitted data in bytes between rate increases if no CNP's are received. A value of zero means disabled.") \ 646 m(+1, u64 rp_threshold, "rp_threshold", "The number of times rpByteStage or rpTimeStage can count before the RP rate control state machine advances states") \ 647 m(+1, u64 rp_ai_rate, "rp_ai_rate", "The rate, in Mbits per second, used to increase rpTargetRate in the active increase state") \ 648 m(+1, u64 rp_hai_rate, "rp_hai_rate", "The rate, in Mbits per second, used to increase rpTargetRate in the hyper increase state") \ 649 m(+1, u64 rp_min_dec_fac, "rp_min_dec_fac", "The minimum factor by which the current transmit rate can be changed when processing a CNP. Value is given as a percentage, [1 .. 100]") \ 650 m(+1, u64 rp_min_rate, "rp_min_rate", "The minimum value, in Mbps per second, for rate to limit") \ 651 m(+1, u64 rp_rate_to_set_on_first_cnp, "rp_rate_to_set_on_first_cnp", "The rate that is set for the flow when a rate limiter is allocated to it upon first CNP received, in Mbps. A value of zero means use full port speed") \ 652 m(+1, u64 rp_dce_tcp_g, "rp_dce_tcp_g", "Used to update the congestion estimator, alpha, once every dce_tcp_rtt once every dce_tcp_rtt microseconds") \ 653 m(+1, u64 rp_dce_tcp_rtt, "rp_dce_tcp_rtt", "The time between updates of the aolpha value, in microseconds") \ 654 m(+1, u64 rp_rate_reduce_monitor_period, "rp_rate_reduce_monitor_period", "The minimum time between two consecutive rate reductions for a single flow") \ 655 m(+1, u64 rp_initial_alpha_value, "rp_initial_alpha_value", "The initial value of alpha to use when receiving the first CNP for a flow") \ 656 m(+1, u64 rp_gd, "rp_gd", "If a CNP is received, the flow rate is reduced at the beginning of the next rate_reduce_monitor_period interval") \ 657 /* ECN NP */ \ 658 m(+1, u64 np_cnp_dscp, "np_cnp_dscp", "The DiffServ Code Point of the generated CNP for this port") \ 659 m(+1, u64 np_cnp_prio_mode, "np_cnp_prio_mode", "The 802.1p priority value of the generated CNP for this port") \ 660 m(+1, u64 np_cnp_prio, "np_cnp_prio", "The 802.1p priority value of the generated CNP for this port") 661 662 #define MLX5_IB_CONG_PARAMS_NUM (0 MLX5_IB_CONG_PARAMS(MLX5_IB_STATS_COUNT)) 663 664 #define MLX5_IB_CONG_STATS(m) \ 665 m(+1, u64 syndrome, "syndrome", "Syndrome number") \ 666 m(+1, u64 rp_cur_flows, "rp_cur_flows", "Number of flows limited") \ 667 m(+1, u64 sum_flows, "sum_flows", "Sum of the number of flows limited over time") \ 668 m(+1, u64 rp_cnp_ignored, "rp_cnp_ignored", "Number of CNPs and CNMs ignored") \ 669 m(+1, u64 rp_cnp_handled, "rp_cnp_handled", "Number of CNPs and CNMs successfully handled") \ 670 m(+1, u64 time_stamp, "time_stamp", "Time stamp in microseconds") \ 671 m(+1, u64 accumulators_period, "accumulators_period", "The value of X variable for accumulating counters") \ 672 m(+1, u64 np_ecn_marked_roce_packets, "np_ecn_marked_roce_packets", "Number of ECN marked packets seen") \ 673 m(+1, u64 np_cnp_sent, "np_cnp_sent", "Number of CNPs sent") 674 675 #define MLX5_IB_CONG_STATS_NUM (0 MLX5_IB_CONG_STATS(MLX5_IB_STATS_COUNT)) 676 677 struct mlx5_ib_congestion { 678 struct sysctl_ctx_list ctx; 679 struct sx lock; 680 struct delayed_work dwork; 681 union { 682 u64 arg[1]; 683 struct { 684 MLX5_IB_CONG_PARAMS(MLX5_IB_STATS_VAR) 685 MLX5_IB_CONG_STATS(MLX5_IB_STATS_VAR) 686 }; 687 }; 688 }; 689 690 struct mlx5_ib_dev { 691 struct ib_device ib_dev; 692 struct mlx5_core_dev *mdev; 693 struct mlx5_roce roce; 694 MLX5_DECLARE_DOORBELL_LOCK(uar_lock); 695 int num_ports; 696 /* serialize update of capability mask 697 */ 698 struct mutex cap_mask_mutex; 699 bool ib_active; 700 struct umr_common umrc; 701 /* sync used page count stats 702 */ 703 struct mlx5_ib_resources devr; 704 struct mlx5_mr_cache cache; 705 struct timer_list delay_timer; 706 /* Prevents soft lock on massive reg MRs */ 707 struct mutex slow_path_mutex; 708 int fill_delay; 709 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 710 struct ib_odp_caps odp_caps; 711 /* 712 * Sleepable RCU that prevents destruction of MRs while they are still 713 * being used by a page fault handler. 714 */ 715 struct srcu_struct mr_srcu; 716 #endif 717 struct mlx5_ib_flow_db flow_db; 718 /* protect resources needed as part of reset flow */ 719 spinlock_t reset_flow_resource_lock; 720 struct list_head qp_list; 721 /* Array with num_ports elements */ 722 struct mlx5_ib_port *port; 723 struct mlx5_sq_bfreg bfreg; 724 struct mlx5_sq_bfreg wc_bfreg; 725 struct mlx5_sq_bfreg fp_bfreg; 726 struct mlx5_ib_congestion congestion; 727 728 struct mlx5_async_ctx async_ctx; 729 }; 730 731 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 732 { 733 return container_of(mcq, struct mlx5_ib_cq, mcq); 734 } 735 736 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 737 { 738 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 739 } 740 741 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 742 { 743 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 744 } 745 746 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 747 { 748 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 749 } 750 751 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 752 { 753 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 754 } 755 756 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 757 { 758 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 759 } 760 761 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mr *mmkey) 762 { 763 return container_of(mmkey, struct mlx5_ib_mr, mmkey); 764 } 765 766 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 767 { 768 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 769 } 770 771 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 772 { 773 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 774 } 775 776 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 777 { 778 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 779 } 780 781 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 782 { 783 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 784 } 785 786 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 787 { 788 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 789 } 790 791 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 792 { 793 return container_of(msrq, struct mlx5_ib_srq, msrq); 794 } 795 796 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 797 { 798 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 799 } 800 801 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 802 { 803 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 804 } 805 806 struct mlx5_ib_ah { 807 struct ib_ah ibah; 808 struct mlx5_av av; 809 }; 810 811 static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah) 812 { 813 return container_of(ibah, struct mlx5_ib_ah, ibah); 814 } 815 816 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, 817 struct mlx5_db *db); 818 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 819 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 820 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 821 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 822 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey, 823 u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, 824 const void *in_mad, void *response_mad); 825 struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr, 826 struct ib_udata *udata); 827 int mlx5_ib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr); 828 int mlx5_ib_destroy_ah(struct ib_ah *ah); 829 struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd, 830 struct ib_srq_init_attr *init_attr, 831 struct ib_udata *udata); 832 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 833 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 834 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 835 int mlx5_ib_destroy_srq(struct ib_srq *srq); 836 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr, 837 struct ib_recv_wr **bad_wr); 838 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 839 struct ib_qp_init_attr *init_attr, 840 struct ib_udata *udata); 841 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 842 int attr_mask, struct ib_udata *udata); 843 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 844 struct ib_qp_init_attr *qp_init_attr); 845 int mlx5_ib_destroy_qp(struct ib_qp *qp); 846 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 847 struct ib_send_wr **bad_wr); 848 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 849 struct ib_recv_wr **bad_wr); 850 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n); 851 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 852 void *buffer, u32 length, 853 struct mlx5_ib_qp_base *base); 854 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, 855 const struct ib_cq_init_attr *attr, 856 struct ib_ucontext *context, 857 struct ib_udata *udata); 858 int mlx5_ib_destroy_cq(struct ib_cq *cq); 859 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 860 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 861 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 862 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 863 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 864 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 865 u64 virt_addr, int access_flags, 866 struct ib_udata *udata); 867 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 868 struct ib_udata *udata); 869 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 870 int mlx5_ib_update_mtt(struct mlx5_ib_mr *mr, u64 start_page_index, 871 int npages, int zap); 872 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 873 u64 length, u64 virt_addr, int access_flags, 874 struct ib_pd *pd, struct ib_udata *udata); 875 int mlx5_ib_dereg_mr(struct ib_mr *ibmr); 876 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, 877 enum ib_mr_type mr_type, 878 u32 max_num_sg); 879 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 880 unsigned int *sg_offset); 881 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 882 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 883 const struct ib_mad_hdr *in, size_t in_mad_size, 884 struct ib_mad_hdr *out, size_t *out_mad_size, 885 u16 *out_mad_pkey_index); 886 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 887 struct ib_ucontext *context, 888 struct ib_udata *udata); 889 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd); 890 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset); 891 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port); 892 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev, 893 struct ib_smp *out_mad); 894 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 895 __be64 *sys_image_guid); 896 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 897 u16 *max_pkeys); 898 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 899 u32 *vendor_id); 900 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 901 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 902 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, 903 u16 *pkey); 904 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, 905 union ib_gid *gid); 906 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, 907 struct ib_port_attr *props); 908 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 909 struct ib_port_attr *props); 910 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev); 911 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev); 912 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift, 913 int *ncont, int *order); 914 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 915 int page_shift, size_t offset, size_t num_pages, 916 __be64 *pas, int access_flags); 917 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 918 int page_shift, __be64 *pas, int access_flags); 919 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 920 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq); 921 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); 922 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); 923 int mlx5_mr_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift); 924 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 925 struct ib_mr_status *mr_status); 926 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 927 struct ib_wq_init_attr *init_attr, 928 struct ib_udata *udata); 929 int mlx5_ib_destroy_wq(struct ib_wq *wq); 930 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 931 u32 wq_attr_mask, struct ib_udata *udata); 932 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 933 struct ib_rwq_ind_table_init_attr *init_attr, 934 struct ib_udata *udata); 935 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 936 937 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 938 extern struct workqueue_struct *mlx5_ib_page_fault_wq; 939 940 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); 941 void mlx5_ib_mr_pfault_handler(struct mlx5_ib_qp *qp, 942 struct mlx5_ib_pfault *pfault); 943 void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp); 944 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 945 void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev); 946 int __init mlx5_ib_odp_init(void); 947 void mlx5_ib_odp_cleanup(void); 948 void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp); 949 void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp); 950 void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start, 951 unsigned long end); 952 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 953 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) 954 { 955 return; 956 } 957 958 static inline void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp) {} 959 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 960 static inline void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev) {} 961 static inline int mlx5_ib_odp_init(void) { return 0; } 962 static inline void mlx5_ib_odp_cleanup(void) {} 963 static inline void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp) {} 964 static inline void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp) {} 965 966 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 967 968 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 969 u8 port, struct ifla_vf_info *info); 970 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 971 u8 port, int state); 972 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 973 u8 port, struct ifla_vf_stats *stats); 974 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port, 975 u64 guid, int type); 976 977 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 978 int index); 979 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, 980 int index, enum ib_gid_type *gid_type); 981 982 /* GSI QP helper functions */ 983 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd, 984 struct ib_qp_init_attr *init_attr); 985 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp); 986 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 987 int attr_mask); 988 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 989 int qp_attr_mask, 990 struct ib_qp_init_attr *qp_init_attr); 991 int mlx5_ib_gsi_post_send(struct ib_qp *qp, struct ib_send_wr *wr, 992 struct ib_send_wr **bad_wr); 993 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, struct ib_recv_wr *wr, 994 struct ib_recv_wr **bad_wr); 995 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 996 997 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 998 999 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, 1000 int bfregn); 1001 static inline void init_query_mad(struct ib_smp *mad) 1002 { 1003 mad->base_version = 1; 1004 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 1005 mad->class_version = 1; 1006 mad->method = IB_MGMT_METHOD_GET; 1007 } 1008 1009 static inline u8 convert_access(int acc) 1010 { 1011 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 1012 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 1013 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 1014 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 1015 MLX5_PERM_LOCAL_READ; 1016 } 1017 1018 static inline int is_qp1(enum ib_qp_type qp_type) 1019 { 1020 return qp_type == MLX5_IB_QPT_HW_GSI; 1021 } 1022 1023 #define MLX5_MAX_UMR_SHIFT 16 1024 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) 1025 1026 static inline u32 check_cq_create_flags(u32 flags) 1027 { 1028 /* 1029 * It returns non-zero value for unsupported CQ 1030 * create flags, otherwise it returns zero. 1031 */ 1032 return (flags & ~(IB_CQ_FLAGS_IGNORE_OVERRUN | 1033 IB_CQ_FLAGS_TIMESTAMP_COMPLETION)); 1034 } 1035 1036 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 1037 u32 *user_index) 1038 { 1039 if (cqe_version) { 1040 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 1041 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 1042 return -EINVAL; 1043 *user_index = cmd_uidx; 1044 } else { 1045 *user_index = MLX5_IB_DEFAULT_UIDX; 1046 } 1047 1048 return 0; 1049 } 1050 1051 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 1052 struct mlx5_ib_create_qp *ucmd, 1053 int inlen, 1054 u32 *user_index) 1055 { 1056 u8 cqe_version = ucontext->cqe_version; 1057 1058 if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) && 1059 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1060 return 0; 1061 1062 if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) != 1063 !!cqe_version)) 1064 return -EINVAL; 1065 1066 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1067 } 1068 1069 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 1070 struct mlx5_ib_create_srq *ucmd, 1071 int inlen, 1072 u32 *user_index) 1073 { 1074 u8 cqe_version = ucontext->cqe_version; 1075 1076 if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) && 1077 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1078 return 0; 1079 1080 if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) != 1081 !!cqe_version)) 1082 return -EINVAL; 1083 1084 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1085 } 1086 1087 void mlx5_ib_cleanup_congestion(struct mlx5_ib_dev *); 1088 int mlx5_ib_init_congestion(struct mlx5_ib_dev *); 1089 1090 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) 1091 { 1092 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1093 MLX5_UARS_IN_PAGE : 1; 1094 } 1095 1096 static inline int get_num_static_uars(struct mlx5_ib_dev *dev, 1097 struct mlx5_bfreg_info *bfregi) 1098 { 1099 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages; 1100 } 1101 1102 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 1103 struct mlx5_bfreg_info *bfregi, u32 bfregn, 1104 bool dyn_bfreg); 1105 1106 #endif /* MLX5_IB_H */ 1107