1 /*- 2 * Copyright (c) 2013-2020, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_IB_H 29 #define MLX5_IB_H 30 31 #include <linux/kernel.h> 32 #include <linux/sched.h> 33 #include <linux/printk.h> 34 #include <linux/netdevice.h> 35 #include <rdma/ib_verbs.h> 36 #include <rdma/ib_smi.h> 37 #include <dev/mlx5/cq.h> 38 #include <dev/mlx5/qp.h> 39 #include <dev/mlx5/srq.h> 40 #include <linux/types.h> 41 #include <dev/mlx5/mlx5_core/transobj.h> 42 #include <rdma/ib_user_verbs.h> 43 #include <rdma/mlx5-abi.h> 44 45 #define mlx5_ib_dbg(dev, format, arg...) \ 46 pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 47 __LINE__, current->pid, ##arg) 48 49 #define mlx5_ib_err(dev, format, arg...) \ 50 pr_err("%s: ERR: %s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 51 __LINE__, current->pid, ##arg) 52 53 #define mlx5_ib_warn(dev, format, arg...) \ 54 pr_warn("%s: WARN: %s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 55 __LINE__, current->pid, ##arg) 56 57 #define field_avail(type, fld, sz) (offsetof(type, fld) + \ 58 sizeof(((type *)0)->fld) <= (sz)) 59 #define MLX5_IB_DEFAULT_UIDX 0xffffff 60 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 61 62 #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size) 63 64 enum { 65 MLX5_IB_MMAP_CMD_SHIFT = 8, 66 MLX5_IB_MMAP_CMD_MASK = 0xff, 67 }; 68 69 enum mlx5_ib_mmap_cmd { 70 MLX5_IB_MMAP_REGULAR_PAGE = 0, 71 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, 72 MLX5_IB_MMAP_WC_PAGE = 2, 73 MLX5_IB_MMAP_NC_PAGE = 3, 74 /* 5 is chosen in order to be compatible with old versions of libmlx5 */ 75 MLX5_IB_MMAP_CORE_CLOCK = 5, 76 }; 77 78 enum { 79 MLX5_RES_SCAT_DATA32_CQE = 0x1, 80 MLX5_RES_SCAT_DATA64_CQE = 0x2, 81 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 82 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 83 }; 84 85 enum mlx5_ib_latency_class { 86 MLX5_IB_LATENCY_CLASS_LOW, 87 MLX5_IB_LATENCY_CLASS_MEDIUM, 88 MLX5_IB_LATENCY_CLASS_HIGH, 89 MLX5_IB_LATENCY_CLASS_FAST_PATH 90 }; 91 92 enum mlx5_ib_mad_ifc_flags { 93 MLX5_MAD_IFC_IGNORE_MKEY = 1, 94 MLX5_MAD_IFC_IGNORE_BKEY = 2, 95 MLX5_MAD_IFC_NET_VIEW = 4, 96 }; 97 98 enum { 99 MLX5_CROSS_CHANNEL_BFREG = 0, 100 }; 101 102 enum { 103 MLX5_CQE_VERSION_V0, 104 MLX5_CQE_VERSION_V1, 105 }; 106 107 enum { 108 MLX5_IB_INVALID_UAR_INDEX = BIT(31), 109 MLX5_IB_INVALID_BFREG = BIT(31), 110 }; 111 112 struct mlx5_ib_vma_private_data { 113 struct list_head list; 114 struct vm_area_struct *vma; 115 }; 116 117 struct mlx5_bfreg_info { 118 u32 *sys_pages; 119 int num_low_latency_bfregs; 120 unsigned int *count; 121 122 /* 123 * protect bfreg allocation data structs 124 */ 125 struct mutex lock; 126 u32 ver; 127 u8 lib_uar_4k : 1; 128 u8 lib_uar_dyn : 1; 129 u32 num_sys_pages; 130 u32 num_static_sys_pages; 131 u32 total_num_bfregs; 132 u32 num_dyn_bfregs; 133 }; 134 135 struct mlx5_ib_ucontext { 136 struct ib_ucontext ibucontext; 137 struct list_head db_page_list; 138 139 /* protect doorbell record alloc/free 140 */ 141 struct mutex db_page_mutex; 142 struct mlx5_bfreg_info bfregi; 143 u8 cqe_version; 144 /* Transport Domain number */ 145 u32 tdn; 146 struct list_head vma_private_list; 147 }; 148 149 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 150 { 151 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 152 } 153 154 struct mlx5_ib_pd { 155 struct ib_pd ibpd; 156 u32 pdn; 157 }; 158 159 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 160 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 161 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 162 #error "Invalid number of bypass priorities" 163 #endif 164 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 165 166 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 167 #define MLX5_IB_NUM_SNIFFER_FTS 2 168 struct mlx5_ib_flow_prio { 169 struct mlx5_flow_table *flow_table; 170 unsigned int refcount; 171 }; 172 173 struct mlx5_ib_flow_handler { 174 struct list_head list; 175 struct ib_flow ibflow; 176 struct mlx5_ib_flow_prio *prio; 177 struct mlx5_flow_rule *rule; 178 }; 179 180 struct mlx5_ib_flow_db { 181 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 182 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 183 struct mlx5_flow_table *lag_demux_ft; 184 /* Protect flow steering bypass flow tables 185 * when add/del flow rules. 186 * only single add/removal of flow steering rule could be done 187 * simultaneously. 188 */ 189 struct mutex lock; 190 }; 191 192 /* Use macros here so that don't have to duplicate 193 * enum ib_send_flags and enum ib_qp_type for low-level driver 194 */ 195 196 #define MLX5_IB_SEND_UMR_UNREG IB_SEND_RESERVED_START 197 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 1) 198 #define MLX5_IB_SEND_UMR_UPDATE_MTT (IB_SEND_RESERVED_START << 2) 199 200 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 3) 201 #define MLX5_IB_SEND_UMR_UPDATE_PD (IB_SEND_RESERVED_START << 4) 202 #define MLX5_IB_SEND_UMR_UPDATE_ACCESS IB_SEND_RESERVED_END 203 204 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 205 /* 206 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 207 * creates the actual hardware QP. 208 */ 209 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 210 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3 211 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4 212 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 213 214 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 215 * 216 * These flags are intended for internal use by the mlx5_ib driver, and they 217 * rely on the range reserved for that use in the ib_qp_create_flags enum. 218 */ 219 #define MLX5_IB_QP_CREATE_SQPN_QP1 IB_QP_CREATE_RESERVED_START 220 #define MLX5_IB_QP_CREATE_WC_TEST (IB_QP_CREATE_RESERVED_START << 1) 221 222 struct wr_list { 223 u16 opcode; 224 u16 next; 225 }; 226 227 struct mlx5_ib_wq { 228 u64 *wrid; 229 u32 *wr_data; 230 struct wr_list *w_list; 231 unsigned *wqe_head; 232 u16 unsig_count; 233 234 /* serialize post to the work queue 235 */ 236 spinlock_t lock; 237 int wqe_cnt; 238 int max_post; 239 int max_gs; 240 int offset; 241 int wqe_shift; 242 unsigned head; 243 unsigned tail; 244 u16 cur_post; 245 u16 last_poll; 246 void *qend; 247 }; 248 249 struct mlx5_ib_rwq { 250 struct ib_wq ibwq; 251 struct mlx5_core_qp core_qp; 252 u32 rq_num_pas; 253 u32 log_rq_stride; 254 u32 log_rq_size; 255 u32 rq_page_offset; 256 u32 log_page_size; 257 struct ib_umem *umem; 258 size_t buf_size; 259 unsigned int page_shift; 260 int create_type; 261 struct mlx5_db db; 262 u32 user_index; 263 u32 wqe_count; 264 u32 wqe_shift; 265 int wq_sig; 266 }; 267 268 enum { 269 MLX5_QP_USER, 270 MLX5_QP_KERNEL, 271 MLX5_QP_EMPTY 272 }; 273 274 enum { 275 MLX5_WQ_USER, 276 MLX5_WQ_KERNEL 277 }; 278 279 struct mlx5_ib_rwq_ind_table { 280 struct ib_rwq_ind_table ib_rwq_ind_tbl; 281 u32 rqtn; 282 }; 283 284 /* 285 * Connect-IB can trigger up to four concurrent pagefaults 286 * per-QP. 287 */ 288 enum mlx5_ib_pagefault_context { 289 MLX5_IB_PAGEFAULT_RESPONDER_READ, 290 MLX5_IB_PAGEFAULT_REQUESTOR_READ, 291 MLX5_IB_PAGEFAULT_RESPONDER_WRITE, 292 MLX5_IB_PAGEFAULT_REQUESTOR_WRITE, 293 MLX5_IB_PAGEFAULT_CONTEXTS 294 }; 295 296 static inline enum mlx5_ib_pagefault_context 297 mlx5_ib_get_pagefault_context(struct mlx5_pagefault *pagefault) 298 { 299 return pagefault->flags & (MLX5_PFAULT_REQUESTOR | MLX5_PFAULT_WRITE); 300 } 301 302 struct mlx5_ib_pfault { 303 struct work_struct work; 304 struct mlx5_pagefault mpfault; 305 }; 306 307 struct mlx5_ib_ubuffer { 308 struct ib_umem *umem; 309 int buf_size; 310 u64 buf_addr; 311 }; 312 313 struct mlx5_ib_qp_base { 314 struct mlx5_ib_qp *container_mibqp; 315 struct mlx5_core_qp mqp; 316 struct mlx5_ib_ubuffer ubuffer; 317 }; 318 319 struct mlx5_ib_qp_trans { 320 struct mlx5_ib_qp_base base; 321 u16 xrcdn; 322 u8 alt_port; 323 u8 atomic_rd_en; 324 u8 resp_depth; 325 }; 326 327 struct mlx5_ib_rss_qp { 328 u32 tirn; 329 }; 330 331 struct mlx5_ib_rq { 332 struct mlx5_ib_qp_base base; 333 struct mlx5_ib_wq *rq; 334 struct mlx5_ib_ubuffer ubuffer; 335 struct mlx5_db *doorbell; 336 u32 tirn; 337 u8 state; 338 }; 339 340 struct mlx5_ib_sq { 341 struct mlx5_ib_qp_base base; 342 struct mlx5_ib_wq *sq; 343 struct mlx5_ib_ubuffer ubuffer; 344 struct mlx5_db *doorbell; 345 u32 tisn; 346 u8 state; 347 }; 348 349 struct mlx5_ib_raw_packet_qp { 350 struct mlx5_ib_sq sq; 351 struct mlx5_ib_rq rq; 352 }; 353 354 struct mlx5_bf { 355 int buf_size; 356 unsigned long offset; 357 struct mlx5_sq_bfreg *bfreg; 358 spinlock_t lock32; 359 }; 360 361 struct mlx5_ib_qp { 362 struct ib_qp ibqp; 363 union { 364 struct mlx5_ib_qp_trans trans_qp; 365 struct mlx5_ib_raw_packet_qp raw_packet_qp; 366 struct mlx5_ib_rss_qp rss_qp; 367 }; 368 struct mlx5_buf buf; 369 370 struct mlx5_db db; 371 struct mlx5_ib_wq rq; 372 373 u8 sq_signal_bits; 374 u8 fm_cache; 375 struct mlx5_ib_wq sq; 376 377 /* serialize qp state modifications 378 */ 379 struct mutex mutex; 380 u32 flags; 381 u8 port; 382 u8 state; 383 int wq_sig; 384 int scat_cqe; 385 int max_inline_data; 386 struct mlx5_bf bf; 387 int has_rq; 388 389 /* only for user space QPs. For kernel 390 * we have it from the bf object 391 */ 392 int bfregn; 393 394 int create_type; 395 396 /* Store signature errors */ 397 bool signature_en; 398 399 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 400 /* 401 * A flag that is true for QP's that are in a state that doesn't 402 * allow page faults, and shouldn't schedule any more faults. 403 */ 404 int disable_page_faults; 405 /* 406 * The disable_page_faults_lock protects a QP's disable_page_faults 407 * field, allowing for a thread to atomically check whether the QP 408 * allows page faults, and if so schedule a page fault. 409 */ 410 spinlock_t disable_page_faults_lock; 411 struct mlx5_ib_pfault pagefaults[MLX5_IB_PAGEFAULT_CONTEXTS]; 412 #endif 413 struct list_head qps_list; 414 struct list_head cq_recv_list; 415 struct list_head cq_send_list; 416 }; 417 418 struct mlx5_ib_cq_buf { 419 struct mlx5_buf buf; 420 struct ib_umem *umem; 421 int cqe_size; 422 int nent; 423 }; 424 425 enum mlx5_ib_qp_flags { 426 MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO, 427 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 428 MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL, 429 MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND, 430 MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV, 431 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5, 432 /* QP uses 1 as its source QP number */ 433 MLX5_IB_QP_SQPN_QP1 = 1 << 6, 434 MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7, 435 MLX5_IB_QP_RSS = 1 << 8, 436 }; 437 438 struct mlx5_umr_wr { 439 struct ib_send_wr wr; 440 union { 441 u64 virt_addr; 442 u64 offset; 443 } target; 444 struct ib_pd *pd; 445 unsigned int page_shift; 446 unsigned int npages; 447 u32 length; 448 int access_flags; 449 u32 mkey; 450 }; 451 452 static inline const struct mlx5_umr_wr *umr_wr(const struct ib_send_wr *wr) 453 { 454 return container_of(wr, struct mlx5_umr_wr, wr); 455 } 456 457 struct mlx5_shared_mr_info { 458 int mr_id; 459 struct ib_umem *umem; 460 }; 461 462 struct mlx5_ib_cq { 463 struct ib_cq ibcq; 464 struct mlx5_core_cq mcq; 465 struct mlx5_ib_cq_buf buf; 466 struct mlx5_db db; 467 468 /* serialize access to the CQ 469 */ 470 spinlock_t lock; 471 472 /* protect resize cq 473 */ 474 struct mutex resize_mutex; 475 struct mlx5_ib_cq_buf *resize_buf; 476 struct ib_umem *resize_umem; 477 int cqe_size; 478 struct list_head list_send_qp; 479 struct list_head list_recv_qp; 480 u32 create_flags; 481 struct list_head wc_list; 482 enum ib_cq_notify_flags notify_flags; 483 struct work_struct notify_work; 484 }; 485 486 struct mlx5_ib_wc { 487 struct ib_wc wc; 488 struct list_head list; 489 }; 490 491 struct mlx5_ib_srq { 492 struct ib_srq ibsrq; 493 struct mlx5_core_srq msrq; 494 struct mlx5_buf buf; 495 struct mlx5_db db; 496 u64 *wrid; 497 /* protect SRQ hanlding 498 */ 499 spinlock_t lock; 500 int head; 501 int tail; 502 u16 wqe_ctr; 503 struct ib_umem *umem; 504 /* serialize arming a SRQ 505 */ 506 struct mutex mutex; 507 int wq_sig; 508 }; 509 510 struct mlx5_ib_xrcd { 511 struct ib_xrcd ibxrcd; 512 u32 xrcdn; 513 }; 514 515 enum mlx5_ib_mtt_access_flags { 516 MLX5_IB_MTT_READ = (1 << 0), 517 MLX5_IB_MTT_WRITE = (1 << 1), 518 }; 519 520 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 521 522 struct mlx5_ib_mr { 523 struct ib_mr ibmr; 524 void *descs; 525 dma_addr_t desc_map; 526 int ndescs; 527 int max_descs; 528 int desc_size; 529 int access_mode; 530 struct mlx5_core_mr mmkey; 531 struct ib_umem *umem; 532 struct mlx5_shared_mr_info *smr_info; 533 struct list_head list; 534 int order; 535 int umred; 536 int npages; 537 struct mlx5_ib_dev *dev; 538 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 539 struct mlx5_core_sig_ctx *sig; 540 int live; 541 void *descs_alloc; 542 int access_flags; /* Needed for rereg MR */ 543 struct mlx5_async_work cb_work; 544 }; 545 546 struct mlx5_ib_mw { 547 struct ib_mw ibmw; 548 struct mlx5_core_mr mmkey; 549 }; 550 551 struct mlx5_ib_umr_context { 552 struct ib_cqe cqe; 553 enum ib_wc_status status; 554 struct completion done; 555 }; 556 557 struct umr_common { 558 struct ib_pd *pd; 559 struct ib_cq *cq; 560 struct ib_qp *qp; 561 /* control access to UMR QP 562 */ 563 struct semaphore sem; 564 }; 565 566 enum { 567 MLX5_FMR_INVALID, 568 MLX5_FMR_VALID, 569 MLX5_FMR_BUSY, 570 }; 571 572 struct mlx5_cache_ent { 573 struct list_head head; 574 /* sync access to the cahce entry 575 */ 576 spinlock_t lock; 577 578 579 struct dentry *dir; 580 char name[4]; 581 u32 order; 582 u32 size; 583 u32 cur; 584 u32 miss; 585 u32 limit; 586 587 struct dentry *fsize; 588 struct dentry *fcur; 589 struct dentry *fmiss; 590 struct dentry *flimit; 591 592 struct mlx5_ib_dev *dev; 593 struct work_struct work; 594 struct delayed_work dwork; 595 int pending; 596 }; 597 598 struct mlx5_mr_cache { 599 struct workqueue_struct *wq; 600 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; 601 int stopped; 602 struct dentry *root; 603 unsigned long last_add; 604 }; 605 606 struct mlx5_ib_gsi_qp; 607 608 struct mlx5_ib_port_resources { 609 struct mlx5_ib_resources *devr; 610 struct mlx5_ib_gsi_qp *gsi; 611 struct work_struct pkey_change_work; 612 }; 613 614 struct mlx5_ib_resources { 615 struct ib_cq *c0; 616 struct ib_xrcd *x0; 617 struct ib_xrcd *x1; 618 struct ib_pd *p0; 619 struct ib_srq *s0; 620 struct ib_srq *s1; 621 struct mlx5_ib_port_resources ports[2]; 622 /* Protects changes to the port resources */ 623 struct mutex mutex; 624 }; 625 626 struct mlx5_ib_port { 627 u16 q_cnt_id; 628 }; 629 630 struct mlx5_roce { 631 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 632 * netdev pointer 633 */ 634 rwlock_t netdev_lock; 635 struct ifnet *netdev; 636 struct notifier_block nb; 637 atomic_t next_port; 638 }; 639 640 #define MLX5_IB_STATS_COUNT(a,...) a 641 #define MLX5_IB_STATS_VAR(a,b,c,...) b c; 642 #define MLX5_IB_STATS_DESC(a,b,c,d,e,...) d, e, 643 644 #define MLX5_IB_CONG_PARAMS(m) \ 645 /* ECN RP */ \ 646 m(+1, u64, rp_clamp_tgt_rate, "rp_clamp_tgt_rate", "If set, whenever a CNP is processed, the target rate is updated to be the current rate") \ 647 m(+1, u64, rp_clamp_tgt_rate_ati, "rp_clamp_tgt_rate_ati", "If set, when receiving a CNP, the target rate should be updated if the transission rate was increased due to the timer, and not only due to the byte counter") \ 648 m(+1, u64, rp_time_reset, "rp_time_reset", "Time in microseconds between rate increases if no CNPs are received") \ 649 m(+1, u64, rp_byte_reset, "rp_byte_reset", "Transmitted data in bytes between rate increases if no CNP's are received. A value of zero means disabled.") \ 650 m(+1, u64, rp_threshold, "rp_threshold", "The number of times rpByteStage or rpTimeStage can count before the RP rate control state machine advances states") \ 651 m(+1, u64, rp_ai_rate, "rp_ai_rate", "The rate, in Mbits per second, used to increase rpTargetRate in the active increase state") \ 652 m(+1, u64, rp_hai_rate, "rp_hai_rate", "The rate, in Mbits per second, used to increase rpTargetRate in the hyper increase state") \ 653 m(+1, u64, rp_min_dec_fac, "rp_min_dec_fac", "The minimum factor by which the current transmit rate can be changed when processing a CNP. Value is given as a percentage, [1 .. 100]") \ 654 m(+1, u64, rp_min_rate, "rp_min_rate", "The minimum value, in Mbps per second, for rate to limit") \ 655 m(+1, u64, rp_rate_to_set_on_first_cnp, "rp_rate_to_set_on_first_cnp", "The rate that is set for the flow when a rate limiter is allocated to it upon first CNP received, in Mbps. A value of zero means use full port speed") \ 656 m(+1, u64, rp_dce_tcp_g, "rp_dce_tcp_g", "Used to update the congestion estimator, alpha, once every dce_tcp_rtt once every dce_tcp_rtt microseconds") \ 657 m(+1, u64, rp_dce_tcp_rtt, "rp_dce_tcp_rtt", "The time between updates of the aolpha value, in microseconds") \ 658 m(+1, u64, rp_rate_reduce_monitor_period, "rp_rate_reduce_monitor_period", "The minimum time between two consecutive rate reductions for a single flow") \ 659 m(+1, u64, rp_initial_alpha_value, "rp_initial_alpha_value", "The initial value of alpha to use when receiving the first CNP for a flow") \ 660 m(+1, u64, rp_gd, "rp_gd", "If a CNP is received, the flow rate is reduced at the beginning of the next rate_reduce_monitor_period interval") \ 661 /* ECN NP */ \ 662 m(+1, u64, np_cnp_dscp, "np_cnp_dscp", "The DiffServ Code Point of the generated CNP for this port") \ 663 m(+1, u64, np_cnp_prio_mode, "np_cnp_prio_mode", "The 802.1p priority value of the generated CNP for this port") \ 664 m(+1, u64, np_cnp_prio, "np_cnp_prio", "The 802.1p priority value of the generated CNP for this port") 665 666 #define MLX5_IB_CONG_PARAMS_NUM (0 MLX5_IB_CONG_PARAMS(MLX5_IB_STATS_COUNT)) 667 668 #define MLX5_IB_CONG_STATS(m) \ 669 m(+1, u64, syndrome, "syndrome", "Syndrome number") \ 670 m(+1, u64, rp_cur_flows, "rp_cur_flows", "Number of flows limited") \ 671 m(+1, u64, sum_flows, "sum_flows", "Sum of the number of flows limited over time") \ 672 m(+1, u64, rp_cnp_ignored, "rp_cnp_ignored", "Number of CNPs and CNMs ignored") \ 673 m(+1, u64, rp_cnp_handled, "rp_cnp_handled", "Number of CNPs and CNMs successfully handled") \ 674 m(+1, u64, time_stamp, "time_stamp", "Time stamp in microseconds") \ 675 m(+1, u64, accumulators_period, "accumulators_period", "The value of X variable for accumulating counters") \ 676 m(+1, u64, np_ecn_marked_roce_packets, "np_ecn_marked_roce_packets", "Number of ECN marked packets seen") \ 677 m(+1, u64, np_cnp_sent, "np_cnp_sent", "Number of CNPs sent") 678 679 #define MLX5_IB_CONG_STATS_NUM (0 MLX5_IB_CONG_STATS(MLX5_IB_STATS_COUNT)) 680 681 #define MLX5_IB_CONG_STATUS(m) \ 682 /* ECN RP */ \ 683 m(+1, u64, rp_0_enable, "rp_0_enable", "Enable reaction point, priority 0", MLX5_IB_RROCE_ECN_RP, 0, enable) \ 684 m(+1, u64, rp_1_enable, "rp_1_enable", "Enable reaction point, priority 1", MLX5_IB_RROCE_ECN_RP, 1, enable) \ 685 m(+1, u64, rp_2_enable, "rp_2_enable", "Enable reaction point, priority 2", MLX5_IB_RROCE_ECN_RP, 2, enable) \ 686 m(+1, u64, rp_3_enable, "rp_3_enable", "Enable reaction point, priority 3", MLX5_IB_RROCE_ECN_RP, 3, enable) \ 687 m(+1, u64, rp_4_enable, "rp_4_enable", "Enable reaction point, priority 4", MLX5_IB_RROCE_ECN_RP, 4, enable) \ 688 m(+1, u64, rp_5_enable, "rp_5_enable", "Enable reaction point, priority 5", MLX5_IB_RROCE_ECN_RP, 5, enable) \ 689 m(+1, u64, rp_6_enable, "rp_6_enable", "Enable reaction point, priority 6", MLX5_IB_RROCE_ECN_RP, 6, enable) \ 690 m(+1, u64, rp_7_enable, "rp_7_enable", "Enable reaction point, priority 7", MLX5_IB_RROCE_ECN_RP, 7, enable) \ 691 m(+1, u64, rp_8_enable, "rp_8_enable", "Enable reaction point, priority 8", MLX5_IB_RROCE_ECN_RP, 8, enable) \ 692 m(+1, u64, rp_9_enable, "rp_9_enable", "Enable reaction point, priority 9", MLX5_IB_RROCE_ECN_RP, 9, enable) \ 693 m(+1, u64, rp_10_enable, "rp_10_enable", "Enable reaction point, priority 10", MLX5_IB_RROCE_ECN_RP, 10, enable) \ 694 m(+1, u64, rp_11_enable, "rp_11_enable", "Enable reaction point, priority 11", MLX5_IB_RROCE_ECN_RP, 11, enable) \ 695 m(+1, u64, rp_12_enable, "rp_12_enable", "Enable reaction point, priority 12", MLX5_IB_RROCE_ECN_RP, 12, enable) \ 696 m(+1, u64, rp_13_enable, "rp_13_enable", "Enable reaction point, priority 13", MLX5_IB_RROCE_ECN_RP, 13, enable) \ 697 m(+1, u64, rp_14_enable, "rp_14_enable", "Enable reaction point, priority 14", MLX5_IB_RROCE_ECN_RP, 14, enable) \ 698 m(+1, u64, rp_15_enable, "rp_15_enable", "Enable reaction point, priority 15", MLX5_IB_RROCE_ECN_RP, 15, enable) \ 699 /* ECN NP */ \ 700 m(+1, u64, np_0_enable, "np_0_enable", "Enable notification point, priority 0", MLX5_IB_RROCE_ECN_NP, 0, enable) \ 701 m(+1, u64, np_1_enable, "np_1_enable", "Enable notification point, priority 1", MLX5_IB_RROCE_ECN_NP, 1, enable) \ 702 m(+1, u64, np_2_enable, "np_2_enable", "Enable notification point, priority 2", MLX5_IB_RROCE_ECN_NP, 2, enable) \ 703 m(+1, u64, np_3_enable, "np_3_enable", "Enable notification point, priority 3", MLX5_IB_RROCE_ECN_NP, 3, enable) \ 704 m(+1, u64, np_4_enable, "np_4_enable", "Enable notification point, priority 4", MLX5_IB_RROCE_ECN_NP, 4, enable) \ 705 m(+1, u64, np_5_enable, "np_5_enable", "Enable notification point, priority 5", MLX5_IB_RROCE_ECN_NP, 5, enable) \ 706 m(+1, u64, np_6_enable, "np_6_enable", "Enable notification point, priority 6", MLX5_IB_RROCE_ECN_NP, 6, enable) \ 707 m(+1, u64, np_7_enable, "np_7_enable", "Enable notification point, priority 7", MLX5_IB_RROCE_ECN_NP, 7, enable) \ 708 m(+1, u64, np_8_enable, "np_8_enable", "Enable notification point, priority 8", MLX5_IB_RROCE_ECN_NP, 8, enable) \ 709 m(+1, u64, np_9_enable, "np_9_enable", "Enable notification point, priority 9", MLX5_IB_RROCE_ECN_NP, 9, enable) \ 710 m(+1, u64, np_10_enable, "np_10_enable", "Enable notification point, priority 10", MLX5_IB_RROCE_ECN_NP, 10, enable) \ 711 m(+1, u64, np_11_enable, "np_11_enable", "Enable notification point, priority 11", MLX5_IB_RROCE_ECN_NP, 11, enable) \ 712 m(+1, u64, np_12_enable, "np_12_enable", "Enable notification point, priority 12", MLX5_IB_RROCE_ECN_NP, 12, enable) \ 713 m(+1, u64, np_13_enable, "np_13_enable", "Enable notification point, priority 13", MLX5_IB_RROCE_ECN_NP, 13, enable) \ 714 m(+1, u64, np_14_enable, "np_14_enable", "Enable notification point, priority 14", MLX5_IB_RROCE_ECN_NP, 14, enable) \ 715 m(+1, u64, np_15_enable, "np_15_enable", "Enable notification point, priority 15", MLX5_IB_RROCE_ECN_NP, 15, enable) \ 716 717 #define MLX5_IB_CONG_STATUS_NUM (0 MLX5_IB_CONG_STATUS(MLX5_IB_STATS_COUNT)) 718 719 struct mlx5_ib_congestion { 720 struct sysctl_ctx_list ctx; 721 struct sx lock; 722 struct delayed_work dwork; 723 union { 724 u64 arg[1]; 725 struct { 726 MLX5_IB_CONG_PARAMS(MLX5_IB_STATS_VAR) 727 MLX5_IB_CONG_STATS(MLX5_IB_STATS_VAR) 728 MLX5_IB_CONG_STATUS(MLX5_IB_STATS_VAR) 729 }; 730 }; 731 }; 732 733 struct mlx5_ib_dev { 734 struct ib_device ib_dev; 735 struct mlx5_core_dev *mdev; 736 struct mlx5_roce roce; 737 MLX5_DECLARE_DOORBELL_LOCK(uar_lock); 738 int num_ports; 739 /* serialize update of capability mask 740 */ 741 struct mutex cap_mask_mutex; 742 bool ib_active; 743 struct umr_common umrc; 744 /* sync used page count stats 745 */ 746 struct mlx5_ib_resources devr; 747 struct mlx5_mr_cache cache; 748 struct timer_list delay_timer; 749 /* Prevents soft lock on massive reg MRs */ 750 struct mutex slow_path_mutex; 751 int fill_delay; 752 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 753 struct ib_odp_caps odp_caps; 754 /* 755 * Sleepable RCU that prevents destruction of MRs while they are still 756 * being used by a page fault handler. 757 */ 758 struct srcu_struct mr_srcu; 759 #endif 760 struct mlx5_ib_flow_db flow_db; 761 /* protect resources needed as part of reset flow */ 762 spinlock_t reset_flow_resource_lock; 763 struct list_head qp_list; 764 /* Array with num_ports elements */ 765 struct mlx5_ib_port *port; 766 struct mlx5_sq_bfreg bfreg; 767 struct mlx5_sq_bfreg wc_bfreg; 768 struct mlx5_sq_bfreg fp_bfreg; 769 struct mlx5_ib_congestion congestion; 770 771 struct mlx5_async_ctx async_ctx; 772 }; 773 774 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 775 { 776 return container_of(mcq, struct mlx5_ib_cq, mcq); 777 } 778 779 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 780 { 781 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 782 } 783 784 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 785 { 786 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 787 } 788 789 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 790 { 791 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 792 } 793 794 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 795 { 796 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 797 } 798 799 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 800 { 801 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 802 } 803 804 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mr *mmkey) 805 { 806 return container_of(mmkey, struct mlx5_ib_mr, mmkey); 807 } 808 809 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 810 { 811 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 812 } 813 814 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 815 { 816 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 817 } 818 819 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 820 { 821 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 822 } 823 824 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 825 { 826 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 827 } 828 829 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 830 { 831 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 832 } 833 834 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 835 { 836 return container_of(msrq, struct mlx5_ib_srq, msrq); 837 } 838 839 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 840 { 841 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 842 } 843 844 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 845 { 846 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 847 } 848 849 struct mlx5_ib_ah { 850 struct ib_ah ibah; 851 struct mlx5_av av; 852 }; 853 854 static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah) 855 { 856 return container_of(ibah, struct mlx5_ib_ah, ibah); 857 } 858 859 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, 860 struct mlx5_db *db); 861 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 862 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 863 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 864 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 865 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey, 866 u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, 867 const void *in_mad, void *response_mad); 868 struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr, 869 struct ib_udata *udata); 870 int mlx5_ib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr); 871 int mlx5_ib_destroy_ah(struct ib_ah *ah); 872 struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd, 873 struct ib_srq_init_attr *init_attr, 874 struct ib_udata *udata); 875 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 876 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 877 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 878 int mlx5_ib_destroy_srq(struct ib_srq *srq); 879 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, 880 const struct ib_recv_wr **bad_wr); 881 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 882 struct ib_qp_init_attr *init_attr, 883 struct ib_udata *udata); 884 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 885 int attr_mask, struct ib_udata *udata); 886 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 887 struct ib_qp_init_attr *qp_init_attr); 888 int mlx5_ib_destroy_qp(struct ib_qp *qp); 889 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 890 const struct ib_send_wr **bad_wr); 891 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 892 const struct ib_recv_wr **bad_wr); 893 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n); 894 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 895 void *buffer, u32 length, 896 struct mlx5_ib_qp_base *base); 897 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, 898 const struct ib_cq_init_attr *attr, 899 struct ib_ucontext *context, 900 struct ib_udata *udata); 901 int mlx5_ib_destroy_cq(struct ib_cq *cq); 902 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 903 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 904 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 905 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 906 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 907 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 908 u64 virt_addr, int access_flags, 909 struct ib_udata *udata); 910 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 911 struct ib_udata *udata); 912 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 913 int mlx5_ib_update_mtt(struct mlx5_ib_mr *mr, u64 start_page_index, 914 int npages, int zap); 915 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 916 u64 length, u64 virt_addr, int access_flags, 917 struct ib_pd *pd, struct ib_udata *udata); 918 int mlx5_ib_dereg_mr(struct ib_mr *ibmr); 919 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, 920 enum ib_mr_type mr_type, 921 u32 max_num_sg); 922 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 923 unsigned int *sg_offset); 924 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 925 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 926 const struct ib_mad_hdr *in, size_t in_mad_size, 927 struct ib_mad_hdr *out, size_t *out_mad_size, 928 u16 *out_mad_pkey_index); 929 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 930 struct ib_ucontext *context, 931 struct ib_udata *udata); 932 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd); 933 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset); 934 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port); 935 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev, 936 struct ib_smp *out_mad); 937 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 938 __be64 *sys_image_guid); 939 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 940 u16 *max_pkeys); 941 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 942 u32 *vendor_id); 943 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 944 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 945 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, 946 u16 *pkey); 947 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, 948 union ib_gid *gid); 949 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, 950 struct ib_port_attr *props); 951 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 952 struct ib_port_attr *props); 953 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev); 954 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev); 955 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, 956 unsigned long max_page_shift, 957 int *count, int *shift, 958 int *ncont, int *order); 959 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 960 int page_shift, size_t offset, size_t num_pages, 961 __be64 *pas, int access_flags); 962 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 963 int page_shift, __be64 *pas, int access_flags); 964 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 965 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq); 966 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); 967 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); 968 int mlx5_mr_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift); 969 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 970 struct ib_mr_status *mr_status); 971 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 972 struct ib_wq_init_attr *init_attr, 973 struct ib_udata *udata); 974 int mlx5_ib_destroy_wq(struct ib_wq *wq); 975 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 976 u32 wq_attr_mask, struct ib_udata *udata); 977 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 978 struct ib_rwq_ind_table_init_attr *init_attr, 979 struct ib_udata *udata); 980 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 981 982 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 983 extern struct workqueue_struct *mlx5_ib_page_fault_wq; 984 985 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); 986 void mlx5_ib_mr_pfault_handler(struct mlx5_ib_qp *qp, 987 struct mlx5_ib_pfault *pfault); 988 void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp); 989 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 990 void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev); 991 int __init mlx5_ib_odp_init(void); 992 void mlx5_ib_odp_cleanup(void); 993 void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp); 994 void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp); 995 void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start, 996 unsigned long end); 997 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 998 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) 999 { 1000 return; 1001 } 1002 1003 static inline void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp) {} 1004 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 1005 static inline void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev) {} 1006 static inline int mlx5_ib_odp_init(void) { return 0; } 1007 static inline void mlx5_ib_odp_cleanup(void) {} 1008 static inline void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp) {} 1009 static inline void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp) {} 1010 1011 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1012 1013 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 1014 u8 port, struct ifla_vf_info *info); 1015 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 1016 u8 port, int state); 1017 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 1018 u8 port, struct ifla_vf_stats *stats); 1019 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port, 1020 u64 guid, int type); 1021 1022 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 1023 int index); 1024 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, 1025 int index, enum ib_gid_type *gid_type); 1026 1027 /* GSI QP helper functions */ 1028 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd, 1029 struct ib_qp_init_attr *init_attr); 1030 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp); 1031 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 1032 int attr_mask); 1033 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 1034 int qp_attr_mask, 1035 struct ib_qp_init_attr *qp_init_attr); 1036 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr, 1037 const struct ib_send_wr **bad_wr); 1038 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr, 1039 const struct ib_recv_wr **bad_wr); 1040 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 1041 1042 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 1043 1044 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, 1045 int bfregn); 1046 static inline void init_query_mad(struct ib_smp *mad) 1047 { 1048 mad->base_version = 1; 1049 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 1050 mad->class_version = 1; 1051 mad->method = IB_MGMT_METHOD_GET; 1052 } 1053 1054 static inline u8 convert_access(int acc) 1055 { 1056 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 1057 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 1058 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 1059 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 1060 MLX5_PERM_LOCAL_READ; 1061 } 1062 1063 static inline int is_qp1(enum ib_qp_type qp_type) 1064 { 1065 return qp_type == MLX5_IB_QPT_HW_GSI; 1066 } 1067 1068 #define MLX5_MAX_UMR_SHIFT 16 1069 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) 1070 1071 static inline u32 check_cq_create_flags(u32 flags) 1072 { 1073 /* 1074 * It returns non-zero value for unsupported CQ 1075 * create flags, otherwise it returns zero. 1076 */ 1077 return (flags & ~(IB_CQ_FLAGS_IGNORE_OVERRUN | 1078 IB_CQ_FLAGS_TIMESTAMP_COMPLETION)); 1079 } 1080 1081 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 1082 u32 *user_index) 1083 { 1084 if (cqe_version) { 1085 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 1086 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 1087 return -EINVAL; 1088 *user_index = cmd_uidx; 1089 } else { 1090 *user_index = MLX5_IB_DEFAULT_UIDX; 1091 } 1092 1093 return 0; 1094 } 1095 1096 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 1097 struct mlx5_ib_create_qp *ucmd, 1098 int inlen, 1099 u32 *user_index) 1100 { 1101 u8 cqe_version = ucontext->cqe_version; 1102 1103 if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) && 1104 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1105 return 0; 1106 1107 if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) != 1108 !!cqe_version)) 1109 return -EINVAL; 1110 1111 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1112 } 1113 1114 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 1115 struct mlx5_ib_create_srq *ucmd, 1116 int inlen, 1117 u32 *user_index) 1118 { 1119 u8 cqe_version = ucontext->cqe_version; 1120 1121 if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) && 1122 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1123 return 0; 1124 1125 if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) != 1126 !!cqe_version)) 1127 return -EINVAL; 1128 1129 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1130 } 1131 1132 void mlx5_ib_cleanup_congestion(struct mlx5_ib_dev *); 1133 int mlx5_ib_init_congestion(struct mlx5_ib_dev *); 1134 1135 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) 1136 { 1137 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1138 MLX5_UARS_IN_PAGE : 1; 1139 } 1140 1141 static inline int get_num_static_uars(struct mlx5_ib_dev *dev, 1142 struct mlx5_bfreg_info *bfregi) 1143 { 1144 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages; 1145 } 1146 1147 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 1148 struct mlx5_bfreg_info *bfregi, u32 bfregn, 1149 bool dyn_bfreg); 1150 1151 #endif /* MLX5_IB_H */ 1152