1 /*- 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_IB_H 29 #define MLX5_IB_H 30 31 #include <linux/kernel.h> 32 #include <linux/sched.h> 33 #include <linux/printk.h> 34 #include <rdma/ib_verbs.h> 35 #include <rdma/ib_smi.h> 36 #include <dev/mlx5/cq.h> 37 #include <dev/mlx5/qp.h> 38 #include <dev/mlx5/srq.h> 39 #include <linux/types.h> 40 #include <dev/mlx5/mlx5_core/transobj.h> 41 #include <rdma/ib_user_verbs.h> 42 #include <rdma/mlx5-abi.h> 43 44 #define mlx5_ib_dbg(dev, format, arg...) \ 45 pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 46 __LINE__, current->pid, ##arg) 47 48 #define mlx5_ib_err(dev, format, arg...) \ 49 pr_err("%s: ERR: %s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 50 __LINE__, current->pid, ##arg) 51 52 #define mlx5_ib_warn(dev, format, arg...) \ 53 pr_warn("%s: WARN: %s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ 54 __LINE__, current->pid, ##arg) 55 56 #define field_avail(type, fld, sz) (offsetof(type, fld) + \ 57 sizeof(((type *)0)->fld) <= (sz)) 58 #define MLX5_IB_DEFAULT_UIDX 0xffffff 59 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 60 61 enum { 62 MLX5_IB_MMAP_CMD_SHIFT = 8, 63 MLX5_IB_MMAP_CMD_MASK = 0xff, 64 }; 65 66 enum mlx5_ib_mmap_cmd { 67 MLX5_IB_MMAP_REGULAR_PAGE = 0, 68 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, 69 MLX5_IB_MMAP_WC_PAGE = 2, 70 MLX5_IB_MMAP_NC_PAGE = 3, 71 /* 5 is chosen in order to be compatible with old versions of libmlx5 */ 72 MLX5_IB_MMAP_CORE_CLOCK = 5, 73 }; 74 75 enum { 76 MLX5_RES_SCAT_DATA32_CQE = 0x1, 77 MLX5_RES_SCAT_DATA64_CQE = 0x2, 78 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 79 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 80 }; 81 82 enum mlx5_ib_latency_class { 83 MLX5_IB_LATENCY_CLASS_LOW, 84 MLX5_IB_LATENCY_CLASS_MEDIUM, 85 MLX5_IB_LATENCY_CLASS_HIGH, 86 MLX5_IB_LATENCY_CLASS_FAST_PATH 87 }; 88 89 enum mlx5_ib_mad_ifc_flags { 90 MLX5_MAD_IFC_IGNORE_MKEY = 1, 91 MLX5_MAD_IFC_IGNORE_BKEY = 2, 92 MLX5_MAD_IFC_NET_VIEW = 4, 93 }; 94 95 enum { 96 MLX5_CROSS_CHANNEL_BFREG = 0, 97 }; 98 99 enum { 100 MLX5_CQE_VERSION_V0, 101 MLX5_CQE_VERSION_V1, 102 }; 103 104 enum { 105 MLX5_IB_INVALID_UAR_INDEX = BIT(31), 106 MLX5_IB_INVALID_BFREG = BIT(31), 107 }; 108 109 struct mlx5_ib_vma_private_data { 110 struct list_head list; 111 struct vm_area_struct *vma; 112 }; 113 114 struct mlx5_bfreg_info { 115 u32 *sys_pages; 116 int num_low_latency_bfregs; 117 unsigned int *count; 118 119 /* 120 * protect bfreg allocation data structs 121 */ 122 struct mutex lock; 123 u32 ver; 124 u8 lib_uar_4k : 1; 125 u8 lib_uar_dyn : 1; 126 u32 num_sys_pages; 127 u32 num_static_sys_pages; 128 u32 total_num_bfregs; 129 u32 num_dyn_bfregs; 130 }; 131 132 struct mlx5_ib_ucontext { 133 struct ib_ucontext ibucontext; 134 struct list_head db_page_list; 135 136 /* protect doorbell record alloc/free 137 */ 138 struct mutex db_page_mutex; 139 struct mlx5_bfreg_info bfregi; 140 u8 cqe_version; 141 /* Transport Domain number */ 142 u32 tdn; 143 struct list_head vma_private_list; 144 }; 145 146 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 147 { 148 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 149 } 150 151 struct mlx5_ib_pd { 152 struct ib_pd ibpd; 153 u32 pdn; 154 }; 155 156 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 157 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 158 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 159 #error "Invalid number of bypass priorities" 160 #endif 161 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 162 163 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 164 #define MLX5_IB_NUM_SNIFFER_FTS 2 165 struct mlx5_ib_flow_prio { 166 struct mlx5_flow_table *flow_table; 167 unsigned int refcount; 168 }; 169 170 struct mlx5_ib_flow_handler { 171 struct list_head list; 172 struct ib_flow ibflow; 173 struct mlx5_ib_flow_prio *prio; 174 struct mlx5_flow_rule *rule; 175 }; 176 177 struct mlx5_ib_flow_db { 178 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 179 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 180 struct mlx5_flow_table *lag_demux_ft; 181 /* Protect flow steering bypass flow tables 182 * when add/del flow rules. 183 * only single add/removal of flow steering rule could be done 184 * simultaneously. 185 */ 186 struct mutex lock; 187 }; 188 189 /* Use macros here so that don't have to duplicate 190 * enum ib_send_flags and enum ib_qp_type for low-level driver 191 */ 192 193 #define MLX5_IB_SEND_UMR_UNREG IB_SEND_RESERVED_START 194 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 1) 195 #define MLX5_IB_SEND_UMR_UPDATE_MTT (IB_SEND_RESERVED_START << 2) 196 197 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 3) 198 #define MLX5_IB_SEND_UMR_UPDATE_PD (IB_SEND_RESERVED_START << 4) 199 #define MLX5_IB_SEND_UMR_UPDATE_ACCESS IB_SEND_RESERVED_END 200 201 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 202 /* 203 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 204 * creates the actual hardware QP. 205 */ 206 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 207 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 208 209 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 210 * 211 * These flags are intended for internal use by the mlx5_ib driver, and they 212 * rely on the range reserved for that use in the ib_qp_create_flags enum. 213 */ 214 #define MLX5_IB_QP_CREATE_SQPN_QP1 IB_QP_CREATE_RESERVED_START 215 #define MLX5_IB_QP_CREATE_WC_TEST (IB_QP_CREATE_RESERVED_START << 1) 216 217 struct wr_list { 218 u16 opcode; 219 u16 next; 220 }; 221 222 struct mlx5_ib_wq { 223 u64 *wrid; 224 u32 *wr_data; 225 struct wr_list *w_list; 226 unsigned *wqe_head; 227 u16 unsig_count; 228 229 /* serialize post to the work queue 230 */ 231 spinlock_t lock; 232 int wqe_cnt; 233 int max_post; 234 int max_gs; 235 int offset; 236 int wqe_shift; 237 unsigned head; 238 unsigned tail; 239 u16 cur_post; 240 u16 last_poll; 241 void *qend; 242 }; 243 244 struct mlx5_ib_rwq { 245 struct ib_wq ibwq; 246 struct mlx5_core_qp core_qp; 247 u32 rq_num_pas; 248 u32 log_rq_stride; 249 u32 log_rq_size; 250 u32 rq_page_offset; 251 u32 log_page_size; 252 struct ib_umem *umem; 253 size_t buf_size; 254 unsigned int page_shift; 255 int create_type; 256 struct mlx5_db db; 257 u32 user_index; 258 u32 wqe_count; 259 u32 wqe_shift; 260 int wq_sig; 261 }; 262 263 enum { 264 MLX5_QP_USER, 265 MLX5_QP_KERNEL, 266 MLX5_QP_EMPTY 267 }; 268 269 enum { 270 MLX5_WQ_USER, 271 MLX5_WQ_KERNEL 272 }; 273 274 struct mlx5_ib_rwq_ind_table { 275 struct ib_rwq_ind_table ib_rwq_ind_tbl; 276 u32 rqtn; 277 }; 278 279 /* 280 * Connect-IB can trigger up to four concurrent pagefaults 281 * per-QP. 282 */ 283 enum mlx5_ib_pagefault_context { 284 MLX5_IB_PAGEFAULT_RESPONDER_READ, 285 MLX5_IB_PAGEFAULT_REQUESTOR_READ, 286 MLX5_IB_PAGEFAULT_RESPONDER_WRITE, 287 MLX5_IB_PAGEFAULT_REQUESTOR_WRITE, 288 MLX5_IB_PAGEFAULT_CONTEXTS 289 }; 290 291 static inline enum mlx5_ib_pagefault_context 292 mlx5_ib_get_pagefault_context(struct mlx5_pagefault *pagefault) 293 { 294 return pagefault->flags & (MLX5_PFAULT_REQUESTOR | MLX5_PFAULT_WRITE); 295 } 296 297 struct mlx5_ib_pfault { 298 struct work_struct work; 299 struct mlx5_pagefault mpfault; 300 }; 301 302 struct mlx5_ib_ubuffer { 303 struct ib_umem *umem; 304 int buf_size; 305 u64 buf_addr; 306 }; 307 308 struct mlx5_ib_qp_base { 309 struct mlx5_ib_qp *container_mibqp; 310 struct mlx5_core_qp mqp; 311 struct mlx5_ib_ubuffer ubuffer; 312 }; 313 314 struct mlx5_ib_qp_trans { 315 struct mlx5_ib_qp_base base; 316 u16 xrcdn; 317 u8 alt_port; 318 u8 atomic_rd_en; 319 u8 resp_depth; 320 }; 321 322 struct mlx5_ib_rss_qp { 323 u32 tirn; 324 }; 325 326 struct mlx5_ib_rq { 327 struct mlx5_ib_qp_base base; 328 struct mlx5_ib_wq *rq; 329 struct mlx5_ib_ubuffer ubuffer; 330 struct mlx5_db *doorbell; 331 u32 tirn; 332 u8 state; 333 }; 334 335 struct mlx5_ib_sq { 336 struct mlx5_ib_qp_base base; 337 struct mlx5_ib_wq *sq; 338 struct mlx5_ib_ubuffer ubuffer; 339 struct mlx5_db *doorbell; 340 u32 tisn; 341 u8 state; 342 }; 343 344 struct mlx5_ib_raw_packet_qp { 345 struct mlx5_ib_sq sq; 346 struct mlx5_ib_rq rq; 347 }; 348 349 struct mlx5_bf { 350 int buf_size; 351 unsigned long offset; 352 struct mlx5_sq_bfreg *bfreg; 353 spinlock_t lock32; 354 }; 355 356 struct mlx5_ib_qp { 357 struct ib_qp ibqp; 358 union { 359 struct mlx5_ib_qp_trans trans_qp; 360 struct mlx5_ib_raw_packet_qp raw_packet_qp; 361 struct mlx5_ib_rss_qp rss_qp; 362 }; 363 struct mlx5_buf buf; 364 365 struct mlx5_db db; 366 struct mlx5_ib_wq rq; 367 368 u8 sq_signal_bits; 369 u8 fm_cache; 370 struct mlx5_ib_wq sq; 371 372 /* serialize qp state modifications 373 */ 374 struct mutex mutex; 375 u32 flags; 376 u8 port; 377 u8 state; 378 int wq_sig; 379 int scat_cqe; 380 int max_inline_data; 381 struct mlx5_bf bf; 382 int has_rq; 383 384 /* only for user space QPs. For kernel 385 * we have it from the bf object 386 */ 387 int bfregn; 388 389 int create_type; 390 391 /* Store signature errors */ 392 bool signature_en; 393 394 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 395 /* 396 * A flag that is true for QP's that are in a state that doesn't 397 * allow page faults, and shouldn't schedule any more faults. 398 */ 399 int disable_page_faults; 400 /* 401 * The disable_page_faults_lock protects a QP's disable_page_faults 402 * field, allowing for a thread to atomically check whether the QP 403 * allows page faults, and if so schedule a page fault. 404 */ 405 spinlock_t disable_page_faults_lock; 406 struct mlx5_ib_pfault pagefaults[MLX5_IB_PAGEFAULT_CONTEXTS]; 407 #endif 408 struct list_head qps_list; 409 struct list_head cq_recv_list; 410 struct list_head cq_send_list; 411 }; 412 413 struct mlx5_ib_cq_buf { 414 struct mlx5_buf buf; 415 struct ib_umem *umem; 416 int cqe_size; 417 int nent; 418 }; 419 420 enum mlx5_ib_qp_flags { 421 MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO, 422 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, 423 MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL, 424 MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND, 425 MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV, 426 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5, 427 /* QP uses 1 as its source QP number */ 428 MLX5_IB_QP_SQPN_QP1 = 1 << 6, 429 MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7, 430 MLX5_IB_QP_RSS = 1 << 8, 431 }; 432 433 struct mlx5_umr_wr { 434 struct ib_send_wr wr; 435 union { 436 u64 virt_addr; 437 u64 offset; 438 } target; 439 struct ib_pd *pd; 440 unsigned int page_shift; 441 unsigned int npages; 442 u32 length; 443 int access_flags; 444 u32 mkey; 445 }; 446 447 static inline struct mlx5_umr_wr *umr_wr(struct ib_send_wr *wr) 448 { 449 return container_of(wr, struct mlx5_umr_wr, wr); 450 } 451 452 struct mlx5_shared_mr_info { 453 int mr_id; 454 struct ib_umem *umem; 455 }; 456 457 struct mlx5_ib_cq { 458 struct ib_cq ibcq; 459 struct mlx5_core_cq mcq; 460 struct mlx5_ib_cq_buf buf; 461 struct mlx5_db db; 462 463 /* serialize access to the CQ 464 */ 465 spinlock_t lock; 466 467 /* protect resize cq 468 */ 469 struct mutex resize_mutex; 470 struct mlx5_ib_cq_buf *resize_buf; 471 struct ib_umem *resize_umem; 472 int cqe_size; 473 struct list_head list_send_qp; 474 struct list_head list_recv_qp; 475 u32 create_flags; 476 struct list_head wc_list; 477 enum ib_cq_notify_flags notify_flags; 478 struct work_struct notify_work; 479 }; 480 481 struct mlx5_ib_wc { 482 struct ib_wc wc; 483 struct list_head list; 484 }; 485 486 struct mlx5_ib_srq { 487 struct ib_srq ibsrq; 488 struct mlx5_core_srq msrq; 489 struct mlx5_buf buf; 490 struct mlx5_db db; 491 u64 *wrid; 492 /* protect SRQ hanlding 493 */ 494 spinlock_t lock; 495 int head; 496 int tail; 497 u16 wqe_ctr; 498 struct ib_umem *umem; 499 /* serialize arming a SRQ 500 */ 501 struct mutex mutex; 502 int wq_sig; 503 }; 504 505 struct mlx5_ib_xrcd { 506 struct ib_xrcd ibxrcd; 507 u32 xrcdn; 508 }; 509 510 enum mlx5_ib_mtt_access_flags { 511 MLX5_IB_MTT_READ = (1 << 0), 512 MLX5_IB_MTT_WRITE = (1 << 1), 513 }; 514 515 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 516 517 struct mlx5_ib_mr { 518 struct ib_mr ibmr; 519 void *descs; 520 dma_addr_t desc_map; 521 int ndescs; 522 int max_descs; 523 int desc_size; 524 int access_mode; 525 struct mlx5_core_mr mmkey; 526 struct ib_umem *umem; 527 struct mlx5_shared_mr_info *smr_info; 528 struct list_head list; 529 int order; 530 int umred; 531 int npages; 532 struct mlx5_ib_dev *dev; 533 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 534 struct mlx5_core_sig_ctx *sig; 535 int live; 536 void *descs_alloc; 537 int access_flags; /* Needed for rereg MR */ 538 struct mlx5_async_work cb_work; 539 }; 540 541 struct mlx5_ib_mw { 542 struct ib_mw ibmw; 543 struct mlx5_core_mr mmkey; 544 }; 545 546 struct mlx5_ib_umr_context { 547 struct ib_cqe cqe; 548 enum ib_wc_status status; 549 struct completion done; 550 }; 551 552 struct umr_common { 553 struct ib_pd *pd; 554 struct ib_cq *cq; 555 struct ib_qp *qp; 556 /* control access to UMR QP 557 */ 558 struct semaphore sem; 559 }; 560 561 enum { 562 MLX5_FMR_INVALID, 563 MLX5_FMR_VALID, 564 MLX5_FMR_BUSY, 565 }; 566 567 struct mlx5_cache_ent { 568 struct list_head head; 569 /* sync access to the cahce entry 570 */ 571 spinlock_t lock; 572 573 574 struct dentry *dir; 575 char name[4]; 576 u32 order; 577 u32 size; 578 u32 cur; 579 u32 miss; 580 u32 limit; 581 582 struct dentry *fsize; 583 struct dentry *fcur; 584 struct dentry *fmiss; 585 struct dentry *flimit; 586 587 struct mlx5_ib_dev *dev; 588 struct work_struct work; 589 struct delayed_work dwork; 590 int pending; 591 }; 592 593 struct mlx5_mr_cache { 594 struct workqueue_struct *wq; 595 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; 596 int stopped; 597 struct dentry *root; 598 unsigned long last_add; 599 }; 600 601 struct mlx5_ib_gsi_qp; 602 603 struct mlx5_ib_port_resources { 604 struct mlx5_ib_resources *devr; 605 struct mlx5_ib_gsi_qp *gsi; 606 struct work_struct pkey_change_work; 607 }; 608 609 struct mlx5_ib_resources { 610 struct ib_cq *c0; 611 struct ib_xrcd *x0; 612 struct ib_xrcd *x1; 613 struct ib_pd *p0; 614 struct ib_srq *s0; 615 struct ib_srq *s1; 616 struct mlx5_ib_port_resources ports[2]; 617 /* Protects changes to the port resources */ 618 struct mutex mutex; 619 }; 620 621 struct mlx5_ib_port { 622 u16 q_cnt_id; 623 }; 624 625 struct mlx5_roce { 626 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 627 * netdev pointer 628 */ 629 rwlock_t netdev_lock; 630 struct net_device *netdev; 631 struct notifier_block nb; 632 atomic_t next_port; 633 }; 634 635 #define MLX5_IB_STATS_COUNT(a,b,c,d) a 636 #define MLX5_IB_STATS_VAR(a,b,c,d) b; 637 #define MLX5_IB_STATS_DESC(a,b,c,d) c, d, 638 639 #define MLX5_IB_CONG_PARAMS(m) \ 640 /* ECN RP */ \ 641 m(+1, u64 rp_clamp_tgt_rate, "rp_clamp_tgt_rate", "If set, whenever a CNP is processed, the target rate is updated to be the current rate") \ 642 m(+1, u64 rp_clamp_tgt_rate_ati, "rp_clamp_tgt_rate_ati", "If set, when receiving a CNP, the target rate should be updated if the transission rate was increased due to the timer, and not only due to the byte counter") \ 643 m(+1, u64 rp_time_reset, "rp_time_reset", "Time in microseconds between rate increases if no CNPs are received") \ 644 m(+1, u64 rp_byte_reset, "rp_byte_reset", "Transmitted data in bytes between rate increases if no CNP's are received. A value of zero means disabled.") \ 645 m(+1, u64 rp_threshold, "rp_threshold", "The number of times rpByteStage or rpTimeStage can count before the RP rate control state machine advances states") \ 646 m(+1, u64 rp_ai_rate, "rp_ai_rate", "The rate, in Mbits per second, used to increase rpTargetRate in the active increase state") \ 647 m(+1, u64 rp_hai_rate, "rp_hai_rate", "The rate, in Mbits per second, used to increase rpTargetRate in the hyper increase state") \ 648 m(+1, u64 rp_min_dec_fac, "rp_min_dec_fac", "The minimum factor by which the current transmit rate can be changed when processing a CNP. Value is given as a percentage, [1 .. 100]") \ 649 m(+1, u64 rp_min_rate, "rp_min_rate", "The minimum value, in Mbps per second, for rate to limit") \ 650 m(+1, u64 rp_rate_to_set_on_first_cnp, "rp_rate_to_set_on_first_cnp", "The rate that is set for the flow when a rate limiter is allocated to it upon first CNP received, in Mbps. A value of zero means use full port speed") \ 651 m(+1, u64 rp_dce_tcp_g, "rp_dce_tcp_g", "Used to update the congestion estimator, alpha, once every dce_tcp_rtt once every dce_tcp_rtt microseconds") \ 652 m(+1, u64 rp_dce_tcp_rtt, "rp_dce_tcp_rtt", "The time between updates of the aolpha value, in microseconds") \ 653 m(+1, u64 rp_rate_reduce_monitor_period, "rp_rate_reduce_monitor_period", "The minimum time between two consecutive rate reductions for a single flow") \ 654 m(+1, u64 rp_initial_alpha_value, "rp_initial_alpha_value", "The initial value of alpha to use when receiving the first CNP for a flow") \ 655 m(+1, u64 rp_gd, "rp_gd", "If a CNP is received, the flow rate is reduced at the beginning of the next rate_reduce_monitor_period interval") \ 656 /* ECN NP */ \ 657 m(+1, u64 np_cnp_dscp, "np_cnp_dscp", "The DiffServ Code Point of the generated CNP for this port") \ 658 m(+1, u64 np_cnp_prio_mode, "np_cnp_prio_mode", "The 802.1p priority value of the generated CNP for this port") \ 659 m(+1, u64 np_cnp_prio, "np_cnp_prio", "The 802.1p priority value of the generated CNP for this port") 660 661 #define MLX5_IB_CONG_PARAMS_NUM (0 MLX5_IB_CONG_PARAMS(MLX5_IB_STATS_COUNT)) 662 663 #define MLX5_IB_CONG_STATS(m) \ 664 m(+1, u64 syndrome, "syndrome", "Syndrome number") \ 665 m(+1, u64 rp_cur_flows, "rp_cur_flows", "Number of flows limited") \ 666 m(+1, u64 sum_flows, "sum_flows", "Sum of the number of flows limited over time") \ 667 m(+1, u64 rp_cnp_ignored, "rp_cnp_ignored", "Number of CNPs and CNMs ignored") \ 668 m(+1, u64 rp_cnp_handled, "rp_cnp_handled", "Number of CNPs and CNMs successfully handled") \ 669 m(+1, u64 time_stamp, "time_stamp", "Time stamp in microseconds") \ 670 m(+1, u64 accumulators_period, "accumulators_period", "The value of X variable for accumulating counters") \ 671 m(+1, u64 np_ecn_marked_roce_packets, "np_ecn_marked_roce_packets", "Number of ECN marked packets seen") \ 672 m(+1, u64 np_cnp_sent, "np_cnp_sent", "Number of CNPs sent") 673 674 #define MLX5_IB_CONG_STATS_NUM (0 MLX5_IB_CONG_STATS(MLX5_IB_STATS_COUNT)) 675 676 struct mlx5_ib_congestion { 677 struct sysctl_ctx_list ctx; 678 struct sx lock; 679 struct delayed_work dwork; 680 union { 681 u64 arg[1]; 682 struct { 683 MLX5_IB_CONG_PARAMS(MLX5_IB_STATS_VAR) 684 MLX5_IB_CONG_STATS(MLX5_IB_STATS_VAR) 685 }; 686 }; 687 }; 688 689 struct mlx5_ib_dev { 690 struct ib_device ib_dev; 691 struct mlx5_core_dev *mdev; 692 struct mlx5_roce roce; 693 MLX5_DECLARE_DOORBELL_LOCK(uar_lock); 694 int num_ports; 695 /* serialize update of capability mask 696 */ 697 struct mutex cap_mask_mutex; 698 bool ib_active; 699 struct umr_common umrc; 700 /* sync used page count stats 701 */ 702 struct mlx5_ib_resources devr; 703 struct mlx5_mr_cache cache; 704 struct timer_list delay_timer; 705 /* Prevents soft lock on massive reg MRs */ 706 struct mutex slow_path_mutex; 707 int fill_delay; 708 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 709 struct ib_odp_caps odp_caps; 710 /* 711 * Sleepable RCU that prevents destruction of MRs while they are still 712 * being used by a page fault handler. 713 */ 714 struct srcu_struct mr_srcu; 715 #endif 716 struct mlx5_ib_flow_db flow_db; 717 /* protect resources needed as part of reset flow */ 718 spinlock_t reset_flow_resource_lock; 719 struct list_head qp_list; 720 /* Array with num_ports elements */ 721 struct mlx5_ib_port *port; 722 struct mlx5_sq_bfreg bfreg; 723 struct mlx5_sq_bfreg wc_bfreg; 724 struct mlx5_sq_bfreg fp_bfreg; 725 struct mlx5_ib_congestion congestion; 726 727 struct mlx5_async_ctx async_ctx; 728 }; 729 730 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 731 { 732 return container_of(mcq, struct mlx5_ib_cq, mcq); 733 } 734 735 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 736 { 737 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 738 } 739 740 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 741 { 742 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 743 } 744 745 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 746 { 747 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 748 } 749 750 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 751 { 752 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 753 } 754 755 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 756 { 757 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 758 } 759 760 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mr *mmkey) 761 { 762 return container_of(mmkey, struct mlx5_ib_mr, mmkey); 763 } 764 765 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 766 { 767 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 768 } 769 770 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 771 { 772 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 773 } 774 775 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 776 { 777 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 778 } 779 780 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 781 { 782 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 783 } 784 785 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 786 { 787 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 788 } 789 790 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 791 { 792 return container_of(msrq, struct mlx5_ib_srq, msrq); 793 } 794 795 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 796 { 797 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 798 } 799 800 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 801 { 802 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 803 } 804 805 struct mlx5_ib_ah { 806 struct ib_ah ibah; 807 struct mlx5_av av; 808 }; 809 810 static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah) 811 { 812 return container_of(ibah, struct mlx5_ib_ah, ibah); 813 } 814 815 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, 816 struct mlx5_db *db); 817 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 818 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 819 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 820 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 821 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey, 822 u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, 823 const void *in_mad, void *response_mad); 824 struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr, 825 struct ib_udata *udata); 826 int mlx5_ib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr); 827 int mlx5_ib_destroy_ah(struct ib_ah *ah); 828 struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd, 829 struct ib_srq_init_attr *init_attr, 830 struct ib_udata *udata); 831 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 832 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 833 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 834 int mlx5_ib_destroy_srq(struct ib_srq *srq); 835 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr, 836 struct ib_recv_wr **bad_wr); 837 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 838 struct ib_qp_init_attr *init_attr, 839 struct ib_udata *udata); 840 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 841 int attr_mask, struct ib_udata *udata); 842 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 843 struct ib_qp_init_attr *qp_init_attr); 844 int mlx5_ib_destroy_qp(struct ib_qp *qp); 845 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 846 struct ib_send_wr **bad_wr); 847 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 848 struct ib_recv_wr **bad_wr); 849 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n); 850 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 851 void *buffer, u32 length, 852 struct mlx5_ib_qp_base *base); 853 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, 854 const struct ib_cq_init_attr *attr, 855 struct ib_ucontext *context, 856 struct ib_udata *udata); 857 int mlx5_ib_destroy_cq(struct ib_cq *cq); 858 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 859 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 860 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 861 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 862 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 863 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 864 u64 virt_addr, int access_flags, 865 struct ib_udata *udata); 866 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 867 struct ib_udata *udata); 868 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 869 int mlx5_ib_update_mtt(struct mlx5_ib_mr *mr, u64 start_page_index, 870 int npages, int zap); 871 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 872 u64 length, u64 virt_addr, int access_flags, 873 struct ib_pd *pd, struct ib_udata *udata); 874 int mlx5_ib_dereg_mr(struct ib_mr *ibmr); 875 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, 876 enum ib_mr_type mr_type, 877 u32 max_num_sg); 878 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 879 unsigned int *sg_offset); 880 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 881 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 882 const struct ib_mad_hdr *in, size_t in_mad_size, 883 struct ib_mad_hdr *out, size_t *out_mad_size, 884 u16 *out_mad_pkey_index); 885 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 886 struct ib_ucontext *context, 887 struct ib_udata *udata); 888 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd); 889 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset); 890 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port); 891 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev, 892 struct ib_smp *out_mad); 893 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 894 __be64 *sys_image_guid); 895 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 896 u16 *max_pkeys); 897 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 898 u32 *vendor_id); 899 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 900 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 901 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, 902 u16 *pkey); 903 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, 904 union ib_gid *gid); 905 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, 906 struct ib_port_attr *props); 907 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 908 struct ib_port_attr *props); 909 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev); 910 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev); 911 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift, 912 int *ncont, int *order); 913 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 914 int page_shift, size_t offset, size_t num_pages, 915 __be64 *pas, int access_flags); 916 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 917 int page_shift, __be64 *pas, int access_flags); 918 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 919 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq); 920 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); 921 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); 922 int mlx5_mr_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift); 923 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 924 struct ib_mr_status *mr_status); 925 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 926 struct ib_wq_init_attr *init_attr, 927 struct ib_udata *udata); 928 int mlx5_ib_destroy_wq(struct ib_wq *wq); 929 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 930 u32 wq_attr_mask, struct ib_udata *udata); 931 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 932 struct ib_rwq_ind_table_init_attr *init_attr, 933 struct ib_udata *udata); 934 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 935 936 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 937 extern struct workqueue_struct *mlx5_ib_page_fault_wq; 938 939 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); 940 void mlx5_ib_mr_pfault_handler(struct mlx5_ib_qp *qp, 941 struct mlx5_ib_pfault *pfault); 942 void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp); 943 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 944 void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev); 945 int __init mlx5_ib_odp_init(void); 946 void mlx5_ib_odp_cleanup(void); 947 void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp); 948 void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp); 949 void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start, 950 unsigned long end); 951 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 952 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) 953 { 954 return; 955 } 956 957 static inline void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp) {} 958 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 959 static inline void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev) {} 960 static inline int mlx5_ib_odp_init(void) { return 0; } 961 static inline void mlx5_ib_odp_cleanup(void) {} 962 static inline void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp) {} 963 static inline void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp) {} 964 965 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 966 967 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 968 u8 port, struct ifla_vf_info *info); 969 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 970 u8 port, int state); 971 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 972 u8 port, struct ifla_vf_stats *stats); 973 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port, 974 u64 guid, int type); 975 976 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 977 int index); 978 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, 979 int index, enum ib_gid_type *gid_type); 980 981 /* GSI QP helper functions */ 982 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd, 983 struct ib_qp_init_attr *init_attr); 984 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp); 985 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 986 int attr_mask); 987 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 988 int qp_attr_mask, 989 struct ib_qp_init_attr *qp_init_attr); 990 int mlx5_ib_gsi_post_send(struct ib_qp *qp, struct ib_send_wr *wr, 991 struct ib_send_wr **bad_wr); 992 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, struct ib_recv_wr *wr, 993 struct ib_recv_wr **bad_wr); 994 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 995 996 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 997 998 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, 999 int bfregn); 1000 static inline void init_query_mad(struct ib_smp *mad) 1001 { 1002 mad->base_version = 1; 1003 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 1004 mad->class_version = 1; 1005 mad->method = IB_MGMT_METHOD_GET; 1006 } 1007 1008 static inline u8 convert_access(int acc) 1009 { 1010 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 1011 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 1012 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 1013 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 1014 MLX5_PERM_LOCAL_READ; 1015 } 1016 1017 static inline int is_qp1(enum ib_qp_type qp_type) 1018 { 1019 return qp_type == MLX5_IB_QPT_HW_GSI; 1020 } 1021 1022 #define MLX5_MAX_UMR_SHIFT 16 1023 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) 1024 1025 static inline u32 check_cq_create_flags(u32 flags) 1026 { 1027 /* 1028 * It returns non-zero value for unsupported CQ 1029 * create flags, otherwise it returns zero. 1030 */ 1031 return (flags & ~(IB_CQ_FLAGS_IGNORE_OVERRUN | 1032 IB_CQ_FLAGS_TIMESTAMP_COMPLETION)); 1033 } 1034 1035 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 1036 u32 *user_index) 1037 { 1038 if (cqe_version) { 1039 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 1040 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 1041 return -EINVAL; 1042 *user_index = cmd_uidx; 1043 } else { 1044 *user_index = MLX5_IB_DEFAULT_UIDX; 1045 } 1046 1047 return 0; 1048 } 1049 1050 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 1051 struct mlx5_ib_create_qp *ucmd, 1052 int inlen, 1053 u32 *user_index) 1054 { 1055 u8 cqe_version = ucontext->cqe_version; 1056 1057 if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) && 1058 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1059 return 0; 1060 1061 if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) != 1062 !!cqe_version)) 1063 return -EINVAL; 1064 1065 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1066 } 1067 1068 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 1069 struct mlx5_ib_create_srq *ucmd, 1070 int inlen, 1071 u32 *user_index) 1072 { 1073 u8 cqe_version = ucontext->cqe_version; 1074 1075 if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) && 1076 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1077 return 0; 1078 1079 if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) != 1080 !!cqe_version)) 1081 return -EINVAL; 1082 1083 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1084 } 1085 1086 void mlx5_ib_cleanup_congestion(struct mlx5_ib_dev *); 1087 int mlx5_ib_init_congestion(struct mlx5_ib_dev *); 1088 1089 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) 1090 { 1091 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1092 MLX5_UARS_IN_PAGE : 1; 1093 } 1094 1095 static inline int get_num_static_uars(struct mlx5_ib_dev *dev, 1096 struct mlx5_bfreg_info *bfregi) 1097 { 1098 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages; 1099 } 1100 1101 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 1102 struct mlx5_bfreg_info *bfregi, u32 bfregn, 1103 bool dyn_bfreg); 1104 1105 #endif /* MLX5_IB_H */ 1106