1 /*- 2 * Copyright (c) 2017 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef __MLX5_FPGA_TRANS_H__ 34 #define __MLX5_FPGA_TRANS_H__ 35 36 #include <dev/mlx5/mlx5_fpga/sdk.h> 37 #include <dev/mlx5/mlx5_fpga/core.h> 38 39 #define MLX5_FPGA_TRANSACTION_MAX_SIZE 1008 40 #define MLX5_FPGA_TRANSACTION_SEND_ALIGN_BITS 3 41 #define MLX5_FPGA_TRANSACTION_SEND_PAGE_BITS 12 42 #define MLX5_FPGA_TID_COUNT 256 43 44 enum mlx5_fpga_direction { 45 MLX5_FPGA_READ, 46 MLX5_FPGA_WRITE, 47 }; 48 49 struct mlx5_fpga_transaction { 50 struct mlx5_fpga_conn *conn; 51 enum mlx5_fpga_direction direction; 52 size_t size; 53 u64 addr; 54 u8 *data; 55 void (*complete1)(const struct mlx5_fpga_transaction *complete, 56 u8 status); 57 }; 58 59 int mlx5_fpga_trans_device_init(struct mlx5_fpga_device *fdev); 60 void mlx5_fpga_trans_device_cleanup(struct mlx5_fpga_device *fdev); 61 int mlx5_fpga_trans_exec(const struct mlx5_fpga_transaction *trans); 62 void mlx5_fpga_trans_recv(void *cb_arg, struct mlx5_fpga_dma_buf *buf); 63 64 #endif /* __MLX_FPGA_TRANS_H__ */ 65