1 /*- 2 * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_IFC_FPGA_H 34 #define MLX5_IFC_FPGA_H 35 36 enum { 37 MLX5_FPGA_CAP_SANDBOX_VENDOR_ID_MLNX = 0x2c9, 38 }; 39 40 enum { 41 MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_EXAMPLE = 0x1, 42 MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_IPSEC = 0x2, 43 MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_TLS = 0x3, 44 }; 45 46 enum { 47 MLX5_FPGA_SHELL_CAPS_QP_TYPE_SHELL_QP = 0x1, 48 MLX5_FPGA_SHELL_CAPS_QP_TYPE_SANDBOX_QP = 0x2, 49 }; 50 51 struct mlx5_ifc_fpga_shell_caps_bits { 52 u8 max_num_qps[0x10]; 53 u8 reserved_at_10[0x8]; 54 u8 total_rcv_credits[0x8]; 55 56 u8 reserved_at_20[0xe]; 57 u8 qp_type[0x2]; 58 u8 reserved_at_30[0x5]; 59 u8 rae[0x1]; 60 u8 rwe[0x1]; 61 u8 rre[0x1]; 62 u8 reserved_at_38[0x4]; 63 u8 dc[0x1]; 64 u8 ud[0x1]; 65 u8 uc[0x1]; 66 u8 rc[0x1]; 67 68 u8 reserved_at_40[0x1a]; 69 u8 log_ddr_size[0x6]; 70 71 u8 max_fpga_qp_msg_size[0x20]; 72 73 u8 reserved_at_80[0x180]; 74 }; 75 76 struct mlx5_ifc_fpga_cap_bits { 77 u8 fpga_id[0x8]; 78 u8 fpga_device[0x18]; 79 80 u8 register_file_ver[0x20]; 81 82 u8 fpga_ctrl_modify[0x1]; 83 u8 reserved_at_41[0x5]; 84 u8 access_reg_query_mode[0x2]; 85 u8 reserved_at_48[0x6]; 86 u8 access_reg_modify_mode[0x2]; 87 u8 reserved_at_50[0x10]; 88 89 u8 reserved_at_60[0x20]; 90 91 u8 image_version[0x20]; 92 93 u8 image_date[0x20]; 94 95 u8 image_time[0x20]; 96 97 u8 shell_version[0x20]; 98 99 u8 reserved_at_100[0x80]; 100 101 struct mlx5_ifc_fpga_shell_caps_bits shell_caps; 102 103 u8 reserved_at_380[0x8]; 104 u8 ieee_vendor_id[0x18]; 105 106 u8 sandbox_product_version[0x10]; 107 u8 sandbox_product_id[0x10]; 108 109 u8 sandbox_basic_caps[0x20]; 110 111 u8 reserved_at_3e0[0x10]; 112 u8 sandbox_extended_caps_len[0x10]; 113 114 u8 sandbox_extended_caps_addr[0x40]; 115 116 u8 fpga_ddr_start_addr[0x40]; 117 118 u8 fpga_cr_space_start_addr[0x40]; 119 120 u8 fpga_ddr_size[0x20]; 121 122 u8 fpga_cr_space_size[0x20]; 123 124 u8 reserved_at_500[0x300]; 125 }; 126 127 enum { 128 MLX5_FPGA_CTRL_OPERATION_LOAD = 0x1, 129 MLX5_FPGA_CTRL_OPERATION_RESET = 0x2, 130 MLX5_FPGA_CTRL_OPERATION_FLASH_SELECT = 0x3, 131 MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_ON = 0x4, 132 MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_OFF = 0x5, 133 MLX5_FPGA_CTRL_OPERATION_RESET_SANDBOX = 0x6, 134 MLX5_FPGA_CTRL_OPERATION_DISCONNECT = 0x9, 135 MLX5_FPGA_CTRL_OPERATION_CONNECT = 0xA, 136 MLX5_FPGA_CTRL_OPERATION_RELOAD = 0xB, 137 }; 138 139 struct mlx5_ifc_fpga_ctrl_bits { 140 u8 reserved_at_0[0x8]; 141 u8 operation[0x8]; 142 u8 reserved_at_10[0x8]; 143 u8 status[0x8]; 144 145 u8 reserved_at_20[0x8]; 146 u8 flash_select_admin[0x8]; 147 u8 reserved_at_30[0x8]; 148 u8 flash_select_oper[0x8]; 149 150 u8 reserved_at_40[0x40]; 151 }; 152 153 enum { 154 MLX5_FPGA_ERROR_EVENT_SYNDROME_CORRUPTED_DDR = 0x1, 155 MLX5_FPGA_ERROR_EVENT_SYNDROME_FLASH_TIMEOUT = 0x2, 156 MLX5_FPGA_ERROR_EVENT_SYNDROME_INTERNAL_LINK_ERROR = 0x3, 157 MLX5_FPGA_ERROR_EVENT_SYNDROME_WATCHDOG_FAILURE = 0x4, 158 MLX5_FPGA_ERROR_EVENT_SYNDROME_I2C_FAILURE = 0x5, 159 MLX5_FPGA_ERROR_EVENT_SYNDROME_IMAGE_CHANGED = 0x6, 160 MLX5_FPGA_ERROR_EVENT_SYNDROME_TEMPERATURE_CRITICAL = 0x7, 161 }; 162 163 struct mlx5_ifc_fpga_error_event_bits { 164 u8 reserved_at_0[0x40]; 165 166 u8 reserved_at_40[0x18]; 167 u8 syndrome[0x8]; 168 169 u8 reserved_at_60[0x80]; 170 }; 171 172 #define MLX5_FPGA_ACCESS_REG_SIZE_MAX 64 173 174 struct mlx5_ifc_fpga_access_reg_bits { 175 u8 reserved_at_0[0x20]; 176 177 u8 reserved_at_20[0x10]; 178 u8 size[0x10]; 179 180 u8 address[0x40]; 181 182 u8 data[0][0x8]; 183 }; 184 185 enum mlx5_ifc_fpga_qp_state { 186 MLX5_FPGA_QPC_STATE_INIT = 0x0, 187 MLX5_FPGA_QPC_STATE_ACTIVE = 0x1, 188 MLX5_FPGA_QPC_STATE_ERROR = 0x2, 189 }; 190 191 enum mlx5_ifc_fpga_qp_type { 192 MLX5_FPGA_QPC_QP_TYPE_SHELL_QP = 0x0, 193 MLX5_FPGA_QPC_QP_TYPE_SANDBOX_QP = 0x1, 194 }; 195 196 enum mlx5_ifc_fpga_qp_service_type { 197 MLX5_FPGA_QPC_ST_RC = 0x0, 198 }; 199 200 struct mlx5_ifc_fpga_qpc_bits { 201 u8 state[0x4]; 202 u8 reserved_at_4[0x1b]; 203 u8 qp_type[0x1]; 204 205 u8 reserved_at_20[0x4]; 206 u8 st[0x4]; 207 u8 reserved_at_28[0x10]; 208 u8 traffic_class[0x8]; 209 210 u8 ether_type[0x10]; 211 u8 prio[0x3]; 212 u8 dei[0x1]; 213 u8 vid[0xc]; 214 215 u8 reserved_at_60[0x20]; 216 217 u8 reserved_at_80[0x8]; 218 u8 next_rcv_psn[0x18]; 219 220 u8 reserved_at_a0[0x8]; 221 u8 next_send_psn[0x18]; 222 223 u8 reserved_at_c0[0x10]; 224 u8 pkey[0x10]; 225 226 u8 reserved_at_e0[0x8]; 227 u8 remote_qpn[0x18]; 228 229 u8 reserved_at_100[0x15]; 230 u8 rnr_retry[0x3]; 231 u8 reserved_at_118[0x5]; 232 u8 retry_count[0x3]; 233 234 u8 reserved_at_120[0x20]; 235 236 u8 reserved_at_140[0x10]; 237 u8 remote_mac_47_32[0x10]; 238 239 u8 remote_mac_31_0[0x20]; 240 241 u8 remote_ip[16][0x8]; 242 243 u8 reserved_at_200[0x40]; 244 245 u8 reserved_at_240[0x10]; 246 u8 fpga_mac_47_32[0x10]; 247 248 u8 fpga_mac_31_0[0x20]; 249 250 u8 fpga_ip[16][0x8]; 251 }; 252 253 struct mlx5_ifc_fpga_create_qp_in_bits { 254 u8 opcode[0x10]; 255 u8 reserved_at_10[0x10]; 256 257 u8 reserved_at_20[0x10]; 258 u8 op_mod[0x10]; 259 260 u8 reserved_at_40[0x40]; 261 262 struct mlx5_ifc_fpga_qpc_bits fpga_qpc; 263 }; 264 265 struct mlx5_ifc_fpga_create_qp_out_bits { 266 u8 status[0x8]; 267 u8 reserved_at_8[0x18]; 268 269 u8 syndrome[0x20]; 270 271 u8 reserved_at_40[0x8]; 272 u8 fpga_qpn[0x18]; 273 274 u8 reserved_at_60[0x20]; 275 276 struct mlx5_ifc_fpga_qpc_bits fpga_qpc; 277 }; 278 279 struct mlx5_ifc_fpga_modify_qp_in_bits { 280 u8 opcode[0x10]; 281 u8 reserved_at_10[0x10]; 282 283 u8 reserved_at_20[0x10]; 284 u8 op_mod[0x10]; 285 286 u8 reserved_at_40[0x8]; 287 u8 fpga_qpn[0x18]; 288 289 u8 field_select[0x20]; 290 291 struct mlx5_ifc_fpga_qpc_bits fpga_qpc; 292 }; 293 294 struct mlx5_ifc_fpga_modify_qp_out_bits { 295 u8 status[0x8]; 296 u8 reserved_at_8[0x18]; 297 298 u8 syndrome[0x20]; 299 300 u8 reserved_at_40[0x40]; 301 }; 302 303 struct mlx5_ifc_fpga_query_qp_in_bits { 304 u8 opcode[0x10]; 305 u8 reserved_at_10[0x10]; 306 307 u8 reserved_at_20[0x10]; 308 u8 op_mod[0x10]; 309 310 u8 reserved_at_40[0x8]; 311 u8 fpga_qpn[0x18]; 312 313 u8 reserved_at_60[0x20]; 314 }; 315 316 struct mlx5_ifc_fpga_query_qp_out_bits { 317 u8 status[0x8]; 318 u8 reserved_at_8[0x18]; 319 320 u8 syndrome[0x20]; 321 322 u8 reserved_at_40[0x40]; 323 324 struct mlx5_ifc_fpga_qpc_bits fpga_qpc; 325 }; 326 327 struct mlx5_ifc_fpga_query_qp_counters_in_bits { 328 u8 opcode[0x10]; 329 u8 reserved_at_10[0x10]; 330 331 u8 reserved_at_20[0x10]; 332 u8 op_mod[0x10]; 333 334 u8 clear[0x1]; 335 u8 reserved_at_41[0x7]; 336 u8 fpga_qpn[0x18]; 337 338 u8 reserved_at_60[0x20]; 339 }; 340 341 struct mlx5_ifc_fpga_query_qp_counters_out_bits { 342 u8 status[0x8]; 343 u8 reserved_at_8[0x18]; 344 345 u8 syndrome[0x20]; 346 347 u8 reserved_at_40[0x40]; 348 349 u8 rx_ack_packets[0x40]; 350 351 u8 rx_send_packets[0x40]; 352 353 u8 tx_ack_packets[0x40]; 354 355 u8 tx_send_packets[0x40]; 356 357 u8 rx_total_drop[0x40]; 358 359 u8 reserved_at_1c0[0x1c0]; 360 }; 361 362 struct mlx5_ifc_fpga_destroy_qp_in_bits { 363 u8 opcode[0x10]; 364 u8 reserved_at_10[0x10]; 365 366 u8 reserved_at_20[0x10]; 367 u8 op_mod[0x10]; 368 369 u8 reserved_at_40[0x8]; 370 u8 fpga_qpn[0x18]; 371 372 u8 reserved_at_60[0x20]; 373 }; 374 375 struct mlx5_ifc_fpga_destroy_qp_out_bits { 376 u8 status[0x8]; 377 u8 reserved_at_8[0x18]; 378 379 u8 syndrome[0x20]; 380 381 u8 reserved_at_40[0x40]; 382 }; 383 384 struct mlx5_ifc_ipsec_extended_cap_bits { 385 u8 encapsulation[0x20]; 386 387 u8 reserved_0[0x15]; 388 u8 ipv4_fragment[0x1]; 389 u8 ipv6[0x1]; 390 u8 esn[0x1]; 391 u8 lso[0x1]; 392 u8 transport_and_tunnel_mode[0x1]; 393 u8 tunnel_mode[0x1]; 394 u8 transport_mode[0x1]; 395 u8 ah_esp[0x1]; 396 u8 esp[0x1]; 397 u8 ah[0x1]; 398 u8 ipv4_options[0x1]; 399 400 u8 auth_alg[0x20]; 401 402 u8 enc_alg[0x20]; 403 404 u8 sa_cap[0x20]; 405 406 u8 reserved_1[0x10]; 407 u8 number_of_ipsec_counters[0x10]; 408 409 u8 ipsec_counters_addr_low[0x20]; 410 u8 ipsec_counters_addr_high[0x20]; 411 }; 412 413 struct mlx5_ifc_ipsec_counters_bits { 414 u8 dec_in_packets[0x40]; 415 416 u8 dec_out_packets[0x40]; 417 418 u8 dec_bypass_packets[0x40]; 419 420 u8 enc_in_packets[0x40]; 421 422 u8 enc_out_packets[0x40]; 423 424 u8 enc_bypass_packets[0x40]; 425 426 u8 drop_dec_packets[0x40]; 427 428 u8 failed_auth_dec_packets[0x40]; 429 430 u8 drop_enc_packets[0x40]; 431 432 u8 success_add_sa[0x40]; 433 434 u8 fail_add_sa[0x40]; 435 436 u8 success_delete_sa[0x40]; 437 438 u8 fail_delete_sa[0x40]; 439 440 u8 dropped_cmd[0x40]; 441 }; 442 443 struct mlx5_ifc_fpga_shell_counters_bits { 444 u8 reserved_0[0x20]; 445 446 u8 clear[0x1]; 447 u8 reserved_1[0x1f]; 448 449 u8 reserved_2[0x40]; 450 451 u8 ddr_read_requests[0x40]; 452 453 u8 ddr_write_requests[0x40]; 454 455 u8 ddr_read_bytes[0x40]; 456 457 u8 ddr_write_bytes[0x40]; 458 459 u8 reserved_3[0x200]; 460 }; 461 462 enum { 463 MLX5_FPGA_SHELL_QP_PACKET_TYPE_DDR_READ = 0x0, 464 MLX5_FPGA_SHELL_QP_PACKET_TYPE_DDR_WRITE = 0x1, 465 MLX5_FPGA_SHELL_QP_PACKET_TYPE_DDR_READ_RESPONSE = 0x2, 466 MLX5_FPGA_SHELL_QP_PACKET_TYPE_DDR_WRITE_RESPONSE = 0x3, 467 }; 468 469 struct mlx5_ifc_fpga_shell_qp_packet_bits { 470 u8 version[0x4]; 471 u8 syndrome[0x4]; 472 u8 reserved_at_8[0x4]; 473 u8 type[0x4]; 474 u8 reserved_at_10[0x8]; 475 u8 tid[0x8]; 476 477 u8 len[0x20]; 478 479 u8 address[0x40]; 480 481 u8 data[0][0x8]; 482 }; 483 484 enum { 485 MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RETRY_COUNTER_EXPIRED = 0x1, 486 MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RNR_EXPIRED = 0x2, 487 }; 488 489 struct mlx5_ifc_fpga_qp_error_event_bits { 490 u8 reserved_0[0x40]; 491 492 u8 reserved_1[0x18]; 493 u8 syndrome[0x8]; 494 495 u8 reserved_2[0x60]; 496 497 u8 reserved_3[0x8]; 498 u8 fpga_qpn[0x18]; 499 }; 500 501 #endif /* MLX5_IFC_FPGA_H */ 502