1 /*- 2 * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 * $FreeBSD$ 33 */ 34 35 #ifndef MLX5_IFC_FPGA_H 36 #define MLX5_IFC_FPGA_H 37 38 enum { 39 MLX5_FPGA_CAP_SANDBOX_VENDOR_ID_MLNX = 0x2c9, 40 }; 41 42 enum { 43 MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_EXAMPLE = 0x1, 44 MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_IPSEC = 0x2, 45 MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_TLS = 0x3, 46 }; 47 48 enum { 49 MLX5_FPGA_SHELL_CAPS_QP_TYPE_SHELL_QP = 0x1, 50 MLX5_FPGA_SHELL_CAPS_QP_TYPE_SANDBOX_QP = 0x2, 51 }; 52 53 struct mlx5_ifc_fpga_shell_caps_bits { 54 u8 max_num_qps[0x10]; 55 u8 reserved_at_10[0x8]; 56 u8 total_rcv_credits[0x8]; 57 58 u8 reserved_at_20[0xe]; 59 u8 qp_type[0x2]; 60 u8 reserved_at_30[0x5]; 61 u8 rae[0x1]; 62 u8 rwe[0x1]; 63 u8 rre[0x1]; 64 u8 reserved_at_38[0x4]; 65 u8 dc[0x1]; 66 u8 ud[0x1]; 67 u8 uc[0x1]; 68 u8 rc[0x1]; 69 70 u8 reserved_at_40[0x1a]; 71 u8 log_ddr_size[0x6]; 72 73 u8 max_fpga_qp_msg_size[0x20]; 74 75 u8 reserved_at_80[0x180]; 76 }; 77 78 struct mlx5_ifc_fpga_cap_bits { 79 u8 fpga_id[0x8]; 80 u8 fpga_device[0x18]; 81 82 u8 register_file_ver[0x20]; 83 84 u8 fpga_ctrl_modify[0x1]; 85 u8 reserved_at_41[0x5]; 86 u8 access_reg_query_mode[0x2]; 87 u8 reserved_at_48[0x6]; 88 u8 access_reg_modify_mode[0x2]; 89 u8 reserved_at_50[0x10]; 90 91 u8 reserved_at_60[0x20]; 92 93 u8 image_version[0x20]; 94 95 u8 image_date[0x20]; 96 97 u8 image_time[0x20]; 98 99 u8 shell_version[0x20]; 100 101 u8 reserved_at_100[0x80]; 102 103 struct mlx5_ifc_fpga_shell_caps_bits shell_caps; 104 105 u8 reserved_at_380[0x8]; 106 u8 ieee_vendor_id[0x18]; 107 108 u8 sandbox_product_version[0x10]; 109 u8 sandbox_product_id[0x10]; 110 111 u8 sandbox_basic_caps[0x20]; 112 113 u8 reserved_at_3e0[0x10]; 114 u8 sandbox_extended_caps_len[0x10]; 115 116 u8 sandbox_extended_caps_addr[0x40]; 117 118 u8 fpga_ddr_start_addr[0x40]; 119 120 u8 fpga_cr_space_start_addr[0x40]; 121 122 u8 fpga_ddr_size[0x20]; 123 124 u8 fpga_cr_space_size[0x20]; 125 126 u8 reserved_at_500[0x300]; 127 }; 128 129 enum { 130 MLX5_FPGA_CTRL_OPERATION_LOAD = 0x1, 131 MLX5_FPGA_CTRL_OPERATION_RESET = 0x2, 132 MLX5_FPGA_CTRL_OPERATION_FLASH_SELECT = 0x3, 133 MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_ON = 0x4, 134 MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_OFF = 0x5, 135 MLX5_FPGA_CTRL_OPERATION_RESET_SANDBOX = 0x6, 136 MLX5_FPGA_CTRL_OPERATION_DISCONNECT = 0x9, 137 MLX5_FPGA_CTRL_OPERATION_CONNECT = 0xA, 138 }; 139 140 struct mlx5_ifc_fpga_ctrl_bits { 141 u8 reserved_at_0[0x8]; 142 u8 operation[0x8]; 143 u8 reserved_at_10[0x8]; 144 u8 status[0x8]; 145 146 u8 reserved_at_20[0x8]; 147 u8 flash_select_admin[0x8]; 148 u8 reserved_at_30[0x8]; 149 u8 flash_select_oper[0x8]; 150 151 u8 reserved_at_40[0x40]; 152 }; 153 154 enum { 155 MLX5_FPGA_ERROR_EVENT_SYNDROME_CORRUPTED_DDR = 0x1, 156 MLX5_FPGA_ERROR_EVENT_SYNDROME_FLASH_TIMEOUT = 0x2, 157 MLX5_FPGA_ERROR_EVENT_SYNDROME_INTERNAL_LINK_ERROR = 0x3, 158 MLX5_FPGA_ERROR_EVENT_SYNDROME_WATCHDOG_FAILURE = 0x4, 159 MLX5_FPGA_ERROR_EVENT_SYNDROME_I2C_FAILURE = 0x5, 160 MLX5_FPGA_ERROR_EVENT_SYNDROME_IMAGE_CHANGED = 0x6, 161 MLX5_FPGA_ERROR_EVENT_SYNDROME_TEMPERATURE_CRITICAL = 0x7, 162 }; 163 164 struct mlx5_ifc_fpga_error_event_bits { 165 u8 reserved_at_0[0x40]; 166 167 u8 reserved_at_40[0x18]; 168 u8 syndrome[0x8]; 169 170 u8 reserved_at_60[0x80]; 171 }; 172 173 #define MLX5_FPGA_ACCESS_REG_SIZE_MAX 64 174 175 struct mlx5_ifc_fpga_access_reg_bits { 176 u8 reserved_at_0[0x20]; 177 178 u8 reserved_at_20[0x10]; 179 u8 size[0x10]; 180 181 u8 address[0x40]; 182 183 u8 data[0][0x8]; 184 }; 185 186 enum mlx5_ifc_fpga_qp_state { 187 MLX5_FPGA_QPC_STATE_INIT = 0x0, 188 MLX5_FPGA_QPC_STATE_ACTIVE = 0x1, 189 MLX5_FPGA_QPC_STATE_ERROR = 0x2, 190 }; 191 192 enum mlx5_ifc_fpga_qp_type { 193 MLX5_FPGA_QPC_QP_TYPE_SHELL_QP = 0x0, 194 MLX5_FPGA_QPC_QP_TYPE_SANDBOX_QP = 0x1, 195 }; 196 197 enum mlx5_ifc_fpga_qp_service_type { 198 MLX5_FPGA_QPC_ST_RC = 0x0, 199 }; 200 201 struct mlx5_ifc_fpga_qpc_bits { 202 u8 state[0x4]; 203 u8 reserved_at_4[0x1b]; 204 u8 qp_type[0x1]; 205 206 u8 reserved_at_20[0x4]; 207 u8 st[0x4]; 208 u8 reserved_at_28[0x10]; 209 u8 traffic_class[0x8]; 210 211 u8 ether_type[0x10]; 212 u8 prio[0x3]; 213 u8 dei[0x1]; 214 u8 vid[0xc]; 215 216 u8 reserved_at_60[0x20]; 217 218 u8 reserved_at_80[0x8]; 219 u8 next_rcv_psn[0x18]; 220 221 u8 reserved_at_a0[0x8]; 222 u8 next_send_psn[0x18]; 223 224 u8 reserved_at_c0[0x10]; 225 u8 pkey[0x10]; 226 227 u8 reserved_at_e0[0x8]; 228 u8 remote_qpn[0x18]; 229 230 u8 reserved_at_100[0x15]; 231 u8 rnr_retry[0x3]; 232 u8 reserved_at_118[0x5]; 233 u8 retry_count[0x3]; 234 235 u8 reserved_at_120[0x20]; 236 237 u8 reserved_at_140[0x10]; 238 u8 remote_mac_47_32[0x10]; 239 240 u8 remote_mac_31_0[0x20]; 241 242 u8 remote_ip[16][0x8]; 243 244 u8 reserved_at_200[0x40]; 245 246 u8 reserved_at_240[0x10]; 247 u8 fpga_mac_47_32[0x10]; 248 249 u8 fpga_mac_31_0[0x20]; 250 251 u8 fpga_ip[16][0x8]; 252 }; 253 254 struct mlx5_ifc_fpga_create_qp_in_bits { 255 u8 opcode[0x10]; 256 u8 reserved_at_10[0x10]; 257 258 u8 reserved_at_20[0x10]; 259 u8 op_mod[0x10]; 260 261 u8 reserved_at_40[0x40]; 262 263 struct mlx5_ifc_fpga_qpc_bits fpga_qpc; 264 }; 265 266 struct mlx5_ifc_fpga_create_qp_out_bits { 267 u8 status[0x8]; 268 u8 reserved_at_8[0x18]; 269 270 u8 syndrome[0x20]; 271 272 u8 reserved_at_40[0x8]; 273 u8 fpga_qpn[0x18]; 274 275 u8 reserved_at_60[0x20]; 276 277 struct mlx5_ifc_fpga_qpc_bits fpga_qpc; 278 }; 279 280 struct mlx5_ifc_fpga_modify_qp_in_bits { 281 u8 opcode[0x10]; 282 u8 reserved_at_10[0x10]; 283 284 u8 reserved_at_20[0x10]; 285 u8 op_mod[0x10]; 286 287 u8 reserved_at_40[0x8]; 288 u8 fpga_qpn[0x18]; 289 290 u8 field_select[0x20]; 291 292 struct mlx5_ifc_fpga_qpc_bits fpga_qpc; 293 }; 294 295 struct mlx5_ifc_fpga_modify_qp_out_bits { 296 u8 status[0x8]; 297 u8 reserved_at_8[0x18]; 298 299 u8 syndrome[0x20]; 300 301 u8 reserved_at_40[0x40]; 302 }; 303 304 struct mlx5_ifc_fpga_query_qp_in_bits { 305 u8 opcode[0x10]; 306 u8 reserved_at_10[0x10]; 307 308 u8 reserved_at_20[0x10]; 309 u8 op_mod[0x10]; 310 311 u8 reserved_at_40[0x8]; 312 u8 fpga_qpn[0x18]; 313 314 u8 reserved_at_60[0x20]; 315 }; 316 317 struct mlx5_ifc_fpga_query_qp_out_bits { 318 u8 status[0x8]; 319 u8 reserved_at_8[0x18]; 320 321 u8 syndrome[0x20]; 322 323 u8 reserved_at_40[0x40]; 324 325 struct mlx5_ifc_fpga_qpc_bits fpga_qpc; 326 }; 327 328 struct mlx5_ifc_fpga_query_qp_counters_in_bits { 329 u8 opcode[0x10]; 330 u8 reserved_at_10[0x10]; 331 332 u8 reserved_at_20[0x10]; 333 u8 op_mod[0x10]; 334 335 u8 clear[0x1]; 336 u8 reserved_at_41[0x7]; 337 u8 fpga_qpn[0x18]; 338 339 u8 reserved_at_60[0x20]; 340 }; 341 342 struct mlx5_ifc_fpga_query_qp_counters_out_bits { 343 u8 status[0x8]; 344 u8 reserved_at_8[0x18]; 345 346 u8 syndrome[0x20]; 347 348 u8 reserved_at_40[0x40]; 349 350 u8 rx_ack_packets[0x40]; 351 352 u8 rx_send_packets[0x40]; 353 354 u8 tx_ack_packets[0x40]; 355 356 u8 tx_send_packets[0x40]; 357 358 u8 rx_total_drop[0x40]; 359 360 u8 reserved_at_1c0[0x1c0]; 361 }; 362 363 struct mlx5_ifc_fpga_destroy_qp_in_bits { 364 u8 opcode[0x10]; 365 u8 reserved_at_10[0x10]; 366 367 u8 reserved_at_20[0x10]; 368 u8 op_mod[0x10]; 369 370 u8 reserved_at_40[0x8]; 371 u8 fpga_qpn[0x18]; 372 373 u8 reserved_at_60[0x20]; 374 }; 375 376 struct mlx5_ifc_fpga_destroy_qp_out_bits { 377 u8 status[0x8]; 378 u8 reserved_at_8[0x18]; 379 380 u8 syndrome[0x20]; 381 382 u8 reserved_at_40[0x40]; 383 }; 384 385 struct mlx5_ifc_ipsec_extended_cap_bits { 386 u8 encapsulation[0x20]; 387 388 u8 reserved_0[0x15]; 389 u8 ipv4_fragment[0x1]; 390 u8 ipv6[0x1]; 391 u8 esn[0x1]; 392 u8 lso[0x1]; 393 u8 transport_and_tunnel_mode[0x1]; 394 u8 tunnel_mode[0x1]; 395 u8 transport_mode[0x1]; 396 u8 ah_esp[0x1]; 397 u8 esp[0x1]; 398 u8 ah[0x1]; 399 u8 ipv4_options[0x1]; 400 401 u8 auth_alg[0x20]; 402 403 u8 enc_alg[0x20]; 404 405 u8 sa_cap[0x20]; 406 407 u8 reserved_1[0x10]; 408 u8 number_of_ipsec_counters[0x10]; 409 410 u8 ipsec_counters_addr_low[0x20]; 411 u8 ipsec_counters_addr_high[0x20]; 412 }; 413 414 struct mlx5_ifc_ipsec_counters_bits { 415 u8 dec_in_packets[0x40]; 416 417 u8 dec_out_packets[0x40]; 418 419 u8 dec_bypass_packets[0x40]; 420 421 u8 enc_in_packets[0x40]; 422 423 u8 enc_out_packets[0x40]; 424 425 u8 enc_bypass_packets[0x40]; 426 427 u8 drop_dec_packets[0x40]; 428 429 u8 failed_auth_dec_packets[0x40]; 430 431 u8 drop_enc_packets[0x40]; 432 433 u8 success_add_sa[0x40]; 434 435 u8 fail_add_sa[0x40]; 436 437 u8 success_delete_sa[0x40]; 438 439 u8 fail_delete_sa[0x40]; 440 441 u8 dropped_cmd[0x40]; 442 }; 443 444 struct mlx5_ifc_fpga_shell_counters_bits { 445 u8 reserved_0[0x20]; 446 447 u8 clear[0x1]; 448 u8 reserved_1[0x1f]; 449 450 u8 reserved_2[0x40]; 451 452 u8 ddr_read_requests[0x40]; 453 454 u8 ddr_write_requests[0x40]; 455 456 u8 ddr_read_bytes[0x40]; 457 458 u8 ddr_write_bytes[0x40]; 459 460 u8 reserved_3[0x200]; 461 }; 462 463 enum { 464 MLX5_FPGA_SHELL_QP_PACKET_TYPE_DDR_READ = 0x0, 465 MLX5_FPGA_SHELL_QP_PACKET_TYPE_DDR_WRITE = 0x1, 466 MLX5_FPGA_SHELL_QP_PACKET_TYPE_DDR_READ_RESPONSE = 0x2, 467 MLX5_FPGA_SHELL_QP_PACKET_TYPE_DDR_WRITE_RESPONSE = 0x3, 468 }; 469 470 struct mlx5_ifc_fpga_shell_qp_packet_bits { 471 u8 version[0x4]; 472 u8 syndrome[0x4]; 473 u8 reserved_at_8[0x4]; 474 u8 type[0x4]; 475 u8 reserved_at_10[0x8]; 476 u8 tid[0x8]; 477 478 u8 len[0x20]; 479 480 u8 address[0x40]; 481 482 u8 data[0][0x8]; 483 }; 484 485 enum { 486 MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RETRY_COUNTER_EXPIRED = 0x1, 487 MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RNR_EXPIRED = 0x2, 488 }; 489 490 struct mlx5_ifc_fpga_qp_error_event_bits { 491 u8 reserved_0[0x40]; 492 493 u8 reserved_1[0x18]; 494 u8 syndrome[0x8]; 495 496 u8 reserved_2[0x60]; 497 498 u8 reserved_3[0x8]; 499 u8 fpga_qpn[0x18]; 500 }; 501 502 #endif /* MLX5_IFC_FPGA_H */ 503