1 /*- 2 * Copyright (c) 2017 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef __MLX5_FPGA_CONN_H__ 34 #define __MLX5_FPGA_CONN_H__ 35 36 #include <dev/mlx5/cq.h> 37 #include <dev/mlx5/qp.h> 38 #include <dev/mlx5/mlx5_fpga/core.h> 39 #include <dev/mlx5/mlx5_fpga/sdk.h> 40 #include <dev/mlx5/mlx5_core/wq.h> 41 #include <linux/interrupt.h> 42 43 struct mlx5_fpga_conn { 44 struct mlx5_fpga_device *fdev; 45 46 void (*recv_cb)(void *cb_arg, struct mlx5_fpga_dma_buf *buf); 47 void *cb_arg; 48 49 /* FPGA QP */ 50 u32 fpga_qpc[MLX5_ST_SZ_DW(fpga_qpc)]; 51 u32 fpga_qpn; 52 53 /* CQ */ 54 struct { 55 struct mlx5_cqwq wq; 56 struct mlx5_frag_wq_ctrl wq_ctrl; 57 struct mlx5_core_cq mcq; 58 struct tasklet_struct tasklet; 59 } cq; 60 61 /* QP */ 62 struct { 63 bool active; 64 int sgid_index; 65 struct mlx5_wq_qp wq; 66 struct mlx5_wq_ctrl wq_ctrl; 67 struct mlx5_core_qp mqp; 68 struct { 69 spinlock_t lock; /* Protects all SQ state */ 70 unsigned int pc; 71 unsigned int cc; 72 unsigned int size; 73 struct mlx5_fpga_dma_buf **bufs; 74 struct list_head backlog; 75 } sq; 76 struct { 77 unsigned int pc; 78 unsigned int cc; 79 unsigned int size; 80 struct mlx5_fpga_dma_buf **bufs; 81 } rq; 82 } qp; 83 }; 84 85 int mlx5_fpga_conn_device_init(struct mlx5_fpga_device *fdev); 86 void mlx5_fpga_conn_device_cleanup(struct mlx5_fpga_device *fdev); 87 struct mlx5_fpga_conn * 88 mlx5_fpga_conn_create(struct mlx5_fpga_device *fdev, 89 struct mlx5_fpga_conn_attr *attr, 90 enum mlx5_ifc_fpga_qp_type qp_type); 91 void mlx5_fpga_conn_destroy(struct mlx5_fpga_conn *conn); 92 int mlx5_fpga_conn_send(struct mlx5_fpga_conn *conn, 93 struct mlx5_fpga_dma_buf *buf); 94 95 #endif /* __MLX5_FPGA_CONN_H__ */ 96