1*e9dcd831SSlava Shwartsman /*- 2*e9dcd831SSlava Shwartsman * Copyright (c) 2017 Mellanox Technologies. All rights reserved. 3*e9dcd831SSlava Shwartsman * 4*e9dcd831SSlava Shwartsman * This software is available to you under a choice of one of two 5*e9dcd831SSlava Shwartsman * licenses. You may choose to be licensed under the terms of the GNU 6*e9dcd831SSlava Shwartsman * General Public License (GPL) Version 2, available from the file 7*e9dcd831SSlava Shwartsman * COPYING in the main directory of this source tree, or the 8*e9dcd831SSlava Shwartsman * OpenIB.org BSD license below: 9*e9dcd831SSlava Shwartsman * 10*e9dcd831SSlava Shwartsman * Redistribution and use in source and binary forms, with or 11*e9dcd831SSlava Shwartsman * without modification, are permitted provided that the following 12*e9dcd831SSlava Shwartsman * conditions are met: 13*e9dcd831SSlava Shwartsman * 14*e9dcd831SSlava Shwartsman * - Redistributions of source code must retain the above 15*e9dcd831SSlava Shwartsman * copyright notice, this list of conditions and the following 16*e9dcd831SSlava Shwartsman * disclaimer. 17*e9dcd831SSlava Shwartsman * 18*e9dcd831SSlava Shwartsman * - Redistributions in binary form must reproduce the above 19*e9dcd831SSlava Shwartsman * copyright notice, this list of conditions and the following 20*e9dcd831SSlava Shwartsman * disclaimer in the documentation and/or other materials 21*e9dcd831SSlava Shwartsman * provided with the distribution. 22*e9dcd831SSlava Shwartsman * 23*e9dcd831SSlava Shwartsman * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24*e9dcd831SSlava Shwartsman * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25*e9dcd831SSlava Shwartsman * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26*e9dcd831SSlava Shwartsman * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27*e9dcd831SSlava Shwartsman * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28*e9dcd831SSlava Shwartsman * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29*e9dcd831SSlava Shwartsman * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30*e9dcd831SSlava Shwartsman * SOFTWARE. 31*e9dcd831SSlava Shwartsman */ 32*e9dcd831SSlava Shwartsman 33*e9dcd831SSlava Shwartsman #ifndef __MLX5_FPGA_CONN_H__ 34*e9dcd831SSlava Shwartsman #define __MLX5_FPGA_CONN_H__ 35*e9dcd831SSlava Shwartsman 36*e9dcd831SSlava Shwartsman #include <dev/mlx5/cq.h> 37*e9dcd831SSlava Shwartsman #include <dev/mlx5/qp.h> 38*e9dcd831SSlava Shwartsman #include <dev/mlx5/mlx5_fpga/core.h> 39*e9dcd831SSlava Shwartsman #include <dev/mlx5/mlx5_fpga/sdk.h> 40*e9dcd831SSlava Shwartsman #include <dev/mlx5/mlx5_core/wq.h> 41*e9dcd831SSlava Shwartsman #include <linux/interrupt.h> 42*e9dcd831SSlava Shwartsman 43*e9dcd831SSlava Shwartsman struct mlx5_fpga_conn { 44*e9dcd831SSlava Shwartsman struct mlx5_fpga_device *fdev; 45*e9dcd831SSlava Shwartsman 46*e9dcd831SSlava Shwartsman void (*recv_cb)(void *cb_arg, struct mlx5_fpga_dma_buf *buf); 47*e9dcd831SSlava Shwartsman void *cb_arg; 48*e9dcd831SSlava Shwartsman 49*e9dcd831SSlava Shwartsman /* FPGA QP */ 50*e9dcd831SSlava Shwartsman u32 fpga_qpc[MLX5_ST_SZ_DW(fpga_qpc)]; 51*e9dcd831SSlava Shwartsman u32 fpga_qpn; 52*e9dcd831SSlava Shwartsman 53*e9dcd831SSlava Shwartsman /* CQ */ 54*e9dcd831SSlava Shwartsman struct { 55*e9dcd831SSlava Shwartsman struct mlx5_cqwq wq; 56*e9dcd831SSlava Shwartsman struct mlx5_frag_wq_ctrl wq_ctrl; 57*e9dcd831SSlava Shwartsman struct mlx5_core_cq mcq; 58*e9dcd831SSlava Shwartsman struct tasklet_struct tasklet; 59*e9dcd831SSlava Shwartsman } cq; 60*e9dcd831SSlava Shwartsman 61*e9dcd831SSlava Shwartsman /* QP */ 62*e9dcd831SSlava Shwartsman struct { 63*e9dcd831SSlava Shwartsman bool active; 64*e9dcd831SSlava Shwartsman int sgid_index; 65*e9dcd831SSlava Shwartsman struct mlx5_wq_qp wq; 66*e9dcd831SSlava Shwartsman struct mlx5_wq_ctrl wq_ctrl; 67*e9dcd831SSlava Shwartsman struct mlx5_core_qp mqp; 68*e9dcd831SSlava Shwartsman struct { 69*e9dcd831SSlava Shwartsman spinlock_t lock; /* Protects all SQ state */ 70*e9dcd831SSlava Shwartsman unsigned int pc; 71*e9dcd831SSlava Shwartsman unsigned int cc; 72*e9dcd831SSlava Shwartsman unsigned int size; 73*e9dcd831SSlava Shwartsman struct mlx5_fpga_dma_buf **bufs; 74*e9dcd831SSlava Shwartsman struct list_head backlog; 75*e9dcd831SSlava Shwartsman } sq; 76*e9dcd831SSlava Shwartsman struct { 77*e9dcd831SSlava Shwartsman unsigned int pc; 78*e9dcd831SSlava Shwartsman unsigned int cc; 79*e9dcd831SSlava Shwartsman unsigned int size; 80*e9dcd831SSlava Shwartsman struct mlx5_fpga_dma_buf **bufs; 81*e9dcd831SSlava Shwartsman } rq; 82*e9dcd831SSlava Shwartsman } qp; 83*e9dcd831SSlava Shwartsman }; 84*e9dcd831SSlava Shwartsman 85*e9dcd831SSlava Shwartsman int mlx5_fpga_conn_device_init(struct mlx5_fpga_device *fdev); 86*e9dcd831SSlava Shwartsman void mlx5_fpga_conn_device_cleanup(struct mlx5_fpga_device *fdev); 87*e9dcd831SSlava Shwartsman struct mlx5_fpga_conn * 88*e9dcd831SSlava Shwartsman mlx5_fpga_conn_create(struct mlx5_fpga_device *fdev, 89*e9dcd831SSlava Shwartsman struct mlx5_fpga_conn_attr *attr, 90*e9dcd831SSlava Shwartsman enum mlx5_ifc_fpga_qp_type qp_type); 91*e9dcd831SSlava Shwartsman void mlx5_fpga_conn_destroy(struct mlx5_fpga_conn *conn); 92*e9dcd831SSlava Shwartsman int mlx5_fpga_conn_send(struct mlx5_fpga_conn *conn, 93*e9dcd831SSlava Shwartsman struct mlx5_fpga_dma_buf *buf); 94*e9dcd831SSlava Shwartsman 95*e9dcd831SSlava Shwartsman #endif /* __MLX5_FPGA_CONN_H__ */ 96