1 /*- 2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include "en.h" 29 #include <machine/atomic.h> 30 31 void 32 mlx5e_send_nop(struct mlx5e_sq *sq, u32 ds_cnt, bool notify_hw) 33 { 34 u16 pi = sq->pc & sq->wq.sz_m1; 35 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, pi); 36 37 memset(&wqe->ctrl, 0, sizeof(wqe->ctrl)); 38 39 wqe->ctrl.opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_NOP); 40 wqe->ctrl.qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt); 41 wqe->ctrl.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; 42 43 sq->mbuf[pi].mbuf = NULL; 44 sq->mbuf[pi].num_bytes = 0; 45 sq->mbuf[pi].num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS); 46 sq->pc += sq->mbuf[pi].num_wqebbs; 47 if (notify_hw) 48 mlx5e_tx_notify_hw(sq, wqe, 0); 49 } 50 51 #if (__FreeBSD_version >= 1100000) 52 static uint32_t mlx5e_hash_value; 53 54 static void 55 mlx5e_hash_init(void *arg) 56 { 57 mlx5e_hash_value = m_ether_tcpip_hash_init(); 58 } 59 60 /* Make kernel call mlx5e_hash_init after the random stack finished initializing */ 61 SYSINIT(mlx5e_hash_init, SI_SUB_RANDOM, SI_ORDER_ANY, &mlx5e_hash_init, NULL); 62 #endif 63 64 static struct mlx5e_sq * 65 mlx5e_select_queue(struct ifnet *ifp, struct mbuf *mb) 66 { 67 struct mlx5e_priv *priv = ifp->if_softc; 68 u32 ch; 69 u32 tc; 70 71 /* check if channels are successfully opened */ 72 if (unlikely(priv->channel == NULL)) 73 return (NULL); 74 75 /* obtain VLAN information if present */ 76 if (mb->m_flags & M_VLANTAG) { 77 tc = (mb->m_pkthdr.ether_vtag >> 13); 78 if (tc >= priv->num_tc) 79 tc = priv->default_vlan_prio; 80 } else { 81 tc = priv->default_vlan_prio; 82 } 83 84 ch = priv->params.num_channels; 85 86 /* check if flowid is set */ 87 if (M_HASHTYPE_GET(mb) != M_HASHTYPE_NONE) { 88 ch = (mb->m_pkthdr.flowid % 128) % ch; 89 } else { 90 #if (__FreeBSD_version >= 1100000) 91 ch = m_ether_tcpip_hash(MBUF_HASHFLAG_L3 | 92 MBUF_HASHFLAG_L4, mb, mlx5e_hash_value) % ch; 93 #else 94 /* 95 * m_ether_tcpip_hash not present in stable, so just 96 * throw unhashed mbufs on queue 0 97 */ 98 ch = 0; 99 #endif 100 } 101 102 /* check if channel is allocated */ 103 if (unlikely(priv->channel[ch] == NULL)) 104 return (NULL); 105 106 return (&priv->channel[ch]->sq[tc]); 107 } 108 109 static inline u16 110 mlx5e_get_inline_hdr_size(struct mlx5e_sq *sq, struct mbuf *mb) 111 { 112 return (MIN(MLX5E_MAX_TX_INLINE, mb->m_len)); 113 } 114 115 static int 116 mlx5e_get_header_size(struct mbuf *mb) 117 { 118 struct ether_vlan_header *eh; 119 struct tcphdr *th; 120 struct ip *ip; 121 int ip_hlen, tcp_hlen; 122 struct ip6_hdr *ip6; 123 uint16_t eth_type; 124 int eth_hdr_len; 125 126 eh = mtod(mb, struct ether_vlan_header *); 127 if (mb->m_len < ETHER_HDR_LEN) 128 return (0); 129 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 130 eth_type = ntohs(eh->evl_proto); 131 eth_hdr_len = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 132 } else { 133 eth_type = ntohs(eh->evl_encap_proto); 134 eth_hdr_len = ETHER_HDR_LEN; 135 } 136 if (mb->m_len < eth_hdr_len) 137 return (0); 138 switch (eth_type) { 139 case ETHERTYPE_IP: 140 ip = (struct ip *)(mb->m_data + eth_hdr_len); 141 if (mb->m_len < eth_hdr_len + sizeof(*ip)) 142 return (0); 143 if (ip->ip_p != IPPROTO_TCP) 144 return (0); 145 ip_hlen = ip->ip_hl << 2; 146 eth_hdr_len += ip_hlen; 147 break; 148 case ETHERTYPE_IPV6: 149 ip6 = (struct ip6_hdr *)(mb->m_data + eth_hdr_len); 150 if (mb->m_len < eth_hdr_len + sizeof(*ip6)) 151 return (0); 152 if (ip6->ip6_nxt != IPPROTO_TCP) 153 return (0); 154 eth_hdr_len += sizeof(*ip6); 155 break; 156 default: 157 return (0); 158 } 159 if (mb->m_len < eth_hdr_len + sizeof(*th)) 160 return (0); 161 th = (struct tcphdr *)(mb->m_data + eth_hdr_len); 162 tcp_hlen = th->th_off << 2; 163 eth_hdr_len += tcp_hlen; 164 if (mb->m_len < eth_hdr_len) 165 return (0); 166 return (eth_hdr_len); 167 } 168 169 /* The return value is not going back to the stack because of 170 * the drbr */ 171 static int 172 mlx5e_sq_xmit(struct mlx5e_sq *sq, struct mbuf **mbp) 173 { 174 bus_dma_segment_t segs[MLX5E_MAX_TX_MBUF_FRAGS]; 175 struct mlx5_wqe_data_seg *dseg; 176 struct mlx5e_tx_wqe *wqe; 177 struct ifnet *ifp; 178 int nsegs; 179 int err; 180 int x; 181 struct mbuf *mb = *mbp; 182 u16 ds_cnt; 183 u16 ihs; 184 u16 pi; 185 u8 opcode; 186 187 /* Return ENOBUFS if the queue is full, this may trigger reinsertion 188 * of the mbuf into the drbr (see mlx5e_xmit_locked) */ 189 if (unlikely(!mlx5e_sq_has_room_for(sq, 2 * MLX5_SEND_WQE_MAX_WQEBBS))) { 190 return (ENOBUFS); 191 } 192 193 /* Align SQ edge with NOPs to avoid WQE wrap around */ 194 pi = ((~sq->pc) & sq->wq.sz_m1); 195 if (pi < (MLX5_SEND_WQE_MAX_WQEBBS - 1)) { 196 /* send one multi NOP message instead of many */ 197 mlx5e_send_nop(sq, (pi + 1) * MLX5_SEND_WQEBB_NUM_DS, false); 198 pi = ((~sq->pc) & sq->wq.sz_m1); 199 if (pi < (MLX5_SEND_WQE_MAX_WQEBBS - 1)) { 200 m_freem(mb); 201 return (ENOMEM); 202 } 203 } 204 205 /* Setup local variables */ 206 pi = sq->pc & sq->wq.sz_m1; 207 wqe = mlx5_wq_cyc_get_wqe(&sq->wq, pi); 208 ifp = sq->channel->ifp; 209 210 memset(wqe, 0, sizeof(*wqe)); 211 212 /* send a copy of the frame to the BPF listener, if any */ 213 if (ifp != NULL && ifp->if_bpf != NULL) 214 ETHER_BPF_MTAP(ifp, mb); 215 216 if (mb->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO)) { 217 wqe->eth.cs_flags |= MLX5_ETH_WQE_L3_CSUM; 218 } 219 if (mb->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) { 220 wqe->eth.cs_flags |= MLX5_ETH_WQE_L4_CSUM; 221 } 222 if ( wqe->eth.cs_flags == 0 ) { 223 sq->stats.csum_offload_none++; 224 } 225 226 if (mb->m_pkthdr.csum_flags & CSUM_TSO) { 227 u32 payload_len; 228 u32 mss = mb->m_pkthdr.tso_segsz; 229 u32 num_pkts; 230 231 wqe->eth.mss = cpu_to_be16(mss); 232 opcode = MLX5_OPCODE_LSO; 233 ihs = mlx5e_get_header_size(mb); 234 payload_len = mb->m_pkthdr.len - ihs; 235 if (payload_len == 0) 236 num_pkts = 1; 237 else 238 num_pkts = DIV_ROUND_UP(payload_len, mss); 239 sq->mbuf[pi].num_bytes = payload_len + (num_pkts * ihs); 240 241 sq->stats.tso_packets++; 242 sq->stats.tso_bytes += payload_len; 243 } else { 244 opcode = MLX5_OPCODE_SEND; 245 ihs = mlx5e_get_inline_hdr_size(sq, mb); 246 sq->mbuf[pi].num_bytes = max_t (unsigned int, 247 mb->m_pkthdr.len, ETHER_MIN_LEN - ETHER_CRC_LEN); 248 } 249 if (mb->m_flags & M_VLANTAG) { 250 struct ether_vlan_header *eh = 251 (struct ether_vlan_header *)wqe->eth.inline_hdr_start; 252 /* range checks */ 253 if (ihs > (MLX5E_MAX_TX_INLINE - ETHER_VLAN_ENCAP_LEN)) 254 ihs = (MLX5E_MAX_TX_INLINE - ETHER_VLAN_ENCAP_LEN); 255 else if (ihs < ETHER_HDR_LEN) { 256 err = EINVAL; 257 goto tx_drop; 258 } 259 m_copydata(mb, 0, ETHER_HDR_LEN, (caddr_t)eh); 260 m_adj(mb, ETHER_HDR_LEN); 261 /* insert 4 bytes VLAN tag into data stream */ 262 eh->evl_proto = eh->evl_encap_proto; 263 eh->evl_encap_proto = htons(ETHERTYPE_VLAN); 264 eh->evl_tag = htons(mb->m_pkthdr.ether_vtag); 265 /* copy rest of header data, if any */ 266 m_copydata(mb, 0, ihs - ETHER_HDR_LEN, (caddr_t)(eh + 1)); 267 m_adj(mb, ihs - ETHER_HDR_LEN); 268 /* extend header by 4 bytes */ 269 ihs += ETHER_VLAN_ENCAP_LEN; 270 } else { 271 m_copydata(mb, 0, ihs, wqe->eth.inline_hdr_start); 272 m_adj(mb, ihs); 273 } 274 275 wqe->eth.inline_hdr_sz = cpu_to_be16(ihs); 276 277 ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS; 278 if (likely(ihs > sizeof(wqe->eth.inline_hdr_start))) { 279 ds_cnt += DIV_ROUND_UP(ihs - sizeof(wqe->eth.inline_hdr_start), 280 MLX5_SEND_WQE_DS); 281 } 282 dseg = ((struct mlx5_wqe_data_seg *)&wqe->ctrl) + ds_cnt; 283 284 /* trim off empty mbufs */ 285 while (mb->m_len == 0) { 286 mb = m_free(mb); 287 /* check if all data has been inlined */ 288 if (mb == NULL) 289 goto skip_dma; 290 } 291 292 err = bus_dmamap_load_mbuf_sg(sq->dma_tag, sq->mbuf[pi].dma_map, 293 mb, segs, &nsegs, BUS_DMA_NOWAIT); 294 if (err == EFBIG) { 295 /* Update *mbp before defrag in case it was trimmed in the loop above */ 296 *mbp = mb; 297 /* Update statistics */ 298 sq->stats.defragged++; 299 /* Too many mbuf fragments */ 300 mb = m_defrag(*mbp, M_NOWAIT); 301 if (mb == NULL) { 302 mb = *mbp; 303 goto tx_drop; 304 } 305 /* Try again */ 306 err = bus_dmamap_load_mbuf_sg(sq->dma_tag, sq->mbuf[pi].dma_map, 307 mb, segs, &nsegs, BUS_DMA_NOWAIT); 308 } 309 /* catch errors */ 310 if (err != 0) { 311 goto tx_drop; 312 } 313 *mbp = mb; 314 315 for (x = 0; x != nsegs; x++) { 316 if (segs[x].ds_len == 0) 317 continue; 318 dseg->addr = cpu_to_be64((uint64_t)segs[x].ds_addr); 319 dseg->lkey = sq->mkey_be; 320 dseg->byte_count = cpu_to_be32((uint32_t)segs[x].ds_len); 321 dseg++; 322 } 323 skip_dma: 324 ds_cnt = (dseg - ((struct mlx5_wqe_data_seg *)&wqe->ctrl)); 325 326 wqe->ctrl.opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | opcode); 327 wqe->ctrl.qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt); 328 wqe->ctrl.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; 329 330 /* store pointer to mbuf */ 331 sq->mbuf[pi].mbuf = mb; 332 sq->mbuf[pi].num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS); 333 sq->pc += sq->mbuf[pi].num_wqebbs; 334 335 /* make sure all mbuf data is written to RAM */ 336 if (mb != NULL) 337 bus_dmamap_sync(sq->dma_tag, sq->mbuf[pi].dma_map, BUS_DMASYNC_PREWRITE); 338 339 mlx5e_tx_notify_hw(sq, wqe, 0); 340 341 sq->stats.packets++; 342 return (0); 343 344 tx_drop: 345 sq->stats.dropped++; 346 *mbp = NULL; 347 m_freem(mb); 348 return err; 349 } 350 351 static void 352 mlx5e_poll_tx_cq(struct mlx5e_sq *sq, int budget) 353 { 354 u16 sqcc; 355 356 /* 357 * sq->cc must be updated only after mlx5_cqwq_update_db_record(), 358 * otherwise a cq overrun may occur 359 */ 360 sqcc = sq->cc; 361 362 while (budget--) { 363 struct mlx5_cqe64 *cqe; 364 struct mbuf *mb; 365 u16 ci; 366 367 cqe = mlx5e_get_cqe(&sq->cq); 368 if (!cqe) 369 break; 370 371 ci = sqcc & sq->wq.sz_m1; 372 mb = sq->mbuf[ci].mbuf; 373 sq->mbuf[ci].mbuf = NULL; /* safety clear */ 374 375 if (mb == NULL) { 376 if (sq->mbuf[ci].num_bytes == 0) { 377 /* NOP */ 378 sq->stats.nop++; 379 } 380 } else { 381 bus_dmamap_sync(sq->dma_tag, sq->mbuf[ci].dma_map, 382 BUS_DMASYNC_POSTWRITE); 383 bus_dmamap_unload(sq->dma_tag, sq->mbuf[ci].dma_map); 384 385 /* free transmitted mbuf */ 386 m_freem(mb); 387 } 388 sqcc += sq->mbuf[ci].num_wqebbs; 389 } 390 391 mlx5_cqwq_update_db_record(&sq->cq.wq); 392 393 /* ensure cq space is freed before enabling more cqes */ 394 wmb(); 395 396 sq->cc = sqcc; 397 398 if (atomic_cmpset_int(&sq->queue_state, MLX5E_SQ_FULL, MLX5E_SQ_READY)) 399 taskqueue_enqueue(sq->sq_tq, &sq->sq_task); 400 } 401 402 static int 403 mlx5e_xmit_locked(struct ifnet *ifp, struct mlx5e_sq *sq, struct mbuf *mb) 404 { 405 struct mbuf *next; 406 int err = 0; 407 408 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 409 if (mb) 410 err = drbr_enqueue(ifp, sq->br, mb); 411 return (err); 412 } 413 414 if (mb != NULL) 415 /* If we can't insert mbuf into drbr, try to xmit anyway. 416 * We keep the error we got so we could return that after xmit. 417 */ 418 err = drbr_enqueue(ifp, sq->br, mb); 419 420 /* Process the queue */ 421 while ((next = drbr_peek(ifp, sq->br)) != NULL) { 422 if (mlx5e_sq_xmit(sq, &next) != 0) { 423 if (next == NULL) { 424 drbr_advance(ifp, sq->br); 425 } else { 426 drbr_putback(ifp, sq->br, next); 427 atomic_store_rel_int(&sq->queue_state, MLX5E_SQ_FULL); 428 } 429 break; 430 } 431 drbr_advance(ifp, sq->br); 432 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 433 break; 434 } 435 return (err); 436 } 437 438 int 439 mlx5e_xmit(struct ifnet *ifp, struct mbuf *mb) 440 { 441 struct mlx5e_sq *sq; 442 int ret; 443 444 sq = mlx5e_select_queue(ifp, mb); 445 if (unlikely(sq == NULL)) { 446 /* invalid send queue */ 447 m_freem(mb); 448 return (ENXIO); 449 } 450 451 if (mtx_trylock(&sq->lock)) { 452 ret = mlx5e_xmit_locked(ifp, sq, mb); 453 mtx_unlock(&sq->lock); 454 } else { 455 ret = drbr_enqueue(ifp, sq->br, mb); 456 taskqueue_enqueue(sq->sq_tq, &sq->sq_task); 457 } 458 459 return (ret); 460 } 461 462 void 463 mlx5e_tx_cq_comp(struct mlx5_core_cq *mcq) 464 { 465 struct mlx5e_sq *sq = container_of(mcq, struct mlx5e_sq, cq.mcq); 466 467 mtx_lock(&sq->comp_lock); 468 mlx5e_poll_tx_cq(sq, MLX5E_BUDGET_MAX); 469 mlx5e_cq_arm(&sq->cq); 470 mtx_unlock(&sq->comp_lock); 471 } 472 473 void 474 mlx5e_tx_que(void *context, int pending) 475 { 476 struct mlx5e_sq *sq = context; 477 struct ifnet *ifp = sq->channel->ifp; 478 479 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 480 mtx_lock(&sq->lock); 481 if (!drbr_empty(ifp, sq->br)) 482 mlx5e_xmit_locked(ifp, sq, NULL); 483 mtx_unlock(&sq->lock); 484 } 485 } 486