1 /*- 2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include "en.h" 29 #include <machine/in_cksum.h> 30 31 static inline int 32 mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, 33 struct mlx5e_rx_wqe *wqe, u16 ix) 34 { 35 bus_dma_segment_t segs[1]; 36 struct mbuf *mb; 37 int nsegs; 38 int err; 39 40 if (rq->mbuf[ix].mbuf != NULL) 41 return (0); 42 43 mb = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, rq->wqe_sz); 44 if (unlikely(!mb)) 45 return (-ENOMEM); 46 47 /* set initial mbuf length */ 48 mb->m_pkthdr.len = mb->m_len = rq->wqe_sz; 49 50 /* get IP header aligned */ 51 m_adj(mb, MLX5E_NET_IP_ALIGN); 52 53 err = -bus_dmamap_load_mbuf_sg(rq->dma_tag, rq->mbuf[ix].dma_map, 54 mb, segs, &nsegs, BUS_DMA_NOWAIT); 55 if (err != 0) 56 goto err_free_mbuf; 57 if (unlikely(nsegs != 1)) { 58 bus_dmamap_unload(rq->dma_tag, rq->mbuf[ix].dma_map); 59 err = -ENOMEM; 60 goto err_free_mbuf; 61 } 62 wqe->data.addr = cpu_to_be64(segs[0].ds_addr); 63 64 rq->mbuf[ix].mbuf = mb; 65 rq->mbuf[ix].data = mb->m_data; 66 67 bus_dmamap_sync(rq->dma_tag, rq->mbuf[ix].dma_map, 68 BUS_DMASYNC_PREREAD); 69 return (0); 70 71 err_free_mbuf: 72 m_freem(mb); 73 return (err); 74 } 75 76 static void 77 mlx5e_post_rx_wqes(struct mlx5e_rq *rq) 78 { 79 if (unlikely(rq->enabled == 0)) 80 return; 81 82 while (!mlx5_wq_ll_is_full(&rq->wq)) { 83 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, rq->wq.head); 84 85 if (unlikely(mlx5e_alloc_rx_wqe(rq, wqe, rq->wq.head))) 86 break; 87 88 mlx5_wq_ll_push(&rq->wq, be16_to_cpu(wqe->next.next_wqe_index)); 89 } 90 91 /* ensure wqes are visible to device before updating doorbell record */ 92 wmb(); 93 94 mlx5_wq_ll_update_db_record(&rq->wq); 95 } 96 97 static void 98 mlx5e_lro_update_hdr(struct mbuf *mb, struct mlx5_cqe64 *cqe) 99 { 100 /* TODO: consider vlans, ip options, ... */ 101 struct ether_header *eh; 102 uint16_t eh_type; 103 uint16_t tot_len; 104 struct ip6_hdr *ip6 = NULL; 105 struct ip *ip4 = NULL; 106 struct tcphdr *th; 107 uint32_t *ts_ptr; 108 uint8_t l4_hdr_type; 109 int tcp_ack; 110 111 eh = mtod(mb, struct ether_header *); 112 eh_type = ntohs(eh->ether_type); 113 114 l4_hdr_type = get_cqe_l4_hdr_type(cqe); 115 tcp_ack = ((CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA == l4_hdr_type) || 116 (CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA == l4_hdr_type)); 117 118 /* TODO: consider vlan */ 119 tot_len = be32_to_cpu(cqe->byte_cnt) - ETHER_HDR_LEN; 120 121 switch (eh_type) { 122 case ETHERTYPE_IP: 123 ip4 = (struct ip *)(eh + 1); 124 th = (struct tcphdr *)(ip4 + 1); 125 break; 126 case ETHERTYPE_IPV6: 127 ip6 = (struct ip6_hdr *)(eh + 1); 128 th = (struct tcphdr *)(ip6 + 1); 129 break; 130 default: 131 return; 132 } 133 134 ts_ptr = (uint32_t *)(th + 1); 135 136 if (get_cqe_lro_tcppsh(cqe)) 137 th->th_flags |= TH_PUSH; 138 139 if (tcp_ack) { 140 th->th_flags |= TH_ACK; 141 th->th_ack = cqe->lro_ack_seq_num; 142 th->th_win = cqe->lro_tcp_win; 143 144 /* 145 * FreeBSD handles only 32bit aligned timestamp right after 146 * the TCP hdr 147 * +--------+--------+--------+--------+ 148 * | NOP | NOP | TSopt | 10 | 149 * +--------+--------+--------+--------+ 150 * | TSval timestamp | 151 * +--------+--------+--------+--------+ 152 * | TSecr timestamp | 153 * +--------+--------+--------+--------+ 154 */ 155 if (get_cqe_lro_timestamp_valid(cqe) && 156 (__predict_true(*ts_ptr) == ntohl(TCPOPT_NOP << 24 | 157 TCPOPT_NOP << 16 | TCPOPT_TIMESTAMP << 8 | 158 TCPOLEN_TIMESTAMP))) { 159 /* 160 * cqe->timestamp is 64bit long. 161 * [0-31] - timestamp. 162 * [32-64] - timestamp echo replay. 163 */ 164 ts_ptr[1] = *(uint32_t *)&cqe->timestamp; 165 ts_ptr[2] = *((uint32_t *)&cqe->timestamp + 1); 166 } 167 } 168 if (ip4) { 169 ip4->ip_ttl = cqe->lro_min_ttl; 170 ip4->ip_len = cpu_to_be16(tot_len); 171 ip4->ip_sum = 0; 172 ip4->ip_sum = in_cksum(mb, ip4->ip_hl << 2); 173 } else { 174 ip6->ip6_hlim = cqe->lro_min_ttl; 175 ip6->ip6_plen = cpu_to_be16(tot_len - 176 sizeof(struct ip6_hdr)); 177 } 178 /* TODO: handle tcp checksum */ 179 } 180 181 static inline void 182 mlx5e_build_rx_mbuf(struct mlx5_cqe64 *cqe, 183 struct mlx5e_rq *rq, struct mbuf *mb, 184 u32 cqe_bcnt) 185 { 186 struct ifnet *ifp = rq->ifp; 187 int lro_num_seg; /* HW LRO session aggregated packets counter */ 188 189 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24; 190 if (lro_num_seg > 1) { 191 mlx5e_lro_update_hdr(mb, cqe); 192 rq->stats.lro_packets++; 193 rq->stats.lro_bytes += cqe_bcnt; 194 } 195 196 mb->m_pkthdr.len = mb->m_len = cqe_bcnt; 197 /* check if a Toeplitz hash was computed */ 198 if (cqe->rss_hash_type != 0) { 199 mb->m_pkthdr.flowid = be32_to_cpu(cqe->rss_hash_result); 200 #ifdef RSS 201 /* decode the RSS hash type */ 202 switch (cqe->rss_hash_type & 203 (CQE_RSS_DST_HTYPE_L4 | CQE_RSS_DST_HTYPE_IP)) { 204 /* IPv4 */ 205 case (CQE_RSS_DST_HTYPE_TCP | CQE_RSS_DST_HTYPE_IPV4): 206 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_TCP_IPV4); 207 break; 208 case (CQE_RSS_DST_HTYPE_UDP | CQE_RSS_DST_HTYPE_IPV4): 209 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_UDP_IPV4); 210 break; 211 case CQE_RSS_DST_HTYPE_IPV4: 212 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_IPV4); 213 break; 214 /* IPv6 */ 215 case (CQE_RSS_DST_HTYPE_TCP | CQE_RSS_DST_HTYPE_IPV6): 216 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_TCP_IPV6); 217 break; 218 case (CQE_RSS_DST_HTYPE_UDP | CQE_RSS_DST_HTYPE_IPV6): 219 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_UDP_IPV6); 220 break; 221 case CQE_RSS_DST_HTYPE_IPV6: 222 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_IPV6); 223 break; 224 default: /* Other */ 225 M_HASHTYPE_SET(mb, M_HASHTYPE_OPAQUE); 226 break; 227 } 228 #else 229 M_HASHTYPE_SET(mb, M_HASHTYPE_OPAQUE); 230 #endif 231 } else { 232 mb->m_pkthdr.flowid = rq->ix; 233 M_HASHTYPE_SET(mb, M_HASHTYPE_OPAQUE); 234 } 235 mb->m_pkthdr.rcvif = ifp; 236 237 if (likely(ifp->if_capenable & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) && 238 ((cqe->hds_ip_ext & (CQE_L2_OK | CQE_L3_OK | CQE_L4_OK)) == 239 (CQE_L2_OK | CQE_L3_OK | CQE_L4_OK))) { 240 mb->m_pkthdr.csum_flags = 241 CSUM_IP_CHECKED | CSUM_IP_VALID | 242 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 243 mb->m_pkthdr.csum_data = htons(0xffff); 244 } else { 245 rq->stats.csum_none++; 246 } 247 248 if (cqe_has_vlan(cqe)) { 249 mb->m_pkthdr.ether_vtag = be16_to_cpu(cqe->vlan_info); 250 mb->m_flags |= M_VLANTAG; 251 } 252 } 253 254 static inline void 255 mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cc, void *data) 256 { 257 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, (cc & cq->wq.sz_m1)), 258 sizeof(struct mlx5_cqe64)); 259 } 260 261 static inline void 262 mlx5e_write_cqe_slot(struct mlx5e_cq *cq, u32 cc, void *data) 263 { 264 memcpy(mlx5_cqwq_get_wqe(&cq->wq, cc & cq->wq.sz_m1), 265 data, sizeof(struct mlx5_cqe64)); 266 } 267 268 static inline void 269 mlx5e_decompress_cqe(struct mlx5e_cq *cq, struct mlx5_cqe64 *title, 270 struct mlx5_mini_cqe8 *mini, 271 u16 wqe_counter, int i) 272 { 273 /* 274 * NOTE: The fields which are not set here are copied from the 275 * initial and common title. See memcpy() in 276 * mlx5e_write_cqe_slot(). 277 */ 278 title->byte_cnt = mini->byte_cnt; 279 title->wqe_counter = cpu_to_be16((wqe_counter + i) & cq->wq.sz_m1); 280 title->check_sum = mini->checksum; 281 title->op_own = (title->op_own & 0xf0) | 282 (((cq->wq.cc + i) >> cq->wq.log_sz) & 1); 283 } 284 285 #define MLX5E_MINI_ARRAY_SZ 8 286 /* Make sure structs are not packet differently */ 287 CTASSERT(sizeof(struct mlx5_cqe64) == 288 sizeof(struct mlx5_mini_cqe8) * MLX5E_MINI_ARRAY_SZ); 289 static void 290 mlx5e_decompress_cqes(struct mlx5e_cq *cq) 291 { 292 struct mlx5_mini_cqe8 mini_array[MLX5E_MINI_ARRAY_SZ]; 293 struct mlx5_cqe64 title; 294 u32 cqe_count; 295 u32 i = 0; 296 u16 title_wqe_counter; 297 298 mlx5e_read_cqe_slot(cq, cq->wq.cc, &title); 299 title_wqe_counter = be16_to_cpu(title.wqe_counter); 300 cqe_count = be32_to_cpu(title.byte_cnt); 301 302 /* Make sure we won't overflow */ 303 KASSERT(cqe_count <= cq->wq.sz_m1, 304 ("%s: cqe_count %u > cq->wq.sz_m1 %u", __func__, 305 cqe_count, cq->wq.sz_m1)); 306 307 mlx5e_read_cqe_slot(cq, cq->wq.cc + 1, mini_array); 308 while (true) { 309 mlx5e_decompress_cqe(cq, &title, 310 &mini_array[i % MLX5E_MINI_ARRAY_SZ], 311 title_wqe_counter, i); 312 mlx5e_write_cqe_slot(cq, cq->wq.cc + i, &title); 313 i++; 314 315 if (i == cqe_count) 316 break; 317 if (i % MLX5E_MINI_ARRAY_SZ == 0) 318 mlx5e_read_cqe_slot(cq, cq->wq.cc + i, mini_array); 319 } 320 } 321 322 static int 323 mlx5e_poll_rx_cq(struct mlx5e_rq *rq, int budget) 324 { 325 #ifndef HAVE_TURBO_LRO 326 struct lro_entry *queued; 327 #endif 328 int i; 329 330 for (i = 0; i < budget; i++) { 331 struct mlx5e_rx_wqe *wqe; 332 struct mlx5_cqe64 *cqe; 333 struct mbuf *mb; 334 __be16 wqe_counter_be; 335 u16 wqe_counter; 336 u32 byte_cnt; 337 338 cqe = mlx5e_get_cqe(&rq->cq); 339 if (!cqe) 340 break; 341 342 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) 343 mlx5e_decompress_cqes(&rq->cq); 344 345 mlx5_cqwq_pop(&rq->cq.wq); 346 347 wqe_counter_be = cqe->wqe_counter; 348 wqe_counter = be16_to_cpu(wqe_counter_be); 349 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 350 byte_cnt = be32_to_cpu(cqe->byte_cnt); 351 352 bus_dmamap_sync(rq->dma_tag, 353 rq->mbuf[wqe_counter].dma_map, 354 BUS_DMASYNC_POSTREAD); 355 356 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 357 rq->stats.wqe_err++; 358 goto wq_ll_pop; 359 } 360 361 if (MHLEN >= byte_cnt && 362 (mb = m_gethdr(M_NOWAIT, MT_DATA)) != NULL) { 363 bcopy(rq->mbuf[wqe_counter].data, mtod(mb, caddr_t), 364 byte_cnt); 365 } else { 366 mb = rq->mbuf[wqe_counter].mbuf; 367 rq->mbuf[wqe_counter].mbuf = NULL; /* safety clear */ 368 369 bus_dmamap_unload(rq->dma_tag, 370 rq->mbuf[wqe_counter].dma_map); 371 } 372 373 mlx5e_build_rx_mbuf(cqe, rq, mb, byte_cnt); 374 rq->stats.packets++; 375 #ifdef HAVE_TURBO_LRO 376 if (mb->m_pkthdr.csum_flags == 0 || 377 (rq->ifp->if_capenable & IFCAP_LRO) == 0 || 378 rq->lro.mbuf == NULL) { 379 /* normal input */ 380 rq->ifp->if_input(rq->ifp, mb); 381 } else { 382 tcp_tlro_rx(&rq->lro, mb); 383 } 384 #else 385 if (mb->m_pkthdr.csum_flags == 0 || 386 (rq->ifp->if_capenable & IFCAP_LRO) == 0 || 387 rq->lro.lro_cnt == 0 || 388 tcp_lro_rx(&rq->lro, mb, 0) != 0) { 389 rq->ifp->if_input(rq->ifp, mb); 390 } 391 #endif 392 wq_ll_pop: 393 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 394 &wqe->next.next_wqe_index); 395 } 396 397 mlx5_cqwq_update_db_record(&rq->cq.wq); 398 399 /* ensure cq space is freed before enabling more cqes */ 400 wmb(); 401 #ifndef HAVE_TURBO_LRO 402 while ((queued = SLIST_FIRST(&rq->lro.lro_active)) != NULL) { 403 SLIST_REMOVE_HEAD(&rq->lro.lro_active, next); 404 tcp_lro_flush(&rq->lro, queued); 405 } 406 #endif 407 return (i); 408 } 409 410 void 411 mlx5e_rx_cq_comp(struct mlx5_core_cq *mcq) 412 { 413 struct mlx5e_rq *rq = container_of(mcq, struct mlx5e_rq, cq.mcq); 414 int i = 0; 415 416 #ifdef HAVE_PER_CQ_EVENT_PACKET 417 struct mbuf *mb = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, rq->wqe_sz); 418 419 if (mb != NULL) { 420 /* this code is used for debugging purpose only */ 421 mb->m_pkthdr.len = mb->m_len = 15; 422 memset(mb->m_data, 255, 14); 423 mb->m_data[14] = rq->ix; 424 mb->m_pkthdr.rcvif = rq->ifp; 425 rq->ifp->if_input(rq->ifp, mb); 426 } 427 #endif 428 429 mtx_lock(&rq->mtx); 430 431 /* 432 * Polling the entire CQ without posting new WQEs results in 433 * lack of receive WQEs during heavy traffic scenarios. 434 */ 435 while (1) { 436 if (mlx5e_poll_rx_cq(rq, MLX5E_RX_BUDGET_MAX) != 437 MLX5E_RX_BUDGET_MAX) 438 break; 439 i += MLX5E_RX_BUDGET_MAX; 440 if (i >= MLX5E_BUDGET_MAX) 441 break; 442 mlx5e_post_rx_wqes(rq); 443 } 444 mlx5e_post_rx_wqes(rq); 445 mlx5e_cq_arm(&rq->cq); 446 #ifdef HAVE_TURBO_LRO 447 tcp_tlro_flush(&rq->lro, 1); 448 #endif 449 mtx_unlock(&rq->mtx); 450 } 451