1 /*- 2 * Copyright (c) 2015-2021 Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include "opt_rss.h" 29 #include "opt_ratelimit.h" 30 31 #include <dev/mlx5/mlx5_en/en.h> 32 #include <machine/in_cksum.h> 33 34 static inline int 35 mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, 36 struct mlx5e_rx_wqe *wqe, u16 ix) 37 { 38 bus_dma_segment_t segs[MLX5E_MAX_BUSDMA_RX_SEGS]; 39 struct mbuf *mb; 40 int nsegs; 41 int err; 42 struct mbuf *mb_head; 43 int i; 44 45 if (rq->mbuf[ix].mbuf != NULL) 46 return (0); 47 48 mb_head = mb = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, 49 MLX5E_MAX_RX_BYTES); 50 if (unlikely(mb == NULL)) 51 return (-ENOMEM); 52 53 mb->m_len = MLX5E_MAX_RX_BYTES; 54 mb->m_pkthdr.len = MLX5E_MAX_RX_BYTES; 55 56 for (i = 1; i < rq->nsegs; i++) { 57 if (mb_head->m_pkthdr.len >= rq->wqe_sz) 58 break; 59 mb = mb->m_next = m_getjcl(M_NOWAIT, MT_DATA, 0, 60 MLX5E_MAX_RX_BYTES); 61 if (unlikely(mb == NULL)) { 62 m_freem(mb_head); 63 return (-ENOMEM); 64 } 65 mb->m_len = MLX5E_MAX_RX_BYTES; 66 mb_head->m_pkthdr.len += MLX5E_MAX_RX_BYTES; 67 } 68 /* rewind to first mbuf in chain */ 69 mb = mb_head; 70 71 /* get IP header aligned */ 72 m_adj(mb, MLX5E_NET_IP_ALIGN); 73 74 err = -bus_dmamap_load_mbuf_sg(rq->dma_tag, rq->mbuf[ix].dma_map, 75 mb, segs, &nsegs, BUS_DMA_NOWAIT); 76 if (err != 0) 77 goto err_free_mbuf; 78 if (unlikely(nsegs == 0)) { 79 bus_dmamap_unload(rq->dma_tag, rq->mbuf[ix].dma_map); 80 err = -ENOMEM; 81 goto err_free_mbuf; 82 } 83 wqe->data[0].addr = cpu_to_be64(segs[0].ds_addr); 84 wqe->data[0].byte_count = cpu_to_be32(segs[0].ds_len | 85 MLX5_HW_START_PADDING); 86 for (i = 1; i != nsegs; i++) { 87 wqe->data[i].addr = cpu_to_be64(segs[i].ds_addr); 88 wqe->data[i].byte_count = cpu_to_be32(segs[i].ds_len); 89 } 90 for (; i < rq->nsegs; i++) { 91 wqe->data[i].addr = 0; 92 wqe->data[i].byte_count = 0; 93 } 94 95 rq->mbuf[ix].mbuf = mb; 96 rq->mbuf[ix].data = mb->m_data; 97 98 bus_dmamap_sync(rq->dma_tag, rq->mbuf[ix].dma_map, 99 BUS_DMASYNC_PREREAD); 100 return (0); 101 102 err_free_mbuf: 103 m_freem(mb); 104 return (err); 105 } 106 107 static void 108 mlx5e_post_rx_wqes(struct mlx5e_rq *rq) 109 { 110 if (unlikely(rq->enabled == 0)) 111 return; 112 113 while (!mlx5_wq_ll_is_full(&rq->wq)) { 114 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, rq->wq.head); 115 116 if (unlikely(mlx5e_alloc_rx_wqe(rq, wqe, rq->wq.head))) { 117 callout_reset_curcpu(&rq->watchdog, 1, (void *)&mlx5e_post_rx_wqes, rq); 118 break; 119 } 120 mlx5_wq_ll_push(&rq->wq, be16_to_cpu(wqe->next.next_wqe_index)); 121 } 122 123 /* ensure wqes are visible to device before updating doorbell record */ 124 atomic_thread_fence_rel(); 125 126 mlx5_wq_ll_update_db_record(&rq->wq); 127 } 128 129 static void 130 mlx5e_lro_update_hdr(struct mbuf *mb, struct mlx5_cqe64 *cqe) 131 { 132 /* TODO: consider vlans, ip options, ... */ 133 struct ether_header *eh; 134 uint16_t eh_type; 135 uint16_t tot_len; 136 struct ip6_hdr *ip6 = NULL; 137 struct ip *ip4 = NULL; 138 struct tcphdr *th; 139 uint32_t *ts_ptr; 140 uint8_t l4_hdr_type; 141 int tcp_ack; 142 143 eh = mtod(mb, struct ether_header *); 144 eh_type = ntohs(eh->ether_type); 145 146 l4_hdr_type = get_cqe_l4_hdr_type(cqe); 147 tcp_ack = ((CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA == l4_hdr_type) || 148 (CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA == l4_hdr_type)); 149 150 /* TODO: consider vlan */ 151 tot_len = be32_to_cpu(cqe->byte_cnt) - ETHER_HDR_LEN; 152 153 switch (eh_type) { 154 case ETHERTYPE_IP: 155 ip4 = (struct ip *)(eh + 1); 156 th = (struct tcphdr *)(ip4 + 1); 157 break; 158 case ETHERTYPE_IPV6: 159 ip6 = (struct ip6_hdr *)(eh + 1); 160 th = (struct tcphdr *)(ip6 + 1); 161 break; 162 default: 163 return; 164 } 165 166 ts_ptr = (uint32_t *)(th + 1); 167 168 if (get_cqe_lro_tcppsh(cqe)) 169 th->th_flags |= TH_PUSH; 170 171 if (tcp_ack) { 172 th->th_flags |= TH_ACK; 173 th->th_ack = cqe->lro_ack_seq_num; 174 th->th_win = cqe->lro_tcp_win; 175 176 /* 177 * FreeBSD handles only 32bit aligned timestamp right after 178 * the TCP hdr 179 * +--------+--------+--------+--------+ 180 * | NOP | NOP | TSopt | 10 | 181 * +--------+--------+--------+--------+ 182 * | TSval timestamp | 183 * +--------+--------+--------+--------+ 184 * | TSecr timestamp | 185 * +--------+--------+--------+--------+ 186 */ 187 if (get_cqe_lro_timestamp_valid(cqe) && 188 (__predict_true(*ts_ptr) == ntohl(TCPOPT_NOP << 24 | 189 TCPOPT_NOP << 16 | TCPOPT_TIMESTAMP << 8 | 190 TCPOLEN_TIMESTAMP))) { 191 /* 192 * cqe->timestamp is 64bit long. 193 * [0-31] - timestamp. 194 * [32-64] - timestamp echo replay. 195 */ 196 ts_ptr[1] = *(uint32_t *)&cqe->timestamp; 197 ts_ptr[2] = *((uint32_t *)&cqe->timestamp + 1); 198 } 199 } 200 if (ip4) { 201 ip4->ip_ttl = cqe->lro_min_ttl; 202 ip4->ip_len = cpu_to_be16(tot_len); 203 ip4->ip_sum = 0; 204 ip4->ip_sum = in_cksum(mb, ip4->ip_hl << 2); 205 } else { 206 ip6->ip6_hlim = cqe->lro_min_ttl; 207 ip6->ip6_plen = cpu_to_be16(tot_len - 208 sizeof(struct ip6_hdr)); 209 } 210 /* TODO: handle tcp checksum */ 211 } 212 213 static uint64_t 214 mlx5e_mbuf_tstmp(struct mlx5e_priv *priv, uint64_t hw_tstmp) 215 { 216 struct mlx5e_clbr_point *cp, dcp; 217 uint64_t a1, a2, res; 218 u_int gen; 219 220 do { 221 cp = &priv->clbr_points[priv->clbr_curr]; 222 gen = atomic_load_acq_int(&cp->clbr_gen); 223 if (gen == 0) 224 return (0); 225 dcp = *cp; 226 atomic_thread_fence_acq(); 227 } while (gen != cp->clbr_gen); 228 229 a1 = (hw_tstmp - dcp.clbr_hw_prev) >> MLX5E_TSTMP_PREC; 230 a2 = (dcp.base_curr - dcp.base_prev) >> MLX5E_TSTMP_PREC; 231 res = (a1 * a2) << MLX5E_TSTMP_PREC; 232 233 /* 234 * Divisor cannot be zero because calibration callback 235 * checks for the condition and disables timestamping 236 * if clock halted. 237 */ 238 res /= (dcp.clbr_hw_curr - dcp.clbr_hw_prev) >> MLX5E_TSTMP_PREC; 239 240 res += dcp.base_prev; 241 return (res); 242 } 243 244 static inline void 245 mlx5e_build_rx_mbuf(struct mlx5_cqe64 *cqe, 246 struct mlx5e_rq *rq, struct mbuf *mb, 247 u32 cqe_bcnt) 248 { 249 struct ifnet *ifp = rq->ifp; 250 struct mlx5e_channel *c; 251 struct mbuf *mb_head; 252 int lro_num_seg; /* HW LRO session aggregated packets counter */ 253 uint64_t tstmp; 254 255 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24; 256 if (lro_num_seg > 1) { 257 mlx5e_lro_update_hdr(mb, cqe); 258 rq->stats.lro_packets++; 259 rq->stats.lro_bytes += cqe_bcnt; 260 } 261 262 mb->m_pkthdr.len = cqe_bcnt; 263 for (mb_head = mb; mb != NULL; mb = mb->m_next) { 264 if (mb->m_len > cqe_bcnt) 265 mb->m_len = cqe_bcnt; 266 cqe_bcnt -= mb->m_len; 267 if (likely(cqe_bcnt == 0)) { 268 if (likely(mb->m_next != NULL)) { 269 /* trim off empty mbufs */ 270 m_freem(mb->m_next); 271 mb->m_next = NULL; 272 } 273 break; 274 } 275 } 276 /* rewind to first mbuf in chain */ 277 mb = mb_head; 278 279 /* check if a Toeplitz hash was computed */ 280 if (cqe->rss_hash_type != 0) { 281 mb->m_pkthdr.flowid = be32_to_cpu(cqe->rss_hash_result); 282 #ifdef RSS 283 /* decode the RSS hash type */ 284 switch (cqe->rss_hash_type & 285 (CQE_RSS_DST_HTYPE_L4 | CQE_RSS_DST_HTYPE_IP)) { 286 /* IPv4 */ 287 case (CQE_RSS_DST_HTYPE_TCP | CQE_RSS_DST_HTYPE_IPV4): 288 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_TCP_IPV4); 289 break; 290 case (CQE_RSS_DST_HTYPE_UDP | CQE_RSS_DST_HTYPE_IPV4): 291 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_UDP_IPV4); 292 break; 293 case CQE_RSS_DST_HTYPE_IPV4: 294 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_IPV4); 295 break; 296 /* IPv6 */ 297 case (CQE_RSS_DST_HTYPE_TCP | CQE_RSS_DST_HTYPE_IPV6): 298 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_TCP_IPV6); 299 break; 300 case (CQE_RSS_DST_HTYPE_UDP | CQE_RSS_DST_HTYPE_IPV6): 301 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_UDP_IPV6); 302 break; 303 case CQE_RSS_DST_HTYPE_IPV6: 304 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_IPV6); 305 break; 306 default: /* Other */ 307 M_HASHTYPE_SET(mb, M_HASHTYPE_OPAQUE_HASH); 308 break; 309 } 310 #else 311 M_HASHTYPE_SET(mb, M_HASHTYPE_OPAQUE_HASH); 312 #endif 313 #ifdef M_HASHTYPE_SETINNER 314 if (cqe_is_tunneled(cqe)) 315 M_HASHTYPE_SETINNER(mb); 316 #endif 317 } else { 318 mb->m_pkthdr.flowid = rq->ix; 319 M_HASHTYPE_SET(mb, M_HASHTYPE_OPAQUE); 320 } 321 mb->m_pkthdr.rcvif = ifp; 322 323 if (cqe_is_tunneled(cqe)) { 324 /* 325 * CQE can be tunneled only if TIR is configured to 326 * enable parsing of tunneled payload, so no need to 327 * check for capabilities. 328 */ 329 if (((cqe->hds_ip_ext & (CQE_L2_OK | CQE_L3_OK)) == 330 (CQE_L2_OK | CQE_L3_OK))) { 331 mb->m_pkthdr.csum_flags |= 332 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID | 333 CSUM_IP_CHECKED | CSUM_IP_VALID | 334 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 335 mb->m_pkthdr.csum_data = htons(0xffff); 336 337 if (likely((cqe->hds_ip_ext & CQE_L4_OK) == CQE_L4_OK)) { 338 mb->m_pkthdr.csum_flags |= 339 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID; 340 } 341 } else { 342 rq->stats.csum_none++; 343 } 344 } else if (likely((ifp->if_capenable & (IFCAP_RXCSUM | 345 IFCAP_RXCSUM_IPV6)) != 0) && 346 ((cqe->hds_ip_ext & (CQE_L2_OK | CQE_L3_OK | CQE_L4_OK)) == 347 (CQE_L2_OK | CQE_L3_OK | CQE_L4_OK))) { 348 mb->m_pkthdr.csum_flags = 349 CSUM_IP_CHECKED | CSUM_IP_VALID | 350 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 351 mb->m_pkthdr.csum_data = htons(0xffff); 352 } else { 353 rq->stats.csum_none++; 354 } 355 356 if (cqe_has_vlan(cqe)) { 357 mb->m_pkthdr.ether_vtag = be16_to_cpu(cqe->vlan_info); 358 mb->m_flags |= M_VLANTAG; 359 } 360 361 c = container_of(rq, struct mlx5e_channel, rq); 362 if (c->priv->clbr_done >= 2) { 363 tstmp = mlx5e_mbuf_tstmp(c->priv, be64_to_cpu(cqe->timestamp)); 364 if ((tstmp & MLX5_CQE_TSTMP_PTP) != 0) { 365 /* 366 * Timestamp was taken on the packet entrance, 367 * instead of the cqe generation. 368 */ 369 tstmp &= ~MLX5_CQE_TSTMP_PTP; 370 mb->m_flags |= M_TSTMP_HPREC; 371 } 372 mb->m_pkthdr.rcv_tstmp = tstmp; 373 mb->m_flags |= M_TSTMP; 374 } 375 376 switch (get_cqe_tls_offload(cqe)) { 377 case CQE_TLS_OFFLOAD_DECRYPTED: 378 /* set proper checksum flag for decrypted packets */ 379 mb->m_pkthdr.csum_flags |= CSUM_TLS_DECRYPTED; 380 rq->stats.decrypted_ok_packets++; 381 break; 382 case CQE_TLS_OFFLOAD_ERROR: 383 rq->stats.decrypted_error_packets++; 384 break; 385 default: 386 break; 387 } 388 } 389 390 static inline void 391 mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cc, void *data) 392 { 393 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, (cc & cq->wq.sz_m1)), 394 sizeof(struct mlx5_cqe64)); 395 } 396 397 static inline void 398 mlx5e_write_cqe_slot(struct mlx5e_cq *cq, u32 cc, void *data) 399 { 400 memcpy(mlx5_cqwq_get_wqe(&cq->wq, cc & cq->wq.sz_m1), 401 data, sizeof(struct mlx5_cqe64)); 402 } 403 404 static inline void 405 mlx5e_decompress_cqe(struct mlx5e_cq *cq, struct mlx5_cqe64 *title, 406 struct mlx5_mini_cqe8 *mini, 407 u16 wqe_counter, int i) 408 { 409 /* 410 * NOTE: The fields which are not set here are copied from the 411 * initial and common title. See memcpy() in 412 * mlx5e_write_cqe_slot(). 413 */ 414 title->byte_cnt = mini->byte_cnt; 415 title->wqe_counter = cpu_to_be16((wqe_counter + i) & cq->wq.sz_m1); 416 title->rss_hash_result = mini->rx_hash_result; 417 /* 418 * Since we use MLX5_CQE_FORMAT_HASH when creating the RX CQ, 419 * the value of the checksum should be ignored. 420 */ 421 title->check_sum = 0; 422 title->op_own = (title->op_own & 0xf0) | 423 (((cq->wq.cc + i) >> cq->wq.log_sz) & 1); 424 } 425 426 #define MLX5E_MINI_ARRAY_SZ 8 427 /* Make sure structs are not packet differently */ 428 CTASSERT(sizeof(struct mlx5_cqe64) == 429 sizeof(struct mlx5_mini_cqe8) * MLX5E_MINI_ARRAY_SZ); 430 static void 431 mlx5e_decompress_cqes(struct mlx5e_cq *cq) 432 { 433 struct mlx5_mini_cqe8 mini_array[MLX5E_MINI_ARRAY_SZ]; 434 struct mlx5_cqe64 title; 435 u32 cqe_count; 436 u32 i = 0; 437 u16 title_wqe_counter; 438 439 mlx5e_read_cqe_slot(cq, cq->wq.cc, &title); 440 title_wqe_counter = be16_to_cpu(title.wqe_counter); 441 cqe_count = be32_to_cpu(title.byte_cnt); 442 443 /* Make sure we won't overflow */ 444 KASSERT(cqe_count <= cq->wq.sz_m1, 445 ("%s: cqe_count %u > cq->wq.sz_m1 %u", __func__, 446 cqe_count, cq->wq.sz_m1)); 447 448 mlx5e_read_cqe_slot(cq, cq->wq.cc + 1, mini_array); 449 while (true) { 450 mlx5e_decompress_cqe(cq, &title, 451 &mini_array[i % MLX5E_MINI_ARRAY_SZ], 452 title_wqe_counter, i); 453 mlx5e_write_cqe_slot(cq, cq->wq.cc + i, &title); 454 i++; 455 456 if (i == cqe_count) 457 break; 458 if (i % MLX5E_MINI_ARRAY_SZ == 0) 459 mlx5e_read_cqe_slot(cq, cq->wq.cc + i, mini_array); 460 } 461 } 462 463 static int 464 mlx5e_poll_rx_cq(struct mlx5e_rq *rq, int budget) 465 { 466 struct pfil_head *pfil; 467 int i, rv; 468 469 CURVNET_SET_QUIET(rq->ifp->if_vnet); 470 pfil = rq->channel->priv->pfil; 471 for (i = 0; i < budget; i++) { 472 struct mlx5e_rx_wqe *wqe; 473 struct mlx5_cqe64 *cqe; 474 struct mbuf *mb; 475 __be16 wqe_counter_be; 476 u16 wqe_counter; 477 u32 byte_cnt, seglen; 478 479 cqe = mlx5e_get_cqe(&rq->cq); 480 if (!cqe) 481 break; 482 483 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) 484 mlx5e_decompress_cqes(&rq->cq); 485 486 mlx5_cqwq_pop(&rq->cq.wq); 487 488 wqe_counter_be = cqe->wqe_counter; 489 wqe_counter = be16_to_cpu(wqe_counter_be); 490 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 491 byte_cnt = be32_to_cpu(cqe->byte_cnt); 492 493 bus_dmamap_sync(rq->dma_tag, 494 rq->mbuf[wqe_counter].dma_map, 495 BUS_DMASYNC_POSTREAD); 496 497 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 498 mlx5e_dump_err_cqe(&rq->cq, rq->rqn, (const void *)cqe); 499 rq->stats.wqe_err++; 500 goto wq_ll_pop; 501 } 502 if (pfil != NULL && PFIL_HOOKED_IN(pfil)) { 503 seglen = MIN(byte_cnt, MLX5E_MAX_RX_BYTES); 504 rv = pfil_run_hooks(rq->channel->priv->pfil, 505 rq->mbuf[wqe_counter].data, rq->ifp, 506 seglen | PFIL_MEMPTR | PFIL_IN, NULL); 507 508 switch (rv) { 509 case PFIL_DROPPED: 510 case PFIL_CONSUMED: 511 /* 512 * Filter dropped or consumed it. In 513 * either case, we can just recycle 514 * buffer; there is no more work to do. 515 */ 516 rq->stats.packets++; 517 goto wq_ll_pop; 518 case PFIL_REALLOCED: 519 /* 520 * Filter copied it; recycle buffer 521 * and receive the new mbuf allocated 522 * by the Filter 523 */ 524 mb = pfil_mem2mbuf(rq->mbuf[wqe_counter].data); 525 goto rx_common; 526 default: 527 /* 528 * The Filter said it was OK, so 529 * receive like normal. 530 */ 531 KASSERT(rv == PFIL_PASS, 532 ("Filter returned %d!\n", rv)); 533 } 534 } 535 if ((MHLEN - MLX5E_NET_IP_ALIGN) >= byte_cnt && 536 (mb = m_gethdr(M_NOWAIT, MT_DATA)) != NULL) { 537 /* set maximum mbuf length */ 538 mb->m_len = MHLEN - MLX5E_NET_IP_ALIGN; 539 /* get IP header aligned */ 540 mb->m_data += MLX5E_NET_IP_ALIGN; 541 542 bcopy(rq->mbuf[wqe_counter].data, mtod(mb, caddr_t), 543 byte_cnt); 544 } else { 545 mb = rq->mbuf[wqe_counter].mbuf; 546 rq->mbuf[wqe_counter].mbuf = NULL; /* safety clear */ 547 548 bus_dmamap_unload(rq->dma_tag, 549 rq->mbuf[wqe_counter].dma_map); 550 } 551 rx_common: 552 mlx5e_build_rx_mbuf(cqe, rq, mb, byte_cnt); 553 rq->stats.bytes += byte_cnt; 554 rq->stats.packets++; 555 #ifdef NUMA 556 mb->m_pkthdr.numa_domain = rq->ifp->if_numa_domain; 557 #endif 558 559 #if !defined(HAVE_TCP_LRO_RX) 560 tcp_lro_queue_mbuf(&rq->lro, mb); 561 #else 562 if (mb->m_pkthdr.csum_flags == 0 || 563 (rq->ifp->if_capenable & IFCAP_LRO) == 0 || 564 rq->lro.lro_cnt == 0 || 565 tcp_lro_rx(&rq->lro, mb, 0) != 0) { 566 rq->ifp->if_input(rq->ifp, mb); 567 } 568 #endif 569 wq_ll_pop: 570 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 571 &wqe->next.next_wqe_index); 572 } 573 CURVNET_RESTORE(); 574 575 mlx5_cqwq_update_db_record(&rq->cq.wq); 576 577 /* ensure cq space is freed before enabling more cqes */ 578 atomic_thread_fence_rel(); 579 return (i); 580 } 581 582 void 583 mlx5e_rx_cq_comp(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe __unused) 584 { 585 struct mlx5e_channel *c = container_of(mcq, struct mlx5e_channel, rq.cq.mcq); 586 struct mlx5e_rq *rq = container_of(mcq, struct mlx5e_rq, cq.mcq); 587 int i = 0; 588 589 #ifdef HAVE_PER_CQ_EVENT_PACKET 590 #if (MHLEN < 15) 591 #error "MHLEN is too small" 592 #endif 593 struct mbuf *mb = m_gethdr(M_NOWAIT, MT_DATA); 594 595 if (mb != NULL) { 596 /* this code is used for debugging purpose only */ 597 mb->m_pkthdr.len = mb->m_len = 15; 598 memset(mb->m_data, 255, 14); 599 mb->m_data[14] = rq->ix; 600 mb->m_pkthdr.rcvif = rq->ifp; 601 rq->ifp->if_input(rq->ifp, mb); 602 } 603 #endif 604 for (int j = 0; j != MLX5E_MAX_TX_NUM_TC; j++) { 605 mtx_lock(&c->sq[j].lock); 606 c->sq[j].db_inhibit++; 607 mtx_unlock(&c->sq[j].lock); 608 } 609 610 mtx_lock(&c->iq.lock); 611 c->iq.db_inhibit++; 612 mtx_unlock(&c->iq.lock); 613 614 mtx_lock(&rq->mtx); 615 616 /* 617 * Polling the entire CQ without posting new WQEs results in 618 * lack of receive WQEs during heavy traffic scenarios. 619 */ 620 while (1) { 621 if (mlx5e_poll_rx_cq(rq, MLX5E_RX_BUDGET_MAX) != 622 MLX5E_RX_BUDGET_MAX) 623 break; 624 i += MLX5E_RX_BUDGET_MAX; 625 if (i >= MLX5E_BUDGET_MAX) 626 break; 627 mlx5e_post_rx_wqes(rq); 628 } 629 mlx5e_post_rx_wqes(rq); 630 /* check for dynamic interrupt moderation callback */ 631 if (rq->dim.mode != NET_DIM_CQ_PERIOD_MODE_DISABLED) 632 net_dim(&rq->dim, rq->stats.packets, rq->stats.bytes); 633 mlx5e_cq_arm(&rq->cq, MLX5_GET_DOORBELL_LOCK(&rq->channel->priv->doorbell_lock)); 634 tcp_lro_flush_all(&rq->lro); 635 mtx_unlock(&rq->mtx); 636 637 for (int j = 0; j != MLX5E_MAX_TX_NUM_TC; j++) { 638 mtx_lock(&c->sq[j].lock); 639 c->sq[j].db_inhibit--; 640 /* Update the doorbell record, if any. */ 641 mlx5e_tx_notify_hw(c->sq + j, true); 642 mtx_unlock(&c->sq[j].lock); 643 } 644 645 mtx_lock(&c->iq.lock); 646 c->iq.db_inhibit--; 647 mlx5e_iq_notify_hw(&c->iq); 648 mtx_unlock(&c->iq.lock); 649 } 650