1 /*- 2 * Copyright (c) 2015-2021 Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include "opt_rss.h" 29 #include "opt_ratelimit.h" 30 31 #include <dev/mlx5/mlx5_en/en.h> 32 #include <machine/in_cksum.h> 33 34 static inline int 35 mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, 36 struct mlx5e_rx_wqe *wqe, u16 ix) 37 { 38 bus_dma_segment_t segs[MLX5E_MAX_BUSDMA_RX_SEGS]; 39 struct mbuf *mb; 40 int nsegs; 41 int err; 42 struct mbuf *mb_head; 43 int i; 44 45 if (rq->mbuf[ix].mbuf != NULL) 46 return (0); 47 48 mb_head = mb = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, 49 MLX5E_MAX_RX_BYTES); 50 if (unlikely(mb == NULL)) 51 return (-ENOMEM); 52 53 mb->m_len = MLX5E_MAX_RX_BYTES; 54 mb->m_pkthdr.len = MLX5E_MAX_RX_BYTES; 55 56 for (i = 1; i < rq->nsegs; i++) { 57 if (mb_head->m_pkthdr.len >= rq->wqe_sz) 58 break; 59 mb = mb->m_next = m_getjcl(M_NOWAIT, MT_DATA, 0, 60 MLX5E_MAX_RX_BYTES); 61 if (unlikely(mb == NULL)) { 62 m_freem(mb_head); 63 return (-ENOMEM); 64 } 65 mb->m_len = MLX5E_MAX_RX_BYTES; 66 mb_head->m_pkthdr.len += MLX5E_MAX_RX_BYTES; 67 } 68 /* rewind to first mbuf in chain */ 69 mb = mb_head; 70 71 /* get IP header aligned */ 72 m_adj(mb, MLX5E_NET_IP_ALIGN); 73 74 err = -bus_dmamap_load_mbuf_sg(rq->dma_tag, rq->mbuf[ix].dma_map, 75 mb, segs, &nsegs, BUS_DMA_NOWAIT); 76 if (err != 0) 77 goto err_free_mbuf; 78 if (unlikely(nsegs == 0)) { 79 bus_dmamap_unload(rq->dma_tag, rq->mbuf[ix].dma_map); 80 err = -ENOMEM; 81 goto err_free_mbuf; 82 } 83 wqe->data[0].addr = cpu_to_be64(segs[0].ds_addr); 84 wqe->data[0].byte_count = cpu_to_be32(segs[0].ds_len | 85 MLX5_HW_START_PADDING); 86 for (i = 1; i != nsegs; i++) { 87 wqe->data[i].addr = cpu_to_be64(segs[i].ds_addr); 88 wqe->data[i].byte_count = cpu_to_be32(segs[i].ds_len); 89 } 90 for (; i < rq->nsegs; i++) { 91 wqe->data[i].addr = 0; 92 wqe->data[i].byte_count = 0; 93 } 94 95 rq->mbuf[ix].mbuf = mb; 96 rq->mbuf[ix].data = mb->m_data; 97 98 bus_dmamap_sync(rq->dma_tag, rq->mbuf[ix].dma_map, 99 BUS_DMASYNC_PREREAD); 100 return (0); 101 102 err_free_mbuf: 103 m_freem(mb); 104 return (err); 105 } 106 107 static void 108 mlx5e_post_rx_wqes(struct mlx5e_rq *rq) 109 { 110 if (unlikely(rq->enabled == 0)) 111 return; 112 113 while (!mlx5_wq_ll_is_full(&rq->wq)) { 114 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, rq->wq.head); 115 116 if (unlikely(mlx5e_alloc_rx_wqe(rq, wqe, rq->wq.head))) { 117 callout_reset_curcpu(&rq->watchdog, 1, (void *)&mlx5e_post_rx_wqes, rq); 118 break; 119 } 120 mlx5_wq_ll_push(&rq->wq, be16_to_cpu(wqe->next.next_wqe_index)); 121 } 122 123 /* ensure wqes are visible to device before updating doorbell record */ 124 atomic_thread_fence_rel(); 125 126 mlx5_wq_ll_update_db_record(&rq->wq); 127 } 128 129 static void 130 mlx5e_lro_update_hdr(struct mbuf *mb, struct mlx5_cqe64 *cqe) 131 { 132 /* TODO: consider vlans, ip options, ... */ 133 struct ether_header *eh; 134 uint16_t eh_type; 135 uint16_t tot_len; 136 struct ip6_hdr *ip6 = NULL; 137 struct ip *ip4 = NULL; 138 struct tcphdr *th; 139 uint32_t *ts_ptr; 140 uint8_t l4_hdr_type; 141 int tcp_ack; 142 143 eh = mtod(mb, struct ether_header *); 144 eh_type = ntohs(eh->ether_type); 145 146 l4_hdr_type = get_cqe_l4_hdr_type(cqe); 147 tcp_ack = ((CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA == l4_hdr_type) || 148 (CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA == l4_hdr_type)); 149 150 /* TODO: consider vlan */ 151 tot_len = be32_to_cpu(cqe->byte_cnt) - ETHER_HDR_LEN; 152 153 switch (eh_type) { 154 case ETHERTYPE_IP: 155 ip4 = (struct ip *)(eh + 1); 156 th = (struct tcphdr *)(ip4 + 1); 157 break; 158 case ETHERTYPE_IPV6: 159 ip6 = (struct ip6_hdr *)(eh + 1); 160 th = (struct tcphdr *)(ip6 + 1); 161 break; 162 default: 163 return; 164 } 165 166 ts_ptr = (uint32_t *)(th + 1); 167 168 if (get_cqe_lro_tcppsh(cqe)) 169 th->th_flags |= TH_PUSH; 170 171 if (tcp_ack) { 172 th->th_flags |= TH_ACK; 173 th->th_ack = cqe->lro_ack_seq_num; 174 th->th_win = cqe->lro_tcp_win; 175 176 /* 177 * FreeBSD handles only 32bit aligned timestamp right after 178 * the TCP hdr 179 * +--------+--------+--------+--------+ 180 * | NOP | NOP | TSopt | 10 | 181 * +--------+--------+--------+--------+ 182 * | TSval timestamp | 183 * +--------+--------+--------+--------+ 184 * | TSecr timestamp | 185 * +--------+--------+--------+--------+ 186 */ 187 if (get_cqe_lro_timestamp_valid(cqe) && 188 (__predict_true(*ts_ptr) == ntohl(TCPOPT_NOP << 24 | 189 TCPOPT_NOP << 16 | TCPOPT_TIMESTAMP << 8 | 190 TCPOLEN_TIMESTAMP))) { 191 /* 192 * cqe->timestamp is 64bit long. 193 * [0-31] - timestamp. 194 * [32-64] - timestamp echo replay. 195 */ 196 ts_ptr[1] = *(uint32_t *)&cqe->timestamp; 197 ts_ptr[2] = *((uint32_t *)&cqe->timestamp + 1); 198 } 199 } 200 if (ip4) { 201 ip4->ip_ttl = cqe->lro_min_ttl; 202 ip4->ip_len = cpu_to_be16(tot_len); 203 ip4->ip_sum = 0; 204 ip4->ip_sum = in_cksum(mb, ip4->ip_hl << 2); 205 } else { 206 ip6->ip6_hlim = cqe->lro_min_ttl; 207 ip6->ip6_plen = cpu_to_be16(tot_len - 208 sizeof(struct ip6_hdr)); 209 } 210 /* TODO: handle tcp checksum */ 211 } 212 213 static uint64_t 214 mlx5e_mbuf_tstmp(struct mlx5e_priv *priv, uint64_t hw_tstmp) 215 { 216 struct mlx5e_clbr_point *cp, dcp; 217 uint64_t a1, a2, res; 218 u_int gen; 219 220 do { 221 cp = &priv->clbr_points[priv->clbr_curr]; 222 gen = atomic_load_acq_int(&cp->clbr_gen); 223 if (gen == 0) 224 return (0); 225 dcp = *cp; 226 atomic_thread_fence_acq(); 227 } while (gen != cp->clbr_gen); 228 229 a1 = (hw_tstmp - dcp.clbr_hw_prev) >> MLX5E_TSTMP_PREC; 230 a2 = (dcp.base_curr - dcp.base_prev) >> MLX5E_TSTMP_PREC; 231 res = (a1 * a2) << MLX5E_TSTMP_PREC; 232 233 /* 234 * Divisor cannot be zero because calibration callback 235 * checks for the condition and disables timestamping 236 * if clock halted. 237 */ 238 res /= (dcp.clbr_hw_curr - dcp.clbr_hw_prev) >> MLX5E_TSTMP_PREC; 239 240 res += dcp.base_prev; 241 return (res); 242 } 243 244 static inline void 245 mlx5e_build_rx_mbuf(struct mlx5_cqe64 *cqe, 246 struct mlx5e_rq *rq, struct mbuf *mb, 247 u32 cqe_bcnt) 248 { 249 struct ifnet *ifp = rq->ifp; 250 struct mlx5e_channel *c; 251 struct mbuf *mb_head; 252 int lro_num_seg; /* HW LRO session aggregated packets counter */ 253 uint64_t tstmp; 254 255 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24; 256 if (lro_num_seg > 1) { 257 mlx5e_lro_update_hdr(mb, cqe); 258 rq->stats.lro_packets++; 259 rq->stats.lro_bytes += cqe_bcnt; 260 } 261 262 mb->m_pkthdr.len = cqe_bcnt; 263 for (mb_head = mb; mb != NULL; mb = mb->m_next) { 264 if (mb->m_len > cqe_bcnt) 265 mb->m_len = cqe_bcnt; 266 cqe_bcnt -= mb->m_len; 267 if (likely(cqe_bcnt == 0)) { 268 if (likely(mb->m_next != NULL)) { 269 /* trim off empty mbufs */ 270 m_freem(mb->m_next); 271 mb->m_next = NULL; 272 } 273 break; 274 } 275 } 276 /* rewind to first mbuf in chain */ 277 mb = mb_head; 278 279 /* check if a Toeplitz hash was computed */ 280 if (cqe->rss_hash_type != 0) { 281 mb->m_pkthdr.flowid = be32_to_cpu(cqe->rss_hash_result); 282 #ifdef RSS 283 /* decode the RSS hash type */ 284 switch (cqe->rss_hash_type & 285 (CQE_RSS_DST_HTYPE_L4 | CQE_RSS_DST_HTYPE_IP)) { 286 /* IPv4 */ 287 case (CQE_RSS_DST_HTYPE_TCP | CQE_RSS_DST_HTYPE_IPV4): 288 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_TCP_IPV4); 289 break; 290 case (CQE_RSS_DST_HTYPE_UDP | CQE_RSS_DST_HTYPE_IPV4): 291 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_UDP_IPV4); 292 break; 293 case CQE_RSS_DST_HTYPE_IPV4: 294 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_IPV4); 295 break; 296 /* IPv6 */ 297 case (CQE_RSS_DST_HTYPE_TCP | CQE_RSS_DST_HTYPE_IPV6): 298 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_TCP_IPV6); 299 break; 300 case (CQE_RSS_DST_HTYPE_UDP | CQE_RSS_DST_HTYPE_IPV6): 301 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_UDP_IPV6); 302 break; 303 case CQE_RSS_DST_HTYPE_IPV6: 304 M_HASHTYPE_SET(mb, M_HASHTYPE_RSS_IPV6); 305 break; 306 default: /* Other */ 307 M_HASHTYPE_SET(mb, M_HASHTYPE_OPAQUE_HASH); 308 break; 309 } 310 #else 311 M_HASHTYPE_SET(mb, M_HASHTYPE_OPAQUE_HASH); 312 #endif 313 #ifdef M_HASHTYPE_SETINNER 314 if (cqe_is_tunneled(cqe)) 315 M_HASHTYPE_SETINNER(mb); 316 #endif 317 } else { 318 mb->m_pkthdr.flowid = rq->ix; 319 M_HASHTYPE_SET(mb, M_HASHTYPE_OPAQUE); 320 } 321 mb->m_pkthdr.rcvif = ifp; 322 mb->m_pkthdr.leaf_rcvif = ifp; 323 324 if (cqe_is_tunneled(cqe)) { 325 /* 326 * CQE can be tunneled only if TIR is configured to 327 * enable parsing of tunneled payload, so no need to 328 * check for capabilities. 329 */ 330 if (((cqe->hds_ip_ext & (CQE_L2_OK | CQE_L3_OK)) == 331 (CQE_L2_OK | CQE_L3_OK))) { 332 mb->m_pkthdr.csum_flags |= 333 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID | 334 CSUM_IP_CHECKED | CSUM_IP_VALID | 335 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 336 mb->m_pkthdr.csum_data = htons(0xffff); 337 338 if (likely((cqe->hds_ip_ext & CQE_L4_OK) == CQE_L4_OK)) { 339 mb->m_pkthdr.csum_flags |= 340 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID; 341 } 342 } else { 343 rq->stats.csum_none++; 344 } 345 } else if (likely((ifp->if_capenable & (IFCAP_RXCSUM | 346 IFCAP_RXCSUM_IPV6)) != 0) && 347 ((cqe->hds_ip_ext & (CQE_L2_OK | CQE_L3_OK | CQE_L4_OK)) == 348 (CQE_L2_OK | CQE_L3_OK | CQE_L4_OK))) { 349 mb->m_pkthdr.csum_flags = 350 CSUM_IP_CHECKED | CSUM_IP_VALID | 351 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 352 mb->m_pkthdr.csum_data = htons(0xffff); 353 } else { 354 rq->stats.csum_none++; 355 } 356 357 if (cqe_has_vlan(cqe)) { 358 mb->m_pkthdr.ether_vtag = be16_to_cpu(cqe->vlan_info); 359 mb->m_flags |= M_VLANTAG; 360 } 361 362 c = container_of(rq, struct mlx5e_channel, rq); 363 if (c->priv->clbr_done >= 2) { 364 tstmp = mlx5e_mbuf_tstmp(c->priv, be64_to_cpu(cqe->timestamp)); 365 if ((tstmp & MLX5_CQE_TSTMP_PTP) != 0) { 366 /* 367 * Timestamp was taken on the packet entrance, 368 * instead of the cqe generation. 369 */ 370 tstmp &= ~MLX5_CQE_TSTMP_PTP; 371 mb->m_flags |= M_TSTMP_HPREC; 372 } 373 mb->m_pkthdr.rcv_tstmp = tstmp; 374 mb->m_flags |= M_TSTMP; 375 } 376 377 switch (get_cqe_tls_offload(cqe)) { 378 case CQE_TLS_OFFLOAD_DECRYPTED: 379 /* set proper checksum flag for decrypted packets */ 380 mb->m_pkthdr.csum_flags |= CSUM_TLS_DECRYPTED; 381 rq->stats.decrypted_ok_packets++; 382 break; 383 case CQE_TLS_OFFLOAD_ERROR: 384 rq->stats.decrypted_error_packets++; 385 break; 386 default: 387 break; 388 } 389 } 390 391 static inline void 392 mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cc, void *data) 393 { 394 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, (cc & cq->wq.sz_m1)), 395 sizeof(struct mlx5_cqe64)); 396 } 397 398 static inline void 399 mlx5e_write_cqe_slot(struct mlx5e_cq *cq, u32 cc, void *data) 400 { 401 memcpy(mlx5_cqwq_get_wqe(&cq->wq, cc & cq->wq.sz_m1), 402 data, sizeof(struct mlx5_cqe64)); 403 } 404 405 static inline void 406 mlx5e_decompress_cqe(struct mlx5e_cq *cq, struct mlx5_cqe64 *title, 407 struct mlx5_mini_cqe8 *mini, 408 u16 wqe_counter, int i) 409 { 410 /* 411 * NOTE: The fields which are not set here are copied from the 412 * initial and common title. See memcpy() in 413 * mlx5e_write_cqe_slot(). 414 */ 415 title->byte_cnt = mini->byte_cnt; 416 title->wqe_counter = cpu_to_be16((wqe_counter + i) & cq->wq.sz_m1); 417 title->rss_hash_result = mini->rx_hash_result; 418 /* 419 * Since we use MLX5_CQE_FORMAT_HASH when creating the RX CQ, 420 * the value of the checksum should be ignored. 421 */ 422 title->check_sum = 0; 423 title->op_own = (title->op_own & 0xf0) | 424 (((cq->wq.cc + i) >> cq->wq.log_sz) & 1); 425 } 426 427 #define MLX5E_MINI_ARRAY_SZ 8 428 /* Make sure structs are not packet differently */ 429 CTASSERT(sizeof(struct mlx5_cqe64) == 430 sizeof(struct mlx5_mini_cqe8) * MLX5E_MINI_ARRAY_SZ); 431 static void 432 mlx5e_decompress_cqes(struct mlx5e_cq *cq) 433 { 434 struct mlx5_mini_cqe8 mini_array[MLX5E_MINI_ARRAY_SZ]; 435 struct mlx5_cqe64 title; 436 u32 cqe_count; 437 u32 i = 0; 438 u16 title_wqe_counter; 439 440 mlx5e_read_cqe_slot(cq, cq->wq.cc, &title); 441 title_wqe_counter = be16_to_cpu(title.wqe_counter); 442 cqe_count = be32_to_cpu(title.byte_cnt); 443 444 /* Make sure we won't overflow */ 445 KASSERT(cqe_count <= cq->wq.sz_m1, 446 ("%s: cqe_count %u > cq->wq.sz_m1 %u", __func__, 447 cqe_count, cq->wq.sz_m1)); 448 449 mlx5e_read_cqe_slot(cq, cq->wq.cc + 1, mini_array); 450 while (true) { 451 mlx5e_decompress_cqe(cq, &title, 452 &mini_array[i % MLX5E_MINI_ARRAY_SZ], 453 title_wqe_counter, i); 454 mlx5e_write_cqe_slot(cq, cq->wq.cc + i, &title); 455 i++; 456 457 if (i == cqe_count) 458 break; 459 if (i % MLX5E_MINI_ARRAY_SZ == 0) 460 mlx5e_read_cqe_slot(cq, cq->wq.cc + i, mini_array); 461 } 462 } 463 464 static int 465 mlx5e_poll_rx_cq(struct mlx5e_rq *rq, int budget) 466 { 467 struct pfil_head *pfil; 468 int i, rv; 469 470 CURVNET_SET_QUIET(rq->ifp->if_vnet); 471 pfil = rq->channel->priv->pfil; 472 for (i = 0; i < budget; i++) { 473 struct mlx5e_rx_wqe *wqe; 474 struct mlx5_cqe64 *cqe; 475 struct mbuf *mb; 476 __be16 wqe_counter_be; 477 u16 wqe_counter; 478 u32 byte_cnt, seglen; 479 480 cqe = mlx5e_get_cqe(&rq->cq); 481 if (!cqe) 482 break; 483 484 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) 485 mlx5e_decompress_cqes(&rq->cq); 486 487 mlx5_cqwq_pop(&rq->cq.wq); 488 489 wqe_counter_be = cqe->wqe_counter; 490 wqe_counter = be16_to_cpu(wqe_counter_be); 491 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 492 byte_cnt = be32_to_cpu(cqe->byte_cnt); 493 494 bus_dmamap_sync(rq->dma_tag, 495 rq->mbuf[wqe_counter].dma_map, 496 BUS_DMASYNC_POSTREAD); 497 498 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 499 mlx5e_dump_err_cqe(&rq->cq, rq->rqn, (const void *)cqe); 500 rq->stats.wqe_err++; 501 goto wq_ll_pop; 502 } 503 if (pfil != NULL && PFIL_HOOKED_IN(pfil)) { 504 seglen = MIN(byte_cnt, MLX5E_MAX_RX_BYTES); 505 rv = pfil_run_hooks(rq->channel->priv->pfil, 506 rq->mbuf[wqe_counter].data, rq->ifp, 507 seglen | PFIL_MEMPTR | PFIL_IN, NULL); 508 509 switch (rv) { 510 case PFIL_DROPPED: 511 case PFIL_CONSUMED: 512 /* 513 * Filter dropped or consumed it. In 514 * either case, we can just recycle 515 * buffer; there is no more work to do. 516 */ 517 rq->stats.packets++; 518 goto wq_ll_pop; 519 case PFIL_REALLOCED: 520 /* 521 * Filter copied it; recycle buffer 522 * and receive the new mbuf allocated 523 * by the Filter 524 */ 525 mb = pfil_mem2mbuf(rq->mbuf[wqe_counter].data); 526 goto rx_common; 527 default: 528 /* 529 * The Filter said it was OK, so 530 * receive like normal. 531 */ 532 KASSERT(rv == PFIL_PASS, 533 ("Filter returned %d!\n", rv)); 534 } 535 } 536 if ((MHLEN - MLX5E_NET_IP_ALIGN) >= byte_cnt && 537 (mb = m_gethdr(M_NOWAIT, MT_DATA)) != NULL) { 538 /* set maximum mbuf length */ 539 mb->m_len = MHLEN - MLX5E_NET_IP_ALIGN; 540 /* get IP header aligned */ 541 mb->m_data += MLX5E_NET_IP_ALIGN; 542 543 bcopy(rq->mbuf[wqe_counter].data, mtod(mb, caddr_t), 544 byte_cnt); 545 } else { 546 mb = rq->mbuf[wqe_counter].mbuf; 547 rq->mbuf[wqe_counter].mbuf = NULL; /* safety clear */ 548 549 bus_dmamap_unload(rq->dma_tag, 550 rq->mbuf[wqe_counter].dma_map); 551 } 552 rx_common: 553 mlx5e_build_rx_mbuf(cqe, rq, mb, byte_cnt); 554 rq->stats.bytes += byte_cnt; 555 rq->stats.packets++; 556 #ifdef NUMA 557 mb->m_pkthdr.numa_domain = rq->ifp->if_numa_domain; 558 #endif 559 560 #if !defined(HAVE_TCP_LRO_RX) 561 tcp_lro_queue_mbuf(&rq->lro, mb); 562 #else 563 if (mb->m_pkthdr.csum_flags == 0 || 564 (rq->ifp->if_capenable & IFCAP_LRO) == 0 || 565 rq->lro.lro_cnt == 0 || 566 tcp_lro_rx(&rq->lro, mb, 0) != 0) { 567 rq->ifp->if_input(rq->ifp, mb); 568 } 569 #endif 570 wq_ll_pop: 571 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 572 &wqe->next.next_wqe_index); 573 } 574 CURVNET_RESTORE(); 575 576 mlx5_cqwq_update_db_record(&rq->cq.wq); 577 578 /* ensure cq space is freed before enabling more cqes */ 579 atomic_thread_fence_rel(); 580 return (i); 581 } 582 583 void 584 mlx5e_rx_cq_comp(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe __unused) 585 { 586 struct mlx5e_channel *c = container_of(mcq, struct mlx5e_channel, rq.cq.mcq); 587 struct mlx5e_rq *rq = container_of(mcq, struct mlx5e_rq, cq.mcq); 588 int i = 0; 589 590 #ifdef HAVE_PER_CQ_EVENT_PACKET 591 #if (MHLEN < 15) 592 #error "MHLEN is too small" 593 #endif 594 struct mbuf *mb = m_gethdr(M_NOWAIT, MT_DATA); 595 596 if (mb != NULL) { 597 /* this code is used for debugging purpose only */ 598 mb->m_pkthdr.len = mb->m_len = 15; 599 memset(mb->m_data, 255, 14); 600 mb->m_data[14] = rq->ix; 601 mb->m_pkthdr.rcvif = rq->ifp; 602 mb->m_pkthdr.leaf_rcvif = rq->ifp; 603 rq->ifp->if_input(rq->ifp, mb); 604 } 605 #endif 606 for (int j = 0; j != MLX5E_MAX_TX_NUM_TC; j++) { 607 mtx_lock(&c->sq[j].lock); 608 c->sq[j].db_inhibit++; 609 mtx_unlock(&c->sq[j].lock); 610 } 611 612 mtx_lock(&c->iq.lock); 613 c->iq.db_inhibit++; 614 mtx_unlock(&c->iq.lock); 615 616 mtx_lock(&rq->mtx); 617 618 /* 619 * Polling the entire CQ without posting new WQEs results in 620 * lack of receive WQEs during heavy traffic scenarios. 621 */ 622 while (1) { 623 if (mlx5e_poll_rx_cq(rq, MLX5E_RX_BUDGET_MAX) != 624 MLX5E_RX_BUDGET_MAX) 625 break; 626 i += MLX5E_RX_BUDGET_MAX; 627 if (i >= MLX5E_BUDGET_MAX) 628 break; 629 mlx5e_post_rx_wqes(rq); 630 } 631 mlx5e_post_rx_wqes(rq); 632 /* check for dynamic interrupt moderation callback */ 633 if (rq->dim.mode != NET_DIM_CQ_PERIOD_MODE_DISABLED) 634 net_dim(&rq->dim, rq->stats.packets, rq->stats.bytes); 635 mlx5e_cq_arm(&rq->cq, MLX5_GET_DOORBELL_LOCK(&rq->channel->priv->doorbell_lock)); 636 tcp_lro_flush_all(&rq->lro); 637 mtx_unlock(&rq->mtx); 638 639 for (int j = 0; j != MLX5E_MAX_TX_NUM_TC; j++) { 640 mtx_lock(&c->sq[j].lock); 641 c->sq[j].db_inhibit--; 642 /* Update the doorbell record, if any. */ 643 mlx5e_tx_notify_hw(c->sq + j, true); 644 mtx_unlock(&c->sq[j].lock); 645 } 646 647 mtx_lock(&c->iq.lock); 648 c->iq.db_inhibit--; 649 mlx5e_iq_notify_hw(&c->iq); 650 mtx_unlock(&c->iq.lock); 651 } 652