1 /*- 2 * Copyright (c) 2015-2021 Mellanox Technologies. All rights reserved. 3 * Copyright (c) 2022 NVIDIA corporation & affiliates. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include "opt_ipsec.h" 28 #include "opt_kern_tls.h" 29 #include "opt_rss.h" 30 #include "opt_ratelimit.h" 31 32 #include <dev/mlx5/mlx5_en/en.h> 33 #include <dev/mlx5/mlx5_accel/ipsec.h> 34 35 #include <sys/eventhandler.h> 36 #include <sys/sockio.h> 37 #include <machine/atomic.h> 38 39 #include <net/debugnet.h> 40 #include <netinet/tcp_ratelimit.h> 41 #include <netipsec/keydb.h> 42 #include <netipsec/ipsec_offload.h> 43 44 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs); 45 static if_snd_tag_query_t mlx5e_ul_snd_tag_query; 46 static if_snd_tag_free_t mlx5e_ul_snd_tag_free; 47 48 struct mlx5e_channel_param { 49 struct mlx5e_rq_param rq; 50 struct mlx5e_sq_param sq; 51 struct mlx5e_cq_param rx_cq; 52 struct mlx5e_cq_param tx_cq; 53 }; 54 55 struct media { 56 u32 subtype; 57 u64 baudrate; 58 }; 59 60 static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER] = 61 { 62 [MLX5E_1000BASE_CX_SGMII] = { 63 .subtype = IFM_1000_CX_SGMII, 64 .baudrate = IF_Mbps(1000ULL), 65 }, 66 [MLX5E_1000BASE_KX] = { 67 .subtype = IFM_1000_KX, 68 .baudrate = IF_Mbps(1000ULL), 69 }, 70 [MLX5E_10GBASE_CX4] = { 71 .subtype = IFM_10G_CX4, 72 .baudrate = IF_Gbps(10ULL), 73 }, 74 [MLX5E_10GBASE_KX4] = { 75 .subtype = IFM_10G_KX4, 76 .baudrate = IF_Gbps(10ULL), 77 }, 78 [MLX5E_10GBASE_KR] = { 79 .subtype = IFM_10G_KR, 80 .baudrate = IF_Gbps(10ULL), 81 }, 82 [MLX5E_20GBASE_KR2] = { 83 .subtype = IFM_20G_KR2, 84 .baudrate = IF_Gbps(20ULL), 85 }, 86 [MLX5E_40GBASE_CR4] = { 87 .subtype = IFM_40G_CR4, 88 .baudrate = IF_Gbps(40ULL), 89 }, 90 [MLX5E_40GBASE_KR4] = { 91 .subtype = IFM_40G_KR4, 92 .baudrate = IF_Gbps(40ULL), 93 }, 94 [MLX5E_56GBASE_R4] = { 95 .subtype = IFM_56G_R4, 96 .baudrate = IF_Gbps(56ULL), 97 }, 98 [MLX5E_10GBASE_CR] = { 99 .subtype = IFM_10G_CR1, 100 .baudrate = IF_Gbps(10ULL), 101 }, 102 [MLX5E_10GBASE_SR] = { 103 .subtype = IFM_10G_SR, 104 .baudrate = IF_Gbps(10ULL), 105 }, 106 [MLX5E_10GBASE_ER_LR] = { 107 .subtype = IFM_10G_ER, 108 .baudrate = IF_Gbps(10ULL), 109 }, 110 [MLX5E_40GBASE_SR4] = { 111 .subtype = IFM_40G_SR4, 112 .baudrate = IF_Gbps(40ULL), 113 }, 114 [MLX5E_40GBASE_LR4_ER4] = { 115 .subtype = IFM_40G_LR4, 116 .baudrate = IF_Gbps(40ULL), 117 }, 118 [MLX5E_100GBASE_CR4] = { 119 .subtype = IFM_100G_CR4, 120 .baudrate = IF_Gbps(100ULL), 121 }, 122 [MLX5E_100GBASE_SR4] = { 123 .subtype = IFM_100G_SR4, 124 .baudrate = IF_Gbps(100ULL), 125 }, 126 [MLX5E_100GBASE_KR4] = { 127 .subtype = IFM_100G_KR4, 128 .baudrate = IF_Gbps(100ULL), 129 }, 130 [MLX5E_100GBASE_LR4] = { 131 .subtype = IFM_100G_LR4, 132 .baudrate = IF_Gbps(100ULL), 133 }, 134 [MLX5E_100BASE_TX] = { 135 .subtype = IFM_100_TX, 136 .baudrate = IF_Mbps(100ULL), 137 }, 138 [MLX5E_1000BASE_T] = { 139 .subtype = IFM_1000_T, 140 .baudrate = IF_Mbps(1000ULL), 141 }, 142 [MLX5E_10GBASE_T] = { 143 .subtype = IFM_10G_T, 144 .baudrate = IF_Gbps(10ULL), 145 }, 146 [MLX5E_25GBASE_CR] = { 147 .subtype = IFM_25G_CR, 148 .baudrate = IF_Gbps(25ULL), 149 }, 150 [MLX5E_25GBASE_KR] = { 151 .subtype = IFM_25G_KR, 152 .baudrate = IF_Gbps(25ULL), 153 }, 154 [MLX5E_25GBASE_SR] = { 155 .subtype = IFM_25G_SR, 156 .baudrate = IF_Gbps(25ULL), 157 }, 158 [MLX5E_50GBASE_CR2] = { 159 .subtype = IFM_50G_CR2, 160 .baudrate = IF_Gbps(50ULL), 161 }, 162 [MLX5E_50GBASE_KR2] = { 163 .subtype = IFM_50G_KR2, 164 .baudrate = IF_Gbps(50ULL), 165 }, 166 [MLX5E_50GBASE_KR4] = { 167 .subtype = IFM_50G_KR4, 168 .baudrate = IF_Gbps(50ULL), 169 }, 170 }; 171 172 static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_CONNECTOR_TYPE_NUMBER] = 173 { 174 /**/ 175 [MLX5E_SGMII_100M][MLX5E_PORT_UNKNOWN] = { 176 .subtype = IFM_100_SGMII, 177 .baudrate = IF_Mbps(100), 178 }, 179 180 /**/ 181 [MLX5E_1000BASE_X_SGMII][MLX5E_PORT_UNKNOWN] = { 182 .subtype = IFM_1000_CX, 183 .baudrate = IF_Mbps(1000), 184 }, 185 [MLX5E_1000BASE_X_SGMII][MLX5E_PORT_FIBRE] = { 186 .subtype = IFM_1000_SX, 187 .baudrate = IF_Mbps(1000), 188 }, 189 190 /**/ 191 [MLX5E_5GBASE_R][MLX5E_PORT_UNKNOWN] = { 192 .subtype = IFM_5000_KR, 193 .baudrate = IF_Mbps(5000), 194 }, 195 [MLX5E_5GBASE_R][MLX5E_PORT_TP] = { 196 .subtype = IFM_5000_T, 197 .baudrate = IF_Mbps(5000), 198 }, 199 200 /**/ 201 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_PORT_UNKNOWN] = { 202 .subtype = IFM_10G_KR, 203 .baudrate = IF_Gbps(10ULL), 204 }, 205 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_PORT_DA] = { 206 .subtype = IFM_10G_CR1, 207 .baudrate = IF_Gbps(10ULL), 208 }, 209 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_PORT_FIBRE] = { 210 .subtype = IFM_10G_SR, 211 .baudrate = IF_Gbps(10ULL), 212 }, 213 214 /**/ 215 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_PORT_UNKNOWN] = { 216 .subtype = IFM_40G_KR4, 217 .baudrate = IF_Gbps(40ULL), 218 }, 219 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_PORT_DA] = { 220 .subtype = IFM_40G_CR4, 221 .baudrate = IF_Gbps(40ULL), 222 }, 223 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_PORT_FIBRE] = { 224 .subtype = IFM_40G_SR4, 225 .baudrate = IF_Gbps(40ULL), 226 }, 227 228 /**/ 229 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_PORT_UNKNOWN] = { 230 .subtype = IFM_25G_KR, 231 .baudrate = IF_Gbps(25ULL), 232 }, 233 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_PORT_DA] = { 234 .subtype = IFM_25G_CR, 235 .baudrate = IF_Gbps(25ULL), 236 }, 237 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_PORT_FIBRE] = { 238 .subtype = IFM_25G_SR, 239 .baudrate = IF_Gbps(25ULL), 240 }, 241 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_PORT_TP] = { 242 .subtype = IFM_25G_T, 243 .baudrate = IF_Gbps(25ULL), 244 }, 245 246 /**/ 247 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_PORT_UNKNOWN] = { 248 .subtype = IFM_50G_KR2, 249 .baudrate = IF_Gbps(50ULL), 250 }, 251 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_PORT_DA] = { 252 .subtype = IFM_50G_CR2, 253 .baudrate = IF_Gbps(50ULL), 254 }, 255 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_PORT_FIBRE] = { 256 .subtype = IFM_50G_SR2, 257 .baudrate = IF_Gbps(50ULL), 258 }, 259 260 /**/ 261 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_PORT_UNKNOWN] = { 262 .subtype = IFM_50G_KR_PAM4, 263 .baudrate = IF_Gbps(50ULL), 264 }, 265 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_PORT_DA] = { 266 .subtype = IFM_50G_CP, 267 .baudrate = IF_Gbps(50ULL), 268 }, 269 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_PORT_FIBRE] = { 270 .subtype = IFM_50G_SR, 271 .baudrate = IF_Gbps(50ULL), 272 }, 273 274 /**/ 275 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_PORT_UNKNOWN] = { 276 .subtype = IFM_100G_KR4, 277 .baudrate = IF_Gbps(100ULL), 278 }, 279 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_PORT_DA] = { 280 .subtype = IFM_100G_CR4, 281 .baudrate = IF_Gbps(100ULL), 282 }, 283 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_PORT_FIBRE] = { 284 .subtype = IFM_100G_SR4, 285 .baudrate = IF_Gbps(100ULL), 286 }, 287 288 /**/ 289 [MLX5E_100GAUI_1_100GBASE_CR_KR][MLX5E_PORT_UNKNOWN] = { 290 .subtype = IFM_100G_KR_PAM4, 291 .baudrate = IF_Gbps(100ULL), 292 }, 293 [MLX5E_100GAUI_1_100GBASE_CR_KR][MLX5E_PORT_DA] = { 294 .subtype = IFM_100G_CR_PAM4, 295 .baudrate = IF_Gbps(100ULL), 296 }, 297 [MLX5E_100GAUI_1_100GBASE_CR_KR][MLX5E_PORT_FIBRE] = { 298 .subtype = IFM_100G_SR2, /* XXX */ 299 .baudrate = IF_Gbps(100ULL), 300 }, 301 302 /**/ 303 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_PORT_UNKNOWN] = { 304 .subtype = IFM_100G_KR4, 305 .baudrate = IF_Gbps(100ULL), 306 }, 307 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_PORT_DA] = { 308 .subtype = IFM_100G_CP2, 309 .baudrate = IF_Gbps(100ULL), 310 }, 311 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_PORT_FIBRE] = { 312 .subtype = IFM_100G_SR2, 313 .baudrate = IF_Gbps(100ULL), 314 }, 315 316 /**/ 317 [MLX5E_200GAUI_2_200GBASE_CR2_KR2][MLX5E_PORT_UNKNOWN] = { 318 .subtype = IFM_200G_KR4_PAM4, /* XXX */ 319 .baudrate = IF_Gbps(200ULL), 320 }, 321 [MLX5E_200GAUI_2_200GBASE_CR2_KR2][MLX5E_PORT_DA] = { 322 .subtype = IFM_200G_CR4_PAM4, /* XXX */ 323 .baudrate = IF_Gbps(200ULL), 324 }, 325 [MLX5E_200GAUI_2_200GBASE_CR2_KR2][MLX5E_PORT_FIBRE] = { 326 .subtype = IFM_200G_SR4, /* XXX */ 327 .baudrate = IF_Gbps(200ULL), 328 }, 329 330 /**/ 331 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_PORT_UNKNOWN] = { 332 .subtype = IFM_200G_KR4_PAM4, 333 .baudrate = IF_Gbps(200ULL), 334 }, 335 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_PORT_DA] = { 336 .subtype = IFM_200G_CR4_PAM4, 337 .baudrate = IF_Gbps(200ULL), 338 }, 339 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_PORT_FIBRE] = { 340 .subtype = IFM_200G_SR4, 341 .baudrate = IF_Gbps(200ULL), 342 }, 343 344 /**/ 345 [MLX5E_400GAUI_8][MLX5E_PORT_UNKNOWN] = { 346 .subtype = IFM_400G_LR8, /* XXX */ 347 .baudrate = IF_Gbps(400ULL), 348 }, 349 350 /**/ 351 [MLX5E_400GAUI_4_400GBASE_CR4_KR4][MLX5E_PORT_UNKNOWN] = { 352 .subtype = IFM_400G_LR8, /* XXX */ 353 .baudrate = IF_Gbps(400ULL), 354 }, 355 }; 356 357 static const struct if_snd_tag_sw mlx5e_ul_snd_tag_sw = { 358 .snd_tag_query = mlx5e_ul_snd_tag_query, 359 .snd_tag_free = mlx5e_ul_snd_tag_free, 360 .type = IF_SND_TAG_TYPE_UNLIMITED 361 }; 362 363 DEBUGNET_DEFINE(mlx5_en); 364 365 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet"); 366 367 static void 368 mlx5e_update_carrier(struct mlx5e_priv *priv) 369 { 370 struct mlx5_core_dev *mdev = priv->mdev; 371 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 372 u32 eth_proto_oper; 373 int error; 374 u8 i; 375 u8 connector_type; 376 u8 port_state; 377 u8 is_er_type; 378 bool ext; 379 struct media media_entry = {}; 380 381 port_state = mlx5_query_vport_state(mdev, 382 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0); 383 384 if (port_state == VPORT_STATE_UP) { 385 priv->media_status_last |= IFM_ACTIVE; 386 } else { 387 priv->media_status_last &= ~IFM_ACTIVE; 388 priv->media_active_last = IFM_ETHER; 389 if_link_state_change(priv->ifp, LINK_STATE_DOWN); 390 return; 391 } 392 393 error = mlx5_query_port_ptys(mdev, out, sizeof(out), 394 MLX5_PTYS_EN, 1); 395 if (error) { 396 priv->media_active_last = IFM_ETHER; 397 if_setbaudrate(priv->ifp, 1); 398 mlx5_en_err(priv->ifp, "query port ptys failed: 0x%x\n", 399 error); 400 return; 401 } 402 403 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet); 404 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 405 eth_proto_oper); 406 connector_type = MLX5_GET(ptys_reg, out, connector_type); 407 i = ilog2(eth_proto_oper); 408 409 if (ext) { 410 media_entry = mlx5e_ext_mode_table[i][connector_type]; 411 /* check if we should use fallback entry */ 412 if (media_entry.subtype == 0) 413 media_entry = mlx5e_ext_mode_table[i][MLX5E_PORT_UNKNOWN]; 414 } else { 415 media_entry = mlx5e_mode_table[i]; 416 } 417 418 if (media_entry.subtype == 0) { 419 mlx5_en_err(priv->ifp, 420 "Could not find operational media subtype\n"); 421 return; 422 } 423 424 switch (media_entry.subtype) { 425 case IFM_10G_ER: 426 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type); 427 if (error != 0) { 428 mlx5_en_err(priv->ifp, 429 "query port pddr failed: %d\n", error); 430 } 431 if (error != 0 || is_er_type == 0) 432 media_entry.subtype = IFM_10G_LR; 433 break; 434 case IFM_40G_LR4: 435 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type); 436 if (error != 0) { 437 mlx5_en_err(priv->ifp, 438 "query port pddr failed: %d\n", error); 439 } 440 if (error == 0 && is_er_type != 0) 441 media_entry.subtype = IFM_40G_ER4; 442 break; 443 } 444 priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX; 445 if_setbaudrate(priv->ifp, media_entry.baudrate); 446 447 if_link_state_change(priv->ifp, LINK_STATE_UP); 448 } 449 450 static void 451 mlx5e_media_status(if_t dev, struct ifmediareq *ifmr) 452 { 453 struct mlx5e_priv *priv = if_getsoftc(dev); 454 455 ifmr->ifm_status = priv->media_status_last; 456 ifmr->ifm_current = ifmr->ifm_active = priv->media_active_last | 457 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) | 458 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0); 459 460 } 461 462 static u32 463 mlx5e_find_link_mode(u32 subtype, bool ext) 464 { 465 u32 link_mode = 0; 466 467 switch (subtype) { 468 case 0: 469 goto done; 470 case IFM_10G_LR: 471 subtype = IFM_10G_ER; 472 break; 473 case IFM_40G_ER4: 474 subtype = IFM_40G_LR4; 475 break; 476 default: 477 break; 478 } 479 480 if (ext) { 481 for (unsigned i = 0; i != MLX5E_EXT_LINK_SPEEDS_NUMBER; i++) { 482 for (unsigned j = 0; j != MLX5E_CABLE_TYPE_NUMBER; j++) { 483 if (mlx5e_ext_mode_table[i][j].subtype == subtype) 484 link_mode |= MLX5E_PROT_MASK(i); 485 } 486 } 487 } else { 488 for (unsigned i = 0; i != MLX5E_LINK_SPEEDS_NUMBER; i++) { 489 if (mlx5e_mode_table[i].subtype == subtype) 490 link_mode |= MLX5E_PROT_MASK(i); 491 } 492 } 493 done: 494 return (link_mode); 495 } 496 497 static int 498 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv) 499 { 500 return (mlx5_set_port_pause_and_pfc(priv->mdev, 1, 501 priv->params.rx_pauseframe_control, 502 priv->params.tx_pauseframe_control, 503 priv->params.rx_priority_flow_control, 504 priv->params.tx_priority_flow_control)); 505 } 506 507 static int 508 mlx5e_set_port_pfc(struct mlx5e_priv *priv) 509 { 510 int error; 511 512 if (priv->gone != 0) { 513 error = -ENXIO; 514 } else if (priv->params.rx_pauseframe_control || 515 priv->params.tx_pauseframe_control) { 516 mlx5_en_err(priv->ifp, 517 "Global pauseframes must be disabled before enabling PFC.\n"); 518 error = -EINVAL; 519 } else { 520 error = mlx5e_set_port_pause_and_pfc(priv); 521 } 522 return (error); 523 } 524 525 static int 526 mlx5e_media_change(if_t dev) 527 { 528 struct mlx5e_priv *priv = if_getsoftc(dev); 529 struct mlx5_core_dev *mdev = priv->mdev; 530 u32 eth_proto_cap; 531 u32 link_mode; 532 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 533 int was_opened; 534 int locked; 535 int error; 536 bool ext; 537 538 locked = PRIV_LOCKED(priv); 539 if (!locked) 540 PRIV_LOCK(priv); 541 542 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) { 543 error = EINVAL; 544 goto done; 545 } 546 547 error = mlx5_query_port_ptys(mdev, out, sizeof(out), 548 MLX5_PTYS_EN, 1); 549 if (error != 0) { 550 mlx5_en_err(dev, "Query port media capability failed\n"); 551 goto done; 552 } 553 554 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet); 555 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext); 556 557 /* query supported capabilities */ 558 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 559 eth_proto_capability); 560 561 /* check for autoselect */ 562 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) { 563 link_mode = eth_proto_cap; 564 if (link_mode == 0) { 565 mlx5_en_err(dev, "Port media capability is zero\n"); 566 error = EINVAL; 567 goto done; 568 } 569 } else { 570 link_mode = link_mode & eth_proto_cap; 571 if (link_mode == 0) { 572 mlx5_en_err(dev, "Not supported link mode requested\n"); 573 error = EINVAL; 574 goto done; 575 } 576 } 577 if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) { 578 /* check if PFC is enabled */ 579 if (priv->params.rx_priority_flow_control || 580 priv->params.tx_priority_flow_control) { 581 mlx5_en_err(dev, "PFC must be disabled before enabling global pauseframes.\n"); 582 error = EINVAL; 583 goto done; 584 } 585 } 586 /* update pauseframe control bits */ 587 priv->params.rx_pauseframe_control = 588 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0; 589 priv->params.tx_pauseframe_control = 590 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0; 591 592 /* check if device is opened */ 593 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 594 595 /* reconfigure the hardware */ 596 mlx5_set_port_status(mdev, MLX5_PORT_DOWN); 597 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext); 598 error = -mlx5e_set_port_pause_and_pfc(priv); 599 if (was_opened) 600 mlx5_set_port_status(mdev, MLX5_PORT_UP); 601 602 done: 603 if (!locked) 604 PRIV_UNLOCK(priv); 605 return (error); 606 } 607 608 static void 609 mlx5e_update_carrier_work(struct work_struct *work) 610 { 611 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 612 update_carrier_work); 613 614 PRIV_LOCK(priv); 615 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) 616 mlx5e_update_carrier(priv); 617 PRIV_UNLOCK(priv); 618 } 619 620 #define MLX5E_PCIE_PERF_GET_64(a,b,c,d,e,f) \ 621 s_debug->c = MLX5_GET64(mpcnt_reg, out, counter_set.f.c); 622 623 #define MLX5E_PCIE_PERF_GET_32(a,b,c,d,e,f) \ 624 s_debug->c = MLX5_GET(mpcnt_reg, out, counter_set.f.c); 625 626 static void 627 mlx5e_update_pcie_counters(struct mlx5e_priv *priv) 628 { 629 struct mlx5_core_dev *mdev = priv->mdev; 630 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug; 631 const unsigned sz = MLX5_ST_SZ_BYTES(mpcnt_reg); 632 void *out; 633 void *in; 634 int err; 635 636 /* allocate firmware request structures */ 637 in = mlx5_vzalloc(sz); 638 out = mlx5_vzalloc(sz); 639 if (in == NULL || out == NULL) 640 goto free_out; 641 642 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP); 643 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 644 if (err != 0) 645 goto free_out; 646 647 MLX5E_PCIE_PERFORMANCE_COUNTERS_64(MLX5E_PCIE_PERF_GET_64) 648 MLX5E_PCIE_PERFORMANCE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 649 650 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP); 651 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 652 if (err != 0) 653 goto free_out; 654 655 MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 656 657 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_LANE_COUNTERS_GROUP); 658 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 659 if (err != 0) 660 goto free_out; 661 662 MLX5E_PCIE_LANE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 663 664 free_out: 665 /* free firmware request structures */ 666 kvfree(in); 667 kvfree(out); 668 } 669 670 /* 671 * This function reads the physical port counters from the firmware 672 * using a pre-defined layout defined by various MLX5E_PPORT_XXX() 673 * macros. The output is converted from big-endian 64-bit values into 674 * host endian ones and stored in the "priv->stats.pport" structure. 675 */ 676 static void 677 mlx5e_update_pport_counters(struct mlx5e_priv *priv) 678 { 679 struct mlx5_core_dev *mdev = priv->mdev; 680 struct mlx5e_pport_stats *s = &priv->stats.pport; 681 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug; 682 u32 *in; 683 u32 *out; 684 const u64 *ptr; 685 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 686 unsigned x; 687 unsigned y; 688 unsigned z; 689 690 /* allocate firmware request structures */ 691 in = mlx5_vzalloc(sz); 692 out = mlx5_vzalloc(sz); 693 if (in == NULL || out == NULL) 694 goto free_out; 695 696 /* 697 * Get pointer to the 64-bit counter set which is located at a 698 * fixed offset in the output firmware request structure: 699 */ 700 ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set); 701 702 MLX5_SET(ppcnt_reg, in, local_port, 1); 703 704 /* read IEEE802_3 counter group using predefined counter layout */ 705 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP); 706 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 707 for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM; 708 x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++) 709 s->arg[y] = be64toh(ptr[x]); 710 711 /* read RFC2819 counter group using predefined counter layout */ 712 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP); 713 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 714 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++) 715 s->arg[y] = be64toh(ptr[x]); 716 717 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM + 718 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++) 719 s_debug->arg[y] = be64toh(ptr[x]); 720 721 /* read RFC2863 counter group using predefined counter layout */ 722 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP); 723 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 724 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++) 725 s_debug->arg[y] = be64toh(ptr[x]); 726 727 /* read physical layer stats counter group using predefined counter layout */ 728 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP); 729 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 730 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++) 731 s_debug->arg[y] = be64toh(ptr[x]); 732 733 /* read Extended Ethernet counter group using predefined counter layout */ 734 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP); 735 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 736 for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++) 737 s_debug->arg[y] = be64toh(ptr[x]); 738 739 /* read Extended Statistical Group */ 740 if (MLX5_CAP_GEN(mdev, pcam_reg) && 741 MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) && 742 MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) { 743 /* read Extended Statistical counter group using predefined counter layout */ 744 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP); 745 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 746 747 for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++) 748 s_debug->arg[y] = be64toh(ptr[x]); 749 } 750 751 /* read PCIE counters */ 752 mlx5e_update_pcie_counters(priv); 753 754 /* read per-priority counters */ 755 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP); 756 757 /* iterate all the priorities */ 758 for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) { 759 MLX5_SET(ppcnt_reg, in, prio_tc, z); 760 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 761 762 /* read per priority stats counter group using predefined counter layout */ 763 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM / 764 MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++) 765 s->arg[y] = be64toh(ptr[x]); 766 } 767 768 free_out: 769 /* free firmware request structures */ 770 kvfree(in); 771 kvfree(out); 772 } 773 774 static void 775 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv) 776 { 777 u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {}; 778 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {}; 779 780 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard)) 781 return; 782 783 MLX5_SET(query_vnic_env_in, in, opcode, 784 MLX5_CMD_OP_QUERY_VNIC_ENV); 785 MLX5_SET(query_vnic_env_in, in, op_mod, 0); 786 MLX5_SET(query_vnic_env_in, in, other_vport, 0); 787 788 if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0) 789 return; 790 791 priv->stats.vport.rx_steer_missed_packets = 792 MLX5_GET64(query_vnic_env_out, out, 793 vport_env.nic_receive_steering_discard); 794 } 795 796 /* 797 * This function is called regularly to collect all statistics 798 * counters from the firmware. The values can be viewed through the 799 * sysctl interface. Execution is serialized using the priv's global 800 * configuration lock. 801 */ 802 static void 803 mlx5e_update_stats_locked(struct mlx5e_priv *priv) 804 { 805 struct mlx5_core_dev *mdev = priv->mdev; 806 struct mlx5e_vport_stats *s = &priv->stats.vport; 807 struct mlx5e_sq_stats *sq_stats; 808 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)]; 809 u32 *out; 810 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out); 811 u64 tso_packets = 0; 812 u64 tso_bytes = 0; 813 u64 tx_queue_dropped = 0; 814 u64 tx_defragged = 0; 815 u64 tx_offload_none = 0; 816 u64 lro_packets = 0; 817 u64 lro_bytes = 0; 818 u64 sw_lro_queued = 0; 819 u64 sw_lro_flushed = 0; 820 u64 rx_csum_none = 0; 821 u64 rx_wqe_err = 0; 822 u64 rx_packets = 0; 823 u64 rx_bytes = 0; 824 u64 rx_decrypted_error = 0; 825 u64 rx_decrypted_ok = 0; 826 u32 rx_out_of_buffer = 0; 827 int error; 828 int i; 829 int j; 830 831 out = mlx5_vzalloc(outlen); 832 if (out == NULL) 833 goto free_out; 834 835 /* Collect firts the SW counters and then HW for consistency */ 836 for (i = 0; i < priv->params.num_channels; i++) { 837 struct mlx5e_channel *pch = priv->channel + i; 838 struct mlx5e_rq *rq = &pch->rq; 839 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats; 840 841 /* collect stats from LRO */ 842 rq_stats->sw_lro_queued = rq->lro.lro_queued; 843 rq_stats->sw_lro_flushed = rq->lro.lro_flushed; 844 sw_lro_queued += rq_stats->sw_lro_queued; 845 sw_lro_flushed += rq_stats->sw_lro_flushed; 846 lro_packets += rq_stats->lro_packets; 847 lro_bytes += rq_stats->lro_bytes; 848 rx_csum_none += rq_stats->csum_none; 849 rx_wqe_err += rq_stats->wqe_err; 850 rx_packets += rq_stats->packets; 851 rx_bytes += rq_stats->bytes; 852 rx_decrypted_error += rq_stats->decrypted_error_packets; 853 rx_decrypted_ok += rq_stats->decrypted_ok_packets; 854 855 for (j = 0; j < priv->num_tc; j++) { 856 sq_stats = &pch->sq[j].stats; 857 858 tso_packets += sq_stats->tso_packets; 859 tso_bytes += sq_stats->tso_bytes; 860 tx_queue_dropped += sq_stats->dropped; 861 tx_queue_dropped += sq_stats->enobuf; 862 tx_defragged += sq_stats->defragged; 863 tx_offload_none += sq_stats->csum_offload_none; 864 } 865 } 866 867 #ifdef RATELIMIT 868 /* Collect statistics from all rate-limit queues */ 869 for (j = 0; j < priv->rl.param.tx_worker_threads_def; j++) { 870 struct mlx5e_rl_worker *rlw = priv->rl.workers + j; 871 872 for (i = 0; i < priv->rl.param.tx_channels_per_worker_def; i++) { 873 struct mlx5e_rl_channel *channel = rlw->channels + i; 874 struct mlx5e_sq *sq = channel->sq; 875 876 if (sq == NULL) 877 continue; 878 879 sq_stats = &sq->stats; 880 881 tso_packets += sq_stats->tso_packets; 882 tso_bytes += sq_stats->tso_bytes; 883 tx_queue_dropped += sq_stats->dropped; 884 tx_queue_dropped += sq_stats->enobuf; 885 tx_defragged += sq_stats->defragged; 886 tx_offload_none += sq_stats->csum_offload_none; 887 } 888 } 889 #endif 890 891 /* update counters */ 892 s->tso_packets = tso_packets; 893 s->tso_bytes = tso_bytes; 894 s->tx_queue_dropped = tx_queue_dropped; 895 s->tx_defragged = tx_defragged; 896 s->lro_packets = lro_packets; 897 s->lro_bytes = lro_bytes; 898 s->sw_lro_queued = sw_lro_queued; 899 s->sw_lro_flushed = sw_lro_flushed; 900 s->rx_csum_none = rx_csum_none; 901 s->rx_wqe_err = rx_wqe_err; 902 s->rx_packets = rx_packets; 903 s->rx_bytes = rx_bytes; 904 s->rx_decrypted_error_packets = rx_decrypted_error; 905 s->rx_decrypted_ok_packets = rx_decrypted_ok; 906 907 mlx5e_grp_vnic_env_update_stats(priv); 908 909 /* HW counters */ 910 memset(in, 0, sizeof(in)); 911 912 MLX5_SET(query_vport_counter_in, in, opcode, 913 MLX5_CMD_OP_QUERY_VPORT_COUNTER); 914 MLX5_SET(query_vport_counter_in, in, op_mod, 0); 915 MLX5_SET(query_vport_counter_in, in, other_vport, 0); 916 917 memset(out, 0, outlen); 918 919 /* get number of out-of-buffer drops first */ 920 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 && 921 mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id, 922 &rx_out_of_buffer) == 0) { 923 s->rx_out_of_buffer = rx_out_of_buffer; 924 } 925 926 /* get port statistics */ 927 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) { 928 #define MLX5_GET_CTR(out, x) \ 929 MLX5_GET64(query_vport_counter_out, out, x) 930 931 s->rx_error_packets = 932 MLX5_GET_CTR(out, received_errors.packets); 933 s->rx_error_bytes = 934 MLX5_GET_CTR(out, received_errors.octets); 935 s->tx_error_packets = 936 MLX5_GET_CTR(out, transmit_errors.packets); 937 s->tx_error_bytes = 938 MLX5_GET_CTR(out, transmit_errors.octets); 939 940 s->rx_unicast_packets = 941 MLX5_GET_CTR(out, received_eth_unicast.packets); 942 s->rx_unicast_bytes = 943 MLX5_GET_CTR(out, received_eth_unicast.octets); 944 s->tx_unicast_packets = 945 MLX5_GET_CTR(out, transmitted_eth_unicast.packets); 946 s->tx_unicast_bytes = 947 MLX5_GET_CTR(out, transmitted_eth_unicast.octets); 948 949 s->rx_multicast_packets = 950 MLX5_GET_CTR(out, received_eth_multicast.packets); 951 s->rx_multicast_bytes = 952 MLX5_GET_CTR(out, received_eth_multicast.octets); 953 s->tx_multicast_packets = 954 MLX5_GET_CTR(out, transmitted_eth_multicast.packets); 955 s->tx_multicast_bytes = 956 MLX5_GET_CTR(out, transmitted_eth_multicast.octets); 957 958 s->rx_broadcast_packets = 959 MLX5_GET_CTR(out, received_eth_broadcast.packets); 960 s->rx_broadcast_bytes = 961 MLX5_GET_CTR(out, received_eth_broadcast.octets); 962 s->tx_broadcast_packets = 963 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets); 964 s->tx_broadcast_bytes = 965 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets); 966 967 s->tx_packets = s->tx_unicast_packets + 968 s->tx_multicast_packets + s->tx_broadcast_packets; 969 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes + 970 s->tx_broadcast_bytes; 971 972 /* Update calculated offload counters */ 973 s->tx_csum_offload = s->tx_packets - tx_offload_none; 974 s->rx_csum_good = s->rx_packets - s->rx_csum_none; 975 } 976 977 /* Get physical port counters */ 978 mlx5e_update_pport_counters(priv); 979 980 s->tx_jumbo_packets = 981 priv->stats.port_stats_debug.tx_stat_p1519to2047octets + 982 priv->stats.port_stats_debug.tx_stat_p2048to4095octets + 983 priv->stats.port_stats_debug.tx_stat_p4096to8191octets + 984 priv->stats.port_stats_debug.tx_stat_p8192to10239octets; 985 986 free_out: 987 kvfree(out); 988 989 /* Update diagnostics, if any */ 990 if (priv->params_ethtool.diag_pci_enable || 991 priv->params_ethtool.diag_general_enable) { 992 error = mlx5_core_get_diagnostics_full(mdev, 993 priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL, 994 priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL); 995 if (error != 0) 996 mlx5_en_err(priv->ifp, 997 "Failed reading diagnostics: %d\n", error); 998 } 999 1000 /* Update FEC, if any */ 1001 error = mlx5e_fec_update(priv); 1002 if (error != 0 && error != EOPNOTSUPP) { 1003 mlx5_en_err(priv->ifp, 1004 "Updating FEC failed: %d\n", error); 1005 } 1006 1007 /* Update temperature, if any */ 1008 if (priv->params_ethtool.hw_num_temp != 0) { 1009 error = mlx5e_hw_temperature_update(priv); 1010 if (error != 0 && error != EOPNOTSUPP) { 1011 mlx5_en_err(priv->ifp, 1012 "Updating temperature failed: %d\n", error); 1013 } 1014 } 1015 } 1016 1017 static void 1018 mlx5e_update_stats_work(struct work_struct *work) 1019 { 1020 struct mlx5e_priv *priv; 1021 1022 priv = container_of(work, struct mlx5e_priv, update_stats_work); 1023 PRIV_LOCK(priv); 1024 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 && 1025 !test_bit(MLX5_INTERFACE_STATE_TEARDOWN, &priv->mdev->intf_state)) 1026 mlx5e_update_stats_locked(priv); 1027 PRIV_UNLOCK(priv); 1028 } 1029 1030 static void 1031 mlx5e_update_stats(void *arg) 1032 { 1033 struct mlx5e_priv *priv = arg; 1034 1035 queue_work(priv->wq, &priv->update_stats_work); 1036 1037 callout_reset(&priv->watchdog, hz / 4, &mlx5e_update_stats, priv); 1038 } 1039 1040 static void 1041 mlx5e_async_event_sub(struct mlx5e_priv *priv, 1042 enum mlx5_dev_event event) 1043 { 1044 switch (event) { 1045 case MLX5_DEV_EVENT_PORT_UP: 1046 case MLX5_DEV_EVENT_PORT_DOWN: 1047 queue_work(priv->wq, &priv->update_carrier_work); 1048 break; 1049 1050 default: 1051 break; 1052 } 1053 } 1054 1055 static void 1056 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv, 1057 enum mlx5_dev_event event, unsigned long param) 1058 { 1059 struct mlx5e_priv *priv = vpriv; 1060 1061 mtx_lock(&priv->async_events_mtx); 1062 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state)) 1063 mlx5e_async_event_sub(priv, event); 1064 mtx_unlock(&priv->async_events_mtx); 1065 } 1066 1067 static void 1068 mlx5e_enable_async_events(struct mlx5e_priv *priv) 1069 { 1070 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 1071 } 1072 1073 static void 1074 mlx5e_disable_async_events(struct mlx5e_priv *priv) 1075 { 1076 mtx_lock(&priv->async_events_mtx); 1077 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 1078 mtx_unlock(&priv->async_events_mtx); 1079 } 1080 1081 static void mlx5e_calibration_callout(void *arg); 1082 static int mlx5e_calibration_duration = 20; 1083 static int mlx5e_fast_calibration = 1; 1084 static int mlx5e_normal_calibration = 30; 1085 1086 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 1087 "MLX5 timestamp calibration parameters"); 1088 1089 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN, 1090 &mlx5e_calibration_duration, 0, 1091 "Duration of initial calibration"); 1092 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN, 1093 &mlx5e_fast_calibration, 0, 1094 "Recalibration interval during initial calibration"); 1095 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN, 1096 &mlx5e_normal_calibration, 0, 1097 "Recalibration interval during normal operations"); 1098 1099 /* 1100 * Ignites the calibration process. 1101 */ 1102 static void 1103 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv) 1104 { 1105 1106 if (priv->clbr_done == 0) 1107 mlx5e_calibration_callout(priv); 1108 else 1109 callout_reset_sbt_curcpu(&priv->tstmp_clbr, (priv->clbr_done < 1110 mlx5e_calibration_duration ? mlx5e_fast_calibration : 1111 mlx5e_normal_calibration) * SBT_1S, 0, 1112 mlx5e_calibration_callout, priv, C_DIRECT_EXEC); 1113 } 1114 1115 static uint64_t 1116 mlx5e_timespec2usec(const struct timespec *ts) 1117 { 1118 1119 return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec); 1120 } 1121 1122 static uint64_t 1123 mlx5e_hw_clock(struct mlx5e_priv *priv) 1124 { 1125 struct mlx5_init_seg *iseg; 1126 uint32_t hw_h, hw_h1, hw_l; 1127 1128 iseg = priv->mdev->iseg; 1129 do { 1130 hw_h = ioread32be(&iseg->internal_timer_h); 1131 hw_l = ioread32be(&iseg->internal_timer_l); 1132 hw_h1 = ioread32be(&iseg->internal_timer_h); 1133 } while (hw_h1 != hw_h); 1134 return (((uint64_t)hw_h << 32) | hw_l); 1135 } 1136 1137 /* 1138 * The calibration callout, it runs either in the context of the 1139 * thread which enables calibration, or in callout. It takes the 1140 * snapshot of system and adapter clocks, then advances the pointers to 1141 * the calibration point to allow rx path to read the consistent data 1142 * lockless. 1143 */ 1144 static void 1145 mlx5e_calibration_callout(void *arg) 1146 { 1147 struct mlx5e_priv *priv; 1148 struct mlx5e_clbr_point *next, *curr; 1149 struct timespec ts; 1150 int clbr_curr_next; 1151 1152 priv = arg; 1153 curr = &priv->clbr_points[priv->clbr_curr]; 1154 clbr_curr_next = priv->clbr_curr + 1; 1155 if (clbr_curr_next >= nitems(priv->clbr_points)) 1156 clbr_curr_next = 0; 1157 next = &priv->clbr_points[clbr_curr_next]; 1158 1159 next->base_prev = curr->base_curr; 1160 next->clbr_hw_prev = curr->clbr_hw_curr; 1161 1162 next->clbr_hw_curr = mlx5e_hw_clock(priv); 1163 if (((next->clbr_hw_curr - curr->clbr_hw_curr) >> MLX5E_TSTMP_PREC) == 1164 0) { 1165 if (priv->clbr_done != 0) { 1166 mlx5_en_err(priv->ifp, 1167 "HW failed tstmp frozen %#jx %#jx, disabling\n", 1168 next->clbr_hw_curr, curr->clbr_hw_prev); 1169 priv->clbr_done = 0; 1170 } 1171 atomic_store_rel_int(&curr->clbr_gen, 0); 1172 return; 1173 } 1174 1175 nanouptime(&ts); 1176 next->base_curr = mlx5e_timespec2usec(&ts); 1177 1178 curr->clbr_gen = 0; 1179 atomic_thread_fence_rel(); 1180 priv->clbr_curr = clbr_curr_next; 1181 atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen)); 1182 1183 if (priv->clbr_done < mlx5e_calibration_duration) 1184 priv->clbr_done++; 1185 mlx5e_reset_calibration_callout(priv); 1186 } 1187 1188 static const char *mlx5e_rq_stats_desc[] = { 1189 MLX5E_RQ_STATS(MLX5E_STATS_DESC) 1190 }; 1191 1192 static int 1193 mlx5e_create_rq(struct mlx5e_channel *c, 1194 struct mlx5e_rq_param *param, 1195 struct mlx5e_rq *rq) 1196 { 1197 struct mlx5e_priv *priv = c->priv; 1198 struct mlx5_core_dev *mdev = priv->mdev; 1199 char buffer[16]; 1200 void *rqc = param->rqc; 1201 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); 1202 int wq_sz; 1203 int err; 1204 int i; 1205 u32 nsegs, wqe_sz; 1206 1207 err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs); 1208 if (err != 0) 1209 goto done; 1210 1211 /* Create DMA descriptor TAG */ 1212 if ((err = -bus_dma_tag_create( 1213 bus_get_dma_tag(mdev->pdev->dev.bsddev), 1214 1, /* any alignment */ 1215 0, /* no boundary */ 1216 BUS_SPACE_MAXADDR, /* lowaddr */ 1217 BUS_SPACE_MAXADDR, /* highaddr */ 1218 NULL, NULL, /* filter, filterarg */ 1219 nsegs * wqe_sz, /* maxsize */ 1220 nsegs, /* nsegments */ 1221 nsegs * wqe_sz, /* maxsegsize */ 1222 0, /* flags */ 1223 NULL, NULL, /* lockfunc, lockfuncarg */ 1224 &rq->dma_tag))) 1225 goto done; 1226 1227 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, 1228 &rq->wq_ctrl); 1229 if (err) 1230 goto err_free_dma_tag; 1231 1232 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR]; 1233 1234 err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs); 1235 if (err != 0) 1236 goto err_rq_wq_destroy; 1237 1238 wq_sz = mlx5_wq_ll_get_size(&rq->wq); 1239 1240 err = -tcp_lro_init_args(&rq->lro, priv->ifp, TCP_LRO_ENTRIES, wq_sz); 1241 if (err) 1242 goto err_rq_wq_destroy; 1243 1244 rq->mbuf = malloc_domainset(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, 1245 mlx5_dev_domainset(mdev), M_WAITOK | M_ZERO); 1246 for (i = 0; i != wq_sz; i++) { 1247 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i); 1248 int j; 1249 1250 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map); 1251 if (err != 0) { 1252 while (i--) 1253 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 1254 goto err_rq_mbuf_free; 1255 } 1256 1257 /* set value for constant fields */ 1258 for (j = 0; j < rq->nsegs; j++) 1259 wqe->data[j].lkey = cpu_to_be32(priv->mr.key); 1260 } 1261 1262 INIT_WORK(&rq->dim.work, mlx5e_dim_work); 1263 if (priv->params.rx_cq_moderation_mode < 2) { 1264 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 1265 } else { 1266 void *cqc = container_of(param, 1267 struct mlx5e_channel_param, rq)->rx_cq.cqc; 1268 1269 switch (MLX5_GET(cqc, cqc, cq_period_mode)) { 1270 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE: 1271 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; 1272 break; 1273 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE: 1274 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE; 1275 break; 1276 default: 1277 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 1278 break; 1279 } 1280 } 1281 1282 rq->ifp = priv->ifp; 1283 rq->channel = c; 1284 rq->ix = c->ix; 1285 1286 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix); 1287 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 1288 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM, 1289 rq->stats.arg); 1290 return (0); 1291 1292 err_rq_mbuf_free: 1293 free(rq->mbuf, M_MLX5EN); 1294 tcp_lro_free(&rq->lro); 1295 err_rq_wq_destroy: 1296 mlx5_wq_destroy(&rq->wq_ctrl); 1297 err_free_dma_tag: 1298 bus_dma_tag_destroy(rq->dma_tag); 1299 done: 1300 return (err); 1301 } 1302 1303 static void 1304 mlx5e_destroy_rq(struct mlx5e_rq *rq) 1305 { 1306 int wq_sz; 1307 int i; 1308 1309 /* destroy all sysctl nodes */ 1310 sysctl_ctx_free(&rq->stats.ctx); 1311 1312 /* free leftover LRO packets, if any */ 1313 tcp_lro_free(&rq->lro); 1314 1315 wq_sz = mlx5_wq_ll_get_size(&rq->wq); 1316 for (i = 0; i != wq_sz; i++) { 1317 if (rq->mbuf[i].mbuf != NULL) { 1318 if (rq->mbuf[i].ipsec_mtag != NULL) 1319 m_tag_free(&rq->mbuf[i].ipsec_mtag->tag); 1320 bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map); 1321 m_freem(rq->mbuf[i].mbuf); 1322 } 1323 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 1324 } 1325 free(rq->mbuf, M_MLX5EN); 1326 mlx5_wq_destroy(&rq->wq_ctrl); 1327 bus_dma_tag_destroy(rq->dma_tag); 1328 } 1329 1330 static int 1331 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param) 1332 { 1333 struct mlx5e_channel *c = rq->channel; 1334 struct mlx5e_priv *priv = c->priv; 1335 struct mlx5_core_dev *mdev = priv->mdev; 1336 void *in; 1337 void *rqc; 1338 void *wq; 1339 int inlen; 1340 int err; 1341 u8 ts_format; 1342 1343 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 1344 sizeof(u64) * rq->wq_ctrl.buf.npages; 1345 in = mlx5_vzalloc(inlen); 1346 if (in == NULL) 1347 return (-ENOMEM); 1348 1349 ts_format = mlx5_get_rq_default_ts(mdev); 1350 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1351 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1352 1353 memcpy(rqc, param->rqc, sizeof(param->rqc)); 1354 1355 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1356 MLX5_SET(rqc, rqc, ts_format, ts_format); 1357 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1358 if (priv->counter_set_id >= 0) 1359 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id); 1360 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - 1361 MLX5_ADAPTER_PAGE_SHIFT); 1362 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); 1363 1364 mlx5_fill_page_array(&rq->wq_ctrl.buf, 1365 (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 1366 1367 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); 1368 1369 kvfree(in); 1370 1371 return (err); 1372 } 1373 1374 static int 1375 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state) 1376 { 1377 struct mlx5e_channel *c = rq->channel; 1378 struct mlx5e_priv *priv = c->priv; 1379 struct mlx5_core_dev *mdev = priv->mdev; 1380 1381 void *in; 1382 void *rqc; 1383 int inlen; 1384 int err; 1385 1386 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 1387 in = mlx5_vzalloc(inlen); 1388 if (in == NULL) 1389 return (-ENOMEM); 1390 1391 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1392 1393 MLX5_SET(modify_rq_in, in, rqn, rq->rqn); 1394 MLX5_SET(modify_rq_in, in, rq_state, curr_state); 1395 MLX5_SET(rqc, rqc, state, next_state); 1396 1397 err = mlx5_core_modify_rq(mdev, in, inlen); 1398 1399 kvfree(in); 1400 1401 return (err); 1402 } 1403 1404 static void 1405 mlx5e_disable_rq(struct mlx5e_rq *rq) 1406 { 1407 struct mlx5e_channel *c = rq->channel; 1408 struct mlx5e_priv *priv = c->priv; 1409 struct mlx5_core_dev *mdev = priv->mdev; 1410 1411 mlx5_core_destroy_rq(mdev, rq->rqn); 1412 } 1413 1414 static int 1415 mlx5e_open_rq(struct mlx5e_channel *c, 1416 struct mlx5e_rq_param *param, 1417 struct mlx5e_rq *rq) 1418 { 1419 int err; 1420 1421 err = mlx5e_create_rq(c, param, rq); 1422 if (err) 1423 return (err); 1424 1425 /* set CQN in RQ parameters */ 1426 MLX5_SET(rqc, param->rqc, cqn, c->rq.cq.mcq.cqn); 1427 1428 err = mlx5e_enable_rq(rq, param); 1429 if (err) 1430 goto err_destroy_rq; 1431 1432 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 1433 if (err) 1434 goto err_disable_rq; 1435 1436 c->rq.enabled = 1; 1437 1438 return (0); 1439 1440 err_disable_rq: 1441 mlx5e_disable_rq(rq); 1442 err_destroy_rq: 1443 mlx5e_destroy_rq(rq); 1444 1445 return (err); 1446 } 1447 1448 static void 1449 mlx5e_close_rq(struct mlx5e_rq *rq) 1450 { 1451 mtx_lock(&rq->mtx); 1452 rq->enabled = 0; 1453 callout_stop(&rq->watchdog); 1454 mtx_unlock(&rq->mtx); 1455 1456 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 1457 } 1458 1459 static void 1460 mlx5e_close_rq_wait(struct mlx5e_rq *rq) 1461 { 1462 1463 mtx_lock(&rq->mtx); 1464 MPASS(rq->enabled == 0); 1465 while (rq->processing > 0) { 1466 /* 1467 * No wakeup, relying on timeout. 1468 * Use msleep_sbt() since msleep() conflicts with linuxkpi. 1469 */ 1470 msleep_sbt(&rq->processing, &rq->mtx, 0, "mlx5ecrq", 1471 tick_sbt * hz, 0, C_HARDCLOCK); 1472 } 1473 mtx_unlock(&rq->mtx); 1474 mlx5e_disable_rq(rq); 1475 mlx5e_close_cq(&rq->cq); 1476 cancel_work_sync(&rq->dim.work); 1477 mlx5e_destroy_rq(rq); 1478 } 1479 1480 /* 1481 * What is a drop RQ and why is it needed? 1482 * 1483 * The RSS indirection table, also called the RQT, selects the 1484 * destination RQ based on the receive queue number, RQN. The RQT is 1485 * frequently referred to by flow steering rules to distribute traffic 1486 * among multiple RQs. The problem is that the RQs cannot be destroyed 1487 * before the RQT referring them is destroyed too. Further, TLS RX 1488 * rules may still be referring to the RQT even if the link went 1489 * down. Because there is no magic RQN for dropping packets, we create 1490 * a dummy RQ, also called drop RQ, which sole purpose is to drop all 1491 * received packets. When the link goes down this RQN is filled in all 1492 * RQT entries, of the main RQT, so the real RQs which are about to be 1493 * destroyed can be released and the TLS RX rules can be sustained. 1494 */ 1495 static void 1496 mlx5e_open_drop_rq_comp(struct mlx5_core_cq *mcq __unused, struct mlx5_eqe *eqe __unused) 1497 { 1498 } 1499 1500 static int 1501 mlx5e_open_drop_rq(struct mlx5e_priv *priv, 1502 struct mlx5e_rq *drop_rq) 1503 { 1504 struct mlx5e_cq_param param_cq = {}; 1505 struct mlx5e_rq_param param_rq = {}; 1506 void *rqc_wq = MLX5_ADDR_OF(rqc, param_rq.rqc, wq); 1507 int err; 1508 1509 /* set channel pointer */ 1510 drop_rq->channel = priv->channel; 1511 1512 /* set basic CQ parameters needed */ 1513 MLX5_SET(cqc, param_cq.cqc, log_cq_size, 0); 1514 MLX5_SET(cqc, param_cq.cqc, uar_page, priv->mdev->priv.uar->index); 1515 1516 /* open receive completion queue */ 1517 err = mlx5e_open_cq(priv, ¶m_cq, &drop_rq->cq, 1518 &mlx5e_open_drop_rq_comp, 0); 1519 if (err) 1520 goto err_done; 1521 1522 /* set basic WQ parameters needed */ 1523 MLX5_SET(wq, rqc_wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); 1524 MLX5_SET(wq, rqc_wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1525 MLX5_SET(wq, rqc_wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) + sizeof(struct mlx5_wqe_data_seg))); 1526 MLX5_SET(wq, rqc_wq, log_wq_sz, 0); 1527 MLX5_SET(wq, rqc_wq, pd, priv->pdn); 1528 1529 param_rq.wq.linear = 1; 1530 1531 err = mlx5_wq_ll_create(priv->mdev, ¶m_rq.wq, rqc_wq, &drop_rq->wq, 1532 &drop_rq->wq_ctrl); 1533 if (err) 1534 goto err_close_cq; 1535 1536 /* set CQN in RQ parameters */ 1537 MLX5_SET(rqc, param_rq.rqc, cqn, drop_rq->cq.mcq.cqn); 1538 1539 err = mlx5e_enable_rq(drop_rq, ¶m_rq); 1540 if (err) 1541 goto err_wq_destroy; 1542 1543 err = mlx5e_modify_rq(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 1544 if (err) 1545 goto err_disable_rq; 1546 1547 return (err); 1548 1549 err_disable_rq: 1550 mlx5e_disable_rq(drop_rq); 1551 err_wq_destroy: 1552 mlx5_wq_destroy(&drop_rq->wq_ctrl); 1553 err_close_cq: 1554 mlx5e_close_cq(&drop_rq->cq); 1555 err_done: 1556 return (err); 1557 } 1558 1559 static void 1560 mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq) 1561 { 1562 mlx5e_modify_rq(drop_rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 1563 mlx5e_disable_rq(drop_rq); 1564 mlx5_wq_destroy(&drop_rq->wq_ctrl); 1565 mlx5e_close_cq(&drop_rq->cq); 1566 } 1567 1568 void 1569 mlx5e_free_sq_db(struct mlx5e_sq *sq) 1570 { 1571 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1572 int x; 1573 1574 for (x = 0; x != wq_sz; x++) { 1575 if (sq->mbuf[x].mbuf != NULL) { 1576 bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map); 1577 m_freem(sq->mbuf[x].mbuf); 1578 } 1579 if (sq->mbuf[x].mst != NULL) { 1580 m_snd_tag_rele(sq->mbuf[x].mst); 1581 sq->mbuf[x].mst = NULL; 1582 } 1583 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 1584 } 1585 free(sq->mbuf, M_MLX5EN); 1586 } 1587 1588 int 1589 mlx5e_alloc_sq_db(struct mlx5e_sq *sq) 1590 { 1591 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1592 int err; 1593 int x; 1594 1595 sq->mbuf = malloc_domainset(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, 1596 mlx5_dev_domainset(sq->priv->mdev), M_WAITOK | M_ZERO); 1597 1598 /* Create DMA descriptor MAPs */ 1599 for (x = 0; x != wq_sz; x++) { 1600 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map); 1601 if (err != 0) { 1602 while (x--) 1603 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 1604 free(sq->mbuf, M_MLX5EN); 1605 return (err); 1606 } 1607 } 1608 return (0); 1609 } 1610 1611 static const char *mlx5e_sq_stats_desc[] = { 1612 MLX5E_SQ_STATS(MLX5E_STATS_DESC) 1613 }; 1614 1615 void 1616 mlx5e_update_sq_inline(struct mlx5e_sq *sq) 1617 { 1618 sq->max_inline = sq->priv->params.tx_max_inline; 1619 sq->min_inline_mode = sq->priv->params.tx_min_inline_mode; 1620 1621 /* 1622 * Check if trust state is DSCP or if inline mode is NONE which 1623 * indicates CX-5 or newer hardware. 1624 */ 1625 if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP || 1626 sq->min_inline_mode == MLX5_INLINE_MODE_NONE) { 1627 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert)) 1628 sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN; 1629 else 1630 sq->min_insert_caps = MLX5E_INSERT_NON_VLAN; 1631 } else { 1632 sq->min_insert_caps = 0; 1633 } 1634 } 1635 1636 static void 1637 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c) 1638 { 1639 int i; 1640 1641 for (i = 0; i != priv->num_tc; i++) { 1642 mtx_lock(&c->sq[i].lock); 1643 mlx5e_update_sq_inline(&c->sq[i]); 1644 mtx_unlock(&c->sq[i].lock); 1645 } 1646 } 1647 1648 void 1649 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv) 1650 { 1651 int i; 1652 1653 /* check if channels are closed */ 1654 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 1655 return; 1656 1657 for (i = 0; i < priv->params.num_channels; i++) 1658 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]); 1659 } 1660 1661 static int 1662 mlx5e_create_sq(struct mlx5e_channel *c, 1663 int tc, 1664 struct mlx5e_sq_param *param, 1665 struct mlx5e_sq *sq) 1666 { 1667 struct mlx5e_priv *priv = c->priv; 1668 struct mlx5_core_dev *mdev = priv->mdev; 1669 char buffer[16]; 1670 void *sqc = param->sqc; 1671 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq); 1672 int err; 1673 1674 /* Create DMA descriptor TAG */ 1675 if ((err = -bus_dma_tag_create( 1676 bus_get_dma_tag(mdev->pdev->dev.bsddev), 1677 1, /* any alignment */ 1678 0, /* no boundary */ 1679 BUS_SPACE_MAXADDR, /* lowaddr */ 1680 BUS_SPACE_MAXADDR, /* highaddr */ 1681 NULL, NULL, /* filter, filterarg */ 1682 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */ 1683 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */ 1684 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */ 1685 0, /* flags */ 1686 NULL, NULL, /* lockfunc, lockfuncarg */ 1687 &sq->dma_tag))) 1688 goto done; 1689 1690 sq->mkey_be = cpu_to_be32(priv->mr.key); 1691 sq->ifp = priv->ifp; 1692 sq->priv = priv; 1693 sq->tc = tc; 1694 1695 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, 1696 &sq->wq_ctrl); 1697 if (err) 1698 goto err_free_dma_tag; 1699 1700 sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; 1701 1702 err = mlx5e_alloc_sq_db(sq); 1703 if (err) 1704 goto err_sq_wq_destroy; 1705 1706 mlx5e_update_sq_inline(sq); 1707 1708 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc); 1709 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 1710 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM, 1711 sq->stats.arg); 1712 1713 return (0); 1714 1715 err_sq_wq_destroy: 1716 mlx5_wq_destroy(&sq->wq_ctrl); 1717 1718 err_free_dma_tag: 1719 bus_dma_tag_destroy(sq->dma_tag); 1720 done: 1721 return (err); 1722 } 1723 1724 static void 1725 mlx5e_destroy_sq(struct mlx5e_sq *sq) 1726 { 1727 /* destroy all sysctl nodes */ 1728 sysctl_ctx_free(&sq->stats.ctx); 1729 1730 mlx5e_free_sq_db(sq); 1731 mlx5_wq_destroy(&sq->wq_ctrl); 1732 bus_dma_tag_destroy(sq->dma_tag); 1733 } 1734 1735 int 1736 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param, 1737 const struct mlx5_sq_bfreg *bfreg, int tis_num) 1738 { 1739 void *in; 1740 void *sqc; 1741 void *wq; 1742 int inlen; 1743 int err; 1744 u8 ts_format; 1745 1746 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1747 sizeof(u64) * sq->wq_ctrl.buf.npages; 1748 in = mlx5_vzalloc(inlen); 1749 if (in == NULL) 1750 return (-ENOMEM); 1751 1752 sq->uar_map = bfreg->map; 1753 1754 ts_format = mlx5_get_sq_default_ts(sq->priv->mdev); 1755 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1756 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1757 1758 memcpy(sqc, param->sqc, sizeof(param->sqc)); 1759 1760 MLX5_SET(sqc, sqc, tis_num_0, tis_num); 1761 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn); 1762 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1763 MLX5_SET(sqc, sqc, ts_format, ts_format); 1764 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1765 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1766 MLX5_SET(sqc, sqc, allow_swp, 1); 1767 1768 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1769 MLX5_SET(wq, wq, uar_page, bfreg->index); 1770 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift - 1771 MLX5_ADAPTER_PAGE_SHIFT); 1772 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma); 1773 1774 mlx5_fill_page_array(&sq->wq_ctrl.buf, 1775 (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 1776 1777 err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn); 1778 1779 kvfree(in); 1780 1781 return (err); 1782 } 1783 1784 int 1785 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state) 1786 { 1787 void *in; 1788 void *sqc; 1789 int inlen; 1790 int err; 1791 1792 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 1793 in = mlx5_vzalloc(inlen); 1794 if (in == NULL) 1795 return (-ENOMEM); 1796 1797 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1798 1799 MLX5_SET(modify_sq_in, in, sqn, sq->sqn); 1800 MLX5_SET(modify_sq_in, in, sq_state, curr_state); 1801 MLX5_SET(sqc, sqc, state, next_state); 1802 1803 err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen); 1804 1805 kvfree(in); 1806 1807 return (err); 1808 } 1809 1810 void 1811 mlx5e_disable_sq(struct mlx5e_sq *sq) 1812 { 1813 1814 mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn); 1815 } 1816 1817 static int 1818 mlx5e_open_sq(struct mlx5e_channel *c, 1819 int tc, 1820 struct mlx5e_sq_param *param, 1821 struct mlx5e_sq *sq) 1822 { 1823 int err; 1824 1825 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact; 1826 1827 /* ensure the TX completion event factor is not zero */ 1828 if (sq->cev_factor == 0) 1829 sq->cev_factor = 1; 1830 1831 err = mlx5e_create_sq(c, tc, param, sq); 1832 if (err) 1833 return (err); 1834 1835 err = mlx5e_enable_sq(sq, param, &c->bfreg, c->priv->tisn[tc]); 1836 if (err) 1837 goto err_destroy_sq; 1838 1839 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY); 1840 if (err) 1841 goto err_disable_sq; 1842 1843 WRITE_ONCE(sq->running, 1); 1844 1845 return (0); 1846 1847 err_disable_sq: 1848 mlx5e_disable_sq(sq); 1849 err_destroy_sq: 1850 mlx5e_destroy_sq(sq); 1851 1852 return (err); 1853 } 1854 1855 static void 1856 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep) 1857 { 1858 /* fill up remainder with NOPs */ 1859 while (sq->cev_counter != 0) { 1860 while (!mlx5e_sq_has_room_for(sq, 1)) { 1861 if (can_sleep != 0) { 1862 mtx_unlock(&sq->lock); 1863 msleep(4); 1864 mtx_lock(&sq->lock); 1865 } else { 1866 goto done; 1867 } 1868 } 1869 /* send a single NOP */ 1870 mlx5e_send_nop(sq, 1); 1871 atomic_thread_fence_rel(); 1872 } 1873 done: 1874 mlx5e_tx_notify_hw(sq, false); 1875 } 1876 1877 void 1878 mlx5e_sq_cev_timeout(void *arg) 1879 { 1880 struct mlx5e_sq *sq = arg; 1881 1882 mtx_assert(&sq->lock, MA_OWNED); 1883 1884 /* check next state */ 1885 switch (sq->cev_next_state) { 1886 case MLX5E_CEV_STATE_SEND_NOPS: 1887 /* fill TX ring with NOPs, if any */ 1888 mlx5e_sq_send_nops_locked(sq, 0); 1889 1890 /* check if completed */ 1891 if (sq->cev_counter == 0) { 1892 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL; 1893 return; 1894 } 1895 break; 1896 default: 1897 /* send NOPs on next timeout */ 1898 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS; 1899 break; 1900 } 1901 1902 /* restart timer */ 1903 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq); 1904 } 1905 1906 void 1907 mlx5e_drain_sq(struct mlx5e_sq *sq) 1908 { 1909 int error; 1910 struct mlx5_core_dev *mdev= sq->priv->mdev; 1911 1912 /* 1913 * Check if already stopped. 1914 * 1915 * NOTE: Serialization of this function is managed by the 1916 * caller ensuring the priv's state lock is locked or in case 1917 * of rate limit support, a single thread manages drain and 1918 * resume of SQs. The "running" variable can therefore safely 1919 * be read without any locks. 1920 */ 1921 if (READ_ONCE(sq->running) == 0) 1922 return; 1923 1924 /* don't put more packets into the SQ */ 1925 WRITE_ONCE(sq->running, 0); 1926 1927 /* serialize access to DMA rings */ 1928 mtx_lock(&sq->lock); 1929 1930 /* teardown event factor timer, if any */ 1931 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS; 1932 callout_stop(&sq->cev_callout); 1933 1934 /* send dummy NOPs in order to flush the transmit ring */ 1935 mlx5e_sq_send_nops_locked(sq, 1); 1936 mtx_unlock(&sq->lock); 1937 1938 /* wait till SQ is empty or link is down */ 1939 mtx_lock(&sq->lock); 1940 while (sq->cc != sq->pc && 1941 (sq->priv->media_status_last & IFM_ACTIVE) != 0 && 1942 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR && 1943 pci_channel_offline(mdev->pdev) == 0) { 1944 mtx_unlock(&sq->lock); 1945 msleep(1); 1946 sq->cq.mcq.comp(&sq->cq.mcq, NULL); 1947 mtx_lock(&sq->lock); 1948 } 1949 mtx_unlock(&sq->lock); 1950 1951 /* error out remaining requests */ 1952 error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR); 1953 if (error != 0) { 1954 mlx5_en_err(sq->ifp, 1955 "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error); 1956 } 1957 1958 /* wait till SQ is empty */ 1959 mtx_lock(&sq->lock); 1960 while (sq->cc != sq->pc && 1961 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR && 1962 pci_channel_offline(mdev->pdev) == 0) { 1963 mtx_unlock(&sq->lock); 1964 msleep(1); 1965 sq->cq.mcq.comp(&sq->cq.mcq, NULL); 1966 mtx_lock(&sq->lock); 1967 } 1968 mtx_unlock(&sq->lock); 1969 } 1970 1971 static void 1972 mlx5e_close_sq_wait(struct mlx5e_sq *sq) 1973 { 1974 1975 mlx5e_drain_sq(sq); 1976 mlx5e_disable_sq(sq); 1977 mlx5e_destroy_sq(sq); 1978 } 1979 1980 static int 1981 mlx5e_create_cq(struct mlx5e_priv *priv, 1982 struct mlx5e_cq_param *param, 1983 struct mlx5e_cq *cq, 1984 mlx5e_cq_comp_t *comp, 1985 int eq_ix) 1986 { 1987 struct mlx5_core_dev *mdev = priv->mdev; 1988 struct mlx5_core_cq *mcq = &cq->mcq; 1989 int eqn_not_used; 1990 int irqn; 1991 int err; 1992 u32 i; 1993 1994 err = mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn); 1995 if (err) 1996 return (err); 1997 1998 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, 1999 &cq->wq_ctrl); 2000 if (err) 2001 return (err); 2002 2003 mcq->cqe_sz = 64; 2004 mcq->set_ci_db = cq->wq_ctrl.db.db; 2005 mcq->arm_db = cq->wq_ctrl.db.db + 1; 2006 *mcq->set_ci_db = 0; 2007 *mcq->arm_db = 0; 2008 mcq->vector = eq_ix; 2009 mcq->comp = comp; 2010 mcq->event = mlx5e_cq_error_event; 2011 mcq->irqn = irqn; 2012 2013 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { 2014 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); 2015 2016 cqe->op_own = 0xf1; 2017 } 2018 2019 cq->priv = priv; 2020 2021 return (0); 2022 } 2023 2024 static void 2025 mlx5e_destroy_cq(struct mlx5e_cq *cq) 2026 { 2027 mlx5_wq_destroy(&cq->wq_ctrl); 2028 } 2029 2030 static int 2031 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix) 2032 { 2033 struct mlx5_core_cq *mcq = &cq->mcq; 2034 u32 out[MLX5_ST_SZ_DW(create_cq_out)]; 2035 void *in; 2036 void *cqc; 2037 int inlen; 2038 int irqn_not_used; 2039 int eqn; 2040 int err; 2041 2042 inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 2043 sizeof(u64) * cq->wq_ctrl.buf.npages; 2044 in = mlx5_vzalloc(inlen); 2045 if (in == NULL) 2046 return (-ENOMEM); 2047 2048 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); 2049 2050 memcpy(cqc, param->cqc, sizeof(param->cqc)); 2051 2052 mlx5_fill_page_array(&cq->wq_ctrl.buf, 2053 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas)); 2054 2055 mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used); 2056 2057 MLX5_SET(cqc, cqc, c_eqn, eqn); 2058 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - 2059 MLX5_ADAPTER_PAGE_SHIFT); 2060 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); 2061 2062 err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen, out, sizeof(out)); 2063 2064 kvfree(in); 2065 2066 if (err) 2067 return (err); 2068 2069 mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock)); 2070 2071 return (0); 2072 } 2073 2074 static void 2075 mlx5e_disable_cq(struct mlx5e_cq *cq) 2076 { 2077 2078 mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq); 2079 } 2080 2081 int 2082 mlx5e_open_cq(struct mlx5e_priv *priv, 2083 struct mlx5e_cq_param *param, 2084 struct mlx5e_cq *cq, 2085 mlx5e_cq_comp_t *comp, 2086 int eq_ix) 2087 { 2088 int err; 2089 2090 err = mlx5e_create_cq(priv, param, cq, comp, eq_ix); 2091 if (err) 2092 return (err); 2093 2094 err = mlx5e_enable_cq(cq, param, eq_ix); 2095 if (err) 2096 goto err_destroy_cq; 2097 2098 return (0); 2099 2100 err_destroy_cq: 2101 mlx5e_destroy_cq(cq); 2102 2103 return (err); 2104 } 2105 2106 void 2107 mlx5e_close_cq(struct mlx5e_cq *cq) 2108 { 2109 mlx5e_disable_cq(cq); 2110 mlx5e_destroy_cq(cq); 2111 } 2112 2113 static int 2114 mlx5e_open_tx_cqs(struct mlx5e_channel *c, 2115 struct mlx5e_channel_param *cparam) 2116 { 2117 int err; 2118 int tc; 2119 2120 for (tc = 0; tc < c->priv->num_tc; tc++) { 2121 /* open completion queue */ 2122 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq, 2123 &mlx5e_tx_cq_comp, c->ix); 2124 if (err) 2125 goto err_close_tx_cqs; 2126 } 2127 return (0); 2128 2129 err_close_tx_cqs: 2130 for (tc--; tc >= 0; tc--) 2131 mlx5e_close_cq(&c->sq[tc].cq); 2132 2133 return (err); 2134 } 2135 2136 static void 2137 mlx5e_close_tx_cqs(struct mlx5e_channel *c) 2138 { 2139 int tc; 2140 2141 for (tc = 0; tc < c->priv->num_tc; tc++) 2142 mlx5e_close_cq(&c->sq[tc].cq); 2143 } 2144 2145 static int 2146 mlx5e_open_sqs(struct mlx5e_channel *c, 2147 struct mlx5e_channel_param *cparam) 2148 { 2149 int err; 2150 int tc; 2151 2152 for (tc = 0; tc < c->priv->num_tc; tc++) { 2153 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]); 2154 if (err) 2155 goto err_close_sqs; 2156 } 2157 2158 return (0); 2159 2160 err_close_sqs: 2161 for (tc--; tc >= 0; tc--) 2162 mlx5e_close_sq_wait(&c->sq[tc]); 2163 2164 return (err); 2165 } 2166 2167 static void 2168 mlx5e_close_sqs_wait(struct mlx5e_channel *c) 2169 { 2170 int tc; 2171 2172 for (tc = 0; tc < c->priv->num_tc; tc++) 2173 mlx5e_close_sq_wait(&c->sq[tc]); 2174 } 2175 2176 static void 2177 mlx5e_chan_static_init(struct mlx5e_priv *priv, struct mlx5e_channel *c, int ix) 2178 { 2179 int tc; 2180 2181 /* setup priv and channel number */ 2182 c->priv = priv; 2183 c->ix = ix; 2184 2185 /* setup send tag */ 2186 m_snd_tag_init(&c->tag, c->priv->ifp, &mlx5e_ul_snd_tag_sw); 2187 2188 init_completion(&c->completion); 2189 2190 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF); 2191 2192 callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0); 2193 2194 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) { 2195 struct mlx5e_sq *sq = c->sq + tc; 2196 2197 mtx_init(&sq->lock, "mlx5tx", 2198 MTX_NETWORK_LOCK " TX", MTX_DEF); 2199 mtx_init(&sq->comp_lock, "mlx5comp", 2200 MTX_NETWORK_LOCK " TX", MTX_DEF); 2201 2202 callout_init_mtx(&sq->cev_callout, &sq->lock, 0); 2203 } 2204 2205 mlx5e_iq_static_init(&c->iq); 2206 } 2207 2208 static void 2209 mlx5e_chan_wait_for_completion(struct mlx5e_channel *c) 2210 { 2211 2212 m_snd_tag_rele(&c->tag); 2213 wait_for_completion(&c->completion); 2214 } 2215 2216 static void 2217 mlx5e_priv_wait_for_completion(struct mlx5e_priv *priv, const uint32_t channels) 2218 { 2219 uint32_t x; 2220 2221 for (x = 0; x != channels; x++) 2222 mlx5e_chan_wait_for_completion(&priv->channel[x]); 2223 } 2224 2225 static void 2226 mlx5e_chan_static_destroy(struct mlx5e_channel *c) 2227 { 2228 int tc; 2229 2230 callout_drain(&c->rq.watchdog); 2231 2232 mtx_destroy(&c->rq.mtx); 2233 2234 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) { 2235 callout_drain(&c->sq[tc].cev_callout); 2236 mtx_destroy(&c->sq[tc].lock); 2237 mtx_destroy(&c->sq[tc].comp_lock); 2238 } 2239 2240 mlx5e_iq_static_destroy(&c->iq); 2241 } 2242 2243 static int 2244 mlx5e_open_channel(struct mlx5e_priv *priv, 2245 struct mlx5e_channel_param *cparam, 2246 struct mlx5e_channel *c) 2247 { 2248 struct epoch_tracker et; 2249 int i, err; 2250 2251 /* zero non-persistent data */ 2252 MLX5E_ZERO(&c->rq, mlx5e_rq_zero_start); 2253 for (i = 0; i != priv->num_tc; i++) 2254 MLX5E_ZERO(&c->sq[i], mlx5e_sq_zero_start); 2255 MLX5E_ZERO(&c->iq, mlx5e_iq_zero_start); 2256 2257 /* open transmit completion queue */ 2258 err = mlx5e_open_tx_cqs(c, cparam); 2259 if (err) 2260 goto err_free; 2261 2262 /* open receive completion queue */ 2263 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq, 2264 &mlx5e_rx_cq_comp, c->ix); 2265 if (err) 2266 goto err_close_tx_cqs; 2267 2268 err = mlx5e_open_sqs(c, cparam); 2269 if (err) 2270 goto err_close_rx_cq; 2271 2272 err = mlx5e_iq_open(c, &cparam->sq, &cparam->tx_cq, &c->iq); 2273 if (err) 2274 goto err_close_sqs; 2275 2276 err = mlx5e_open_rq(c, &cparam->rq, &c->rq); 2277 if (err) 2278 goto err_close_iq; 2279 2280 /* poll receive queue initially */ 2281 NET_EPOCH_ENTER(et); 2282 c->rq.cq.mcq.comp(&c->rq.cq.mcq, NULL); 2283 NET_EPOCH_EXIT(et); 2284 2285 return (0); 2286 2287 err_close_iq: 2288 mlx5e_iq_close(&c->iq); 2289 2290 err_close_sqs: 2291 mlx5e_close_sqs_wait(c); 2292 2293 err_close_rx_cq: 2294 mlx5e_close_cq(&c->rq.cq); 2295 2296 err_close_tx_cqs: 2297 mlx5e_close_tx_cqs(c); 2298 2299 err_free: 2300 return (err); 2301 } 2302 2303 static void 2304 mlx5e_close_channel(struct mlx5e_channel *c) 2305 { 2306 mlx5e_close_rq(&c->rq); 2307 } 2308 2309 static void 2310 mlx5e_close_channel_wait(struct mlx5e_channel *c) 2311 { 2312 mlx5e_close_rq_wait(&c->rq); 2313 mlx5e_iq_close(&c->iq); 2314 mlx5e_close_sqs_wait(c); 2315 mlx5e_close_tx_cqs(c); 2316 } 2317 2318 static int 2319 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs) 2320 { 2321 u32 r, n, maxs; 2322 2323 maxs = priv->params.hw_lro_en ? priv->params.lro_wqe_sz : 2324 MLX5E_SW2MB_MTU(if_getmtu(priv->ifp)); 2325 r = maxs > MCLBYTES ? MJUMPAGESIZE : MCLBYTES; 2326 2327 /* 2328 * n + 1 must be a power of two, because stride size must be. 2329 * Stride size is 16 * (n + 1), as the first segment is 2330 * control. 2331 */ 2332 n = roundup_pow_of_two(1 + howmany(maxs, r)) - 1; 2333 if (n > MLX5E_MAX_BUSDMA_RX_SEGS) 2334 return (-ENOMEM); 2335 2336 *wqe_sz = r; 2337 *nsegs = n; 2338 return (0); 2339 } 2340 2341 static void 2342 mlx5e_build_rq_param(struct mlx5e_priv *priv, 2343 struct mlx5e_rq_param *param) 2344 { 2345 void *rqc = param->rqc; 2346 void *wq = MLX5_ADDR_OF(rqc, rqc, wq); 2347 u32 wqe_sz, nsegs; 2348 2349 mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs); 2350 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); 2351 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 2352 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) + 2353 nsegs * sizeof(struct mlx5_wqe_data_seg))); 2354 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size); 2355 MLX5_SET(wq, wq, pd, priv->pdn); 2356 2357 param->wq.linear = 1; 2358 } 2359 2360 static void 2361 mlx5e_build_sq_param(struct mlx5e_priv *priv, 2362 struct mlx5e_sq_param *param) 2363 { 2364 void *sqc = param->sqc; 2365 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 2366 2367 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size); 2368 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 2369 MLX5_SET(wq, wq, pd, priv->pdn); 2370 2371 param->wq.linear = 1; 2372 } 2373 2374 static void 2375 mlx5e_build_common_cq_param(struct mlx5e_priv *priv, 2376 struct mlx5e_cq_param *param) 2377 { 2378 void *cqc = param->cqc; 2379 2380 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index); 2381 } 2382 2383 static void 2384 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr) 2385 { 2386 2387 *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE); 2388 2389 /* apply LRO restrictions */ 2390 if (priv->params.hw_lro_en && 2391 ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) { 2392 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO; 2393 } 2394 } 2395 2396 static void 2397 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, 2398 struct mlx5e_cq_param *param) 2399 { 2400 struct net_dim_cq_moder curr; 2401 void *cqc = param->cqc; 2402 2403 /* 2404 * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE 2405 * format is more beneficial for FreeBSD use case. 2406 * 2407 * Adding support for MLX5_CQE_FORMAT_CSUM will require changes 2408 * in mlx5e_decompress_cqe. 2409 */ 2410 if (priv->params.cqe_zipping_en) { 2411 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH); 2412 MLX5_SET(cqc, cqc, cqe_compression_en, 1); 2413 } 2414 2415 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size); 2416 2417 switch (priv->params.rx_cq_moderation_mode) { 2418 case 0: 2419 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec); 2420 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts); 2421 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2422 break; 2423 case 1: 2424 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec); 2425 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts); 2426 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2427 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2428 else 2429 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2430 break; 2431 case 2: 2432 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr); 2433 MLX5_SET(cqc, cqc, cq_period, curr.usec); 2434 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts); 2435 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2436 break; 2437 case 3: 2438 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr); 2439 MLX5_SET(cqc, cqc, cq_period, curr.usec); 2440 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts); 2441 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2442 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2443 else 2444 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2445 break; 2446 default: 2447 break; 2448 } 2449 2450 mlx5e_dim_build_cq_param(priv, param); 2451 2452 mlx5e_build_common_cq_param(priv, param); 2453 } 2454 2455 static void 2456 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv, 2457 struct mlx5e_cq_param *param) 2458 { 2459 void *cqc = param->cqc; 2460 2461 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size); 2462 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec); 2463 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts); 2464 2465 switch (priv->params.tx_cq_moderation_mode) { 2466 case 0: 2467 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2468 break; 2469 default: 2470 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2471 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2472 else 2473 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2474 break; 2475 } 2476 2477 mlx5e_build_common_cq_param(priv, param); 2478 } 2479 2480 static void 2481 mlx5e_build_channel_param(struct mlx5e_priv *priv, 2482 struct mlx5e_channel_param *cparam) 2483 { 2484 memset(cparam, 0, sizeof(*cparam)); 2485 2486 mlx5e_build_rq_param(priv, &cparam->rq); 2487 mlx5e_build_sq_param(priv, &cparam->sq); 2488 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq); 2489 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq); 2490 } 2491 2492 static int 2493 mlx5e_open_channels(struct mlx5e_priv *priv) 2494 { 2495 struct mlx5e_channel_param *cparam; 2496 int err; 2497 int i; 2498 2499 cparam = malloc(sizeof(*cparam), M_MLX5EN, M_WAITOK); 2500 2501 mlx5e_build_channel_param(priv, cparam); 2502 for (i = 0; i < priv->params.num_channels; i++) { 2503 err = mlx5e_open_channel(priv, cparam, &priv->channel[i]); 2504 if (err) 2505 goto err_close_channels; 2506 2507 /* Bind interrupt vectors, if any. */ 2508 if (priv->params_ethtool.irq_cpu_base > -1) { 2509 cpuset_t cpuset; 2510 int cpu; 2511 int irq; 2512 int eqn; 2513 int nirq; 2514 2515 err = mlx5_vector2eqn(priv->mdev, i, 2516 &eqn, &nirq); 2517 2518 /* error here is non-fatal */ 2519 if (err != 0) 2520 continue; 2521 2522 irq = priv->mdev->priv.msix_arr[nirq].vector; 2523 cpu = (unsigned)(priv->params_ethtool.irq_cpu_base + 2524 i * priv->params_ethtool.irq_cpu_stride) % (unsigned)mp_ncpus; 2525 2526 CPU_ZERO(&cpuset); 2527 CPU_SET(cpu, &cpuset); 2528 intr_setaffinity(irq, CPU_WHICH_INTRHANDLER, &cpuset); 2529 } 2530 } 2531 free(cparam, M_MLX5EN); 2532 return (0); 2533 2534 err_close_channels: 2535 while (i--) { 2536 mlx5e_close_channel(&priv->channel[i]); 2537 mlx5e_close_channel_wait(&priv->channel[i]); 2538 } 2539 free(cparam, M_MLX5EN); 2540 return (err); 2541 } 2542 2543 static void 2544 mlx5e_close_channels(struct mlx5e_priv *priv) 2545 { 2546 int i; 2547 2548 for (i = 0; i < priv->params.num_channels; i++) 2549 mlx5e_close_channel(&priv->channel[i]); 2550 for (i = 0; i < priv->params.num_channels; i++) 2551 mlx5e_close_channel_wait(&priv->channel[i]); 2552 } 2553 2554 static int 2555 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq) 2556 { 2557 2558 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) { 2559 uint8_t cq_mode; 2560 2561 switch (priv->params.tx_cq_moderation_mode) { 2562 case 0: 2563 case 2: 2564 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 2565 break; 2566 default: 2567 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE; 2568 break; 2569 } 2570 2571 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq, 2572 priv->params.tx_cq_moderation_usec, 2573 priv->params.tx_cq_moderation_pkts, 2574 cq_mode)); 2575 } 2576 2577 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq, 2578 priv->params.tx_cq_moderation_usec, 2579 priv->params.tx_cq_moderation_pkts)); 2580 } 2581 2582 static int 2583 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq) 2584 { 2585 2586 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) { 2587 uint8_t cq_mode; 2588 uint8_t dim_mode; 2589 int retval; 2590 2591 switch (priv->params.rx_cq_moderation_mode) { 2592 case 0: 2593 case 2: 2594 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 2595 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; 2596 break; 2597 default: 2598 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE; 2599 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE; 2600 break; 2601 } 2602 2603 /* tear down dynamic interrupt moderation */ 2604 mtx_lock(&rq->mtx); 2605 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 2606 mtx_unlock(&rq->mtx); 2607 2608 /* wait for dynamic interrupt moderation work task, if any */ 2609 cancel_work_sync(&rq->dim.work); 2610 2611 if (priv->params.rx_cq_moderation_mode >= 2) { 2612 struct net_dim_cq_moder curr; 2613 2614 mlx5e_get_default_profile(priv, dim_mode, &curr); 2615 2616 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq, 2617 curr.usec, curr.pkts, cq_mode); 2618 2619 /* set dynamic interrupt moderation mode and zero defaults */ 2620 mtx_lock(&rq->mtx); 2621 rq->dim.mode = dim_mode; 2622 rq->dim.state = 0; 2623 rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE; 2624 mtx_unlock(&rq->mtx); 2625 } else { 2626 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq, 2627 priv->params.rx_cq_moderation_usec, 2628 priv->params.rx_cq_moderation_pkts, 2629 cq_mode); 2630 } 2631 return (retval); 2632 } 2633 2634 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq, 2635 priv->params.rx_cq_moderation_usec, 2636 priv->params.rx_cq_moderation_pkts)); 2637 } 2638 2639 static int 2640 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c) 2641 { 2642 int err; 2643 int i; 2644 2645 err = mlx5e_refresh_rq_params(priv, &c->rq); 2646 if (err) 2647 goto done; 2648 2649 for (i = 0; i != priv->num_tc; i++) { 2650 err = mlx5e_refresh_sq_params(priv, &c->sq[i]); 2651 if (err) 2652 goto done; 2653 } 2654 done: 2655 return (err); 2656 } 2657 2658 int 2659 mlx5e_refresh_channel_params(struct mlx5e_priv *priv) 2660 { 2661 int i; 2662 2663 /* check if channels are closed */ 2664 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 2665 return (EINVAL); 2666 2667 for (i = 0; i < priv->params.num_channels; i++) { 2668 int err; 2669 2670 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]); 2671 if (err) 2672 return (err); 2673 } 2674 return (0); 2675 } 2676 2677 static int 2678 mlx5e_open_tis(struct mlx5e_priv *priv, int tc) 2679 { 2680 struct mlx5_core_dev *mdev = priv->mdev; 2681 u32 in[MLX5_ST_SZ_DW(create_tis_in)]; 2682 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 2683 2684 memset(in, 0, sizeof(in)); 2685 2686 MLX5_SET(tisc, tisc, prio, tc); 2687 MLX5_SET(tisc, tisc, transport_domain, priv->tdn); 2688 2689 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc])); 2690 } 2691 2692 static void 2693 mlx5e_close_tis(struct mlx5e_priv *priv, int tc) 2694 { 2695 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc], 0); 2696 } 2697 2698 static int 2699 mlx5e_open_tises(struct mlx5e_priv *priv) 2700 { 2701 int num_tc = priv->num_tc; 2702 int err; 2703 int tc; 2704 2705 for (tc = 0; tc < num_tc; tc++) { 2706 err = mlx5e_open_tis(priv, tc); 2707 if (err) 2708 goto err_close_tises; 2709 } 2710 2711 return (0); 2712 2713 err_close_tises: 2714 for (tc--; tc >= 0; tc--) 2715 mlx5e_close_tis(priv, tc); 2716 2717 return (err); 2718 } 2719 2720 static void 2721 mlx5e_close_tises(struct mlx5e_priv *priv) 2722 { 2723 int num_tc = priv->num_tc; 2724 int tc; 2725 2726 for (tc = 0; tc < num_tc; tc++) 2727 mlx5e_close_tis(priv, tc); 2728 } 2729 2730 static int 2731 mlx5e_open_default_rqt(struct mlx5e_priv *priv, u32 *prqtn, int sz) 2732 { 2733 u32 *in; 2734 void *rqtc; 2735 int inlen; 2736 int err; 2737 int i; 2738 2739 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 2740 in = mlx5_vzalloc(inlen); 2741 if (in == NULL) 2742 return (-ENOMEM); 2743 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 2744 2745 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 2746 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 2747 2748 for (i = 0; i != sz; i++) 2749 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn); 2750 2751 err = mlx5_core_create_rqt(priv->mdev, in, inlen, prqtn); 2752 kvfree(in); 2753 2754 return (err); 2755 } 2756 2757 static int 2758 mlx5e_open_rqts(struct mlx5e_priv *priv) 2759 { 2760 int err; 2761 int i; 2762 2763 err = mlx5e_open_default_rqt(priv, &priv->rqtn, 2764 1 << priv->params.rx_hash_log_tbl_sz); 2765 if (err) 2766 goto err_default; 2767 2768 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) { 2769 err = mlx5e_open_default_rqt(priv, &priv->channel[i].rqtn, 1); 2770 if (err) 2771 goto err_channel; 2772 } 2773 return (0); 2774 2775 err_channel: 2776 while (i--) 2777 mlx5_core_destroy_rqt(priv->mdev, priv->channel[i].rqtn, 0); 2778 2779 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn, 0); 2780 2781 err_default: 2782 return (err); 2783 } 2784 2785 static void 2786 mlx5e_close_rqts(struct mlx5e_priv *priv) 2787 { 2788 int i; 2789 2790 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) 2791 mlx5_core_destroy_rqt(priv->mdev, priv->channel[i].rqtn, 0); 2792 2793 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn, 0); 2794 } 2795 2796 static int 2797 mlx5e_activate_rqt(struct mlx5e_priv *priv) 2798 { 2799 u32 *in; 2800 void *rqtc; 2801 int inlen; 2802 int err; 2803 int sz; 2804 int i; 2805 2806 sz = 1 << priv->params.rx_hash_log_tbl_sz; 2807 2808 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz; 2809 in = mlx5_vzalloc(inlen); 2810 if (in == NULL) 2811 return (-ENOMEM); 2812 2813 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx); 2814 2815 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 2816 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1); 2817 2818 for (i = 0; i != sz; i++) { 2819 int ix; 2820 #ifdef RSS 2821 ix = rss_get_indirection_to_bucket(i); 2822 #else 2823 ix = i; 2824 #endif 2825 /* ensure we don't overflow */ 2826 ix %= priv->params.num_channels; 2827 2828 /* apply receive side scaling stride, if any */ 2829 ix -= ix % (int)priv->params.channels_rsss; 2830 2831 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn); 2832 } 2833 2834 err = mlx5_core_modify_rqt(priv->mdev, priv->rqtn, in, inlen); 2835 if (err) 2836 goto err_modify; 2837 2838 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32); 2839 2840 MLX5_SET(rqtc, rqtc, rqt_actual_size, 1); 2841 2842 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) { 2843 int ix; 2844 #ifdef RSS 2845 ix = rss_get_indirection_to_bucket(i); 2846 #else 2847 ix = i; 2848 #endif 2849 /* ensure we don't overflow */ 2850 ix %= priv->params.num_channels; 2851 2852 /* apply receive side scaling stride, if any */ 2853 ix -= ix % (int)priv->params.channels_rsss; 2854 2855 MLX5_SET(rqtc, rqtc, rq_num[0], priv->channel[ix].rq.rqn); 2856 2857 err = mlx5_core_modify_rqt(priv->mdev, priv->channel[i].rqtn, in, inlen); 2858 if (err) 2859 goto err_modify; 2860 } 2861 2862 err_modify: 2863 kvfree(in); 2864 return (err); 2865 } 2866 2867 static int 2868 mlx5e_deactivate_rqt(struct mlx5e_priv *priv) 2869 { 2870 u32 *in; 2871 void *rqtc; 2872 int inlen; 2873 int err; 2874 int sz; 2875 int i; 2876 2877 sz = 1 << priv->params.rx_hash_log_tbl_sz; 2878 2879 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz; 2880 in = mlx5_vzalloc(inlen); 2881 if (in == NULL) 2882 return (-ENOMEM); 2883 2884 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx); 2885 2886 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 2887 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1); 2888 2889 for (i = 0; i != sz; i++) 2890 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn); 2891 2892 err = mlx5_core_modify_rqt(priv->mdev, priv->rqtn, in, inlen); 2893 if (err) 2894 goto err_modify; 2895 2896 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32); 2897 2898 MLX5_SET(rqtc, rqtc, rqt_actual_size, 1); 2899 2900 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) { 2901 MLX5_SET(rqtc, rqtc, rq_num[0], priv->drop_rq.rqn); 2902 2903 err = mlx5_core_modify_rqt(priv->mdev, priv->channel[i].rqtn, in, inlen); 2904 if (err) 2905 goto err_modify; 2906 } 2907 2908 err_modify: 2909 kvfree(in); 2910 return (err); 2911 } 2912 2913 #define MLX5E_RSS_KEY_SIZE (10 * 4) /* bytes */ 2914 2915 static void 2916 mlx5e_get_rss_key(void *key_ptr) 2917 { 2918 #ifdef RSS 2919 rss_getkey(key_ptr); 2920 #else 2921 static const u32 rsskey[] = { 2922 cpu_to_be32(0xD181C62C), 2923 cpu_to_be32(0xF7F4DB5B), 2924 cpu_to_be32(0x1983A2FC), 2925 cpu_to_be32(0x943E1ADB), 2926 cpu_to_be32(0xD9389E6B), 2927 cpu_to_be32(0xD1039C2C), 2928 cpu_to_be32(0xA74499AD), 2929 cpu_to_be32(0x593D56D9), 2930 cpu_to_be32(0xF3253C06), 2931 cpu_to_be32(0x2ADC1FFC), 2932 }; 2933 CTASSERT(sizeof(rsskey) == MLX5E_RSS_KEY_SIZE); 2934 memcpy(key_ptr, rsskey, MLX5E_RSS_KEY_SIZE); 2935 #endif 2936 } 2937 2938 static void 2939 mlx5e_hw_lro_set_tir_ctx_lro_max_msg_sz(struct mlx5e_priv *priv, u32 *tirc) 2940 { 2941 MLX5_SET(tirc, tirc, lro_max_msg_sz, (priv->params.lro_wqe_sz >> 8) - 2942 (MLX5_CAP_ETH(priv->mdev, lro_max_msg_sz_mode) == 0 ? 1 : 0)); 2943 } 2944 2945 static void 2946 mlx5e_hw_lro_set_tir_ctx(struct mlx5e_priv *priv, u32 *tirc) 2947 { 2948 MLX5_SET(tirc, tirc, lro_enable_mask, 2949 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | 2950 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO); 2951 /* TODO: add the option to choose timer value dynamically */ 2952 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, 2953 MLX5_CAP_ETH(priv->mdev, lro_timer_supported_periods[2])); 2954 mlx5e_hw_lro_set_tir_ctx_lro_max_msg_sz(priv, tirc); 2955 } 2956 2957 static int 2958 mlx5e_hw_lro_update_tir(struct mlx5e_priv *priv, int tt, bool inner_vxlan) 2959 { 2960 struct mlx5_core_dev *mdev = priv->mdev; 2961 u32 *in; 2962 void *tirc; 2963 int inlen; 2964 int err; 2965 2966 inlen = MLX5_ST_SZ_BYTES(modify_tir_in); 2967 in = mlx5_vzalloc(inlen); 2968 if (in == NULL) 2969 return (-ENOMEM); 2970 tirc = MLX5_ADDR_OF(modify_tir_in, in, tir_context); 2971 2972 /* fill the command part */ 2973 MLX5_SET(modify_tir_in, in, tirn, inner_vxlan ? 2974 priv->tirn_inner_vxlan[tt] : priv->tirn[tt]); 2975 MLX5_SET64(modify_tir_in, in, modify_bitmask, 2976 (1 << MLX5_MODIFY_TIR_BITMASK_LRO)); 2977 2978 /* fill the context */ 2979 if (priv->params.hw_lro_en) 2980 mlx5e_hw_lro_set_tir_ctx(priv, tirc); 2981 2982 err = mlx5_core_modify_tir(mdev, in, inlen); 2983 2984 kvfree(in); 2985 return (err); 2986 } 2987 2988 int 2989 mlx5e_hw_lro_update_tirs(struct mlx5e_priv *priv) 2990 { 2991 int err, err1, i; 2992 2993 err = 0; 2994 for (i = 0; i != 2 * MLX5E_NUM_TT; i++) { 2995 err1 = mlx5e_hw_lro_update_tir(priv, i / 2, (i % 2) ? true : 2996 false); 2997 if (err1 != 0 && err == 0) 2998 err = err1; 2999 } 3000 return (-err); 3001 } 3002 3003 static void 3004 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt, bool inner_vxlan) 3005 { 3006 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 3007 void *hfsi = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 3008 void *hfs = inner_vxlan ? hfsi : hfso; 3009 __be32 *hkey; 3010 3011 MLX5_SET(tirc, tirc, transport_domain, priv->tdn); 3012 3013 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\ 3014 MLX5_HASH_FIELD_SEL_DST_IP) 3015 3016 #define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\ 3017 MLX5_HASH_FIELD_SEL_DST_IP |\ 3018 MLX5_HASH_FIELD_SEL_L4_SPORT |\ 3019 MLX5_HASH_FIELD_SEL_L4_DPORT) 3020 3021 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\ 3022 MLX5_HASH_FIELD_SEL_DST_IP |\ 3023 MLX5_HASH_FIELD_SEL_IPSEC_SPI) 3024 3025 if (priv->params.hw_lro_en) 3026 mlx5e_hw_lro_set_tir_ctx(priv, tirc); 3027 3028 if (inner_vxlan) 3029 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 3030 3031 /* 3032 * All packets must go through the indirection table, RQT, 3033 * because it is not possible to modify the RQN of the TIR 3034 * for direct dispatchment after it is created, typically 3035 * when the link goes up and down. 3036 */ 3037 MLX5_SET(tirc, tirc, disp_type, 3038 MLX5_TIRC_DISP_TYPE_INDIRECT); 3039 MLX5_SET(tirc, tirc, indirect_table, 3040 priv->rqtn); 3041 MLX5_SET(tirc, tirc, rx_hash_fn, 3042 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ); 3043 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 3044 3045 CTASSERT(MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key) >= 3046 MLX5E_RSS_KEY_SIZE); 3047 #ifdef RSS 3048 /* 3049 * The FreeBSD RSS implementation does currently not 3050 * support symmetric Toeplitz hashes: 3051 */ 3052 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0); 3053 #else 3054 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 3055 #endif 3056 mlx5e_get_rss_key(hkey); 3057 3058 switch (tt) { 3059 case MLX5E_TT_IPV4_TCP: 3060 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3061 MLX5_L3_PROT_TYPE_IPV4); 3062 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type, 3063 MLX5_L4_PROT_TYPE_TCP); 3064 #ifdef RSS 3065 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) { 3066 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3067 MLX5_HASH_IP); 3068 } else 3069 #endif 3070 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3071 MLX5_HASH_ALL); 3072 break; 3073 3074 case MLX5E_TT_IPV6_TCP: 3075 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3076 MLX5_L3_PROT_TYPE_IPV6); 3077 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type, 3078 MLX5_L4_PROT_TYPE_TCP); 3079 #ifdef RSS 3080 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) { 3081 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3082 MLX5_HASH_IP); 3083 } else 3084 #endif 3085 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3086 MLX5_HASH_ALL); 3087 break; 3088 3089 case MLX5E_TT_IPV4_UDP: 3090 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3091 MLX5_L3_PROT_TYPE_IPV4); 3092 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type, 3093 MLX5_L4_PROT_TYPE_UDP); 3094 #ifdef RSS 3095 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) { 3096 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3097 MLX5_HASH_IP); 3098 } else 3099 #endif 3100 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3101 MLX5_HASH_ALL); 3102 break; 3103 3104 case MLX5E_TT_IPV6_UDP: 3105 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3106 MLX5_L3_PROT_TYPE_IPV6); 3107 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type, 3108 MLX5_L4_PROT_TYPE_UDP); 3109 #ifdef RSS 3110 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) { 3111 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3112 MLX5_HASH_IP); 3113 } else 3114 #endif 3115 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3116 MLX5_HASH_ALL); 3117 break; 3118 3119 case MLX5E_TT_IPV4_IPSEC_AH: 3120 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3121 MLX5_L3_PROT_TYPE_IPV4); 3122 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3123 MLX5_HASH_IP_IPSEC_SPI); 3124 break; 3125 3126 case MLX5E_TT_IPV6_IPSEC_AH: 3127 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3128 MLX5_L3_PROT_TYPE_IPV6); 3129 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3130 MLX5_HASH_IP_IPSEC_SPI); 3131 break; 3132 3133 case MLX5E_TT_IPV4_IPSEC_ESP: 3134 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3135 MLX5_L3_PROT_TYPE_IPV4); 3136 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3137 MLX5_HASH_IP_IPSEC_SPI); 3138 break; 3139 3140 case MLX5E_TT_IPV6_IPSEC_ESP: 3141 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3142 MLX5_L3_PROT_TYPE_IPV6); 3143 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3144 MLX5_HASH_IP_IPSEC_SPI); 3145 break; 3146 3147 case MLX5E_TT_IPV4: 3148 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3149 MLX5_L3_PROT_TYPE_IPV4); 3150 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3151 MLX5_HASH_IP); 3152 break; 3153 3154 case MLX5E_TT_IPV6: 3155 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3156 MLX5_L3_PROT_TYPE_IPV6); 3157 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3158 MLX5_HASH_IP); 3159 break; 3160 3161 default: 3162 break; 3163 } 3164 } 3165 3166 static int 3167 mlx5e_open_tir(struct mlx5e_priv *priv, int tt, bool inner_vxlan) 3168 { 3169 struct mlx5_core_dev *mdev = priv->mdev; 3170 u32 *in; 3171 void *tirc; 3172 int inlen; 3173 int err; 3174 3175 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 3176 in = mlx5_vzalloc(inlen); 3177 if (in == NULL) 3178 return (-ENOMEM); 3179 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context); 3180 3181 mlx5e_build_tir_ctx(priv, tirc, tt, inner_vxlan); 3182 3183 err = mlx5_core_create_tir(mdev, in, inlen, inner_vxlan ? 3184 &priv->tirn_inner_vxlan[tt] : &priv->tirn[tt]); 3185 3186 kvfree(in); 3187 3188 return (err); 3189 } 3190 3191 static void 3192 mlx5e_close_tir(struct mlx5e_priv *priv, int tt, bool inner_vxlan) 3193 { 3194 mlx5_core_destroy_tir(priv->mdev, inner_vxlan ? 3195 priv->tirn_inner_vxlan[tt] : priv->tirn[tt], 0); 3196 } 3197 3198 static int 3199 mlx5e_open_tirs(struct mlx5e_priv *priv) 3200 { 3201 int err; 3202 int i; 3203 3204 for (i = 0; i != 2 * MLX5E_NUM_TT; i++) { 3205 err = mlx5e_open_tir(priv, i / 2, (i % 2) ? true : false); 3206 if (err) 3207 goto err_close_tirs; 3208 } 3209 3210 return (0); 3211 3212 err_close_tirs: 3213 for (i--; i >= 0; i--) 3214 mlx5e_close_tir(priv, i / 2, (i % 2) ? true : false); 3215 3216 return (err); 3217 } 3218 3219 static void 3220 mlx5e_close_tirs(struct mlx5e_priv *priv) 3221 { 3222 int i; 3223 3224 for (i = 0; i != 2 * MLX5E_NUM_TT; i++) 3225 mlx5e_close_tir(priv, i / 2, (i % 2) ? true : false); 3226 } 3227 3228 /* 3229 * SW MTU does not include headers, 3230 * HW MTU includes all headers and checksums. 3231 */ 3232 static int 3233 mlx5e_set_dev_port_mtu(if_t ifp, int sw_mtu) 3234 { 3235 struct mlx5e_priv *priv = if_getsoftc(ifp); 3236 struct mlx5_core_dev *mdev = priv->mdev; 3237 int hw_mtu; 3238 int err; 3239 3240 hw_mtu = MLX5E_SW2HW_MTU(sw_mtu); 3241 3242 err = mlx5_set_port_mtu(mdev, hw_mtu); 3243 if (err) { 3244 mlx5_en_err(ifp, "mlx5_set_port_mtu failed setting %d, err=%d\n", 3245 sw_mtu, err); 3246 return (err); 3247 } 3248 3249 /* Update vport context MTU */ 3250 err = mlx5_set_vport_mtu(mdev, hw_mtu); 3251 if (err) { 3252 mlx5_en_err(ifp, 3253 "Failed updating vport context with MTU size, err=%d\n", 3254 err); 3255 } 3256 3257 if_setmtu(ifp, sw_mtu); 3258 3259 err = mlx5_query_vport_mtu(mdev, &hw_mtu); 3260 if (err || !hw_mtu) { 3261 /* fallback to port oper mtu */ 3262 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu); 3263 } 3264 if (err) { 3265 mlx5_en_err(ifp, 3266 "Query port MTU, after setting new MTU value, failed\n"); 3267 return (err); 3268 } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) { 3269 err = -E2BIG, 3270 mlx5_en_err(ifp, 3271 "Port MTU %d is smaller than ifp mtu %d\n", 3272 hw_mtu, sw_mtu); 3273 } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) { 3274 err = -EINVAL; 3275 mlx5_en_err(ifp, 3276 "Port MTU %d is bigger than ifp mtu %d\n", 3277 hw_mtu, sw_mtu); 3278 } 3279 priv->params_ethtool.hw_mtu = hw_mtu; 3280 3281 /* compute MSB */ 3282 while (hw_mtu & (hw_mtu - 1)) 3283 hw_mtu &= (hw_mtu - 1); 3284 priv->params_ethtool.hw_mtu_msb = hw_mtu; 3285 3286 return (err); 3287 } 3288 3289 int 3290 mlx5e_open_locked(if_t ifp) 3291 { 3292 struct mlx5e_priv *priv = if_getsoftc(ifp); 3293 int err; 3294 u16 set_id; 3295 3296 /* check if already opened */ 3297 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 3298 return (0); 3299 3300 #ifdef RSS 3301 if (rss_getnumbuckets() > priv->params.num_channels) { 3302 mlx5_en_info(ifp, 3303 "NOTE: There are more RSS buckets(%u) than channels(%u) available\n", 3304 rss_getnumbuckets(), priv->params.num_channels); 3305 } 3306 #endif 3307 err = mlx5e_open_tises(priv); 3308 if (err) { 3309 mlx5_en_err(ifp, "mlx5e_open_tises failed, %d\n", err); 3310 return (err); 3311 } 3312 err = mlx5_vport_alloc_q_counter(priv->mdev, 3313 MLX5_INTERFACE_PROTOCOL_ETH, &set_id); 3314 if (err) { 3315 mlx5_en_err(priv->ifp, 3316 "mlx5_vport_alloc_q_counter failed: %d\n", err); 3317 goto err_close_tises; 3318 } 3319 /* store counter set ID */ 3320 priv->counter_set_id = set_id; 3321 3322 err = mlx5e_open_channels(priv); 3323 if (err) { 3324 mlx5_en_err(ifp, 3325 "mlx5e_open_channels failed, %d\n", err); 3326 goto err_dalloc_q_counter; 3327 } 3328 err = mlx5e_activate_rqt(priv); 3329 if (err) { 3330 mlx5_en_err(ifp, "mlx5e_activate_rqt failed, %d\n", err); 3331 goto err_close_channels; 3332 } 3333 3334 set_bit(MLX5E_STATE_OPENED, &priv->state); 3335 3336 mlx5e_update_carrier(priv); 3337 3338 return (0); 3339 3340 err_close_channels: 3341 mlx5e_close_channels(priv); 3342 3343 err_dalloc_q_counter: 3344 mlx5_vport_dealloc_q_counter(priv->mdev, 3345 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 3346 3347 err_close_tises: 3348 mlx5e_close_tises(priv); 3349 3350 return (err); 3351 } 3352 3353 static void 3354 mlx5e_open(void *arg) 3355 { 3356 struct mlx5e_priv *priv = arg; 3357 3358 PRIV_LOCK(priv); 3359 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP)) 3360 mlx5_en_err(priv->ifp, 3361 "Setting port status to up failed\n"); 3362 3363 mlx5e_open_locked(priv->ifp); 3364 if_setdrvflagbits(priv->ifp, IFF_DRV_RUNNING, 0); 3365 PRIV_UNLOCK(priv); 3366 } 3367 3368 int 3369 mlx5e_close_locked(if_t ifp) 3370 { 3371 struct mlx5e_priv *priv = if_getsoftc(ifp); 3372 3373 /* check if already closed */ 3374 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3375 return (0); 3376 3377 clear_bit(MLX5E_STATE_OPENED, &priv->state); 3378 3379 if_link_state_change(priv->ifp, LINK_STATE_DOWN); 3380 3381 mlx5e_deactivate_rqt(priv); 3382 mlx5e_close_channels(priv); 3383 mlx5_vport_dealloc_q_counter(priv->mdev, 3384 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 3385 mlx5e_close_tises(priv); 3386 3387 return (0); 3388 } 3389 3390 static uint64_t 3391 mlx5e_get_counter(if_t ifp, ift_counter cnt) 3392 { 3393 struct mlx5e_priv *priv = if_getsoftc(ifp); 3394 u64 retval; 3395 3396 /* PRIV_LOCK(priv); XXX not allowed */ 3397 switch (cnt) { 3398 case IFCOUNTER_IPACKETS: 3399 retval = priv->stats.vport.rx_packets; 3400 break; 3401 case IFCOUNTER_IERRORS: 3402 retval = priv->stats.pport.in_range_len_errors + 3403 priv->stats.pport.out_of_range_len + 3404 priv->stats.pport.too_long_errors + 3405 priv->stats.pport.check_seq_err + 3406 priv->stats.pport.alignment_err; 3407 break; 3408 case IFCOUNTER_IQDROPS: 3409 retval = priv->stats.vport.rx_out_of_buffer; 3410 break; 3411 case IFCOUNTER_OPACKETS: 3412 retval = priv->stats.vport.tx_packets; 3413 break; 3414 case IFCOUNTER_OERRORS: 3415 retval = priv->stats.port_stats_debug.out_discards; 3416 break; 3417 case IFCOUNTER_IBYTES: 3418 retval = priv->stats.vport.rx_bytes; 3419 break; 3420 case IFCOUNTER_OBYTES: 3421 retval = priv->stats.vport.tx_bytes; 3422 break; 3423 case IFCOUNTER_IMCASTS: 3424 retval = priv->stats.vport.rx_multicast_packets; 3425 break; 3426 case IFCOUNTER_OMCASTS: 3427 retval = priv->stats.vport.tx_multicast_packets; 3428 break; 3429 case IFCOUNTER_OQDROPS: 3430 retval = priv->stats.vport.tx_queue_dropped; 3431 break; 3432 case IFCOUNTER_COLLISIONS: 3433 retval = priv->stats.pport.collisions; 3434 break; 3435 default: 3436 retval = if_get_counter_default(ifp, cnt); 3437 break; 3438 } 3439 /* PRIV_UNLOCK(priv); XXX not allowed */ 3440 return (retval); 3441 } 3442 3443 static void 3444 mlx5e_set_rx_mode(if_t ifp) 3445 { 3446 struct mlx5e_priv *priv = if_getsoftc(ifp); 3447 3448 queue_work(priv->wq, &priv->set_rx_mode_work); 3449 } 3450 3451 static bool 3452 mlx5e_is_ipsec_capable(struct mlx5_core_dev *mdev) 3453 { 3454 #ifdef IPSEC_OFFLOAD 3455 if ((mlx5_ipsec_device_caps(mdev) & MLX5_IPSEC_CAP_PACKET_OFFLOAD) != 0) 3456 return (true); 3457 #endif 3458 return (false); 3459 } 3460 3461 static bool 3462 mlx5e_is_ratelimit_capable(struct mlx5_core_dev *mdev) 3463 { 3464 #ifdef RATELIMIT 3465 if (MLX5_CAP_GEN(mdev, qos) && 3466 MLX5_CAP_QOS(mdev, packet_pacing)) 3467 return (true); 3468 #endif 3469 return (false); 3470 } 3471 3472 static bool 3473 mlx5e_is_tlstx_capable(struct mlx5_core_dev *mdev) 3474 { 3475 #ifdef KERN_TLS 3476 if (MLX5_CAP_GEN(mdev, tls_tx) != 0 && 3477 MLX5_CAP_GEN(mdev, log_max_dek) != 0) 3478 return (true); 3479 #endif 3480 return (false); 3481 } 3482 3483 static bool 3484 mlx5e_is_tlsrx_capable(struct mlx5_core_dev *mdev) 3485 { 3486 #ifdef KERN_TLS 3487 if (MLX5_CAP_GEN(mdev, tls_rx) != 0 && 3488 MLX5_CAP_GEN(mdev, log_max_dek) != 0 && 3489 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, 3490 ft_field_support.outer_ip_version) != 0) 3491 return (true); 3492 #endif 3493 return (false); 3494 } 3495 3496 static int 3497 mlx5e_ioctl(if_t ifp, u_long command, caddr_t data) 3498 { 3499 struct mlx5e_priv *priv; 3500 struct ifreq *ifr; 3501 struct ifdownreason *ifdr; 3502 struct ifi2creq i2c; 3503 struct ifrsskey *ifrk; 3504 struct ifrsshash *ifrh; 3505 struct siocsifcapnv_driver_data *drv_ioctl_data, drv_ioctl_data_d; 3506 int error = 0; 3507 int mask; 3508 int size_read = 0; 3509 int module_status; 3510 int module_num; 3511 int max_mtu; 3512 uint8_t read_addr; 3513 3514 priv = if_getsoftc(ifp); 3515 3516 /* check if detaching */ 3517 if (priv == NULL || priv->gone != 0) 3518 return (ENXIO); 3519 3520 switch (command) { 3521 case SIOCSIFMTU: 3522 ifr = (struct ifreq *)data; 3523 3524 PRIV_LOCK(priv); 3525 mlx5_query_port_max_mtu(priv->mdev, &max_mtu); 3526 3527 if (ifr->ifr_mtu >= MLX5E_MTU_MIN && 3528 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) { 3529 int was_opened; 3530 3531 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 3532 if (was_opened) 3533 mlx5e_close_locked(ifp); 3534 3535 /* set new MTU */ 3536 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu); 3537 3538 if (was_opened) 3539 mlx5e_open_locked(ifp); 3540 } else { 3541 error = EINVAL; 3542 mlx5_en_err(ifp, 3543 "Invalid MTU value. Min val: %d, Max val: %d\n", 3544 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu)); 3545 } 3546 PRIV_UNLOCK(priv); 3547 break; 3548 case SIOCSIFFLAGS: 3549 if ((if_getflags(ifp) & IFF_UP) && 3550 (if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 3551 mlx5e_set_rx_mode(ifp); 3552 break; 3553 } 3554 PRIV_LOCK(priv); 3555 if (if_getflags(ifp) & IFF_UP) { 3556 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 3557 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3558 mlx5e_open_locked(ifp); 3559 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 3560 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP); 3561 } 3562 } else { 3563 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3564 mlx5_set_port_status(priv->mdev, 3565 MLX5_PORT_DOWN); 3566 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 3567 mlx5e_close_locked(ifp); 3568 mlx5e_update_carrier(priv); 3569 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3570 } 3571 } 3572 PRIV_UNLOCK(priv); 3573 break; 3574 case SIOCADDMULTI: 3575 case SIOCDELMULTI: 3576 mlx5e_set_rx_mode(ifp); 3577 break; 3578 case SIOCSIFMEDIA: 3579 case SIOCGIFMEDIA: 3580 case SIOCGIFXMEDIA: 3581 ifr = (struct ifreq *)data; 3582 error = ifmedia_ioctl(ifp, ifr, &priv->media, command); 3583 break; 3584 case SIOCGIFCAPNV: 3585 error = 0; 3586 break; 3587 case SIOCSIFCAP: 3588 ifr = (struct ifreq *)data; 3589 drv_ioctl_data = &drv_ioctl_data_d; 3590 drv_ioctl_data->reqcap = ifr->ifr_reqcap; 3591 PRIV_LOCK(priv); 3592 drv_ioctl_data->reqcap2 = if_getcapenable2(ifp); 3593 drv_ioctl_data->nvcap = NULL; 3594 goto siocsifcap_driver; 3595 case SIOCSIFCAPNV: 3596 drv_ioctl_data = (struct siocsifcapnv_driver_data *)data; 3597 PRIV_LOCK(priv); 3598 siocsifcap_driver: 3599 if (!mlx5e_is_tlstx_capable(priv->mdev)) { 3600 drv_ioctl_data->reqcap &= ~(IFCAP_TXTLS4 | 3601 IFCAP_TXTLS6); 3602 } 3603 if (!mlx5e_is_tlsrx_capable(priv->mdev)) { 3604 drv_ioctl_data->reqcap2 &= ~( 3605 IFCAP2_BIT(IFCAP2_RXTLS4) | 3606 IFCAP2_BIT(IFCAP2_RXTLS6)); 3607 } 3608 if (!mlx5e_is_ipsec_capable(priv->mdev)) { 3609 drv_ioctl_data->reqcap2 &= 3610 ~IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD); 3611 } 3612 if (!mlx5e_is_ratelimit_capable(priv->mdev)) { 3613 drv_ioctl_data->reqcap &= ~(IFCAP_TXTLS_RTLMT | 3614 IFCAP_TXRTLMT); 3615 } 3616 3617 mask = drv_ioctl_data->reqcap ^ if_getcapenable(ifp); 3618 3619 if (mask & IFCAP_TXCSUM) { 3620 if_togglecapenable(ifp, IFCAP_TXCSUM); 3621 if_togglehwassist(ifp, (CSUM_TCP | CSUM_UDP | CSUM_IP)); 3622 3623 if (IFCAP_TSO4 & if_getcapenable(ifp) && 3624 !(IFCAP_TXCSUM & if_getcapenable(ifp))) { 3625 mask &= ~IFCAP_TSO4; 3626 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 3627 if_sethwassistbits(ifp, 0, CSUM_IP_TSO); 3628 mlx5_en_err(ifp, 3629 "tso4 disabled due to -txcsum.\n"); 3630 } 3631 } 3632 if (mask & IFCAP_TXCSUM_IPV6) { 3633 if_togglecapenable(ifp, IFCAP_TXCSUM_IPV6); 3634 if_togglehwassist(ifp, (CSUM_UDP_IPV6 | CSUM_TCP_IPV6)); 3635 3636 if (IFCAP_TSO6 & if_getcapenable(ifp) && 3637 !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) { 3638 mask &= ~IFCAP_TSO6; 3639 if_setcapenablebit(ifp, 0, IFCAP_TSO6); 3640 if_sethwassistbits(ifp, 0, CSUM_IP6_TSO); 3641 mlx5_en_err(ifp, 3642 "tso6 disabled due to -txcsum6.\n"); 3643 } 3644 } 3645 if (mask & IFCAP_MEXTPG) 3646 if_togglecapenable(ifp, IFCAP_MEXTPG); 3647 if (mask & IFCAP_TXTLS4) 3648 if_togglecapenable(ifp, IFCAP_TXTLS4); 3649 if (mask & IFCAP_TXTLS6) 3650 if_togglecapenable(ifp, IFCAP_TXTLS6); 3651 #ifdef RATELIMIT 3652 if (mask & IFCAP_TXTLS_RTLMT) 3653 if_togglecapenable(ifp, IFCAP_TXTLS_RTLMT); 3654 #endif 3655 if (mask & IFCAP_RXCSUM) 3656 if_togglecapenable(ifp, IFCAP_RXCSUM); 3657 if (mask & IFCAP_RXCSUM_IPV6) 3658 if_togglecapenable(ifp, IFCAP_RXCSUM_IPV6); 3659 if (mask & IFCAP_TSO4) { 3660 if (!(IFCAP_TSO4 & if_getcapenable(ifp)) && 3661 !(IFCAP_TXCSUM & if_getcapenable(ifp))) { 3662 mlx5_en_err(ifp, "enable txcsum first.\n"); 3663 error = EAGAIN; 3664 goto out; 3665 } 3666 if_togglecapenable(ifp, IFCAP_TSO4); 3667 if_togglehwassist(ifp, CSUM_IP_TSO); 3668 } 3669 if (mask & IFCAP_TSO6) { 3670 if (!(IFCAP_TSO6 & if_getcapenable(ifp)) && 3671 !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) { 3672 mlx5_en_err(ifp, "enable txcsum6 first.\n"); 3673 error = EAGAIN; 3674 goto out; 3675 } 3676 if_togglecapenable(ifp, IFCAP_TSO6); 3677 if_togglehwassist(ifp, CSUM_IP6_TSO); 3678 } 3679 if (mask & IFCAP_VLAN_HWTSO) 3680 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 3681 if (mask & IFCAP_VLAN_HWFILTER) { 3682 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 3683 mlx5e_disable_vlan_filter(priv); 3684 else 3685 mlx5e_enable_vlan_filter(priv); 3686 3687 if_togglecapenable(ifp, IFCAP_VLAN_HWFILTER); 3688 } 3689 if (mask & IFCAP_VLAN_HWTAGGING) 3690 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 3691 if (mask & IFCAP_WOL_MAGIC) 3692 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 3693 if (mask & IFCAP_VXLAN_HWCSUM) { 3694 const bool was_enabled = 3695 (if_getcapenable(ifp) & IFCAP_VXLAN_HWCSUM) != 0; 3696 if (was_enabled) 3697 mlx5e_del_all_vxlan_rules(priv); 3698 if_togglecapenable(ifp, IFCAP_VXLAN_HWCSUM); 3699 if_togglehwassist(ifp, CSUM_INNER_IP | CSUM_INNER_IP_UDP | 3700 CSUM_INNER_IP_TCP | CSUM_INNER_IP6_UDP | 3701 CSUM_INNER_IP6_TCP); 3702 if (!was_enabled) { 3703 int err = mlx5e_add_all_vxlan_rules(priv); 3704 if (err != 0) { 3705 mlx5_en_err(ifp, 3706 "mlx5e_add_all_vxlan_rules() failed, %d (ignored)\n", err); 3707 } 3708 } 3709 } 3710 if (mask & IFCAP_VXLAN_HWTSO) { 3711 if_togglecapenable(ifp, IFCAP_VXLAN_HWTSO); 3712 if_togglehwassist(ifp, CSUM_INNER_IP_TSO | 3713 CSUM_INNER_IP6_TSO); 3714 } 3715 3716 VLAN_CAPABILITIES(ifp); 3717 3718 /* hw_lro and IFCAP_LRO are divorsed, only toggle sw LRO. */ 3719 if (mask & IFCAP_LRO) 3720 if_togglecapenable(ifp, IFCAP_LRO); 3721 3722 if (mask & IFCAP_HWRXTSTMP) { 3723 if_togglecapenable(ifp, IFCAP_HWRXTSTMP); 3724 if (if_getcapenable(ifp) & IFCAP_HWRXTSTMP) { 3725 if (priv->clbr_done == 0) 3726 mlx5e_reset_calibration_callout(priv); 3727 } else { 3728 callout_drain(&priv->tstmp_clbr); 3729 priv->clbr_done = 0; 3730 } 3731 } 3732 mask = drv_ioctl_data->reqcap2 ^ if_getcapenable2(ifp); 3733 if ((mask & IFCAP2_BIT(IFCAP2_RXTLS4)) != 0) 3734 if_togglecapenable2(ifp, IFCAP2_BIT(IFCAP2_RXTLS4)); 3735 if ((mask & IFCAP2_BIT(IFCAP2_RXTLS6)) != 0) 3736 if_togglecapenable2(ifp, IFCAP2_BIT(IFCAP2_RXTLS6)); 3737 #ifdef IPSEC_OFFLOAD 3738 if ((mask & IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD)) != 0) { 3739 bool was_enabled = (if_getcapenable2(ifp) & 3740 IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD)) != 0; 3741 mlx5e_close_locked(ifp); 3742 if (was_enabled) 3743 ipsec_accel_on_ifdown(priv->ifp); 3744 if_togglecapenable2(ifp, 3745 IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD)); 3746 mlx5e_open_locked(ifp); 3747 } 3748 #endif 3749 out: 3750 PRIV_UNLOCK(priv); 3751 break; 3752 3753 case SIOCGI2C: 3754 ifr = (struct ifreq *)data; 3755 3756 /* 3757 * Copy from the user-space address ifr_data to the 3758 * kernel-space address i2c 3759 */ 3760 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 3761 if (error) 3762 break; 3763 3764 if (i2c.len > sizeof(i2c.data)) { 3765 error = EINVAL; 3766 break; 3767 } 3768 3769 PRIV_LOCK(priv); 3770 /* Get module_num which is required for the query_eeprom */ 3771 error = mlx5_query_module_num(priv->mdev, &module_num); 3772 if (error) { 3773 mlx5_en_err(ifp, 3774 "Query module num failed, eeprom reading is not supported\n"); 3775 error = EINVAL; 3776 goto err_i2c; 3777 } 3778 /* Check if module is present before doing an access */ 3779 module_status = mlx5_query_module_status(priv->mdev, module_num); 3780 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED) { 3781 if (bootverbose) 3782 mlx5_en_err(ifp, 3783 "Query module %d status: not plugged (%d), " 3784 "eeprom reading is not supported\n", 3785 module_num, module_status); 3786 error = EINVAL; 3787 goto err_i2c; 3788 } 3789 /* 3790 * Currently 0XA0 and 0xA2 are the only addresses permitted. 3791 * The internal conversion is as follows: 3792 */ 3793 if (i2c.dev_addr == 0xA0) 3794 read_addr = MLX5_I2C_ADDR_LOW; 3795 else if (i2c.dev_addr == 0xA2) 3796 read_addr = MLX5_I2C_ADDR_HIGH; 3797 else { 3798 mlx5_en_err(ifp, 3799 "Query eeprom failed, Invalid Address: %X\n", 3800 i2c.dev_addr); 3801 error = EINVAL; 3802 goto err_i2c; 3803 } 3804 error = mlx5_query_eeprom(priv->mdev, 3805 read_addr, MLX5_EEPROM_LOW_PAGE, 3806 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num, 3807 (uint32_t *)i2c.data, &size_read); 3808 if (error) { 3809 mlx5_en_err(ifp, 3810 "Query eeprom failed, eeprom reading is not supported\n"); 3811 error = EINVAL; 3812 goto err_i2c; 3813 } 3814 3815 if (i2c.len > MLX5_EEPROM_MAX_BYTES) { 3816 error = mlx5_query_eeprom(priv->mdev, 3817 read_addr, MLX5_EEPROM_LOW_PAGE, 3818 (uint32_t)(i2c.offset + size_read), 3819 (uint32_t)(i2c.len - size_read), module_num, 3820 (uint32_t *)(i2c.data + size_read), &size_read); 3821 } 3822 if (error) { 3823 mlx5_en_err(ifp, 3824 "Query eeprom failed, eeprom reading is not supported\n"); 3825 error = EINVAL; 3826 goto err_i2c; 3827 } 3828 3829 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 3830 err_i2c: 3831 PRIV_UNLOCK(priv); 3832 break; 3833 case SIOCGIFDOWNREASON: 3834 ifdr = (struct ifdownreason *)data; 3835 bzero(ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg)); 3836 PRIV_LOCK(priv); 3837 error = -mlx5_query_pddr_troubleshooting_info(priv->mdev, NULL, 3838 ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg)); 3839 PRIV_UNLOCK(priv); 3840 if (error == 0) 3841 ifdr->ifdr_reason = IFDR_REASON_MSG; 3842 break; 3843 3844 case SIOCGIFRSSKEY: 3845 ifrk = (struct ifrsskey *)data; 3846 ifrk->ifrk_func = RSS_FUNC_TOEPLITZ; 3847 ifrk->ifrk_keylen = MLX5E_RSS_KEY_SIZE; 3848 CTASSERT(sizeof(ifrk->ifrk_key) >= MLX5E_RSS_KEY_SIZE); 3849 mlx5e_get_rss_key(ifrk->ifrk_key); 3850 break; 3851 3852 case SIOCGIFRSSHASH: 3853 ifrh = (struct ifrsshash *)data; 3854 ifrh->ifrh_func = RSS_FUNC_TOEPLITZ; 3855 ifrh->ifrh_types = 3856 RSS_TYPE_IPV4 | 3857 RSS_TYPE_TCP_IPV4 | 3858 RSS_TYPE_UDP_IPV4 | 3859 RSS_TYPE_IPV6 | 3860 RSS_TYPE_TCP_IPV6 | 3861 RSS_TYPE_UDP_IPV6; 3862 break; 3863 3864 default: 3865 error = ether_ioctl(ifp, command, data); 3866 break; 3867 } 3868 return (error); 3869 } 3870 3871 static int 3872 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev) 3873 { 3874 /* 3875 * TODO: uncoment once FW really sets all these bits if 3876 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap || 3877 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap || 3878 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return 3879 * -ENOTSUPP; 3880 */ 3881 3882 /* TODO: add more must-to-have features */ 3883 3884 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) 3885 return (-ENODEV); 3886 3887 return (0); 3888 } 3889 3890 static u16 3891 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev) 3892 { 3893 const int min_size = ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN; 3894 const int max_size = MLX5E_MAX_TX_INLINE; 3895 const int bf_buf_size = 3896 ((1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U) - 3897 (sizeof(struct mlx5e_tx_wqe) - 2); 3898 3899 /* verify against driver limits */ 3900 if (bf_buf_size > max_size) 3901 return (max_size); 3902 else if (bf_buf_size < min_size) 3903 return (min_size); 3904 else 3905 return (bf_buf_size); 3906 } 3907 3908 static int 3909 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev, 3910 struct mlx5e_priv *priv, 3911 int num_comp_vectors) 3912 { 3913 int err; 3914 3915 /* 3916 * TODO: Consider link speed for setting "log_sq_size", 3917 * "log_rq_size" and "cq_moderation_xxx": 3918 */ 3919 priv->params.log_sq_size = 3920 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; 3921 priv->params.log_rq_size = 3922 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; 3923 priv->params.rx_cq_moderation_usec = 3924 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 3925 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE : 3926 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; 3927 priv->params.rx_cq_moderation_mode = 3928 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0; 3929 priv->params.rx_cq_moderation_pkts = 3930 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; 3931 priv->params.tx_cq_moderation_usec = 3932 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; 3933 priv->params.tx_cq_moderation_pkts = 3934 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; 3935 priv->params.rx_hash_log_tbl_sz = 3936 (order_base_2(num_comp_vectors) > 3937 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ? 3938 order_base_2(num_comp_vectors) : 3939 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ; 3940 priv->params.num_tc = 1; 3941 priv->params.default_vlan_prio = 0; 3942 priv->counter_set_id = -1; 3943 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev); 3944 3945 err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode); 3946 if (err) 3947 return (err); 3948 3949 /* 3950 * hw lro is currently defaulted to off. when it won't anymore we 3951 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)" 3952 */ 3953 priv->params.hw_lro_en = false; 3954 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; 3955 3956 /* 3957 * CQE zipping is off, because the per-packet 32-bit Toeplitz hash 3958 * is then not supported. The 32-bit Toeplitz hash is needed to 3959 * correctly demultiplex incoming traffic into the expected 3960 * network queues. 3961 */ 3962 priv->params.cqe_zipping_en = false; 3963 3964 priv->mdev = mdev; 3965 priv->params.num_channels = num_comp_vectors; 3966 priv->params.channels_rsss = 1; 3967 priv->order_base_2_num_channels = order_base_2(num_comp_vectors); 3968 priv->queue_mapping_channel_mask = 3969 roundup_pow_of_two(num_comp_vectors) - 1; 3970 priv->num_tc = priv->params.num_tc; 3971 priv->default_vlan_prio = priv->params.default_vlan_prio; 3972 3973 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work); 3974 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); 3975 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); 3976 3977 return (0); 3978 } 3979 3980 static void 3981 mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc) 3982 { 3983 bool ro_pci_enable = 3984 pci_get_relaxed_ordering_enabled(mdev->pdev->dev.bsddev); 3985 bool ro_write = MLX5_CAP_GEN(mdev, relaxed_ordering_write); 3986 bool ro_read = MLX5_CAP_GEN(mdev, relaxed_ordering_read); 3987 3988 MLX5_SET(mkc, mkc, relaxed_ordering_read, ro_pci_enable && ro_read); 3989 MLX5_SET(mkc, mkc, relaxed_ordering_write, ro_pci_enable && ro_write); 3990 } 3991 3992 static int 3993 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn, 3994 struct mlx5_core_mkey *mkey) 3995 { 3996 if_t ifp = priv->ifp; 3997 struct mlx5_core_dev *mdev = priv->mdev; 3998 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 3999 void *mkc; 4000 u32 *in; 4001 int err; 4002 4003 in = mlx5_vzalloc(inlen); 4004 if (in == NULL) { 4005 mlx5_en_err(ifp, "failed to allocate inbox\n"); 4006 return (-ENOMEM); 4007 } 4008 4009 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 4010 MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA); 4011 MLX5_SET(mkc, mkc, umr_en, 1); /* used by HW TLS */ 4012 MLX5_SET(mkc, mkc, lw, 1); 4013 MLX5_SET(mkc, mkc, lr, 1); 4014 mlx5e_mkey_set_relaxed_ordering(mdev, mkc); 4015 MLX5_SET(mkc, mkc, pd, pdn); 4016 MLX5_SET(mkc, mkc, length64, 1); 4017 MLX5_SET(mkc, mkc, qpn, 0xffffff); 4018 4019 err = mlx5_core_create_mkey(mdev, mkey, in, inlen); 4020 if (err) 4021 mlx5_en_err(ifp, "mlx5_core_create_mkey failed, %d\n", 4022 err); 4023 4024 kvfree(in); 4025 return (err); 4026 } 4027 4028 static const char *mlx5e_vport_stats_desc[] = { 4029 MLX5E_VPORT_STATS(MLX5E_STATS_DESC) 4030 }; 4031 4032 static const char *mlx5e_pport_stats_desc[] = { 4033 MLX5E_PPORT_STATS(MLX5E_STATS_DESC) 4034 }; 4035 4036 static int 4037 mlx5e_priv_static_init(struct mlx5e_priv *priv, struct mlx5_core_dev *mdev, 4038 const uint32_t channels) 4039 { 4040 uint32_t x; 4041 int err; 4042 4043 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF); 4044 sx_init(&priv->state_lock, "mlx5state"); 4045 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0); 4046 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock); 4047 for (x = 0; x != channels; x++) 4048 mlx5e_chan_static_init(priv, &priv->channel[x], x); 4049 4050 for (x = 0; x != channels; x++) { 4051 err = mlx5_alloc_bfreg(mdev, &priv->channel[x].bfreg, false, false); 4052 if (err) 4053 goto err_alloc_bfreg; 4054 } 4055 return (0); 4056 4057 err_alloc_bfreg: 4058 while (x--) 4059 mlx5_free_bfreg(mdev, &priv->channel[x].bfreg); 4060 4061 for (x = 0; x != channels; x++) 4062 mlx5e_chan_static_destroy(&priv->channel[x]); 4063 callout_drain(&priv->watchdog); 4064 mtx_destroy(&priv->async_events_mtx); 4065 sx_destroy(&priv->state_lock); 4066 return (err); 4067 } 4068 4069 static void 4070 mlx5e_priv_static_destroy(struct mlx5e_priv *priv, struct mlx5_core_dev *mdev, 4071 const uint32_t channels) 4072 { 4073 uint32_t x; 4074 4075 for (x = 0; x != channels; x++) 4076 mlx5_free_bfreg(mdev, &priv->channel[x].bfreg); 4077 for (x = 0; x != channels; x++) 4078 mlx5e_chan_static_destroy(&priv->channel[x]); 4079 callout_drain(&priv->watchdog); 4080 mtx_destroy(&priv->async_events_mtx); 4081 sx_destroy(&priv->state_lock); 4082 } 4083 4084 static int 4085 sysctl_firmware(SYSCTL_HANDLER_ARGS) 4086 { 4087 /* 4088 * %d.%d%.d the string format. 4089 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536. 4090 * We need at most 5 chars to store that. 4091 * It also has: two "." and NULL at the end, which means we need 18 4092 * (5*3 + 3) chars at most. 4093 */ 4094 char fw[18]; 4095 struct mlx5e_priv *priv = arg1; 4096 int error; 4097 4098 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev), 4099 fw_rev_sub(priv->mdev)); 4100 error = sysctl_handle_string(oidp, fw, sizeof(fw), req); 4101 return (error); 4102 } 4103 4104 static void 4105 mlx5e_disable_tx_dma(struct mlx5e_channel *ch) 4106 { 4107 int i; 4108 4109 for (i = 0; i < ch->priv->num_tc; i++) 4110 mlx5e_drain_sq(&ch->sq[i]); 4111 } 4112 4113 static void 4114 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq) 4115 { 4116 4117 sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP); 4118 sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8); 4119 mlx5e_tx_notify_hw(sq, true); 4120 } 4121 4122 void 4123 mlx5e_resume_sq(struct mlx5e_sq *sq) 4124 { 4125 int err; 4126 4127 /* check if already enabled */ 4128 if (READ_ONCE(sq->running) != 0) 4129 return; 4130 4131 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR, 4132 MLX5_SQC_STATE_RST); 4133 if (err != 0) { 4134 mlx5_en_err(sq->ifp, 4135 "mlx5e_modify_sq() from ERR to RST failed: %d\n", err); 4136 } 4137 4138 sq->cc = 0; 4139 sq->pc = 0; 4140 4141 /* reset doorbell prior to moving from RST to RDY */ 4142 mlx5e_reset_sq_doorbell_record(sq); 4143 4144 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, 4145 MLX5_SQC_STATE_RDY); 4146 if (err != 0) { 4147 mlx5_en_err(sq->ifp, 4148 "mlx5e_modify_sq() from RST to RDY failed: %d\n", err); 4149 } 4150 4151 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL; 4152 WRITE_ONCE(sq->running, 1); 4153 } 4154 4155 static void 4156 mlx5e_enable_tx_dma(struct mlx5e_channel *ch) 4157 { 4158 int i; 4159 4160 for (i = 0; i < ch->priv->num_tc; i++) 4161 mlx5e_resume_sq(&ch->sq[i]); 4162 } 4163 4164 static void 4165 mlx5e_disable_rx_dma(struct mlx5e_channel *ch) 4166 { 4167 struct mlx5e_rq *rq = &ch->rq; 4168 struct epoch_tracker et; 4169 int err; 4170 4171 mtx_lock(&rq->mtx); 4172 rq->enabled = 0; 4173 callout_stop(&rq->watchdog); 4174 mtx_unlock(&rq->mtx); 4175 4176 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 4177 if (err != 0) { 4178 mlx5_en_err(rq->ifp, 4179 "mlx5e_modify_rq() from RDY to RST failed: %d\n", err); 4180 } 4181 4182 while (!mlx5_wq_ll_is_empty(&rq->wq)) { 4183 msleep(1); 4184 NET_EPOCH_ENTER(et); 4185 rq->cq.mcq.comp(&rq->cq.mcq, NULL); 4186 NET_EPOCH_EXIT(et); 4187 } 4188 4189 /* 4190 * Transitioning into RST state will allow the FW to track less ERR state queues, 4191 * thus reducing the recv queue flushing time 4192 */ 4193 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST); 4194 if (err != 0) { 4195 mlx5_en_err(rq->ifp, 4196 "mlx5e_modify_rq() from ERR to RST failed: %d\n", err); 4197 } 4198 } 4199 4200 static void 4201 mlx5e_enable_rx_dma(struct mlx5e_channel *ch) 4202 { 4203 struct mlx5e_rq *rq = &ch->rq; 4204 struct epoch_tracker et; 4205 int err; 4206 4207 rq->wq.wqe_ctr = 0; 4208 mlx5_wq_ll_update_db_record(&rq->wq); 4209 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 4210 if (err != 0) { 4211 mlx5_en_err(rq->ifp, 4212 "mlx5e_modify_rq() from RST to RDY failed: %d\n", err); 4213 } 4214 4215 rq->enabled = 1; 4216 4217 NET_EPOCH_ENTER(et); 4218 rq->cq.mcq.comp(&rq->cq.mcq, NULL); 4219 NET_EPOCH_EXIT(et); 4220 } 4221 4222 void 4223 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value) 4224 { 4225 int i; 4226 4227 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 4228 return; 4229 4230 for (i = 0; i < priv->params.num_channels; i++) { 4231 if (value) 4232 mlx5e_disable_tx_dma(&priv->channel[i]); 4233 else 4234 mlx5e_enable_tx_dma(&priv->channel[i]); 4235 } 4236 } 4237 4238 void 4239 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value) 4240 { 4241 int i; 4242 4243 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 4244 return; 4245 4246 for (i = 0; i < priv->params.num_channels; i++) { 4247 if (value) 4248 mlx5e_disable_rx_dma(&priv->channel[i]); 4249 else 4250 mlx5e_enable_rx_dma(&priv->channel[i]); 4251 } 4252 } 4253 4254 static void 4255 mlx5e_add_hw_stats(struct mlx5e_priv *priv) 4256 { 4257 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 4258 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 4259 priv, 0, sysctl_firmware, "A", "HCA firmware version"); 4260 4261 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 4262 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0, 4263 "Board ID"); 4264 } 4265 4266 static int 4267 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS) 4268 { 4269 struct mlx5e_priv *priv = arg1; 4270 uint8_t temp[MLX5E_MAX_PRIORITY]; 4271 uint32_t tx_pfc; 4272 int err; 4273 int i; 4274 4275 PRIV_LOCK(priv); 4276 4277 tx_pfc = priv->params.tx_priority_flow_control; 4278 4279 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) 4280 temp[i] = (tx_pfc >> i) & 1; 4281 4282 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY); 4283 if (err || !req->newptr) 4284 goto done; 4285 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY); 4286 if (err) 4287 goto done; 4288 4289 priv->params.tx_priority_flow_control = 0; 4290 4291 /* range check input value */ 4292 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) { 4293 if (temp[i] > 1) { 4294 err = ERANGE; 4295 goto done; 4296 } 4297 priv->params.tx_priority_flow_control |= (temp[i] << i); 4298 } 4299 4300 /* check if update is required */ 4301 if (tx_pfc != priv->params.tx_priority_flow_control) 4302 err = -mlx5e_set_port_pfc(priv); 4303 done: 4304 if (err != 0) 4305 priv->params.tx_priority_flow_control= tx_pfc; 4306 PRIV_UNLOCK(priv); 4307 4308 return (err); 4309 } 4310 4311 static int 4312 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS) 4313 { 4314 struct mlx5e_priv *priv = arg1; 4315 uint8_t temp[MLX5E_MAX_PRIORITY]; 4316 uint32_t rx_pfc; 4317 int err; 4318 int i; 4319 4320 PRIV_LOCK(priv); 4321 4322 rx_pfc = priv->params.rx_priority_flow_control; 4323 4324 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) 4325 temp[i] = (rx_pfc >> i) & 1; 4326 4327 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY); 4328 if (err || !req->newptr) 4329 goto done; 4330 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY); 4331 if (err) 4332 goto done; 4333 4334 priv->params.rx_priority_flow_control = 0; 4335 4336 /* range check input value */ 4337 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) { 4338 if (temp[i] > 1) { 4339 err = ERANGE; 4340 goto done; 4341 } 4342 priv->params.rx_priority_flow_control |= (temp[i] << i); 4343 } 4344 4345 /* check if update is required */ 4346 if (rx_pfc != priv->params.rx_priority_flow_control) { 4347 err = -mlx5e_set_port_pfc(priv); 4348 if (err == 0 && priv->sw_is_port_buf_owner) 4349 err = mlx5e_update_buf_lossy(priv); 4350 } 4351 done: 4352 if (err != 0) 4353 priv->params.rx_priority_flow_control= rx_pfc; 4354 PRIV_UNLOCK(priv); 4355 4356 return (err); 4357 } 4358 4359 static void 4360 mlx5e_setup_pauseframes(struct mlx5e_priv *priv) 4361 { 4362 int error; 4363 4364 /* enable pauseframes by default */ 4365 priv->params.tx_pauseframe_control = 1; 4366 priv->params.rx_pauseframe_control = 1; 4367 4368 /* disable ports flow control, PFC, by default */ 4369 priv->params.tx_priority_flow_control = 0; 4370 priv->params.rx_priority_flow_control = 0; 4371 4372 /* register pauseframe SYSCTLs */ 4373 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4374 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN, 4375 &priv->params.tx_pauseframe_control, 0, 4376 "Set to enable TX pause frames. Clear to disable."); 4377 4378 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4379 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN, 4380 &priv->params.rx_pauseframe_control, 0, 4381 "Set to enable RX pause frames. Clear to disable."); 4382 4383 /* register priority flow control, PFC, SYSCTLs */ 4384 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4385 OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN | 4386 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU", 4387 "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable."); 4388 4389 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4390 OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN | 4391 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU", 4392 "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable."); 4393 4394 PRIV_LOCK(priv); 4395 4396 /* range check */ 4397 priv->params.tx_pauseframe_control = 4398 priv->params.tx_pauseframe_control ? 1 : 0; 4399 priv->params.rx_pauseframe_control = 4400 priv->params.rx_pauseframe_control ? 1 : 0; 4401 4402 /* update firmware */ 4403 error = mlx5e_set_port_pause_and_pfc(priv); 4404 if (error == -EINVAL) { 4405 mlx5_en_err(priv->ifp, 4406 "Global pauseframes must be disabled before enabling PFC.\n"); 4407 priv->params.rx_priority_flow_control = 0; 4408 priv->params.tx_priority_flow_control = 0; 4409 4410 /* update firmware */ 4411 (void) mlx5e_set_port_pause_and_pfc(priv); 4412 } 4413 PRIV_UNLOCK(priv); 4414 } 4415 4416 static int 4417 mlx5e_ul_snd_tag_alloc(if_t ifp, 4418 union if_snd_tag_alloc_params *params, 4419 struct m_snd_tag **ppmt) 4420 { 4421 struct mlx5e_priv *priv; 4422 struct mlx5e_channel *pch; 4423 4424 priv = if_getsoftc(ifp); 4425 4426 if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) { 4427 return (EOPNOTSUPP); 4428 } else { 4429 /* keep this code synced with mlx5e_select_queue() */ 4430 u32 ch = priv->params.num_channels; 4431 #ifdef RSS 4432 u32 temp; 4433 4434 if (rss_hash2bucket(params->hdr.flowid, 4435 params->hdr.flowtype, &temp) == 0) 4436 ch = temp % ch; 4437 else 4438 #endif 4439 ch = (params->hdr.flowid % 128) % ch; 4440 4441 /* 4442 * NOTE: The channels array is only freed at detach 4443 * and it safe to return a pointer to the send tag 4444 * inside the channels structure as long as we 4445 * reference the priv. 4446 */ 4447 pch = priv->channel + ch; 4448 4449 /* check if send queue is not running */ 4450 if (unlikely(pch->sq[0].running == 0)) 4451 return (ENXIO); 4452 m_snd_tag_ref(&pch->tag); 4453 *ppmt = &pch->tag; 4454 return (0); 4455 } 4456 } 4457 4458 static int 4459 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params) 4460 { 4461 struct mlx5e_channel *pch = 4462 container_of(pmt, struct mlx5e_channel, tag); 4463 4464 params->unlimited.max_rate = -1ULL; 4465 params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]); 4466 return (0); 4467 } 4468 4469 static void 4470 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt) 4471 { 4472 struct mlx5e_channel *pch = 4473 container_of(pmt, struct mlx5e_channel, tag); 4474 4475 complete(&pch->completion); 4476 } 4477 4478 static int 4479 mlx5e_snd_tag_alloc(if_t ifp, 4480 union if_snd_tag_alloc_params *params, 4481 struct m_snd_tag **ppmt) 4482 { 4483 4484 switch (params->hdr.type) { 4485 #ifdef RATELIMIT 4486 case IF_SND_TAG_TYPE_RATE_LIMIT: 4487 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt)); 4488 #ifdef KERN_TLS 4489 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT: 4490 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt)); 4491 #endif 4492 #endif 4493 case IF_SND_TAG_TYPE_UNLIMITED: 4494 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt)); 4495 #ifdef KERN_TLS 4496 case IF_SND_TAG_TYPE_TLS: 4497 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt)); 4498 case IF_SND_TAG_TYPE_TLS_RX: 4499 return (mlx5e_tls_rx_snd_tag_alloc(ifp, params, ppmt)); 4500 #endif 4501 default: 4502 return (EOPNOTSUPP); 4503 } 4504 } 4505 4506 #ifdef RATELIMIT 4507 #define NUM_HDWR_RATES_MLX 13 4508 static const uint64_t adapter_rates_mlx[NUM_HDWR_RATES_MLX] = { 4509 135375, /* 1,083,000 */ 4510 180500, /* 1,444,000 */ 4511 270750, /* 2,166,000 */ 4512 361000, /* 2,888,000 */ 4513 541500, /* 4,332,000 */ 4514 721875, /* 5,775,000 */ 4515 1082875, /* 8,663,000 */ 4516 1443875, /* 11,551,000 */ 4517 2165750, /* 17,326,000 */ 4518 2887750, /* 23,102,000 */ 4519 4331625, /* 34,653,000 */ 4520 5775500, /* 46,204,000 */ 4521 8663125 /* 69,305,000 */ 4522 }; 4523 4524 static void 4525 mlx5e_ratelimit_query(if_t ifp __unused, struct if_ratelimit_query_results *q) 4526 { 4527 /* 4528 * This function needs updating by the driver maintainer! 4529 * For the MLX card there are currently (ConectX-4?) 13 4530 * pre-set rates and others i.e. ConnectX-5, 6, 7?? 4531 * 4532 * This will change based on later adapters 4533 * and this code should be updated to look at ifp 4534 * and figure out the specific adapter type 4535 * settings i.e. how many rates as well 4536 * as if they are fixed (as is shown here) or 4537 * if they are dynamic (example chelsio t4). Also if there 4538 * is a maximum number of flows that the adapter 4539 * can handle that too needs to be updated in 4540 * the max_flows field. 4541 */ 4542 q->rate_table = adapter_rates_mlx; 4543 q->flags = RT_IS_FIXED_TABLE; 4544 q->max_flows = 0; /* mlx has no limit */ 4545 q->number_of_rates = NUM_HDWR_RATES_MLX; 4546 q->min_segment_burst = 1; 4547 } 4548 #endif 4549 4550 static void 4551 mlx5e_ifm_add(struct mlx5e_priv *priv, int type) 4552 { 4553 ifmedia_add(&priv->media, type | IFM_ETHER, 0, NULL); 4554 ifmedia_add(&priv->media, type | IFM_ETHER | 4555 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 4556 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_RXPAUSE, 0, NULL); 4557 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_TXPAUSE, 0, NULL); 4558 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX, 0, NULL); 4559 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX | 4560 IFM_ETH_RXPAUSE, 0, NULL); 4561 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX | 4562 IFM_ETH_TXPAUSE, 0, NULL); 4563 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX | 4564 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 4565 } 4566 4567 static void * 4568 mlx5e_create_ifp(struct mlx5_core_dev *mdev) 4569 { 4570 if_t ifp; 4571 struct mlx5e_priv *priv; 4572 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4); 4573 struct sysctl_oid_list *child; 4574 int ncv = mdev->priv.eq_table.num_comp_vectors; 4575 char unit[16]; 4576 struct pfil_head_args pa; 4577 int err; 4578 u32 eth_proto_cap; 4579 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 4580 bool ext; 4581 struct media media_entry = {}; 4582 4583 if (mlx5e_check_required_hca_cap(mdev)) { 4584 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n"); 4585 return (NULL); 4586 } 4587 4588 /* 4589 * Try to allocate the priv and make room for worst-case 4590 * number of channel structures: 4591 */ 4592 priv = malloc_domainset(sizeof(*priv) + 4593 (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors), 4594 M_MLX5EN, mlx5_dev_domainset(mdev), M_WAITOK | M_ZERO); 4595 4596 ifp = priv->ifp = if_alloc_dev(IFT_ETHER, mdev->pdev->dev.bsddev); 4597 /* setup all static fields */ 4598 if (mlx5e_priv_static_init(priv, mdev, mdev->priv.eq_table.num_comp_vectors)) { 4599 mlx5_core_err(mdev, "mlx5e_priv_static_init() failed\n"); 4600 goto err_free_ifp; 4601 } 4602 4603 if_setsoftc(ifp, priv); 4604 if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev)); 4605 if_setmtu(ifp, ETHERMTU); 4606 if_setinitfn(ifp, mlx5e_open); 4607 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 4608 if_setioctlfn(ifp, mlx5e_ioctl); 4609 if_settransmitfn(ifp, mlx5e_xmit); 4610 if_setqflushfn(ifp, if_qflush); 4611 if_setgetcounterfn(ifp, mlx5e_get_counter); 4612 if_setsendqlen(ifp, ifqmaxlen); 4613 /* 4614 * Set driver features 4615 */ 4616 if_setcapabilities(ifp, IFCAP_NV); 4617 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6, 0); 4618 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING, 0); 4619 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER, 0); 4620 if_setcapabilitiesbit(ifp, IFCAP_LINKSTATE | IFCAP_JUMBO_MTU, 0); 4621 if_setcapabilitiesbit(ifp, IFCAP_LRO, 0); 4622 if_setcapabilitiesbit(ifp, IFCAP_TSO | IFCAP_VLAN_HWTSO, 0); 4623 if_setcapabilitiesbit(ifp, IFCAP_HWSTATS | IFCAP_HWRXTSTMP, 0); 4624 if_setcapabilitiesbit(ifp, IFCAP_MEXTPG, 0); 4625 if (mlx5e_is_tlstx_capable(mdev)) 4626 if_setcapabilitiesbit(ifp, IFCAP_TXTLS4 | IFCAP_TXTLS6, 0); 4627 if (mlx5e_is_tlsrx_capable(mdev)) 4628 if_setcapabilities2bit(ifp, IFCAP2_BIT(IFCAP2_RXTLS4) | 4629 IFCAP2_BIT(IFCAP2_RXTLS6), 0); 4630 if (mlx5e_is_ratelimit_capable(mdev)) { 4631 if_setcapabilitiesbit(ifp, IFCAP_TXRTLMT, 0); 4632 if (mlx5e_is_tlstx_capable(mdev)) 4633 if_setcapabilitiesbit(ifp, IFCAP_TXTLS_RTLMT, 0); 4634 } 4635 if_setcapabilitiesbit(ifp, IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO, 0); 4636 if (mlx5e_is_ipsec_capable(mdev)) 4637 if_setcapabilities2bit(ifp, IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD), 4638 0); 4639 4640 if_setsndtagallocfn(ifp, mlx5e_snd_tag_alloc); 4641 #ifdef RATELIMIT 4642 if_setratelimitqueryfn(ifp, mlx5e_ratelimit_query); 4643 #endif 4644 /* set TSO limits so that we don't have to drop TX packets */ 4645 if_sethwtsomax(ifp, MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN)); 4646 if_sethwtsomaxsegcount(ifp, MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */); 4647 if_sethwtsomaxsegsize(ifp, MLX5E_MAX_TX_MBUF_SIZE); 4648 4649 if_setcapenable(ifp, if_getcapabilities(ifp)); 4650 if_setcapenable2(ifp, if_getcapabilities2(ifp)); 4651 if_sethwassist(ifp, 0); 4652 if (if_getcapenable(ifp) & IFCAP_TSO) 4653 if_sethwassistbits(ifp, CSUM_TSO, 0); 4654 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 4655 if_sethwassistbits(ifp, (CSUM_TCP | CSUM_UDP | CSUM_IP), 0); 4656 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 4657 if_sethwassistbits(ifp, (CSUM_UDP_IPV6 | CSUM_TCP_IPV6), 0); 4658 if (if_getcapabilities(ifp) & IFCAP_VXLAN_HWCSUM) 4659 if_sethwassistbits(ifp, CSUM_INNER_IP6_UDP | CSUM_INNER_IP6_TCP | 4660 CSUM_INNER_IP | CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP | 4661 CSUM_ENCAP_VXLAN, 0); 4662 if (if_getcapabilities(ifp) & IFCAP_VXLAN_HWTSO) 4663 if_sethwassistbits(ifp, CSUM_INNER_IP6_TSO | CSUM_INNER_IP_TSO, 0); 4664 4665 /* ifnet sysctl tree */ 4666 sysctl_ctx_init(&priv->sysctl_ctx); 4667 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev), 4668 OID_AUTO, if_getdname(ifp), CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 4669 "MLX5 ethernet - interface name"); 4670 if (priv->sysctl_ifnet == NULL) { 4671 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4672 goto err_free_sysctl; 4673 } 4674 snprintf(unit, sizeof(unit), "%d", if_getdunit(ifp)); 4675 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4676 OID_AUTO, unit, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 4677 "MLX5 ethernet - interface unit"); 4678 if (priv->sysctl_ifnet == NULL) { 4679 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4680 goto err_free_sysctl; 4681 } 4682 4683 /* HW sysctl tree */ 4684 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev)); 4685 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child, 4686 OID_AUTO, "hw", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 4687 "MLX5 ethernet dev hw"); 4688 if (priv->sysctl_hw == NULL) { 4689 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4690 goto err_free_sysctl; 4691 } 4692 4693 err = mlx5e_build_ifp_priv(mdev, priv, ncv); 4694 if (err) { 4695 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err); 4696 goto err_free_sysctl; 4697 } 4698 4699 /* reuse mlx5core's watchdog workqueue */ 4700 priv->wq = mdev->priv.health.wq_watchdog; 4701 4702 err = mlx5_core_alloc_pd(mdev, &priv->pdn, 0); 4703 if (err) { 4704 mlx5_en_err(ifp, "mlx5_core_alloc_pd failed, %d\n", err); 4705 goto err_free_wq; 4706 } 4707 err = mlx5_alloc_transport_domain(mdev, &priv->tdn, 0); 4708 if (err) { 4709 mlx5_en_err(ifp, 4710 "mlx5_alloc_transport_domain failed, %d\n", err); 4711 goto err_dealloc_pd; 4712 } 4713 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr); 4714 if (err) { 4715 mlx5_en_err(ifp, "mlx5e_create_mkey failed, %d\n", err); 4716 goto err_dealloc_transport_domain; 4717 } 4718 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr); 4719 4720 /* check if we should generate a random MAC address */ 4721 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 && 4722 is_zero_ether_addr(dev_addr)) { 4723 random_ether_addr(dev_addr); 4724 mlx5_en_err(ifp, "Assigned random MAC address\n"); 4725 } 4726 4727 err = mlx5e_rl_init(priv); 4728 if (err) { 4729 mlx5_en_err(ifp, "mlx5e_rl_init failed, %d\n", err); 4730 goto err_create_mkey; 4731 } 4732 4733 err = mlx5e_tls_init(priv); 4734 if (err) { 4735 if_printf(ifp, "%s: mlx5e_tls_init failed\n", __func__); 4736 goto err_rl_init; 4737 } 4738 4739 if ((if_getcapenable2(ifp) & IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD)) != 0) { 4740 err = mlx5e_ipsec_init(priv); 4741 if (err) { 4742 if_printf(ifp, "%s: mlx5e_tls_init failed\n", __func__); 4743 goto err_tls_init; 4744 } 4745 } 4746 4747 err = mlx5e_open_drop_rq(priv, &priv->drop_rq); 4748 if (err) { 4749 if_printf(ifp, "%s: mlx5e_open_drop_rq failed (%d)\n", __func__, err); 4750 goto err_ipsec_init; 4751 } 4752 4753 err = mlx5e_open_rqts(priv); 4754 if (err) { 4755 if_printf(ifp, "%s: mlx5e_open_rqts failed (%d)\n", __func__, err); 4756 goto err_open_drop_rq; 4757 } 4758 4759 err = mlx5e_open_tirs(priv); 4760 if (err) { 4761 mlx5_en_err(ifp, "mlx5e_open_tirs() failed, %d\n", err); 4762 goto err_open_rqts; 4763 } 4764 4765 err = mlx5e_open_flow_tables(priv); 4766 if (err) { 4767 if_printf(ifp, "%s: mlx5e_open_flow_tables failed (%d)\n", __func__, err); 4768 goto err_open_tirs; 4769 } 4770 4771 err = mlx5e_tls_rx_init(priv); 4772 if (err) { 4773 if_printf(ifp, "%s: mlx5e_tls_rx_init() failed, %d\n", __func__, err); 4774 goto err_open_flow_tables; 4775 } 4776 4777 /* set default MTU */ 4778 mlx5e_set_dev_port_mtu(ifp, if_getmtu(ifp)); 4779 4780 /* Set default media status */ 4781 priv->media_status_last = IFM_AVALID; 4782 priv->media_active_last = IFM_ETHER | IFM_AUTO | IFM_FDX; 4783 4784 /* setup default pauseframes configuration */ 4785 mlx5e_setup_pauseframes(priv); 4786 4787 /* Setup supported medias */ 4788 if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) { 4789 ext = MLX5_CAP_PCAM_FEATURE(mdev, 4790 ptys_extended_ethernet); 4791 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 4792 eth_proto_capability); 4793 } else { 4794 ext = false; 4795 eth_proto_cap = 0; 4796 mlx5_en_err(ifp, "Query port media capability failed, %d\n", err); 4797 } 4798 4799 ifmedia_init(&priv->media, IFM_IMASK, 4800 mlx5e_media_change, mlx5e_media_status); 4801 4802 if (ext) { 4803 for (unsigned i = 0; i != MLX5E_EXT_LINK_SPEEDS_NUMBER; i++) { 4804 /* check if hardware has the right capability */ 4805 if (MLX5E_PROT_MASK(i) & ~eth_proto_cap) 4806 continue; 4807 for (unsigned j = 0; j != MLX5E_CABLE_TYPE_NUMBER; j++) { 4808 media_entry = mlx5e_ext_mode_table[i][j]; 4809 if (media_entry.subtype == 0) 4810 continue; 4811 /* check if this subtype was already added */ 4812 for (unsigned k = 0; k != i; k++) { 4813 /* check if hardware has the right capability */ 4814 if (MLX5E_PROT_MASK(k) & ~eth_proto_cap) 4815 continue; 4816 for (unsigned m = 0; m != MLX5E_CABLE_TYPE_NUMBER; m++) { 4817 if (media_entry.subtype == mlx5e_ext_mode_table[k][m].subtype) 4818 goto skip_ext_media; 4819 } 4820 } 4821 mlx5e_ifm_add(priv, media_entry.subtype); 4822 skip_ext_media:; 4823 } 4824 } 4825 } else { 4826 for (unsigned i = 0; i != MLX5E_LINK_SPEEDS_NUMBER; i++) { 4827 media_entry = mlx5e_mode_table[i]; 4828 if (media_entry.subtype == 0) 4829 continue; 4830 if (MLX5E_PROT_MASK(i) & ~eth_proto_cap) 4831 continue; 4832 /* check if this subtype was already added */ 4833 for (unsigned k = 0; k != i; k++) { 4834 if (media_entry.subtype == mlx5e_mode_table[k].subtype) 4835 goto skip_media; 4836 } 4837 mlx5e_ifm_add(priv, media_entry.subtype); 4838 4839 /* NOTE: 10G ER and LR shares the same entry */ 4840 if (media_entry.subtype == IFM_10G_ER) 4841 mlx5e_ifm_add(priv, IFM_10G_LR); 4842 skip_media:; 4843 } 4844 } 4845 4846 mlx5e_ifm_add(priv, IFM_AUTO); 4847 4848 /* Set autoselect by default */ 4849 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX | 4850 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE); 4851 4852 DEBUGNET_SET(ifp, mlx5_en); 4853 4854 ether_ifattach(ifp, dev_addr); 4855 4856 /* Register for VLAN events */ 4857 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config, 4858 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST); 4859 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig, 4860 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST); 4861 4862 /* Register for VxLAN events */ 4863 priv->vxlan_start = EVENTHANDLER_REGISTER(vxlan_start, 4864 mlx5e_vxlan_start, priv, EVENTHANDLER_PRI_ANY); 4865 priv->vxlan_stop = EVENTHANDLER_REGISTER(vxlan_stop, 4866 mlx5e_vxlan_stop, priv, EVENTHANDLER_PRI_ANY); 4867 4868 /* Link is down by default */ 4869 if_link_state_change(ifp, LINK_STATE_DOWN); 4870 4871 mlx5e_enable_async_events(priv); 4872 4873 mlx5e_add_hw_stats(priv); 4874 4875 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4876 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM, 4877 priv->stats.vport.arg); 4878 4879 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4880 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM, 4881 priv->stats.pport.arg); 4882 4883 mlx5e_create_ethtool(priv); 4884 4885 mtx_lock(&priv->async_events_mtx); 4886 mlx5e_update_stats(priv); 4887 mtx_unlock(&priv->async_events_mtx); 4888 4889 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4890 OID_AUTO, "rx_clbr_done", CTLFLAG_RD, 4891 &priv->clbr_done, 0, 4892 "RX timestamps calibration state"); 4893 callout_init(&priv->tstmp_clbr, 1); 4894 /* Pull out the frequency of the clock in hz */ 4895 priv->cclk = (uint64_t)MLX5_CAP_GEN(mdev, device_frequency_khz) * 1000ULL; 4896 mlx5e_reset_calibration_callout(priv); 4897 4898 pa.pa_version = PFIL_VERSION; 4899 pa.pa_flags = PFIL_IN; 4900 pa.pa_type = PFIL_TYPE_ETHERNET; 4901 pa.pa_headname = if_name(ifp); 4902 priv->pfil = pfil_head_register(&pa); 4903 4904 PRIV_LOCK(priv); 4905 err = mlx5e_open_flow_rules(priv); 4906 if (err) { 4907 mlx5_en_err(ifp, 4908 "mlx5e_open_flow_rules() failed, %d (ignored)\n", err); 4909 } 4910 PRIV_UNLOCK(priv); 4911 4912 return (priv); 4913 4914 err_open_flow_tables: 4915 mlx5e_close_flow_tables(priv); 4916 4917 err_open_tirs: 4918 mlx5e_close_tirs(priv); 4919 4920 err_open_rqts: 4921 mlx5e_close_rqts(priv); 4922 4923 err_open_drop_rq: 4924 mlx5e_close_drop_rq(&priv->drop_rq); 4925 4926 err_ipsec_init: 4927 mlx5e_ipsec_cleanup(priv); 4928 4929 err_tls_init: 4930 mlx5e_tls_cleanup(priv); 4931 4932 err_rl_init: 4933 mlx5e_rl_cleanup(priv); 4934 4935 err_create_mkey: 4936 mlx5_core_destroy_mkey(priv->mdev, &priv->mr); 4937 4938 err_dealloc_transport_domain: 4939 mlx5_dealloc_transport_domain(mdev, priv->tdn, 0); 4940 4941 err_dealloc_pd: 4942 mlx5_core_dealloc_pd(mdev, priv->pdn, 0); 4943 4944 err_free_wq: 4945 flush_workqueue(priv->wq); 4946 4947 err_free_sysctl: 4948 sysctl_ctx_free(&priv->sysctl_ctx); 4949 if (priv->sysctl_debug) 4950 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx); 4951 mlx5e_priv_static_destroy(priv, mdev, mdev->priv.eq_table.num_comp_vectors); 4952 4953 err_free_ifp: 4954 if_free(ifp); 4955 free(priv, M_MLX5EN); 4956 return (NULL); 4957 } 4958 4959 static void 4960 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv) 4961 { 4962 struct mlx5e_priv *priv = vpriv; 4963 if_t ifp = priv->ifp; 4964 4965 /* don't allow more IOCTLs */ 4966 priv->gone = 1; 4967 4968 /* XXX wait a bit to allow IOCTL handlers to complete */ 4969 pause("W", hz); 4970 4971 #ifdef RATELIMIT 4972 /* 4973 * Tell the TCP ratelimit code to release the rate-sets attached 4974 * to our ifnet. 4975 */ 4976 tcp_rl_release_ifnet(ifp); 4977 /* 4978 * The kernel can still have reference(s) via the m_snd_tag's into 4979 * the ratelimit channels, and these must go away before 4980 * detaching: 4981 */ 4982 while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) { 4983 mlx5_en_err(priv->ifp, 4984 "Waiting for all ratelimit connections to terminate\n"); 4985 pause("W", hz); 4986 } 4987 #endif 4988 4989 #ifdef KERN_TLS 4990 /* wait for all TLS tags to get freed */ 4991 while (priv->tls.init != 0 && 4992 uma_zone_get_cur(priv->tls.zone) != 0) { 4993 mlx5_en_err(priv->ifp, 4994 "Waiting for all TLS connections to terminate\n"); 4995 pause("W", hz); 4996 } 4997 4998 /* wait for all TLS RX tags to get freed */ 4999 while (priv->tls_rx.init != 0 && 5000 uma_zone_get_cur(priv->tls_rx.zone) != 0) { 5001 mlx5_en_err(priv->ifp, 5002 "Waiting for all TLS RX connections to terminate\n"); 5003 pause("W", hz); 5004 } 5005 #endif 5006 /* wait for all unlimited send tags to complete */ 5007 mlx5e_priv_wait_for_completion(priv, mdev->priv.eq_table.num_comp_vectors); 5008 5009 /* stop watchdog timer */ 5010 callout_drain(&priv->watchdog); 5011 5012 callout_drain(&priv->tstmp_clbr); 5013 5014 if (priv->vlan_attach != NULL) 5015 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach); 5016 if (priv->vlan_detach != NULL) 5017 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach); 5018 if (priv->vxlan_start != NULL) 5019 EVENTHANDLER_DEREGISTER(vxlan_start, priv->vxlan_start); 5020 if (priv->vxlan_stop != NULL) 5021 EVENTHANDLER_DEREGISTER(vxlan_stop, priv->vxlan_stop); 5022 5023 /* make sure device gets closed */ 5024 PRIV_LOCK(priv); 5025 mlx5e_close_locked(ifp); 5026 mlx5e_close_flow_rules(priv); 5027 PRIV_UNLOCK(priv); 5028 5029 /* deregister pfil */ 5030 if (priv->pfil != NULL) { 5031 pfil_head_unregister(priv->pfil); 5032 priv->pfil = NULL; 5033 } 5034 5035 /* unregister device */ 5036 ifmedia_removeall(&priv->media); 5037 ether_ifdetach(ifp); 5038 5039 mlx5e_tls_rx_cleanup(priv); 5040 #ifdef IPSEC_OFFLOAD 5041 ipsec_accel_on_ifdown(priv->ifp); 5042 #endif 5043 mlx5e_close_flow_tables(priv); 5044 mlx5e_close_tirs(priv); 5045 mlx5e_close_rqts(priv); 5046 mlx5e_close_drop_rq(&priv->drop_rq); 5047 mlx5e_ipsec_cleanup(priv); 5048 mlx5e_tls_cleanup(priv); 5049 mlx5e_rl_cleanup(priv); 5050 5051 /* destroy all remaining sysctl nodes */ 5052 sysctl_ctx_free(&priv->stats.vport.ctx); 5053 sysctl_ctx_free(&priv->stats.pport.ctx); 5054 if (priv->sysctl_debug) 5055 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx); 5056 sysctl_ctx_free(&priv->sysctl_ctx); 5057 5058 mlx5_core_destroy_mkey(priv->mdev, &priv->mr); 5059 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn, 0); 5060 mlx5_core_dealloc_pd(priv->mdev, priv->pdn, 0); 5061 mlx5e_disable_async_events(priv); 5062 flush_workqueue(priv->wq); 5063 mlx5e_priv_static_destroy(priv, mdev, mdev->priv.eq_table.num_comp_vectors); 5064 if_free(ifp); 5065 free(priv, M_MLX5EN); 5066 } 5067 5068 #ifdef DEBUGNET 5069 static void 5070 mlx5_en_debugnet_init(if_t dev, int *nrxr, int *ncl, int *clsize) 5071 { 5072 struct mlx5e_priv *priv = if_getsoftc(dev); 5073 5074 PRIV_LOCK(priv); 5075 *nrxr = priv->params.num_channels; 5076 *ncl = DEBUGNET_MAX_IN_FLIGHT; 5077 *clsize = MLX5E_MAX_RX_BYTES; 5078 PRIV_UNLOCK(priv); 5079 } 5080 5081 static void 5082 mlx5_en_debugnet_event(if_t dev, enum debugnet_ev event) 5083 { 5084 } 5085 5086 static int 5087 mlx5_en_debugnet_transmit(if_t dev, struct mbuf *m) 5088 { 5089 struct mlx5e_priv *priv = if_getsoftc(dev); 5090 struct mlx5e_sq *sq; 5091 int err; 5092 5093 if ((if_getdrvflags(dev) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 5094 IFF_DRV_RUNNING || (priv->media_status_last & IFM_ACTIVE) == 0) 5095 return (ENOENT); 5096 5097 sq = &priv->channel[0].sq[0]; 5098 5099 if (sq->running == 0) { 5100 m_freem(m); 5101 return (ENOENT); 5102 } 5103 5104 if (mlx5e_sq_xmit(sq, &m) != 0) { 5105 m_freem(m); 5106 err = ENOBUFS; 5107 } else { 5108 err = 0; 5109 } 5110 5111 mlx5e_tx_notify_hw(sq, true); 5112 5113 return (err); 5114 } 5115 5116 static int 5117 mlx5_en_debugnet_poll(if_t dev, int count) 5118 { 5119 struct mlx5e_priv *priv = if_getsoftc(dev); 5120 5121 if ((if_getdrvflags(dev) & IFF_DRV_RUNNING) == 0 || 5122 (priv->media_status_last & IFM_ACTIVE) == 0) 5123 return (ENOENT); 5124 5125 mlx5_poll_interrupts(priv->mdev); 5126 5127 return (0); 5128 } 5129 #endif /* DEBUGNET */ 5130 5131 static void * 5132 mlx5e_get_ifp(void *vpriv) 5133 { 5134 struct mlx5e_priv *priv = vpriv; 5135 5136 return (priv->ifp); 5137 } 5138 5139 static struct mlx5_interface mlx5e_interface = { 5140 .add = mlx5e_create_ifp, 5141 .remove = mlx5e_destroy_ifp, 5142 .event = mlx5e_async_event, 5143 .protocol = MLX5_INTERFACE_PROTOCOL_ETH, 5144 .get_dev = mlx5e_get_ifp, 5145 }; 5146 5147 void 5148 mlx5e_init(void) 5149 { 5150 mlx5_register_interface(&mlx5e_interface); 5151 } 5152 5153 void 5154 mlx5e_cleanup(void) 5155 { 5156 mlx5_unregister_interface(&mlx5e_interface); 5157 } 5158 5159 module_init_order(mlx5e_init, SI_ORDER_SIXTH); 5160 module_exit_order(mlx5e_cleanup, SI_ORDER_SIXTH); 5161 5162 MODULE_DEPEND(mlx5en, ipsec, 1, 1, 1); 5163 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1); 5164 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1); 5165 MODULE_VERSION(mlx5en, 1); 5166