1 /*- 2 * Copyright (c) 2015-2021 Mellanox Technologies. All rights reserved. 3 * Copyright (c) 2022 NVIDIA corporation & affiliates. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include "opt_ipsec.h" 28 #include "opt_kern_tls.h" 29 #include "opt_rss.h" 30 #include "opt_ratelimit.h" 31 32 #include <dev/mlx5/mlx5_en/en.h> 33 34 #include <sys/eventhandler.h> 35 #include <sys/sockio.h> 36 #include <machine/atomic.h> 37 38 #include <net/debugnet.h> 39 #include <netinet/tcp_ratelimit.h> 40 #include <netipsec/keydb.h> 41 #include <netipsec/ipsec_offload.h> 42 43 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs); 44 static if_snd_tag_query_t mlx5e_ul_snd_tag_query; 45 static if_snd_tag_free_t mlx5e_ul_snd_tag_free; 46 47 struct mlx5e_channel_param { 48 struct mlx5e_rq_param rq; 49 struct mlx5e_sq_param sq; 50 struct mlx5e_cq_param rx_cq; 51 struct mlx5e_cq_param tx_cq; 52 }; 53 54 struct media { 55 u32 subtype; 56 u64 baudrate; 57 }; 58 59 static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER] = 60 { 61 [MLX5E_1000BASE_CX_SGMII] = { 62 .subtype = IFM_1000_CX_SGMII, 63 .baudrate = IF_Mbps(1000ULL), 64 }, 65 [MLX5E_1000BASE_KX] = { 66 .subtype = IFM_1000_KX, 67 .baudrate = IF_Mbps(1000ULL), 68 }, 69 [MLX5E_10GBASE_CX4] = { 70 .subtype = IFM_10G_CX4, 71 .baudrate = IF_Gbps(10ULL), 72 }, 73 [MLX5E_10GBASE_KX4] = { 74 .subtype = IFM_10G_KX4, 75 .baudrate = IF_Gbps(10ULL), 76 }, 77 [MLX5E_10GBASE_KR] = { 78 .subtype = IFM_10G_KR, 79 .baudrate = IF_Gbps(10ULL), 80 }, 81 [MLX5E_20GBASE_KR2] = { 82 .subtype = IFM_20G_KR2, 83 .baudrate = IF_Gbps(20ULL), 84 }, 85 [MLX5E_40GBASE_CR4] = { 86 .subtype = IFM_40G_CR4, 87 .baudrate = IF_Gbps(40ULL), 88 }, 89 [MLX5E_40GBASE_KR4] = { 90 .subtype = IFM_40G_KR4, 91 .baudrate = IF_Gbps(40ULL), 92 }, 93 [MLX5E_56GBASE_R4] = { 94 .subtype = IFM_56G_R4, 95 .baudrate = IF_Gbps(56ULL), 96 }, 97 [MLX5E_10GBASE_CR] = { 98 .subtype = IFM_10G_CR1, 99 .baudrate = IF_Gbps(10ULL), 100 }, 101 [MLX5E_10GBASE_SR] = { 102 .subtype = IFM_10G_SR, 103 .baudrate = IF_Gbps(10ULL), 104 }, 105 [MLX5E_10GBASE_ER_LR] = { 106 .subtype = IFM_10G_ER, 107 .baudrate = IF_Gbps(10ULL), 108 }, 109 [MLX5E_40GBASE_SR4] = { 110 .subtype = IFM_40G_SR4, 111 .baudrate = IF_Gbps(40ULL), 112 }, 113 [MLX5E_40GBASE_LR4_ER4] = { 114 .subtype = IFM_40G_LR4, 115 .baudrate = IF_Gbps(40ULL), 116 }, 117 [MLX5E_100GBASE_CR4] = { 118 .subtype = IFM_100G_CR4, 119 .baudrate = IF_Gbps(100ULL), 120 }, 121 [MLX5E_100GBASE_SR4] = { 122 .subtype = IFM_100G_SR4, 123 .baudrate = IF_Gbps(100ULL), 124 }, 125 [MLX5E_100GBASE_KR4] = { 126 .subtype = IFM_100G_KR4, 127 .baudrate = IF_Gbps(100ULL), 128 }, 129 [MLX5E_100GBASE_LR4] = { 130 .subtype = IFM_100G_LR4, 131 .baudrate = IF_Gbps(100ULL), 132 }, 133 [MLX5E_100BASE_TX] = { 134 .subtype = IFM_100_TX, 135 .baudrate = IF_Mbps(100ULL), 136 }, 137 [MLX5E_1000BASE_T] = { 138 .subtype = IFM_1000_T, 139 .baudrate = IF_Mbps(1000ULL), 140 }, 141 [MLX5E_10GBASE_T] = { 142 .subtype = IFM_10G_T, 143 .baudrate = IF_Gbps(10ULL), 144 }, 145 [MLX5E_25GBASE_CR] = { 146 .subtype = IFM_25G_CR, 147 .baudrate = IF_Gbps(25ULL), 148 }, 149 [MLX5E_25GBASE_KR] = { 150 .subtype = IFM_25G_KR, 151 .baudrate = IF_Gbps(25ULL), 152 }, 153 [MLX5E_25GBASE_SR] = { 154 .subtype = IFM_25G_SR, 155 .baudrate = IF_Gbps(25ULL), 156 }, 157 [MLX5E_50GBASE_CR2] = { 158 .subtype = IFM_50G_CR2, 159 .baudrate = IF_Gbps(50ULL), 160 }, 161 [MLX5E_50GBASE_KR2] = { 162 .subtype = IFM_50G_KR2, 163 .baudrate = IF_Gbps(50ULL), 164 }, 165 [MLX5E_50GBASE_KR4] = { 166 .subtype = IFM_50G_KR4, 167 .baudrate = IF_Gbps(50ULL), 168 }, 169 }; 170 171 static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_CABLE_TYPE_NUMBER] = 172 { 173 /**/ 174 [MLX5E_SGMII_100M][MLX5E_CABLE_TYPE_UNKNOWN] = { 175 .subtype = IFM_100_SGMII, 176 .baudrate = IF_Mbps(100), 177 }, 178 179 /**/ 180 [MLX5E_1000BASE_X_SGMII][MLX5E_CABLE_TYPE_UNKNOWN] = { 181 .subtype = IFM_1000_CX, 182 .baudrate = IF_Mbps(1000), 183 }, 184 [MLX5E_1000BASE_X_SGMII][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 185 .subtype = IFM_1000_SX, 186 .baudrate = IF_Mbps(1000), 187 }, 188 189 /**/ 190 [MLX5E_5GBASE_R][MLX5E_CABLE_TYPE_UNKNOWN] = { 191 .subtype = IFM_5000_KR, 192 .baudrate = IF_Mbps(5000), 193 }, 194 [MLX5E_5GBASE_R][MLX5E_CABLE_TYPE_TWISTED_PAIR] = { 195 .subtype = IFM_5000_T, 196 .baudrate = IF_Mbps(5000), 197 }, 198 199 /**/ 200 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CABLE_TYPE_UNKNOWN] = { 201 .subtype = IFM_10G_KR, 202 .baudrate = IF_Gbps(10ULL), 203 }, 204 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 205 .subtype = IFM_10G_CR1, 206 .baudrate = IF_Gbps(10ULL), 207 }, 208 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 209 .subtype = IFM_10G_SR, 210 .baudrate = IF_Gbps(10ULL), 211 }, 212 213 /**/ 214 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CABLE_TYPE_UNKNOWN] = { 215 .subtype = IFM_40G_KR4, 216 .baudrate = IF_Gbps(40ULL), 217 }, 218 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 219 .subtype = IFM_40G_CR4, 220 .baudrate = IF_Gbps(40ULL), 221 }, 222 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 223 .subtype = IFM_40G_SR4, 224 .baudrate = IF_Gbps(40ULL), 225 }, 226 227 /**/ 228 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_UNKNOWN] = { 229 .subtype = IFM_25G_KR, 230 .baudrate = IF_Gbps(25ULL), 231 }, 232 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 233 .subtype = IFM_25G_CR, 234 .baudrate = IF_Gbps(25ULL), 235 }, 236 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 237 .subtype = IFM_25G_SR, 238 .baudrate = IF_Gbps(25ULL), 239 }, 240 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_TWISTED_PAIR] = { 241 .subtype = IFM_25G_T, 242 .baudrate = IF_Gbps(25ULL), 243 }, 244 245 /**/ 246 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CABLE_TYPE_UNKNOWN] = { 247 .subtype = IFM_50G_KR2, 248 .baudrate = IF_Gbps(50ULL), 249 }, 250 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 251 .subtype = IFM_50G_CR2, 252 .baudrate = IF_Gbps(50ULL), 253 }, 254 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 255 .subtype = IFM_50G_SR2, 256 .baudrate = IF_Gbps(50ULL), 257 }, 258 259 /**/ 260 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CABLE_TYPE_UNKNOWN] = { 261 .subtype = IFM_50G_KR_PAM4, 262 .baudrate = IF_Gbps(50ULL), 263 }, 264 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 265 .subtype = IFM_50G_CP, 266 .baudrate = IF_Gbps(50ULL), 267 }, 268 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 269 .subtype = IFM_50G_SR, 270 .baudrate = IF_Gbps(50ULL), 271 }, 272 273 /**/ 274 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CABLE_TYPE_UNKNOWN] = { 275 .subtype = IFM_100G_KR4, 276 .baudrate = IF_Gbps(100ULL), 277 }, 278 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 279 .subtype = IFM_100G_CR4, 280 .baudrate = IF_Gbps(100ULL), 281 }, 282 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 283 .subtype = IFM_100G_SR4, 284 .baudrate = IF_Gbps(100ULL), 285 }, 286 287 /**/ 288 [MLX5E_100GAUI_1_100GBASE_CR_KR][MLX5E_CABLE_TYPE_UNKNOWN] = { 289 .subtype = IFM_100G_KR_PAM4, 290 .baudrate = IF_Gbps(100ULL), 291 }, 292 [MLX5E_100GAUI_1_100GBASE_CR_KR][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 293 .subtype = IFM_100G_CR_PAM4, 294 .baudrate = IF_Gbps(100ULL), 295 }, 296 [MLX5E_100GAUI_1_100GBASE_CR_KR][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 297 .subtype = IFM_100G_SR2, /* XXX */ 298 .baudrate = IF_Gbps(100ULL), 299 }, 300 301 /**/ 302 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CABLE_TYPE_UNKNOWN] = { 303 .subtype = IFM_100G_KR4, 304 .baudrate = IF_Gbps(100ULL), 305 }, 306 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 307 .subtype = IFM_100G_CP2, 308 .baudrate = IF_Gbps(100ULL), 309 }, 310 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 311 .subtype = IFM_100G_SR2, 312 .baudrate = IF_Gbps(100ULL), 313 }, 314 315 /**/ 316 [MLX5E_200GAUI_2_200GBASE_CR2_KR2][MLX5E_CABLE_TYPE_UNKNOWN] = { 317 .subtype = IFM_200G_KR4_PAM4, /* XXX */ 318 .baudrate = IF_Gbps(200ULL), 319 }, 320 [MLX5E_200GAUI_2_200GBASE_CR2_KR2][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 321 .subtype = IFM_200G_CR4_PAM4, /* XXX */ 322 .baudrate = IF_Gbps(200ULL), 323 }, 324 [MLX5E_200GAUI_2_200GBASE_CR2_KR2][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 325 .subtype = IFM_200G_SR4, /* XXX */ 326 .baudrate = IF_Gbps(200ULL), 327 }, 328 329 /**/ 330 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CABLE_TYPE_UNKNOWN] = { 331 .subtype = IFM_200G_KR4_PAM4, 332 .baudrate = IF_Gbps(200ULL), 333 }, 334 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 335 .subtype = IFM_200G_CR4_PAM4, 336 .baudrate = IF_Gbps(200ULL), 337 }, 338 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 339 .subtype = IFM_200G_SR4, 340 .baudrate = IF_Gbps(200ULL), 341 }, 342 343 /**/ 344 [MLX5E_400GAUI_8][MLX5E_CABLE_TYPE_UNKNOWN] = { 345 .subtype = IFM_400G_LR8, /* XXX */ 346 .baudrate = IF_Gbps(400ULL), 347 }, 348 349 /**/ 350 [MLX5E_400GAUI_4_400GBASE_CR4_KR4][MLX5E_CABLE_TYPE_UNKNOWN] = { 351 .subtype = IFM_400G_LR8, /* XXX */ 352 .baudrate = IF_Gbps(400ULL), 353 }, 354 }; 355 356 static const struct if_snd_tag_sw mlx5e_ul_snd_tag_sw = { 357 .snd_tag_query = mlx5e_ul_snd_tag_query, 358 .snd_tag_free = mlx5e_ul_snd_tag_free, 359 .type = IF_SND_TAG_TYPE_UNLIMITED 360 }; 361 362 DEBUGNET_DEFINE(mlx5_en); 363 364 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet"); 365 366 static void 367 mlx5e_update_carrier(struct mlx5e_priv *priv) 368 { 369 struct mlx5_core_dev *mdev = priv->mdev; 370 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 371 u32 eth_proto_oper; 372 int error; 373 u8 i; 374 u8 cable_type; 375 u8 port_state; 376 u8 is_er_type; 377 bool ext; 378 struct media media_entry = {}; 379 380 port_state = mlx5_query_vport_state(mdev, 381 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0); 382 383 if (port_state == VPORT_STATE_UP) { 384 priv->media_status_last |= IFM_ACTIVE; 385 } else { 386 priv->media_status_last &= ~IFM_ACTIVE; 387 priv->media_active_last = IFM_ETHER; 388 if_link_state_change(priv->ifp, LINK_STATE_DOWN); 389 return; 390 } 391 392 error = mlx5_query_port_ptys(mdev, out, sizeof(out), 393 MLX5_PTYS_EN, 1); 394 if (error) { 395 priv->media_active_last = IFM_ETHER; 396 if_setbaudrate(priv->ifp, 1); 397 mlx5_en_err(priv->ifp, "query port ptys failed: 0x%x\n", 398 error); 399 return; 400 } 401 402 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet); 403 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 404 eth_proto_oper); 405 406 i = ilog2(eth_proto_oper); 407 408 if (ext) { 409 error = mlx5_query_pddr_cable_type(mdev, 1, &cable_type); 410 if (error != 0) { 411 /* use fallback entry */ 412 media_entry = mlx5e_ext_mode_table[i][MLX5E_CABLE_TYPE_UNKNOWN]; 413 414 mlx5_en_err(priv->ifp, 415 "query port pddr failed: %d\n", error); 416 } else { 417 media_entry = mlx5e_ext_mode_table[i][cable_type]; 418 419 /* check if we should use fallback entry */ 420 if (media_entry.subtype == 0) 421 media_entry = mlx5e_ext_mode_table[i][MLX5E_CABLE_TYPE_UNKNOWN]; 422 } 423 } else { 424 media_entry = mlx5e_mode_table[i]; 425 } 426 427 if (media_entry.subtype == 0) { 428 mlx5_en_err(priv->ifp, 429 "Could not find operational media subtype\n"); 430 return; 431 } 432 433 switch (media_entry.subtype) { 434 case IFM_10G_ER: 435 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type); 436 if (error != 0) { 437 mlx5_en_err(priv->ifp, 438 "query port pddr failed: %d\n", error); 439 } 440 if (error != 0 || is_er_type == 0) 441 media_entry.subtype = IFM_10G_LR; 442 break; 443 case IFM_40G_LR4: 444 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type); 445 if (error != 0) { 446 mlx5_en_err(priv->ifp, 447 "query port pddr failed: %d\n", error); 448 } 449 if (error == 0 && is_er_type != 0) 450 media_entry.subtype = IFM_40G_ER4; 451 break; 452 } 453 priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX; 454 if_setbaudrate(priv->ifp, media_entry.baudrate); 455 456 if_link_state_change(priv->ifp, LINK_STATE_UP); 457 } 458 459 static void 460 mlx5e_media_status(if_t dev, struct ifmediareq *ifmr) 461 { 462 struct mlx5e_priv *priv = if_getsoftc(dev); 463 464 ifmr->ifm_status = priv->media_status_last; 465 ifmr->ifm_current = ifmr->ifm_active = priv->media_active_last | 466 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) | 467 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0); 468 469 } 470 471 static u32 472 mlx5e_find_link_mode(u32 subtype, bool ext) 473 { 474 u32 link_mode = 0; 475 476 switch (subtype) { 477 case 0: 478 goto done; 479 case IFM_10G_LR: 480 subtype = IFM_10G_ER; 481 break; 482 case IFM_40G_ER4: 483 subtype = IFM_40G_LR4; 484 break; 485 default: 486 break; 487 } 488 489 if (ext) { 490 for (unsigned i = 0; i != MLX5E_EXT_LINK_SPEEDS_NUMBER; i++) { 491 for (unsigned j = 0; j != MLX5E_CABLE_TYPE_NUMBER; j++) { 492 if (mlx5e_ext_mode_table[i][j].subtype == subtype) 493 link_mode |= MLX5E_PROT_MASK(i); 494 } 495 } 496 } else { 497 for (unsigned i = 0; i != MLX5E_LINK_SPEEDS_NUMBER; i++) { 498 if (mlx5e_mode_table[i].subtype == subtype) 499 link_mode |= MLX5E_PROT_MASK(i); 500 } 501 } 502 done: 503 return (link_mode); 504 } 505 506 static int 507 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv) 508 { 509 return (mlx5_set_port_pause_and_pfc(priv->mdev, 1, 510 priv->params.rx_pauseframe_control, 511 priv->params.tx_pauseframe_control, 512 priv->params.rx_priority_flow_control, 513 priv->params.tx_priority_flow_control)); 514 } 515 516 static int 517 mlx5e_set_port_pfc(struct mlx5e_priv *priv) 518 { 519 int error; 520 521 if (priv->gone != 0) { 522 error = -ENXIO; 523 } else if (priv->params.rx_pauseframe_control || 524 priv->params.tx_pauseframe_control) { 525 mlx5_en_err(priv->ifp, 526 "Global pauseframes must be disabled before enabling PFC.\n"); 527 error = -EINVAL; 528 } else { 529 error = mlx5e_set_port_pause_and_pfc(priv); 530 } 531 return (error); 532 } 533 534 static int 535 mlx5e_media_change(if_t dev) 536 { 537 struct mlx5e_priv *priv = if_getsoftc(dev); 538 struct mlx5_core_dev *mdev = priv->mdev; 539 u32 eth_proto_cap; 540 u32 link_mode; 541 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 542 int was_opened; 543 int locked; 544 int error; 545 bool ext; 546 547 locked = PRIV_LOCKED(priv); 548 if (!locked) 549 PRIV_LOCK(priv); 550 551 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) { 552 error = EINVAL; 553 goto done; 554 } 555 556 error = mlx5_query_port_ptys(mdev, out, sizeof(out), 557 MLX5_PTYS_EN, 1); 558 if (error != 0) { 559 mlx5_en_err(dev, "Query port media capability failed\n"); 560 goto done; 561 } 562 563 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet); 564 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext); 565 566 /* query supported capabilities */ 567 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 568 eth_proto_capability); 569 570 /* check for autoselect */ 571 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) { 572 link_mode = eth_proto_cap; 573 if (link_mode == 0) { 574 mlx5_en_err(dev, "Port media capability is zero\n"); 575 error = EINVAL; 576 goto done; 577 } 578 } else { 579 link_mode = link_mode & eth_proto_cap; 580 if (link_mode == 0) { 581 mlx5_en_err(dev, "Not supported link mode requested\n"); 582 error = EINVAL; 583 goto done; 584 } 585 } 586 if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) { 587 /* check if PFC is enabled */ 588 if (priv->params.rx_priority_flow_control || 589 priv->params.tx_priority_flow_control) { 590 mlx5_en_err(dev, "PFC must be disabled before enabling global pauseframes.\n"); 591 error = EINVAL; 592 goto done; 593 } 594 } 595 /* update pauseframe control bits */ 596 priv->params.rx_pauseframe_control = 597 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0; 598 priv->params.tx_pauseframe_control = 599 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0; 600 601 /* check if device is opened */ 602 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 603 604 /* reconfigure the hardware */ 605 mlx5_set_port_status(mdev, MLX5_PORT_DOWN); 606 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext); 607 error = -mlx5e_set_port_pause_and_pfc(priv); 608 if (was_opened) 609 mlx5_set_port_status(mdev, MLX5_PORT_UP); 610 611 done: 612 if (!locked) 613 PRIV_UNLOCK(priv); 614 return (error); 615 } 616 617 static void 618 mlx5e_update_carrier_work(struct work_struct *work) 619 { 620 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 621 update_carrier_work); 622 623 PRIV_LOCK(priv); 624 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) 625 mlx5e_update_carrier(priv); 626 PRIV_UNLOCK(priv); 627 } 628 629 #define MLX5E_PCIE_PERF_GET_64(a,b,c,d,e,f) \ 630 s_debug->c = MLX5_GET64(mpcnt_reg, out, counter_set.f.c); 631 632 #define MLX5E_PCIE_PERF_GET_32(a,b,c,d,e,f) \ 633 s_debug->c = MLX5_GET(mpcnt_reg, out, counter_set.f.c); 634 635 static void 636 mlx5e_update_pcie_counters(struct mlx5e_priv *priv) 637 { 638 struct mlx5_core_dev *mdev = priv->mdev; 639 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug; 640 const unsigned sz = MLX5_ST_SZ_BYTES(mpcnt_reg); 641 void *out; 642 void *in; 643 int err; 644 645 /* allocate firmware request structures */ 646 in = mlx5_vzalloc(sz); 647 out = mlx5_vzalloc(sz); 648 if (in == NULL || out == NULL) 649 goto free_out; 650 651 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP); 652 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 653 if (err != 0) 654 goto free_out; 655 656 MLX5E_PCIE_PERFORMANCE_COUNTERS_64(MLX5E_PCIE_PERF_GET_64) 657 MLX5E_PCIE_PERFORMANCE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 658 659 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP); 660 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 661 if (err != 0) 662 goto free_out; 663 664 MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 665 666 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_LANE_COUNTERS_GROUP); 667 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 668 if (err != 0) 669 goto free_out; 670 671 MLX5E_PCIE_LANE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 672 673 free_out: 674 /* free firmware request structures */ 675 kvfree(in); 676 kvfree(out); 677 } 678 679 /* 680 * This function reads the physical port counters from the firmware 681 * using a pre-defined layout defined by various MLX5E_PPORT_XXX() 682 * macros. The output is converted from big-endian 64-bit values into 683 * host endian ones and stored in the "priv->stats.pport" structure. 684 */ 685 static void 686 mlx5e_update_pport_counters(struct mlx5e_priv *priv) 687 { 688 struct mlx5_core_dev *mdev = priv->mdev; 689 struct mlx5e_pport_stats *s = &priv->stats.pport; 690 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug; 691 u32 *in; 692 u32 *out; 693 const u64 *ptr; 694 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 695 unsigned x; 696 unsigned y; 697 unsigned z; 698 699 /* allocate firmware request structures */ 700 in = mlx5_vzalloc(sz); 701 out = mlx5_vzalloc(sz); 702 if (in == NULL || out == NULL) 703 goto free_out; 704 705 /* 706 * Get pointer to the 64-bit counter set which is located at a 707 * fixed offset in the output firmware request structure: 708 */ 709 ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set); 710 711 MLX5_SET(ppcnt_reg, in, local_port, 1); 712 713 /* read IEEE802_3 counter group using predefined counter layout */ 714 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP); 715 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 716 for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM; 717 x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++) 718 s->arg[y] = be64toh(ptr[x]); 719 720 /* read RFC2819 counter group using predefined counter layout */ 721 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP); 722 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 723 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++) 724 s->arg[y] = be64toh(ptr[x]); 725 726 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM + 727 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++) 728 s_debug->arg[y] = be64toh(ptr[x]); 729 730 /* read RFC2863 counter group using predefined counter layout */ 731 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP); 732 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 733 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++) 734 s_debug->arg[y] = be64toh(ptr[x]); 735 736 /* read physical layer stats counter group using predefined counter layout */ 737 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP); 738 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 739 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++) 740 s_debug->arg[y] = be64toh(ptr[x]); 741 742 /* read Extended Ethernet counter group using predefined counter layout */ 743 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP); 744 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 745 for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++) 746 s_debug->arg[y] = be64toh(ptr[x]); 747 748 /* read Extended Statistical Group */ 749 if (MLX5_CAP_GEN(mdev, pcam_reg) && 750 MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) && 751 MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) { 752 /* read Extended Statistical counter group using predefined counter layout */ 753 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP); 754 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 755 756 for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++) 757 s_debug->arg[y] = be64toh(ptr[x]); 758 } 759 760 /* read PCIE counters */ 761 mlx5e_update_pcie_counters(priv); 762 763 /* read per-priority counters */ 764 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP); 765 766 /* iterate all the priorities */ 767 for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) { 768 MLX5_SET(ppcnt_reg, in, prio_tc, z); 769 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 770 771 /* read per priority stats counter group using predefined counter layout */ 772 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM / 773 MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++) 774 s->arg[y] = be64toh(ptr[x]); 775 } 776 777 free_out: 778 /* free firmware request structures */ 779 kvfree(in); 780 kvfree(out); 781 } 782 783 static void 784 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv) 785 { 786 u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {}; 787 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {}; 788 789 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard)) 790 return; 791 792 MLX5_SET(query_vnic_env_in, in, opcode, 793 MLX5_CMD_OP_QUERY_VNIC_ENV); 794 MLX5_SET(query_vnic_env_in, in, op_mod, 0); 795 MLX5_SET(query_vnic_env_in, in, other_vport, 0); 796 797 if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0) 798 return; 799 800 priv->stats.vport.rx_steer_missed_packets = 801 MLX5_GET64(query_vnic_env_out, out, 802 vport_env.nic_receive_steering_discard); 803 } 804 805 /* 806 * This function is called regularly to collect all statistics 807 * counters from the firmware. The values can be viewed through the 808 * sysctl interface. Execution is serialized using the priv's global 809 * configuration lock. 810 */ 811 static void 812 mlx5e_update_stats_locked(struct mlx5e_priv *priv) 813 { 814 struct mlx5_core_dev *mdev = priv->mdev; 815 struct mlx5e_vport_stats *s = &priv->stats.vport; 816 struct mlx5e_sq_stats *sq_stats; 817 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)]; 818 u32 *out; 819 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out); 820 u64 tso_packets = 0; 821 u64 tso_bytes = 0; 822 u64 tx_queue_dropped = 0; 823 u64 tx_defragged = 0; 824 u64 tx_offload_none = 0; 825 u64 lro_packets = 0; 826 u64 lro_bytes = 0; 827 u64 sw_lro_queued = 0; 828 u64 sw_lro_flushed = 0; 829 u64 rx_csum_none = 0; 830 u64 rx_wqe_err = 0; 831 u64 rx_packets = 0; 832 u64 rx_bytes = 0; 833 u64 rx_decrypted_error = 0; 834 u64 rx_decrypted_ok = 0; 835 u32 rx_out_of_buffer = 0; 836 int error; 837 int i; 838 int j; 839 840 out = mlx5_vzalloc(outlen); 841 if (out == NULL) 842 goto free_out; 843 844 /* Collect firts the SW counters and then HW for consistency */ 845 for (i = 0; i < priv->params.num_channels; i++) { 846 struct mlx5e_channel *pch = priv->channel + i; 847 struct mlx5e_rq *rq = &pch->rq; 848 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats; 849 850 /* collect stats from LRO */ 851 rq_stats->sw_lro_queued = rq->lro.lro_queued; 852 rq_stats->sw_lro_flushed = rq->lro.lro_flushed; 853 sw_lro_queued += rq_stats->sw_lro_queued; 854 sw_lro_flushed += rq_stats->sw_lro_flushed; 855 lro_packets += rq_stats->lro_packets; 856 lro_bytes += rq_stats->lro_bytes; 857 rx_csum_none += rq_stats->csum_none; 858 rx_wqe_err += rq_stats->wqe_err; 859 rx_packets += rq_stats->packets; 860 rx_bytes += rq_stats->bytes; 861 rx_decrypted_error += rq_stats->decrypted_error_packets; 862 rx_decrypted_ok += rq_stats->decrypted_ok_packets; 863 864 for (j = 0; j < priv->num_tc; j++) { 865 sq_stats = &pch->sq[j].stats; 866 867 tso_packets += sq_stats->tso_packets; 868 tso_bytes += sq_stats->tso_bytes; 869 tx_queue_dropped += sq_stats->dropped; 870 tx_queue_dropped += sq_stats->enobuf; 871 tx_defragged += sq_stats->defragged; 872 tx_offload_none += sq_stats->csum_offload_none; 873 } 874 } 875 876 #ifdef RATELIMIT 877 /* Collect statistics from all rate-limit queues */ 878 for (j = 0; j < priv->rl.param.tx_worker_threads_def; j++) { 879 struct mlx5e_rl_worker *rlw = priv->rl.workers + j; 880 881 for (i = 0; i < priv->rl.param.tx_channels_per_worker_def; i++) { 882 struct mlx5e_rl_channel *channel = rlw->channels + i; 883 struct mlx5e_sq *sq = channel->sq; 884 885 if (sq == NULL) 886 continue; 887 888 sq_stats = &sq->stats; 889 890 tso_packets += sq_stats->tso_packets; 891 tso_bytes += sq_stats->tso_bytes; 892 tx_queue_dropped += sq_stats->dropped; 893 tx_queue_dropped += sq_stats->enobuf; 894 tx_defragged += sq_stats->defragged; 895 tx_offload_none += sq_stats->csum_offload_none; 896 } 897 } 898 #endif 899 900 /* update counters */ 901 s->tso_packets = tso_packets; 902 s->tso_bytes = tso_bytes; 903 s->tx_queue_dropped = tx_queue_dropped; 904 s->tx_defragged = tx_defragged; 905 s->lro_packets = lro_packets; 906 s->lro_bytes = lro_bytes; 907 s->sw_lro_queued = sw_lro_queued; 908 s->sw_lro_flushed = sw_lro_flushed; 909 s->rx_csum_none = rx_csum_none; 910 s->rx_wqe_err = rx_wqe_err; 911 s->rx_packets = rx_packets; 912 s->rx_bytes = rx_bytes; 913 s->rx_decrypted_error_packets = rx_decrypted_error; 914 s->rx_decrypted_ok_packets = rx_decrypted_ok; 915 916 mlx5e_grp_vnic_env_update_stats(priv); 917 918 /* HW counters */ 919 memset(in, 0, sizeof(in)); 920 921 MLX5_SET(query_vport_counter_in, in, opcode, 922 MLX5_CMD_OP_QUERY_VPORT_COUNTER); 923 MLX5_SET(query_vport_counter_in, in, op_mod, 0); 924 MLX5_SET(query_vport_counter_in, in, other_vport, 0); 925 926 memset(out, 0, outlen); 927 928 /* get number of out-of-buffer drops first */ 929 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 && 930 mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id, 931 &rx_out_of_buffer) == 0) { 932 s->rx_out_of_buffer = rx_out_of_buffer; 933 } 934 935 /* get port statistics */ 936 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) { 937 #define MLX5_GET_CTR(out, x) \ 938 MLX5_GET64(query_vport_counter_out, out, x) 939 940 s->rx_error_packets = 941 MLX5_GET_CTR(out, received_errors.packets); 942 s->rx_error_bytes = 943 MLX5_GET_CTR(out, received_errors.octets); 944 s->tx_error_packets = 945 MLX5_GET_CTR(out, transmit_errors.packets); 946 s->tx_error_bytes = 947 MLX5_GET_CTR(out, transmit_errors.octets); 948 949 s->rx_unicast_packets = 950 MLX5_GET_CTR(out, received_eth_unicast.packets); 951 s->rx_unicast_bytes = 952 MLX5_GET_CTR(out, received_eth_unicast.octets); 953 s->tx_unicast_packets = 954 MLX5_GET_CTR(out, transmitted_eth_unicast.packets); 955 s->tx_unicast_bytes = 956 MLX5_GET_CTR(out, transmitted_eth_unicast.octets); 957 958 s->rx_multicast_packets = 959 MLX5_GET_CTR(out, received_eth_multicast.packets); 960 s->rx_multicast_bytes = 961 MLX5_GET_CTR(out, received_eth_multicast.octets); 962 s->tx_multicast_packets = 963 MLX5_GET_CTR(out, transmitted_eth_multicast.packets); 964 s->tx_multicast_bytes = 965 MLX5_GET_CTR(out, transmitted_eth_multicast.octets); 966 967 s->rx_broadcast_packets = 968 MLX5_GET_CTR(out, received_eth_broadcast.packets); 969 s->rx_broadcast_bytes = 970 MLX5_GET_CTR(out, received_eth_broadcast.octets); 971 s->tx_broadcast_packets = 972 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets); 973 s->tx_broadcast_bytes = 974 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets); 975 976 s->tx_packets = s->tx_unicast_packets + 977 s->tx_multicast_packets + s->tx_broadcast_packets; 978 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes + 979 s->tx_broadcast_bytes; 980 981 /* Update calculated offload counters */ 982 s->tx_csum_offload = s->tx_packets - tx_offload_none; 983 s->rx_csum_good = s->rx_packets - s->rx_csum_none; 984 } 985 986 /* Get physical port counters */ 987 mlx5e_update_pport_counters(priv); 988 989 s->tx_jumbo_packets = 990 priv->stats.port_stats_debug.tx_stat_p1519to2047octets + 991 priv->stats.port_stats_debug.tx_stat_p2048to4095octets + 992 priv->stats.port_stats_debug.tx_stat_p4096to8191octets + 993 priv->stats.port_stats_debug.tx_stat_p8192to10239octets; 994 995 free_out: 996 kvfree(out); 997 998 /* Update diagnostics, if any */ 999 if (priv->params_ethtool.diag_pci_enable || 1000 priv->params_ethtool.diag_general_enable) { 1001 error = mlx5_core_get_diagnostics_full(mdev, 1002 priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL, 1003 priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL); 1004 if (error != 0) 1005 mlx5_en_err(priv->ifp, 1006 "Failed reading diagnostics: %d\n", error); 1007 } 1008 1009 /* Update FEC, if any */ 1010 error = mlx5e_fec_update(priv); 1011 if (error != 0 && error != EOPNOTSUPP) { 1012 mlx5_en_err(priv->ifp, 1013 "Updating FEC failed: %d\n", error); 1014 } 1015 1016 /* Update temperature, if any */ 1017 if (priv->params_ethtool.hw_num_temp != 0) { 1018 error = mlx5e_hw_temperature_update(priv); 1019 if (error != 0 && error != EOPNOTSUPP) { 1020 mlx5_en_err(priv->ifp, 1021 "Updating temperature failed: %d\n", error); 1022 } 1023 } 1024 } 1025 1026 static void 1027 mlx5e_update_stats_work(struct work_struct *work) 1028 { 1029 struct mlx5e_priv *priv; 1030 1031 priv = container_of(work, struct mlx5e_priv, update_stats_work); 1032 PRIV_LOCK(priv); 1033 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 && 1034 !test_bit(MLX5_INTERFACE_STATE_TEARDOWN, &priv->mdev->intf_state)) 1035 mlx5e_update_stats_locked(priv); 1036 PRIV_UNLOCK(priv); 1037 } 1038 1039 static void 1040 mlx5e_update_stats(void *arg) 1041 { 1042 struct mlx5e_priv *priv = arg; 1043 1044 queue_work(priv->wq, &priv->update_stats_work); 1045 1046 callout_reset(&priv->watchdog, hz / 4, &mlx5e_update_stats, priv); 1047 } 1048 1049 static void 1050 mlx5e_async_event_sub(struct mlx5e_priv *priv, 1051 enum mlx5_dev_event event) 1052 { 1053 switch (event) { 1054 case MLX5_DEV_EVENT_PORT_UP: 1055 case MLX5_DEV_EVENT_PORT_DOWN: 1056 queue_work(priv->wq, &priv->update_carrier_work); 1057 break; 1058 1059 default: 1060 break; 1061 } 1062 } 1063 1064 static void 1065 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv, 1066 enum mlx5_dev_event event, unsigned long param) 1067 { 1068 struct mlx5e_priv *priv = vpriv; 1069 1070 mtx_lock(&priv->async_events_mtx); 1071 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state)) 1072 mlx5e_async_event_sub(priv, event); 1073 mtx_unlock(&priv->async_events_mtx); 1074 } 1075 1076 static void 1077 mlx5e_enable_async_events(struct mlx5e_priv *priv) 1078 { 1079 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 1080 } 1081 1082 static void 1083 mlx5e_disable_async_events(struct mlx5e_priv *priv) 1084 { 1085 mtx_lock(&priv->async_events_mtx); 1086 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 1087 mtx_unlock(&priv->async_events_mtx); 1088 } 1089 1090 static void mlx5e_calibration_callout(void *arg); 1091 static int mlx5e_calibration_duration = 20; 1092 static int mlx5e_fast_calibration = 1; 1093 static int mlx5e_normal_calibration = 30; 1094 1095 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 1096 "MLX5 timestamp calibration parameters"); 1097 1098 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN, 1099 &mlx5e_calibration_duration, 0, 1100 "Duration of initial calibration"); 1101 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN, 1102 &mlx5e_fast_calibration, 0, 1103 "Recalibration interval during initial calibration"); 1104 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN, 1105 &mlx5e_normal_calibration, 0, 1106 "Recalibration interval during normal operations"); 1107 1108 /* 1109 * Ignites the calibration process. 1110 */ 1111 static void 1112 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv) 1113 { 1114 1115 if (priv->clbr_done == 0) 1116 mlx5e_calibration_callout(priv); 1117 else 1118 callout_reset_sbt_curcpu(&priv->tstmp_clbr, (priv->clbr_done < 1119 mlx5e_calibration_duration ? mlx5e_fast_calibration : 1120 mlx5e_normal_calibration) * SBT_1S, 0, 1121 mlx5e_calibration_callout, priv, C_DIRECT_EXEC); 1122 } 1123 1124 static uint64_t 1125 mlx5e_timespec2usec(const struct timespec *ts) 1126 { 1127 1128 return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec); 1129 } 1130 1131 static uint64_t 1132 mlx5e_hw_clock(struct mlx5e_priv *priv) 1133 { 1134 struct mlx5_init_seg *iseg; 1135 uint32_t hw_h, hw_h1, hw_l; 1136 1137 iseg = priv->mdev->iseg; 1138 do { 1139 hw_h = ioread32be(&iseg->internal_timer_h); 1140 hw_l = ioread32be(&iseg->internal_timer_l); 1141 hw_h1 = ioread32be(&iseg->internal_timer_h); 1142 } while (hw_h1 != hw_h); 1143 return (((uint64_t)hw_h << 32) | hw_l); 1144 } 1145 1146 /* 1147 * The calibration callout, it runs either in the context of the 1148 * thread which enables calibration, or in callout. It takes the 1149 * snapshot of system and adapter clocks, then advances the pointers to 1150 * the calibration point to allow rx path to read the consistent data 1151 * lockless. 1152 */ 1153 static void 1154 mlx5e_calibration_callout(void *arg) 1155 { 1156 struct mlx5e_priv *priv; 1157 struct mlx5e_clbr_point *next, *curr; 1158 struct timespec ts; 1159 int clbr_curr_next; 1160 1161 priv = arg; 1162 curr = &priv->clbr_points[priv->clbr_curr]; 1163 clbr_curr_next = priv->clbr_curr + 1; 1164 if (clbr_curr_next >= nitems(priv->clbr_points)) 1165 clbr_curr_next = 0; 1166 next = &priv->clbr_points[clbr_curr_next]; 1167 1168 next->base_prev = curr->base_curr; 1169 next->clbr_hw_prev = curr->clbr_hw_curr; 1170 1171 next->clbr_hw_curr = mlx5e_hw_clock(priv); 1172 if (((next->clbr_hw_curr - curr->clbr_hw_curr) >> MLX5E_TSTMP_PREC) == 1173 0) { 1174 if (priv->clbr_done != 0) { 1175 mlx5_en_err(priv->ifp, 1176 "HW failed tstmp frozen %#jx %#jx, disabling\n", 1177 next->clbr_hw_curr, curr->clbr_hw_prev); 1178 priv->clbr_done = 0; 1179 } 1180 atomic_store_rel_int(&curr->clbr_gen, 0); 1181 return; 1182 } 1183 1184 nanouptime(&ts); 1185 next->base_curr = mlx5e_timespec2usec(&ts); 1186 1187 curr->clbr_gen = 0; 1188 atomic_thread_fence_rel(); 1189 priv->clbr_curr = clbr_curr_next; 1190 atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen)); 1191 1192 if (priv->clbr_done < mlx5e_calibration_duration) 1193 priv->clbr_done++; 1194 mlx5e_reset_calibration_callout(priv); 1195 } 1196 1197 static const char *mlx5e_rq_stats_desc[] = { 1198 MLX5E_RQ_STATS(MLX5E_STATS_DESC) 1199 }; 1200 1201 static int 1202 mlx5e_create_rq(struct mlx5e_channel *c, 1203 struct mlx5e_rq_param *param, 1204 struct mlx5e_rq *rq) 1205 { 1206 struct mlx5e_priv *priv = c->priv; 1207 struct mlx5_core_dev *mdev = priv->mdev; 1208 char buffer[16]; 1209 void *rqc = param->rqc; 1210 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); 1211 int wq_sz; 1212 int err; 1213 int i; 1214 u32 nsegs, wqe_sz; 1215 1216 err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs); 1217 if (err != 0) 1218 goto done; 1219 1220 /* Create DMA descriptor TAG */ 1221 if ((err = -bus_dma_tag_create( 1222 bus_get_dma_tag(mdev->pdev->dev.bsddev), 1223 1, /* any alignment */ 1224 0, /* no boundary */ 1225 BUS_SPACE_MAXADDR, /* lowaddr */ 1226 BUS_SPACE_MAXADDR, /* highaddr */ 1227 NULL, NULL, /* filter, filterarg */ 1228 nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */ 1229 nsegs, /* nsegments */ 1230 nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */ 1231 0, /* flags */ 1232 NULL, NULL, /* lockfunc, lockfuncarg */ 1233 &rq->dma_tag))) 1234 goto done; 1235 1236 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, 1237 &rq->wq_ctrl); 1238 if (err) 1239 goto err_free_dma_tag; 1240 1241 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR]; 1242 1243 err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs); 1244 if (err != 0) 1245 goto err_rq_wq_destroy; 1246 1247 wq_sz = mlx5_wq_ll_get_size(&rq->wq); 1248 1249 err = -tcp_lro_init_args(&rq->lro, priv->ifp, TCP_LRO_ENTRIES, wq_sz); 1250 if (err) 1251 goto err_rq_wq_destroy; 1252 1253 rq->mbuf = malloc_domainset(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, 1254 mlx5_dev_domainset(mdev), M_WAITOK | M_ZERO); 1255 for (i = 0; i != wq_sz; i++) { 1256 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i); 1257 int j; 1258 1259 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map); 1260 if (err != 0) { 1261 while (i--) 1262 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 1263 goto err_rq_mbuf_free; 1264 } 1265 1266 /* set value for constant fields */ 1267 for (j = 0; j < rq->nsegs; j++) 1268 wqe->data[j].lkey = cpu_to_be32(priv->mr.key); 1269 } 1270 1271 INIT_WORK(&rq->dim.work, mlx5e_dim_work); 1272 if (priv->params.rx_cq_moderation_mode < 2) { 1273 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 1274 } else { 1275 void *cqc = container_of(param, 1276 struct mlx5e_channel_param, rq)->rx_cq.cqc; 1277 1278 switch (MLX5_GET(cqc, cqc, cq_period_mode)) { 1279 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE: 1280 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; 1281 break; 1282 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE: 1283 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE; 1284 break; 1285 default: 1286 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 1287 break; 1288 } 1289 } 1290 1291 rq->ifp = priv->ifp; 1292 rq->channel = c; 1293 rq->ix = c->ix; 1294 1295 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix); 1296 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 1297 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM, 1298 rq->stats.arg); 1299 return (0); 1300 1301 err_rq_mbuf_free: 1302 free(rq->mbuf, M_MLX5EN); 1303 tcp_lro_free(&rq->lro); 1304 err_rq_wq_destroy: 1305 mlx5_wq_destroy(&rq->wq_ctrl); 1306 err_free_dma_tag: 1307 bus_dma_tag_destroy(rq->dma_tag); 1308 done: 1309 return (err); 1310 } 1311 1312 static void 1313 mlx5e_destroy_rq(struct mlx5e_rq *rq) 1314 { 1315 int wq_sz; 1316 int i; 1317 1318 /* destroy all sysctl nodes */ 1319 sysctl_ctx_free(&rq->stats.ctx); 1320 1321 /* free leftover LRO packets, if any */ 1322 tcp_lro_free(&rq->lro); 1323 1324 wq_sz = mlx5_wq_ll_get_size(&rq->wq); 1325 for (i = 0; i != wq_sz; i++) { 1326 if (rq->mbuf[i].mbuf != NULL) { 1327 bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map); 1328 m_freem(rq->mbuf[i].mbuf); 1329 } 1330 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 1331 } 1332 free(rq->mbuf, M_MLX5EN); 1333 mlx5_wq_destroy(&rq->wq_ctrl); 1334 bus_dma_tag_destroy(rq->dma_tag); 1335 } 1336 1337 static int 1338 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param) 1339 { 1340 struct mlx5e_channel *c = rq->channel; 1341 struct mlx5e_priv *priv = c->priv; 1342 struct mlx5_core_dev *mdev = priv->mdev; 1343 void *in; 1344 void *rqc; 1345 void *wq; 1346 int inlen; 1347 int err; 1348 u8 ts_format; 1349 1350 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 1351 sizeof(u64) * rq->wq_ctrl.buf.npages; 1352 in = mlx5_vzalloc(inlen); 1353 if (in == NULL) 1354 return (-ENOMEM); 1355 1356 ts_format = mlx5_get_rq_default_ts(mdev); 1357 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1358 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1359 1360 memcpy(rqc, param->rqc, sizeof(param->rqc)); 1361 1362 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1363 MLX5_SET(rqc, rqc, ts_format, ts_format); 1364 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1365 if (priv->counter_set_id >= 0) 1366 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id); 1367 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - 1368 MLX5_ADAPTER_PAGE_SHIFT); 1369 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); 1370 1371 mlx5_fill_page_array(&rq->wq_ctrl.buf, 1372 (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 1373 1374 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); 1375 1376 kvfree(in); 1377 1378 return (err); 1379 } 1380 1381 static int 1382 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state) 1383 { 1384 struct mlx5e_channel *c = rq->channel; 1385 struct mlx5e_priv *priv = c->priv; 1386 struct mlx5_core_dev *mdev = priv->mdev; 1387 1388 void *in; 1389 void *rqc; 1390 int inlen; 1391 int err; 1392 1393 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 1394 in = mlx5_vzalloc(inlen); 1395 if (in == NULL) 1396 return (-ENOMEM); 1397 1398 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1399 1400 MLX5_SET(modify_rq_in, in, rqn, rq->rqn); 1401 MLX5_SET(modify_rq_in, in, rq_state, curr_state); 1402 MLX5_SET(rqc, rqc, state, next_state); 1403 1404 err = mlx5_core_modify_rq(mdev, in, inlen); 1405 1406 kvfree(in); 1407 1408 return (err); 1409 } 1410 1411 static void 1412 mlx5e_disable_rq(struct mlx5e_rq *rq) 1413 { 1414 struct mlx5e_channel *c = rq->channel; 1415 struct mlx5e_priv *priv = c->priv; 1416 struct mlx5_core_dev *mdev = priv->mdev; 1417 1418 mlx5_core_destroy_rq(mdev, rq->rqn); 1419 } 1420 1421 static int 1422 mlx5e_open_rq(struct mlx5e_channel *c, 1423 struct mlx5e_rq_param *param, 1424 struct mlx5e_rq *rq) 1425 { 1426 int err; 1427 1428 err = mlx5e_create_rq(c, param, rq); 1429 if (err) 1430 return (err); 1431 1432 /* set CQN in RQ parameters */ 1433 MLX5_SET(rqc, param->rqc, cqn, c->rq.cq.mcq.cqn); 1434 1435 err = mlx5e_enable_rq(rq, param); 1436 if (err) 1437 goto err_destroy_rq; 1438 1439 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 1440 if (err) 1441 goto err_disable_rq; 1442 1443 c->rq.enabled = 1; 1444 1445 return (0); 1446 1447 err_disable_rq: 1448 mlx5e_disable_rq(rq); 1449 err_destroy_rq: 1450 mlx5e_destroy_rq(rq); 1451 1452 return (err); 1453 } 1454 1455 static void 1456 mlx5e_close_rq(struct mlx5e_rq *rq) 1457 { 1458 mtx_lock(&rq->mtx); 1459 rq->enabled = 0; 1460 callout_stop(&rq->watchdog); 1461 mtx_unlock(&rq->mtx); 1462 1463 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 1464 } 1465 1466 static void 1467 mlx5e_close_rq_wait(struct mlx5e_rq *rq) 1468 { 1469 1470 mlx5e_disable_rq(rq); 1471 mlx5e_close_cq(&rq->cq); 1472 cancel_work_sync(&rq->dim.work); 1473 mlx5e_destroy_rq(rq); 1474 } 1475 1476 /* 1477 * What is a drop RQ and why is it needed? 1478 * 1479 * The RSS indirection table, also called the RQT, selects the 1480 * destination RQ based on the receive queue number, RQN. The RQT is 1481 * frequently referred to by flow steering rules to distribute traffic 1482 * among multiple RQs. The problem is that the RQs cannot be destroyed 1483 * before the RQT referring them is destroyed too. Further, TLS RX 1484 * rules may still be referring to the RQT even if the link went 1485 * down. Because there is no magic RQN for dropping packets, we create 1486 * a dummy RQ, also called drop RQ, which sole purpose is to drop all 1487 * received packets. When the link goes down this RQN is filled in all 1488 * RQT entries, of the main RQT, so the real RQs which are about to be 1489 * destroyed can be released and the TLS RX rules can be sustained. 1490 */ 1491 static void 1492 mlx5e_open_drop_rq_comp(struct mlx5_core_cq *mcq __unused, struct mlx5_eqe *eqe __unused) 1493 { 1494 } 1495 1496 static int 1497 mlx5e_open_drop_rq(struct mlx5e_priv *priv, 1498 struct mlx5e_rq *drop_rq) 1499 { 1500 struct mlx5e_cq_param param_cq = {}; 1501 struct mlx5e_rq_param param_rq = {}; 1502 void *rqc_wq = MLX5_ADDR_OF(rqc, param_rq.rqc, wq); 1503 int err; 1504 1505 /* set channel pointer */ 1506 drop_rq->channel = priv->channel; 1507 1508 /* set basic CQ parameters needed */ 1509 MLX5_SET(cqc, param_cq.cqc, log_cq_size, 0); 1510 MLX5_SET(cqc, param_cq.cqc, uar_page, priv->mdev->priv.uar->index); 1511 1512 /* open receive completion queue */ 1513 err = mlx5e_open_cq(priv, ¶m_cq, &drop_rq->cq, 1514 &mlx5e_open_drop_rq_comp, 0); 1515 if (err) 1516 goto err_done; 1517 1518 /* set basic WQ parameters needed */ 1519 MLX5_SET(wq, rqc_wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); 1520 MLX5_SET(wq, rqc_wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1521 MLX5_SET(wq, rqc_wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) + sizeof(struct mlx5_wqe_data_seg))); 1522 MLX5_SET(wq, rqc_wq, log_wq_sz, 0); 1523 MLX5_SET(wq, rqc_wq, pd, priv->pdn); 1524 1525 param_rq.wq.linear = 1; 1526 1527 err = mlx5_wq_ll_create(priv->mdev, ¶m_rq.wq, rqc_wq, &drop_rq->wq, 1528 &drop_rq->wq_ctrl); 1529 if (err) 1530 goto err_close_cq; 1531 1532 /* set CQN in RQ parameters */ 1533 MLX5_SET(rqc, param_rq.rqc, cqn, drop_rq->cq.mcq.cqn); 1534 1535 err = mlx5e_enable_rq(drop_rq, ¶m_rq); 1536 if (err) 1537 goto err_wq_destroy; 1538 1539 err = mlx5e_modify_rq(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 1540 if (err) 1541 goto err_disable_rq; 1542 1543 return (err); 1544 1545 err_disable_rq: 1546 mlx5e_disable_rq(drop_rq); 1547 err_wq_destroy: 1548 mlx5_wq_destroy(&drop_rq->wq_ctrl); 1549 err_close_cq: 1550 mlx5e_close_cq(&drop_rq->cq); 1551 err_done: 1552 return (err); 1553 } 1554 1555 static void 1556 mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq) 1557 { 1558 mlx5e_modify_rq(drop_rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 1559 mlx5e_disable_rq(drop_rq); 1560 mlx5_wq_destroy(&drop_rq->wq_ctrl); 1561 mlx5e_close_cq(&drop_rq->cq); 1562 } 1563 1564 void 1565 mlx5e_free_sq_db(struct mlx5e_sq *sq) 1566 { 1567 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1568 int x; 1569 1570 for (x = 0; x != wq_sz; x++) { 1571 if (sq->mbuf[x].mbuf != NULL) { 1572 bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map); 1573 m_freem(sq->mbuf[x].mbuf); 1574 } 1575 if (sq->mbuf[x].mst != NULL) { 1576 m_snd_tag_rele(sq->mbuf[x].mst); 1577 sq->mbuf[x].mst = NULL; 1578 } 1579 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 1580 } 1581 free(sq->mbuf, M_MLX5EN); 1582 } 1583 1584 int 1585 mlx5e_alloc_sq_db(struct mlx5e_sq *sq) 1586 { 1587 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1588 int err; 1589 int x; 1590 1591 sq->mbuf = malloc_domainset(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, 1592 mlx5_dev_domainset(sq->priv->mdev), M_WAITOK | M_ZERO); 1593 1594 /* Create DMA descriptor MAPs */ 1595 for (x = 0; x != wq_sz; x++) { 1596 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map); 1597 if (err != 0) { 1598 while (x--) 1599 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 1600 free(sq->mbuf, M_MLX5EN); 1601 return (err); 1602 } 1603 } 1604 return (0); 1605 } 1606 1607 static const char *mlx5e_sq_stats_desc[] = { 1608 MLX5E_SQ_STATS(MLX5E_STATS_DESC) 1609 }; 1610 1611 void 1612 mlx5e_update_sq_inline(struct mlx5e_sq *sq) 1613 { 1614 sq->max_inline = sq->priv->params.tx_max_inline; 1615 sq->min_inline_mode = sq->priv->params.tx_min_inline_mode; 1616 1617 /* 1618 * Check if trust state is DSCP or if inline mode is NONE which 1619 * indicates CX-5 or newer hardware. 1620 */ 1621 if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP || 1622 sq->min_inline_mode == MLX5_INLINE_MODE_NONE) { 1623 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert)) 1624 sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN; 1625 else 1626 sq->min_insert_caps = MLX5E_INSERT_NON_VLAN; 1627 } else { 1628 sq->min_insert_caps = 0; 1629 } 1630 } 1631 1632 static void 1633 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c) 1634 { 1635 int i; 1636 1637 for (i = 0; i != priv->num_tc; i++) { 1638 mtx_lock(&c->sq[i].lock); 1639 mlx5e_update_sq_inline(&c->sq[i]); 1640 mtx_unlock(&c->sq[i].lock); 1641 } 1642 } 1643 1644 void 1645 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv) 1646 { 1647 int i; 1648 1649 /* check if channels are closed */ 1650 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 1651 return; 1652 1653 for (i = 0; i < priv->params.num_channels; i++) 1654 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]); 1655 } 1656 1657 static int 1658 mlx5e_create_sq(struct mlx5e_channel *c, 1659 int tc, 1660 struct mlx5e_sq_param *param, 1661 struct mlx5e_sq *sq) 1662 { 1663 struct mlx5e_priv *priv = c->priv; 1664 struct mlx5_core_dev *mdev = priv->mdev; 1665 char buffer[16]; 1666 void *sqc = param->sqc; 1667 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq); 1668 int err; 1669 1670 /* Create DMA descriptor TAG */ 1671 if ((err = -bus_dma_tag_create( 1672 bus_get_dma_tag(mdev->pdev->dev.bsddev), 1673 1, /* any alignment */ 1674 0, /* no boundary */ 1675 BUS_SPACE_MAXADDR, /* lowaddr */ 1676 BUS_SPACE_MAXADDR, /* highaddr */ 1677 NULL, NULL, /* filter, filterarg */ 1678 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */ 1679 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */ 1680 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */ 1681 0, /* flags */ 1682 NULL, NULL, /* lockfunc, lockfuncarg */ 1683 &sq->dma_tag))) 1684 goto done; 1685 1686 sq->mkey_be = cpu_to_be32(priv->mr.key); 1687 sq->ifp = priv->ifp; 1688 sq->priv = priv; 1689 sq->tc = tc; 1690 1691 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, 1692 &sq->wq_ctrl); 1693 if (err) 1694 goto err_free_dma_tag; 1695 1696 sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; 1697 1698 err = mlx5e_alloc_sq_db(sq); 1699 if (err) 1700 goto err_sq_wq_destroy; 1701 1702 mlx5e_update_sq_inline(sq); 1703 1704 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc); 1705 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 1706 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM, 1707 sq->stats.arg); 1708 1709 return (0); 1710 1711 err_sq_wq_destroy: 1712 mlx5_wq_destroy(&sq->wq_ctrl); 1713 1714 err_free_dma_tag: 1715 bus_dma_tag_destroy(sq->dma_tag); 1716 done: 1717 return (err); 1718 } 1719 1720 static void 1721 mlx5e_destroy_sq(struct mlx5e_sq *sq) 1722 { 1723 /* destroy all sysctl nodes */ 1724 sysctl_ctx_free(&sq->stats.ctx); 1725 1726 mlx5e_free_sq_db(sq); 1727 mlx5_wq_destroy(&sq->wq_ctrl); 1728 bus_dma_tag_destroy(sq->dma_tag); 1729 } 1730 1731 int 1732 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param, 1733 const struct mlx5_sq_bfreg *bfreg, int tis_num) 1734 { 1735 void *in; 1736 void *sqc; 1737 void *wq; 1738 int inlen; 1739 int err; 1740 u8 ts_format; 1741 1742 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1743 sizeof(u64) * sq->wq_ctrl.buf.npages; 1744 in = mlx5_vzalloc(inlen); 1745 if (in == NULL) 1746 return (-ENOMEM); 1747 1748 sq->uar_map = bfreg->map; 1749 1750 ts_format = mlx5_get_sq_default_ts(sq->priv->mdev); 1751 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1752 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1753 1754 memcpy(sqc, param->sqc, sizeof(param->sqc)); 1755 1756 MLX5_SET(sqc, sqc, tis_num_0, tis_num); 1757 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn); 1758 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1759 MLX5_SET(sqc, sqc, ts_format, ts_format); 1760 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1761 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1762 MLX5_SET(sqc, sqc, allow_swp, 1); 1763 1764 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1765 MLX5_SET(wq, wq, uar_page, bfreg->index); 1766 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift - 1767 MLX5_ADAPTER_PAGE_SHIFT); 1768 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma); 1769 1770 mlx5_fill_page_array(&sq->wq_ctrl.buf, 1771 (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 1772 1773 err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn); 1774 1775 kvfree(in); 1776 1777 return (err); 1778 } 1779 1780 int 1781 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state) 1782 { 1783 void *in; 1784 void *sqc; 1785 int inlen; 1786 int err; 1787 1788 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 1789 in = mlx5_vzalloc(inlen); 1790 if (in == NULL) 1791 return (-ENOMEM); 1792 1793 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1794 1795 MLX5_SET(modify_sq_in, in, sqn, sq->sqn); 1796 MLX5_SET(modify_sq_in, in, sq_state, curr_state); 1797 MLX5_SET(sqc, sqc, state, next_state); 1798 1799 err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen); 1800 1801 kvfree(in); 1802 1803 return (err); 1804 } 1805 1806 void 1807 mlx5e_disable_sq(struct mlx5e_sq *sq) 1808 { 1809 1810 mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn); 1811 } 1812 1813 static int 1814 mlx5e_open_sq(struct mlx5e_channel *c, 1815 int tc, 1816 struct mlx5e_sq_param *param, 1817 struct mlx5e_sq *sq) 1818 { 1819 int err; 1820 1821 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact; 1822 1823 /* ensure the TX completion event factor is not zero */ 1824 if (sq->cev_factor == 0) 1825 sq->cev_factor = 1; 1826 1827 err = mlx5e_create_sq(c, tc, param, sq); 1828 if (err) 1829 return (err); 1830 1831 err = mlx5e_enable_sq(sq, param, &c->bfreg, c->priv->tisn[tc]); 1832 if (err) 1833 goto err_destroy_sq; 1834 1835 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY); 1836 if (err) 1837 goto err_disable_sq; 1838 1839 WRITE_ONCE(sq->running, 1); 1840 1841 return (0); 1842 1843 err_disable_sq: 1844 mlx5e_disable_sq(sq); 1845 err_destroy_sq: 1846 mlx5e_destroy_sq(sq); 1847 1848 return (err); 1849 } 1850 1851 static void 1852 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep) 1853 { 1854 /* fill up remainder with NOPs */ 1855 while (sq->cev_counter != 0) { 1856 while (!mlx5e_sq_has_room_for(sq, 1)) { 1857 if (can_sleep != 0) { 1858 mtx_unlock(&sq->lock); 1859 msleep(4); 1860 mtx_lock(&sq->lock); 1861 } else { 1862 goto done; 1863 } 1864 } 1865 /* send a single NOP */ 1866 mlx5e_send_nop(sq, 1); 1867 atomic_thread_fence_rel(); 1868 } 1869 done: 1870 mlx5e_tx_notify_hw(sq, false); 1871 } 1872 1873 void 1874 mlx5e_sq_cev_timeout(void *arg) 1875 { 1876 struct mlx5e_sq *sq = arg; 1877 1878 mtx_assert(&sq->lock, MA_OWNED); 1879 1880 /* check next state */ 1881 switch (sq->cev_next_state) { 1882 case MLX5E_CEV_STATE_SEND_NOPS: 1883 /* fill TX ring with NOPs, if any */ 1884 mlx5e_sq_send_nops_locked(sq, 0); 1885 1886 /* check if completed */ 1887 if (sq->cev_counter == 0) { 1888 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL; 1889 return; 1890 } 1891 break; 1892 default: 1893 /* send NOPs on next timeout */ 1894 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS; 1895 break; 1896 } 1897 1898 /* restart timer */ 1899 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq); 1900 } 1901 1902 void 1903 mlx5e_drain_sq(struct mlx5e_sq *sq) 1904 { 1905 int error; 1906 struct mlx5_core_dev *mdev= sq->priv->mdev; 1907 1908 /* 1909 * Check if already stopped. 1910 * 1911 * NOTE: Serialization of this function is managed by the 1912 * caller ensuring the priv's state lock is locked or in case 1913 * of rate limit support, a single thread manages drain and 1914 * resume of SQs. The "running" variable can therefore safely 1915 * be read without any locks. 1916 */ 1917 if (READ_ONCE(sq->running) == 0) 1918 return; 1919 1920 /* don't put more packets into the SQ */ 1921 WRITE_ONCE(sq->running, 0); 1922 1923 /* serialize access to DMA rings */ 1924 mtx_lock(&sq->lock); 1925 1926 /* teardown event factor timer, if any */ 1927 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS; 1928 callout_stop(&sq->cev_callout); 1929 1930 /* send dummy NOPs in order to flush the transmit ring */ 1931 mlx5e_sq_send_nops_locked(sq, 1); 1932 mtx_unlock(&sq->lock); 1933 1934 /* wait till SQ is empty or link is down */ 1935 mtx_lock(&sq->lock); 1936 while (sq->cc != sq->pc && 1937 (sq->priv->media_status_last & IFM_ACTIVE) != 0 && 1938 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR && 1939 pci_channel_offline(mdev->pdev) == 0) { 1940 mtx_unlock(&sq->lock); 1941 msleep(1); 1942 sq->cq.mcq.comp(&sq->cq.mcq, NULL); 1943 mtx_lock(&sq->lock); 1944 } 1945 mtx_unlock(&sq->lock); 1946 1947 /* error out remaining requests */ 1948 error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR); 1949 if (error != 0) { 1950 mlx5_en_err(sq->ifp, 1951 "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error); 1952 } 1953 1954 /* wait till SQ is empty */ 1955 mtx_lock(&sq->lock); 1956 while (sq->cc != sq->pc && 1957 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR && 1958 pci_channel_offline(mdev->pdev) == 0) { 1959 mtx_unlock(&sq->lock); 1960 msleep(1); 1961 sq->cq.mcq.comp(&sq->cq.mcq, NULL); 1962 mtx_lock(&sq->lock); 1963 } 1964 mtx_unlock(&sq->lock); 1965 } 1966 1967 static void 1968 mlx5e_close_sq_wait(struct mlx5e_sq *sq) 1969 { 1970 1971 mlx5e_drain_sq(sq); 1972 mlx5e_disable_sq(sq); 1973 mlx5e_destroy_sq(sq); 1974 } 1975 1976 static int 1977 mlx5e_create_cq(struct mlx5e_priv *priv, 1978 struct mlx5e_cq_param *param, 1979 struct mlx5e_cq *cq, 1980 mlx5e_cq_comp_t *comp, 1981 int eq_ix) 1982 { 1983 struct mlx5_core_dev *mdev = priv->mdev; 1984 struct mlx5_core_cq *mcq = &cq->mcq; 1985 int eqn_not_used; 1986 int irqn; 1987 int err; 1988 u32 i; 1989 1990 err = mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn); 1991 if (err) 1992 return (err); 1993 1994 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, 1995 &cq->wq_ctrl); 1996 if (err) 1997 return (err); 1998 1999 mcq->cqe_sz = 64; 2000 mcq->set_ci_db = cq->wq_ctrl.db.db; 2001 mcq->arm_db = cq->wq_ctrl.db.db + 1; 2002 *mcq->set_ci_db = 0; 2003 *mcq->arm_db = 0; 2004 mcq->vector = eq_ix; 2005 mcq->comp = comp; 2006 mcq->event = mlx5e_cq_error_event; 2007 mcq->irqn = irqn; 2008 2009 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { 2010 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); 2011 2012 cqe->op_own = 0xf1; 2013 } 2014 2015 cq->priv = priv; 2016 2017 return (0); 2018 } 2019 2020 static void 2021 mlx5e_destroy_cq(struct mlx5e_cq *cq) 2022 { 2023 mlx5_wq_destroy(&cq->wq_ctrl); 2024 } 2025 2026 static int 2027 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix) 2028 { 2029 struct mlx5_core_cq *mcq = &cq->mcq; 2030 u32 out[MLX5_ST_SZ_DW(create_cq_out)]; 2031 void *in; 2032 void *cqc; 2033 int inlen; 2034 int irqn_not_used; 2035 int eqn; 2036 int err; 2037 2038 inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 2039 sizeof(u64) * cq->wq_ctrl.buf.npages; 2040 in = mlx5_vzalloc(inlen); 2041 if (in == NULL) 2042 return (-ENOMEM); 2043 2044 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); 2045 2046 memcpy(cqc, param->cqc, sizeof(param->cqc)); 2047 2048 mlx5_fill_page_array(&cq->wq_ctrl.buf, 2049 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas)); 2050 2051 mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used); 2052 2053 MLX5_SET(cqc, cqc, c_eqn, eqn); 2054 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - 2055 MLX5_ADAPTER_PAGE_SHIFT); 2056 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); 2057 2058 err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen, out, sizeof(out)); 2059 2060 kvfree(in); 2061 2062 if (err) 2063 return (err); 2064 2065 mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock)); 2066 2067 return (0); 2068 } 2069 2070 static void 2071 mlx5e_disable_cq(struct mlx5e_cq *cq) 2072 { 2073 2074 mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq); 2075 } 2076 2077 int 2078 mlx5e_open_cq(struct mlx5e_priv *priv, 2079 struct mlx5e_cq_param *param, 2080 struct mlx5e_cq *cq, 2081 mlx5e_cq_comp_t *comp, 2082 int eq_ix) 2083 { 2084 int err; 2085 2086 err = mlx5e_create_cq(priv, param, cq, comp, eq_ix); 2087 if (err) 2088 return (err); 2089 2090 err = mlx5e_enable_cq(cq, param, eq_ix); 2091 if (err) 2092 goto err_destroy_cq; 2093 2094 return (0); 2095 2096 err_destroy_cq: 2097 mlx5e_destroy_cq(cq); 2098 2099 return (err); 2100 } 2101 2102 void 2103 mlx5e_close_cq(struct mlx5e_cq *cq) 2104 { 2105 mlx5e_disable_cq(cq); 2106 mlx5e_destroy_cq(cq); 2107 } 2108 2109 static int 2110 mlx5e_open_tx_cqs(struct mlx5e_channel *c, 2111 struct mlx5e_channel_param *cparam) 2112 { 2113 int err; 2114 int tc; 2115 2116 for (tc = 0; tc < c->priv->num_tc; tc++) { 2117 /* open completion queue */ 2118 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq, 2119 &mlx5e_tx_cq_comp, c->ix); 2120 if (err) 2121 goto err_close_tx_cqs; 2122 } 2123 return (0); 2124 2125 err_close_tx_cqs: 2126 for (tc--; tc >= 0; tc--) 2127 mlx5e_close_cq(&c->sq[tc].cq); 2128 2129 return (err); 2130 } 2131 2132 static void 2133 mlx5e_close_tx_cqs(struct mlx5e_channel *c) 2134 { 2135 int tc; 2136 2137 for (tc = 0; tc < c->priv->num_tc; tc++) 2138 mlx5e_close_cq(&c->sq[tc].cq); 2139 } 2140 2141 static int 2142 mlx5e_open_sqs(struct mlx5e_channel *c, 2143 struct mlx5e_channel_param *cparam) 2144 { 2145 int err; 2146 int tc; 2147 2148 for (tc = 0; tc < c->priv->num_tc; tc++) { 2149 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]); 2150 if (err) 2151 goto err_close_sqs; 2152 } 2153 2154 return (0); 2155 2156 err_close_sqs: 2157 for (tc--; tc >= 0; tc--) 2158 mlx5e_close_sq_wait(&c->sq[tc]); 2159 2160 return (err); 2161 } 2162 2163 static void 2164 mlx5e_close_sqs_wait(struct mlx5e_channel *c) 2165 { 2166 int tc; 2167 2168 for (tc = 0; tc < c->priv->num_tc; tc++) 2169 mlx5e_close_sq_wait(&c->sq[tc]); 2170 } 2171 2172 static void 2173 mlx5e_chan_static_init(struct mlx5e_priv *priv, struct mlx5e_channel *c, int ix) 2174 { 2175 int tc; 2176 2177 /* setup priv and channel number */ 2178 c->priv = priv; 2179 c->ix = ix; 2180 2181 /* setup send tag */ 2182 m_snd_tag_init(&c->tag, c->priv->ifp, &mlx5e_ul_snd_tag_sw); 2183 2184 init_completion(&c->completion); 2185 2186 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF); 2187 2188 callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0); 2189 2190 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) { 2191 struct mlx5e_sq *sq = c->sq + tc; 2192 2193 mtx_init(&sq->lock, "mlx5tx", 2194 MTX_NETWORK_LOCK " TX", MTX_DEF); 2195 mtx_init(&sq->comp_lock, "mlx5comp", 2196 MTX_NETWORK_LOCK " TX", MTX_DEF); 2197 2198 callout_init_mtx(&sq->cev_callout, &sq->lock, 0); 2199 } 2200 2201 mlx5e_iq_static_init(&c->iq); 2202 } 2203 2204 static void 2205 mlx5e_chan_wait_for_completion(struct mlx5e_channel *c) 2206 { 2207 2208 m_snd_tag_rele(&c->tag); 2209 wait_for_completion(&c->completion); 2210 } 2211 2212 static void 2213 mlx5e_priv_wait_for_completion(struct mlx5e_priv *priv, const uint32_t channels) 2214 { 2215 uint32_t x; 2216 2217 for (x = 0; x != channels; x++) 2218 mlx5e_chan_wait_for_completion(&priv->channel[x]); 2219 } 2220 2221 static void 2222 mlx5e_chan_static_destroy(struct mlx5e_channel *c) 2223 { 2224 int tc; 2225 2226 callout_drain(&c->rq.watchdog); 2227 2228 mtx_destroy(&c->rq.mtx); 2229 2230 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) { 2231 callout_drain(&c->sq[tc].cev_callout); 2232 mtx_destroy(&c->sq[tc].lock); 2233 mtx_destroy(&c->sq[tc].comp_lock); 2234 } 2235 2236 mlx5e_iq_static_destroy(&c->iq); 2237 } 2238 2239 static int 2240 mlx5e_open_channel(struct mlx5e_priv *priv, 2241 struct mlx5e_channel_param *cparam, 2242 struct mlx5e_channel *c) 2243 { 2244 struct epoch_tracker et; 2245 int i, err; 2246 2247 /* zero non-persistent data */ 2248 MLX5E_ZERO(&c->rq, mlx5e_rq_zero_start); 2249 for (i = 0; i != priv->num_tc; i++) 2250 MLX5E_ZERO(&c->sq[i], mlx5e_sq_zero_start); 2251 MLX5E_ZERO(&c->iq, mlx5e_iq_zero_start); 2252 2253 /* open transmit completion queue */ 2254 err = mlx5e_open_tx_cqs(c, cparam); 2255 if (err) 2256 goto err_free; 2257 2258 /* open receive completion queue */ 2259 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq, 2260 &mlx5e_rx_cq_comp, c->ix); 2261 if (err) 2262 goto err_close_tx_cqs; 2263 2264 err = mlx5e_open_sqs(c, cparam); 2265 if (err) 2266 goto err_close_rx_cq; 2267 2268 err = mlx5e_iq_open(c, &cparam->sq, &cparam->tx_cq, &c->iq); 2269 if (err) 2270 goto err_close_sqs; 2271 2272 err = mlx5e_open_rq(c, &cparam->rq, &c->rq); 2273 if (err) 2274 goto err_close_iq; 2275 2276 /* poll receive queue initially */ 2277 NET_EPOCH_ENTER(et); 2278 c->rq.cq.mcq.comp(&c->rq.cq.mcq, NULL); 2279 NET_EPOCH_EXIT(et); 2280 2281 return (0); 2282 2283 err_close_iq: 2284 mlx5e_iq_close(&c->iq); 2285 2286 err_close_sqs: 2287 mlx5e_close_sqs_wait(c); 2288 2289 err_close_rx_cq: 2290 mlx5e_close_cq(&c->rq.cq); 2291 2292 err_close_tx_cqs: 2293 mlx5e_close_tx_cqs(c); 2294 2295 err_free: 2296 return (err); 2297 } 2298 2299 static void 2300 mlx5e_close_channel(struct mlx5e_channel *c) 2301 { 2302 mlx5e_close_rq(&c->rq); 2303 } 2304 2305 static void 2306 mlx5e_close_channel_wait(struct mlx5e_channel *c) 2307 { 2308 mlx5e_close_rq_wait(&c->rq); 2309 mlx5e_iq_close(&c->iq); 2310 mlx5e_close_sqs_wait(c); 2311 mlx5e_close_tx_cqs(c); 2312 } 2313 2314 static int 2315 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs) 2316 { 2317 u32 r, n; 2318 2319 r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz : 2320 MLX5E_SW2MB_MTU(if_getmtu(priv->ifp)); 2321 if (r > MJUM16BYTES) 2322 return (-ENOMEM); 2323 2324 if (r > MJUM9BYTES) 2325 r = MJUM16BYTES; 2326 else if (r > MJUMPAGESIZE) 2327 r = MJUM9BYTES; 2328 else if (r > MCLBYTES) 2329 r = MJUMPAGESIZE; 2330 else 2331 r = MCLBYTES; 2332 2333 /* 2334 * n + 1 must be a power of two, because stride size must be. 2335 * Stride size is 16 * (n + 1), as the first segment is 2336 * control. 2337 */ 2338 n = roundup_pow_of_two(1 + howmany(r, MLX5E_MAX_RX_BYTES)) - 1; 2339 if (n > MLX5E_MAX_BUSDMA_RX_SEGS) 2340 return (-ENOMEM); 2341 2342 *wqe_sz = r; 2343 *nsegs = n; 2344 return (0); 2345 } 2346 2347 static void 2348 mlx5e_build_rq_param(struct mlx5e_priv *priv, 2349 struct mlx5e_rq_param *param) 2350 { 2351 void *rqc = param->rqc; 2352 void *wq = MLX5_ADDR_OF(rqc, rqc, wq); 2353 u32 wqe_sz, nsegs; 2354 2355 mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs); 2356 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); 2357 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 2358 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) + 2359 nsegs * sizeof(struct mlx5_wqe_data_seg))); 2360 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size); 2361 MLX5_SET(wq, wq, pd, priv->pdn); 2362 2363 param->wq.linear = 1; 2364 } 2365 2366 static void 2367 mlx5e_build_sq_param(struct mlx5e_priv *priv, 2368 struct mlx5e_sq_param *param) 2369 { 2370 void *sqc = param->sqc; 2371 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 2372 2373 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size); 2374 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 2375 MLX5_SET(wq, wq, pd, priv->pdn); 2376 2377 param->wq.linear = 1; 2378 } 2379 2380 static void 2381 mlx5e_build_common_cq_param(struct mlx5e_priv *priv, 2382 struct mlx5e_cq_param *param) 2383 { 2384 void *cqc = param->cqc; 2385 2386 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index); 2387 } 2388 2389 static void 2390 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr) 2391 { 2392 2393 *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE); 2394 2395 /* apply LRO restrictions */ 2396 if (priv->params.hw_lro_en && 2397 ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) { 2398 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO; 2399 } 2400 } 2401 2402 static void 2403 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, 2404 struct mlx5e_cq_param *param) 2405 { 2406 struct net_dim_cq_moder curr; 2407 void *cqc = param->cqc; 2408 2409 /* 2410 * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE 2411 * format is more beneficial for FreeBSD use case. 2412 * 2413 * Adding support for MLX5_CQE_FORMAT_CSUM will require changes 2414 * in mlx5e_decompress_cqe. 2415 */ 2416 if (priv->params.cqe_zipping_en) { 2417 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH); 2418 MLX5_SET(cqc, cqc, cqe_compression_en, 1); 2419 } 2420 2421 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size); 2422 2423 switch (priv->params.rx_cq_moderation_mode) { 2424 case 0: 2425 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec); 2426 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts); 2427 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2428 break; 2429 case 1: 2430 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec); 2431 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts); 2432 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2433 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2434 else 2435 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2436 break; 2437 case 2: 2438 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr); 2439 MLX5_SET(cqc, cqc, cq_period, curr.usec); 2440 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts); 2441 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2442 break; 2443 case 3: 2444 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr); 2445 MLX5_SET(cqc, cqc, cq_period, curr.usec); 2446 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts); 2447 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2448 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2449 else 2450 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2451 break; 2452 default: 2453 break; 2454 } 2455 2456 mlx5e_dim_build_cq_param(priv, param); 2457 2458 mlx5e_build_common_cq_param(priv, param); 2459 } 2460 2461 static void 2462 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv, 2463 struct mlx5e_cq_param *param) 2464 { 2465 void *cqc = param->cqc; 2466 2467 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size); 2468 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec); 2469 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts); 2470 2471 switch (priv->params.tx_cq_moderation_mode) { 2472 case 0: 2473 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2474 break; 2475 default: 2476 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2477 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2478 else 2479 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2480 break; 2481 } 2482 2483 mlx5e_build_common_cq_param(priv, param); 2484 } 2485 2486 static void 2487 mlx5e_build_channel_param(struct mlx5e_priv *priv, 2488 struct mlx5e_channel_param *cparam) 2489 { 2490 memset(cparam, 0, sizeof(*cparam)); 2491 2492 mlx5e_build_rq_param(priv, &cparam->rq); 2493 mlx5e_build_sq_param(priv, &cparam->sq); 2494 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq); 2495 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq); 2496 } 2497 2498 static int 2499 mlx5e_open_channels(struct mlx5e_priv *priv) 2500 { 2501 struct mlx5e_channel_param *cparam; 2502 int err; 2503 int i; 2504 2505 cparam = malloc(sizeof(*cparam), M_MLX5EN, M_WAITOK); 2506 2507 mlx5e_build_channel_param(priv, cparam); 2508 for (i = 0; i < priv->params.num_channels; i++) { 2509 err = mlx5e_open_channel(priv, cparam, &priv->channel[i]); 2510 if (err) 2511 goto err_close_channels; 2512 2513 /* Bind interrupt vectors, if any. */ 2514 if (priv->params_ethtool.irq_cpu_base > -1) { 2515 cpuset_t cpuset; 2516 int cpu; 2517 int irq; 2518 int eqn; 2519 int nirq; 2520 2521 err = mlx5_vector2eqn(priv->mdev, i, 2522 &eqn, &nirq); 2523 2524 /* error here is non-fatal */ 2525 if (err != 0) 2526 continue; 2527 2528 irq = priv->mdev->priv.msix_arr[nirq].vector; 2529 cpu = (unsigned)(priv->params_ethtool.irq_cpu_base + 2530 i * priv->params_ethtool.irq_cpu_stride) % (unsigned)mp_ncpus; 2531 2532 CPU_ZERO(&cpuset); 2533 CPU_SET(cpu, &cpuset); 2534 intr_setaffinity(irq, CPU_WHICH_INTRHANDLER, &cpuset); 2535 } 2536 } 2537 free(cparam, M_MLX5EN); 2538 return (0); 2539 2540 err_close_channels: 2541 while (i--) { 2542 mlx5e_close_channel(&priv->channel[i]); 2543 mlx5e_close_channel_wait(&priv->channel[i]); 2544 } 2545 free(cparam, M_MLX5EN); 2546 return (err); 2547 } 2548 2549 static void 2550 mlx5e_close_channels(struct mlx5e_priv *priv) 2551 { 2552 int i; 2553 2554 for (i = 0; i < priv->params.num_channels; i++) 2555 mlx5e_close_channel(&priv->channel[i]); 2556 for (i = 0; i < priv->params.num_channels; i++) 2557 mlx5e_close_channel_wait(&priv->channel[i]); 2558 } 2559 2560 static int 2561 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq) 2562 { 2563 2564 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) { 2565 uint8_t cq_mode; 2566 2567 switch (priv->params.tx_cq_moderation_mode) { 2568 case 0: 2569 case 2: 2570 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 2571 break; 2572 default: 2573 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE; 2574 break; 2575 } 2576 2577 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq, 2578 priv->params.tx_cq_moderation_usec, 2579 priv->params.tx_cq_moderation_pkts, 2580 cq_mode)); 2581 } 2582 2583 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq, 2584 priv->params.tx_cq_moderation_usec, 2585 priv->params.tx_cq_moderation_pkts)); 2586 } 2587 2588 static int 2589 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq) 2590 { 2591 2592 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) { 2593 uint8_t cq_mode; 2594 uint8_t dim_mode; 2595 int retval; 2596 2597 switch (priv->params.rx_cq_moderation_mode) { 2598 case 0: 2599 case 2: 2600 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 2601 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; 2602 break; 2603 default: 2604 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE; 2605 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE; 2606 break; 2607 } 2608 2609 /* tear down dynamic interrupt moderation */ 2610 mtx_lock(&rq->mtx); 2611 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 2612 mtx_unlock(&rq->mtx); 2613 2614 /* wait for dynamic interrupt moderation work task, if any */ 2615 cancel_work_sync(&rq->dim.work); 2616 2617 if (priv->params.rx_cq_moderation_mode >= 2) { 2618 struct net_dim_cq_moder curr; 2619 2620 mlx5e_get_default_profile(priv, dim_mode, &curr); 2621 2622 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq, 2623 curr.usec, curr.pkts, cq_mode); 2624 2625 /* set dynamic interrupt moderation mode and zero defaults */ 2626 mtx_lock(&rq->mtx); 2627 rq->dim.mode = dim_mode; 2628 rq->dim.state = 0; 2629 rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE; 2630 mtx_unlock(&rq->mtx); 2631 } else { 2632 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq, 2633 priv->params.rx_cq_moderation_usec, 2634 priv->params.rx_cq_moderation_pkts, 2635 cq_mode); 2636 } 2637 return (retval); 2638 } 2639 2640 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq, 2641 priv->params.rx_cq_moderation_usec, 2642 priv->params.rx_cq_moderation_pkts)); 2643 } 2644 2645 static int 2646 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c) 2647 { 2648 int err; 2649 int i; 2650 2651 err = mlx5e_refresh_rq_params(priv, &c->rq); 2652 if (err) 2653 goto done; 2654 2655 for (i = 0; i != priv->num_tc; i++) { 2656 err = mlx5e_refresh_sq_params(priv, &c->sq[i]); 2657 if (err) 2658 goto done; 2659 } 2660 done: 2661 return (err); 2662 } 2663 2664 int 2665 mlx5e_refresh_channel_params(struct mlx5e_priv *priv) 2666 { 2667 int i; 2668 2669 /* check if channels are closed */ 2670 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 2671 return (EINVAL); 2672 2673 for (i = 0; i < priv->params.num_channels; i++) { 2674 int err; 2675 2676 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]); 2677 if (err) 2678 return (err); 2679 } 2680 return (0); 2681 } 2682 2683 static int 2684 mlx5e_open_tis(struct mlx5e_priv *priv, int tc) 2685 { 2686 struct mlx5_core_dev *mdev = priv->mdev; 2687 u32 in[MLX5_ST_SZ_DW(create_tis_in)]; 2688 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 2689 2690 memset(in, 0, sizeof(in)); 2691 2692 MLX5_SET(tisc, tisc, prio, tc); 2693 MLX5_SET(tisc, tisc, transport_domain, priv->tdn); 2694 2695 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc])); 2696 } 2697 2698 static void 2699 mlx5e_close_tis(struct mlx5e_priv *priv, int tc) 2700 { 2701 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc], 0); 2702 } 2703 2704 static int 2705 mlx5e_open_tises(struct mlx5e_priv *priv) 2706 { 2707 int num_tc = priv->num_tc; 2708 int err; 2709 int tc; 2710 2711 for (tc = 0; tc < num_tc; tc++) { 2712 err = mlx5e_open_tis(priv, tc); 2713 if (err) 2714 goto err_close_tises; 2715 } 2716 2717 return (0); 2718 2719 err_close_tises: 2720 for (tc--; tc >= 0; tc--) 2721 mlx5e_close_tis(priv, tc); 2722 2723 return (err); 2724 } 2725 2726 static void 2727 mlx5e_close_tises(struct mlx5e_priv *priv) 2728 { 2729 int num_tc = priv->num_tc; 2730 int tc; 2731 2732 for (tc = 0; tc < num_tc; tc++) 2733 mlx5e_close_tis(priv, tc); 2734 } 2735 2736 static int 2737 mlx5e_open_default_rqt(struct mlx5e_priv *priv, u32 *prqtn, int sz) 2738 { 2739 u32 *in; 2740 void *rqtc; 2741 int inlen; 2742 int err; 2743 int i; 2744 2745 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 2746 in = mlx5_vzalloc(inlen); 2747 if (in == NULL) 2748 return (-ENOMEM); 2749 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 2750 2751 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 2752 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 2753 2754 for (i = 0; i != sz; i++) 2755 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn); 2756 2757 err = mlx5_core_create_rqt(priv->mdev, in, inlen, prqtn); 2758 kvfree(in); 2759 2760 return (err); 2761 } 2762 2763 static int 2764 mlx5e_open_rqts(struct mlx5e_priv *priv) 2765 { 2766 int err; 2767 int i; 2768 2769 err = mlx5e_open_default_rqt(priv, &priv->rqtn, 2770 1 << priv->params.rx_hash_log_tbl_sz); 2771 if (err) 2772 goto err_default; 2773 2774 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) { 2775 err = mlx5e_open_default_rqt(priv, &priv->channel[i].rqtn, 1); 2776 if (err) 2777 goto err_channel; 2778 } 2779 return (0); 2780 2781 err_channel: 2782 while (i--) 2783 mlx5_core_destroy_rqt(priv->mdev, priv->channel[i].rqtn, 0); 2784 2785 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn, 0); 2786 2787 err_default: 2788 return (err); 2789 } 2790 2791 static void 2792 mlx5e_close_rqts(struct mlx5e_priv *priv) 2793 { 2794 int i; 2795 2796 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) 2797 mlx5_core_destroy_rqt(priv->mdev, priv->channel[i].rqtn, 0); 2798 2799 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn, 0); 2800 } 2801 2802 static int 2803 mlx5e_activate_rqt(struct mlx5e_priv *priv) 2804 { 2805 u32 *in; 2806 void *rqtc; 2807 int inlen; 2808 int err; 2809 int sz; 2810 int i; 2811 2812 sz = 1 << priv->params.rx_hash_log_tbl_sz; 2813 2814 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz; 2815 in = mlx5_vzalloc(inlen); 2816 if (in == NULL) 2817 return (-ENOMEM); 2818 2819 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx); 2820 2821 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 2822 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1); 2823 2824 for (i = 0; i != sz; i++) { 2825 int ix; 2826 #ifdef RSS 2827 ix = rss_get_indirection_to_bucket(i); 2828 #else 2829 ix = i; 2830 #endif 2831 /* ensure we don't overflow */ 2832 ix %= priv->params.num_channels; 2833 2834 /* apply receive side scaling stride, if any */ 2835 ix -= ix % (int)priv->params.channels_rsss; 2836 2837 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn); 2838 } 2839 2840 err = mlx5_core_modify_rqt(priv->mdev, priv->rqtn, in, inlen); 2841 if (err) 2842 goto err_modify; 2843 2844 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32); 2845 2846 MLX5_SET(rqtc, rqtc, rqt_actual_size, 1); 2847 2848 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) { 2849 int ix; 2850 #ifdef RSS 2851 ix = rss_get_indirection_to_bucket(i); 2852 #else 2853 ix = i; 2854 #endif 2855 /* ensure we don't overflow */ 2856 ix %= priv->params.num_channels; 2857 2858 /* apply receive side scaling stride, if any */ 2859 ix -= ix % (int)priv->params.channels_rsss; 2860 2861 MLX5_SET(rqtc, rqtc, rq_num[0], priv->channel[ix].rq.rqn); 2862 2863 err = mlx5_core_modify_rqt(priv->mdev, priv->channel[i].rqtn, in, inlen); 2864 if (err) 2865 goto err_modify; 2866 } 2867 2868 err_modify: 2869 kvfree(in); 2870 return (err); 2871 } 2872 2873 static int 2874 mlx5e_deactivate_rqt(struct mlx5e_priv *priv) 2875 { 2876 u32 *in; 2877 void *rqtc; 2878 int inlen; 2879 int err; 2880 int sz; 2881 int i; 2882 2883 sz = 1 << priv->params.rx_hash_log_tbl_sz; 2884 2885 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz; 2886 in = mlx5_vzalloc(inlen); 2887 if (in == NULL) 2888 return (-ENOMEM); 2889 2890 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx); 2891 2892 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 2893 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1); 2894 2895 for (i = 0; i != sz; i++) 2896 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn); 2897 2898 err = mlx5_core_modify_rqt(priv->mdev, priv->rqtn, in, inlen); 2899 if (err) 2900 goto err_modify; 2901 2902 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32); 2903 2904 MLX5_SET(rqtc, rqtc, rqt_actual_size, 1); 2905 2906 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) { 2907 MLX5_SET(rqtc, rqtc, rq_num[0], priv->drop_rq.rqn); 2908 2909 err = mlx5_core_modify_rqt(priv->mdev, priv->channel[i].rqtn, in, inlen); 2910 if (err) 2911 goto err_modify; 2912 } 2913 2914 err_modify: 2915 kvfree(in); 2916 return (err); 2917 } 2918 2919 #define MLX5E_RSS_KEY_SIZE (10 * 4) /* bytes */ 2920 2921 static void 2922 mlx5e_get_rss_key(void *key_ptr) 2923 { 2924 #ifdef RSS 2925 rss_getkey(key_ptr); 2926 #else 2927 static const u32 rsskey[] = { 2928 cpu_to_be32(0xD181C62C), 2929 cpu_to_be32(0xF7F4DB5B), 2930 cpu_to_be32(0x1983A2FC), 2931 cpu_to_be32(0x943E1ADB), 2932 cpu_to_be32(0xD9389E6B), 2933 cpu_to_be32(0xD1039C2C), 2934 cpu_to_be32(0xA74499AD), 2935 cpu_to_be32(0x593D56D9), 2936 cpu_to_be32(0xF3253C06), 2937 cpu_to_be32(0x2ADC1FFC), 2938 }; 2939 CTASSERT(sizeof(rsskey) == MLX5E_RSS_KEY_SIZE); 2940 memcpy(key_ptr, rsskey, MLX5E_RSS_KEY_SIZE); 2941 #endif 2942 } 2943 2944 static void 2945 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt, bool inner_vxlan) 2946 { 2947 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 2948 void *hfsi = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 2949 void *hfs = inner_vxlan ? hfsi : hfso; 2950 __be32 *hkey; 2951 2952 MLX5_SET(tirc, tirc, transport_domain, priv->tdn); 2953 2954 #define ROUGH_MAX_L2_L3_HDR_SZ 256 2955 2956 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2957 MLX5_HASH_FIELD_SEL_DST_IP) 2958 2959 #define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2960 MLX5_HASH_FIELD_SEL_DST_IP |\ 2961 MLX5_HASH_FIELD_SEL_L4_SPORT |\ 2962 MLX5_HASH_FIELD_SEL_L4_DPORT) 2963 2964 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2965 MLX5_HASH_FIELD_SEL_DST_IP |\ 2966 MLX5_HASH_FIELD_SEL_IPSEC_SPI) 2967 2968 if (priv->params.hw_lro_en) { 2969 MLX5_SET(tirc, tirc, lro_enable_mask, 2970 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | 2971 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO); 2972 MLX5_SET(tirc, tirc, lro_max_msg_sz, 2973 (priv->params.lro_wqe_sz - 2974 ROUGH_MAX_L2_L3_HDR_SZ) >> 8); 2975 /* TODO: add the option to choose timer value dynamically */ 2976 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, 2977 MLX5_CAP_ETH(priv->mdev, 2978 lro_timer_supported_periods[2])); 2979 } 2980 2981 if (inner_vxlan) 2982 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 2983 2984 /* 2985 * All packets must go through the indirection table, RQT, 2986 * because it is not possible to modify the RQN of the TIR 2987 * for direct dispatchment after it is created, typically 2988 * when the link goes up and down. 2989 */ 2990 MLX5_SET(tirc, tirc, disp_type, 2991 MLX5_TIRC_DISP_TYPE_INDIRECT); 2992 MLX5_SET(tirc, tirc, indirect_table, 2993 priv->rqtn); 2994 MLX5_SET(tirc, tirc, rx_hash_fn, 2995 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ); 2996 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 2997 2998 CTASSERT(MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key) >= 2999 MLX5E_RSS_KEY_SIZE); 3000 #ifdef RSS 3001 /* 3002 * The FreeBSD RSS implementation does currently not 3003 * support symmetric Toeplitz hashes: 3004 */ 3005 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0); 3006 #else 3007 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 3008 #endif 3009 mlx5e_get_rss_key(hkey); 3010 3011 switch (tt) { 3012 case MLX5E_TT_IPV4_TCP: 3013 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3014 MLX5_L3_PROT_TYPE_IPV4); 3015 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type, 3016 MLX5_L4_PROT_TYPE_TCP); 3017 #ifdef RSS 3018 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) { 3019 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3020 MLX5_HASH_IP); 3021 } else 3022 #endif 3023 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3024 MLX5_HASH_ALL); 3025 break; 3026 3027 case MLX5E_TT_IPV6_TCP: 3028 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3029 MLX5_L3_PROT_TYPE_IPV6); 3030 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type, 3031 MLX5_L4_PROT_TYPE_TCP); 3032 #ifdef RSS 3033 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) { 3034 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3035 MLX5_HASH_IP); 3036 } else 3037 #endif 3038 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3039 MLX5_HASH_ALL); 3040 break; 3041 3042 case MLX5E_TT_IPV4_UDP: 3043 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3044 MLX5_L3_PROT_TYPE_IPV4); 3045 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type, 3046 MLX5_L4_PROT_TYPE_UDP); 3047 #ifdef RSS 3048 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) { 3049 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3050 MLX5_HASH_IP); 3051 } else 3052 #endif 3053 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3054 MLX5_HASH_ALL); 3055 break; 3056 3057 case MLX5E_TT_IPV6_UDP: 3058 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3059 MLX5_L3_PROT_TYPE_IPV6); 3060 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type, 3061 MLX5_L4_PROT_TYPE_UDP); 3062 #ifdef RSS 3063 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) { 3064 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3065 MLX5_HASH_IP); 3066 } else 3067 #endif 3068 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3069 MLX5_HASH_ALL); 3070 break; 3071 3072 case MLX5E_TT_IPV4_IPSEC_AH: 3073 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3074 MLX5_L3_PROT_TYPE_IPV4); 3075 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3076 MLX5_HASH_IP_IPSEC_SPI); 3077 break; 3078 3079 case MLX5E_TT_IPV6_IPSEC_AH: 3080 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3081 MLX5_L3_PROT_TYPE_IPV6); 3082 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3083 MLX5_HASH_IP_IPSEC_SPI); 3084 break; 3085 3086 case MLX5E_TT_IPV4_IPSEC_ESP: 3087 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3088 MLX5_L3_PROT_TYPE_IPV4); 3089 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3090 MLX5_HASH_IP_IPSEC_SPI); 3091 break; 3092 3093 case MLX5E_TT_IPV6_IPSEC_ESP: 3094 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3095 MLX5_L3_PROT_TYPE_IPV6); 3096 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3097 MLX5_HASH_IP_IPSEC_SPI); 3098 break; 3099 3100 case MLX5E_TT_IPV4: 3101 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3102 MLX5_L3_PROT_TYPE_IPV4); 3103 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3104 MLX5_HASH_IP); 3105 break; 3106 3107 case MLX5E_TT_IPV6: 3108 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3109 MLX5_L3_PROT_TYPE_IPV6); 3110 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3111 MLX5_HASH_IP); 3112 break; 3113 3114 default: 3115 break; 3116 } 3117 } 3118 3119 static int 3120 mlx5e_open_tir(struct mlx5e_priv *priv, int tt, bool inner_vxlan) 3121 { 3122 struct mlx5_core_dev *mdev = priv->mdev; 3123 u32 *in; 3124 void *tirc; 3125 int inlen; 3126 int err; 3127 3128 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 3129 in = mlx5_vzalloc(inlen); 3130 if (in == NULL) 3131 return (-ENOMEM); 3132 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context); 3133 3134 mlx5e_build_tir_ctx(priv, tirc, tt, inner_vxlan); 3135 3136 err = mlx5_core_create_tir(mdev, in, inlen, inner_vxlan ? 3137 &priv->tirn_inner_vxlan[tt] : &priv->tirn[tt]); 3138 3139 kvfree(in); 3140 3141 return (err); 3142 } 3143 3144 static void 3145 mlx5e_close_tir(struct mlx5e_priv *priv, int tt, bool inner_vxlan) 3146 { 3147 mlx5_core_destroy_tir(priv->mdev, inner_vxlan ? 3148 priv->tirn_inner_vxlan[tt] : priv->tirn[tt], 0); 3149 } 3150 3151 static int 3152 mlx5e_open_tirs(struct mlx5e_priv *priv) 3153 { 3154 int err; 3155 int i; 3156 3157 for (i = 0; i != 2 * MLX5E_NUM_TT; i++) { 3158 err = mlx5e_open_tir(priv, i / 2, (i % 2) ? true : false); 3159 if (err) 3160 goto err_close_tirs; 3161 } 3162 3163 return (0); 3164 3165 err_close_tirs: 3166 for (i--; i >= 0; i--) 3167 mlx5e_close_tir(priv, i / 2, (i % 2) ? true : false); 3168 3169 return (err); 3170 } 3171 3172 static void 3173 mlx5e_close_tirs(struct mlx5e_priv *priv) 3174 { 3175 int i; 3176 3177 for (i = 0; i != 2 * MLX5E_NUM_TT; i++) 3178 mlx5e_close_tir(priv, i / 2, (i % 2) ? true : false); 3179 } 3180 3181 /* 3182 * SW MTU does not include headers, 3183 * HW MTU includes all headers and checksums. 3184 */ 3185 static int 3186 mlx5e_set_dev_port_mtu(if_t ifp, int sw_mtu) 3187 { 3188 struct mlx5e_priv *priv = if_getsoftc(ifp); 3189 struct mlx5_core_dev *mdev = priv->mdev; 3190 int hw_mtu; 3191 int err; 3192 3193 hw_mtu = MLX5E_SW2HW_MTU(sw_mtu); 3194 3195 err = mlx5_set_port_mtu(mdev, hw_mtu); 3196 if (err) { 3197 mlx5_en_err(ifp, "mlx5_set_port_mtu failed setting %d, err=%d\n", 3198 sw_mtu, err); 3199 return (err); 3200 } 3201 3202 /* Update vport context MTU */ 3203 err = mlx5_set_vport_mtu(mdev, hw_mtu); 3204 if (err) { 3205 mlx5_en_err(ifp, 3206 "Failed updating vport context with MTU size, err=%d\n", 3207 err); 3208 } 3209 3210 if_setmtu(ifp, sw_mtu); 3211 3212 err = mlx5_query_vport_mtu(mdev, &hw_mtu); 3213 if (err || !hw_mtu) { 3214 /* fallback to port oper mtu */ 3215 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu); 3216 } 3217 if (err) { 3218 mlx5_en_err(ifp, 3219 "Query port MTU, after setting new MTU value, failed\n"); 3220 return (err); 3221 } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) { 3222 err = -E2BIG, 3223 mlx5_en_err(ifp, 3224 "Port MTU %d is smaller than ifp mtu %d\n", 3225 hw_mtu, sw_mtu); 3226 } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) { 3227 err = -EINVAL; 3228 mlx5_en_err(ifp, 3229 "Port MTU %d is bigger than ifp mtu %d\n", 3230 hw_mtu, sw_mtu); 3231 } 3232 priv->params_ethtool.hw_mtu = hw_mtu; 3233 3234 /* compute MSB */ 3235 while (hw_mtu & (hw_mtu - 1)) 3236 hw_mtu &= (hw_mtu - 1); 3237 priv->params_ethtool.hw_mtu_msb = hw_mtu; 3238 3239 return (err); 3240 } 3241 3242 int 3243 mlx5e_open_locked(if_t ifp) 3244 { 3245 struct mlx5e_priv *priv = if_getsoftc(ifp); 3246 int err; 3247 u16 set_id; 3248 3249 /* check if already opened */ 3250 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 3251 return (0); 3252 3253 #ifdef RSS 3254 if (rss_getnumbuckets() > priv->params.num_channels) { 3255 mlx5_en_info(ifp, 3256 "NOTE: There are more RSS buckets(%u) than channels(%u) available\n", 3257 rss_getnumbuckets(), priv->params.num_channels); 3258 } 3259 #endif 3260 err = mlx5e_open_tises(priv); 3261 if (err) { 3262 mlx5_en_err(ifp, "mlx5e_open_tises failed, %d\n", err); 3263 return (err); 3264 } 3265 err = mlx5_vport_alloc_q_counter(priv->mdev, 3266 MLX5_INTERFACE_PROTOCOL_ETH, &set_id); 3267 if (err) { 3268 mlx5_en_err(priv->ifp, 3269 "mlx5_vport_alloc_q_counter failed: %d\n", err); 3270 goto err_close_tises; 3271 } 3272 /* store counter set ID */ 3273 priv->counter_set_id = set_id; 3274 3275 err = mlx5e_open_channels(priv); 3276 if (err) { 3277 mlx5_en_err(ifp, 3278 "mlx5e_open_channels failed, %d\n", err); 3279 goto err_dalloc_q_counter; 3280 } 3281 err = mlx5e_activate_rqt(priv); 3282 if (err) { 3283 mlx5_en_err(ifp, "mlx5e_activate_rqt failed, %d\n", err); 3284 goto err_close_channels; 3285 } 3286 3287 set_bit(MLX5E_STATE_OPENED, &priv->state); 3288 3289 mlx5e_update_carrier(priv); 3290 3291 return (0); 3292 3293 err_close_channels: 3294 mlx5e_close_channels(priv); 3295 3296 err_dalloc_q_counter: 3297 mlx5_vport_dealloc_q_counter(priv->mdev, 3298 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 3299 3300 err_close_tises: 3301 mlx5e_close_tises(priv); 3302 3303 return (err); 3304 } 3305 3306 static void 3307 mlx5e_open(void *arg) 3308 { 3309 struct mlx5e_priv *priv = arg; 3310 3311 PRIV_LOCK(priv); 3312 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP)) 3313 mlx5_en_err(priv->ifp, 3314 "Setting port status to up failed\n"); 3315 3316 mlx5e_open_locked(priv->ifp); 3317 if_setdrvflagbits(priv->ifp, IFF_DRV_RUNNING, 0); 3318 PRIV_UNLOCK(priv); 3319 } 3320 3321 int 3322 mlx5e_close_locked(if_t ifp) 3323 { 3324 struct mlx5e_priv *priv = if_getsoftc(ifp); 3325 3326 /* check if already closed */ 3327 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3328 return (0); 3329 3330 clear_bit(MLX5E_STATE_OPENED, &priv->state); 3331 3332 if_link_state_change(priv->ifp, LINK_STATE_DOWN); 3333 3334 mlx5e_deactivate_rqt(priv); 3335 mlx5e_close_channels(priv); 3336 mlx5_vport_dealloc_q_counter(priv->mdev, 3337 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 3338 mlx5e_close_tises(priv); 3339 3340 return (0); 3341 } 3342 3343 static uint64_t 3344 mlx5e_get_counter(if_t ifp, ift_counter cnt) 3345 { 3346 struct mlx5e_priv *priv = if_getsoftc(ifp); 3347 u64 retval; 3348 3349 /* PRIV_LOCK(priv); XXX not allowed */ 3350 switch (cnt) { 3351 case IFCOUNTER_IPACKETS: 3352 retval = priv->stats.vport.rx_packets; 3353 break; 3354 case IFCOUNTER_IERRORS: 3355 retval = priv->stats.pport.in_range_len_errors + 3356 priv->stats.pport.out_of_range_len + 3357 priv->stats.pport.too_long_errors + 3358 priv->stats.pport.check_seq_err + 3359 priv->stats.pport.alignment_err; 3360 break; 3361 case IFCOUNTER_IQDROPS: 3362 retval = priv->stats.vport.rx_out_of_buffer; 3363 break; 3364 case IFCOUNTER_OPACKETS: 3365 retval = priv->stats.vport.tx_packets; 3366 break; 3367 case IFCOUNTER_OERRORS: 3368 retval = priv->stats.port_stats_debug.out_discards; 3369 break; 3370 case IFCOUNTER_IBYTES: 3371 retval = priv->stats.vport.rx_bytes; 3372 break; 3373 case IFCOUNTER_OBYTES: 3374 retval = priv->stats.vport.tx_bytes; 3375 break; 3376 case IFCOUNTER_IMCASTS: 3377 retval = priv->stats.vport.rx_multicast_packets; 3378 break; 3379 case IFCOUNTER_OMCASTS: 3380 retval = priv->stats.vport.tx_multicast_packets; 3381 break; 3382 case IFCOUNTER_OQDROPS: 3383 retval = priv->stats.vport.tx_queue_dropped; 3384 break; 3385 case IFCOUNTER_COLLISIONS: 3386 retval = priv->stats.pport.collisions; 3387 break; 3388 default: 3389 retval = if_get_counter_default(ifp, cnt); 3390 break; 3391 } 3392 /* PRIV_UNLOCK(priv); XXX not allowed */ 3393 return (retval); 3394 } 3395 3396 static void 3397 mlx5e_set_rx_mode(if_t ifp) 3398 { 3399 struct mlx5e_priv *priv = if_getsoftc(ifp); 3400 3401 queue_work(priv->wq, &priv->set_rx_mode_work); 3402 } 3403 3404 static int 3405 mlx5e_ioctl(if_t ifp, u_long command, caddr_t data) 3406 { 3407 struct mlx5e_priv *priv; 3408 struct ifreq *ifr; 3409 struct ifdownreason *ifdr; 3410 struct ifi2creq i2c; 3411 struct ifrsskey *ifrk; 3412 struct ifrsshash *ifrh; 3413 struct siocsifcapnv_driver_data *drv_ioctl_data, drv_ioctl_data_d; 3414 int error = 0; 3415 int mask; 3416 int size_read = 0; 3417 int module_status; 3418 int module_num; 3419 int max_mtu; 3420 uint8_t read_addr; 3421 3422 priv = if_getsoftc(ifp); 3423 3424 /* check if detaching */ 3425 if (priv == NULL || priv->gone != 0) 3426 return (ENXIO); 3427 3428 switch (command) { 3429 case SIOCSIFMTU: 3430 ifr = (struct ifreq *)data; 3431 3432 PRIV_LOCK(priv); 3433 mlx5_query_port_max_mtu(priv->mdev, &max_mtu); 3434 3435 if (ifr->ifr_mtu >= MLX5E_MTU_MIN && 3436 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) { 3437 int was_opened; 3438 3439 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 3440 if (was_opened) 3441 mlx5e_close_locked(ifp); 3442 3443 /* set new MTU */ 3444 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu); 3445 3446 if (was_opened) 3447 mlx5e_open_locked(ifp); 3448 } else { 3449 error = EINVAL; 3450 mlx5_en_err(ifp, 3451 "Invalid MTU value. Min val: %d, Max val: %d\n", 3452 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu)); 3453 } 3454 PRIV_UNLOCK(priv); 3455 break; 3456 case SIOCSIFFLAGS: 3457 if ((if_getflags(ifp) & IFF_UP) && 3458 (if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 3459 mlx5e_set_rx_mode(ifp); 3460 break; 3461 } 3462 PRIV_LOCK(priv); 3463 if (if_getflags(ifp) & IFF_UP) { 3464 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 3465 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3466 mlx5e_open_locked(ifp); 3467 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 3468 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP); 3469 } 3470 } else { 3471 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3472 mlx5_set_port_status(priv->mdev, 3473 MLX5_PORT_DOWN); 3474 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 3475 mlx5e_close_locked(ifp); 3476 mlx5e_update_carrier(priv); 3477 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3478 } 3479 } 3480 PRIV_UNLOCK(priv); 3481 break; 3482 case SIOCADDMULTI: 3483 case SIOCDELMULTI: 3484 mlx5e_set_rx_mode(ifp); 3485 break; 3486 case SIOCSIFMEDIA: 3487 case SIOCGIFMEDIA: 3488 case SIOCGIFXMEDIA: 3489 ifr = (struct ifreq *)data; 3490 error = ifmedia_ioctl(ifp, ifr, &priv->media, command); 3491 break; 3492 case SIOCGIFCAPNV: 3493 error = 0; 3494 break; 3495 case SIOCSIFCAP: 3496 ifr = (struct ifreq *)data; 3497 drv_ioctl_data = &drv_ioctl_data_d; 3498 drv_ioctl_data->reqcap = ifr->ifr_reqcap; 3499 PRIV_LOCK(priv); 3500 drv_ioctl_data->reqcap2 = if_getcapenable2(ifp); 3501 drv_ioctl_data->nvcap = NULL; 3502 goto siocsifcap_driver; 3503 case SIOCSIFCAPNV: 3504 drv_ioctl_data = (struct siocsifcapnv_driver_data *)data; 3505 PRIV_LOCK(priv); 3506 siocsifcap_driver: 3507 mask = drv_ioctl_data->reqcap ^ if_getcapenable(ifp); 3508 3509 if (mask & IFCAP_TXCSUM) { 3510 if_togglecapenable(ifp, IFCAP_TXCSUM); 3511 if_togglehwassist(ifp, (CSUM_TCP | CSUM_UDP | CSUM_IP)); 3512 3513 if (IFCAP_TSO4 & if_getcapenable(ifp) && 3514 !(IFCAP_TXCSUM & if_getcapenable(ifp))) { 3515 mask &= ~IFCAP_TSO4; 3516 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 3517 if_sethwassistbits(ifp, 0, CSUM_IP_TSO); 3518 mlx5_en_err(ifp, 3519 "tso4 disabled due to -txcsum.\n"); 3520 } 3521 } 3522 if (mask & IFCAP_TXCSUM_IPV6) { 3523 if_togglecapenable(ifp, IFCAP_TXCSUM_IPV6); 3524 if_togglehwassist(ifp, (CSUM_UDP_IPV6 | CSUM_TCP_IPV6)); 3525 3526 if (IFCAP_TSO6 & if_getcapenable(ifp) && 3527 !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) { 3528 mask &= ~IFCAP_TSO6; 3529 if_setcapenablebit(ifp, 0, IFCAP_TSO6); 3530 if_sethwassistbits(ifp, 0, CSUM_IP6_TSO); 3531 mlx5_en_err(ifp, 3532 "tso6 disabled due to -txcsum6.\n"); 3533 } 3534 } 3535 if (mask & IFCAP_MEXTPG) 3536 if_togglecapenable(ifp, IFCAP_MEXTPG); 3537 if (mask & IFCAP_TXTLS4) 3538 if_togglecapenable(ifp, IFCAP_TXTLS4); 3539 if (mask & IFCAP_TXTLS6) 3540 if_togglecapenable(ifp, IFCAP_TXTLS6); 3541 #ifdef RATELIMIT 3542 if (mask & IFCAP_TXTLS_RTLMT) 3543 if_togglecapenable(ifp, IFCAP_TXTLS_RTLMT); 3544 #endif 3545 if (mask & IFCAP_RXCSUM) 3546 if_togglecapenable(ifp, IFCAP_RXCSUM); 3547 if (mask & IFCAP_RXCSUM_IPV6) 3548 if_togglecapenable(ifp, IFCAP_RXCSUM_IPV6); 3549 if (mask & IFCAP_TSO4) { 3550 if (!(IFCAP_TSO4 & if_getcapenable(ifp)) && 3551 !(IFCAP_TXCSUM & if_getcapenable(ifp))) { 3552 mlx5_en_err(ifp, "enable txcsum first.\n"); 3553 error = EAGAIN; 3554 goto out; 3555 } 3556 if_togglecapenable(ifp, IFCAP_TSO4); 3557 if_togglehwassist(ifp, CSUM_IP_TSO); 3558 } 3559 if (mask & IFCAP_TSO6) { 3560 if (!(IFCAP_TSO6 & if_getcapenable(ifp)) && 3561 !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) { 3562 mlx5_en_err(ifp, "enable txcsum6 first.\n"); 3563 error = EAGAIN; 3564 goto out; 3565 } 3566 if_togglecapenable(ifp, IFCAP_TSO6); 3567 if_togglehwassist(ifp, CSUM_IP6_TSO); 3568 } 3569 if (mask & IFCAP_VLAN_HWTSO) 3570 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 3571 if (mask & IFCAP_VLAN_HWFILTER) { 3572 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 3573 mlx5e_disable_vlan_filter(priv); 3574 else 3575 mlx5e_enable_vlan_filter(priv); 3576 3577 if_togglecapenable(ifp, IFCAP_VLAN_HWFILTER); 3578 } 3579 if (mask & IFCAP_VLAN_HWTAGGING) 3580 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 3581 if (mask & IFCAP_WOL_MAGIC) 3582 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 3583 if (mask & IFCAP_VXLAN_HWCSUM) { 3584 const bool was_enabled = 3585 (if_getcapenable(ifp) & IFCAP_VXLAN_HWCSUM) != 0; 3586 if (was_enabled) 3587 mlx5e_del_all_vxlan_rules(priv); 3588 if_togglecapenable(ifp, IFCAP_VXLAN_HWCSUM); 3589 if_togglehwassist(ifp, CSUM_INNER_IP | CSUM_INNER_IP_UDP | 3590 CSUM_INNER_IP_TCP | CSUM_INNER_IP6_UDP | 3591 CSUM_INNER_IP6_TCP); 3592 if (!was_enabled) { 3593 int err = mlx5e_add_all_vxlan_rules(priv); 3594 if (err != 0) { 3595 mlx5_en_err(ifp, 3596 "mlx5e_add_all_vxlan_rules() failed, %d (ignored)\n", err); 3597 } 3598 } 3599 } 3600 if (mask & IFCAP_VXLAN_HWTSO) { 3601 if_togglecapenable(ifp, IFCAP_VXLAN_HWTSO); 3602 if_togglehwassist(ifp, CSUM_INNER_IP_TSO | 3603 CSUM_INNER_IP6_TSO); 3604 } 3605 3606 VLAN_CAPABILITIES(ifp); 3607 /* turn off LRO means also turn of HW LRO - if it's on */ 3608 if (mask & IFCAP_LRO) { 3609 int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 3610 bool need_restart = false; 3611 3612 if_togglecapenable(ifp, IFCAP_LRO); 3613 3614 /* figure out if updating HW LRO is needed */ 3615 if (!(if_getcapenable(ifp) & IFCAP_LRO)) { 3616 if (priv->params.hw_lro_en) { 3617 priv->params.hw_lro_en = false; 3618 need_restart = true; 3619 } 3620 } else { 3621 if (priv->params.hw_lro_en == false && 3622 priv->params_ethtool.hw_lro != 0) { 3623 priv->params.hw_lro_en = true; 3624 need_restart = true; 3625 } 3626 } 3627 if (was_opened && need_restart) { 3628 mlx5e_close_locked(ifp); 3629 mlx5e_open_locked(ifp); 3630 } 3631 } 3632 if (mask & IFCAP_HWRXTSTMP) { 3633 if_togglecapenable(ifp, IFCAP_HWRXTSTMP); 3634 if (if_getcapenable(ifp) & IFCAP_HWRXTSTMP) { 3635 if (priv->clbr_done == 0) 3636 mlx5e_reset_calibration_callout(priv); 3637 } else { 3638 callout_drain(&priv->tstmp_clbr); 3639 priv->clbr_done = 0; 3640 } 3641 } 3642 mask = drv_ioctl_data->reqcap2 ^ if_getcapenable2(ifp); 3643 if ((mask & IFCAP2_BIT(IFCAP2_RXTLS4)) != 0) 3644 if_togglecapenable2(ifp, IFCAP2_BIT(IFCAP2_RXTLS4)); 3645 if ((mask & IFCAP2_BIT(IFCAP2_RXTLS6)) != 0) 3646 if_togglecapenable2(ifp, IFCAP2_BIT(IFCAP2_RXTLS6)); 3647 #ifdef IPSEC_OFFLOAD 3648 if ((mask & IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD)) != 0) { 3649 bool was_enabled = (if_getcapenable2(ifp) & 3650 IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD)) != 0; 3651 mlx5e_close_locked(ifp); 3652 if (was_enabled) 3653 ipsec_accel_on_ifdown(priv->ifp); 3654 if_togglecapenable2(ifp, 3655 IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD)); 3656 mlx5e_open_locked(ifp); 3657 } 3658 #endif 3659 out: 3660 PRIV_UNLOCK(priv); 3661 break; 3662 3663 case SIOCGI2C: 3664 ifr = (struct ifreq *)data; 3665 3666 /* 3667 * Copy from the user-space address ifr_data to the 3668 * kernel-space address i2c 3669 */ 3670 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 3671 if (error) 3672 break; 3673 3674 if (i2c.len > sizeof(i2c.data)) { 3675 error = EINVAL; 3676 break; 3677 } 3678 3679 PRIV_LOCK(priv); 3680 /* Get module_num which is required for the query_eeprom */ 3681 error = mlx5_query_module_num(priv->mdev, &module_num); 3682 if (error) { 3683 mlx5_en_err(ifp, 3684 "Query module num failed, eeprom reading is not supported\n"); 3685 error = EINVAL; 3686 goto err_i2c; 3687 } 3688 /* Check if module is present before doing an access */ 3689 module_status = mlx5_query_module_status(priv->mdev, module_num); 3690 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED) { 3691 if (bootverbose) 3692 mlx5_en_err(ifp, 3693 "Query module %d status: not plugged (%d), " 3694 "eeprom reading is not supported\n", 3695 module_num, module_status); 3696 error = EINVAL; 3697 goto err_i2c; 3698 } 3699 /* 3700 * Currently 0XA0 and 0xA2 are the only addresses permitted. 3701 * The internal conversion is as follows: 3702 */ 3703 if (i2c.dev_addr == 0xA0) 3704 read_addr = MLX5_I2C_ADDR_LOW; 3705 else if (i2c.dev_addr == 0xA2) 3706 read_addr = MLX5_I2C_ADDR_HIGH; 3707 else { 3708 mlx5_en_err(ifp, 3709 "Query eeprom failed, Invalid Address: %X\n", 3710 i2c.dev_addr); 3711 error = EINVAL; 3712 goto err_i2c; 3713 } 3714 error = mlx5_query_eeprom(priv->mdev, 3715 read_addr, MLX5_EEPROM_LOW_PAGE, 3716 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num, 3717 (uint32_t *)i2c.data, &size_read); 3718 if (error) { 3719 mlx5_en_err(ifp, 3720 "Query eeprom failed, eeprom reading is not supported\n"); 3721 error = EINVAL; 3722 goto err_i2c; 3723 } 3724 3725 if (i2c.len > MLX5_EEPROM_MAX_BYTES) { 3726 error = mlx5_query_eeprom(priv->mdev, 3727 read_addr, MLX5_EEPROM_LOW_PAGE, 3728 (uint32_t)(i2c.offset + size_read), 3729 (uint32_t)(i2c.len - size_read), module_num, 3730 (uint32_t *)(i2c.data + size_read), &size_read); 3731 } 3732 if (error) { 3733 mlx5_en_err(ifp, 3734 "Query eeprom failed, eeprom reading is not supported\n"); 3735 error = EINVAL; 3736 goto err_i2c; 3737 } 3738 3739 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 3740 err_i2c: 3741 PRIV_UNLOCK(priv); 3742 break; 3743 case SIOCGIFDOWNREASON: 3744 ifdr = (struct ifdownreason *)data; 3745 bzero(ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg)); 3746 PRIV_LOCK(priv); 3747 error = -mlx5_query_pddr_troubleshooting_info(priv->mdev, NULL, 3748 ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg)); 3749 PRIV_UNLOCK(priv); 3750 if (error == 0) 3751 ifdr->ifdr_reason = IFDR_REASON_MSG; 3752 break; 3753 3754 case SIOCGIFRSSKEY: 3755 ifrk = (struct ifrsskey *)data; 3756 ifrk->ifrk_func = RSS_FUNC_TOEPLITZ; 3757 ifrk->ifrk_keylen = MLX5E_RSS_KEY_SIZE; 3758 CTASSERT(sizeof(ifrk->ifrk_key) >= MLX5E_RSS_KEY_SIZE); 3759 mlx5e_get_rss_key(ifrk->ifrk_key); 3760 break; 3761 3762 case SIOCGIFRSSHASH: 3763 ifrh = (struct ifrsshash *)data; 3764 ifrh->ifrh_func = RSS_FUNC_TOEPLITZ; 3765 ifrh->ifrh_types = 3766 RSS_TYPE_IPV4 | 3767 RSS_TYPE_TCP_IPV4 | 3768 RSS_TYPE_UDP_IPV4 | 3769 RSS_TYPE_IPV6 | 3770 RSS_TYPE_TCP_IPV6 | 3771 RSS_TYPE_UDP_IPV6; 3772 break; 3773 3774 default: 3775 error = ether_ioctl(ifp, command, data); 3776 break; 3777 } 3778 return (error); 3779 } 3780 3781 static int 3782 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev) 3783 { 3784 /* 3785 * TODO: uncoment once FW really sets all these bits if 3786 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap || 3787 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap || 3788 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return 3789 * -ENOTSUPP; 3790 */ 3791 3792 /* TODO: add more must-to-have features */ 3793 3794 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) 3795 return (-ENODEV); 3796 3797 return (0); 3798 } 3799 3800 static u16 3801 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev) 3802 { 3803 const int min_size = ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN; 3804 const int max_size = MLX5E_MAX_TX_INLINE; 3805 const int bf_buf_size = 3806 ((1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U) - 3807 (sizeof(struct mlx5e_tx_wqe) - 2); 3808 3809 /* verify against driver limits */ 3810 if (bf_buf_size > max_size) 3811 return (max_size); 3812 else if (bf_buf_size < min_size) 3813 return (min_size); 3814 else 3815 return (bf_buf_size); 3816 } 3817 3818 static int 3819 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev, 3820 struct mlx5e_priv *priv, 3821 int num_comp_vectors) 3822 { 3823 int err; 3824 3825 /* 3826 * TODO: Consider link speed for setting "log_sq_size", 3827 * "log_rq_size" and "cq_moderation_xxx": 3828 */ 3829 priv->params.log_sq_size = 3830 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; 3831 priv->params.log_rq_size = 3832 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; 3833 priv->params.rx_cq_moderation_usec = 3834 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 3835 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE : 3836 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; 3837 priv->params.rx_cq_moderation_mode = 3838 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0; 3839 priv->params.rx_cq_moderation_pkts = 3840 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; 3841 priv->params.tx_cq_moderation_usec = 3842 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; 3843 priv->params.tx_cq_moderation_pkts = 3844 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; 3845 priv->params.rx_hash_log_tbl_sz = 3846 (order_base_2(num_comp_vectors) > 3847 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ? 3848 order_base_2(num_comp_vectors) : 3849 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ; 3850 priv->params.num_tc = 1; 3851 priv->params.default_vlan_prio = 0; 3852 priv->counter_set_id = -1; 3853 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev); 3854 3855 err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode); 3856 if (err) 3857 return (err); 3858 3859 /* 3860 * hw lro is currently defaulted to off. when it won't anymore we 3861 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)" 3862 */ 3863 priv->params.hw_lro_en = false; 3864 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; 3865 3866 /* 3867 * CQE zipping is off, because the per-packet 32-bit Toeplitz hash 3868 * is then not supported. The 32-bit Toeplitz hash is needed to 3869 * correctly demultiplex incoming traffic into the expected 3870 * network queues. 3871 */ 3872 priv->params.cqe_zipping_en = false; 3873 3874 priv->mdev = mdev; 3875 priv->params.num_channels = num_comp_vectors; 3876 priv->params.channels_rsss = 1; 3877 priv->order_base_2_num_channels = order_base_2(num_comp_vectors); 3878 priv->queue_mapping_channel_mask = 3879 roundup_pow_of_two(num_comp_vectors) - 1; 3880 priv->num_tc = priv->params.num_tc; 3881 priv->default_vlan_prio = priv->params.default_vlan_prio; 3882 3883 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work); 3884 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); 3885 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); 3886 3887 return (0); 3888 } 3889 3890 static void 3891 mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc) 3892 { 3893 bool ro_pci_enable = 3894 pci_get_relaxed_ordering_enabled(mdev->pdev->dev.bsddev); 3895 bool ro_write = MLX5_CAP_GEN(mdev, relaxed_ordering_write); 3896 bool ro_read = MLX5_CAP_GEN(mdev, relaxed_ordering_read); 3897 3898 MLX5_SET(mkc, mkc, relaxed_ordering_read, ro_pci_enable && ro_read); 3899 MLX5_SET(mkc, mkc, relaxed_ordering_write, ro_pci_enable && ro_write); 3900 } 3901 3902 static int 3903 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn, 3904 struct mlx5_core_mkey *mkey) 3905 { 3906 if_t ifp = priv->ifp; 3907 struct mlx5_core_dev *mdev = priv->mdev; 3908 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 3909 void *mkc; 3910 u32 *in; 3911 int err; 3912 3913 in = mlx5_vzalloc(inlen); 3914 if (in == NULL) { 3915 mlx5_en_err(ifp, "failed to allocate inbox\n"); 3916 return (-ENOMEM); 3917 } 3918 3919 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 3920 MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA); 3921 MLX5_SET(mkc, mkc, umr_en, 1); /* used by HW TLS */ 3922 MLX5_SET(mkc, mkc, lw, 1); 3923 MLX5_SET(mkc, mkc, lr, 1); 3924 mlx5e_mkey_set_relaxed_ordering(mdev, mkc); 3925 MLX5_SET(mkc, mkc, pd, pdn); 3926 MLX5_SET(mkc, mkc, length64, 1); 3927 MLX5_SET(mkc, mkc, qpn, 0xffffff); 3928 3929 err = mlx5_core_create_mkey(mdev, mkey, in, inlen); 3930 if (err) 3931 mlx5_en_err(ifp, "mlx5_core_create_mkey failed, %d\n", 3932 err); 3933 3934 kvfree(in); 3935 return (err); 3936 } 3937 3938 static const char *mlx5e_vport_stats_desc[] = { 3939 MLX5E_VPORT_STATS(MLX5E_STATS_DESC) 3940 }; 3941 3942 static const char *mlx5e_pport_stats_desc[] = { 3943 MLX5E_PPORT_STATS(MLX5E_STATS_DESC) 3944 }; 3945 3946 static int 3947 mlx5e_priv_static_init(struct mlx5e_priv *priv, struct mlx5_core_dev *mdev, 3948 const uint32_t channels) 3949 { 3950 uint32_t x; 3951 int err; 3952 3953 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF); 3954 sx_init(&priv->state_lock, "mlx5state"); 3955 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0); 3956 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock); 3957 for (x = 0; x != channels; x++) 3958 mlx5e_chan_static_init(priv, &priv->channel[x], x); 3959 3960 for (x = 0; x != channels; x++) { 3961 err = mlx5_alloc_bfreg(mdev, &priv->channel[x].bfreg, false, false); 3962 if (err) 3963 goto err_alloc_bfreg; 3964 } 3965 return (0); 3966 3967 err_alloc_bfreg: 3968 while (x--) 3969 mlx5_free_bfreg(mdev, &priv->channel[x].bfreg); 3970 3971 for (x = 0; x != channels; x++) 3972 mlx5e_chan_static_destroy(&priv->channel[x]); 3973 callout_drain(&priv->watchdog); 3974 mtx_destroy(&priv->async_events_mtx); 3975 sx_destroy(&priv->state_lock); 3976 return (err); 3977 } 3978 3979 static void 3980 mlx5e_priv_static_destroy(struct mlx5e_priv *priv, struct mlx5_core_dev *mdev, 3981 const uint32_t channels) 3982 { 3983 uint32_t x; 3984 3985 for (x = 0; x != channels; x++) 3986 mlx5_free_bfreg(mdev, &priv->channel[x].bfreg); 3987 for (x = 0; x != channels; x++) 3988 mlx5e_chan_static_destroy(&priv->channel[x]); 3989 callout_drain(&priv->watchdog); 3990 mtx_destroy(&priv->async_events_mtx); 3991 sx_destroy(&priv->state_lock); 3992 } 3993 3994 static int 3995 sysctl_firmware(SYSCTL_HANDLER_ARGS) 3996 { 3997 /* 3998 * %d.%d%.d the string format. 3999 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536. 4000 * We need at most 5 chars to store that. 4001 * It also has: two "." and NULL at the end, which means we need 18 4002 * (5*3 + 3) chars at most. 4003 */ 4004 char fw[18]; 4005 struct mlx5e_priv *priv = arg1; 4006 int error; 4007 4008 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev), 4009 fw_rev_sub(priv->mdev)); 4010 error = sysctl_handle_string(oidp, fw, sizeof(fw), req); 4011 return (error); 4012 } 4013 4014 static void 4015 mlx5e_disable_tx_dma(struct mlx5e_channel *ch) 4016 { 4017 int i; 4018 4019 for (i = 0; i < ch->priv->num_tc; i++) 4020 mlx5e_drain_sq(&ch->sq[i]); 4021 } 4022 4023 static void 4024 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq) 4025 { 4026 4027 sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP); 4028 sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8); 4029 mlx5e_tx_notify_hw(sq, true); 4030 } 4031 4032 void 4033 mlx5e_resume_sq(struct mlx5e_sq *sq) 4034 { 4035 int err; 4036 4037 /* check if already enabled */ 4038 if (READ_ONCE(sq->running) != 0) 4039 return; 4040 4041 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR, 4042 MLX5_SQC_STATE_RST); 4043 if (err != 0) { 4044 mlx5_en_err(sq->ifp, 4045 "mlx5e_modify_sq() from ERR to RST failed: %d\n", err); 4046 } 4047 4048 sq->cc = 0; 4049 sq->pc = 0; 4050 4051 /* reset doorbell prior to moving from RST to RDY */ 4052 mlx5e_reset_sq_doorbell_record(sq); 4053 4054 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, 4055 MLX5_SQC_STATE_RDY); 4056 if (err != 0) { 4057 mlx5_en_err(sq->ifp, 4058 "mlx5e_modify_sq() from RST to RDY failed: %d\n", err); 4059 } 4060 4061 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL; 4062 WRITE_ONCE(sq->running, 1); 4063 } 4064 4065 static void 4066 mlx5e_enable_tx_dma(struct mlx5e_channel *ch) 4067 { 4068 int i; 4069 4070 for (i = 0; i < ch->priv->num_tc; i++) 4071 mlx5e_resume_sq(&ch->sq[i]); 4072 } 4073 4074 static void 4075 mlx5e_disable_rx_dma(struct mlx5e_channel *ch) 4076 { 4077 struct mlx5e_rq *rq = &ch->rq; 4078 struct epoch_tracker et; 4079 int err; 4080 4081 mtx_lock(&rq->mtx); 4082 rq->enabled = 0; 4083 callout_stop(&rq->watchdog); 4084 mtx_unlock(&rq->mtx); 4085 4086 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 4087 if (err != 0) { 4088 mlx5_en_err(rq->ifp, 4089 "mlx5e_modify_rq() from RDY to RST failed: %d\n", err); 4090 } 4091 4092 while (!mlx5_wq_ll_is_empty(&rq->wq)) { 4093 msleep(1); 4094 NET_EPOCH_ENTER(et); 4095 rq->cq.mcq.comp(&rq->cq.mcq, NULL); 4096 NET_EPOCH_EXIT(et); 4097 } 4098 4099 /* 4100 * Transitioning into RST state will allow the FW to track less ERR state queues, 4101 * thus reducing the recv queue flushing time 4102 */ 4103 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST); 4104 if (err != 0) { 4105 mlx5_en_err(rq->ifp, 4106 "mlx5e_modify_rq() from ERR to RST failed: %d\n", err); 4107 } 4108 } 4109 4110 static void 4111 mlx5e_enable_rx_dma(struct mlx5e_channel *ch) 4112 { 4113 struct mlx5e_rq *rq = &ch->rq; 4114 struct epoch_tracker et; 4115 int err; 4116 4117 rq->wq.wqe_ctr = 0; 4118 mlx5_wq_ll_update_db_record(&rq->wq); 4119 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 4120 if (err != 0) { 4121 mlx5_en_err(rq->ifp, 4122 "mlx5e_modify_rq() from RST to RDY failed: %d\n", err); 4123 } 4124 4125 rq->enabled = 1; 4126 4127 NET_EPOCH_ENTER(et); 4128 rq->cq.mcq.comp(&rq->cq.mcq, NULL); 4129 NET_EPOCH_EXIT(et); 4130 } 4131 4132 void 4133 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value) 4134 { 4135 int i; 4136 4137 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 4138 return; 4139 4140 for (i = 0; i < priv->params.num_channels; i++) { 4141 if (value) 4142 mlx5e_disable_tx_dma(&priv->channel[i]); 4143 else 4144 mlx5e_enable_tx_dma(&priv->channel[i]); 4145 } 4146 } 4147 4148 void 4149 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value) 4150 { 4151 int i; 4152 4153 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 4154 return; 4155 4156 for (i = 0; i < priv->params.num_channels; i++) { 4157 if (value) 4158 mlx5e_disable_rx_dma(&priv->channel[i]); 4159 else 4160 mlx5e_enable_rx_dma(&priv->channel[i]); 4161 } 4162 } 4163 4164 static void 4165 mlx5e_add_hw_stats(struct mlx5e_priv *priv) 4166 { 4167 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 4168 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 4169 priv, 0, sysctl_firmware, "A", "HCA firmware version"); 4170 4171 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 4172 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0, 4173 "Board ID"); 4174 } 4175 4176 static int 4177 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS) 4178 { 4179 struct mlx5e_priv *priv = arg1; 4180 uint8_t temp[MLX5E_MAX_PRIORITY]; 4181 uint32_t tx_pfc; 4182 int err; 4183 int i; 4184 4185 PRIV_LOCK(priv); 4186 4187 tx_pfc = priv->params.tx_priority_flow_control; 4188 4189 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) 4190 temp[i] = (tx_pfc >> i) & 1; 4191 4192 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY); 4193 if (err || !req->newptr) 4194 goto done; 4195 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY); 4196 if (err) 4197 goto done; 4198 4199 priv->params.tx_priority_flow_control = 0; 4200 4201 /* range check input value */ 4202 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) { 4203 if (temp[i] > 1) { 4204 err = ERANGE; 4205 goto done; 4206 } 4207 priv->params.tx_priority_flow_control |= (temp[i] << i); 4208 } 4209 4210 /* check if update is required */ 4211 if (tx_pfc != priv->params.tx_priority_flow_control) 4212 err = -mlx5e_set_port_pfc(priv); 4213 done: 4214 if (err != 0) 4215 priv->params.tx_priority_flow_control= tx_pfc; 4216 PRIV_UNLOCK(priv); 4217 4218 return (err); 4219 } 4220 4221 static int 4222 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS) 4223 { 4224 struct mlx5e_priv *priv = arg1; 4225 uint8_t temp[MLX5E_MAX_PRIORITY]; 4226 uint32_t rx_pfc; 4227 int err; 4228 int i; 4229 4230 PRIV_LOCK(priv); 4231 4232 rx_pfc = priv->params.rx_priority_flow_control; 4233 4234 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) 4235 temp[i] = (rx_pfc >> i) & 1; 4236 4237 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY); 4238 if (err || !req->newptr) 4239 goto done; 4240 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY); 4241 if (err) 4242 goto done; 4243 4244 priv->params.rx_priority_flow_control = 0; 4245 4246 /* range check input value */ 4247 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) { 4248 if (temp[i] > 1) { 4249 err = ERANGE; 4250 goto done; 4251 } 4252 priv->params.rx_priority_flow_control |= (temp[i] << i); 4253 } 4254 4255 /* check if update is required */ 4256 if (rx_pfc != priv->params.rx_priority_flow_control) { 4257 err = -mlx5e_set_port_pfc(priv); 4258 if (err == 0 && priv->sw_is_port_buf_owner) 4259 err = mlx5e_update_buf_lossy(priv); 4260 } 4261 done: 4262 if (err != 0) 4263 priv->params.rx_priority_flow_control= rx_pfc; 4264 PRIV_UNLOCK(priv); 4265 4266 return (err); 4267 } 4268 4269 static void 4270 mlx5e_setup_pauseframes(struct mlx5e_priv *priv) 4271 { 4272 int error; 4273 4274 /* enable pauseframes by default */ 4275 priv->params.tx_pauseframe_control = 1; 4276 priv->params.rx_pauseframe_control = 1; 4277 4278 /* disable ports flow control, PFC, by default */ 4279 priv->params.tx_priority_flow_control = 0; 4280 priv->params.rx_priority_flow_control = 0; 4281 4282 /* register pauseframe SYSCTLs */ 4283 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4284 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN, 4285 &priv->params.tx_pauseframe_control, 0, 4286 "Set to enable TX pause frames. Clear to disable."); 4287 4288 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4289 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN, 4290 &priv->params.rx_pauseframe_control, 0, 4291 "Set to enable RX pause frames. Clear to disable."); 4292 4293 /* register priority flow control, PFC, SYSCTLs */ 4294 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4295 OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN | 4296 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU", 4297 "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable."); 4298 4299 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4300 OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN | 4301 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU", 4302 "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable."); 4303 4304 PRIV_LOCK(priv); 4305 4306 /* range check */ 4307 priv->params.tx_pauseframe_control = 4308 priv->params.tx_pauseframe_control ? 1 : 0; 4309 priv->params.rx_pauseframe_control = 4310 priv->params.rx_pauseframe_control ? 1 : 0; 4311 4312 /* update firmware */ 4313 error = mlx5e_set_port_pause_and_pfc(priv); 4314 if (error == -EINVAL) { 4315 mlx5_en_err(priv->ifp, 4316 "Global pauseframes must be disabled before enabling PFC.\n"); 4317 priv->params.rx_priority_flow_control = 0; 4318 priv->params.tx_priority_flow_control = 0; 4319 4320 /* update firmware */ 4321 (void) mlx5e_set_port_pause_and_pfc(priv); 4322 } 4323 PRIV_UNLOCK(priv); 4324 } 4325 4326 static int 4327 mlx5e_ul_snd_tag_alloc(if_t ifp, 4328 union if_snd_tag_alloc_params *params, 4329 struct m_snd_tag **ppmt) 4330 { 4331 struct mlx5e_priv *priv; 4332 struct mlx5e_channel *pch; 4333 4334 priv = if_getsoftc(ifp); 4335 4336 if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) { 4337 return (EOPNOTSUPP); 4338 } else { 4339 /* keep this code synced with mlx5e_select_queue() */ 4340 u32 ch = priv->params.num_channels; 4341 #ifdef RSS 4342 u32 temp; 4343 4344 if (rss_hash2bucket(params->hdr.flowid, 4345 params->hdr.flowtype, &temp) == 0) 4346 ch = temp % ch; 4347 else 4348 #endif 4349 ch = (params->hdr.flowid % 128) % ch; 4350 4351 /* 4352 * NOTE: The channels array is only freed at detach 4353 * and it safe to return a pointer to the send tag 4354 * inside the channels structure as long as we 4355 * reference the priv. 4356 */ 4357 pch = priv->channel + ch; 4358 4359 /* check if send queue is not running */ 4360 if (unlikely(pch->sq[0].running == 0)) 4361 return (ENXIO); 4362 m_snd_tag_ref(&pch->tag); 4363 *ppmt = &pch->tag; 4364 return (0); 4365 } 4366 } 4367 4368 static int 4369 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params) 4370 { 4371 struct mlx5e_channel *pch = 4372 container_of(pmt, struct mlx5e_channel, tag); 4373 4374 params->unlimited.max_rate = -1ULL; 4375 params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]); 4376 return (0); 4377 } 4378 4379 static void 4380 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt) 4381 { 4382 struct mlx5e_channel *pch = 4383 container_of(pmt, struct mlx5e_channel, tag); 4384 4385 complete(&pch->completion); 4386 } 4387 4388 static int 4389 mlx5e_snd_tag_alloc(if_t ifp, 4390 union if_snd_tag_alloc_params *params, 4391 struct m_snd_tag **ppmt) 4392 { 4393 4394 switch (params->hdr.type) { 4395 #ifdef RATELIMIT 4396 case IF_SND_TAG_TYPE_RATE_LIMIT: 4397 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt)); 4398 #ifdef KERN_TLS 4399 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT: 4400 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt)); 4401 #endif 4402 #endif 4403 case IF_SND_TAG_TYPE_UNLIMITED: 4404 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt)); 4405 #ifdef KERN_TLS 4406 case IF_SND_TAG_TYPE_TLS: 4407 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt)); 4408 case IF_SND_TAG_TYPE_TLS_RX: 4409 return (mlx5e_tls_rx_snd_tag_alloc(ifp, params, ppmt)); 4410 #endif 4411 default: 4412 return (EOPNOTSUPP); 4413 } 4414 } 4415 4416 #ifdef RATELIMIT 4417 #define NUM_HDWR_RATES_MLX 13 4418 static const uint64_t adapter_rates_mlx[NUM_HDWR_RATES_MLX] = { 4419 135375, /* 1,083,000 */ 4420 180500, /* 1,444,000 */ 4421 270750, /* 2,166,000 */ 4422 361000, /* 2,888,000 */ 4423 541500, /* 4,332,000 */ 4424 721875, /* 5,775,000 */ 4425 1082875, /* 8,663,000 */ 4426 1443875, /* 11,551,000 */ 4427 2165750, /* 17,326,000 */ 4428 2887750, /* 23,102,000 */ 4429 4331625, /* 34,653,000 */ 4430 5775500, /* 46,204,000 */ 4431 8663125 /* 69,305,000 */ 4432 }; 4433 4434 static void 4435 mlx5e_ratelimit_query(if_t ifp __unused, struct if_ratelimit_query_results *q) 4436 { 4437 /* 4438 * This function needs updating by the driver maintainer! 4439 * For the MLX card there are currently (ConectX-4?) 13 4440 * pre-set rates and others i.e. ConnectX-5, 6, 7?? 4441 * 4442 * This will change based on later adapters 4443 * and this code should be updated to look at ifp 4444 * and figure out the specific adapter type 4445 * settings i.e. how many rates as well 4446 * as if they are fixed (as is shown here) or 4447 * if they are dynamic (example chelsio t4). Also if there 4448 * is a maximum number of flows that the adapter 4449 * can handle that too needs to be updated in 4450 * the max_flows field. 4451 */ 4452 q->rate_table = adapter_rates_mlx; 4453 q->flags = RT_IS_FIXED_TABLE; 4454 q->max_flows = 0; /* mlx has no limit */ 4455 q->number_of_rates = NUM_HDWR_RATES_MLX; 4456 q->min_segment_burst = 1; 4457 } 4458 #endif 4459 4460 static void 4461 mlx5e_ifm_add(struct mlx5e_priv *priv, int type) 4462 { 4463 ifmedia_add(&priv->media, type | IFM_ETHER, 0, NULL); 4464 ifmedia_add(&priv->media, type | IFM_ETHER | 4465 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 4466 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_RXPAUSE, 0, NULL); 4467 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_TXPAUSE, 0, NULL); 4468 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX, 0, NULL); 4469 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX | 4470 IFM_ETH_RXPAUSE, 0, NULL); 4471 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX | 4472 IFM_ETH_TXPAUSE, 0, NULL); 4473 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX | 4474 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 4475 } 4476 4477 static void * 4478 mlx5e_create_ifp(struct mlx5_core_dev *mdev) 4479 { 4480 if_t ifp; 4481 struct mlx5e_priv *priv; 4482 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4); 4483 struct sysctl_oid_list *child; 4484 int ncv = mdev->priv.eq_table.num_comp_vectors; 4485 char unit[16]; 4486 struct pfil_head_args pa; 4487 int err; 4488 u32 eth_proto_cap; 4489 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 4490 bool ext; 4491 struct media media_entry = {}; 4492 4493 if (mlx5e_check_required_hca_cap(mdev)) { 4494 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n"); 4495 return (NULL); 4496 } 4497 4498 /* 4499 * Try to allocate the priv and make room for worst-case 4500 * number of channel structures: 4501 */ 4502 priv = malloc_domainset(sizeof(*priv) + 4503 (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors), 4504 M_MLX5EN, mlx5_dev_domainset(mdev), M_WAITOK | M_ZERO); 4505 4506 ifp = priv->ifp = if_alloc_dev(IFT_ETHER, mdev->pdev->dev.bsddev); 4507 /* setup all static fields */ 4508 if (mlx5e_priv_static_init(priv, mdev, mdev->priv.eq_table.num_comp_vectors)) { 4509 mlx5_core_err(mdev, "mlx5e_priv_static_init() failed\n"); 4510 goto err_free_ifp; 4511 } 4512 4513 if_setsoftc(ifp, priv); 4514 if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev)); 4515 if_setmtu(ifp, ETHERMTU); 4516 if_setinitfn(ifp, mlx5e_open); 4517 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 4518 if_setioctlfn(ifp, mlx5e_ioctl); 4519 if_settransmitfn(ifp, mlx5e_xmit); 4520 if_setqflushfn(ifp, if_qflush); 4521 if_setgetcounterfn(ifp, mlx5e_get_counter); 4522 if_setsendqlen(ifp, ifqmaxlen); 4523 /* 4524 * Set driver features 4525 */ 4526 if_setcapabilities(ifp, IFCAP_NV); 4527 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6, 0); 4528 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING, 0); 4529 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER, 0); 4530 if_setcapabilitiesbit(ifp, IFCAP_LINKSTATE | IFCAP_JUMBO_MTU, 0); 4531 if_setcapabilitiesbit(ifp, IFCAP_LRO, 0); 4532 if_setcapabilitiesbit(ifp, IFCAP_TSO | IFCAP_VLAN_HWTSO, 0); 4533 if_setcapabilitiesbit(ifp, IFCAP_HWSTATS | IFCAP_HWRXTSTMP, 0); 4534 if_setcapabilitiesbit(ifp, IFCAP_MEXTPG, 0); 4535 if_setcapabilitiesbit(ifp, IFCAP_TXTLS4 | IFCAP_TXTLS6, 0); 4536 #ifdef RATELIMIT 4537 if_setcapabilitiesbit(ifp, IFCAP_TXRTLMT | IFCAP_TXTLS_RTLMT, 0); 4538 #endif 4539 if_setcapabilitiesbit(ifp, IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO, 0); 4540 if_setcapabilities2bit(ifp, IFCAP2_BIT(IFCAP2_RXTLS4) | 4541 IFCAP2_BIT(IFCAP2_RXTLS6), 0); 4542 4543 if (mlx5_ipsec_device_caps(mdev) & MLX5_IPSEC_CAP_PACKET_OFFLOAD) 4544 if_setcapabilities2bit(ifp, IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD), 4545 0); 4546 4547 if_setsndtagallocfn(ifp, mlx5e_snd_tag_alloc); 4548 #ifdef RATELIMIT 4549 if_setratelimitqueryfn(ifp, mlx5e_ratelimit_query); 4550 #endif 4551 /* set TSO limits so that we don't have to drop TX packets */ 4552 if_sethwtsomax(ifp, MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN)); 4553 if_sethwtsomaxsegcount(ifp, MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */); 4554 if_sethwtsomaxsegsize(ifp, MLX5E_MAX_TX_MBUF_SIZE); 4555 4556 if_setcapenable(ifp, if_getcapabilities(ifp)); 4557 if_setcapenable2(ifp, if_getcapabilities2(ifp)); 4558 if_sethwassist(ifp, 0); 4559 if (if_getcapenable(ifp) & IFCAP_TSO) 4560 if_sethwassistbits(ifp, CSUM_TSO, 0); 4561 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 4562 if_sethwassistbits(ifp, (CSUM_TCP | CSUM_UDP | CSUM_IP), 0); 4563 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 4564 if_sethwassistbits(ifp, (CSUM_UDP_IPV6 | CSUM_TCP_IPV6), 0); 4565 if (if_getcapabilities(ifp) & IFCAP_VXLAN_HWCSUM) 4566 if_sethwassistbits(ifp, CSUM_INNER_IP6_UDP | CSUM_INNER_IP6_TCP | 4567 CSUM_INNER_IP | CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP | 4568 CSUM_ENCAP_VXLAN, 0); 4569 if (if_getcapabilities(ifp) & IFCAP_VXLAN_HWTSO) 4570 if_sethwassistbits(ifp, CSUM_INNER_IP6_TSO | CSUM_INNER_IP_TSO, 0); 4571 4572 /* ifnet sysctl tree */ 4573 sysctl_ctx_init(&priv->sysctl_ctx); 4574 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev), 4575 OID_AUTO, if_getdname(ifp), CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 4576 "MLX5 ethernet - interface name"); 4577 if (priv->sysctl_ifnet == NULL) { 4578 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4579 goto err_free_sysctl; 4580 } 4581 snprintf(unit, sizeof(unit), "%d", if_getdunit(ifp)); 4582 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4583 OID_AUTO, unit, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 4584 "MLX5 ethernet - interface unit"); 4585 if (priv->sysctl_ifnet == NULL) { 4586 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4587 goto err_free_sysctl; 4588 } 4589 4590 /* HW sysctl tree */ 4591 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev)); 4592 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child, 4593 OID_AUTO, "hw", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 4594 "MLX5 ethernet dev hw"); 4595 if (priv->sysctl_hw == NULL) { 4596 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4597 goto err_free_sysctl; 4598 } 4599 4600 err = mlx5e_build_ifp_priv(mdev, priv, ncv); 4601 if (err) { 4602 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err); 4603 goto err_free_sysctl; 4604 } 4605 4606 /* reuse mlx5core's watchdog workqueue */ 4607 priv->wq = mdev->priv.health.wq_watchdog; 4608 4609 err = mlx5_core_alloc_pd(mdev, &priv->pdn, 0); 4610 if (err) { 4611 mlx5_en_err(ifp, "mlx5_core_alloc_pd failed, %d\n", err); 4612 goto err_free_wq; 4613 } 4614 err = mlx5_alloc_transport_domain(mdev, &priv->tdn, 0); 4615 if (err) { 4616 mlx5_en_err(ifp, 4617 "mlx5_alloc_transport_domain failed, %d\n", err); 4618 goto err_dealloc_pd; 4619 } 4620 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr); 4621 if (err) { 4622 mlx5_en_err(ifp, "mlx5e_create_mkey failed, %d\n", err); 4623 goto err_dealloc_transport_domain; 4624 } 4625 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr); 4626 4627 /* check if we should generate a random MAC address */ 4628 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 && 4629 is_zero_ether_addr(dev_addr)) { 4630 random_ether_addr(dev_addr); 4631 mlx5_en_err(ifp, "Assigned random MAC address\n"); 4632 } 4633 4634 err = mlx5e_rl_init(priv); 4635 if (err) { 4636 mlx5_en_err(ifp, "mlx5e_rl_init failed, %d\n", err); 4637 goto err_create_mkey; 4638 } 4639 4640 err = mlx5e_tls_init(priv); 4641 if (err) { 4642 if_printf(ifp, "%s: mlx5e_tls_init failed\n", __func__); 4643 goto err_rl_init; 4644 } 4645 4646 if ((if_getcapenable2(ifp) & IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD)) != 0) { 4647 err = mlx5e_ipsec_init(priv); 4648 if (err) { 4649 if_printf(ifp, "%s: mlx5e_tls_init failed\n", __func__); 4650 goto err_tls_init; 4651 } 4652 } 4653 4654 err = mlx5e_open_drop_rq(priv, &priv->drop_rq); 4655 if (err) { 4656 if_printf(ifp, "%s: mlx5e_open_drop_rq failed (%d)\n", __func__, err); 4657 goto err_ipsec_init; 4658 } 4659 4660 err = mlx5e_open_rqts(priv); 4661 if (err) { 4662 if_printf(ifp, "%s: mlx5e_open_rqts failed (%d)\n", __func__, err); 4663 goto err_open_drop_rq; 4664 } 4665 4666 err = mlx5e_open_tirs(priv); 4667 if (err) { 4668 mlx5_en_err(ifp, "mlx5e_open_tirs() failed, %d\n", err); 4669 goto err_open_rqts; 4670 } 4671 4672 err = mlx5e_open_flow_tables(priv); 4673 if (err) { 4674 if_printf(ifp, "%s: mlx5e_open_flow_tables failed (%d)\n", __func__, err); 4675 goto err_open_tirs; 4676 } 4677 4678 err = mlx5e_tls_rx_init(priv); 4679 if (err) { 4680 if_printf(ifp, "%s: mlx5e_tls_rx_init() failed, %d\n", __func__, err); 4681 goto err_open_flow_tables; 4682 } 4683 4684 /* set default MTU */ 4685 mlx5e_set_dev_port_mtu(ifp, if_getmtu(ifp)); 4686 4687 /* Set default media status */ 4688 priv->media_status_last = IFM_AVALID; 4689 priv->media_active_last = IFM_ETHER | IFM_AUTO | IFM_FDX; 4690 4691 /* setup default pauseframes configuration */ 4692 mlx5e_setup_pauseframes(priv); 4693 4694 /* Setup supported medias */ 4695 if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) { 4696 ext = MLX5_CAP_PCAM_FEATURE(mdev, 4697 ptys_extended_ethernet); 4698 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 4699 eth_proto_capability); 4700 } else { 4701 ext = false; 4702 eth_proto_cap = 0; 4703 mlx5_en_err(ifp, "Query port media capability failed, %d\n", err); 4704 } 4705 4706 ifmedia_init(&priv->media, IFM_IMASK, 4707 mlx5e_media_change, mlx5e_media_status); 4708 4709 if (ext) { 4710 for (unsigned i = 0; i != MLX5E_EXT_LINK_SPEEDS_NUMBER; i++) { 4711 /* check if hardware has the right capability */ 4712 if (MLX5E_PROT_MASK(i) & ~eth_proto_cap) 4713 continue; 4714 for (unsigned j = 0; j != MLX5E_CABLE_TYPE_NUMBER; j++) { 4715 media_entry = mlx5e_ext_mode_table[i][j]; 4716 if (media_entry.subtype == 0) 4717 continue; 4718 /* check if this subtype was already added */ 4719 for (unsigned k = 0; k != i; k++) { 4720 /* check if hardware has the right capability */ 4721 if (MLX5E_PROT_MASK(k) & ~eth_proto_cap) 4722 continue; 4723 for (unsigned m = 0; m != MLX5E_CABLE_TYPE_NUMBER; m++) { 4724 if (media_entry.subtype == mlx5e_ext_mode_table[k][m].subtype) 4725 goto skip_ext_media; 4726 } 4727 } 4728 mlx5e_ifm_add(priv, media_entry.subtype); 4729 skip_ext_media:; 4730 } 4731 } 4732 } else { 4733 for (unsigned i = 0; i != MLX5E_LINK_SPEEDS_NUMBER; i++) { 4734 media_entry = mlx5e_mode_table[i]; 4735 if (media_entry.subtype == 0) 4736 continue; 4737 if (MLX5E_PROT_MASK(i) & ~eth_proto_cap) 4738 continue; 4739 /* check if this subtype was already added */ 4740 for (unsigned k = 0; k != i; k++) { 4741 if (media_entry.subtype == mlx5e_mode_table[k].subtype) 4742 goto skip_media; 4743 } 4744 mlx5e_ifm_add(priv, media_entry.subtype); 4745 4746 /* NOTE: 10G ER and LR shares the same entry */ 4747 if (media_entry.subtype == IFM_10G_ER) 4748 mlx5e_ifm_add(priv, IFM_10G_LR); 4749 skip_media:; 4750 } 4751 } 4752 4753 mlx5e_ifm_add(priv, IFM_AUTO); 4754 4755 /* Set autoselect by default */ 4756 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX | 4757 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE); 4758 4759 DEBUGNET_SET(ifp, mlx5_en); 4760 4761 ether_ifattach(ifp, dev_addr); 4762 4763 /* Register for VLAN events */ 4764 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config, 4765 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST); 4766 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig, 4767 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST); 4768 4769 /* Register for VxLAN events */ 4770 priv->vxlan_start = EVENTHANDLER_REGISTER(vxlan_start, 4771 mlx5e_vxlan_start, priv, EVENTHANDLER_PRI_ANY); 4772 priv->vxlan_stop = EVENTHANDLER_REGISTER(vxlan_stop, 4773 mlx5e_vxlan_stop, priv, EVENTHANDLER_PRI_ANY); 4774 4775 /* Link is down by default */ 4776 if_link_state_change(ifp, LINK_STATE_DOWN); 4777 4778 mlx5e_enable_async_events(priv); 4779 4780 mlx5e_add_hw_stats(priv); 4781 4782 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4783 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM, 4784 priv->stats.vport.arg); 4785 4786 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4787 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM, 4788 priv->stats.pport.arg); 4789 4790 mlx5e_create_ethtool(priv); 4791 4792 mtx_lock(&priv->async_events_mtx); 4793 mlx5e_update_stats(priv); 4794 mtx_unlock(&priv->async_events_mtx); 4795 4796 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4797 OID_AUTO, "rx_clbr_done", CTLFLAG_RD, 4798 &priv->clbr_done, 0, 4799 "RX timestamps calibration state"); 4800 callout_init(&priv->tstmp_clbr, 1); 4801 /* Pull out the frequency of the clock in hz */ 4802 priv->cclk = (uint64_t)MLX5_CAP_GEN(mdev, device_frequency_khz) * 1000ULL; 4803 mlx5e_reset_calibration_callout(priv); 4804 4805 pa.pa_version = PFIL_VERSION; 4806 pa.pa_flags = PFIL_IN; 4807 pa.pa_type = PFIL_TYPE_ETHERNET; 4808 pa.pa_headname = if_name(ifp); 4809 priv->pfil = pfil_head_register(&pa); 4810 4811 PRIV_LOCK(priv); 4812 err = mlx5e_open_flow_rules(priv); 4813 if (err) { 4814 mlx5_en_err(ifp, 4815 "mlx5e_open_flow_rules() failed, %d (ignored)\n", err); 4816 } 4817 PRIV_UNLOCK(priv); 4818 4819 return (priv); 4820 4821 err_open_flow_tables: 4822 mlx5e_close_flow_tables(priv); 4823 4824 err_open_tirs: 4825 mlx5e_close_tirs(priv); 4826 4827 err_open_rqts: 4828 mlx5e_close_rqts(priv); 4829 4830 err_open_drop_rq: 4831 mlx5e_close_drop_rq(&priv->drop_rq); 4832 4833 err_ipsec_init: 4834 mlx5e_ipsec_cleanup(priv); 4835 4836 err_tls_init: 4837 mlx5e_tls_cleanup(priv); 4838 4839 err_rl_init: 4840 mlx5e_rl_cleanup(priv); 4841 4842 err_create_mkey: 4843 mlx5_core_destroy_mkey(priv->mdev, &priv->mr); 4844 4845 err_dealloc_transport_domain: 4846 mlx5_dealloc_transport_domain(mdev, priv->tdn, 0); 4847 4848 err_dealloc_pd: 4849 mlx5_core_dealloc_pd(mdev, priv->pdn, 0); 4850 4851 err_free_wq: 4852 flush_workqueue(priv->wq); 4853 4854 err_free_sysctl: 4855 sysctl_ctx_free(&priv->sysctl_ctx); 4856 if (priv->sysctl_debug) 4857 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx); 4858 mlx5e_priv_static_destroy(priv, mdev, mdev->priv.eq_table.num_comp_vectors); 4859 4860 err_free_ifp: 4861 if_free(ifp); 4862 free(priv, M_MLX5EN); 4863 return (NULL); 4864 } 4865 4866 static void 4867 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv) 4868 { 4869 struct mlx5e_priv *priv = vpriv; 4870 if_t ifp = priv->ifp; 4871 4872 /* don't allow more IOCTLs */ 4873 priv->gone = 1; 4874 4875 /* XXX wait a bit to allow IOCTL handlers to complete */ 4876 pause("W", hz); 4877 4878 #ifdef RATELIMIT 4879 /* 4880 * Tell the TCP ratelimit code to release the rate-sets attached 4881 * to our ifnet. 4882 */ 4883 tcp_rl_release_ifnet(ifp); 4884 /* 4885 * The kernel can still have reference(s) via the m_snd_tag's into 4886 * the ratelimit channels, and these must go away before 4887 * detaching: 4888 */ 4889 while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) { 4890 mlx5_en_err(priv->ifp, 4891 "Waiting for all ratelimit connections to terminate\n"); 4892 pause("W", hz); 4893 } 4894 #endif 4895 4896 #ifdef KERN_TLS 4897 /* wait for all TLS tags to get freed */ 4898 while (priv->tls.init != 0 && 4899 uma_zone_get_cur(priv->tls.zone) != 0) { 4900 mlx5_en_err(priv->ifp, 4901 "Waiting for all TLS connections to terminate\n"); 4902 pause("W", hz); 4903 } 4904 4905 /* wait for all TLS RX tags to get freed */ 4906 while (priv->tls_rx.init != 0 && 4907 uma_zone_get_cur(priv->tls_rx.zone) != 0) { 4908 mlx5_en_err(priv->ifp, 4909 "Waiting for all TLS RX connections to terminate\n"); 4910 pause("W", hz); 4911 } 4912 #endif 4913 /* wait for all unlimited send tags to complete */ 4914 mlx5e_priv_wait_for_completion(priv, mdev->priv.eq_table.num_comp_vectors); 4915 4916 /* stop watchdog timer */ 4917 callout_drain(&priv->watchdog); 4918 4919 callout_drain(&priv->tstmp_clbr); 4920 4921 if (priv->vlan_attach != NULL) 4922 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach); 4923 if (priv->vlan_detach != NULL) 4924 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach); 4925 if (priv->vxlan_start != NULL) 4926 EVENTHANDLER_DEREGISTER(vxlan_start, priv->vxlan_start); 4927 if (priv->vxlan_stop != NULL) 4928 EVENTHANDLER_DEREGISTER(vxlan_stop, priv->vxlan_stop); 4929 4930 /* make sure device gets closed */ 4931 PRIV_LOCK(priv); 4932 mlx5e_close_locked(ifp); 4933 mlx5e_close_flow_rules(priv); 4934 PRIV_UNLOCK(priv); 4935 4936 /* deregister pfil */ 4937 if (priv->pfil != NULL) { 4938 pfil_head_unregister(priv->pfil); 4939 priv->pfil = NULL; 4940 } 4941 4942 /* unregister device */ 4943 ifmedia_removeall(&priv->media); 4944 ether_ifdetach(ifp); 4945 4946 mlx5e_tls_rx_cleanup(priv); 4947 #ifdef IPSEC_OFFLOAD 4948 ipsec_accel_on_ifdown(priv->ifp); 4949 #endif 4950 mlx5e_close_flow_tables(priv); 4951 mlx5e_close_tirs(priv); 4952 mlx5e_close_rqts(priv); 4953 mlx5e_close_drop_rq(&priv->drop_rq); 4954 mlx5e_ipsec_cleanup(priv); 4955 mlx5e_tls_cleanup(priv); 4956 mlx5e_rl_cleanup(priv); 4957 4958 /* destroy all remaining sysctl nodes */ 4959 sysctl_ctx_free(&priv->stats.vport.ctx); 4960 sysctl_ctx_free(&priv->stats.pport.ctx); 4961 if (priv->sysctl_debug) 4962 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx); 4963 sysctl_ctx_free(&priv->sysctl_ctx); 4964 4965 mlx5_core_destroy_mkey(priv->mdev, &priv->mr); 4966 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn, 0); 4967 mlx5_core_dealloc_pd(priv->mdev, priv->pdn, 0); 4968 mlx5e_disable_async_events(priv); 4969 flush_workqueue(priv->wq); 4970 mlx5e_priv_static_destroy(priv, mdev, mdev->priv.eq_table.num_comp_vectors); 4971 if_free(ifp); 4972 free(priv, M_MLX5EN); 4973 } 4974 4975 #ifdef DEBUGNET 4976 static void 4977 mlx5_en_debugnet_init(if_t dev, int *nrxr, int *ncl, int *clsize) 4978 { 4979 struct mlx5e_priv *priv = if_getsoftc(dev); 4980 4981 PRIV_LOCK(priv); 4982 *nrxr = priv->params.num_channels; 4983 *ncl = DEBUGNET_MAX_IN_FLIGHT; 4984 *clsize = MLX5E_MAX_RX_BYTES; 4985 PRIV_UNLOCK(priv); 4986 } 4987 4988 static void 4989 mlx5_en_debugnet_event(if_t dev, enum debugnet_ev event) 4990 { 4991 } 4992 4993 static int 4994 mlx5_en_debugnet_transmit(if_t dev, struct mbuf *m) 4995 { 4996 struct mlx5e_priv *priv = if_getsoftc(dev); 4997 struct mlx5e_sq *sq; 4998 int err; 4999 5000 if ((if_getdrvflags(dev) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 5001 IFF_DRV_RUNNING || (priv->media_status_last & IFM_ACTIVE) == 0) 5002 return (ENOENT); 5003 5004 sq = &priv->channel[0].sq[0]; 5005 5006 if (sq->running == 0) { 5007 m_freem(m); 5008 return (ENOENT); 5009 } 5010 5011 if (mlx5e_sq_xmit(sq, &m) != 0) { 5012 m_freem(m); 5013 err = ENOBUFS; 5014 } else { 5015 err = 0; 5016 } 5017 5018 mlx5e_tx_notify_hw(sq, true); 5019 5020 return (err); 5021 } 5022 5023 static int 5024 mlx5_en_debugnet_poll(if_t dev, int count) 5025 { 5026 struct mlx5e_priv *priv = if_getsoftc(dev); 5027 5028 if ((if_getdrvflags(dev) & IFF_DRV_RUNNING) == 0 || 5029 (priv->media_status_last & IFM_ACTIVE) == 0) 5030 return (ENOENT); 5031 5032 mlx5_poll_interrupts(priv->mdev); 5033 5034 return (0); 5035 } 5036 #endif /* DEBUGNET */ 5037 5038 static void * 5039 mlx5e_get_ifp(void *vpriv) 5040 { 5041 struct mlx5e_priv *priv = vpriv; 5042 5043 return (priv->ifp); 5044 } 5045 5046 static struct mlx5_interface mlx5e_interface = { 5047 .add = mlx5e_create_ifp, 5048 .remove = mlx5e_destroy_ifp, 5049 .event = mlx5e_async_event, 5050 .protocol = MLX5_INTERFACE_PROTOCOL_ETH, 5051 .get_dev = mlx5e_get_ifp, 5052 }; 5053 5054 void 5055 mlx5e_init(void) 5056 { 5057 mlx5_register_interface(&mlx5e_interface); 5058 } 5059 5060 void 5061 mlx5e_cleanup(void) 5062 { 5063 mlx5_unregister_interface(&mlx5e_interface); 5064 } 5065 5066 module_init_order(mlx5e_init, SI_ORDER_SIXTH); 5067 module_exit_order(mlx5e_cleanup, SI_ORDER_SIXTH); 5068 5069 MODULE_DEPEND(mlx5en, ipsec, 1, 1, 1); 5070 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1); 5071 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1); 5072 MODULE_VERSION(mlx5en, 1); 5073