1 /*- 2 * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include "en.h" 29 30 #include <sys/sockio.h> 31 #include <machine/atomic.h> 32 33 #ifndef ETH_DRIVER_VERSION 34 #define ETH_DRIVER_VERSION "3.5.0" 35 #endif 36 #define DRIVER_RELDATE "November 2018" 37 38 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver " 39 ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n"; 40 41 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs); 42 43 struct mlx5e_channel_param { 44 struct mlx5e_rq_param rq; 45 struct mlx5e_sq_param sq; 46 struct mlx5e_cq_param rx_cq; 47 struct mlx5e_cq_param tx_cq; 48 }; 49 50 struct media { 51 u32 subtype; 52 u64 baudrate; 53 }; 54 55 static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = { 56 57 [MLX5E_1000BASE_CX_SGMII][MLX5E_SGMII] = { 58 .subtype = IFM_1000_CX_SGMII, 59 .baudrate = IF_Mbps(1000ULL), 60 }, 61 [MLX5E_1000BASE_KX][MLX5E_KX] = { 62 .subtype = IFM_1000_KX, 63 .baudrate = IF_Mbps(1000ULL), 64 }, 65 [MLX5E_10GBASE_CX4][MLX5E_CX4] = { 66 .subtype = IFM_10G_CX4, 67 .baudrate = IF_Gbps(10ULL), 68 }, 69 [MLX5E_10GBASE_KX4][MLX5E_KX4] = { 70 .subtype = IFM_10G_KX4, 71 .baudrate = IF_Gbps(10ULL), 72 }, 73 [MLX5E_10GBASE_KR][MLX5E_KR] = { 74 .subtype = IFM_10G_KR, 75 .baudrate = IF_Gbps(10ULL), 76 }, 77 [MLX5E_20GBASE_KR2][MLX5E_KR2] = { 78 .subtype = IFM_20G_KR2, 79 .baudrate = IF_Gbps(20ULL), 80 }, 81 [MLX5E_40GBASE_CR4][MLX5E_CR4] = { 82 .subtype = IFM_40G_CR4, 83 .baudrate = IF_Gbps(40ULL), 84 }, 85 [MLX5E_40GBASE_KR4][MLX5E_KR4] = { 86 .subtype = IFM_40G_KR4, 87 .baudrate = IF_Gbps(40ULL), 88 }, 89 [MLX5E_56GBASE_R4][MLX5E_R] = { 90 .subtype = IFM_56G_R4, 91 .baudrate = IF_Gbps(56ULL), 92 }, 93 [MLX5E_10GBASE_CR][MLX5E_CR1] = { 94 .subtype = IFM_10G_CR1, 95 .baudrate = IF_Gbps(10ULL), 96 }, 97 [MLX5E_10GBASE_SR][MLX5E_SR] = { 98 .subtype = IFM_10G_SR, 99 .baudrate = IF_Gbps(10ULL), 100 }, 101 [MLX5E_10GBASE_ER_LR][MLX5E_ER] = { 102 .subtype = IFM_10G_ER, 103 .baudrate = IF_Gbps(10ULL), 104 }, 105 [MLX5E_10GBASE_ER_LR][MLX5E_LR] = { 106 .subtype = IFM_10G_LR, 107 .baudrate = IF_Gbps(10ULL), 108 }, 109 [MLX5E_40GBASE_SR4][MLX5E_SR4] = { 110 .subtype = IFM_40G_SR4, 111 .baudrate = IF_Gbps(40ULL), 112 }, 113 [MLX5E_40GBASE_LR4_ER4][MLX5E_LR4] = { 114 .subtype = IFM_40G_LR4, 115 .baudrate = IF_Gbps(40ULL), 116 }, 117 [MLX5E_40GBASE_LR4_ER4][MLX5E_ER4] = { 118 .subtype = IFM_40G_ER4, 119 .baudrate = IF_Gbps(40ULL), 120 }, 121 [MLX5E_100GBASE_CR4][MLX5E_CR4] = { 122 .subtype = IFM_100G_CR4, 123 .baudrate = IF_Gbps(100ULL), 124 }, 125 [MLX5E_100GBASE_SR4][MLX5E_SR4] = { 126 .subtype = IFM_100G_SR4, 127 .baudrate = IF_Gbps(100ULL), 128 }, 129 [MLX5E_100GBASE_KR4][MLX5E_KR4] = { 130 .subtype = IFM_100G_KR4, 131 .baudrate = IF_Gbps(100ULL), 132 }, 133 [MLX5E_100GBASE_LR4][MLX5E_LR4] = { 134 .subtype = IFM_100G_LR4, 135 .baudrate = IF_Gbps(100ULL), 136 }, 137 [MLX5E_100BASE_TX][MLX5E_TX] = { 138 .subtype = IFM_100_TX, 139 .baudrate = IF_Mbps(100ULL), 140 }, 141 [MLX5E_1000BASE_T][MLX5E_T] = { 142 .subtype = IFM_1000_T, 143 .baudrate = IF_Mbps(1000ULL), 144 }, 145 [MLX5E_10GBASE_T][MLX5E_T] = { 146 .subtype = IFM_10G_T, 147 .baudrate = IF_Gbps(10ULL), 148 }, 149 [MLX5E_25GBASE_CR][MLX5E_CR] = { 150 .subtype = IFM_25G_CR, 151 .baudrate = IF_Gbps(25ULL), 152 }, 153 [MLX5E_25GBASE_KR][MLX5E_KR] = { 154 .subtype = IFM_25G_KR, 155 .baudrate = IF_Gbps(25ULL), 156 }, 157 [MLX5E_25GBASE_SR][MLX5E_SR] = { 158 .subtype = IFM_25G_SR, 159 .baudrate = IF_Gbps(25ULL), 160 }, 161 [MLX5E_50GBASE_CR2][MLX5E_CR2] = { 162 .subtype = IFM_50G_CR2, 163 .baudrate = IF_Gbps(50ULL), 164 }, 165 [MLX5E_50GBASE_KR2][MLX5E_KR2] = { 166 .subtype = IFM_50G_KR2, 167 .baudrate = IF_Gbps(50ULL), 168 }, 169 }; 170 171 static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = { 172 [MLX5E_SGMII_100M][MLX5E_SGMII] = { 173 .subtype = IFM_100_SGMII, 174 .baudrate = IF_Mbps(100), 175 }, 176 [MLX5E_1000BASE_X_SGMII][MLX5E_KX] = { 177 .subtype = IFM_1000_KX, 178 .baudrate = IF_Mbps(1000), 179 }, 180 [MLX5E_1000BASE_X_SGMII][MLX5E_CX_SGMII] = { 181 .subtype = IFM_1000_CX_SGMII, 182 .baudrate = IF_Mbps(1000), 183 }, 184 [MLX5E_1000BASE_X_SGMII][MLX5E_CX] = { 185 .subtype = IFM_1000_CX, 186 .baudrate = IF_Mbps(1000), 187 }, 188 [MLX5E_1000BASE_X_SGMII][MLX5E_LX] = { 189 .subtype = IFM_1000_LX, 190 .baudrate = IF_Mbps(1000), 191 }, 192 [MLX5E_1000BASE_X_SGMII][MLX5E_SX] = { 193 .subtype = IFM_1000_SX, 194 .baudrate = IF_Mbps(1000), 195 }, 196 [MLX5E_1000BASE_X_SGMII][MLX5E_T] = { 197 .subtype = IFM_1000_T, 198 .baudrate = IF_Mbps(1000), 199 }, 200 [MLX5E_5GBASE_R][MLX5E_T] = { 201 .subtype = IFM_5000_T, 202 .baudrate = IF_Mbps(5000), 203 }, 204 [MLX5E_5GBASE_R][MLX5E_KR] = { 205 .subtype = IFM_5000_KR, 206 .baudrate = IF_Mbps(5000), 207 }, 208 [MLX5E_5GBASE_R][MLX5E_KR1] = { 209 .subtype = IFM_5000_KR1, 210 .baudrate = IF_Mbps(5000), 211 }, 212 [MLX5E_5GBASE_R][MLX5E_KR_S] = { 213 .subtype = IFM_5000_KR_S, 214 .baudrate = IF_Mbps(5000), 215 }, 216 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_ER] = { 217 .subtype = IFM_10G_ER, 218 .baudrate = IF_Gbps(10ULL), 219 }, 220 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_KR] = { 221 .subtype = IFM_10G_KR, 222 .baudrate = IF_Gbps(10ULL), 223 }, 224 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_LR] = { 225 .subtype = IFM_10G_LR, 226 .baudrate = IF_Gbps(10ULL), 227 }, 228 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_SR] = { 229 .subtype = IFM_10G_SR, 230 .baudrate = IF_Gbps(10ULL), 231 }, 232 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_T] = { 233 .subtype = IFM_10G_T, 234 .baudrate = IF_Gbps(10ULL), 235 }, 236 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_AOC] = { 237 .subtype = IFM_10G_AOC, 238 .baudrate = IF_Gbps(10ULL), 239 }, 240 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CR1] = { 241 .subtype = IFM_10G_CR1, 242 .baudrate = IF_Gbps(10ULL), 243 }, 244 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CR4] = { 245 .subtype = IFM_40G_CR4, 246 .baudrate = IF_Gbps(40ULL), 247 }, 248 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_KR4] = { 249 .subtype = IFM_40G_KR4, 250 .baudrate = IF_Gbps(40ULL), 251 }, 252 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_LR4] = { 253 .subtype = IFM_40G_LR4, 254 .baudrate = IF_Gbps(40ULL), 255 }, 256 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_SR4] = { 257 .subtype = IFM_40G_SR4, 258 .baudrate = IF_Gbps(40ULL), 259 }, 260 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_ER4] = { 261 .subtype = IFM_40G_ER4, 262 .baudrate = IF_Gbps(40ULL), 263 }, 264 265 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR] = { 266 .subtype = IFM_25G_CR, 267 .baudrate = IF_Gbps(25ULL), 268 }, 269 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR] = { 270 .subtype = IFM_25G_KR, 271 .baudrate = IF_Gbps(25ULL), 272 }, 273 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_SR] = { 274 .subtype = IFM_25G_SR, 275 .baudrate = IF_Gbps(25ULL), 276 }, 277 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_ACC] = { 278 .subtype = IFM_25G_ACC, 279 .baudrate = IF_Gbps(25ULL), 280 }, 281 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_AOC] = { 282 .subtype = IFM_25G_AOC, 283 .baudrate = IF_Gbps(25ULL), 284 }, 285 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR1] = { 286 .subtype = IFM_25G_CR1, 287 .baudrate = IF_Gbps(25ULL), 288 }, 289 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR_S] = { 290 .subtype = IFM_25G_CR_S, 291 .baudrate = IF_Gbps(25ULL), 292 }, 293 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR1] = { 294 .subtype = IFM_5000_KR1, 295 .baudrate = IF_Gbps(25ULL), 296 }, 297 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR_S] = { 298 .subtype = IFM_25G_KR_S, 299 .baudrate = IF_Gbps(25ULL), 300 }, 301 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_LR] = { 302 .subtype = IFM_25G_LR, 303 .baudrate = IF_Gbps(25ULL), 304 }, 305 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_T] = { 306 .subtype = IFM_25G_T, 307 .baudrate = IF_Gbps(25ULL), 308 }, 309 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CR2] = { 310 .subtype = IFM_50G_CR2, 311 .baudrate = IF_Gbps(50ULL), 312 }, 313 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_KR2] = { 314 .subtype = IFM_50G_KR2, 315 .baudrate = IF_Gbps(50ULL), 316 }, 317 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_SR2] = { 318 .subtype = IFM_50G_SR2, 319 .baudrate = IF_Gbps(50ULL), 320 }, 321 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_LR2] = { 322 .subtype = IFM_50G_LR2, 323 .baudrate = IF_Gbps(50ULL), 324 }, 325 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_LR] = { 326 .subtype = IFM_50G_LR, 327 .baudrate = IF_Gbps(50ULL), 328 }, 329 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_SR] = { 330 .subtype = IFM_50G_SR, 331 .baudrate = IF_Gbps(50ULL), 332 }, 333 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CP] = { 334 .subtype = IFM_50G_CP, 335 .baudrate = IF_Gbps(50ULL), 336 }, 337 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_FR] = { 338 .subtype = IFM_50G_FR, 339 .baudrate = IF_Gbps(50ULL), 340 }, 341 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_KR_PAM4] = { 342 .subtype = IFM_50G_KR_PAM4, 343 .baudrate = IF_Gbps(50ULL), 344 }, 345 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CR4] = { 346 .subtype = IFM_100G_CR4, 347 .baudrate = IF_Gbps(100ULL), 348 }, 349 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_KR4] = { 350 .subtype = IFM_100G_KR4, 351 .baudrate = IF_Gbps(100ULL), 352 }, 353 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_LR4] = { 354 .subtype = IFM_100G_LR4, 355 .baudrate = IF_Gbps(100ULL), 356 }, 357 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_SR4] = { 358 .subtype = IFM_100G_SR4, 359 .baudrate = IF_Gbps(100ULL), 360 }, 361 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_SR2] = { 362 .subtype = IFM_100G_SR2, 363 .baudrate = IF_Gbps(100ULL), 364 }, 365 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CP2] = { 366 .subtype = IFM_100G_CP2, 367 .baudrate = IF_Gbps(100ULL), 368 }, 369 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_KR2_PAM4] = { 370 .subtype = IFM_100G_KR2_PAM4, 371 .baudrate = IF_Gbps(100ULL), 372 }, 373 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_DR4] = { 374 .subtype = IFM_200G_DR4, 375 .baudrate = IF_Gbps(200ULL), 376 }, 377 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_LR4] = { 378 .subtype = IFM_200G_LR4, 379 .baudrate = IF_Gbps(200ULL), 380 }, 381 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_SR4] = { 382 .subtype = IFM_200G_SR4, 383 .baudrate = IF_Gbps(200ULL), 384 }, 385 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_FR4] = { 386 .subtype = IFM_200G_FR4, 387 .baudrate = IF_Gbps(200ULL), 388 }, 389 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CR4_PAM4] = { 390 .subtype = IFM_200G_CR4_PAM4, 391 .baudrate = IF_Gbps(200ULL), 392 }, 393 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_KR4_PAM4] = { 394 .subtype = IFM_200G_KR4_PAM4, 395 .baudrate = IF_Gbps(200ULL), 396 }, 397 }; 398 399 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet"); 400 401 static void 402 mlx5e_update_carrier(struct mlx5e_priv *priv) 403 { 404 struct mlx5_core_dev *mdev = priv->mdev; 405 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 406 u32 eth_proto_oper; 407 int error; 408 u8 port_state; 409 u8 is_er_type; 410 u8 i, j; 411 bool ext; 412 struct media media_entry = {}; 413 414 port_state = mlx5_query_vport_state(mdev, 415 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0); 416 417 if (port_state == VPORT_STATE_UP) { 418 priv->media_status_last |= IFM_ACTIVE; 419 } else { 420 priv->media_status_last &= ~IFM_ACTIVE; 421 priv->media_active_last = IFM_ETHER; 422 if_link_state_change(priv->ifp, LINK_STATE_DOWN); 423 return; 424 } 425 426 error = mlx5_query_port_ptys(mdev, out, sizeof(out), 427 MLX5_PTYS_EN, 1); 428 if (error) { 429 priv->media_active_last = IFM_ETHER; 430 priv->ifp->if_baudrate = 1; 431 if_printf(priv->ifp, "%s: query port ptys failed: " 432 "0x%x\n", __func__, error); 433 return; 434 } 435 436 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet); 437 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 438 eth_proto_oper); 439 440 i = ilog2(eth_proto_oper); 441 442 for (j = 0; j != MLX5E_LINK_MODES_NUMBER; j++) { 443 media_entry = ext ? mlx5e_ext_mode_table[i][j] : 444 mlx5e_mode_table[i][j]; 445 if (media_entry.baudrate != 0) 446 break; 447 } 448 449 if (media_entry.subtype == 0) { 450 if_printf(priv->ifp, "%s: Could not find operational " 451 "media subtype\n", __func__); 452 return; 453 } 454 455 switch (media_entry.subtype) { 456 case IFM_10G_ER: 457 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type); 458 if (error != 0) { 459 if_printf(priv->ifp, "%s: query port pddr failed: %d\n", 460 __func__, error); 461 } 462 if (error != 0 || is_er_type == 0) 463 media_entry.subtype = IFM_10G_LR; 464 break; 465 case IFM_40G_LR4: 466 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type); 467 if (error != 0) { 468 if_printf(priv->ifp, "%s: query port pddr failed: %d\n", 469 __func__, error); 470 } 471 if (error == 0 && is_er_type != 0) 472 media_entry.subtype = IFM_40G_ER4; 473 break; 474 } 475 priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX; 476 priv->ifp->if_baudrate = media_entry.baudrate; 477 478 if_link_state_change(priv->ifp, LINK_STATE_UP); 479 } 480 481 static void 482 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr) 483 { 484 struct mlx5e_priv *priv = dev->if_softc; 485 486 ifmr->ifm_status = priv->media_status_last; 487 ifmr->ifm_active = priv->media_active_last | 488 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) | 489 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0); 490 491 } 492 493 static u32 494 mlx5e_find_link_mode(u32 subtype, bool ext) 495 { 496 u32 i; 497 u32 j; 498 u32 link_mode = 0; 499 u32 speeds_num = 0; 500 struct media media_entry = {}; 501 502 switch (subtype) { 503 case IFM_10G_LR: 504 subtype = IFM_10G_ER; 505 break; 506 case IFM_40G_ER4: 507 subtype = IFM_40G_LR4; 508 break; 509 } 510 511 speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER : 512 MLX5E_LINK_SPEEDS_NUMBER; 513 514 for (i = 0; i != speeds_num; i++) { 515 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) { 516 media_entry = ext ? mlx5e_ext_mode_table[i][j] : 517 mlx5e_mode_table[i][j]; 518 if (media_entry.baudrate == 0) 519 continue; 520 if (media_entry.subtype == subtype) { 521 link_mode |= MLX5E_PROT_MASK(i); 522 } 523 } 524 } 525 526 return (link_mode); 527 } 528 529 static int 530 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv) 531 { 532 return (mlx5_set_port_pause_and_pfc(priv->mdev, 1, 533 priv->params.rx_pauseframe_control, 534 priv->params.tx_pauseframe_control, 535 priv->params.rx_priority_flow_control, 536 priv->params.tx_priority_flow_control)); 537 } 538 539 static int 540 mlx5e_set_port_pfc(struct mlx5e_priv *priv) 541 { 542 int error; 543 544 if (priv->gone != 0) { 545 error = -ENXIO; 546 } else if (priv->params.rx_pauseframe_control || 547 priv->params.tx_pauseframe_control) { 548 if_printf(priv->ifp, 549 "Global pauseframes must be disabled before " 550 "enabling PFC.\n"); 551 error = -EINVAL; 552 } else { 553 error = mlx5e_set_port_pause_and_pfc(priv); 554 } 555 return (error); 556 } 557 558 static int 559 mlx5e_media_change(struct ifnet *dev) 560 { 561 struct mlx5e_priv *priv = dev->if_softc; 562 struct mlx5_core_dev *mdev = priv->mdev; 563 u32 eth_proto_cap; 564 u32 link_mode; 565 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 566 int was_opened; 567 int locked; 568 int error; 569 bool ext; 570 571 locked = PRIV_LOCKED(priv); 572 if (!locked) 573 PRIV_LOCK(priv); 574 575 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) { 576 error = EINVAL; 577 goto done; 578 } 579 580 error = mlx5_query_port_ptys(mdev, out, sizeof(out), 581 MLX5_PTYS_EN, 1); 582 if (error != 0) { 583 if_printf(dev, "Query port media capability failed\n"); 584 goto done; 585 } 586 587 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet); 588 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext); 589 590 /* query supported capabilities */ 591 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 592 eth_proto_capability); 593 594 /* check for autoselect */ 595 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) { 596 link_mode = eth_proto_cap; 597 if (link_mode == 0) { 598 if_printf(dev, "Port media capability is zero\n"); 599 error = EINVAL; 600 goto done; 601 } 602 } else { 603 link_mode = link_mode & eth_proto_cap; 604 if (link_mode == 0) { 605 if_printf(dev, "Not supported link mode requested\n"); 606 error = EINVAL; 607 goto done; 608 } 609 } 610 if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) { 611 /* check if PFC is enabled */ 612 if (priv->params.rx_priority_flow_control || 613 priv->params.tx_priority_flow_control) { 614 if_printf(dev, "PFC must be disabled before enabling global pauseframes.\n"); 615 error = EINVAL; 616 goto done; 617 } 618 } 619 /* update pauseframe control bits */ 620 priv->params.rx_pauseframe_control = 621 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0; 622 priv->params.tx_pauseframe_control = 623 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0; 624 625 /* check if device is opened */ 626 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 627 628 /* reconfigure the hardware */ 629 mlx5_set_port_status(mdev, MLX5_PORT_DOWN); 630 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext); 631 error = -mlx5e_set_port_pause_and_pfc(priv); 632 if (was_opened) 633 mlx5_set_port_status(mdev, MLX5_PORT_UP); 634 635 done: 636 if (!locked) 637 PRIV_UNLOCK(priv); 638 return (error); 639 } 640 641 static void 642 mlx5e_update_carrier_work(struct work_struct *work) 643 { 644 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 645 update_carrier_work); 646 647 PRIV_LOCK(priv); 648 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) 649 mlx5e_update_carrier(priv); 650 PRIV_UNLOCK(priv); 651 } 652 653 /* 654 * This function reads the physical port counters from the firmware 655 * using a pre-defined layout defined by various MLX5E_PPORT_XXX() 656 * macros. The output is converted from big-endian 64-bit values into 657 * host endian ones and stored in the "priv->stats.pport" structure. 658 */ 659 static void 660 mlx5e_update_pport_counters(struct mlx5e_priv *priv) 661 { 662 struct mlx5_core_dev *mdev = priv->mdev; 663 struct mlx5e_pport_stats *s = &priv->stats.pport; 664 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug; 665 u32 *in; 666 u32 *out; 667 const u64 *ptr; 668 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 669 unsigned x; 670 unsigned y; 671 unsigned z; 672 673 /* allocate firmware request structures */ 674 in = mlx5_vzalloc(sz); 675 out = mlx5_vzalloc(sz); 676 if (in == NULL || out == NULL) 677 goto free_out; 678 679 /* 680 * Get pointer to the 64-bit counter set which is located at a 681 * fixed offset in the output firmware request structure: 682 */ 683 ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set); 684 685 MLX5_SET(ppcnt_reg, in, local_port, 1); 686 687 /* read IEEE802_3 counter group using predefined counter layout */ 688 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP); 689 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 690 for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM; 691 x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++) 692 s->arg[y] = be64toh(ptr[x]); 693 694 /* read RFC2819 counter group using predefined counter layout */ 695 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP); 696 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 697 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++) 698 s->arg[y] = be64toh(ptr[x]); 699 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM + 700 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++) 701 s_debug->arg[y] = be64toh(ptr[x]); 702 703 /* read RFC2863 counter group using predefined counter layout */ 704 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP); 705 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 706 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++) 707 s_debug->arg[y] = be64toh(ptr[x]); 708 709 /* read physical layer stats counter group using predefined counter layout */ 710 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP); 711 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 712 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++) 713 s_debug->arg[y] = be64toh(ptr[x]); 714 715 /* read Extended Ethernet counter group using predefined counter layout */ 716 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP); 717 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 718 for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++) 719 s_debug->arg[y] = be64toh(ptr[x]); 720 721 /* read per-priority counters */ 722 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP); 723 724 /* iterate all the priorities */ 725 for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) { 726 MLX5_SET(ppcnt_reg, in, prio_tc, z); 727 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 728 729 /* read per priority stats counter group using predefined counter layout */ 730 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM / 731 MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++) 732 s->arg[y] = be64toh(ptr[x]); 733 } 734 735 free_out: 736 /* free firmware request structures */ 737 kvfree(in); 738 kvfree(out); 739 } 740 741 static void 742 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv) 743 { 744 u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {}; 745 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {}; 746 747 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard)) 748 return; 749 750 MLX5_SET(query_vnic_env_in, in, opcode, 751 MLX5_CMD_OP_QUERY_VNIC_ENV); 752 MLX5_SET(query_vnic_env_in, in, op_mod, 0); 753 MLX5_SET(query_vnic_env_in, in, other_vport, 0); 754 755 if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0) 756 return; 757 758 priv->stats.vport.rx_steer_missed_packets = 759 MLX5_GET64(query_vnic_env_out, out, 760 vport_env.nic_receive_steering_discard); 761 } 762 763 /* 764 * This function is called regularly to collect all statistics 765 * counters from the firmware. The values can be viewed through the 766 * sysctl interface. Execution is serialized using the priv's global 767 * configuration lock. 768 */ 769 static void 770 mlx5e_update_stats_locked(struct mlx5e_priv *priv) 771 { 772 struct mlx5_core_dev *mdev = priv->mdev; 773 struct mlx5e_vport_stats *s = &priv->stats.vport; 774 struct mlx5e_sq_stats *sq_stats; 775 struct buf_ring *sq_br; 776 #if (__FreeBSD_version < 1100000) 777 struct ifnet *ifp = priv->ifp; 778 #endif 779 780 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)]; 781 u32 *out; 782 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out); 783 u64 tso_packets = 0; 784 u64 tso_bytes = 0; 785 u64 tx_queue_dropped = 0; 786 u64 tx_defragged = 0; 787 u64 tx_offload_none = 0; 788 u64 lro_packets = 0; 789 u64 lro_bytes = 0; 790 u64 sw_lro_queued = 0; 791 u64 sw_lro_flushed = 0; 792 u64 rx_csum_none = 0; 793 u64 rx_wqe_err = 0; 794 u64 rx_packets = 0; 795 u64 rx_bytes = 0; 796 u32 rx_out_of_buffer = 0; 797 int i; 798 int j; 799 800 out = mlx5_vzalloc(outlen); 801 if (out == NULL) 802 goto free_out; 803 804 /* Collect firts the SW counters and then HW for consistency */ 805 for (i = 0; i < priv->params.num_channels; i++) { 806 struct mlx5e_channel *pch = priv->channel + i; 807 struct mlx5e_rq *rq = &pch->rq; 808 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats; 809 810 /* collect stats from LRO */ 811 rq_stats->sw_lro_queued = rq->lro.lro_queued; 812 rq_stats->sw_lro_flushed = rq->lro.lro_flushed; 813 sw_lro_queued += rq_stats->sw_lro_queued; 814 sw_lro_flushed += rq_stats->sw_lro_flushed; 815 lro_packets += rq_stats->lro_packets; 816 lro_bytes += rq_stats->lro_bytes; 817 rx_csum_none += rq_stats->csum_none; 818 rx_wqe_err += rq_stats->wqe_err; 819 rx_packets += rq_stats->packets; 820 rx_bytes += rq_stats->bytes; 821 822 for (j = 0; j < priv->num_tc; j++) { 823 sq_stats = &pch->sq[j].stats; 824 sq_br = pch->sq[j].br; 825 826 tso_packets += sq_stats->tso_packets; 827 tso_bytes += sq_stats->tso_bytes; 828 tx_queue_dropped += sq_stats->dropped; 829 if (sq_br != NULL) 830 tx_queue_dropped += sq_br->br_drops; 831 tx_defragged += sq_stats->defragged; 832 tx_offload_none += sq_stats->csum_offload_none; 833 } 834 } 835 836 /* update counters */ 837 s->tso_packets = tso_packets; 838 s->tso_bytes = tso_bytes; 839 s->tx_queue_dropped = tx_queue_dropped; 840 s->tx_defragged = tx_defragged; 841 s->lro_packets = lro_packets; 842 s->lro_bytes = lro_bytes; 843 s->sw_lro_queued = sw_lro_queued; 844 s->sw_lro_flushed = sw_lro_flushed; 845 s->rx_csum_none = rx_csum_none; 846 s->rx_wqe_err = rx_wqe_err; 847 s->rx_packets = rx_packets; 848 s->rx_bytes = rx_bytes; 849 850 mlx5e_grp_vnic_env_update_stats(priv); 851 852 /* HW counters */ 853 memset(in, 0, sizeof(in)); 854 855 MLX5_SET(query_vport_counter_in, in, opcode, 856 MLX5_CMD_OP_QUERY_VPORT_COUNTER); 857 MLX5_SET(query_vport_counter_in, in, op_mod, 0); 858 MLX5_SET(query_vport_counter_in, in, other_vport, 0); 859 860 memset(out, 0, outlen); 861 862 /* get number of out-of-buffer drops first */ 863 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 && 864 mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id, 865 &rx_out_of_buffer) == 0) { 866 s->rx_out_of_buffer = rx_out_of_buffer; 867 } 868 869 /* get port statistics */ 870 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) { 871 #define MLX5_GET_CTR(out, x) \ 872 MLX5_GET64(query_vport_counter_out, out, x) 873 874 s->rx_error_packets = 875 MLX5_GET_CTR(out, received_errors.packets); 876 s->rx_error_bytes = 877 MLX5_GET_CTR(out, received_errors.octets); 878 s->tx_error_packets = 879 MLX5_GET_CTR(out, transmit_errors.packets); 880 s->tx_error_bytes = 881 MLX5_GET_CTR(out, transmit_errors.octets); 882 883 s->rx_unicast_packets = 884 MLX5_GET_CTR(out, received_eth_unicast.packets); 885 s->rx_unicast_bytes = 886 MLX5_GET_CTR(out, received_eth_unicast.octets); 887 s->tx_unicast_packets = 888 MLX5_GET_CTR(out, transmitted_eth_unicast.packets); 889 s->tx_unicast_bytes = 890 MLX5_GET_CTR(out, transmitted_eth_unicast.octets); 891 892 s->rx_multicast_packets = 893 MLX5_GET_CTR(out, received_eth_multicast.packets); 894 s->rx_multicast_bytes = 895 MLX5_GET_CTR(out, received_eth_multicast.octets); 896 s->tx_multicast_packets = 897 MLX5_GET_CTR(out, transmitted_eth_multicast.packets); 898 s->tx_multicast_bytes = 899 MLX5_GET_CTR(out, transmitted_eth_multicast.octets); 900 901 s->rx_broadcast_packets = 902 MLX5_GET_CTR(out, received_eth_broadcast.packets); 903 s->rx_broadcast_bytes = 904 MLX5_GET_CTR(out, received_eth_broadcast.octets); 905 s->tx_broadcast_packets = 906 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets); 907 s->tx_broadcast_bytes = 908 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets); 909 910 s->tx_packets = s->tx_unicast_packets + 911 s->tx_multicast_packets + s->tx_broadcast_packets; 912 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes + 913 s->tx_broadcast_bytes; 914 915 /* Update calculated offload counters */ 916 s->tx_csum_offload = s->tx_packets - tx_offload_none; 917 s->rx_csum_good = s->rx_packets - s->rx_csum_none; 918 } 919 920 /* Get physical port counters */ 921 mlx5e_update_pport_counters(priv); 922 923 s->tx_jumbo_packets = 924 priv->stats.port_stats_debug.tx_stat_p1519to2047octets + 925 priv->stats.port_stats_debug.tx_stat_p2048to4095octets + 926 priv->stats.port_stats_debug.tx_stat_p4096to8191octets + 927 priv->stats.port_stats_debug.tx_stat_p8192to10239octets; 928 929 #if (__FreeBSD_version < 1100000) 930 /* no get_counters interface in fbsd 10 */ 931 ifp->if_ipackets = s->rx_packets; 932 ifp->if_ierrors = priv->stats.pport.in_range_len_errors + 933 priv->stats.pport.out_of_range_len + 934 priv->stats.pport.too_long_errors + 935 priv->stats.pport.check_seq_err + 936 priv->stats.pport.alignment_err; 937 ifp->if_iqdrops = s->rx_out_of_buffer; 938 ifp->if_opackets = s->tx_packets; 939 ifp->if_oerrors = priv->stats.port_stats_debug.out_discards; 940 ifp->if_snd.ifq_drops = s->tx_queue_dropped; 941 ifp->if_ibytes = s->rx_bytes; 942 ifp->if_obytes = s->tx_bytes; 943 ifp->if_collisions = 944 priv->stats.pport.collisions; 945 #endif 946 947 free_out: 948 kvfree(out); 949 950 /* Update diagnostics, if any */ 951 if (priv->params_ethtool.diag_pci_enable || 952 priv->params_ethtool.diag_general_enable) { 953 int error = mlx5_core_get_diagnostics_full(mdev, 954 priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL, 955 priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL); 956 if (error != 0) 957 if_printf(priv->ifp, "Failed reading diagnostics: %d\n", error); 958 } 959 } 960 961 static void 962 mlx5e_update_stats_work(struct work_struct *work) 963 { 964 struct mlx5e_priv *priv; 965 966 priv = container_of(work, struct mlx5e_priv, update_stats_work); 967 PRIV_LOCK(priv); 968 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 969 mlx5e_update_stats_locked(priv); 970 PRIV_UNLOCK(priv); 971 } 972 973 static void 974 mlx5e_update_stats(void *arg) 975 { 976 struct mlx5e_priv *priv = arg; 977 978 queue_work(priv->wq, &priv->update_stats_work); 979 980 callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv); 981 } 982 983 static void 984 mlx5e_async_event_sub(struct mlx5e_priv *priv, 985 enum mlx5_dev_event event) 986 { 987 switch (event) { 988 case MLX5_DEV_EVENT_PORT_UP: 989 case MLX5_DEV_EVENT_PORT_DOWN: 990 queue_work(priv->wq, &priv->update_carrier_work); 991 break; 992 993 default: 994 break; 995 } 996 } 997 998 static void 999 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv, 1000 enum mlx5_dev_event event, unsigned long param) 1001 { 1002 struct mlx5e_priv *priv = vpriv; 1003 1004 mtx_lock(&priv->async_events_mtx); 1005 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state)) 1006 mlx5e_async_event_sub(priv, event); 1007 mtx_unlock(&priv->async_events_mtx); 1008 } 1009 1010 static void 1011 mlx5e_enable_async_events(struct mlx5e_priv *priv) 1012 { 1013 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 1014 } 1015 1016 static void 1017 mlx5e_disable_async_events(struct mlx5e_priv *priv) 1018 { 1019 mtx_lock(&priv->async_events_mtx); 1020 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 1021 mtx_unlock(&priv->async_events_mtx); 1022 } 1023 1024 static void mlx5e_calibration_callout(void *arg); 1025 static int mlx5e_calibration_duration = 20; 1026 static int mlx5e_fast_calibration = 1; 1027 static int mlx5e_normal_calibration = 30; 1028 1029 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW, 0, 1030 "MLX5 timestamp calibration parameteres"); 1031 1032 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN, 1033 &mlx5e_calibration_duration, 0, 1034 "Duration of initial calibration"); 1035 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN, 1036 &mlx5e_fast_calibration, 0, 1037 "Recalibration interval during initial calibration"); 1038 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN, 1039 &mlx5e_normal_calibration, 0, 1040 "Recalibration interval during normal operations"); 1041 1042 /* 1043 * Ignites the calibration process. 1044 */ 1045 static void 1046 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv) 1047 { 1048 1049 if (priv->clbr_done == 0) 1050 mlx5e_calibration_callout(priv); 1051 else 1052 callout_reset_curcpu(&priv->tstmp_clbr, (priv->clbr_done < 1053 mlx5e_calibration_duration ? mlx5e_fast_calibration : 1054 mlx5e_normal_calibration) * hz, mlx5e_calibration_callout, 1055 priv); 1056 } 1057 1058 static uint64_t 1059 mlx5e_timespec2usec(const struct timespec *ts) 1060 { 1061 1062 return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec); 1063 } 1064 1065 static uint64_t 1066 mlx5e_hw_clock(struct mlx5e_priv *priv) 1067 { 1068 struct mlx5_init_seg *iseg; 1069 uint32_t hw_h, hw_h1, hw_l; 1070 1071 iseg = priv->mdev->iseg; 1072 do { 1073 hw_h = ioread32be(&iseg->internal_timer_h); 1074 hw_l = ioread32be(&iseg->internal_timer_l); 1075 hw_h1 = ioread32be(&iseg->internal_timer_h); 1076 } while (hw_h1 != hw_h); 1077 return (((uint64_t)hw_h << 32) | hw_l); 1078 } 1079 1080 /* 1081 * The calibration callout, it runs either in the context of the 1082 * thread which enables calibration, or in callout. It takes the 1083 * snapshot of system and adapter clocks, then advances the pointers to 1084 * the calibration point to allow rx path to read the consistent data 1085 * lockless. 1086 */ 1087 static void 1088 mlx5e_calibration_callout(void *arg) 1089 { 1090 struct mlx5e_priv *priv; 1091 struct mlx5e_clbr_point *next, *curr; 1092 struct timespec ts; 1093 int clbr_curr_next; 1094 1095 priv = arg; 1096 curr = &priv->clbr_points[priv->clbr_curr]; 1097 clbr_curr_next = priv->clbr_curr + 1; 1098 if (clbr_curr_next >= nitems(priv->clbr_points)) 1099 clbr_curr_next = 0; 1100 next = &priv->clbr_points[clbr_curr_next]; 1101 1102 next->base_prev = curr->base_curr; 1103 next->clbr_hw_prev = curr->clbr_hw_curr; 1104 1105 next->clbr_hw_curr = mlx5e_hw_clock(priv); 1106 if (((next->clbr_hw_curr - curr->clbr_hw_curr) >> MLX5E_TSTMP_PREC) == 1107 0) { 1108 if (priv->clbr_done != 0) { 1109 if_printf(priv->ifp, "HW failed tstmp frozen %#jx %#jx," 1110 "disabling\n", 1111 next->clbr_hw_curr, curr->clbr_hw_prev); 1112 priv->clbr_done = 0; 1113 } 1114 atomic_store_rel_int(&curr->clbr_gen, 0); 1115 return; 1116 } 1117 1118 nanouptime(&ts); 1119 next->base_curr = mlx5e_timespec2usec(&ts); 1120 1121 curr->clbr_gen = 0; 1122 atomic_thread_fence_rel(); 1123 priv->clbr_curr = clbr_curr_next; 1124 atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen)); 1125 1126 if (priv->clbr_done < mlx5e_calibration_duration) 1127 priv->clbr_done++; 1128 mlx5e_reset_calibration_callout(priv); 1129 } 1130 1131 static const char *mlx5e_rq_stats_desc[] = { 1132 MLX5E_RQ_STATS(MLX5E_STATS_DESC) 1133 }; 1134 1135 static int 1136 mlx5e_create_rq(struct mlx5e_channel *c, 1137 struct mlx5e_rq_param *param, 1138 struct mlx5e_rq *rq) 1139 { 1140 struct mlx5e_priv *priv = c->priv; 1141 struct mlx5_core_dev *mdev = priv->mdev; 1142 char buffer[16]; 1143 void *rqc = param->rqc; 1144 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); 1145 int wq_sz; 1146 int err; 1147 int i; 1148 u32 nsegs, wqe_sz; 1149 1150 err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs); 1151 if (err != 0) 1152 goto done; 1153 1154 /* Create DMA descriptor TAG */ 1155 if ((err = -bus_dma_tag_create( 1156 bus_get_dma_tag(mdev->pdev->dev.bsddev), 1157 1, /* any alignment */ 1158 0, /* no boundary */ 1159 BUS_SPACE_MAXADDR, /* lowaddr */ 1160 BUS_SPACE_MAXADDR, /* highaddr */ 1161 NULL, NULL, /* filter, filterarg */ 1162 nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */ 1163 nsegs, /* nsegments */ 1164 nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */ 1165 0, /* flags */ 1166 NULL, NULL, /* lockfunc, lockfuncarg */ 1167 &rq->dma_tag))) 1168 goto done; 1169 1170 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, 1171 &rq->wq_ctrl); 1172 if (err) 1173 goto err_free_dma_tag; 1174 1175 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR]; 1176 1177 err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs); 1178 if (err != 0) 1179 goto err_rq_wq_destroy; 1180 1181 wq_sz = mlx5_wq_ll_get_size(&rq->wq); 1182 1183 err = -tcp_lro_init_args(&rq->lro, c->tag.m_snd_tag.ifp, TCP_LRO_ENTRIES, wq_sz); 1184 if (err) 1185 goto err_rq_wq_destroy; 1186 1187 rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO); 1188 for (i = 0; i != wq_sz; i++) { 1189 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i); 1190 #if (MLX5E_MAX_RX_SEGS == 1) 1191 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN; 1192 #else 1193 int j; 1194 #endif 1195 1196 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map); 1197 if (err != 0) { 1198 while (i--) 1199 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 1200 goto err_rq_mbuf_free; 1201 } 1202 1203 /* set value for constant fields */ 1204 #if (MLX5E_MAX_RX_SEGS == 1) 1205 wqe->data[0].lkey = c->mkey_be; 1206 wqe->data[0].byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING); 1207 #else 1208 for (j = 0; j < rq->nsegs; j++) 1209 wqe->data[j].lkey = c->mkey_be; 1210 #endif 1211 } 1212 1213 INIT_WORK(&rq->dim.work, mlx5e_dim_work); 1214 if (priv->params.rx_cq_moderation_mode < 2) { 1215 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 1216 } else { 1217 void *cqc = container_of(param, 1218 struct mlx5e_channel_param, rq)->rx_cq.cqc; 1219 1220 switch (MLX5_GET(cqc, cqc, cq_period_mode)) { 1221 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE: 1222 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; 1223 break; 1224 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE: 1225 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE; 1226 break; 1227 default: 1228 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 1229 break; 1230 } 1231 } 1232 1233 rq->ifp = c->tag.m_snd_tag.ifp; 1234 rq->channel = c; 1235 rq->ix = c->ix; 1236 1237 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix); 1238 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 1239 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM, 1240 rq->stats.arg); 1241 return (0); 1242 1243 err_rq_mbuf_free: 1244 free(rq->mbuf, M_MLX5EN); 1245 tcp_lro_free(&rq->lro); 1246 err_rq_wq_destroy: 1247 mlx5_wq_destroy(&rq->wq_ctrl); 1248 err_free_dma_tag: 1249 bus_dma_tag_destroy(rq->dma_tag); 1250 done: 1251 return (err); 1252 } 1253 1254 static void 1255 mlx5e_destroy_rq(struct mlx5e_rq *rq) 1256 { 1257 int wq_sz; 1258 int i; 1259 1260 /* destroy all sysctl nodes */ 1261 sysctl_ctx_free(&rq->stats.ctx); 1262 1263 /* free leftover LRO packets, if any */ 1264 tcp_lro_free(&rq->lro); 1265 1266 wq_sz = mlx5_wq_ll_get_size(&rq->wq); 1267 for (i = 0; i != wq_sz; i++) { 1268 if (rq->mbuf[i].mbuf != NULL) { 1269 bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map); 1270 m_freem(rq->mbuf[i].mbuf); 1271 } 1272 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 1273 } 1274 free(rq->mbuf, M_MLX5EN); 1275 mlx5_wq_destroy(&rq->wq_ctrl); 1276 } 1277 1278 static int 1279 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param) 1280 { 1281 struct mlx5e_channel *c = rq->channel; 1282 struct mlx5e_priv *priv = c->priv; 1283 struct mlx5_core_dev *mdev = priv->mdev; 1284 1285 void *in; 1286 void *rqc; 1287 void *wq; 1288 int inlen; 1289 int err; 1290 1291 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 1292 sizeof(u64) * rq->wq_ctrl.buf.npages; 1293 in = mlx5_vzalloc(inlen); 1294 if (in == NULL) 1295 return (-ENOMEM); 1296 1297 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1298 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1299 1300 memcpy(rqc, param->rqc, sizeof(param->rqc)); 1301 1302 MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn); 1303 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1304 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1305 if (priv->counter_set_id >= 0) 1306 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id); 1307 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - 1308 PAGE_SHIFT); 1309 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); 1310 1311 mlx5_fill_page_array(&rq->wq_ctrl.buf, 1312 (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 1313 1314 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); 1315 1316 kvfree(in); 1317 1318 return (err); 1319 } 1320 1321 static int 1322 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state) 1323 { 1324 struct mlx5e_channel *c = rq->channel; 1325 struct mlx5e_priv *priv = c->priv; 1326 struct mlx5_core_dev *mdev = priv->mdev; 1327 1328 void *in; 1329 void *rqc; 1330 int inlen; 1331 int err; 1332 1333 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 1334 in = mlx5_vzalloc(inlen); 1335 if (in == NULL) 1336 return (-ENOMEM); 1337 1338 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1339 1340 MLX5_SET(modify_rq_in, in, rqn, rq->rqn); 1341 MLX5_SET(modify_rq_in, in, rq_state, curr_state); 1342 MLX5_SET(rqc, rqc, state, next_state); 1343 1344 err = mlx5_core_modify_rq(mdev, in, inlen); 1345 1346 kvfree(in); 1347 1348 return (err); 1349 } 1350 1351 static void 1352 mlx5e_disable_rq(struct mlx5e_rq *rq) 1353 { 1354 struct mlx5e_channel *c = rq->channel; 1355 struct mlx5e_priv *priv = c->priv; 1356 struct mlx5_core_dev *mdev = priv->mdev; 1357 1358 mlx5_core_destroy_rq(mdev, rq->rqn); 1359 } 1360 1361 static int 1362 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq) 1363 { 1364 struct mlx5e_channel *c = rq->channel; 1365 struct mlx5e_priv *priv = c->priv; 1366 struct mlx5_wq_ll *wq = &rq->wq; 1367 int i; 1368 1369 for (i = 0; i < 1000; i++) { 1370 if (wq->cur_sz >= priv->params.min_rx_wqes) 1371 return (0); 1372 1373 msleep(4); 1374 } 1375 return (-ETIMEDOUT); 1376 } 1377 1378 static int 1379 mlx5e_open_rq(struct mlx5e_channel *c, 1380 struct mlx5e_rq_param *param, 1381 struct mlx5e_rq *rq) 1382 { 1383 int err; 1384 1385 err = mlx5e_create_rq(c, param, rq); 1386 if (err) 1387 return (err); 1388 1389 err = mlx5e_enable_rq(rq, param); 1390 if (err) 1391 goto err_destroy_rq; 1392 1393 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 1394 if (err) 1395 goto err_disable_rq; 1396 1397 c->rq.enabled = 1; 1398 1399 return (0); 1400 1401 err_disable_rq: 1402 mlx5e_disable_rq(rq); 1403 err_destroy_rq: 1404 mlx5e_destroy_rq(rq); 1405 1406 return (err); 1407 } 1408 1409 static void 1410 mlx5e_close_rq(struct mlx5e_rq *rq) 1411 { 1412 mtx_lock(&rq->mtx); 1413 rq->enabled = 0; 1414 callout_stop(&rq->watchdog); 1415 mtx_unlock(&rq->mtx); 1416 1417 callout_drain(&rq->watchdog); 1418 1419 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 1420 } 1421 1422 static void 1423 mlx5e_close_rq_wait(struct mlx5e_rq *rq) 1424 { 1425 1426 mlx5e_disable_rq(rq); 1427 mlx5e_close_cq(&rq->cq); 1428 cancel_work_sync(&rq->dim.work); 1429 mlx5e_destroy_rq(rq); 1430 } 1431 1432 void 1433 mlx5e_free_sq_db(struct mlx5e_sq *sq) 1434 { 1435 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1436 int x; 1437 1438 for (x = 0; x != wq_sz; x++) { 1439 if (sq->mbuf[x].mbuf != NULL) { 1440 bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map); 1441 m_freem(sq->mbuf[x].mbuf); 1442 } 1443 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 1444 } 1445 free(sq->mbuf, M_MLX5EN); 1446 } 1447 1448 int 1449 mlx5e_alloc_sq_db(struct mlx5e_sq *sq) 1450 { 1451 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1452 int err; 1453 int x; 1454 1455 sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO); 1456 1457 /* Create DMA descriptor MAPs */ 1458 for (x = 0; x != wq_sz; x++) { 1459 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map); 1460 if (err != 0) { 1461 while (x--) 1462 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 1463 free(sq->mbuf, M_MLX5EN); 1464 return (err); 1465 } 1466 } 1467 return (0); 1468 } 1469 1470 static const char *mlx5e_sq_stats_desc[] = { 1471 MLX5E_SQ_STATS(MLX5E_STATS_DESC) 1472 }; 1473 1474 void 1475 mlx5e_update_sq_inline(struct mlx5e_sq *sq) 1476 { 1477 sq->max_inline = sq->priv->params.tx_max_inline; 1478 sq->min_inline_mode = sq->priv->params.tx_min_inline_mode; 1479 1480 /* 1481 * Check if trust state is DSCP or if inline mode is NONE which 1482 * indicates CX-5 or newer hardware. 1483 */ 1484 if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP || 1485 sq->min_inline_mode == MLX5_INLINE_MODE_NONE) { 1486 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert)) 1487 sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN; 1488 else 1489 sq->min_insert_caps = MLX5E_INSERT_NON_VLAN; 1490 } else { 1491 sq->min_insert_caps = 0; 1492 } 1493 } 1494 1495 static void 1496 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c) 1497 { 1498 int i; 1499 1500 for (i = 0; i != c->num_tc; i++) { 1501 mtx_lock(&c->sq[i].lock); 1502 mlx5e_update_sq_inline(&c->sq[i]); 1503 mtx_unlock(&c->sq[i].lock); 1504 } 1505 } 1506 1507 void 1508 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv) 1509 { 1510 int i; 1511 1512 /* check if channels are closed */ 1513 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 1514 return; 1515 1516 for (i = 0; i < priv->params.num_channels; i++) 1517 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]); 1518 } 1519 1520 static int 1521 mlx5e_create_sq(struct mlx5e_channel *c, 1522 int tc, 1523 struct mlx5e_sq_param *param, 1524 struct mlx5e_sq *sq) 1525 { 1526 struct mlx5e_priv *priv = c->priv; 1527 struct mlx5_core_dev *mdev = priv->mdev; 1528 char buffer[16]; 1529 void *sqc = param->sqc; 1530 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq); 1531 int err; 1532 1533 /* Create DMA descriptor TAG */ 1534 if ((err = -bus_dma_tag_create( 1535 bus_get_dma_tag(mdev->pdev->dev.bsddev), 1536 1, /* any alignment */ 1537 0, /* no boundary */ 1538 BUS_SPACE_MAXADDR, /* lowaddr */ 1539 BUS_SPACE_MAXADDR, /* highaddr */ 1540 NULL, NULL, /* filter, filterarg */ 1541 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */ 1542 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */ 1543 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */ 1544 0, /* flags */ 1545 NULL, NULL, /* lockfunc, lockfuncarg */ 1546 &sq->dma_tag))) 1547 goto done; 1548 1549 err = mlx5_alloc_map_uar(mdev, &sq->uar); 1550 if (err) 1551 goto err_free_dma_tag; 1552 1553 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, 1554 &sq->wq_ctrl); 1555 if (err) 1556 goto err_unmap_free_uar; 1557 1558 sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; 1559 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2; 1560 1561 err = mlx5e_alloc_sq_db(sq); 1562 if (err) 1563 goto err_sq_wq_destroy; 1564 1565 sq->mkey_be = c->mkey_be; 1566 sq->ifp = priv->ifp; 1567 sq->priv = priv; 1568 sq->tc = tc; 1569 1570 mlx5e_update_sq_inline(sq); 1571 1572 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc); 1573 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 1574 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM, 1575 sq->stats.arg); 1576 1577 return (0); 1578 1579 err_sq_wq_destroy: 1580 mlx5_wq_destroy(&sq->wq_ctrl); 1581 1582 err_unmap_free_uar: 1583 mlx5_unmap_free_uar(mdev, &sq->uar); 1584 1585 err_free_dma_tag: 1586 bus_dma_tag_destroy(sq->dma_tag); 1587 done: 1588 return (err); 1589 } 1590 1591 static void 1592 mlx5e_destroy_sq(struct mlx5e_sq *sq) 1593 { 1594 /* destroy all sysctl nodes */ 1595 sysctl_ctx_free(&sq->stats.ctx); 1596 1597 mlx5e_free_sq_db(sq); 1598 mlx5_wq_destroy(&sq->wq_ctrl); 1599 mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar); 1600 } 1601 1602 int 1603 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param, 1604 int tis_num) 1605 { 1606 void *in; 1607 void *sqc; 1608 void *wq; 1609 int inlen; 1610 int err; 1611 1612 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1613 sizeof(u64) * sq->wq_ctrl.buf.npages; 1614 in = mlx5_vzalloc(inlen); 1615 if (in == NULL) 1616 return (-ENOMEM); 1617 1618 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1619 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1620 1621 memcpy(sqc, param->sqc, sizeof(param->sqc)); 1622 1623 MLX5_SET(sqc, sqc, tis_num_0, tis_num); 1624 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn); 1625 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1626 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1627 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1628 1629 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1630 MLX5_SET(wq, wq, uar_page, sq->uar.index); 1631 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift - 1632 PAGE_SHIFT); 1633 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma); 1634 1635 mlx5_fill_page_array(&sq->wq_ctrl.buf, 1636 (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 1637 1638 err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn); 1639 1640 kvfree(in); 1641 1642 return (err); 1643 } 1644 1645 int 1646 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state) 1647 { 1648 void *in; 1649 void *sqc; 1650 int inlen; 1651 int err; 1652 1653 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 1654 in = mlx5_vzalloc(inlen); 1655 if (in == NULL) 1656 return (-ENOMEM); 1657 1658 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1659 1660 MLX5_SET(modify_sq_in, in, sqn, sq->sqn); 1661 MLX5_SET(modify_sq_in, in, sq_state, curr_state); 1662 MLX5_SET(sqc, sqc, state, next_state); 1663 1664 err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen); 1665 1666 kvfree(in); 1667 1668 return (err); 1669 } 1670 1671 void 1672 mlx5e_disable_sq(struct mlx5e_sq *sq) 1673 { 1674 1675 mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn); 1676 } 1677 1678 static int 1679 mlx5e_open_sq(struct mlx5e_channel *c, 1680 int tc, 1681 struct mlx5e_sq_param *param, 1682 struct mlx5e_sq *sq) 1683 { 1684 int err; 1685 1686 err = mlx5e_create_sq(c, tc, param, sq); 1687 if (err) 1688 return (err); 1689 1690 err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]); 1691 if (err) 1692 goto err_destroy_sq; 1693 1694 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY); 1695 if (err) 1696 goto err_disable_sq; 1697 1698 WRITE_ONCE(sq->running, 1); 1699 1700 return (0); 1701 1702 err_disable_sq: 1703 mlx5e_disable_sq(sq); 1704 err_destroy_sq: 1705 mlx5e_destroy_sq(sq); 1706 1707 return (err); 1708 } 1709 1710 static void 1711 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep) 1712 { 1713 /* fill up remainder with NOPs */ 1714 while (sq->cev_counter != 0) { 1715 while (!mlx5e_sq_has_room_for(sq, 1)) { 1716 if (can_sleep != 0) { 1717 mtx_unlock(&sq->lock); 1718 msleep(4); 1719 mtx_lock(&sq->lock); 1720 } else { 1721 goto done; 1722 } 1723 } 1724 /* send a single NOP */ 1725 mlx5e_send_nop(sq, 1); 1726 atomic_thread_fence_rel(); 1727 } 1728 done: 1729 /* Check if we need to write the doorbell */ 1730 if (likely(sq->doorbell.d64 != 0)) { 1731 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0); 1732 sq->doorbell.d64 = 0; 1733 } 1734 } 1735 1736 void 1737 mlx5e_sq_cev_timeout(void *arg) 1738 { 1739 struct mlx5e_sq *sq = arg; 1740 1741 mtx_assert(&sq->lock, MA_OWNED); 1742 1743 /* check next state */ 1744 switch (sq->cev_next_state) { 1745 case MLX5E_CEV_STATE_SEND_NOPS: 1746 /* fill TX ring with NOPs, if any */ 1747 mlx5e_sq_send_nops_locked(sq, 0); 1748 1749 /* check if completed */ 1750 if (sq->cev_counter == 0) { 1751 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL; 1752 return; 1753 } 1754 break; 1755 default: 1756 /* send NOPs on next timeout */ 1757 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS; 1758 break; 1759 } 1760 1761 /* restart timer */ 1762 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq); 1763 } 1764 1765 void 1766 mlx5e_drain_sq(struct mlx5e_sq *sq) 1767 { 1768 int error; 1769 struct mlx5_core_dev *mdev= sq->priv->mdev; 1770 1771 /* 1772 * Check if already stopped. 1773 * 1774 * NOTE: Serialization of this function is managed by the 1775 * caller ensuring the priv's state lock is locked or in case 1776 * of rate limit support, a single thread manages drain and 1777 * resume of SQs. The "running" variable can therefore safely 1778 * be read without any locks. 1779 */ 1780 if (READ_ONCE(sq->running) == 0) 1781 return; 1782 1783 /* don't put more packets into the SQ */ 1784 WRITE_ONCE(sq->running, 0); 1785 1786 /* serialize access to DMA rings */ 1787 mtx_lock(&sq->lock); 1788 1789 /* teardown event factor timer, if any */ 1790 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS; 1791 callout_stop(&sq->cev_callout); 1792 1793 /* send dummy NOPs in order to flush the transmit ring */ 1794 mlx5e_sq_send_nops_locked(sq, 1); 1795 mtx_unlock(&sq->lock); 1796 1797 /* make sure it is safe to free the callout */ 1798 callout_drain(&sq->cev_callout); 1799 1800 /* wait till SQ is empty or link is down */ 1801 mtx_lock(&sq->lock); 1802 while (sq->cc != sq->pc && 1803 (sq->priv->media_status_last & IFM_ACTIVE) != 0 && 1804 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1805 mtx_unlock(&sq->lock); 1806 msleep(1); 1807 sq->cq.mcq.comp(&sq->cq.mcq); 1808 mtx_lock(&sq->lock); 1809 } 1810 mtx_unlock(&sq->lock); 1811 1812 /* error out remaining requests */ 1813 error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR); 1814 if (error != 0) { 1815 if_printf(sq->ifp, 1816 "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error); 1817 } 1818 1819 /* wait till SQ is empty */ 1820 mtx_lock(&sq->lock); 1821 while (sq->cc != sq->pc && 1822 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1823 mtx_unlock(&sq->lock); 1824 msleep(1); 1825 sq->cq.mcq.comp(&sq->cq.mcq); 1826 mtx_lock(&sq->lock); 1827 } 1828 mtx_unlock(&sq->lock); 1829 } 1830 1831 static void 1832 mlx5e_close_sq_wait(struct mlx5e_sq *sq) 1833 { 1834 1835 mlx5e_drain_sq(sq); 1836 mlx5e_disable_sq(sq); 1837 mlx5e_destroy_sq(sq); 1838 } 1839 1840 static int 1841 mlx5e_create_cq(struct mlx5e_priv *priv, 1842 struct mlx5e_cq_param *param, 1843 struct mlx5e_cq *cq, 1844 mlx5e_cq_comp_t *comp, 1845 int eq_ix) 1846 { 1847 struct mlx5_core_dev *mdev = priv->mdev; 1848 struct mlx5_core_cq *mcq = &cq->mcq; 1849 int eqn_not_used; 1850 int irqn; 1851 int err; 1852 u32 i; 1853 1854 param->wq.buf_numa_node = 0; 1855 param->wq.db_numa_node = 0; 1856 1857 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, 1858 &cq->wq_ctrl); 1859 if (err) 1860 return (err); 1861 1862 mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn); 1863 1864 mcq->cqe_sz = 64; 1865 mcq->set_ci_db = cq->wq_ctrl.db.db; 1866 mcq->arm_db = cq->wq_ctrl.db.db + 1; 1867 *mcq->set_ci_db = 0; 1868 *mcq->arm_db = 0; 1869 mcq->vector = eq_ix; 1870 mcq->comp = comp; 1871 mcq->event = mlx5e_cq_error_event; 1872 mcq->irqn = irqn; 1873 mcq->uar = &priv->cq_uar; 1874 1875 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { 1876 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); 1877 1878 cqe->op_own = 0xf1; 1879 } 1880 1881 cq->priv = priv; 1882 1883 return (0); 1884 } 1885 1886 static void 1887 mlx5e_destroy_cq(struct mlx5e_cq *cq) 1888 { 1889 mlx5_wq_destroy(&cq->wq_ctrl); 1890 } 1891 1892 static int 1893 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix) 1894 { 1895 struct mlx5_core_cq *mcq = &cq->mcq; 1896 void *in; 1897 void *cqc; 1898 int inlen; 1899 int irqn_not_used; 1900 int eqn; 1901 int err; 1902 1903 inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 1904 sizeof(u64) * cq->wq_ctrl.buf.npages; 1905 in = mlx5_vzalloc(inlen); 1906 if (in == NULL) 1907 return (-ENOMEM); 1908 1909 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1910 1911 memcpy(cqc, param->cqc, sizeof(param->cqc)); 1912 1913 mlx5_fill_page_array(&cq->wq_ctrl.buf, 1914 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas)); 1915 1916 mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used); 1917 1918 MLX5_SET(cqc, cqc, c_eqn, eqn); 1919 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index); 1920 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - 1921 PAGE_SHIFT); 1922 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); 1923 1924 err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen); 1925 1926 kvfree(in); 1927 1928 if (err) 1929 return (err); 1930 1931 mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock)); 1932 1933 return (0); 1934 } 1935 1936 static void 1937 mlx5e_disable_cq(struct mlx5e_cq *cq) 1938 { 1939 1940 mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq); 1941 } 1942 1943 int 1944 mlx5e_open_cq(struct mlx5e_priv *priv, 1945 struct mlx5e_cq_param *param, 1946 struct mlx5e_cq *cq, 1947 mlx5e_cq_comp_t *comp, 1948 int eq_ix) 1949 { 1950 int err; 1951 1952 err = mlx5e_create_cq(priv, param, cq, comp, eq_ix); 1953 if (err) 1954 return (err); 1955 1956 err = mlx5e_enable_cq(cq, param, eq_ix); 1957 if (err) 1958 goto err_destroy_cq; 1959 1960 return (0); 1961 1962 err_destroy_cq: 1963 mlx5e_destroy_cq(cq); 1964 1965 return (err); 1966 } 1967 1968 void 1969 mlx5e_close_cq(struct mlx5e_cq *cq) 1970 { 1971 mlx5e_disable_cq(cq); 1972 mlx5e_destroy_cq(cq); 1973 } 1974 1975 static int 1976 mlx5e_open_tx_cqs(struct mlx5e_channel *c, 1977 struct mlx5e_channel_param *cparam) 1978 { 1979 int err; 1980 int tc; 1981 1982 for (tc = 0; tc < c->num_tc; tc++) { 1983 /* open completion queue */ 1984 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq, 1985 &mlx5e_tx_cq_comp, c->ix); 1986 if (err) 1987 goto err_close_tx_cqs; 1988 } 1989 return (0); 1990 1991 err_close_tx_cqs: 1992 for (tc--; tc >= 0; tc--) 1993 mlx5e_close_cq(&c->sq[tc].cq); 1994 1995 return (err); 1996 } 1997 1998 static void 1999 mlx5e_close_tx_cqs(struct mlx5e_channel *c) 2000 { 2001 int tc; 2002 2003 for (tc = 0; tc < c->num_tc; tc++) 2004 mlx5e_close_cq(&c->sq[tc].cq); 2005 } 2006 2007 static int 2008 mlx5e_open_sqs(struct mlx5e_channel *c, 2009 struct mlx5e_channel_param *cparam) 2010 { 2011 int err; 2012 int tc; 2013 2014 for (tc = 0; tc < c->num_tc; tc++) { 2015 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]); 2016 if (err) 2017 goto err_close_sqs; 2018 } 2019 2020 return (0); 2021 2022 err_close_sqs: 2023 for (tc--; tc >= 0; tc--) 2024 mlx5e_close_sq_wait(&c->sq[tc]); 2025 2026 return (err); 2027 } 2028 2029 static void 2030 mlx5e_close_sqs_wait(struct mlx5e_channel *c) 2031 { 2032 int tc; 2033 2034 for (tc = 0; tc < c->num_tc; tc++) 2035 mlx5e_close_sq_wait(&c->sq[tc]); 2036 } 2037 2038 static void 2039 mlx5e_chan_mtx_init(struct mlx5e_channel *c) 2040 { 2041 int tc; 2042 2043 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF); 2044 2045 callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0); 2046 2047 for (tc = 0; tc < c->num_tc; tc++) { 2048 struct mlx5e_sq *sq = c->sq + tc; 2049 2050 mtx_init(&sq->lock, "mlx5tx", 2051 MTX_NETWORK_LOCK " TX", MTX_DEF); 2052 mtx_init(&sq->comp_lock, "mlx5comp", 2053 MTX_NETWORK_LOCK " TX", MTX_DEF); 2054 2055 callout_init_mtx(&sq->cev_callout, &sq->lock, 0); 2056 2057 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact; 2058 2059 /* ensure the TX completion event factor is not zero */ 2060 if (sq->cev_factor == 0) 2061 sq->cev_factor = 1; 2062 } 2063 } 2064 2065 static void 2066 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c) 2067 { 2068 int tc; 2069 2070 mtx_destroy(&c->rq.mtx); 2071 2072 for (tc = 0; tc < c->num_tc; tc++) { 2073 mtx_destroy(&c->sq[tc].lock); 2074 mtx_destroy(&c->sq[tc].comp_lock); 2075 } 2076 } 2077 2078 static int 2079 mlx5e_open_channel(struct mlx5e_priv *priv, int ix, 2080 struct mlx5e_channel_param *cparam, 2081 struct mlx5e_channel *c) 2082 { 2083 int err; 2084 2085 memset(c, 0, sizeof(*c)); 2086 2087 c->priv = priv; 2088 c->ix = ix; 2089 /* setup send tag */ 2090 c->tag.m_snd_tag.ifp = priv->ifp; 2091 c->tag.type = IF_SND_TAG_TYPE_UNLIMITED; 2092 c->mkey_be = cpu_to_be32(priv->mr.key); 2093 c->num_tc = priv->num_tc; 2094 2095 /* init mutexes */ 2096 mlx5e_chan_mtx_init(c); 2097 2098 /* open transmit completion queue */ 2099 err = mlx5e_open_tx_cqs(c, cparam); 2100 if (err) 2101 goto err_free; 2102 2103 /* open receive completion queue */ 2104 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq, 2105 &mlx5e_rx_cq_comp, c->ix); 2106 if (err) 2107 goto err_close_tx_cqs; 2108 2109 err = mlx5e_open_sqs(c, cparam); 2110 if (err) 2111 goto err_close_rx_cq; 2112 2113 err = mlx5e_open_rq(c, &cparam->rq, &c->rq); 2114 if (err) 2115 goto err_close_sqs; 2116 2117 /* poll receive queue initially */ 2118 c->rq.cq.mcq.comp(&c->rq.cq.mcq); 2119 2120 return (0); 2121 2122 err_close_sqs: 2123 mlx5e_close_sqs_wait(c); 2124 2125 err_close_rx_cq: 2126 mlx5e_close_cq(&c->rq.cq); 2127 2128 err_close_tx_cqs: 2129 mlx5e_close_tx_cqs(c); 2130 2131 err_free: 2132 /* destroy mutexes */ 2133 mlx5e_chan_mtx_destroy(c); 2134 return (err); 2135 } 2136 2137 static void 2138 mlx5e_close_channel(struct mlx5e_channel *c) 2139 { 2140 mlx5e_close_rq(&c->rq); 2141 } 2142 2143 static void 2144 mlx5e_close_channel_wait(struct mlx5e_channel *c) 2145 { 2146 mlx5e_close_rq_wait(&c->rq); 2147 mlx5e_close_sqs_wait(c); 2148 mlx5e_close_tx_cqs(c); 2149 /* destroy mutexes */ 2150 mlx5e_chan_mtx_destroy(c); 2151 } 2152 2153 static int 2154 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs) 2155 { 2156 u32 r, n; 2157 2158 r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz : 2159 MLX5E_SW2MB_MTU(priv->ifp->if_mtu); 2160 if (r > MJUM16BYTES) 2161 return (-ENOMEM); 2162 2163 if (r > MJUM9BYTES) 2164 r = MJUM16BYTES; 2165 else if (r > MJUMPAGESIZE) 2166 r = MJUM9BYTES; 2167 else if (r > MCLBYTES) 2168 r = MJUMPAGESIZE; 2169 else 2170 r = MCLBYTES; 2171 2172 /* 2173 * n + 1 must be a power of two, because stride size must be. 2174 * Stride size is 16 * (n + 1), as the first segment is 2175 * control. 2176 */ 2177 for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++) 2178 ; 2179 2180 *wqe_sz = r; 2181 *nsegs = n; 2182 return (0); 2183 } 2184 2185 static void 2186 mlx5e_build_rq_param(struct mlx5e_priv *priv, 2187 struct mlx5e_rq_param *param) 2188 { 2189 void *rqc = param->rqc; 2190 void *wq = MLX5_ADDR_OF(rqc, rqc, wq); 2191 u32 wqe_sz, nsegs; 2192 2193 mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs); 2194 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); 2195 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 2196 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) + 2197 nsegs * sizeof(struct mlx5_wqe_data_seg))); 2198 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size); 2199 MLX5_SET(wq, wq, pd, priv->pdn); 2200 2201 param->wq.buf_numa_node = 0; 2202 param->wq.db_numa_node = 0; 2203 param->wq.linear = 1; 2204 } 2205 2206 static void 2207 mlx5e_build_sq_param(struct mlx5e_priv *priv, 2208 struct mlx5e_sq_param *param) 2209 { 2210 void *sqc = param->sqc; 2211 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 2212 2213 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size); 2214 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 2215 MLX5_SET(wq, wq, pd, priv->pdn); 2216 2217 param->wq.buf_numa_node = 0; 2218 param->wq.db_numa_node = 0; 2219 param->wq.linear = 1; 2220 } 2221 2222 static void 2223 mlx5e_build_common_cq_param(struct mlx5e_priv *priv, 2224 struct mlx5e_cq_param *param) 2225 { 2226 void *cqc = param->cqc; 2227 2228 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index); 2229 } 2230 2231 static void 2232 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr) 2233 { 2234 2235 *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE); 2236 2237 /* apply LRO restrictions */ 2238 if (priv->params.hw_lro_en && 2239 ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) { 2240 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO; 2241 } 2242 } 2243 2244 static void 2245 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, 2246 struct mlx5e_cq_param *param) 2247 { 2248 struct net_dim_cq_moder curr; 2249 void *cqc = param->cqc; 2250 2251 /* 2252 * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE 2253 * format is more beneficial for FreeBSD use case. 2254 * 2255 * Adding support for MLX5_CQE_FORMAT_CSUM will require changes 2256 * in mlx5e_decompress_cqe. 2257 */ 2258 if (priv->params.cqe_zipping_en) { 2259 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH); 2260 MLX5_SET(cqc, cqc, cqe_compression_en, 1); 2261 } 2262 2263 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size); 2264 2265 switch (priv->params.rx_cq_moderation_mode) { 2266 case 0: 2267 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec); 2268 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts); 2269 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2270 break; 2271 case 1: 2272 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec); 2273 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts); 2274 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2275 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2276 else 2277 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2278 break; 2279 case 2: 2280 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr); 2281 MLX5_SET(cqc, cqc, cq_period, curr.usec); 2282 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts); 2283 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2284 break; 2285 case 3: 2286 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr); 2287 MLX5_SET(cqc, cqc, cq_period, curr.usec); 2288 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts); 2289 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2290 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2291 else 2292 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2293 break; 2294 default: 2295 break; 2296 } 2297 2298 mlx5e_dim_build_cq_param(priv, param); 2299 2300 mlx5e_build_common_cq_param(priv, param); 2301 } 2302 2303 static void 2304 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv, 2305 struct mlx5e_cq_param *param) 2306 { 2307 void *cqc = param->cqc; 2308 2309 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size); 2310 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec); 2311 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts); 2312 2313 switch (priv->params.tx_cq_moderation_mode) { 2314 case 0: 2315 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2316 break; 2317 default: 2318 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2319 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2320 else 2321 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2322 break; 2323 } 2324 2325 mlx5e_build_common_cq_param(priv, param); 2326 } 2327 2328 static void 2329 mlx5e_build_channel_param(struct mlx5e_priv *priv, 2330 struct mlx5e_channel_param *cparam) 2331 { 2332 memset(cparam, 0, sizeof(*cparam)); 2333 2334 mlx5e_build_rq_param(priv, &cparam->rq); 2335 mlx5e_build_sq_param(priv, &cparam->sq); 2336 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq); 2337 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq); 2338 } 2339 2340 static int 2341 mlx5e_open_channels(struct mlx5e_priv *priv) 2342 { 2343 struct mlx5e_channel_param cparam; 2344 int err; 2345 int i; 2346 int j; 2347 2348 mlx5e_build_channel_param(priv, &cparam); 2349 for (i = 0; i < priv->params.num_channels; i++) { 2350 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]); 2351 if (err) 2352 goto err_close_channels; 2353 } 2354 2355 for (j = 0; j < priv->params.num_channels; j++) { 2356 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq); 2357 if (err) 2358 goto err_close_channels; 2359 } 2360 return (0); 2361 2362 err_close_channels: 2363 while (i--) { 2364 mlx5e_close_channel(&priv->channel[i]); 2365 mlx5e_close_channel_wait(&priv->channel[i]); 2366 } 2367 return (err); 2368 } 2369 2370 static void 2371 mlx5e_close_channels(struct mlx5e_priv *priv) 2372 { 2373 int i; 2374 2375 for (i = 0; i < priv->params.num_channels; i++) 2376 mlx5e_close_channel(&priv->channel[i]); 2377 for (i = 0; i < priv->params.num_channels; i++) 2378 mlx5e_close_channel_wait(&priv->channel[i]); 2379 } 2380 2381 static int 2382 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq) 2383 { 2384 2385 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) { 2386 uint8_t cq_mode; 2387 2388 switch (priv->params.tx_cq_moderation_mode) { 2389 case 0: 2390 case 2: 2391 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 2392 break; 2393 default: 2394 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE; 2395 break; 2396 } 2397 2398 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq, 2399 priv->params.tx_cq_moderation_usec, 2400 priv->params.tx_cq_moderation_pkts, 2401 cq_mode)); 2402 } 2403 2404 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq, 2405 priv->params.tx_cq_moderation_usec, 2406 priv->params.tx_cq_moderation_pkts)); 2407 } 2408 2409 static int 2410 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq) 2411 { 2412 2413 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) { 2414 uint8_t cq_mode; 2415 uint8_t dim_mode; 2416 int retval; 2417 2418 switch (priv->params.rx_cq_moderation_mode) { 2419 case 0: 2420 case 2: 2421 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 2422 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; 2423 break; 2424 default: 2425 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE; 2426 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE; 2427 break; 2428 } 2429 2430 /* tear down dynamic interrupt moderation */ 2431 mtx_lock(&rq->mtx); 2432 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 2433 mtx_unlock(&rq->mtx); 2434 2435 /* wait for dynamic interrupt moderation work task, if any */ 2436 cancel_work_sync(&rq->dim.work); 2437 2438 if (priv->params.rx_cq_moderation_mode >= 2) { 2439 struct net_dim_cq_moder curr; 2440 2441 mlx5e_get_default_profile(priv, dim_mode, &curr); 2442 2443 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq, 2444 curr.usec, curr.pkts, cq_mode); 2445 2446 /* set dynamic interrupt moderation mode and zero defaults */ 2447 mtx_lock(&rq->mtx); 2448 rq->dim.mode = dim_mode; 2449 rq->dim.state = 0; 2450 rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE; 2451 mtx_unlock(&rq->mtx); 2452 } else { 2453 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq, 2454 priv->params.rx_cq_moderation_usec, 2455 priv->params.rx_cq_moderation_pkts, 2456 cq_mode); 2457 } 2458 return (retval); 2459 } 2460 2461 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq, 2462 priv->params.rx_cq_moderation_usec, 2463 priv->params.rx_cq_moderation_pkts)); 2464 } 2465 2466 static int 2467 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c) 2468 { 2469 int err; 2470 int i; 2471 2472 err = mlx5e_refresh_rq_params(priv, &c->rq); 2473 if (err) 2474 goto done; 2475 2476 for (i = 0; i != c->num_tc; i++) { 2477 err = mlx5e_refresh_sq_params(priv, &c->sq[i]); 2478 if (err) 2479 goto done; 2480 } 2481 done: 2482 return (err); 2483 } 2484 2485 int 2486 mlx5e_refresh_channel_params(struct mlx5e_priv *priv) 2487 { 2488 int i; 2489 2490 /* check if channels are closed */ 2491 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 2492 return (EINVAL); 2493 2494 for (i = 0; i < priv->params.num_channels; i++) { 2495 int err; 2496 2497 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]); 2498 if (err) 2499 return (err); 2500 } 2501 return (0); 2502 } 2503 2504 static int 2505 mlx5e_open_tis(struct mlx5e_priv *priv, int tc) 2506 { 2507 struct mlx5_core_dev *mdev = priv->mdev; 2508 u32 in[MLX5_ST_SZ_DW(create_tis_in)]; 2509 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 2510 2511 memset(in, 0, sizeof(in)); 2512 2513 MLX5_SET(tisc, tisc, prio, tc); 2514 MLX5_SET(tisc, tisc, transport_domain, priv->tdn); 2515 2516 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc])); 2517 } 2518 2519 static void 2520 mlx5e_close_tis(struct mlx5e_priv *priv, int tc) 2521 { 2522 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]); 2523 } 2524 2525 static int 2526 mlx5e_open_tises(struct mlx5e_priv *priv) 2527 { 2528 int num_tc = priv->num_tc; 2529 int err; 2530 int tc; 2531 2532 for (tc = 0; tc < num_tc; tc++) { 2533 err = mlx5e_open_tis(priv, tc); 2534 if (err) 2535 goto err_close_tises; 2536 } 2537 2538 return (0); 2539 2540 err_close_tises: 2541 for (tc--; tc >= 0; tc--) 2542 mlx5e_close_tis(priv, tc); 2543 2544 return (err); 2545 } 2546 2547 static void 2548 mlx5e_close_tises(struct mlx5e_priv *priv) 2549 { 2550 int num_tc = priv->num_tc; 2551 int tc; 2552 2553 for (tc = 0; tc < num_tc; tc++) 2554 mlx5e_close_tis(priv, tc); 2555 } 2556 2557 static int 2558 mlx5e_open_rqt(struct mlx5e_priv *priv) 2559 { 2560 struct mlx5_core_dev *mdev = priv->mdev; 2561 u32 *in; 2562 u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 2563 void *rqtc; 2564 int inlen; 2565 int err; 2566 int sz; 2567 int i; 2568 2569 sz = 1 << priv->params.rx_hash_log_tbl_sz; 2570 2571 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 2572 in = mlx5_vzalloc(inlen); 2573 if (in == NULL) 2574 return (-ENOMEM); 2575 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 2576 2577 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 2578 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 2579 2580 for (i = 0; i < sz; i++) { 2581 int ix = i; 2582 #ifdef RSS 2583 ix = rss_get_indirection_to_bucket(ix); 2584 #endif 2585 /* ensure we don't overflow */ 2586 ix %= priv->params.num_channels; 2587 2588 /* apply receive side scaling stride, if any */ 2589 ix -= ix % (int)priv->params.channels_rsss; 2590 2591 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn); 2592 } 2593 2594 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 2595 2596 err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out)); 2597 if (!err) 2598 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn); 2599 2600 kvfree(in); 2601 2602 return (err); 2603 } 2604 2605 static void 2606 mlx5e_close_rqt(struct mlx5e_priv *priv) 2607 { 2608 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0}; 2609 u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0}; 2610 2611 MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT); 2612 MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn); 2613 2614 mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)); 2615 } 2616 2617 static void 2618 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt) 2619 { 2620 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 2621 __be32 *hkey; 2622 2623 MLX5_SET(tirc, tirc, transport_domain, priv->tdn); 2624 2625 #define ROUGH_MAX_L2_L3_HDR_SZ 256 2626 2627 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2628 MLX5_HASH_FIELD_SEL_DST_IP) 2629 2630 #define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2631 MLX5_HASH_FIELD_SEL_DST_IP |\ 2632 MLX5_HASH_FIELD_SEL_L4_SPORT |\ 2633 MLX5_HASH_FIELD_SEL_L4_DPORT) 2634 2635 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2636 MLX5_HASH_FIELD_SEL_DST_IP |\ 2637 MLX5_HASH_FIELD_SEL_IPSEC_SPI) 2638 2639 if (priv->params.hw_lro_en) { 2640 MLX5_SET(tirc, tirc, lro_enable_mask, 2641 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | 2642 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO); 2643 MLX5_SET(tirc, tirc, lro_max_msg_sz, 2644 (priv->params.lro_wqe_sz - 2645 ROUGH_MAX_L2_L3_HDR_SZ) >> 8); 2646 /* TODO: add the option to choose timer value dynamically */ 2647 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, 2648 MLX5_CAP_ETH(priv->mdev, 2649 lro_timer_supported_periods[2])); 2650 } 2651 2652 /* setup parameters for hashing TIR type, if any */ 2653 switch (tt) { 2654 case MLX5E_TT_ANY: 2655 MLX5_SET(tirc, tirc, disp_type, 2656 MLX5_TIRC_DISP_TYPE_DIRECT); 2657 MLX5_SET(tirc, tirc, inline_rqn, 2658 priv->channel[0].rq.rqn); 2659 break; 2660 default: 2661 MLX5_SET(tirc, tirc, disp_type, 2662 MLX5_TIRC_DISP_TYPE_INDIRECT); 2663 MLX5_SET(tirc, tirc, indirect_table, 2664 priv->rqtn); 2665 MLX5_SET(tirc, tirc, rx_hash_fn, 2666 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ); 2667 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 2668 #ifdef RSS 2669 /* 2670 * The FreeBSD RSS implementation does currently not 2671 * support symmetric Toeplitz hashes: 2672 */ 2673 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0); 2674 rss_getkey((uint8_t *)hkey); 2675 #else 2676 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 2677 hkey[0] = cpu_to_be32(0xD181C62C); 2678 hkey[1] = cpu_to_be32(0xF7F4DB5B); 2679 hkey[2] = cpu_to_be32(0x1983A2FC); 2680 hkey[3] = cpu_to_be32(0x943E1ADB); 2681 hkey[4] = cpu_to_be32(0xD9389E6B); 2682 hkey[5] = cpu_to_be32(0xD1039C2C); 2683 hkey[6] = cpu_to_be32(0xA74499AD); 2684 hkey[7] = cpu_to_be32(0x593D56D9); 2685 hkey[8] = cpu_to_be32(0xF3253C06); 2686 hkey[9] = cpu_to_be32(0x2ADC1FFC); 2687 #endif 2688 break; 2689 } 2690 2691 switch (tt) { 2692 case MLX5E_TT_IPV4_TCP: 2693 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2694 MLX5_L3_PROT_TYPE_IPV4); 2695 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2696 MLX5_L4_PROT_TYPE_TCP); 2697 #ifdef RSS 2698 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) { 2699 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2700 MLX5_HASH_IP); 2701 } else 2702 #endif 2703 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2704 MLX5_HASH_ALL); 2705 break; 2706 2707 case MLX5E_TT_IPV6_TCP: 2708 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2709 MLX5_L3_PROT_TYPE_IPV6); 2710 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2711 MLX5_L4_PROT_TYPE_TCP); 2712 #ifdef RSS 2713 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) { 2714 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2715 MLX5_HASH_IP); 2716 } else 2717 #endif 2718 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2719 MLX5_HASH_ALL); 2720 break; 2721 2722 case MLX5E_TT_IPV4_UDP: 2723 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2724 MLX5_L3_PROT_TYPE_IPV4); 2725 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2726 MLX5_L4_PROT_TYPE_UDP); 2727 #ifdef RSS 2728 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) { 2729 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2730 MLX5_HASH_IP); 2731 } else 2732 #endif 2733 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2734 MLX5_HASH_ALL); 2735 break; 2736 2737 case MLX5E_TT_IPV6_UDP: 2738 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2739 MLX5_L3_PROT_TYPE_IPV6); 2740 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2741 MLX5_L4_PROT_TYPE_UDP); 2742 #ifdef RSS 2743 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) { 2744 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2745 MLX5_HASH_IP); 2746 } else 2747 #endif 2748 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2749 MLX5_HASH_ALL); 2750 break; 2751 2752 case MLX5E_TT_IPV4_IPSEC_AH: 2753 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2754 MLX5_L3_PROT_TYPE_IPV4); 2755 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2756 MLX5_HASH_IP_IPSEC_SPI); 2757 break; 2758 2759 case MLX5E_TT_IPV6_IPSEC_AH: 2760 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2761 MLX5_L3_PROT_TYPE_IPV6); 2762 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2763 MLX5_HASH_IP_IPSEC_SPI); 2764 break; 2765 2766 case MLX5E_TT_IPV4_IPSEC_ESP: 2767 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2768 MLX5_L3_PROT_TYPE_IPV4); 2769 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2770 MLX5_HASH_IP_IPSEC_SPI); 2771 break; 2772 2773 case MLX5E_TT_IPV6_IPSEC_ESP: 2774 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2775 MLX5_L3_PROT_TYPE_IPV6); 2776 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2777 MLX5_HASH_IP_IPSEC_SPI); 2778 break; 2779 2780 case MLX5E_TT_IPV4: 2781 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2782 MLX5_L3_PROT_TYPE_IPV4); 2783 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2784 MLX5_HASH_IP); 2785 break; 2786 2787 case MLX5E_TT_IPV6: 2788 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2789 MLX5_L3_PROT_TYPE_IPV6); 2790 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2791 MLX5_HASH_IP); 2792 break; 2793 2794 default: 2795 break; 2796 } 2797 } 2798 2799 static int 2800 mlx5e_open_tir(struct mlx5e_priv *priv, int tt) 2801 { 2802 struct mlx5_core_dev *mdev = priv->mdev; 2803 u32 *in; 2804 void *tirc; 2805 int inlen; 2806 int err; 2807 2808 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 2809 in = mlx5_vzalloc(inlen); 2810 if (in == NULL) 2811 return (-ENOMEM); 2812 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context); 2813 2814 mlx5e_build_tir_ctx(priv, tirc, tt); 2815 2816 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]); 2817 2818 kvfree(in); 2819 2820 return (err); 2821 } 2822 2823 static void 2824 mlx5e_close_tir(struct mlx5e_priv *priv, int tt) 2825 { 2826 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]); 2827 } 2828 2829 static int 2830 mlx5e_open_tirs(struct mlx5e_priv *priv) 2831 { 2832 int err; 2833 int i; 2834 2835 for (i = 0; i < MLX5E_NUM_TT; i++) { 2836 err = mlx5e_open_tir(priv, i); 2837 if (err) 2838 goto err_close_tirs; 2839 } 2840 2841 return (0); 2842 2843 err_close_tirs: 2844 for (i--; i >= 0; i--) 2845 mlx5e_close_tir(priv, i); 2846 2847 return (err); 2848 } 2849 2850 static void 2851 mlx5e_close_tirs(struct mlx5e_priv *priv) 2852 { 2853 int i; 2854 2855 for (i = 0; i < MLX5E_NUM_TT; i++) 2856 mlx5e_close_tir(priv, i); 2857 } 2858 2859 /* 2860 * SW MTU does not include headers, 2861 * HW MTU includes all headers and checksums. 2862 */ 2863 static int 2864 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu) 2865 { 2866 struct mlx5e_priv *priv = ifp->if_softc; 2867 struct mlx5_core_dev *mdev = priv->mdev; 2868 int hw_mtu; 2869 int err; 2870 2871 hw_mtu = MLX5E_SW2HW_MTU(sw_mtu); 2872 2873 err = mlx5_set_port_mtu(mdev, hw_mtu); 2874 if (err) { 2875 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n", 2876 __func__, sw_mtu, err); 2877 return (err); 2878 } 2879 2880 /* Update vport context MTU */ 2881 err = mlx5_set_vport_mtu(mdev, hw_mtu); 2882 if (err) { 2883 if_printf(ifp, "%s: Failed updating vport context with MTU size, err=%d\n", 2884 __func__, err); 2885 } 2886 2887 ifp->if_mtu = sw_mtu; 2888 2889 err = mlx5_query_vport_mtu(mdev, &hw_mtu); 2890 if (err || !hw_mtu) { 2891 /* fallback to port oper mtu */ 2892 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu); 2893 } 2894 if (err) { 2895 if_printf(ifp, "Query port MTU, after setting new " 2896 "MTU value, failed\n"); 2897 return (err); 2898 } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) { 2899 err = -E2BIG, 2900 if_printf(ifp, "Port MTU %d is smaller than " 2901 "ifp mtu %d\n", hw_mtu, sw_mtu); 2902 } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) { 2903 err = -EINVAL; 2904 if_printf(ifp, "Port MTU %d is bigger than " 2905 "ifp mtu %d\n", hw_mtu, sw_mtu); 2906 } 2907 priv->params_ethtool.hw_mtu = hw_mtu; 2908 2909 return (err); 2910 } 2911 2912 int 2913 mlx5e_open_locked(struct ifnet *ifp) 2914 { 2915 struct mlx5e_priv *priv = ifp->if_softc; 2916 int err; 2917 u16 set_id; 2918 2919 /* check if already opened */ 2920 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 2921 return (0); 2922 2923 #ifdef RSS 2924 if (rss_getnumbuckets() > priv->params.num_channels) { 2925 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than " 2926 "channels(%u) available\n", rss_getnumbuckets(), 2927 priv->params.num_channels); 2928 } 2929 #endif 2930 err = mlx5e_open_tises(priv); 2931 if (err) { 2932 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n", 2933 __func__, err); 2934 return (err); 2935 } 2936 err = mlx5_vport_alloc_q_counter(priv->mdev, 2937 MLX5_INTERFACE_PROTOCOL_ETH, &set_id); 2938 if (err) { 2939 if_printf(priv->ifp, 2940 "%s: mlx5_vport_alloc_q_counter failed: %d\n", 2941 __func__, err); 2942 goto err_close_tises; 2943 } 2944 /* store counter set ID */ 2945 priv->counter_set_id = set_id; 2946 2947 err = mlx5e_open_channels(priv); 2948 if (err) { 2949 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n", 2950 __func__, err); 2951 goto err_dalloc_q_counter; 2952 } 2953 err = mlx5e_open_rqt(priv); 2954 if (err) { 2955 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n", 2956 __func__, err); 2957 goto err_close_channels; 2958 } 2959 err = mlx5e_open_tirs(priv); 2960 if (err) { 2961 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n", 2962 __func__, err); 2963 goto err_close_rqls; 2964 } 2965 err = mlx5e_open_flow_table(priv); 2966 if (err) { 2967 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n", 2968 __func__, err); 2969 goto err_close_tirs; 2970 } 2971 err = mlx5e_add_all_vlan_rules(priv); 2972 if (err) { 2973 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n", 2974 __func__, err); 2975 goto err_close_flow_table; 2976 } 2977 set_bit(MLX5E_STATE_OPENED, &priv->state); 2978 2979 mlx5e_update_carrier(priv); 2980 mlx5e_set_rx_mode_core(priv); 2981 2982 return (0); 2983 2984 err_close_flow_table: 2985 mlx5e_close_flow_table(priv); 2986 2987 err_close_tirs: 2988 mlx5e_close_tirs(priv); 2989 2990 err_close_rqls: 2991 mlx5e_close_rqt(priv); 2992 2993 err_close_channels: 2994 mlx5e_close_channels(priv); 2995 2996 err_dalloc_q_counter: 2997 mlx5_vport_dealloc_q_counter(priv->mdev, 2998 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 2999 3000 err_close_tises: 3001 mlx5e_close_tises(priv); 3002 3003 return (err); 3004 } 3005 3006 static void 3007 mlx5e_open(void *arg) 3008 { 3009 struct mlx5e_priv *priv = arg; 3010 3011 PRIV_LOCK(priv); 3012 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP)) 3013 if_printf(priv->ifp, 3014 "%s: Setting port status to up failed\n", 3015 __func__); 3016 3017 mlx5e_open_locked(priv->ifp); 3018 priv->ifp->if_drv_flags |= IFF_DRV_RUNNING; 3019 PRIV_UNLOCK(priv); 3020 } 3021 3022 int 3023 mlx5e_close_locked(struct ifnet *ifp) 3024 { 3025 struct mlx5e_priv *priv = ifp->if_softc; 3026 3027 /* check if already closed */ 3028 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3029 return (0); 3030 3031 clear_bit(MLX5E_STATE_OPENED, &priv->state); 3032 3033 mlx5e_set_rx_mode_core(priv); 3034 mlx5e_del_all_vlan_rules(priv); 3035 if_link_state_change(priv->ifp, LINK_STATE_DOWN); 3036 mlx5e_close_flow_table(priv); 3037 mlx5e_close_tirs(priv); 3038 mlx5e_close_rqt(priv); 3039 mlx5e_close_channels(priv); 3040 mlx5_vport_dealloc_q_counter(priv->mdev, 3041 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 3042 mlx5e_close_tises(priv); 3043 3044 return (0); 3045 } 3046 3047 #if (__FreeBSD_version >= 1100000) 3048 static uint64_t 3049 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt) 3050 { 3051 struct mlx5e_priv *priv = ifp->if_softc; 3052 u64 retval; 3053 3054 /* PRIV_LOCK(priv); XXX not allowed */ 3055 switch (cnt) { 3056 case IFCOUNTER_IPACKETS: 3057 retval = priv->stats.vport.rx_packets; 3058 break; 3059 case IFCOUNTER_IERRORS: 3060 retval = priv->stats.pport.in_range_len_errors + 3061 priv->stats.pport.out_of_range_len + 3062 priv->stats.pport.too_long_errors + 3063 priv->stats.pport.check_seq_err + 3064 priv->stats.pport.alignment_err; 3065 break; 3066 case IFCOUNTER_IQDROPS: 3067 retval = priv->stats.vport.rx_out_of_buffer; 3068 break; 3069 case IFCOUNTER_OPACKETS: 3070 retval = priv->stats.vport.tx_packets; 3071 break; 3072 case IFCOUNTER_OERRORS: 3073 retval = priv->stats.port_stats_debug.out_discards; 3074 break; 3075 case IFCOUNTER_IBYTES: 3076 retval = priv->stats.vport.rx_bytes; 3077 break; 3078 case IFCOUNTER_OBYTES: 3079 retval = priv->stats.vport.tx_bytes; 3080 break; 3081 case IFCOUNTER_IMCASTS: 3082 retval = priv->stats.vport.rx_multicast_packets; 3083 break; 3084 case IFCOUNTER_OMCASTS: 3085 retval = priv->stats.vport.tx_multicast_packets; 3086 break; 3087 case IFCOUNTER_OQDROPS: 3088 retval = priv->stats.vport.tx_queue_dropped; 3089 break; 3090 case IFCOUNTER_COLLISIONS: 3091 retval = priv->stats.pport.collisions; 3092 break; 3093 default: 3094 retval = if_get_counter_default(ifp, cnt); 3095 break; 3096 } 3097 /* PRIV_UNLOCK(priv); XXX not allowed */ 3098 return (retval); 3099 } 3100 #endif 3101 3102 static void 3103 mlx5e_set_rx_mode(struct ifnet *ifp) 3104 { 3105 struct mlx5e_priv *priv = ifp->if_softc; 3106 3107 queue_work(priv->wq, &priv->set_rx_mode_work); 3108 } 3109 3110 static int 3111 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3112 { 3113 struct mlx5e_priv *priv; 3114 struct ifreq *ifr; 3115 struct ifi2creq i2c; 3116 int error = 0; 3117 int mask = 0; 3118 int size_read = 0; 3119 int module_status; 3120 int module_num; 3121 int max_mtu; 3122 uint8_t read_addr; 3123 3124 priv = ifp->if_softc; 3125 3126 /* check if detaching */ 3127 if (priv == NULL || priv->gone != 0) 3128 return (ENXIO); 3129 3130 switch (command) { 3131 case SIOCSIFMTU: 3132 ifr = (struct ifreq *)data; 3133 3134 PRIV_LOCK(priv); 3135 mlx5_query_port_max_mtu(priv->mdev, &max_mtu); 3136 3137 if (ifr->ifr_mtu >= MLX5E_MTU_MIN && 3138 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) { 3139 int was_opened; 3140 3141 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 3142 if (was_opened) 3143 mlx5e_close_locked(ifp); 3144 3145 /* set new MTU */ 3146 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu); 3147 3148 if (was_opened) 3149 mlx5e_open_locked(ifp); 3150 } else { 3151 error = EINVAL; 3152 if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n", 3153 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu)); 3154 } 3155 PRIV_UNLOCK(priv); 3156 break; 3157 case SIOCSIFFLAGS: 3158 if ((ifp->if_flags & IFF_UP) && 3159 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3160 mlx5e_set_rx_mode(ifp); 3161 break; 3162 } 3163 PRIV_LOCK(priv); 3164 if (ifp->if_flags & IFF_UP) { 3165 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3166 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3167 mlx5e_open_locked(ifp); 3168 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3169 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP); 3170 } 3171 } else { 3172 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3173 mlx5_set_port_status(priv->mdev, 3174 MLX5_PORT_DOWN); 3175 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 3176 mlx5e_close_locked(ifp); 3177 mlx5e_update_carrier(priv); 3178 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3179 } 3180 } 3181 PRIV_UNLOCK(priv); 3182 break; 3183 case SIOCADDMULTI: 3184 case SIOCDELMULTI: 3185 mlx5e_set_rx_mode(ifp); 3186 break; 3187 case SIOCSIFMEDIA: 3188 case SIOCGIFMEDIA: 3189 case SIOCGIFXMEDIA: 3190 ifr = (struct ifreq *)data; 3191 error = ifmedia_ioctl(ifp, ifr, &priv->media, command); 3192 break; 3193 case SIOCSIFCAP: 3194 ifr = (struct ifreq *)data; 3195 PRIV_LOCK(priv); 3196 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3197 3198 if (mask & IFCAP_TXCSUM) { 3199 ifp->if_capenable ^= IFCAP_TXCSUM; 3200 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 3201 3202 if (IFCAP_TSO4 & ifp->if_capenable && 3203 !(IFCAP_TXCSUM & ifp->if_capenable)) { 3204 ifp->if_capenable &= ~IFCAP_TSO4; 3205 ifp->if_hwassist &= ~CSUM_IP_TSO; 3206 if_printf(ifp, 3207 "tso4 disabled due to -txcsum.\n"); 3208 } 3209 } 3210 if (mask & IFCAP_TXCSUM_IPV6) { 3211 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 3212 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 3213 3214 if (IFCAP_TSO6 & ifp->if_capenable && 3215 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 3216 ifp->if_capenable &= ~IFCAP_TSO6; 3217 ifp->if_hwassist &= ~CSUM_IP6_TSO; 3218 if_printf(ifp, 3219 "tso6 disabled due to -txcsum6.\n"); 3220 } 3221 } 3222 if (mask & IFCAP_RXCSUM) 3223 ifp->if_capenable ^= IFCAP_RXCSUM; 3224 if (mask & IFCAP_RXCSUM_IPV6) 3225 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 3226 if (mask & IFCAP_TSO4) { 3227 if (!(IFCAP_TSO4 & ifp->if_capenable) && 3228 !(IFCAP_TXCSUM & ifp->if_capenable)) { 3229 if_printf(ifp, "enable txcsum first.\n"); 3230 error = EAGAIN; 3231 goto out; 3232 } 3233 ifp->if_capenable ^= IFCAP_TSO4; 3234 ifp->if_hwassist ^= CSUM_IP_TSO; 3235 } 3236 if (mask & IFCAP_TSO6) { 3237 if (!(IFCAP_TSO6 & ifp->if_capenable) && 3238 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 3239 if_printf(ifp, "enable txcsum6 first.\n"); 3240 error = EAGAIN; 3241 goto out; 3242 } 3243 ifp->if_capenable ^= IFCAP_TSO6; 3244 ifp->if_hwassist ^= CSUM_IP6_TSO; 3245 } 3246 if (mask & IFCAP_VLAN_HWFILTER) { 3247 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) 3248 mlx5e_disable_vlan_filter(priv); 3249 else 3250 mlx5e_enable_vlan_filter(priv); 3251 3252 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER; 3253 } 3254 if (mask & IFCAP_VLAN_HWTAGGING) 3255 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3256 if (mask & IFCAP_WOL_MAGIC) 3257 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3258 3259 VLAN_CAPABILITIES(ifp); 3260 /* turn off LRO means also turn of HW LRO - if it's on */ 3261 if (mask & IFCAP_LRO) { 3262 int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 3263 bool need_restart = false; 3264 3265 ifp->if_capenable ^= IFCAP_LRO; 3266 3267 /* figure out if updating HW LRO is needed */ 3268 if (!(ifp->if_capenable & IFCAP_LRO)) { 3269 if (priv->params.hw_lro_en) { 3270 priv->params.hw_lro_en = false; 3271 need_restart = true; 3272 } 3273 } else { 3274 if (priv->params.hw_lro_en == false && 3275 priv->params_ethtool.hw_lro != 0) { 3276 priv->params.hw_lro_en = true; 3277 need_restart = true; 3278 } 3279 } 3280 if (was_opened && need_restart) { 3281 mlx5e_close_locked(ifp); 3282 mlx5e_open_locked(ifp); 3283 } 3284 } 3285 if (mask & IFCAP_HWRXTSTMP) { 3286 ifp->if_capenable ^= IFCAP_HWRXTSTMP; 3287 if (ifp->if_capenable & IFCAP_HWRXTSTMP) { 3288 if (priv->clbr_done == 0) 3289 mlx5e_reset_calibration_callout(priv); 3290 } else { 3291 callout_drain(&priv->tstmp_clbr); 3292 priv->clbr_done = 0; 3293 } 3294 } 3295 out: 3296 PRIV_UNLOCK(priv); 3297 break; 3298 3299 case SIOCGI2C: 3300 ifr = (struct ifreq *)data; 3301 3302 /* 3303 * Copy from the user-space address ifr_data to the 3304 * kernel-space address i2c 3305 */ 3306 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 3307 if (error) 3308 break; 3309 3310 if (i2c.len > sizeof(i2c.data)) { 3311 error = EINVAL; 3312 break; 3313 } 3314 3315 PRIV_LOCK(priv); 3316 /* Get module_num which is required for the query_eeprom */ 3317 error = mlx5_query_module_num(priv->mdev, &module_num); 3318 if (error) { 3319 if_printf(ifp, "Query module num failed, eeprom " 3320 "reading is not supported\n"); 3321 error = EINVAL; 3322 goto err_i2c; 3323 } 3324 /* Check if module is present before doing an access */ 3325 module_status = mlx5_query_module_status(priv->mdev, module_num); 3326 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED && 3327 module_status != MLX5_MODULE_STATUS_PLUGGED_DISABLED) { 3328 error = EINVAL; 3329 goto err_i2c; 3330 } 3331 /* 3332 * Currently 0XA0 and 0xA2 are the only addresses permitted. 3333 * The internal conversion is as follows: 3334 */ 3335 if (i2c.dev_addr == 0xA0) 3336 read_addr = MLX5E_I2C_ADDR_LOW; 3337 else if (i2c.dev_addr == 0xA2) 3338 read_addr = MLX5E_I2C_ADDR_HIGH; 3339 else { 3340 if_printf(ifp, "Query eeprom failed, " 3341 "Invalid Address: %X\n", i2c.dev_addr); 3342 error = EINVAL; 3343 goto err_i2c; 3344 } 3345 error = mlx5_query_eeprom(priv->mdev, 3346 read_addr, MLX5E_EEPROM_LOW_PAGE, 3347 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num, 3348 (uint32_t *)i2c.data, &size_read); 3349 if (error) { 3350 if_printf(ifp, "Query eeprom failed, eeprom " 3351 "reading is not supported\n"); 3352 error = EINVAL; 3353 goto err_i2c; 3354 } 3355 3356 if (i2c.len > MLX5_EEPROM_MAX_BYTES) { 3357 error = mlx5_query_eeprom(priv->mdev, 3358 read_addr, MLX5E_EEPROM_LOW_PAGE, 3359 (uint32_t)(i2c.offset + size_read), 3360 (uint32_t)(i2c.len - size_read), module_num, 3361 (uint32_t *)(i2c.data + size_read), &size_read); 3362 } 3363 if (error) { 3364 if_printf(ifp, "Query eeprom failed, eeprom " 3365 "reading is not supported\n"); 3366 error = EINVAL; 3367 goto err_i2c; 3368 } 3369 3370 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 3371 err_i2c: 3372 PRIV_UNLOCK(priv); 3373 break; 3374 3375 default: 3376 error = ether_ioctl(ifp, command, data); 3377 break; 3378 } 3379 return (error); 3380 } 3381 3382 static int 3383 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev) 3384 { 3385 /* 3386 * TODO: uncoment once FW really sets all these bits if 3387 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap || 3388 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap || 3389 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return 3390 * -ENOTSUPP; 3391 */ 3392 3393 /* TODO: add more must-to-have features */ 3394 3395 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) 3396 return (-ENODEV); 3397 3398 return (0); 3399 } 3400 3401 static u16 3402 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev) 3403 { 3404 uint32_t bf_buf_size = (1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U; 3405 3406 bf_buf_size -= sizeof(struct mlx5e_tx_wqe) - 2; 3407 3408 /* verify against driver hardware limit */ 3409 if (bf_buf_size > MLX5E_MAX_TX_INLINE) 3410 bf_buf_size = MLX5E_MAX_TX_INLINE; 3411 3412 return (bf_buf_size); 3413 } 3414 3415 static int 3416 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev, 3417 struct mlx5e_priv *priv, 3418 int num_comp_vectors) 3419 { 3420 int err; 3421 3422 /* 3423 * TODO: Consider link speed for setting "log_sq_size", 3424 * "log_rq_size" and "cq_moderation_xxx": 3425 */ 3426 priv->params.log_sq_size = 3427 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; 3428 priv->params.log_rq_size = 3429 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; 3430 priv->params.rx_cq_moderation_usec = 3431 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 3432 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE : 3433 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; 3434 priv->params.rx_cq_moderation_mode = 3435 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0; 3436 priv->params.rx_cq_moderation_pkts = 3437 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; 3438 priv->params.tx_cq_moderation_usec = 3439 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; 3440 priv->params.tx_cq_moderation_pkts = 3441 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; 3442 priv->params.min_rx_wqes = 3443 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES; 3444 priv->params.rx_hash_log_tbl_sz = 3445 (order_base_2(num_comp_vectors) > 3446 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ? 3447 order_base_2(num_comp_vectors) : 3448 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ; 3449 priv->params.num_tc = 1; 3450 priv->params.default_vlan_prio = 0; 3451 priv->counter_set_id = -1; 3452 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev); 3453 3454 err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode); 3455 if (err) 3456 return (err); 3457 3458 /* 3459 * hw lro is currently defaulted to off. when it won't anymore we 3460 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)" 3461 */ 3462 priv->params.hw_lro_en = false; 3463 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; 3464 3465 /* 3466 * CQE zipping is currently defaulted to off. when it won't 3467 * anymore we will consider the HW capability: 3468 * "!!MLX5_CAP_GEN(mdev, cqe_compression)" 3469 */ 3470 priv->params.cqe_zipping_en = false; 3471 3472 priv->mdev = mdev; 3473 priv->params.num_channels = num_comp_vectors; 3474 priv->params.channels_rsss = 1; 3475 priv->order_base_2_num_channels = order_base_2(num_comp_vectors); 3476 priv->queue_mapping_channel_mask = 3477 roundup_pow_of_two(num_comp_vectors) - 1; 3478 priv->num_tc = priv->params.num_tc; 3479 priv->default_vlan_prio = priv->params.default_vlan_prio; 3480 3481 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work); 3482 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); 3483 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); 3484 3485 return (0); 3486 } 3487 3488 static int 3489 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn, 3490 struct mlx5_core_mr *mkey) 3491 { 3492 struct ifnet *ifp = priv->ifp; 3493 struct mlx5_core_dev *mdev = priv->mdev; 3494 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 3495 void *mkc; 3496 u32 *in; 3497 int err; 3498 3499 in = mlx5_vzalloc(inlen); 3500 if (in == NULL) { 3501 if_printf(ifp, "%s: failed to allocate inbox\n", __func__); 3502 return (-ENOMEM); 3503 } 3504 3505 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 3506 MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA); 3507 MLX5_SET(mkc, mkc, lw, 1); 3508 MLX5_SET(mkc, mkc, lr, 1); 3509 3510 MLX5_SET(mkc, mkc, pd, pdn); 3511 MLX5_SET(mkc, mkc, length64, 1); 3512 MLX5_SET(mkc, mkc, qpn, 0xffffff); 3513 3514 err = mlx5_core_create_mkey(mdev, mkey, in, inlen); 3515 if (err) 3516 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n", 3517 __func__, err); 3518 3519 kvfree(in); 3520 return (err); 3521 } 3522 3523 static const char *mlx5e_vport_stats_desc[] = { 3524 MLX5E_VPORT_STATS(MLX5E_STATS_DESC) 3525 }; 3526 3527 static const char *mlx5e_pport_stats_desc[] = { 3528 MLX5E_PPORT_STATS(MLX5E_STATS_DESC) 3529 }; 3530 3531 static void 3532 mlx5e_priv_mtx_init(struct mlx5e_priv *priv) 3533 { 3534 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF); 3535 sx_init(&priv->state_lock, "mlx5state"); 3536 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0); 3537 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock); 3538 } 3539 3540 static void 3541 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv) 3542 { 3543 mtx_destroy(&priv->async_events_mtx); 3544 sx_destroy(&priv->state_lock); 3545 } 3546 3547 static int 3548 sysctl_firmware(SYSCTL_HANDLER_ARGS) 3549 { 3550 /* 3551 * %d.%d%.d the string format. 3552 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536. 3553 * We need at most 5 chars to store that. 3554 * It also has: two "." and NULL at the end, which means we need 18 3555 * (5*3 + 3) chars at most. 3556 */ 3557 char fw[18]; 3558 struct mlx5e_priv *priv = arg1; 3559 int error; 3560 3561 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev), 3562 fw_rev_sub(priv->mdev)); 3563 error = sysctl_handle_string(oidp, fw, sizeof(fw), req); 3564 return (error); 3565 } 3566 3567 static void 3568 mlx5e_disable_tx_dma(struct mlx5e_channel *ch) 3569 { 3570 int i; 3571 3572 for (i = 0; i < ch->num_tc; i++) 3573 mlx5e_drain_sq(&ch->sq[i]); 3574 } 3575 3576 static void 3577 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq) 3578 { 3579 3580 sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP); 3581 sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8); 3582 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0); 3583 sq->doorbell.d64 = 0; 3584 } 3585 3586 void 3587 mlx5e_resume_sq(struct mlx5e_sq *sq) 3588 { 3589 int err; 3590 3591 /* check if already enabled */ 3592 if (READ_ONCE(sq->running) != 0) 3593 return; 3594 3595 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR, 3596 MLX5_SQC_STATE_RST); 3597 if (err != 0) { 3598 if_printf(sq->ifp, 3599 "mlx5e_modify_sq() from ERR to RST failed: %d\n", err); 3600 } 3601 3602 sq->cc = 0; 3603 sq->pc = 0; 3604 3605 /* reset doorbell prior to moving from RST to RDY */ 3606 mlx5e_reset_sq_doorbell_record(sq); 3607 3608 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, 3609 MLX5_SQC_STATE_RDY); 3610 if (err != 0) { 3611 if_printf(sq->ifp, 3612 "mlx5e_modify_sq() from RST to RDY failed: %d\n", err); 3613 } 3614 3615 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL; 3616 WRITE_ONCE(sq->running, 1); 3617 } 3618 3619 static void 3620 mlx5e_enable_tx_dma(struct mlx5e_channel *ch) 3621 { 3622 int i; 3623 3624 for (i = 0; i < ch->num_tc; i++) 3625 mlx5e_resume_sq(&ch->sq[i]); 3626 } 3627 3628 static void 3629 mlx5e_disable_rx_dma(struct mlx5e_channel *ch) 3630 { 3631 struct mlx5e_rq *rq = &ch->rq; 3632 int err; 3633 3634 mtx_lock(&rq->mtx); 3635 rq->enabled = 0; 3636 callout_stop(&rq->watchdog); 3637 mtx_unlock(&rq->mtx); 3638 3639 callout_drain(&rq->watchdog); 3640 3641 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 3642 if (err != 0) { 3643 if_printf(rq->ifp, 3644 "mlx5e_modify_rq() from RDY to RST failed: %d\n", err); 3645 } 3646 3647 while (!mlx5_wq_ll_is_empty(&rq->wq)) { 3648 msleep(1); 3649 rq->cq.mcq.comp(&rq->cq.mcq); 3650 } 3651 3652 /* 3653 * Transitioning into RST state will allow the FW to track less ERR state queues, 3654 * thus reducing the recv queue flushing time 3655 */ 3656 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST); 3657 if (err != 0) { 3658 if_printf(rq->ifp, 3659 "mlx5e_modify_rq() from ERR to RST failed: %d\n", err); 3660 } 3661 } 3662 3663 static void 3664 mlx5e_enable_rx_dma(struct mlx5e_channel *ch) 3665 { 3666 struct mlx5e_rq *rq = &ch->rq; 3667 int err; 3668 3669 rq->wq.wqe_ctr = 0; 3670 mlx5_wq_ll_update_db_record(&rq->wq); 3671 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 3672 if (err != 0) { 3673 if_printf(rq->ifp, 3674 "mlx5e_modify_rq() from RST to RDY failed: %d\n", err); 3675 } 3676 3677 rq->enabled = 1; 3678 3679 rq->cq.mcq.comp(&rq->cq.mcq); 3680 } 3681 3682 void 3683 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value) 3684 { 3685 int i; 3686 3687 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3688 return; 3689 3690 for (i = 0; i < priv->params.num_channels; i++) { 3691 if (value) 3692 mlx5e_disable_tx_dma(&priv->channel[i]); 3693 else 3694 mlx5e_enable_tx_dma(&priv->channel[i]); 3695 } 3696 } 3697 3698 void 3699 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value) 3700 { 3701 int i; 3702 3703 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3704 return; 3705 3706 for (i = 0; i < priv->params.num_channels; i++) { 3707 if (value) 3708 mlx5e_disable_rx_dma(&priv->channel[i]); 3709 else 3710 mlx5e_enable_rx_dma(&priv->channel[i]); 3711 } 3712 } 3713 3714 static void 3715 mlx5e_add_hw_stats(struct mlx5e_priv *priv) 3716 { 3717 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 3718 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0, 3719 sysctl_firmware, "A", "HCA firmware version"); 3720 3721 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 3722 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0, 3723 "Board ID"); 3724 } 3725 3726 static int 3727 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS) 3728 { 3729 struct mlx5e_priv *priv = arg1; 3730 uint8_t temp[MLX5E_MAX_PRIORITY]; 3731 uint32_t tx_pfc; 3732 int err; 3733 int i; 3734 3735 PRIV_LOCK(priv); 3736 3737 tx_pfc = priv->params.tx_priority_flow_control; 3738 3739 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) 3740 temp[i] = (tx_pfc >> i) & 1; 3741 3742 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY); 3743 if (err || !req->newptr) 3744 goto done; 3745 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY); 3746 if (err) 3747 goto done; 3748 3749 priv->params.tx_priority_flow_control = 0; 3750 3751 /* range check input value */ 3752 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) { 3753 if (temp[i] > 1) { 3754 err = ERANGE; 3755 goto done; 3756 } 3757 priv->params.tx_priority_flow_control |= (temp[i] << i); 3758 } 3759 3760 /* check if update is required */ 3761 if (tx_pfc != priv->params.tx_priority_flow_control) 3762 err = -mlx5e_set_port_pfc(priv); 3763 done: 3764 if (err != 0) 3765 priv->params.tx_priority_flow_control= tx_pfc; 3766 PRIV_UNLOCK(priv); 3767 3768 return (err); 3769 } 3770 3771 static int 3772 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS) 3773 { 3774 struct mlx5e_priv *priv = arg1; 3775 uint8_t temp[MLX5E_MAX_PRIORITY]; 3776 uint32_t rx_pfc; 3777 int err; 3778 int i; 3779 3780 PRIV_LOCK(priv); 3781 3782 rx_pfc = priv->params.rx_priority_flow_control; 3783 3784 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) 3785 temp[i] = (rx_pfc >> i) & 1; 3786 3787 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY); 3788 if (err || !req->newptr) 3789 goto done; 3790 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY); 3791 if (err) 3792 goto done; 3793 3794 priv->params.rx_priority_flow_control = 0; 3795 3796 /* range check input value */ 3797 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) { 3798 if (temp[i] > 1) { 3799 err = ERANGE; 3800 goto done; 3801 } 3802 priv->params.rx_priority_flow_control |= (temp[i] << i); 3803 } 3804 3805 /* check if update is required */ 3806 if (rx_pfc != priv->params.rx_priority_flow_control) 3807 err = -mlx5e_set_port_pfc(priv); 3808 done: 3809 if (err != 0) 3810 priv->params.rx_priority_flow_control= rx_pfc; 3811 PRIV_UNLOCK(priv); 3812 3813 return (err); 3814 } 3815 3816 static void 3817 mlx5e_setup_pauseframes(struct mlx5e_priv *priv) 3818 { 3819 #if (__FreeBSD_version < 1100000) 3820 char path[96]; 3821 #endif 3822 int error; 3823 3824 /* enable pauseframes by default */ 3825 priv->params.tx_pauseframe_control = 1; 3826 priv->params.rx_pauseframe_control = 1; 3827 3828 /* disable ports flow control, PFC, by default */ 3829 priv->params.tx_priority_flow_control = 0; 3830 priv->params.rx_priority_flow_control = 0; 3831 3832 #if (__FreeBSD_version < 1100000) 3833 /* compute path for sysctl */ 3834 snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control", 3835 device_get_unit(priv->mdev->pdev->dev.bsddev)); 3836 3837 /* try to fetch tunable, if any */ 3838 TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control); 3839 3840 /* compute path for sysctl */ 3841 snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control", 3842 device_get_unit(priv->mdev->pdev->dev.bsddev)); 3843 3844 /* try to fetch tunable, if any */ 3845 TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control); 3846 #endif 3847 3848 /* register pauseframe SYSCTLs */ 3849 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 3850 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN, 3851 &priv->params.tx_pauseframe_control, 0, 3852 "Set to enable TX pause frames. Clear to disable."); 3853 3854 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 3855 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN, 3856 &priv->params.rx_pauseframe_control, 0, 3857 "Set to enable RX pause frames. Clear to disable."); 3858 3859 /* register priority flow control, PFC, SYSCTLs */ 3860 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 3861 OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN | 3862 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU", 3863 "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable."); 3864 3865 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 3866 OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN | 3867 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU", 3868 "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable."); 3869 3870 PRIV_LOCK(priv); 3871 3872 /* range check */ 3873 priv->params.tx_pauseframe_control = 3874 priv->params.tx_pauseframe_control ? 1 : 0; 3875 priv->params.rx_pauseframe_control = 3876 priv->params.rx_pauseframe_control ? 1 : 0; 3877 3878 /* update firmware */ 3879 error = mlx5e_set_port_pause_and_pfc(priv); 3880 if (error == -EINVAL) { 3881 if_printf(priv->ifp, 3882 "Global pauseframes must be disabled before enabling PFC.\n"); 3883 priv->params.rx_priority_flow_control = 0; 3884 priv->params.tx_priority_flow_control = 0; 3885 3886 /* update firmware */ 3887 (void) mlx5e_set_port_pause_and_pfc(priv); 3888 } 3889 PRIV_UNLOCK(priv); 3890 } 3891 3892 static int 3893 mlx5e_ul_snd_tag_alloc(struct ifnet *ifp, 3894 union if_snd_tag_alloc_params *params, 3895 struct m_snd_tag **ppmt) 3896 { 3897 struct mlx5e_priv *priv; 3898 struct mlx5e_channel *pch; 3899 3900 priv = ifp->if_softc; 3901 3902 if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) { 3903 return (EOPNOTSUPP); 3904 } else { 3905 /* keep this code synced with mlx5e_select_queue() */ 3906 u32 ch = priv->params.num_channels; 3907 #ifdef RSS 3908 u32 temp; 3909 3910 if (rss_hash2bucket(params->hdr.flowid, 3911 params->hdr.flowtype, &temp) == 0) 3912 ch = temp % ch; 3913 else 3914 #endif 3915 ch = (params->hdr.flowid % 128) % ch; 3916 3917 /* 3918 * NOTE: The channels array is only freed at detach 3919 * and it safe to return a pointer to the send tag 3920 * inside the channels structure as long as we 3921 * reference the priv. 3922 */ 3923 pch = priv->channel + ch; 3924 3925 /* check if send queue is not running */ 3926 if (unlikely(pch->sq[0].running == 0)) 3927 return (ENXIO); 3928 mlx5e_ref_channel(priv); 3929 *ppmt = &pch->tag.m_snd_tag; 3930 return (0); 3931 } 3932 } 3933 3934 static int 3935 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params) 3936 { 3937 struct mlx5e_channel *pch = 3938 container_of(pmt, struct mlx5e_channel, tag.m_snd_tag); 3939 3940 params->unlimited.max_rate = -1ULL; 3941 params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]); 3942 return (0); 3943 } 3944 3945 static void 3946 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt) 3947 { 3948 struct mlx5e_channel *pch = 3949 container_of(pmt, struct mlx5e_channel, tag.m_snd_tag); 3950 3951 mlx5e_unref_channel(pch->priv); 3952 } 3953 3954 static int 3955 mlx5e_snd_tag_alloc(struct ifnet *ifp, 3956 union if_snd_tag_alloc_params *params, 3957 struct m_snd_tag **ppmt) 3958 { 3959 3960 switch (params->hdr.type) { 3961 #ifdef RATELIMIT 3962 case IF_SND_TAG_TYPE_RATE_LIMIT: 3963 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt)); 3964 #endif 3965 case IF_SND_TAG_TYPE_UNLIMITED: 3966 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt)); 3967 default: 3968 return (EOPNOTSUPP); 3969 } 3970 } 3971 3972 static int 3973 mlx5e_snd_tag_modify(struct m_snd_tag *pmt, union if_snd_tag_modify_params *params) 3974 { 3975 struct mlx5e_snd_tag *tag = 3976 container_of(pmt, struct mlx5e_snd_tag, m_snd_tag); 3977 3978 switch (tag->type) { 3979 #ifdef RATELIMIT 3980 case IF_SND_TAG_TYPE_RATE_LIMIT: 3981 return (mlx5e_rl_snd_tag_modify(pmt, params)); 3982 #endif 3983 case IF_SND_TAG_TYPE_UNLIMITED: 3984 default: 3985 return (EOPNOTSUPP); 3986 } 3987 } 3988 3989 static int 3990 mlx5e_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params) 3991 { 3992 struct mlx5e_snd_tag *tag = 3993 container_of(pmt, struct mlx5e_snd_tag, m_snd_tag); 3994 3995 switch (tag->type) { 3996 #ifdef RATELIMIT 3997 case IF_SND_TAG_TYPE_RATE_LIMIT: 3998 return (mlx5e_rl_snd_tag_query(pmt, params)); 3999 #endif 4000 case IF_SND_TAG_TYPE_UNLIMITED: 4001 return (mlx5e_ul_snd_tag_query(pmt, params)); 4002 default: 4003 return (EOPNOTSUPP); 4004 } 4005 } 4006 4007 static void 4008 mlx5e_snd_tag_free(struct m_snd_tag *pmt) 4009 { 4010 struct mlx5e_snd_tag *tag = 4011 container_of(pmt, struct mlx5e_snd_tag, m_snd_tag); 4012 4013 switch (tag->type) { 4014 #ifdef RATELIMIT 4015 case IF_SND_TAG_TYPE_RATE_LIMIT: 4016 mlx5e_rl_snd_tag_free(pmt); 4017 break; 4018 #endif 4019 case IF_SND_TAG_TYPE_UNLIMITED: 4020 mlx5e_ul_snd_tag_free(pmt); 4021 break; 4022 default: 4023 break; 4024 } 4025 } 4026 4027 static void * 4028 mlx5e_create_ifp(struct mlx5_core_dev *mdev) 4029 { 4030 struct ifnet *ifp; 4031 struct mlx5e_priv *priv; 4032 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4); 4033 u8 connector_type; 4034 struct sysctl_oid_list *child; 4035 int ncv = mdev->priv.eq_table.num_comp_vectors; 4036 char unit[16]; 4037 struct pfil_head_args pa; 4038 int err; 4039 int i,j; 4040 u32 eth_proto_cap; 4041 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 4042 bool ext = 0; 4043 u32 speeds_num; 4044 struct media media_entry = {}; 4045 4046 if (mlx5e_check_required_hca_cap(mdev)) { 4047 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n"); 4048 return (NULL); 4049 } 4050 /* 4051 * Try to allocate the priv and make room for worst-case 4052 * number of channel structures: 4053 */ 4054 priv = malloc(sizeof(*priv) + 4055 (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors), 4056 M_MLX5EN, M_WAITOK | M_ZERO); 4057 mlx5e_priv_mtx_init(priv); 4058 4059 ifp = priv->ifp = if_alloc_dev(IFT_ETHER, mdev->pdev->dev.bsddev); 4060 if (ifp == NULL) { 4061 mlx5_core_err(mdev, "if_alloc() failed\n"); 4062 goto err_free_priv; 4063 } 4064 ifp->if_softc = priv; 4065 if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev)); 4066 ifp->if_mtu = ETHERMTU; 4067 ifp->if_init = mlx5e_open; 4068 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 4069 ifp->if_ioctl = mlx5e_ioctl; 4070 ifp->if_transmit = mlx5e_xmit; 4071 ifp->if_qflush = if_qflush; 4072 #if (__FreeBSD_version >= 1100000) 4073 ifp->if_get_counter = mlx5e_get_counter; 4074 #endif 4075 ifp->if_snd.ifq_maxlen = ifqmaxlen; 4076 /* 4077 * Set driver features 4078 */ 4079 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6; 4080 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 4081 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER; 4082 ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU; 4083 ifp->if_capabilities |= IFCAP_LRO; 4084 ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO; 4085 ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP; 4086 ifp->if_capabilities |= IFCAP_TXRTLMT; 4087 ifp->if_snd_tag_alloc = mlx5e_snd_tag_alloc; 4088 ifp->if_snd_tag_free = mlx5e_snd_tag_free; 4089 ifp->if_snd_tag_modify = mlx5e_snd_tag_modify; 4090 ifp->if_snd_tag_query = mlx5e_snd_tag_query; 4091 4092 /* set TSO limits so that we don't have to drop TX packets */ 4093 ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 4094 ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */; 4095 ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE; 4096 4097 ifp->if_capenable = ifp->if_capabilities; 4098 ifp->if_hwassist = 0; 4099 if (ifp->if_capenable & IFCAP_TSO) 4100 ifp->if_hwassist |= CSUM_TSO; 4101 if (ifp->if_capenable & IFCAP_TXCSUM) 4102 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP); 4103 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6) 4104 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 4105 4106 /* ifnet sysctl tree */ 4107 sysctl_ctx_init(&priv->sysctl_ctx); 4108 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev), 4109 OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name"); 4110 if (priv->sysctl_ifnet == NULL) { 4111 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4112 goto err_free_sysctl; 4113 } 4114 snprintf(unit, sizeof(unit), "%d", ifp->if_dunit); 4115 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4116 OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit"); 4117 if (priv->sysctl_ifnet == NULL) { 4118 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4119 goto err_free_sysctl; 4120 } 4121 4122 /* HW sysctl tree */ 4123 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev)); 4124 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child, 4125 OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw"); 4126 if (priv->sysctl_hw == NULL) { 4127 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4128 goto err_free_sysctl; 4129 } 4130 4131 err = mlx5e_build_ifp_priv(mdev, priv, ncv); 4132 if (err) { 4133 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err); 4134 goto err_free_sysctl; 4135 } 4136 4137 snprintf(unit, sizeof(unit), "mce%u_wq", 4138 device_get_unit(mdev->pdev->dev.bsddev)); 4139 priv->wq = alloc_workqueue(unit, 0, 1); 4140 if (priv->wq == NULL) { 4141 if_printf(ifp, "%s: alloc_workqueue failed\n", __func__); 4142 goto err_free_sysctl; 4143 } 4144 4145 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar); 4146 if (err) { 4147 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n", 4148 __func__, err); 4149 goto err_free_wq; 4150 } 4151 err = mlx5_core_alloc_pd(mdev, &priv->pdn); 4152 if (err) { 4153 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n", 4154 __func__, err); 4155 goto err_unmap_free_uar; 4156 } 4157 err = mlx5_alloc_transport_domain(mdev, &priv->tdn); 4158 if (err) { 4159 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n", 4160 __func__, err); 4161 goto err_dealloc_pd; 4162 } 4163 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr); 4164 if (err) { 4165 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n", 4166 __func__, err); 4167 goto err_dealloc_transport_domain; 4168 } 4169 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr); 4170 4171 /* check if we should generate a random MAC address */ 4172 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 && 4173 is_zero_ether_addr(dev_addr)) { 4174 random_ether_addr(dev_addr); 4175 if_printf(ifp, "Assigned random MAC address\n"); 4176 } 4177 #ifdef RATELIMIT 4178 err = mlx5e_rl_init(priv); 4179 if (err) { 4180 if_printf(ifp, "%s: mlx5e_rl_init failed, %d\n", 4181 __func__, err); 4182 goto err_create_mkey; 4183 } 4184 #endif 4185 4186 /* set default MTU */ 4187 mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu); 4188 4189 /* Set default media status */ 4190 priv->media_status_last = IFM_AVALID; 4191 priv->media_active_last = IFM_ETHER | IFM_AUTO | 4192 IFM_ETH_RXPAUSE | IFM_FDX; 4193 4194 /* setup default pauseframes configuration */ 4195 mlx5e_setup_pauseframes(priv); 4196 4197 /* Setup supported medias */ 4198 //TODO: If we failed to query ptys is it ok to proceed?? 4199 if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) { 4200 ext = MLX5_CAP_PCAM_FEATURE(mdev, 4201 ptys_extended_ethernet); 4202 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 4203 eth_proto_capability); 4204 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type)) 4205 connector_type = MLX5_GET(ptys_reg, out, 4206 connector_type); 4207 } else { 4208 eth_proto_cap = 0; 4209 if_printf(ifp, "%s: Query port media capability failed," 4210 " %d\n", __func__, err); 4211 } 4212 4213 ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK, 4214 mlx5e_media_change, mlx5e_media_status); 4215 4216 speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER : MLX5E_LINK_SPEEDS_NUMBER; 4217 for (i = 0; i != speeds_num; i++) { 4218 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) { 4219 media_entry = ext ? mlx5e_ext_mode_table[i][j] : 4220 mlx5e_mode_table[i][j]; 4221 if (media_entry.baudrate == 0) 4222 continue; 4223 if (MLX5E_PROT_MASK(i) & eth_proto_cap) { 4224 ifmedia_add(&priv->media, 4225 media_entry.subtype | 4226 IFM_ETHER, 0, NULL); 4227 ifmedia_add(&priv->media, 4228 media_entry.subtype | 4229 IFM_ETHER | IFM_FDX | 4230 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 4231 } 4232 } 4233 } 4234 4235 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL); 4236 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX | 4237 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 4238 4239 /* Set autoselect by default */ 4240 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX | 4241 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE); 4242 ether_ifattach(ifp, dev_addr); 4243 4244 /* Register for VLAN events */ 4245 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config, 4246 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST); 4247 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig, 4248 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST); 4249 4250 /* Link is down by default */ 4251 if_link_state_change(ifp, LINK_STATE_DOWN); 4252 4253 mlx5e_enable_async_events(priv); 4254 4255 mlx5e_add_hw_stats(priv); 4256 4257 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4258 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM, 4259 priv->stats.vport.arg); 4260 4261 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4262 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM, 4263 priv->stats.pport.arg); 4264 4265 mlx5e_create_ethtool(priv); 4266 4267 mtx_lock(&priv->async_events_mtx); 4268 mlx5e_update_stats(priv); 4269 mtx_unlock(&priv->async_events_mtx); 4270 4271 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4272 OID_AUTO, "rx_clbr_done", CTLFLAG_RD, 4273 &priv->clbr_done, 0, 4274 "RX timestamps calibration state"); 4275 callout_init(&priv->tstmp_clbr, CALLOUT_DIRECT); 4276 mlx5e_reset_calibration_callout(priv); 4277 4278 pa.pa_version = PFIL_VERSION; 4279 pa.pa_flags = PFIL_IN; 4280 pa.pa_type = PFIL_TYPE_ETHERNET; 4281 pa.pa_headname = ifp->if_xname; 4282 priv->pfil = pfil_head_register(&pa); 4283 4284 return (priv); 4285 4286 #ifdef RATELIMIT 4287 err_create_mkey: 4288 mlx5_core_destroy_mkey(priv->mdev, &priv->mr); 4289 #endif 4290 err_dealloc_transport_domain: 4291 mlx5_dealloc_transport_domain(mdev, priv->tdn); 4292 4293 err_dealloc_pd: 4294 mlx5_core_dealloc_pd(mdev, priv->pdn); 4295 4296 err_unmap_free_uar: 4297 mlx5_unmap_free_uar(mdev, &priv->cq_uar); 4298 4299 err_free_wq: 4300 destroy_workqueue(priv->wq); 4301 4302 err_free_sysctl: 4303 sysctl_ctx_free(&priv->sysctl_ctx); 4304 if (priv->sysctl_debug) 4305 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx); 4306 if_free(ifp); 4307 4308 err_free_priv: 4309 mlx5e_priv_mtx_destroy(priv); 4310 free(priv, M_MLX5EN); 4311 return (NULL); 4312 } 4313 4314 static void 4315 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv) 4316 { 4317 struct mlx5e_priv *priv = vpriv; 4318 struct ifnet *ifp = priv->ifp; 4319 4320 /* don't allow more IOCTLs */ 4321 priv->gone = 1; 4322 4323 /* XXX wait a bit to allow IOCTL handlers to complete */ 4324 pause("W", hz); 4325 4326 #ifdef RATELIMIT 4327 /* 4328 * The kernel can have reference(s) via the m_snd_tag's into 4329 * the ratelimit channels, and these must go away before 4330 * detaching: 4331 */ 4332 while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) { 4333 if_printf(priv->ifp, "Waiting for all ratelimit connections " 4334 "to terminate\n"); 4335 pause("W", hz); 4336 } 4337 #endif 4338 /* stop watchdog timer */ 4339 callout_drain(&priv->watchdog); 4340 4341 callout_drain(&priv->tstmp_clbr); 4342 4343 if (priv->vlan_attach != NULL) 4344 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach); 4345 if (priv->vlan_detach != NULL) 4346 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach); 4347 4348 /* make sure device gets closed */ 4349 PRIV_LOCK(priv); 4350 mlx5e_close_locked(ifp); 4351 PRIV_UNLOCK(priv); 4352 4353 /* wait for all unlimited send tags to go away */ 4354 while (priv->channel_refs != 0) { 4355 if_printf(priv->ifp, "Waiting for all unlimited connections " 4356 "to terminate\n"); 4357 pause("W", hz); 4358 } 4359 4360 /* deregister pfil */ 4361 if (priv->pfil != NULL) { 4362 pfil_head_unregister(priv->pfil); 4363 priv->pfil = NULL; 4364 } 4365 4366 /* unregister device */ 4367 ifmedia_removeall(&priv->media); 4368 ether_ifdetach(ifp); 4369 if_free(ifp); 4370 4371 #ifdef RATELIMIT 4372 mlx5e_rl_cleanup(priv); 4373 #endif 4374 /* destroy all remaining sysctl nodes */ 4375 sysctl_ctx_free(&priv->stats.vport.ctx); 4376 sysctl_ctx_free(&priv->stats.pport.ctx); 4377 if (priv->sysctl_debug) 4378 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx); 4379 sysctl_ctx_free(&priv->sysctl_ctx); 4380 4381 mlx5_core_destroy_mkey(priv->mdev, &priv->mr); 4382 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn); 4383 mlx5_core_dealloc_pd(priv->mdev, priv->pdn); 4384 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar); 4385 mlx5e_disable_async_events(priv); 4386 destroy_workqueue(priv->wq); 4387 mlx5e_priv_mtx_destroy(priv); 4388 free(priv, M_MLX5EN); 4389 } 4390 4391 static void * 4392 mlx5e_get_ifp(void *vpriv) 4393 { 4394 struct mlx5e_priv *priv = vpriv; 4395 4396 return (priv->ifp); 4397 } 4398 4399 static struct mlx5_interface mlx5e_interface = { 4400 .add = mlx5e_create_ifp, 4401 .remove = mlx5e_destroy_ifp, 4402 .event = mlx5e_async_event, 4403 .protocol = MLX5_INTERFACE_PROTOCOL_ETH, 4404 .get_dev = mlx5e_get_ifp, 4405 }; 4406 4407 void 4408 mlx5e_init(void) 4409 { 4410 mlx5_register_interface(&mlx5e_interface); 4411 } 4412 4413 void 4414 mlx5e_cleanup(void) 4415 { 4416 mlx5_unregister_interface(&mlx5e_interface); 4417 } 4418 4419 static void 4420 mlx5e_show_version(void __unused *arg) 4421 { 4422 4423 printf("%s", mlx5e_version); 4424 } 4425 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL); 4426 4427 module_init_order(mlx5e_init, SI_ORDER_THIRD); 4428 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD); 4429 4430 #if (__FreeBSD_version >= 1100000) 4431 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1); 4432 #endif 4433 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1); 4434 MODULE_VERSION(mlx5en, 1); 4435