1 /*- 2 * Copyright (c) 2015-2021 Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include "opt_kern_tls.h" 29 30 #include "en.h" 31 32 #include <sys/eventhandler.h> 33 #include <sys/sockio.h> 34 #include <machine/atomic.h> 35 36 #include <net/debugnet.h> 37 38 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs); 39 40 struct mlx5e_channel_param { 41 struct mlx5e_rq_param rq; 42 struct mlx5e_sq_param sq; 43 struct mlx5e_cq_param rx_cq; 44 struct mlx5e_cq_param tx_cq; 45 }; 46 47 struct media { 48 u32 subtype; 49 u64 baudrate; 50 }; 51 52 static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER] = 53 { 54 [MLX5E_1000BASE_CX_SGMII] = { 55 .subtype = IFM_1000_CX_SGMII, 56 .baudrate = IF_Mbps(1000ULL), 57 }, 58 [MLX5E_1000BASE_KX] = { 59 .subtype = IFM_1000_KX, 60 .baudrate = IF_Mbps(1000ULL), 61 }, 62 [MLX5E_10GBASE_CX4] = { 63 .subtype = IFM_10G_CX4, 64 .baudrate = IF_Gbps(10ULL), 65 }, 66 [MLX5E_10GBASE_KX4] = { 67 .subtype = IFM_10G_KX4, 68 .baudrate = IF_Gbps(10ULL), 69 }, 70 [MLX5E_10GBASE_KR] = { 71 .subtype = IFM_10G_KR, 72 .baudrate = IF_Gbps(10ULL), 73 }, 74 [MLX5E_20GBASE_KR2] = { 75 .subtype = IFM_20G_KR2, 76 .baudrate = IF_Gbps(20ULL), 77 }, 78 [MLX5E_40GBASE_CR4] = { 79 .subtype = IFM_40G_CR4, 80 .baudrate = IF_Gbps(40ULL), 81 }, 82 [MLX5E_40GBASE_KR4] = { 83 .subtype = IFM_40G_KR4, 84 .baudrate = IF_Gbps(40ULL), 85 }, 86 [MLX5E_56GBASE_R4] = { 87 .subtype = IFM_56G_R4, 88 .baudrate = IF_Gbps(56ULL), 89 }, 90 [MLX5E_10GBASE_CR] = { 91 .subtype = IFM_10G_CR1, 92 .baudrate = IF_Gbps(10ULL), 93 }, 94 [MLX5E_10GBASE_SR] = { 95 .subtype = IFM_10G_SR, 96 .baudrate = IF_Gbps(10ULL), 97 }, 98 [MLX5E_10GBASE_ER_LR] = { 99 .subtype = IFM_10G_ER, 100 .baudrate = IF_Gbps(10ULL), 101 }, 102 [MLX5E_40GBASE_SR4] = { 103 .subtype = IFM_40G_SR4, 104 .baudrate = IF_Gbps(40ULL), 105 }, 106 [MLX5E_40GBASE_LR4_ER4] = { 107 .subtype = IFM_40G_LR4, 108 .baudrate = IF_Gbps(40ULL), 109 }, 110 [MLX5E_100GBASE_CR4] = { 111 .subtype = IFM_100G_CR4, 112 .baudrate = IF_Gbps(100ULL), 113 }, 114 [MLX5E_100GBASE_SR4] = { 115 .subtype = IFM_100G_SR4, 116 .baudrate = IF_Gbps(100ULL), 117 }, 118 [MLX5E_100GBASE_KR4] = { 119 .subtype = IFM_100G_KR4, 120 .baudrate = IF_Gbps(100ULL), 121 }, 122 [MLX5E_100GBASE_LR4] = { 123 .subtype = IFM_100G_LR4, 124 .baudrate = IF_Gbps(100ULL), 125 }, 126 [MLX5E_100BASE_TX] = { 127 .subtype = IFM_100_TX, 128 .baudrate = IF_Mbps(100ULL), 129 }, 130 [MLX5E_1000BASE_T] = { 131 .subtype = IFM_1000_T, 132 .baudrate = IF_Mbps(1000ULL), 133 }, 134 [MLX5E_10GBASE_T] = { 135 .subtype = IFM_10G_T, 136 .baudrate = IF_Gbps(10ULL), 137 }, 138 [MLX5E_25GBASE_CR] = { 139 .subtype = IFM_25G_CR, 140 .baudrate = IF_Gbps(25ULL), 141 }, 142 [MLX5E_25GBASE_KR] = { 143 .subtype = IFM_25G_KR, 144 .baudrate = IF_Gbps(25ULL), 145 }, 146 [MLX5E_25GBASE_SR] = { 147 .subtype = IFM_25G_SR, 148 .baudrate = IF_Gbps(25ULL), 149 }, 150 [MLX5E_50GBASE_CR2] = { 151 .subtype = IFM_50G_CR2, 152 .baudrate = IF_Gbps(50ULL), 153 }, 154 [MLX5E_50GBASE_KR2] = { 155 .subtype = IFM_50G_KR2, 156 .baudrate = IF_Gbps(50ULL), 157 }, 158 [MLX5E_50GBASE_KR4] = { 159 .subtype = IFM_50G_KR4, 160 .baudrate = IF_Gbps(50ULL), 161 }, 162 }; 163 164 static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_CABLE_TYPE_NUMBER] = 165 { 166 /**/ 167 [MLX5E_SGMII_100M][MLX5E_CABLE_TYPE_UNKNOWN] = { 168 .subtype = IFM_100_SGMII, 169 .baudrate = IF_Mbps(100), 170 }, 171 172 /**/ 173 [MLX5E_1000BASE_X_SGMII][MLX5E_CABLE_TYPE_UNKNOWN] = { 174 .subtype = IFM_1000_CX, 175 .baudrate = IF_Mbps(1000), 176 }, 177 [MLX5E_1000BASE_X_SGMII][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 178 .subtype = IFM_1000_SX, 179 .baudrate = IF_Mbps(1000), 180 }, 181 182 /**/ 183 [MLX5E_5GBASE_R][MLX5E_CABLE_TYPE_UNKNOWN] = { 184 .subtype = IFM_5000_KR, 185 .baudrate = IF_Mbps(5000), 186 }, 187 [MLX5E_5GBASE_R][MLX5E_CABLE_TYPE_TWISTED_PAIR] = { 188 .subtype = IFM_5000_T, 189 .baudrate = IF_Mbps(5000), 190 }, 191 192 /**/ 193 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CABLE_TYPE_UNKNOWN] = { 194 .subtype = IFM_10G_KR, 195 .baudrate = IF_Gbps(10ULL), 196 }, 197 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 198 .subtype = IFM_10G_CR1, 199 .baudrate = IF_Gbps(10ULL), 200 }, 201 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 202 .subtype = IFM_10G_SR, 203 .baudrate = IF_Gbps(10ULL), 204 }, 205 206 /**/ 207 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CABLE_TYPE_UNKNOWN] = { 208 .subtype = IFM_40G_KR4, 209 .baudrate = IF_Gbps(40ULL), 210 }, 211 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 212 .subtype = IFM_40G_CR4, 213 .baudrate = IF_Gbps(40ULL), 214 }, 215 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 216 .subtype = IFM_40G_SR4, 217 .baudrate = IF_Gbps(40ULL), 218 }, 219 220 /**/ 221 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_UNKNOWN] = { 222 .subtype = IFM_25G_KR, 223 .baudrate = IF_Gbps(25ULL), 224 }, 225 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 226 .subtype = IFM_25G_CR, 227 .baudrate = IF_Gbps(25ULL), 228 }, 229 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 230 .subtype = IFM_25G_SR, 231 .baudrate = IF_Gbps(25ULL), 232 }, 233 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_TWISTED_PAIR] = { 234 .subtype = IFM_25G_T, 235 .baudrate = IF_Gbps(25ULL), 236 }, 237 238 /**/ 239 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CABLE_TYPE_UNKNOWN] = { 240 .subtype = IFM_50G_KR2, 241 .baudrate = IF_Gbps(50ULL), 242 }, 243 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 244 .subtype = IFM_50G_CR2, 245 .baudrate = IF_Gbps(50ULL), 246 }, 247 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 248 .subtype = IFM_50G_SR2, 249 .baudrate = IF_Gbps(50ULL), 250 }, 251 252 /**/ 253 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CABLE_TYPE_UNKNOWN] = { 254 .subtype = IFM_50G_KR_PAM4, 255 .baudrate = IF_Gbps(50ULL), 256 }, 257 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 258 .subtype = IFM_50G_CP, 259 .baudrate = IF_Gbps(50ULL), 260 }, 261 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 262 .subtype = IFM_50G_SR, 263 .baudrate = IF_Gbps(50ULL), 264 }, 265 266 /**/ 267 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CABLE_TYPE_UNKNOWN] = { 268 .subtype = IFM_100G_KR4, 269 .baudrate = IF_Gbps(100ULL), 270 }, 271 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 272 .subtype = IFM_100G_CR4, 273 .baudrate = IF_Gbps(100ULL), 274 }, 275 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 276 .subtype = IFM_100G_SR4, 277 .baudrate = IF_Gbps(100ULL), 278 }, 279 280 /**/ 281 [MLX5E_100GAUI_1_100GBASE_CR_KR][MLX5E_CABLE_TYPE_UNKNOWN] = { 282 .subtype = IFM_100G_KR_PAM4, 283 .baudrate = IF_Gbps(100ULL), 284 }, 285 [MLX5E_100GAUI_1_100GBASE_CR_KR][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 286 .subtype = IFM_100G_CR_PAM4, 287 .baudrate = IF_Gbps(100ULL), 288 }, 289 [MLX5E_100GAUI_1_100GBASE_CR_KR][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 290 .subtype = IFM_100G_SR2, /* XXX */ 291 .baudrate = IF_Gbps(100ULL), 292 }, 293 294 /**/ 295 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CABLE_TYPE_UNKNOWN] = { 296 .subtype = IFM_100G_KR4, 297 .baudrate = IF_Gbps(100ULL), 298 }, 299 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 300 .subtype = IFM_100G_CP2, 301 .baudrate = IF_Gbps(100ULL), 302 }, 303 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 304 .subtype = IFM_100G_SR2, 305 .baudrate = IF_Gbps(100ULL), 306 }, 307 308 /**/ 309 [MLX5E_200GAUI_2_200GBASE_CR2_KR2][MLX5E_CABLE_TYPE_UNKNOWN] = { 310 .subtype = IFM_200G_KR4_PAM4, /* XXX */ 311 .baudrate = IF_Gbps(200ULL), 312 }, 313 [MLX5E_200GAUI_2_200GBASE_CR2_KR2][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 314 .subtype = IFM_200G_CR4_PAM4, /* XXX */ 315 .baudrate = IF_Gbps(200ULL), 316 }, 317 [MLX5E_200GAUI_2_200GBASE_CR2_KR2][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 318 .subtype = IFM_200G_SR4, /* XXX */ 319 .baudrate = IF_Gbps(200ULL), 320 }, 321 322 /**/ 323 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CABLE_TYPE_UNKNOWN] = { 324 .subtype = IFM_200G_KR4_PAM4, 325 .baudrate = IF_Gbps(200ULL), 326 }, 327 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 328 .subtype = IFM_200G_CR4_PAM4, 329 .baudrate = IF_Gbps(200ULL), 330 }, 331 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 332 .subtype = IFM_200G_SR4, 333 .baudrate = IF_Gbps(200ULL), 334 }, 335 336 /**/ 337 [MLX5E_400GAUI_8][MLX5E_CABLE_TYPE_UNKNOWN] = { 338 .subtype = IFM_400G_LR8, /* XXX */ 339 .baudrate = IF_Gbps(400ULL), 340 }, 341 342 /**/ 343 [MLX5E_400GAUI_4_400GBASE_CR4_KR4][MLX5E_CABLE_TYPE_UNKNOWN] = { 344 .subtype = IFM_400G_LR8, /* XXX */ 345 .baudrate = IF_Gbps(400ULL), 346 }, 347 }; 348 349 DEBUGNET_DEFINE(mlx5_en); 350 351 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet"); 352 353 static void 354 mlx5e_update_carrier(struct mlx5e_priv *priv) 355 { 356 struct mlx5_core_dev *mdev = priv->mdev; 357 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 358 u32 eth_proto_oper; 359 int error; 360 u8 i; 361 u8 cable_type; 362 u8 port_state; 363 u8 is_er_type; 364 bool ext; 365 struct media media_entry = {}; 366 367 port_state = mlx5_query_vport_state(mdev, 368 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0); 369 370 if (port_state == VPORT_STATE_UP) { 371 priv->media_status_last |= IFM_ACTIVE; 372 } else { 373 priv->media_status_last &= ~IFM_ACTIVE; 374 priv->media_active_last = IFM_ETHER; 375 if_link_state_change(priv->ifp, LINK_STATE_DOWN); 376 return; 377 } 378 379 error = mlx5_query_port_ptys(mdev, out, sizeof(out), 380 MLX5_PTYS_EN, 1); 381 if (error) { 382 priv->media_active_last = IFM_ETHER; 383 priv->ifp->if_baudrate = 1; 384 mlx5_en_err(priv->ifp, "query port ptys failed: 0x%x\n", 385 error); 386 return; 387 } 388 389 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet); 390 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 391 eth_proto_oper); 392 393 i = ilog2(eth_proto_oper); 394 395 if (ext) { 396 error = mlx5_query_pddr_cable_type(mdev, 1, &cable_type); 397 if (error != 0) { 398 /* use fallback entry */ 399 media_entry = mlx5e_ext_mode_table[i][MLX5E_CABLE_TYPE_UNKNOWN]; 400 401 mlx5_en_err(priv->ifp, 402 "query port pddr failed: %d\n", error); 403 } else { 404 media_entry = mlx5e_ext_mode_table[i][cable_type]; 405 406 /* check if we should use fallback entry */ 407 if (media_entry.subtype == 0) 408 media_entry = mlx5e_ext_mode_table[i][MLX5E_CABLE_TYPE_UNKNOWN]; 409 } 410 } else { 411 media_entry = mlx5e_mode_table[i]; 412 } 413 414 if (media_entry.subtype == 0) { 415 mlx5_en_err(priv->ifp, 416 "Could not find operational media subtype\n"); 417 return; 418 } 419 420 switch (media_entry.subtype) { 421 case IFM_10G_ER: 422 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type); 423 if (error != 0) { 424 mlx5_en_err(priv->ifp, 425 "query port pddr failed: %d\n", error); 426 } 427 if (error != 0 || is_er_type == 0) 428 media_entry.subtype = IFM_10G_LR; 429 break; 430 case IFM_40G_LR4: 431 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type); 432 if (error != 0) { 433 mlx5_en_err(priv->ifp, 434 "query port pddr failed: %d\n", error); 435 } 436 if (error == 0 && is_er_type != 0) 437 media_entry.subtype = IFM_40G_ER4; 438 break; 439 } 440 priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX; 441 priv->ifp->if_baudrate = media_entry.baudrate; 442 443 if_link_state_change(priv->ifp, LINK_STATE_UP); 444 } 445 446 static void 447 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr) 448 { 449 struct mlx5e_priv *priv = dev->if_softc; 450 451 ifmr->ifm_status = priv->media_status_last; 452 ifmr->ifm_current = ifmr->ifm_active = priv->media_active_last | 453 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) | 454 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0); 455 456 } 457 458 static u32 459 mlx5e_find_link_mode(u32 subtype, bool ext) 460 { 461 u32 link_mode = 0; 462 463 switch (subtype) { 464 case 0: 465 goto done; 466 case IFM_10G_LR: 467 subtype = IFM_10G_ER; 468 break; 469 case IFM_40G_ER4: 470 subtype = IFM_40G_LR4; 471 break; 472 default: 473 break; 474 } 475 476 if (ext) { 477 for (unsigned i = 0; i != MLX5E_EXT_LINK_SPEEDS_NUMBER; i++) { 478 for (unsigned j = 0; j != MLX5E_CABLE_TYPE_NUMBER; j++) { 479 if (mlx5e_ext_mode_table[i][j].subtype == subtype) 480 link_mode |= MLX5E_PROT_MASK(i); 481 } 482 } 483 } else { 484 for (unsigned i = 0; i != MLX5E_LINK_SPEEDS_NUMBER; i++) { 485 if (mlx5e_mode_table[i].subtype == subtype) 486 link_mode |= MLX5E_PROT_MASK(i); 487 } 488 } 489 done: 490 return (link_mode); 491 } 492 493 static int 494 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv) 495 { 496 return (mlx5_set_port_pause_and_pfc(priv->mdev, 1, 497 priv->params.rx_pauseframe_control, 498 priv->params.tx_pauseframe_control, 499 priv->params.rx_priority_flow_control, 500 priv->params.tx_priority_flow_control)); 501 } 502 503 static int 504 mlx5e_set_port_pfc(struct mlx5e_priv *priv) 505 { 506 int error; 507 508 if (priv->gone != 0) { 509 error = -ENXIO; 510 } else if (priv->params.rx_pauseframe_control || 511 priv->params.tx_pauseframe_control) { 512 mlx5_en_err(priv->ifp, 513 "Global pauseframes must be disabled before enabling PFC.\n"); 514 error = -EINVAL; 515 } else { 516 error = mlx5e_set_port_pause_and_pfc(priv); 517 } 518 return (error); 519 } 520 521 static int 522 mlx5e_media_change(struct ifnet *dev) 523 { 524 struct mlx5e_priv *priv = dev->if_softc; 525 struct mlx5_core_dev *mdev = priv->mdev; 526 u32 eth_proto_cap; 527 u32 link_mode; 528 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 529 int was_opened; 530 int locked; 531 int error; 532 bool ext; 533 534 locked = PRIV_LOCKED(priv); 535 if (!locked) 536 PRIV_LOCK(priv); 537 538 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) { 539 error = EINVAL; 540 goto done; 541 } 542 543 error = mlx5_query_port_ptys(mdev, out, sizeof(out), 544 MLX5_PTYS_EN, 1); 545 if (error != 0) { 546 mlx5_en_err(dev, "Query port media capability failed\n"); 547 goto done; 548 } 549 550 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet); 551 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext); 552 553 /* query supported capabilities */ 554 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 555 eth_proto_capability); 556 557 /* check for autoselect */ 558 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) { 559 link_mode = eth_proto_cap; 560 if (link_mode == 0) { 561 mlx5_en_err(dev, "Port media capability is zero\n"); 562 error = EINVAL; 563 goto done; 564 } 565 } else { 566 link_mode = link_mode & eth_proto_cap; 567 if (link_mode == 0) { 568 mlx5_en_err(dev, "Not supported link mode requested\n"); 569 error = EINVAL; 570 goto done; 571 } 572 } 573 if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) { 574 /* check if PFC is enabled */ 575 if (priv->params.rx_priority_flow_control || 576 priv->params.tx_priority_flow_control) { 577 mlx5_en_err(dev, "PFC must be disabled before enabling global pauseframes.\n"); 578 error = EINVAL; 579 goto done; 580 } 581 } 582 /* update pauseframe control bits */ 583 priv->params.rx_pauseframe_control = 584 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0; 585 priv->params.tx_pauseframe_control = 586 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0; 587 588 /* check if device is opened */ 589 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 590 591 /* reconfigure the hardware */ 592 mlx5_set_port_status(mdev, MLX5_PORT_DOWN); 593 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext); 594 error = -mlx5e_set_port_pause_and_pfc(priv); 595 if (was_opened) 596 mlx5_set_port_status(mdev, MLX5_PORT_UP); 597 598 done: 599 if (!locked) 600 PRIV_UNLOCK(priv); 601 return (error); 602 } 603 604 static void 605 mlx5e_update_carrier_work(struct work_struct *work) 606 { 607 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 608 update_carrier_work); 609 610 PRIV_LOCK(priv); 611 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) 612 mlx5e_update_carrier(priv); 613 PRIV_UNLOCK(priv); 614 } 615 616 #define MLX5E_PCIE_PERF_GET_64(a,b,c,d,e,f) \ 617 s_debug->c = MLX5_GET64(mpcnt_reg, out, counter_set.f.c); 618 619 #define MLX5E_PCIE_PERF_GET_32(a,b,c,d,e,f) \ 620 s_debug->c = MLX5_GET(mpcnt_reg, out, counter_set.f.c); 621 622 static void 623 mlx5e_update_pcie_counters(struct mlx5e_priv *priv) 624 { 625 struct mlx5_core_dev *mdev = priv->mdev; 626 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug; 627 const unsigned sz = MLX5_ST_SZ_BYTES(mpcnt_reg); 628 void *out; 629 void *in; 630 int err; 631 632 /* allocate firmware request structures */ 633 in = mlx5_vzalloc(sz); 634 out = mlx5_vzalloc(sz); 635 if (in == NULL || out == NULL) 636 goto free_out; 637 638 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP); 639 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 640 if (err != 0) 641 goto free_out; 642 643 MLX5E_PCIE_PERFORMANCE_COUNTERS_64(MLX5E_PCIE_PERF_GET_64) 644 MLX5E_PCIE_PERFORMANCE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 645 646 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP); 647 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 648 if (err != 0) 649 goto free_out; 650 651 MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 652 653 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_LANE_COUNTERS_GROUP); 654 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 655 if (err != 0) 656 goto free_out; 657 658 MLX5E_PCIE_LANE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 659 660 free_out: 661 /* free firmware request structures */ 662 kvfree(in); 663 kvfree(out); 664 } 665 666 /* 667 * This function reads the physical port counters from the firmware 668 * using a pre-defined layout defined by various MLX5E_PPORT_XXX() 669 * macros. The output is converted from big-endian 64-bit values into 670 * host endian ones and stored in the "priv->stats.pport" structure. 671 */ 672 static void 673 mlx5e_update_pport_counters(struct mlx5e_priv *priv) 674 { 675 struct mlx5_core_dev *mdev = priv->mdev; 676 struct mlx5e_pport_stats *s = &priv->stats.pport; 677 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug; 678 u32 *in; 679 u32 *out; 680 const u64 *ptr; 681 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 682 unsigned x; 683 unsigned y; 684 unsigned z; 685 686 /* allocate firmware request structures */ 687 in = mlx5_vzalloc(sz); 688 out = mlx5_vzalloc(sz); 689 if (in == NULL || out == NULL) 690 goto free_out; 691 692 /* 693 * Get pointer to the 64-bit counter set which is located at a 694 * fixed offset in the output firmware request structure: 695 */ 696 ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set); 697 698 MLX5_SET(ppcnt_reg, in, local_port, 1); 699 700 /* read IEEE802_3 counter group using predefined counter layout */ 701 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP); 702 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 703 for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM; 704 x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++) 705 s->arg[y] = be64toh(ptr[x]); 706 707 /* read RFC2819 counter group using predefined counter layout */ 708 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP); 709 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 710 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++) 711 s->arg[y] = be64toh(ptr[x]); 712 713 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM + 714 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++) 715 s_debug->arg[y] = be64toh(ptr[x]); 716 717 /* read RFC2863 counter group using predefined counter layout */ 718 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP); 719 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 720 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++) 721 s_debug->arg[y] = be64toh(ptr[x]); 722 723 /* read physical layer stats counter group using predefined counter layout */ 724 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP); 725 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 726 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++) 727 s_debug->arg[y] = be64toh(ptr[x]); 728 729 /* read Extended Ethernet counter group using predefined counter layout */ 730 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP); 731 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 732 for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++) 733 s_debug->arg[y] = be64toh(ptr[x]); 734 735 /* read Extended Statistical Group */ 736 if (MLX5_CAP_GEN(mdev, pcam_reg) && 737 MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) && 738 MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) { 739 /* read Extended Statistical counter group using predefined counter layout */ 740 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP); 741 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 742 743 for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++) 744 s_debug->arg[y] = be64toh(ptr[x]); 745 } 746 747 /* read PCIE counters */ 748 mlx5e_update_pcie_counters(priv); 749 750 /* read per-priority counters */ 751 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP); 752 753 /* iterate all the priorities */ 754 for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) { 755 MLX5_SET(ppcnt_reg, in, prio_tc, z); 756 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 757 758 /* read per priority stats counter group using predefined counter layout */ 759 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM / 760 MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++) 761 s->arg[y] = be64toh(ptr[x]); 762 } 763 764 free_out: 765 /* free firmware request structures */ 766 kvfree(in); 767 kvfree(out); 768 } 769 770 static void 771 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv) 772 { 773 u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {}; 774 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {}; 775 776 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard)) 777 return; 778 779 MLX5_SET(query_vnic_env_in, in, opcode, 780 MLX5_CMD_OP_QUERY_VNIC_ENV); 781 MLX5_SET(query_vnic_env_in, in, op_mod, 0); 782 MLX5_SET(query_vnic_env_in, in, other_vport, 0); 783 784 if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0) 785 return; 786 787 priv->stats.vport.rx_steer_missed_packets = 788 MLX5_GET64(query_vnic_env_out, out, 789 vport_env.nic_receive_steering_discard); 790 } 791 792 /* 793 * This function is called regularly to collect all statistics 794 * counters from the firmware. The values can be viewed through the 795 * sysctl interface. Execution is serialized using the priv's global 796 * configuration lock. 797 */ 798 static void 799 mlx5e_update_stats_locked(struct mlx5e_priv *priv) 800 { 801 struct mlx5_core_dev *mdev = priv->mdev; 802 struct mlx5e_vport_stats *s = &priv->stats.vport; 803 struct mlx5e_sq_stats *sq_stats; 804 #if (__FreeBSD_version < 1100000) 805 struct ifnet *ifp = priv->ifp; 806 #endif 807 808 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)]; 809 u32 *out; 810 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out); 811 u64 tso_packets = 0; 812 u64 tso_bytes = 0; 813 u64 tx_queue_dropped = 0; 814 u64 tx_defragged = 0; 815 u64 tx_offload_none = 0; 816 u64 lro_packets = 0; 817 u64 lro_bytes = 0; 818 u64 sw_lro_queued = 0; 819 u64 sw_lro_flushed = 0; 820 u64 rx_csum_none = 0; 821 u64 rx_wqe_err = 0; 822 u64 rx_packets = 0; 823 u64 rx_bytes = 0; 824 u32 rx_out_of_buffer = 0; 825 int error; 826 int i; 827 int j; 828 829 out = mlx5_vzalloc(outlen); 830 if (out == NULL) 831 goto free_out; 832 833 /* Collect firts the SW counters and then HW for consistency */ 834 for (i = 0; i < priv->params.num_channels; i++) { 835 struct mlx5e_channel *pch = priv->channel + i; 836 struct mlx5e_rq *rq = &pch->rq; 837 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats; 838 839 /* collect stats from LRO */ 840 rq_stats->sw_lro_queued = rq->lro.lro_queued; 841 rq_stats->sw_lro_flushed = rq->lro.lro_flushed; 842 sw_lro_queued += rq_stats->sw_lro_queued; 843 sw_lro_flushed += rq_stats->sw_lro_flushed; 844 lro_packets += rq_stats->lro_packets; 845 lro_bytes += rq_stats->lro_bytes; 846 rx_csum_none += rq_stats->csum_none; 847 rx_wqe_err += rq_stats->wqe_err; 848 rx_packets += rq_stats->packets; 849 rx_bytes += rq_stats->bytes; 850 851 for (j = 0; j < priv->num_tc; j++) { 852 sq_stats = &pch->sq[j].stats; 853 854 tso_packets += sq_stats->tso_packets; 855 tso_bytes += sq_stats->tso_bytes; 856 tx_queue_dropped += sq_stats->dropped; 857 tx_queue_dropped += sq_stats->enobuf; 858 tx_defragged += sq_stats->defragged; 859 tx_offload_none += sq_stats->csum_offload_none; 860 } 861 } 862 863 #ifdef RATELIMIT 864 /* Collect statistics from all rate-limit queues */ 865 for (j = 0; j < priv->rl.param.tx_worker_threads_def; j++) { 866 struct mlx5e_rl_worker *rlw = priv->rl.workers + j; 867 868 for (i = 0; i < priv->rl.param.tx_channels_per_worker_def; i++) { 869 struct mlx5e_rl_channel *channel = rlw->channels + i; 870 struct mlx5e_sq *sq = channel->sq; 871 872 if (sq == NULL) 873 continue; 874 875 sq_stats = &sq->stats; 876 877 tso_packets += sq_stats->tso_packets; 878 tso_bytes += sq_stats->tso_bytes; 879 tx_queue_dropped += sq_stats->dropped; 880 tx_queue_dropped += sq_stats->enobuf; 881 tx_defragged += sq_stats->defragged; 882 tx_offload_none += sq_stats->csum_offload_none; 883 } 884 } 885 #endif 886 887 /* update counters */ 888 s->tso_packets = tso_packets; 889 s->tso_bytes = tso_bytes; 890 s->tx_queue_dropped = tx_queue_dropped; 891 s->tx_defragged = tx_defragged; 892 s->lro_packets = lro_packets; 893 s->lro_bytes = lro_bytes; 894 s->sw_lro_queued = sw_lro_queued; 895 s->sw_lro_flushed = sw_lro_flushed; 896 s->rx_csum_none = rx_csum_none; 897 s->rx_wqe_err = rx_wqe_err; 898 s->rx_packets = rx_packets; 899 s->rx_bytes = rx_bytes; 900 901 mlx5e_grp_vnic_env_update_stats(priv); 902 903 /* HW counters */ 904 memset(in, 0, sizeof(in)); 905 906 MLX5_SET(query_vport_counter_in, in, opcode, 907 MLX5_CMD_OP_QUERY_VPORT_COUNTER); 908 MLX5_SET(query_vport_counter_in, in, op_mod, 0); 909 MLX5_SET(query_vport_counter_in, in, other_vport, 0); 910 911 memset(out, 0, outlen); 912 913 /* get number of out-of-buffer drops first */ 914 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 && 915 mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id, 916 &rx_out_of_buffer) == 0) { 917 s->rx_out_of_buffer = rx_out_of_buffer; 918 } 919 920 /* get port statistics */ 921 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) { 922 #define MLX5_GET_CTR(out, x) \ 923 MLX5_GET64(query_vport_counter_out, out, x) 924 925 s->rx_error_packets = 926 MLX5_GET_CTR(out, received_errors.packets); 927 s->rx_error_bytes = 928 MLX5_GET_CTR(out, received_errors.octets); 929 s->tx_error_packets = 930 MLX5_GET_CTR(out, transmit_errors.packets); 931 s->tx_error_bytes = 932 MLX5_GET_CTR(out, transmit_errors.octets); 933 934 s->rx_unicast_packets = 935 MLX5_GET_CTR(out, received_eth_unicast.packets); 936 s->rx_unicast_bytes = 937 MLX5_GET_CTR(out, received_eth_unicast.octets); 938 s->tx_unicast_packets = 939 MLX5_GET_CTR(out, transmitted_eth_unicast.packets); 940 s->tx_unicast_bytes = 941 MLX5_GET_CTR(out, transmitted_eth_unicast.octets); 942 943 s->rx_multicast_packets = 944 MLX5_GET_CTR(out, received_eth_multicast.packets); 945 s->rx_multicast_bytes = 946 MLX5_GET_CTR(out, received_eth_multicast.octets); 947 s->tx_multicast_packets = 948 MLX5_GET_CTR(out, transmitted_eth_multicast.packets); 949 s->tx_multicast_bytes = 950 MLX5_GET_CTR(out, transmitted_eth_multicast.octets); 951 952 s->rx_broadcast_packets = 953 MLX5_GET_CTR(out, received_eth_broadcast.packets); 954 s->rx_broadcast_bytes = 955 MLX5_GET_CTR(out, received_eth_broadcast.octets); 956 s->tx_broadcast_packets = 957 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets); 958 s->tx_broadcast_bytes = 959 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets); 960 961 s->tx_packets = s->tx_unicast_packets + 962 s->tx_multicast_packets + s->tx_broadcast_packets; 963 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes + 964 s->tx_broadcast_bytes; 965 966 /* Update calculated offload counters */ 967 s->tx_csum_offload = s->tx_packets - tx_offload_none; 968 s->rx_csum_good = s->rx_packets - s->rx_csum_none; 969 } 970 971 /* Get physical port counters */ 972 mlx5e_update_pport_counters(priv); 973 974 s->tx_jumbo_packets = 975 priv->stats.port_stats_debug.tx_stat_p1519to2047octets + 976 priv->stats.port_stats_debug.tx_stat_p2048to4095octets + 977 priv->stats.port_stats_debug.tx_stat_p4096to8191octets + 978 priv->stats.port_stats_debug.tx_stat_p8192to10239octets; 979 980 #if (__FreeBSD_version < 1100000) 981 /* no get_counters interface in fbsd 10 */ 982 ifp->if_ipackets = s->rx_packets; 983 ifp->if_ierrors = priv->stats.pport.in_range_len_errors + 984 priv->stats.pport.out_of_range_len + 985 priv->stats.pport.too_long_errors + 986 priv->stats.pport.check_seq_err + 987 priv->stats.pport.alignment_err; 988 ifp->if_iqdrops = s->rx_out_of_buffer; 989 ifp->if_opackets = s->tx_packets; 990 ifp->if_oerrors = priv->stats.port_stats_debug.out_discards; 991 ifp->if_snd.ifq_drops = s->tx_queue_dropped; 992 ifp->if_ibytes = s->rx_bytes; 993 ifp->if_obytes = s->tx_bytes; 994 ifp->if_collisions = 995 priv->stats.pport.collisions; 996 #endif 997 998 free_out: 999 kvfree(out); 1000 1001 /* Update diagnostics, if any */ 1002 if (priv->params_ethtool.diag_pci_enable || 1003 priv->params_ethtool.diag_general_enable) { 1004 error = mlx5_core_get_diagnostics_full(mdev, 1005 priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL, 1006 priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL); 1007 if (error != 0) 1008 mlx5_en_err(priv->ifp, 1009 "Failed reading diagnostics: %d\n", error); 1010 } 1011 1012 /* Update FEC, if any */ 1013 error = mlx5e_fec_update(priv); 1014 if (error != 0 && error != EOPNOTSUPP) { 1015 mlx5_en_err(priv->ifp, 1016 "Updating FEC failed: %d\n", error); 1017 } 1018 1019 /* Update temperature, if any */ 1020 if (priv->params_ethtool.hw_num_temp != 0) { 1021 error = mlx5e_hw_temperature_update(priv); 1022 if (error != 0 && error != EOPNOTSUPP) { 1023 mlx5_en_err(priv->ifp, 1024 "Updating temperature failed: %d\n", error); 1025 } 1026 } 1027 } 1028 1029 static void 1030 mlx5e_update_stats_work(struct work_struct *work) 1031 { 1032 struct mlx5e_priv *priv; 1033 1034 priv = container_of(work, struct mlx5e_priv, update_stats_work); 1035 PRIV_LOCK(priv); 1036 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 && 1037 !test_bit(MLX5_INTERFACE_STATE_TEARDOWN, &priv->mdev->intf_state)) 1038 mlx5e_update_stats_locked(priv); 1039 PRIV_UNLOCK(priv); 1040 } 1041 1042 static void 1043 mlx5e_update_stats(void *arg) 1044 { 1045 struct mlx5e_priv *priv = arg; 1046 1047 queue_work(priv->wq, &priv->update_stats_work); 1048 1049 callout_reset(&priv->watchdog, hz / 4, &mlx5e_update_stats, priv); 1050 } 1051 1052 static void 1053 mlx5e_async_event_sub(struct mlx5e_priv *priv, 1054 enum mlx5_dev_event event) 1055 { 1056 switch (event) { 1057 case MLX5_DEV_EVENT_PORT_UP: 1058 case MLX5_DEV_EVENT_PORT_DOWN: 1059 queue_work(priv->wq, &priv->update_carrier_work); 1060 break; 1061 1062 default: 1063 break; 1064 } 1065 } 1066 1067 static void 1068 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv, 1069 enum mlx5_dev_event event, unsigned long param) 1070 { 1071 struct mlx5e_priv *priv = vpriv; 1072 1073 mtx_lock(&priv->async_events_mtx); 1074 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state)) 1075 mlx5e_async_event_sub(priv, event); 1076 mtx_unlock(&priv->async_events_mtx); 1077 } 1078 1079 static void 1080 mlx5e_enable_async_events(struct mlx5e_priv *priv) 1081 { 1082 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 1083 } 1084 1085 static void 1086 mlx5e_disable_async_events(struct mlx5e_priv *priv) 1087 { 1088 mtx_lock(&priv->async_events_mtx); 1089 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 1090 mtx_unlock(&priv->async_events_mtx); 1091 } 1092 1093 static void mlx5e_calibration_callout(void *arg); 1094 static int mlx5e_calibration_duration = 20; 1095 static int mlx5e_fast_calibration = 1; 1096 static int mlx5e_normal_calibration = 30; 1097 1098 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 1099 "MLX5 timestamp calibration parameteres"); 1100 1101 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN, 1102 &mlx5e_calibration_duration, 0, 1103 "Duration of initial calibration"); 1104 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN, 1105 &mlx5e_fast_calibration, 0, 1106 "Recalibration interval during initial calibration"); 1107 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN, 1108 &mlx5e_normal_calibration, 0, 1109 "Recalibration interval during normal operations"); 1110 1111 /* 1112 * Ignites the calibration process. 1113 */ 1114 static void 1115 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv) 1116 { 1117 1118 if (priv->clbr_done == 0) 1119 mlx5e_calibration_callout(priv); 1120 else 1121 callout_reset_curcpu(&priv->tstmp_clbr, (priv->clbr_done < 1122 mlx5e_calibration_duration ? mlx5e_fast_calibration : 1123 mlx5e_normal_calibration) * hz, mlx5e_calibration_callout, 1124 priv); 1125 } 1126 1127 static uint64_t 1128 mlx5e_timespec2usec(const struct timespec *ts) 1129 { 1130 1131 return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec); 1132 } 1133 1134 static uint64_t 1135 mlx5e_hw_clock(struct mlx5e_priv *priv) 1136 { 1137 struct mlx5_init_seg *iseg; 1138 uint32_t hw_h, hw_h1, hw_l; 1139 1140 iseg = priv->mdev->iseg; 1141 do { 1142 hw_h = ioread32be(&iseg->internal_timer_h); 1143 hw_l = ioread32be(&iseg->internal_timer_l); 1144 hw_h1 = ioread32be(&iseg->internal_timer_h); 1145 } while (hw_h1 != hw_h); 1146 return (((uint64_t)hw_h << 32) | hw_l); 1147 } 1148 1149 /* 1150 * The calibration callout, it runs either in the context of the 1151 * thread which enables calibration, or in callout. It takes the 1152 * snapshot of system and adapter clocks, then advances the pointers to 1153 * the calibration point to allow rx path to read the consistent data 1154 * lockless. 1155 */ 1156 static void 1157 mlx5e_calibration_callout(void *arg) 1158 { 1159 struct mlx5e_priv *priv; 1160 struct mlx5e_clbr_point *next, *curr; 1161 struct timespec ts; 1162 int clbr_curr_next; 1163 1164 priv = arg; 1165 curr = &priv->clbr_points[priv->clbr_curr]; 1166 clbr_curr_next = priv->clbr_curr + 1; 1167 if (clbr_curr_next >= nitems(priv->clbr_points)) 1168 clbr_curr_next = 0; 1169 next = &priv->clbr_points[clbr_curr_next]; 1170 1171 next->base_prev = curr->base_curr; 1172 next->clbr_hw_prev = curr->clbr_hw_curr; 1173 1174 next->clbr_hw_curr = mlx5e_hw_clock(priv); 1175 if (((next->clbr_hw_curr - curr->clbr_hw_curr) >> MLX5E_TSTMP_PREC) == 1176 0) { 1177 if (priv->clbr_done != 0) { 1178 mlx5_en_err(priv->ifp, 1179 "HW failed tstmp frozen %#jx %#jx, disabling\n", 1180 next->clbr_hw_curr, curr->clbr_hw_prev); 1181 priv->clbr_done = 0; 1182 } 1183 atomic_store_rel_int(&curr->clbr_gen, 0); 1184 return; 1185 } 1186 1187 nanouptime(&ts); 1188 next->base_curr = mlx5e_timespec2usec(&ts); 1189 1190 curr->clbr_gen = 0; 1191 atomic_thread_fence_rel(); 1192 priv->clbr_curr = clbr_curr_next; 1193 atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen)); 1194 1195 if (priv->clbr_done < mlx5e_calibration_duration) 1196 priv->clbr_done++; 1197 mlx5e_reset_calibration_callout(priv); 1198 } 1199 1200 static const char *mlx5e_rq_stats_desc[] = { 1201 MLX5E_RQ_STATS(MLX5E_STATS_DESC) 1202 }; 1203 1204 static int 1205 mlx5e_create_rq(struct mlx5e_channel *c, 1206 struct mlx5e_rq_param *param, 1207 struct mlx5e_rq *rq) 1208 { 1209 struct mlx5e_priv *priv = c->priv; 1210 struct mlx5_core_dev *mdev = priv->mdev; 1211 char buffer[16]; 1212 void *rqc = param->rqc; 1213 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); 1214 int wq_sz; 1215 int err; 1216 int i; 1217 u32 nsegs, wqe_sz; 1218 1219 err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs); 1220 if (err != 0) 1221 goto done; 1222 1223 /* Create DMA descriptor TAG */ 1224 if ((err = -bus_dma_tag_create( 1225 bus_get_dma_tag(mdev->pdev->dev.bsddev), 1226 1, /* any alignment */ 1227 0, /* no boundary */ 1228 BUS_SPACE_MAXADDR, /* lowaddr */ 1229 BUS_SPACE_MAXADDR, /* highaddr */ 1230 NULL, NULL, /* filter, filterarg */ 1231 nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */ 1232 nsegs, /* nsegments */ 1233 nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */ 1234 0, /* flags */ 1235 NULL, NULL, /* lockfunc, lockfuncarg */ 1236 &rq->dma_tag))) 1237 goto done; 1238 1239 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, 1240 &rq->wq_ctrl); 1241 if (err) 1242 goto err_free_dma_tag; 1243 1244 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR]; 1245 1246 err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs); 1247 if (err != 0) 1248 goto err_rq_wq_destroy; 1249 1250 wq_sz = mlx5_wq_ll_get_size(&rq->wq); 1251 1252 err = -tcp_lro_init_args(&rq->lro, priv->ifp, TCP_LRO_ENTRIES, wq_sz); 1253 if (err) 1254 goto err_rq_wq_destroy; 1255 1256 rq->mbuf = malloc_domainset(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, 1257 mlx5_dev_domainset(mdev), M_WAITOK | M_ZERO); 1258 for (i = 0; i != wq_sz; i++) { 1259 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i); 1260 int j; 1261 1262 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map); 1263 if (err != 0) { 1264 while (i--) 1265 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 1266 goto err_rq_mbuf_free; 1267 } 1268 1269 /* set value for constant fields */ 1270 for (j = 0; j < rq->nsegs; j++) 1271 wqe->data[j].lkey = cpu_to_be32(priv->mr.key); 1272 } 1273 1274 INIT_WORK(&rq->dim.work, mlx5e_dim_work); 1275 if (priv->params.rx_cq_moderation_mode < 2) { 1276 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 1277 } else { 1278 void *cqc = container_of(param, 1279 struct mlx5e_channel_param, rq)->rx_cq.cqc; 1280 1281 switch (MLX5_GET(cqc, cqc, cq_period_mode)) { 1282 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE: 1283 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; 1284 break; 1285 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE: 1286 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE; 1287 break; 1288 default: 1289 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 1290 break; 1291 } 1292 } 1293 1294 rq->ifp = priv->ifp; 1295 rq->channel = c; 1296 rq->ix = c->ix; 1297 1298 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix); 1299 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 1300 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM, 1301 rq->stats.arg); 1302 return (0); 1303 1304 err_rq_mbuf_free: 1305 free(rq->mbuf, M_MLX5EN); 1306 tcp_lro_free(&rq->lro); 1307 err_rq_wq_destroy: 1308 mlx5_wq_destroy(&rq->wq_ctrl); 1309 err_free_dma_tag: 1310 bus_dma_tag_destroy(rq->dma_tag); 1311 done: 1312 return (err); 1313 } 1314 1315 static void 1316 mlx5e_destroy_rq(struct mlx5e_rq *rq) 1317 { 1318 int wq_sz; 1319 int i; 1320 1321 /* destroy all sysctl nodes */ 1322 sysctl_ctx_free(&rq->stats.ctx); 1323 1324 /* free leftover LRO packets, if any */ 1325 tcp_lro_free(&rq->lro); 1326 1327 wq_sz = mlx5_wq_ll_get_size(&rq->wq); 1328 for (i = 0; i != wq_sz; i++) { 1329 if (rq->mbuf[i].mbuf != NULL) { 1330 bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map); 1331 m_freem(rq->mbuf[i].mbuf); 1332 } 1333 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 1334 } 1335 free(rq->mbuf, M_MLX5EN); 1336 mlx5_wq_destroy(&rq->wq_ctrl); 1337 bus_dma_tag_destroy(rq->dma_tag); 1338 } 1339 1340 static int 1341 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param) 1342 { 1343 struct mlx5e_channel *c = rq->channel; 1344 struct mlx5e_priv *priv = c->priv; 1345 struct mlx5_core_dev *mdev = priv->mdev; 1346 void *in; 1347 void *rqc; 1348 void *wq; 1349 int inlen; 1350 int err; 1351 u8 ts_format; 1352 1353 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 1354 sizeof(u64) * rq->wq_ctrl.buf.npages; 1355 in = mlx5_vzalloc(inlen); 1356 if (in == NULL) 1357 return (-ENOMEM); 1358 1359 ts_format = mlx5_get_rq_default_ts(mdev); 1360 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1361 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1362 1363 memcpy(rqc, param->rqc, sizeof(param->rqc)); 1364 1365 MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn); 1366 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1367 MLX5_SET(rqc, rqc, ts_format, ts_format); 1368 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1369 if (priv->counter_set_id >= 0) 1370 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id); 1371 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - 1372 PAGE_SHIFT); 1373 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); 1374 1375 mlx5_fill_page_array(&rq->wq_ctrl.buf, 1376 (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 1377 1378 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); 1379 1380 kvfree(in); 1381 1382 return (err); 1383 } 1384 1385 static int 1386 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state) 1387 { 1388 struct mlx5e_channel *c = rq->channel; 1389 struct mlx5e_priv *priv = c->priv; 1390 struct mlx5_core_dev *mdev = priv->mdev; 1391 1392 void *in; 1393 void *rqc; 1394 int inlen; 1395 int err; 1396 1397 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 1398 in = mlx5_vzalloc(inlen); 1399 if (in == NULL) 1400 return (-ENOMEM); 1401 1402 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1403 1404 MLX5_SET(modify_rq_in, in, rqn, rq->rqn); 1405 MLX5_SET(modify_rq_in, in, rq_state, curr_state); 1406 MLX5_SET(rqc, rqc, state, next_state); 1407 1408 err = mlx5_core_modify_rq(mdev, in, inlen); 1409 1410 kvfree(in); 1411 1412 return (err); 1413 } 1414 1415 static void 1416 mlx5e_disable_rq(struct mlx5e_rq *rq) 1417 { 1418 struct mlx5e_channel *c = rq->channel; 1419 struct mlx5e_priv *priv = c->priv; 1420 struct mlx5_core_dev *mdev = priv->mdev; 1421 1422 mlx5_core_destroy_rq(mdev, rq->rqn); 1423 } 1424 1425 static int 1426 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq) 1427 { 1428 struct mlx5e_channel *c = rq->channel; 1429 struct mlx5e_priv *priv = c->priv; 1430 struct mlx5_wq_ll *wq = &rq->wq; 1431 int i; 1432 1433 for (i = 0; i < 1000; i++) { 1434 if (wq->cur_sz >= priv->params.min_rx_wqes) 1435 return (0); 1436 1437 msleep(4); 1438 } 1439 return (-ETIMEDOUT); 1440 } 1441 1442 static int 1443 mlx5e_open_rq(struct mlx5e_channel *c, 1444 struct mlx5e_rq_param *param, 1445 struct mlx5e_rq *rq) 1446 { 1447 int err; 1448 1449 err = mlx5e_create_rq(c, param, rq); 1450 if (err) 1451 return (err); 1452 1453 err = mlx5e_enable_rq(rq, param); 1454 if (err) 1455 goto err_destroy_rq; 1456 1457 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 1458 if (err) 1459 goto err_disable_rq; 1460 1461 c->rq.enabled = 1; 1462 1463 return (0); 1464 1465 err_disable_rq: 1466 mlx5e_disable_rq(rq); 1467 err_destroy_rq: 1468 mlx5e_destroy_rq(rq); 1469 1470 return (err); 1471 } 1472 1473 static void 1474 mlx5e_close_rq(struct mlx5e_rq *rq) 1475 { 1476 mtx_lock(&rq->mtx); 1477 rq->enabled = 0; 1478 callout_stop(&rq->watchdog); 1479 mtx_unlock(&rq->mtx); 1480 1481 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 1482 } 1483 1484 static void 1485 mlx5e_close_rq_wait(struct mlx5e_rq *rq) 1486 { 1487 1488 mlx5e_disable_rq(rq); 1489 mlx5e_close_cq(&rq->cq); 1490 cancel_work_sync(&rq->dim.work); 1491 mlx5e_destroy_rq(rq); 1492 } 1493 1494 void 1495 mlx5e_free_sq_db(struct mlx5e_sq *sq) 1496 { 1497 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1498 int x; 1499 1500 for (x = 0; x != wq_sz; x++) { 1501 if (unlikely(sq->mbuf[x].p_refcount != NULL)) { 1502 atomic_add_int(sq->mbuf[x].p_refcount, -1); 1503 sq->mbuf[x].p_refcount = NULL; 1504 } 1505 if (sq->mbuf[x].mbuf != NULL) { 1506 bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map); 1507 m_freem(sq->mbuf[x].mbuf); 1508 } 1509 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 1510 } 1511 free(sq->mbuf, M_MLX5EN); 1512 } 1513 1514 int 1515 mlx5e_alloc_sq_db(struct mlx5e_sq *sq) 1516 { 1517 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1518 int err; 1519 int x; 1520 1521 sq->mbuf = malloc_domainset(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, 1522 mlx5_dev_domainset(sq->priv->mdev), M_WAITOK | M_ZERO); 1523 1524 /* Create DMA descriptor MAPs */ 1525 for (x = 0; x != wq_sz; x++) { 1526 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map); 1527 if (err != 0) { 1528 while (x--) 1529 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 1530 free(sq->mbuf, M_MLX5EN); 1531 return (err); 1532 } 1533 } 1534 return (0); 1535 } 1536 1537 static const char *mlx5e_sq_stats_desc[] = { 1538 MLX5E_SQ_STATS(MLX5E_STATS_DESC) 1539 }; 1540 1541 void 1542 mlx5e_update_sq_inline(struct mlx5e_sq *sq) 1543 { 1544 sq->max_inline = sq->priv->params.tx_max_inline; 1545 sq->min_inline_mode = sq->priv->params.tx_min_inline_mode; 1546 1547 /* 1548 * Check if trust state is DSCP or if inline mode is NONE which 1549 * indicates CX-5 or newer hardware. 1550 */ 1551 if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP || 1552 sq->min_inline_mode == MLX5_INLINE_MODE_NONE) { 1553 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert)) 1554 sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN; 1555 else 1556 sq->min_insert_caps = MLX5E_INSERT_NON_VLAN; 1557 } else { 1558 sq->min_insert_caps = 0; 1559 } 1560 } 1561 1562 static void 1563 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c) 1564 { 1565 int i; 1566 1567 for (i = 0; i != priv->num_tc; i++) { 1568 mtx_lock(&c->sq[i].lock); 1569 mlx5e_update_sq_inline(&c->sq[i]); 1570 mtx_unlock(&c->sq[i].lock); 1571 } 1572 } 1573 1574 void 1575 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv) 1576 { 1577 int i; 1578 1579 /* check if channels are closed */ 1580 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 1581 return; 1582 1583 for (i = 0; i < priv->params.num_channels; i++) 1584 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]); 1585 } 1586 1587 static int 1588 mlx5e_create_sq(struct mlx5e_channel *c, 1589 int tc, 1590 struct mlx5e_sq_param *param, 1591 struct mlx5e_sq *sq) 1592 { 1593 struct mlx5e_priv *priv = c->priv; 1594 struct mlx5_core_dev *mdev = priv->mdev; 1595 char buffer[16]; 1596 void *sqc = param->sqc; 1597 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq); 1598 int err; 1599 1600 /* Create DMA descriptor TAG */ 1601 if ((err = -bus_dma_tag_create( 1602 bus_get_dma_tag(mdev->pdev->dev.bsddev), 1603 1, /* any alignment */ 1604 0, /* no boundary */ 1605 BUS_SPACE_MAXADDR, /* lowaddr */ 1606 BUS_SPACE_MAXADDR, /* highaddr */ 1607 NULL, NULL, /* filter, filterarg */ 1608 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */ 1609 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */ 1610 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */ 1611 0, /* flags */ 1612 NULL, NULL, /* lockfunc, lockfuncarg */ 1613 &sq->dma_tag))) 1614 goto done; 1615 1616 sq->mkey_be = cpu_to_be32(priv->mr.key); 1617 sq->ifp = priv->ifp; 1618 sq->priv = priv; 1619 sq->tc = tc; 1620 1621 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, 1622 &sq->wq_ctrl); 1623 if (err) 1624 goto err_free_dma_tag; 1625 1626 sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; 1627 1628 err = mlx5e_alloc_sq_db(sq); 1629 if (err) 1630 goto err_sq_wq_destroy; 1631 1632 mlx5e_update_sq_inline(sq); 1633 1634 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc); 1635 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 1636 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM, 1637 sq->stats.arg); 1638 1639 return (0); 1640 1641 err_sq_wq_destroy: 1642 mlx5_wq_destroy(&sq->wq_ctrl); 1643 1644 err_free_dma_tag: 1645 bus_dma_tag_destroy(sq->dma_tag); 1646 done: 1647 return (err); 1648 } 1649 1650 static void 1651 mlx5e_destroy_sq(struct mlx5e_sq *sq) 1652 { 1653 /* destroy all sysctl nodes */ 1654 sysctl_ctx_free(&sq->stats.ctx); 1655 1656 mlx5e_free_sq_db(sq); 1657 mlx5_wq_destroy(&sq->wq_ctrl); 1658 bus_dma_tag_destroy(sq->dma_tag); 1659 } 1660 1661 int 1662 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param, 1663 const struct mlx5_sq_bfreg *bfreg, int tis_num) 1664 { 1665 void *in; 1666 void *sqc; 1667 void *wq; 1668 int inlen; 1669 int err; 1670 u8 ts_format; 1671 1672 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1673 sizeof(u64) * sq->wq_ctrl.buf.npages; 1674 in = mlx5_vzalloc(inlen); 1675 if (in == NULL) 1676 return (-ENOMEM); 1677 1678 sq->uar_map = bfreg->map; 1679 1680 ts_format = mlx5_get_sq_default_ts(sq->priv->mdev); 1681 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1682 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1683 1684 memcpy(sqc, param->sqc, sizeof(param->sqc)); 1685 1686 MLX5_SET(sqc, sqc, tis_num_0, tis_num); 1687 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn); 1688 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1689 MLX5_SET(sqc, sqc, ts_format, ts_format); 1690 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1691 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1692 MLX5_SET(sqc, sqc, allow_swp, 1); 1693 1694 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1695 MLX5_SET(wq, wq, uar_page, bfreg->index); 1696 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift - 1697 PAGE_SHIFT); 1698 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma); 1699 1700 mlx5_fill_page_array(&sq->wq_ctrl.buf, 1701 (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 1702 1703 err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn); 1704 1705 kvfree(in); 1706 1707 return (err); 1708 } 1709 1710 int 1711 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state) 1712 { 1713 void *in; 1714 void *sqc; 1715 int inlen; 1716 int err; 1717 1718 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 1719 in = mlx5_vzalloc(inlen); 1720 if (in == NULL) 1721 return (-ENOMEM); 1722 1723 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1724 1725 MLX5_SET(modify_sq_in, in, sqn, sq->sqn); 1726 MLX5_SET(modify_sq_in, in, sq_state, curr_state); 1727 MLX5_SET(sqc, sqc, state, next_state); 1728 1729 err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen); 1730 1731 kvfree(in); 1732 1733 return (err); 1734 } 1735 1736 void 1737 mlx5e_disable_sq(struct mlx5e_sq *sq) 1738 { 1739 1740 mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn); 1741 } 1742 1743 static int 1744 mlx5e_open_sq(struct mlx5e_channel *c, 1745 int tc, 1746 struct mlx5e_sq_param *param, 1747 struct mlx5e_sq *sq) 1748 { 1749 int err; 1750 1751 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact; 1752 1753 /* ensure the TX completion event factor is not zero */ 1754 if (sq->cev_factor == 0) 1755 sq->cev_factor = 1; 1756 1757 err = mlx5e_create_sq(c, tc, param, sq); 1758 if (err) 1759 return (err); 1760 1761 err = mlx5e_enable_sq(sq, param, &c->bfreg, c->priv->tisn[tc]); 1762 if (err) 1763 goto err_destroy_sq; 1764 1765 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY); 1766 if (err) 1767 goto err_disable_sq; 1768 1769 WRITE_ONCE(sq->running, 1); 1770 1771 return (0); 1772 1773 err_disable_sq: 1774 mlx5e_disable_sq(sq); 1775 err_destroy_sq: 1776 mlx5e_destroy_sq(sq); 1777 1778 return (err); 1779 } 1780 1781 static void 1782 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep) 1783 { 1784 /* fill up remainder with NOPs */ 1785 while (sq->cev_counter != 0) { 1786 while (!mlx5e_sq_has_room_for(sq, 1)) { 1787 if (can_sleep != 0) { 1788 mtx_unlock(&sq->lock); 1789 msleep(4); 1790 mtx_lock(&sq->lock); 1791 } else { 1792 goto done; 1793 } 1794 } 1795 /* send a single NOP */ 1796 mlx5e_send_nop(sq, 1); 1797 atomic_thread_fence_rel(); 1798 } 1799 done: 1800 /* Check if we need to write the doorbell */ 1801 if (likely(sq->doorbell.d64 != 0)) { 1802 mlx5e_tx_notify_hw(sq, sq->doorbell.d32); 1803 sq->doorbell.d64 = 0; 1804 } 1805 } 1806 1807 void 1808 mlx5e_sq_cev_timeout(void *arg) 1809 { 1810 struct mlx5e_sq *sq = arg; 1811 1812 mtx_assert(&sq->lock, MA_OWNED); 1813 1814 /* check next state */ 1815 switch (sq->cev_next_state) { 1816 case MLX5E_CEV_STATE_SEND_NOPS: 1817 /* fill TX ring with NOPs, if any */ 1818 mlx5e_sq_send_nops_locked(sq, 0); 1819 1820 /* check if completed */ 1821 if (sq->cev_counter == 0) { 1822 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL; 1823 return; 1824 } 1825 break; 1826 default: 1827 /* send NOPs on next timeout */ 1828 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS; 1829 break; 1830 } 1831 1832 /* restart timer */ 1833 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq); 1834 } 1835 1836 void 1837 mlx5e_drain_sq(struct mlx5e_sq *sq) 1838 { 1839 int error; 1840 struct mlx5_core_dev *mdev= sq->priv->mdev; 1841 1842 /* 1843 * Check if already stopped. 1844 * 1845 * NOTE: Serialization of this function is managed by the 1846 * caller ensuring the priv's state lock is locked or in case 1847 * of rate limit support, a single thread manages drain and 1848 * resume of SQs. The "running" variable can therefore safely 1849 * be read without any locks. 1850 */ 1851 if (READ_ONCE(sq->running) == 0) 1852 return; 1853 1854 /* don't put more packets into the SQ */ 1855 WRITE_ONCE(sq->running, 0); 1856 1857 /* serialize access to DMA rings */ 1858 mtx_lock(&sq->lock); 1859 1860 /* teardown event factor timer, if any */ 1861 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS; 1862 callout_stop(&sq->cev_callout); 1863 1864 /* send dummy NOPs in order to flush the transmit ring */ 1865 mlx5e_sq_send_nops_locked(sq, 1); 1866 mtx_unlock(&sq->lock); 1867 1868 /* wait till SQ is empty or link is down */ 1869 mtx_lock(&sq->lock); 1870 while (sq->cc != sq->pc && 1871 (sq->priv->media_status_last & IFM_ACTIVE) != 0 && 1872 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR && 1873 pci_channel_offline(mdev->pdev) == 0) { 1874 mtx_unlock(&sq->lock); 1875 msleep(1); 1876 sq->cq.mcq.comp(&sq->cq.mcq, NULL); 1877 mtx_lock(&sq->lock); 1878 } 1879 mtx_unlock(&sq->lock); 1880 1881 /* error out remaining requests */ 1882 error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR); 1883 if (error != 0) { 1884 mlx5_en_err(sq->ifp, 1885 "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error); 1886 } 1887 1888 /* wait till SQ is empty */ 1889 mtx_lock(&sq->lock); 1890 while (sq->cc != sq->pc && 1891 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR && 1892 pci_channel_offline(mdev->pdev) == 0) { 1893 mtx_unlock(&sq->lock); 1894 msleep(1); 1895 sq->cq.mcq.comp(&sq->cq.mcq, NULL); 1896 mtx_lock(&sq->lock); 1897 } 1898 mtx_unlock(&sq->lock); 1899 } 1900 1901 static void 1902 mlx5e_close_sq_wait(struct mlx5e_sq *sq) 1903 { 1904 1905 mlx5e_drain_sq(sq); 1906 mlx5e_disable_sq(sq); 1907 mlx5e_destroy_sq(sq); 1908 } 1909 1910 static int 1911 mlx5e_create_cq(struct mlx5e_priv *priv, 1912 struct mlx5e_cq_param *param, 1913 struct mlx5e_cq *cq, 1914 mlx5e_cq_comp_t *comp, 1915 int eq_ix) 1916 { 1917 struct mlx5_core_dev *mdev = priv->mdev; 1918 struct mlx5_core_cq *mcq = &cq->mcq; 1919 int eqn_not_used; 1920 int irqn; 1921 int err; 1922 u32 i; 1923 1924 err = mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn); 1925 if (err) 1926 return (err); 1927 1928 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, 1929 &cq->wq_ctrl); 1930 if (err) 1931 return (err); 1932 1933 mcq->cqe_sz = 64; 1934 mcq->set_ci_db = cq->wq_ctrl.db.db; 1935 mcq->arm_db = cq->wq_ctrl.db.db + 1; 1936 *mcq->set_ci_db = 0; 1937 *mcq->arm_db = 0; 1938 mcq->vector = eq_ix; 1939 mcq->comp = comp; 1940 mcq->event = mlx5e_cq_error_event; 1941 mcq->irqn = irqn; 1942 1943 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { 1944 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); 1945 1946 cqe->op_own = 0xf1; 1947 } 1948 1949 cq->priv = priv; 1950 1951 return (0); 1952 } 1953 1954 static void 1955 mlx5e_destroy_cq(struct mlx5e_cq *cq) 1956 { 1957 mlx5_wq_destroy(&cq->wq_ctrl); 1958 } 1959 1960 static int 1961 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix) 1962 { 1963 struct mlx5_core_cq *mcq = &cq->mcq; 1964 u32 out[MLX5_ST_SZ_DW(create_cq_out)]; 1965 void *in; 1966 void *cqc; 1967 int inlen; 1968 int irqn_not_used; 1969 int eqn; 1970 int err; 1971 1972 inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 1973 sizeof(u64) * cq->wq_ctrl.buf.npages; 1974 in = mlx5_vzalloc(inlen); 1975 if (in == NULL) 1976 return (-ENOMEM); 1977 1978 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1979 1980 memcpy(cqc, param->cqc, sizeof(param->cqc)); 1981 1982 mlx5_fill_page_array(&cq->wq_ctrl.buf, 1983 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas)); 1984 1985 mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used); 1986 1987 MLX5_SET(cqc, cqc, c_eqn, eqn); 1988 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - 1989 PAGE_SHIFT); 1990 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); 1991 1992 err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen, out, sizeof(out)); 1993 1994 kvfree(in); 1995 1996 if (err) 1997 return (err); 1998 1999 mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock)); 2000 2001 return (0); 2002 } 2003 2004 static void 2005 mlx5e_disable_cq(struct mlx5e_cq *cq) 2006 { 2007 2008 mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq); 2009 } 2010 2011 int 2012 mlx5e_open_cq(struct mlx5e_priv *priv, 2013 struct mlx5e_cq_param *param, 2014 struct mlx5e_cq *cq, 2015 mlx5e_cq_comp_t *comp, 2016 int eq_ix) 2017 { 2018 int err; 2019 2020 err = mlx5e_create_cq(priv, param, cq, comp, eq_ix); 2021 if (err) 2022 return (err); 2023 2024 err = mlx5e_enable_cq(cq, param, eq_ix); 2025 if (err) 2026 goto err_destroy_cq; 2027 2028 return (0); 2029 2030 err_destroy_cq: 2031 mlx5e_destroy_cq(cq); 2032 2033 return (err); 2034 } 2035 2036 void 2037 mlx5e_close_cq(struct mlx5e_cq *cq) 2038 { 2039 mlx5e_disable_cq(cq); 2040 mlx5e_destroy_cq(cq); 2041 } 2042 2043 static int 2044 mlx5e_open_tx_cqs(struct mlx5e_channel *c, 2045 struct mlx5e_channel_param *cparam) 2046 { 2047 int err; 2048 int tc; 2049 2050 for (tc = 0; tc < c->priv->num_tc; tc++) { 2051 /* open completion queue */ 2052 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq, 2053 &mlx5e_tx_cq_comp, c->ix); 2054 if (err) 2055 goto err_close_tx_cqs; 2056 } 2057 return (0); 2058 2059 err_close_tx_cqs: 2060 for (tc--; tc >= 0; tc--) 2061 mlx5e_close_cq(&c->sq[tc].cq); 2062 2063 return (err); 2064 } 2065 2066 static void 2067 mlx5e_close_tx_cqs(struct mlx5e_channel *c) 2068 { 2069 int tc; 2070 2071 for (tc = 0; tc < c->priv->num_tc; tc++) 2072 mlx5e_close_cq(&c->sq[tc].cq); 2073 } 2074 2075 static int 2076 mlx5e_open_sqs(struct mlx5e_channel *c, 2077 struct mlx5e_channel_param *cparam) 2078 { 2079 int err; 2080 int tc; 2081 2082 for (tc = 0; tc < c->priv->num_tc; tc++) { 2083 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]); 2084 if (err) 2085 goto err_close_sqs; 2086 } 2087 2088 return (0); 2089 2090 err_close_sqs: 2091 for (tc--; tc >= 0; tc--) 2092 mlx5e_close_sq_wait(&c->sq[tc]); 2093 2094 return (err); 2095 } 2096 2097 static void 2098 mlx5e_close_sqs_wait(struct mlx5e_channel *c) 2099 { 2100 int tc; 2101 2102 for (tc = 0; tc < c->priv->num_tc; tc++) 2103 mlx5e_close_sq_wait(&c->sq[tc]); 2104 } 2105 2106 static void 2107 mlx5e_chan_static_init(struct mlx5e_priv *priv, struct mlx5e_channel *c, int ix) 2108 { 2109 int tc; 2110 2111 /* setup priv and channel number */ 2112 c->priv = priv; 2113 c->ix = ix; 2114 2115 /* setup send tag */ 2116 m_snd_tag_init(&c->tag, c->priv->ifp, IF_SND_TAG_TYPE_UNLIMITED); 2117 2118 init_completion(&c->completion); 2119 2120 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF); 2121 2122 callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0); 2123 2124 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) { 2125 struct mlx5e_sq *sq = c->sq + tc; 2126 2127 mtx_init(&sq->lock, "mlx5tx", 2128 MTX_NETWORK_LOCK " TX", MTX_DEF); 2129 mtx_init(&sq->comp_lock, "mlx5comp", 2130 MTX_NETWORK_LOCK " TX", MTX_DEF); 2131 2132 callout_init_mtx(&sq->cev_callout, &sq->lock, 0); 2133 } 2134 } 2135 2136 static void 2137 mlx5e_chan_wait_for_completion(struct mlx5e_channel *c) 2138 { 2139 2140 m_snd_tag_rele(&c->tag); 2141 wait_for_completion(&c->completion); 2142 } 2143 2144 static void 2145 mlx5e_priv_wait_for_completion(struct mlx5e_priv *priv, const uint32_t channels) 2146 { 2147 uint32_t x; 2148 2149 for (x = 0; x != channels; x++) 2150 mlx5e_chan_wait_for_completion(&priv->channel[x]); 2151 } 2152 2153 static void 2154 mlx5e_chan_static_destroy(struct mlx5e_channel *c) 2155 { 2156 int tc; 2157 2158 callout_drain(&c->rq.watchdog); 2159 2160 mtx_destroy(&c->rq.mtx); 2161 2162 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) { 2163 callout_drain(&c->sq[tc].cev_callout); 2164 mtx_destroy(&c->sq[tc].lock); 2165 mtx_destroy(&c->sq[tc].comp_lock); 2166 } 2167 } 2168 2169 static int 2170 mlx5e_open_channel(struct mlx5e_priv *priv, 2171 struct mlx5e_channel_param *cparam, 2172 struct mlx5e_channel *c) 2173 { 2174 struct epoch_tracker et; 2175 int i, err; 2176 2177 /* zero non-persistant data */ 2178 MLX5E_ZERO(&c->rq, mlx5e_rq_zero_start); 2179 for (i = 0; i != priv->num_tc; i++) 2180 MLX5E_ZERO(&c->sq[i], mlx5e_sq_zero_start); 2181 2182 /* open transmit completion queue */ 2183 err = mlx5e_open_tx_cqs(c, cparam); 2184 if (err) 2185 goto err_free; 2186 2187 /* open receive completion queue */ 2188 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq, 2189 &mlx5e_rx_cq_comp, c->ix); 2190 if (err) 2191 goto err_close_tx_cqs; 2192 2193 err = mlx5e_open_sqs(c, cparam); 2194 if (err) 2195 goto err_close_rx_cq; 2196 2197 err = mlx5e_open_rq(c, &cparam->rq, &c->rq); 2198 if (err) 2199 goto err_close_sqs; 2200 2201 /* poll receive queue initially */ 2202 NET_EPOCH_ENTER(et); 2203 c->rq.cq.mcq.comp(&c->rq.cq.mcq, NULL); 2204 NET_EPOCH_EXIT(et); 2205 2206 return (0); 2207 2208 err_close_sqs: 2209 mlx5e_close_sqs_wait(c); 2210 2211 err_close_rx_cq: 2212 mlx5e_close_cq(&c->rq.cq); 2213 2214 err_close_tx_cqs: 2215 mlx5e_close_tx_cqs(c); 2216 2217 err_free: 2218 return (err); 2219 } 2220 2221 static void 2222 mlx5e_close_channel(struct mlx5e_channel *c) 2223 { 2224 mlx5e_close_rq(&c->rq); 2225 } 2226 2227 static void 2228 mlx5e_close_channel_wait(struct mlx5e_channel *c) 2229 { 2230 mlx5e_close_rq_wait(&c->rq); 2231 mlx5e_close_sqs_wait(c); 2232 mlx5e_close_tx_cqs(c); 2233 } 2234 2235 static int 2236 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs) 2237 { 2238 u32 r, n; 2239 2240 r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz : 2241 MLX5E_SW2MB_MTU(priv->ifp->if_mtu); 2242 if (r > MJUM16BYTES) 2243 return (-ENOMEM); 2244 2245 if (r > MJUM9BYTES) 2246 r = MJUM16BYTES; 2247 else if (r > MJUMPAGESIZE) 2248 r = MJUM9BYTES; 2249 else if (r > MCLBYTES) 2250 r = MJUMPAGESIZE; 2251 else 2252 r = MCLBYTES; 2253 2254 /* 2255 * n + 1 must be a power of two, because stride size must be. 2256 * Stride size is 16 * (n + 1), as the first segment is 2257 * control. 2258 */ 2259 for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++) 2260 ; 2261 2262 if (n > MLX5E_MAX_BUSDMA_RX_SEGS) 2263 return (-ENOMEM); 2264 2265 *wqe_sz = r; 2266 *nsegs = n; 2267 return (0); 2268 } 2269 2270 static void 2271 mlx5e_build_rq_param(struct mlx5e_priv *priv, 2272 struct mlx5e_rq_param *param) 2273 { 2274 void *rqc = param->rqc; 2275 void *wq = MLX5_ADDR_OF(rqc, rqc, wq); 2276 u32 wqe_sz, nsegs; 2277 2278 mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs); 2279 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); 2280 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 2281 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) + 2282 nsegs * sizeof(struct mlx5_wqe_data_seg))); 2283 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size); 2284 MLX5_SET(wq, wq, pd, priv->pdn); 2285 2286 param->wq.linear = 1; 2287 } 2288 2289 static void 2290 mlx5e_build_sq_param(struct mlx5e_priv *priv, 2291 struct mlx5e_sq_param *param) 2292 { 2293 void *sqc = param->sqc; 2294 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 2295 2296 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size); 2297 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 2298 MLX5_SET(wq, wq, pd, priv->pdn); 2299 2300 param->wq.linear = 1; 2301 } 2302 2303 static void 2304 mlx5e_build_common_cq_param(struct mlx5e_priv *priv, 2305 struct mlx5e_cq_param *param) 2306 { 2307 void *cqc = param->cqc; 2308 2309 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index); 2310 } 2311 2312 static void 2313 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr) 2314 { 2315 2316 *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE); 2317 2318 /* apply LRO restrictions */ 2319 if (priv->params.hw_lro_en && 2320 ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) { 2321 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO; 2322 } 2323 } 2324 2325 static void 2326 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, 2327 struct mlx5e_cq_param *param) 2328 { 2329 struct net_dim_cq_moder curr; 2330 void *cqc = param->cqc; 2331 2332 /* 2333 * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE 2334 * format is more beneficial for FreeBSD use case. 2335 * 2336 * Adding support for MLX5_CQE_FORMAT_CSUM will require changes 2337 * in mlx5e_decompress_cqe. 2338 */ 2339 if (priv->params.cqe_zipping_en) { 2340 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH); 2341 MLX5_SET(cqc, cqc, cqe_compression_en, 1); 2342 } 2343 2344 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size); 2345 2346 switch (priv->params.rx_cq_moderation_mode) { 2347 case 0: 2348 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec); 2349 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts); 2350 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2351 break; 2352 case 1: 2353 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec); 2354 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts); 2355 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2356 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2357 else 2358 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2359 break; 2360 case 2: 2361 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr); 2362 MLX5_SET(cqc, cqc, cq_period, curr.usec); 2363 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts); 2364 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2365 break; 2366 case 3: 2367 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr); 2368 MLX5_SET(cqc, cqc, cq_period, curr.usec); 2369 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts); 2370 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2371 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2372 else 2373 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2374 break; 2375 default: 2376 break; 2377 } 2378 2379 mlx5e_dim_build_cq_param(priv, param); 2380 2381 mlx5e_build_common_cq_param(priv, param); 2382 } 2383 2384 static void 2385 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv, 2386 struct mlx5e_cq_param *param) 2387 { 2388 void *cqc = param->cqc; 2389 2390 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size); 2391 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec); 2392 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts); 2393 2394 switch (priv->params.tx_cq_moderation_mode) { 2395 case 0: 2396 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2397 break; 2398 default: 2399 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2400 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2401 else 2402 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2403 break; 2404 } 2405 2406 mlx5e_build_common_cq_param(priv, param); 2407 } 2408 2409 static void 2410 mlx5e_build_channel_param(struct mlx5e_priv *priv, 2411 struct mlx5e_channel_param *cparam) 2412 { 2413 memset(cparam, 0, sizeof(*cparam)); 2414 2415 mlx5e_build_rq_param(priv, &cparam->rq); 2416 mlx5e_build_sq_param(priv, &cparam->sq); 2417 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq); 2418 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq); 2419 } 2420 2421 static int 2422 mlx5e_open_channels(struct mlx5e_priv *priv) 2423 { 2424 struct mlx5e_channel_param *cparam; 2425 int err; 2426 int i; 2427 int j; 2428 2429 cparam = malloc(sizeof(*cparam), M_MLX5EN, M_WAITOK); 2430 2431 mlx5e_build_channel_param(priv, cparam); 2432 for (i = 0; i < priv->params.num_channels; i++) { 2433 err = mlx5e_open_channel(priv, cparam, &priv->channel[i]); 2434 if (err) 2435 goto err_close_channels; 2436 2437 /* Bind interrupt vectors, if any. */ 2438 if (priv->params_ethtool.irq_cpu_base > -1) { 2439 cpuset_t cpuset; 2440 int cpu; 2441 int irq; 2442 int eqn; 2443 int nirq; 2444 2445 err = mlx5_vector2eqn(priv->mdev, i, 2446 &eqn, &nirq); 2447 2448 /* error here is non-fatal */ 2449 if (err != 0) 2450 continue; 2451 2452 irq = priv->mdev->priv.msix_arr[nirq].vector; 2453 cpu = (unsigned)(priv->params_ethtool.irq_cpu_base + 2454 i * priv->params_ethtool.irq_cpu_stride) % (unsigned)mp_ncpus; 2455 2456 CPU_ZERO(&cpuset); 2457 CPU_SET(cpu, &cpuset); 2458 intr_setaffinity(irq, CPU_WHICH_INTRHANDLER, &cpuset); 2459 } 2460 } 2461 2462 for (j = 0; j < priv->params.num_channels; j++) { 2463 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq); 2464 if (err) 2465 goto err_close_channels; 2466 } 2467 free(cparam, M_MLX5EN); 2468 return (0); 2469 2470 err_close_channels: 2471 while (i--) { 2472 mlx5e_close_channel(&priv->channel[i]); 2473 mlx5e_close_channel_wait(&priv->channel[i]); 2474 } 2475 free(cparam, M_MLX5EN); 2476 return (err); 2477 } 2478 2479 static void 2480 mlx5e_close_channels(struct mlx5e_priv *priv) 2481 { 2482 int i; 2483 2484 for (i = 0; i < priv->params.num_channels; i++) 2485 mlx5e_close_channel(&priv->channel[i]); 2486 for (i = 0; i < priv->params.num_channels; i++) 2487 mlx5e_close_channel_wait(&priv->channel[i]); 2488 } 2489 2490 static int 2491 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq) 2492 { 2493 2494 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) { 2495 uint8_t cq_mode; 2496 2497 switch (priv->params.tx_cq_moderation_mode) { 2498 case 0: 2499 case 2: 2500 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 2501 break; 2502 default: 2503 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE; 2504 break; 2505 } 2506 2507 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq, 2508 priv->params.tx_cq_moderation_usec, 2509 priv->params.tx_cq_moderation_pkts, 2510 cq_mode)); 2511 } 2512 2513 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq, 2514 priv->params.tx_cq_moderation_usec, 2515 priv->params.tx_cq_moderation_pkts)); 2516 } 2517 2518 static int 2519 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq) 2520 { 2521 2522 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) { 2523 uint8_t cq_mode; 2524 uint8_t dim_mode; 2525 int retval; 2526 2527 switch (priv->params.rx_cq_moderation_mode) { 2528 case 0: 2529 case 2: 2530 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 2531 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; 2532 break; 2533 default: 2534 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE; 2535 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE; 2536 break; 2537 } 2538 2539 /* tear down dynamic interrupt moderation */ 2540 mtx_lock(&rq->mtx); 2541 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 2542 mtx_unlock(&rq->mtx); 2543 2544 /* wait for dynamic interrupt moderation work task, if any */ 2545 cancel_work_sync(&rq->dim.work); 2546 2547 if (priv->params.rx_cq_moderation_mode >= 2) { 2548 struct net_dim_cq_moder curr; 2549 2550 mlx5e_get_default_profile(priv, dim_mode, &curr); 2551 2552 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq, 2553 curr.usec, curr.pkts, cq_mode); 2554 2555 /* set dynamic interrupt moderation mode and zero defaults */ 2556 mtx_lock(&rq->mtx); 2557 rq->dim.mode = dim_mode; 2558 rq->dim.state = 0; 2559 rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE; 2560 mtx_unlock(&rq->mtx); 2561 } else { 2562 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq, 2563 priv->params.rx_cq_moderation_usec, 2564 priv->params.rx_cq_moderation_pkts, 2565 cq_mode); 2566 } 2567 return (retval); 2568 } 2569 2570 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq, 2571 priv->params.rx_cq_moderation_usec, 2572 priv->params.rx_cq_moderation_pkts)); 2573 } 2574 2575 static int 2576 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c) 2577 { 2578 int err; 2579 int i; 2580 2581 err = mlx5e_refresh_rq_params(priv, &c->rq); 2582 if (err) 2583 goto done; 2584 2585 for (i = 0; i != priv->num_tc; i++) { 2586 err = mlx5e_refresh_sq_params(priv, &c->sq[i]); 2587 if (err) 2588 goto done; 2589 } 2590 done: 2591 return (err); 2592 } 2593 2594 int 2595 mlx5e_refresh_channel_params(struct mlx5e_priv *priv) 2596 { 2597 int i; 2598 2599 /* check if channels are closed */ 2600 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 2601 return (EINVAL); 2602 2603 for (i = 0; i < priv->params.num_channels; i++) { 2604 int err; 2605 2606 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]); 2607 if (err) 2608 return (err); 2609 } 2610 return (0); 2611 } 2612 2613 static int 2614 mlx5e_open_tis(struct mlx5e_priv *priv, int tc) 2615 { 2616 struct mlx5_core_dev *mdev = priv->mdev; 2617 u32 in[MLX5_ST_SZ_DW(create_tis_in)]; 2618 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 2619 2620 memset(in, 0, sizeof(in)); 2621 2622 MLX5_SET(tisc, tisc, prio, tc); 2623 MLX5_SET(tisc, tisc, transport_domain, priv->tdn); 2624 2625 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc])); 2626 } 2627 2628 static void 2629 mlx5e_close_tis(struct mlx5e_priv *priv, int tc) 2630 { 2631 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc], 0); 2632 } 2633 2634 static int 2635 mlx5e_open_tises(struct mlx5e_priv *priv) 2636 { 2637 int num_tc = priv->num_tc; 2638 int err; 2639 int tc; 2640 2641 for (tc = 0; tc < num_tc; tc++) { 2642 err = mlx5e_open_tis(priv, tc); 2643 if (err) 2644 goto err_close_tises; 2645 } 2646 2647 return (0); 2648 2649 err_close_tises: 2650 for (tc--; tc >= 0; tc--) 2651 mlx5e_close_tis(priv, tc); 2652 2653 return (err); 2654 } 2655 2656 static void 2657 mlx5e_close_tises(struct mlx5e_priv *priv) 2658 { 2659 int num_tc = priv->num_tc; 2660 int tc; 2661 2662 for (tc = 0; tc < num_tc; tc++) 2663 mlx5e_close_tis(priv, tc); 2664 } 2665 2666 static int 2667 mlx5e_open_rqt(struct mlx5e_priv *priv) 2668 { 2669 struct mlx5_core_dev *mdev = priv->mdev; 2670 u32 *in; 2671 u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 2672 void *rqtc; 2673 int inlen; 2674 int err; 2675 int sz; 2676 int i; 2677 2678 sz = 1 << priv->params.rx_hash_log_tbl_sz; 2679 2680 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 2681 in = mlx5_vzalloc(inlen); 2682 if (in == NULL) 2683 return (-ENOMEM); 2684 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 2685 2686 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 2687 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 2688 2689 for (i = 0; i < sz; i++) { 2690 int ix = i; 2691 #ifdef RSS 2692 ix = rss_get_indirection_to_bucket(ix); 2693 #endif 2694 /* ensure we don't overflow */ 2695 ix %= priv->params.num_channels; 2696 2697 /* apply receive side scaling stride, if any */ 2698 ix -= ix % (int)priv->params.channels_rsss; 2699 2700 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn); 2701 } 2702 2703 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 2704 2705 err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out)); 2706 if (!err) 2707 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn); 2708 2709 kvfree(in); 2710 2711 return (err); 2712 } 2713 2714 static void 2715 mlx5e_close_rqt(struct mlx5e_priv *priv) 2716 { 2717 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0}; 2718 u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0}; 2719 2720 MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT); 2721 MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn); 2722 2723 mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)); 2724 } 2725 2726 #define MLX5E_RSS_KEY_SIZE (10 * 4) /* bytes */ 2727 2728 static void 2729 mlx5e_get_rss_key(void *key_ptr) 2730 { 2731 #ifdef RSS 2732 rss_getkey(key_ptr); 2733 #else 2734 static const u32 rsskey[] = { 2735 cpu_to_be32(0xD181C62C), 2736 cpu_to_be32(0xF7F4DB5B), 2737 cpu_to_be32(0x1983A2FC), 2738 cpu_to_be32(0x943E1ADB), 2739 cpu_to_be32(0xD9389E6B), 2740 cpu_to_be32(0xD1039C2C), 2741 cpu_to_be32(0xA74499AD), 2742 cpu_to_be32(0x593D56D9), 2743 cpu_to_be32(0xF3253C06), 2744 cpu_to_be32(0x2ADC1FFC), 2745 }; 2746 CTASSERT(sizeof(rsskey) == MLX5E_RSS_KEY_SIZE); 2747 memcpy(key_ptr, rsskey, MLX5E_RSS_KEY_SIZE); 2748 #endif 2749 } 2750 2751 static void 2752 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt, bool inner_vxlan) 2753 { 2754 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 2755 void *hfsi = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 2756 void *hfs = inner_vxlan ? hfsi : hfso; 2757 __be32 *hkey; 2758 2759 MLX5_SET(tirc, tirc, transport_domain, priv->tdn); 2760 2761 #define ROUGH_MAX_L2_L3_HDR_SZ 256 2762 2763 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2764 MLX5_HASH_FIELD_SEL_DST_IP) 2765 2766 #define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2767 MLX5_HASH_FIELD_SEL_DST_IP |\ 2768 MLX5_HASH_FIELD_SEL_L4_SPORT |\ 2769 MLX5_HASH_FIELD_SEL_L4_DPORT) 2770 2771 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2772 MLX5_HASH_FIELD_SEL_DST_IP |\ 2773 MLX5_HASH_FIELD_SEL_IPSEC_SPI) 2774 2775 if (priv->params.hw_lro_en) { 2776 MLX5_SET(tirc, tirc, lro_enable_mask, 2777 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | 2778 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO); 2779 MLX5_SET(tirc, tirc, lro_max_msg_sz, 2780 (priv->params.lro_wqe_sz - 2781 ROUGH_MAX_L2_L3_HDR_SZ) >> 8); 2782 /* TODO: add the option to choose timer value dynamically */ 2783 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, 2784 MLX5_CAP_ETH(priv->mdev, 2785 lro_timer_supported_periods[2])); 2786 } 2787 2788 if (inner_vxlan) 2789 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 2790 2791 /* setup parameters for hashing TIR type, if any */ 2792 switch (tt) { 2793 case MLX5E_TT_ANY: 2794 MLX5_SET(tirc, tirc, disp_type, 2795 MLX5_TIRC_DISP_TYPE_DIRECT); 2796 MLX5_SET(tirc, tirc, inline_rqn, 2797 priv->channel[0].rq.rqn); 2798 break; 2799 default: 2800 MLX5_SET(tirc, tirc, disp_type, 2801 MLX5_TIRC_DISP_TYPE_INDIRECT); 2802 MLX5_SET(tirc, tirc, indirect_table, 2803 priv->rqtn); 2804 MLX5_SET(tirc, tirc, rx_hash_fn, 2805 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ); 2806 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 2807 2808 CTASSERT(MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key) >= 2809 MLX5E_RSS_KEY_SIZE); 2810 #ifdef RSS 2811 /* 2812 * The FreeBSD RSS implementation does currently not 2813 * support symmetric Toeplitz hashes: 2814 */ 2815 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0); 2816 #else 2817 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 2818 #endif 2819 mlx5e_get_rss_key(hkey); 2820 break; 2821 } 2822 2823 switch (tt) { 2824 case MLX5E_TT_IPV4_TCP: 2825 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 2826 MLX5_L3_PROT_TYPE_IPV4); 2827 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type, 2828 MLX5_L4_PROT_TYPE_TCP); 2829 #ifdef RSS 2830 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) { 2831 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 2832 MLX5_HASH_IP); 2833 } else 2834 #endif 2835 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 2836 MLX5_HASH_ALL); 2837 break; 2838 2839 case MLX5E_TT_IPV6_TCP: 2840 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 2841 MLX5_L3_PROT_TYPE_IPV6); 2842 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type, 2843 MLX5_L4_PROT_TYPE_TCP); 2844 #ifdef RSS 2845 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) { 2846 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 2847 MLX5_HASH_IP); 2848 } else 2849 #endif 2850 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 2851 MLX5_HASH_ALL); 2852 break; 2853 2854 case MLX5E_TT_IPV4_UDP: 2855 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 2856 MLX5_L3_PROT_TYPE_IPV4); 2857 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type, 2858 MLX5_L4_PROT_TYPE_UDP); 2859 #ifdef RSS 2860 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) { 2861 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 2862 MLX5_HASH_IP); 2863 } else 2864 #endif 2865 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 2866 MLX5_HASH_ALL); 2867 break; 2868 2869 case MLX5E_TT_IPV6_UDP: 2870 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 2871 MLX5_L3_PROT_TYPE_IPV6); 2872 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type, 2873 MLX5_L4_PROT_TYPE_UDP); 2874 #ifdef RSS 2875 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) { 2876 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 2877 MLX5_HASH_IP); 2878 } else 2879 #endif 2880 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 2881 MLX5_HASH_ALL); 2882 break; 2883 2884 case MLX5E_TT_IPV4_IPSEC_AH: 2885 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 2886 MLX5_L3_PROT_TYPE_IPV4); 2887 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 2888 MLX5_HASH_IP_IPSEC_SPI); 2889 break; 2890 2891 case MLX5E_TT_IPV6_IPSEC_AH: 2892 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 2893 MLX5_L3_PROT_TYPE_IPV6); 2894 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 2895 MLX5_HASH_IP_IPSEC_SPI); 2896 break; 2897 2898 case MLX5E_TT_IPV4_IPSEC_ESP: 2899 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 2900 MLX5_L3_PROT_TYPE_IPV4); 2901 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 2902 MLX5_HASH_IP_IPSEC_SPI); 2903 break; 2904 2905 case MLX5E_TT_IPV6_IPSEC_ESP: 2906 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 2907 MLX5_L3_PROT_TYPE_IPV6); 2908 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 2909 MLX5_HASH_IP_IPSEC_SPI); 2910 break; 2911 2912 case MLX5E_TT_IPV4: 2913 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 2914 MLX5_L3_PROT_TYPE_IPV4); 2915 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 2916 MLX5_HASH_IP); 2917 break; 2918 2919 case MLX5E_TT_IPV6: 2920 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 2921 MLX5_L3_PROT_TYPE_IPV6); 2922 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 2923 MLX5_HASH_IP); 2924 break; 2925 2926 default: 2927 break; 2928 } 2929 } 2930 2931 static int 2932 mlx5e_open_tir(struct mlx5e_priv *priv, int tt, bool inner_vxlan) 2933 { 2934 struct mlx5_core_dev *mdev = priv->mdev; 2935 u32 *in; 2936 void *tirc; 2937 int inlen; 2938 int err; 2939 2940 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 2941 in = mlx5_vzalloc(inlen); 2942 if (in == NULL) 2943 return (-ENOMEM); 2944 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context); 2945 2946 mlx5e_build_tir_ctx(priv, tirc, tt, inner_vxlan); 2947 2948 err = mlx5_core_create_tir(mdev, in, inlen, inner_vxlan ? 2949 &priv->tirn_inner_vxlan[tt] : &priv->tirn[tt]); 2950 2951 kvfree(in); 2952 2953 return (err); 2954 } 2955 2956 static void 2957 mlx5e_close_tir(struct mlx5e_priv *priv, int tt, bool inner_vxlan) 2958 { 2959 mlx5_core_destroy_tir(priv->mdev, inner_vxlan ? 2960 priv->tirn_inner_vxlan[tt] : priv->tirn[tt], 0); 2961 } 2962 2963 static int 2964 mlx5e_open_tirs(struct mlx5e_priv *priv, bool inner_vxlan) 2965 { 2966 int err; 2967 int i; 2968 2969 for (i = 0; i < MLX5E_NUM_TT; i++) { 2970 err = mlx5e_open_tir(priv, i, inner_vxlan); 2971 if (err) 2972 goto err_close_tirs; 2973 } 2974 2975 return (0); 2976 2977 err_close_tirs: 2978 for (i--; i >= 0; i--) 2979 mlx5e_close_tir(priv, i, inner_vxlan); 2980 2981 return (err); 2982 } 2983 2984 static void 2985 mlx5e_close_tirs(struct mlx5e_priv *priv, bool inner_vxlan) 2986 { 2987 int i; 2988 2989 for (i = 0; i < MLX5E_NUM_TT; i++) 2990 mlx5e_close_tir(priv, i, inner_vxlan); 2991 } 2992 2993 /* 2994 * SW MTU does not include headers, 2995 * HW MTU includes all headers and checksums. 2996 */ 2997 static int 2998 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu) 2999 { 3000 struct mlx5e_priv *priv = ifp->if_softc; 3001 struct mlx5_core_dev *mdev = priv->mdev; 3002 int hw_mtu; 3003 int err; 3004 3005 hw_mtu = MLX5E_SW2HW_MTU(sw_mtu); 3006 3007 err = mlx5_set_port_mtu(mdev, hw_mtu); 3008 if (err) { 3009 mlx5_en_err(ifp, "mlx5_set_port_mtu failed setting %d, err=%d\n", 3010 sw_mtu, err); 3011 return (err); 3012 } 3013 3014 /* Update vport context MTU */ 3015 err = mlx5_set_vport_mtu(mdev, hw_mtu); 3016 if (err) { 3017 mlx5_en_err(ifp, 3018 "Failed updating vport context with MTU size, err=%d\n", 3019 err); 3020 } 3021 3022 ifp->if_mtu = sw_mtu; 3023 3024 err = mlx5_query_vport_mtu(mdev, &hw_mtu); 3025 if (err || !hw_mtu) { 3026 /* fallback to port oper mtu */ 3027 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu); 3028 } 3029 if (err) { 3030 mlx5_en_err(ifp, 3031 "Query port MTU, after setting new MTU value, failed\n"); 3032 return (err); 3033 } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) { 3034 err = -E2BIG, 3035 mlx5_en_err(ifp, 3036 "Port MTU %d is smaller than ifp mtu %d\n", 3037 hw_mtu, sw_mtu); 3038 } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) { 3039 err = -EINVAL; 3040 mlx5_en_err(ifp, 3041 "Port MTU %d is bigger than ifp mtu %d\n", 3042 hw_mtu, sw_mtu); 3043 } 3044 priv->params_ethtool.hw_mtu = hw_mtu; 3045 3046 /* compute MSB */ 3047 while (hw_mtu & (hw_mtu - 1)) 3048 hw_mtu &= (hw_mtu - 1); 3049 priv->params_ethtool.hw_mtu_msb = hw_mtu; 3050 3051 return (err); 3052 } 3053 3054 int 3055 mlx5e_open_locked(struct ifnet *ifp) 3056 { 3057 struct mlx5e_priv *priv = ifp->if_softc; 3058 int err; 3059 u16 set_id; 3060 3061 /* check if already opened */ 3062 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 3063 return (0); 3064 3065 #ifdef RSS 3066 if (rss_getnumbuckets() > priv->params.num_channels) { 3067 mlx5_en_info(ifp, 3068 "NOTE: There are more RSS buckets(%u) than channels(%u) available\n", 3069 rss_getnumbuckets(), priv->params.num_channels); 3070 } 3071 #endif 3072 err = mlx5e_open_tises(priv); 3073 if (err) { 3074 mlx5_en_err(ifp, "mlx5e_open_tises failed, %d\n", err); 3075 return (err); 3076 } 3077 err = mlx5_vport_alloc_q_counter(priv->mdev, 3078 MLX5_INTERFACE_PROTOCOL_ETH, &set_id); 3079 if (err) { 3080 mlx5_en_err(priv->ifp, 3081 "mlx5_vport_alloc_q_counter failed: %d\n", err); 3082 goto err_close_tises; 3083 } 3084 /* store counter set ID */ 3085 priv->counter_set_id = set_id; 3086 3087 err = mlx5e_open_channels(priv); 3088 if (err) { 3089 mlx5_en_err(ifp, 3090 "mlx5e_open_channels failed, %d\n", err); 3091 goto err_dalloc_q_counter; 3092 } 3093 err = mlx5e_open_rqt(priv); 3094 if (err) { 3095 mlx5_en_err(ifp, "mlx5e_open_rqt failed, %d\n", err); 3096 goto err_close_channels; 3097 } 3098 err = mlx5e_open_tirs(priv, false); 3099 if (err) { 3100 mlx5_en_err(ifp, "mlx5e_open_tir(main) failed, %d\n", err); 3101 goto err_close_rqls; 3102 } 3103 if ((ifp->if_capenable & IFCAP_VXLAN_HWCSUM) != 0) { 3104 err = mlx5e_open_tirs(priv, true); 3105 if (err) { 3106 mlx5_en_err(ifp, "mlx5e_open_tir(inner) failed, %d\n", 3107 err); 3108 goto err_close_tirs; 3109 } 3110 } 3111 err = mlx5e_open_flow_table(priv); 3112 if (err) { 3113 mlx5_en_err(ifp, 3114 "mlx5e_open_flow_table failed, %d\n", err); 3115 goto err_close_tirs_inner; 3116 } 3117 err = mlx5e_add_all_vlan_rules(priv); 3118 if (err) { 3119 mlx5_en_err(ifp, 3120 "mlx5e_add_all_vlan_rules failed, %d\n", err); 3121 goto err_close_flow_table; 3122 } 3123 if ((ifp->if_capenable & IFCAP_VXLAN_HWCSUM) != 0) { 3124 err = mlx5e_add_all_vxlan_rules(priv); 3125 if (err) { 3126 mlx5_en_err(ifp, 3127 "mlx5e_add_all_vxlan_rules failed, %d\n", err); 3128 goto err_del_vlan_rules; 3129 } 3130 } 3131 set_bit(MLX5E_STATE_OPENED, &priv->state); 3132 3133 mlx5e_update_carrier(priv); 3134 mlx5e_set_rx_mode_core(priv); 3135 3136 return (0); 3137 3138 err_del_vlan_rules: 3139 mlx5e_del_all_vlan_rules(priv); 3140 3141 err_close_flow_table: 3142 mlx5e_close_flow_table(priv); 3143 3144 err_close_tirs_inner: 3145 if ((ifp->if_capenable & IFCAP_VXLAN_HWCSUM) != 0) 3146 mlx5e_close_tirs(priv, true); 3147 3148 err_close_tirs: 3149 mlx5e_close_tirs(priv, false); 3150 3151 err_close_rqls: 3152 mlx5e_close_rqt(priv); 3153 3154 err_close_channels: 3155 mlx5e_close_channels(priv); 3156 3157 err_dalloc_q_counter: 3158 mlx5_vport_dealloc_q_counter(priv->mdev, 3159 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 3160 3161 err_close_tises: 3162 mlx5e_close_tises(priv); 3163 3164 return (err); 3165 } 3166 3167 static void 3168 mlx5e_open(void *arg) 3169 { 3170 struct mlx5e_priv *priv = arg; 3171 3172 PRIV_LOCK(priv); 3173 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP)) 3174 mlx5_en_err(priv->ifp, 3175 "Setting port status to up failed\n"); 3176 3177 mlx5e_open_locked(priv->ifp); 3178 priv->ifp->if_drv_flags |= IFF_DRV_RUNNING; 3179 PRIV_UNLOCK(priv); 3180 } 3181 3182 int 3183 mlx5e_close_locked(struct ifnet *ifp) 3184 { 3185 struct mlx5e_priv *priv = ifp->if_softc; 3186 3187 /* check if already closed */ 3188 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3189 return (0); 3190 3191 clear_bit(MLX5E_STATE_OPENED, &priv->state); 3192 3193 mlx5e_set_rx_mode_core(priv); 3194 mlx5e_del_all_vlan_rules(priv); 3195 if ((ifp->if_capenable & IFCAP_VXLAN_HWCSUM) != 0) 3196 mlx5e_del_all_vxlan_rules(priv); 3197 if_link_state_change(priv->ifp, LINK_STATE_DOWN); 3198 mlx5e_close_flow_table(priv); 3199 if ((ifp->if_capenable & IFCAP_VXLAN_HWCSUM) != 0) 3200 mlx5e_close_tirs(priv, true); 3201 mlx5e_close_tirs(priv, false); 3202 mlx5e_close_rqt(priv); 3203 mlx5e_close_channels(priv); 3204 mlx5_vport_dealloc_q_counter(priv->mdev, 3205 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 3206 mlx5e_close_tises(priv); 3207 3208 return (0); 3209 } 3210 3211 #if (__FreeBSD_version >= 1100000) 3212 static uint64_t 3213 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt) 3214 { 3215 struct mlx5e_priv *priv = ifp->if_softc; 3216 u64 retval; 3217 3218 /* PRIV_LOCK(priv); XXX not allowed */ 3219 switch (cnt) { 3220 case IFCOUNTER_IPACKETS: 3221 retval = priv->stats.vport.rx_packets; 3222 break; 3223 case IFCOUNTER_IERRORS: 3224 retval = priv->stats.pport.in_range_len_errors + 3225 priv->stats.pport.out_of_range_len + 3226 priv->stats.pport.too_long_errors + 3227 priv->stats.pport.check_seq_err + 3228 priv->stats.pport.alignment_err; 3229 break; 3230 case IFCOUNTER_IQDROPS: 3231 retval = priv->stats.vport.rx_out_of_buffer; 3232 break; 3233 case IFCOUNTER_OPACKETS: 3234 retval = priv->stats.vport.tx_packets; 3235 break; 3236 case IFCOUNTER_OERRORS: 3237 retval = priv->stats.port_stats_debug.out_discards; 3238 break; 3239 case IFCOUNTER_IBYTES: 3240 retval = priv->stats.vport.rx_bytes; 3241 break; 3242 case IFCOUNTER_OBYTES: 3243 retval = priv->stats.vport.tx_bytes; 3244 break; 3245 case IFCOUNTER_IMCASTS: 3246 retval = priv->stats.vport.rx_multicast_packets; 3247 break; 3248 case IFCOUNTER_OMCASTS: 3249 retval = priv->stats.vport.tx_multicast_packets; 3250 break; 3251 case IFCOUNTER_OQDROPS: 3252 retval = priv->stats.vport.tx_queue_dropped; 3253 break; 3254 case IFCOUNTER_COLLISIONS: 3255 retval = priv->stats.pport.collisions; 3256 break; 3257 default: 3258 retval = if_get_counter_default(ifp, cnt); 3259 break; 3260 } 3261 /* PRIV_UNLOCK(priv); XXX not allowed */ 3262 return (retval); 3263 } 3264 #endif 3265 3266 static void 3267 mlx5e_set_rx_mode(struct ifnet *ifp) 3268 { 3269 struct mlx5e_priv *priv = ifp->if_softc; 3270 3271 queue_work(priv->wq, &priv->set_rx_mode_work); 3272 } 3273 3274 static int 3275 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3276 { 3277 struct mlx5e_priv *priv; 3278 struct ifreq *ifr; 3279 struct ifdownreason *ifdr; 3280 struct ifi2creq i2c; 3281 struct ifrsskey *ifrk; 3282 struct ifrsshash *ifrh; 3283 int error = 0; 3284 int mask = 0; 3285 int size_read = 0; 3286 int module_status; 3287 int module_num; 3288 int max_mtu; 3289 uint8_t read_addr; 3290 3291 priv = ifp->if_softc; 3292 3293 /* check if detaching */ 3294 if (priv == NULL || priv->gone != 0) 3295 return (ENXIO); 3296 3297 switch (command) { 3298 case SIOCSIFMTU: 3299 ifr = (struct ifreq *)data; 3300 3301 PRIV_LOCK(priv); 3302 mlx5_query_port_max_mtu(priv->mdev, &max_mtu); 3303 3304 if (ifr->ifr_mtu >= MLX5E_MTU_MIN && 3305 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) { 3306 int was_opened; 3307 3308 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 3309 if (was_opened) 3310 mlx5e_close_locked(ifp); 3311 3312 /* set new MTU */ 3313 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu); 3314 3315 if (was_opened) 3316 mlx5e_open_locked(ifp); 3317 } else { 3318 error = EINVAL; 3319 mlx5_en_err(ifp, 3320 "Invalid MTU value. Min val: %d, Max val: %d\n", 3321 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu)); 3322 } 3323 PRIV_UNLOCK(priv); 3324 break; 3325 case SIOCSIFFLAGS: 3326 if ((ifp->if_flags & IFF_UP) && 3327 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3328 mlx5e_set_rx_mode(ifp); 3329 break; 3330 } 3331 PRIV_LOCK(priv); 3332 if (ifp->if_flags & IFF_UP) { 3333 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3334 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3335 mlx5e_open_locked(ifp); 3336 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3337 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP); 3338 } 3339 } else { 3340 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3341 mlx5_set_port_status(priv->mdev, 3342 MLX5_PORT_DOWN); 3343 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 3344 mlx5e_close_locked(ifp); 3345 mlx5e_update_carrier(priv); 3346 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3347 } 3348 } 3349 PRIV_UNLOCK(priv); 3350 break; 3351 case SIOCADDMULTI: 3352 case SIOCDELMULTI: 3353 mlx5e_set_rx_mode(ifp); 3354 break; 3355 case SIOCSIFMEDIA: 3356 case SIOCGIFMEDIA: 3357 case SIOCGIFXMEDIA: 3358 ifr = (struct ifreq *)data; 3359 error = ifmedia_ioctl(ifp, ifr, &priv->media, command); 3360 break; 3361 case SIOCSIFCAP: 3362 ifr = (struct ifreq *)data; 3363 PRIV_LOCK(priv); 3364 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3365 3366 if (mask & IFCAP_TXCSUM) { 3367 ifp->if_capenable ^= IFCAP_TXCSUM; 3368 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 3369 3370 if (IFCAP_TSO4 & ifp->if_capenable && 3371 !(IFCAP_TXCSUM & ifp->if_capenable)) { 3372 mask &= ~IFCAP_TSO4; 3373 ifp->if_capenable &= ~IFCAP_TSO4; 3374 ifp->if_hwassist &= ~CSUM_IP_TSO; 3375 mlx5_en_err(ifp, 3376 "tso4 disabled due to -txcsum.\n"); 3377 } 3378 } 3379 if (mask & IFCAP_TXCSUM_IPV6) { 3380 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 3381 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 3382 3383 if (IFCAP_TSO6 & ifp->if_capenable && 3384 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 3385 mask &= ~IFCAP_TSO6; 3386 ifp->if_capenable &= ~IFCAP_TSO6; 3387 ifp->if_hwassist &= ~CSUM_IP6_TSO; 3388 mlx5_en_err(ifp, 3389 "tso6 disabled due to -txcsum6.\n"); 3390 } 3391 } 3392 if (mask & IFCAP_MEXTPG) 3393 ifp->if_capenable ^= IFCAP_MEXTPG; 3394 if (mask & IFCAP_TXTLS4) 3395 ifp->if_capenable ^= IFCAP_TXTLS4; 3396 if (mask & IFCAP_TXTLS6) 3397 ifp->if_capenable ^= IFCAP_TXTLS6; 3398 #ifdef RATELIMIT 3399 if (mask & IFCAP_TXTLS_RTLMT) 3400 ifp->if_capenable ^= IFCAP_TXTLS_RTLMT; 3401 #endif 3402 if (mask & IFCAP_RXCSUM) 3403 ifp->if_capenable ^= IFCAP_RXCSUM; 3404 if (mask & IFCAP_RXCSUM_IPV6) 3405 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 3406 if (mask & IFCAP_TSO4) { 3407 if (!(IFCAP_TSO4 & ifp->if_capenable) && 3408 !(IFCAP_TXCSUM & ifp->if_capenable)) { 3409 mlx5_en_err(ifp, "enable txcsum first.\n"); 3410 error = EAGAIN; 3411 goto out; 3412 } 3413 ifp->if_capenable ^= IFCAP_TSO4; 3414 ifp->if_hwassist ^= CSUM_IP_TSO; 3415 } 3416 if (mask & IFCAP_TSO6) { 3417 if (!(IFCAP_TSO6 & ifp->if_capenable) && 3418 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 3419 mlx5_en_err(ifp, "enable txcsum6 first.\n"); 3420 error = EAGAIN; 3421 goto out; 3422 } 3423 ifp->if_capenable ^= IFCAP_TSO6; 3424 ifp->if_hwassist ^= CSUM_IP6_TSO; 3425 } 3426 if (mask & IFCAP_VLAN_HWTSO) 3427 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3428 if (mask & IFCAP_VLAN_HWFILTER) { 3429 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) 3430 mlx5e_disable_vlan_filter(priv); 3431 else 3432 mlx5e_enable_vlan_filter(priv); 3433 3434 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER; 3435 } 3436 if (mask & IFCAP_VLAN_HWTAGGING) 3437 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3438 if (mask & IFCAP_WOL_MAGIC) 3439 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3440 if (mask & IFCAP_VXLAN_HWCSUM) { 3441 int was_opened = test_bit(MLX5E_STATE_OPENED, 3442 &priv->state); 3443 if (was_opened) 3444 mlx5e_close_locked(ifp); 3445 ifp->if_capenable ^= IFCAP_VXLAN_HWCSUM; 3446 ifp->if_hwassist ^= CSUM_INNER_IP | CSUM_INNER_IP_UDP | 3447 CSUM_INNER_IP_TCP | CSUM_INNER_IP6_UDP | 3448 CSUM_INNER_IP6_TCP; 3449 if (was_opened) 3450 mlx5e_open_locked(ifp); 3451 } 3452 if (mask & IFCAP_VXLAN_HWTSO) { 3453 ifp->if_capenable ^= IFCAP_VXLAN_HWTSO; 3454 ifp->if_hwassist ^= CSUM_INNER_IP_TSO | 3455 CSUM_INNER_IP6_TSO; 3456 } 3457 3458 VLAN_CAPABILITIES(ifp); 3459 /* turn off LRO means also turn of HW LRO - if it's on */ 3460 if (mask & IFCAP_LRO) { 3461 int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 3462 bool need_restart = false; 3463 3464 ifp->if_capenable ^= IFCAP_LRO; 3465 3466 /* figure out if updating HW LRO is needed */ 3467 if (!(ifp->if_capenable & IFCAP_LRO)) { 3468 if (priv->params.hw_lro_en) { 3469 priv->params.hw_lro_en = false; 3470 need_restart = true; 3471 } 3472 } else { 3473 if (priv->params.hw_lro_en == false && 3474 priv->params_ethtool.hw_lro != 0) { 3475 priv->params.hw_lro_en = true; 3476 need_restart = true; 3477 } 3478 } 3479 if (was_opened && need_restart) { 3480 mlx5e_close_locked(ifp); 3481 mlx5e_open_locked(ifp); 3482 } 3483 } 3484 if (mask & IFCAP_HWRXTSTMP) { 3485 ifp->if_capenable ^= IFCAP_HWRXTSTMP; 3486 if (ifp->if_capenable & IFCAP_HWRXTSTMP) { 3487 if (priv->clbr_done == 0) 3488 mlx5e_reset_calibration_callout(priv); 3489 } else { 3490 callout_drain(&priv->tstmp_clbr); 3491 priv->clbr_done = 0; 3492 } 3493 } 3494 out: 3495 PRIV_UNLOCK(priv); 3496 break; 3497 3498 case SIOCGI2C: 3499 ifr = (struct ifreq *)data; 3500 3501 /* 3502 * Copy from the user-space address ifr_data to the 3503 * kernel-space address i2c 3504 */ 3505 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 3506 if (error) 3507 break; 3508 3509 if (i2c.len > sizeof(i2c.data)) { 3510 error = EINVAL; 3511 break; 3512 } 3513 3514 PRIV_LOCK(priv); 3515 /* Get module_num which is required for the query_eeprom */ 3516 error = mlx5_query_module_num(priv->mdev, &module_num); 3517 if (error) { 3518 mlx5_en_err(ifp, 3519 "Query module num failed, eeprom reading is not supported\n"); 3520 error = EINVAL; 3521 goto err_i2c; 3522 } 3523 /* Check if module is present before doing an access */ 3524 module_status = mlx5_query_module_status(priv->mdev, module_num); 3525 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED) { 3526 error = EINVAL; 3527 goto err_i2c; 3528 } 3529 /* 3530 * Currently 0XA0 and 0xA2 are the only addresses permitted. 3531 * The internal conversion is as follows: 3532 */ 3533 if (i2c.dev_addr == 0xA0) 3534 read_addr = MLX5_I2C_ADDR_LOW; 3535 else if (i2c.dev_addr == 0xA2) 3536 read_addr = MLX5_I2C_ADDR_HIGH; 3537 else { 3538 mlx5_en_err(ifp, 3539 "Query eeprom failed, Invalid Address: %X\n", 3540 i2c.dev_addr); 3541 error = EINVAL; 3542 goto err_i2c; 3543 } 3544 error = mlx5_query_eeprom(priv->mdev, 3545 read_addr, MLX5_EEPROM_LOW_PAGE, 3546 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num, 3547 (uint32_t *)i2c.data, &size_read); 3548 if (error) { 3549 mlx5_en_err(ifp, 3550 "Query eeprom failed, eeprom reading is not supported\n"); 3551 error = EINVAL; 3552 goto err_i2c; 3553 } 3554 3555 if (i2c.len > MLX5_EEPROM_MAX_BYTES) { 3556 error = mlx5_query_eeprom(priv->mdev, 3557 read_addr, MLX5_EEPROM_LOW_PAGE, 3558 (uint32_t)(i2c.offset + size_read), 3559 (uint32_t)(i2c.len - size_read), module_num, 3560 (uint32_t *)(i2c.data + size_read), &size_read); 3561 } 3562 if (error) { 3563 mlx5_en_err(ifp, 3564 "Query eeprom failed, eeprom reading is not supported\n"); 3565 error = EINVAL; 3566 goto err_i2c; 3567 } 3568 3569 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 3570 err_i2c: 3571 PRIV_UNLOCK(priv); 3572 break; 3573 case SIOCGIFDOWNREASON: 3574 ifdr = (struct ifdownreason *)data; 3575 bzero(ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg)); 3576 PRIV_LOCK(priv); 3577 error = -mlx5_query_pddr_troubleshooting_info(priv->mdev, NULL, 3578 ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg)); 3579 PRIV_UNLOCK(priv); 3580 if (error == 0) 3581 ifdr->ifdr_reason = IFDR_REASON_MSG; 3582 break; 3583 3584 case SIOCGIFRSSKEY: 3585 ifrk = (struct ifrsskey *)data; 3586 ifrk->ifrk_func = RSS_FUNC_TOEPLITZ; 3587 ifrk->ifrk_keylen = MLX5E_RSS_KEY_SIZE; 3588 CTASSERT(sizeof(ifrk->ifrk_key) >= MLX5E_RSS_KEY_SIZE); 3589 mlx5e_get_rss_key(ifrk->ifrk_key); 3590 break; 3591 3592 case SIOCGIFRSSHASH: 3593 ifrh = (struct ifrsshash *)data; 3594 ifrh->ifrh_func = RSS_FUNC_TOEPLITZ; 3595 ifrh->ifrh_types = 3596 RSS_TYPE_IPV4 | 3597 RSS_TYPE_TCP_IPV4 | 3598 RSS_TYPE_UDP_IPV4 | 3599 RSS_TYPE_IPV6 | 3600 RSS_TYPE_TCP_IPV6 | 3601 RSS_TYPE_UDP_IPV6; 3602 break; 3603 3604 default: 3605 error = ether_ioctl(ifp, command, data); 3606 break; 3607 } 3608 return (error); 3609 } 3610 3611 static int 3612 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev) 3613 { 3614 /* 3615 * TODO: uncoment once FW really sets all these bits if 3616 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap || 3617 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap || 3618 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return 3619 * -ENOTSUPP; 3620 */ 3621 3622 /* TODO: add more must-to-have features */ 3623 3624 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) 3625 return (-ENODEV); 3626 3627 return (0); 3628 } 3629 3630 static u16 3631 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev) 3632 { 3633 const int min_size = ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN; 3634 const int max_size = MLX5E_MAX_TX_INLINE; 3635 const int bf_buf_size = 3636 ((1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U) - 3637 (sizeof(struct mlx5e_tx_wqe) - 2); 3638 3639 /* verify against driver limits */ 3640 if (bf_buf_size > max_size) 3641 return (max_size); 3642 else if (bf_buf_size < min_size) 3643 return (min_size); 3644 else 3645 return (bf_buf_size); 3646 } 3647 3648 static int 3649 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev, 3650 struct mlx5e_priv *priv, 3651 int num_comp_vectors) 3652 { 3653 int err; 3654 3655 /* 3656 * TODO: Consider link speed for setting "log_sq_size", 3657 * "log_rq_size" and "cq_moderation_xxx": 3658 */ 3659 priv->params.log_sq_size = 3660 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; 3661 priv->params.log_rq_size = 3662 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; 3663 priv->params.rx_cq_moderation_usec = 3664 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 3665 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE : 3666 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; 3667 priv->params.rx_cq_moderation_mode = 3668 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0; 3669 priv->params.rx_cq_moderation_pkts = 3670 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; 3671 priv->params.tx_cq_moderation_usec = 3672 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; 3673 priv->params.tx_cq_moderation_pkts = 3674 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; 3675 priv->params.min_rx_wqes = 3676 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES; 3677 priv->params.rx_hash_log_tbl_sz = 3678 (order_base_2(num_comp_vectors) > 3679 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ? 3680 order_base_2(num_comp_vectors) : 3681 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ; 3682 priv->params.num_tc = 1; 3683 priv->params.default_vlan_prio = 0; 3684 priv->counter_set_id = -1; 3685 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev); 3686 3687 err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode); 3688 if (err) 3689 return (err); 3690 3691 /* 3692 * hw lro is currently defaulted to off. when it won't anymore we 3693 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)" 3694 */ 3695 priv->params.hw_lro_en = false; 3696 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; 3697 3698 /* 3699 * CQE zipping is currently defaulted to off. when it won't 3700 * anymore we will consider the HW capability: 3701 * "!!MLX5_CAP_GEN(mdev, cqe_compression)" 3702 */ 3703 priv->params.cqe_zipping_en = false; 3704 3705 priv->mdev = mdev; 3706 priv->params.num_channels = num_comp_vectors; 3707 priv->params.channels_rsss = 1; 3708 priv->order_base_2_num_channels = order_base_2(num_comp_vectors); 3709 priv->queue_mapping_channel_mask = 3710 roundup_pow_of_two(num_comp_vectors) - 1; 3711 priv->num_tc = priv->params.num_tc; 3712 priv->default_vlan_prio = priv->params.default_vlan_prio; 3713 3714 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work); 3715 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); 3716 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); 3717 3718 return (0); 3719 } 3720 3721 static void 3722 mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc) 3723 { 3724 bool ro_pci_enable = 3725 pci_get_relaxed_ordering_enabled(mdev->pdev->dev.bsddev); 3726 bool ro_write = MLX5_CAP_GEN(mdev, relaxed_ordering_write); 3727 bool ro_read = MLX5_CAP_GEN(mdev, relaxed_ordering_read); 3728 3729 MLX5_SET(mkc, mkc, relaxed_ordering_read, ro_pci_enable && ro_read); 3730 MLX5_SET(mkc, mkc, relaxed_ordering_write, ro_pci_enable && ro_write); 3731 } 3732 3733 static int 3734 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn, 3735 struct mlx5_core_mkey *mkey) 3736 { 3737 struct ifnet *ifp = priv->ifp; 3738 struct mlx5_core_dev *mdev = priv->mdev; 3739 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 3740 void *mkc; 3741 u32 *in; 3742 int err; 3743 3744 in = mlx5_vzalloc(inlen); 3745 if (in == NULL) { 3746 mlx5_en_err(ifp, "failed to allocate inbox\n"); 3747 return (-ENOMEM); 3748 } 3749 3750 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 3751 MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA); 3752 MLX5_SET(mkc, mkc, umr_en, 1); /* used by HW TLS */ 3753 MLX5_SET(mkc, mkc, lw, 1); 3754 MLX5_SET(mkc, mkc, lr, 1); 3755 mlx5e_mkey_set_relaxed_ordering(mdev, mkc); 3756 MLX5_SET(mkc, mkc, pd, pdn); 3757 MLX5_SET(mkc, mkc, length64, 1); 3758 MLX5_SET(mkc, mkc, qpn, 0xffffff); 3759 3760 err = mlx5_core_create_mkey(mdev, mkey, in, inlen); 3761 if (err) 3762 mlx5_en_err(ifp, "mlx5_core_create_mkey failed, %d\n", 3763 err); 3764 3765 kvfree(in); 3766 return (err); 3767 } 3768 3769 static const char *mlx5e_vport_stats_desc[] = { 3770 MLX5E_VPORT_STATS(MLX5E_STATS_DESC) 3771 }; 3772 3773 static const char *mlx5e_pport_stats_desc[] = { 3774 MLX5E_PPORT_STATS(MLX5E_STATS_DESC) 3775 }; 3776 3777 static int 3778 mlx5e_priv_static_init(struct mlx5e_priv *priv, struct mlx5_core_dev *mdev, 3779 const uint32_t channels) 3780 { 3781 uint32_t x; 3782 int err; 3783 3784 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF); 3785 sx_init(&priv->state_lock, "mlx5state"); 3786 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0); 3787 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock); 3788 for (x = 0; x != channels; x++) 3789 mlx5e_chan_static_init(priv, &priv->channel[x], x); 3790 3791 for (x = 0; x != channels; x++) { 3792 err = mlx5_alloc_bfreg(mdev, &priv->channel[x].bfreg, false, false); 3793 if (err) 3794 goto err_alloc_bfreg; 3795 } 3796 return (0); 3797 3798 err_alloc_bfreg: 3799 while (x--) 3800 mlx5_free_bfreg(mdev, &priv->channel[x].bfreg); 3801 3802 for (x = 0; x != channels; x++) 3803 mlx5e_chan_static_destroy(&priv->channel[x]); 3804 callout_drain(&priv->watchdog); 3805 mtx_destroy(&priv->async_events_mtx); 3806 sx_destroy(&priv->state_lock); 3807 return (err); 3808 } 3809 3810 static void 3811 mlx5e_priv_static_destroy(struct mlx5e_priv *priv, struct mlx5_core_dev *mdev, 3812 const uint32_t channels) 3813 { 3814 uint32_t x; 3815 3816 for (x = 0; x != channels; x++) 3817 mlx5_free_bfreg(mdev, &priv->channel[x].bfreg); 3818 for (x = 0; x != channels; x++) 3819 mlx5e_chan_static_destroy(&priv->channel[x]); 3820 callout_drain(&priv->watchdog); 3821 mtx_destroy(&priv->async_events_mtx); 3822 sx_destroy(&priv->state_lock); 3823 } 3824 3825 static int 3826 sysctl_firmware(SYSCTL_HANDLER_ARGS) 3827 { 3828 /* 3829 * %d.%d%.d the string format. 3830 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536. 3831 * We need at most 5 chars to store that. 3832 * It also has: two "." and NULL at the end, which means we need 18 3833 * (5*3 + 3) chars at most. 3834 */ 3835 char fw[18]; 3836 struct mlx5e_priv *priv = arg1; 3837 int error; 3838 3839 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev), 3840 fw_rev_sub(priv->mdev)); 3841 error = sysctl_handle_string(oidp, fw, sizeof(fw), req); 3842 return (error); 3843 } 3844 3845 static void 3846 mlx5e_disable_tx_dma(struct mlx5e_channel *ch) 3847 { 3848 int i; 3849 3850 for (i = 0; i < ch->priv->num_tc; i++) 3851 mlx5e_drain_sq(&ch->sq[i]); 3852 } 3853 3854 static void 3855 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq) 3856 { 3857 3858 sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP); 3859 sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8); 3860 mlx5e_tx_notify_hw(sq, sq->doorbell.d32); 3861 sq->doorbell.d64 = 0; 3862 } 3863 3864 void 3865 mlx5e_resume_sq(struct mlx5e_sq *sq) 3866 { 3867 int err; 3868 3869 /* check if already enabled */ 3870 if (READ_ONCE(sq->running) != 0) 3871 return; 3872 3873 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR, 3874 MLX5_SQC_STATE_RST); 3875 if (err != 0) { 3876 mlx5_en_err(sq->ifp, 3877 "mlx5e_modify_sq() from ERR to RST failed: %d\n", err); 3878 } 3879 3880 sq->cc = 0; 3881 sq->pc = 0; 3882 3883 /* reset doorbell prior to moving from RST to RDY */ 3884 mlx5e_reset_sq_doorbell_record(sq); 3885 3886 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, 3887 MLX5_SQC_STATE_RDY); 3888 if (err != 0) { 3889 mlx5_en_err(sq->ifp, 3890 "mlx5e_modify_sq() from RST to RDY failed: %d\n", err); 3891 } 3892 3893 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL; 3894 WRITE_ONCE(sq->running, 1); 3895 } 3896 3897 static void 3898 mlx5e_enable_tx_dma(struct mlx5e_channel *ch) 3899 { 3900 int i; 3901 3902 for (i = 0; i < ch->priv->num_tc; i++) 3903 mlx5e_resume_sq(&ch->sq[i]); 3904 } 3905 3906 static void 3907 mlx5e_disable_rx_dma(struct mlx5e_channel *ch) 3908 { 3909 struct mlx5e_rq *rq = &ch->rq; 3910 struct epoch_tracker et; 3911 int err; 3912 3913 mtx_lock(&rq->mtx); 3914 rq->enabled = 0; 3915 callout_stop(&rq->watchdog); 3916 mtx_unlock(&rq->mtx); 3917 3918 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 3919 if (err != 0) { 3920 mlx5_en_err(rq->ifp, 3921 "mlx5e_modify_rq() from RDY to RST failed: %d\n", err); 3922 } 3923 3924 while (!mlx5_wq_ll_is_empty(&rq->wq)) { 3925 msleep(1); 3926 NET_EPOCH_ENTER(et); 3927 rq->cq.mcq.comp(&rq->cq.mcq, NULL); 3928 NET_EPOCH_EXIT(et); 3929 } 3930 3931 /* 3932 * Transitioning into RST state will allow the FW to track less ERR state queues, 3933 * thus reducing the recv queue flushing time 3934 */ 3935 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST); 3936 if (err != 0) { 3937 mlx5_en_err(rq->ifp, 3938 "mlx5e_modify_rq() from ERR to RST failed: %d\n", err); 3939 } 3940 } 3941 3942 static void 3943 mlx5e_enable_rx_dma(struct mlx5e_channel *ch) 3944 { 3945 struct mlx5e_rq *rq = &ch->rq; 3946 struct epoch_tracker et; 3947 int err; 3948 3949 rq->wq.wqe_ctr = 0; 3950 mlx5_wq_ll_update_db_record(&rq->wq); 3951 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 3952 if (err != 0) { 3953 mlx5_en_err(rq->ifp, 3954 "mlx5e_modify_rq() from RST to RDY failed: %d\n", err); 3955 } 3956 3957 rq->enabled = 1; 3958 3959 NET_EPOCH_ENTER(et); 3960 rq->cq.mcq.comp(&rq->cq.mcq, NULL); 3961 NET_EPOCH_EXIT(et); 3962 } 3963 3964 void 3965 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value) 3966 { 3967 int i; 3968 3969 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3970 return; 3971 3972 for (i = 0; i < priv->params.num_channels; i++) { 3973 if (value) 3974 mlx5e_disable_tx_dma(&priv->channel[i]); 3975 else 3976 mlx5e_enable_tx_dma(&priv->channel[i]); 3977 } 3978 } 3979 3980 void 3981 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value) 3982 { 3983 int i; 3984 3985 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3986 return; 3987 3988 for (i = 0; i < priv->params.num_channels; i++) { 3989 if (value) 3990 mlx5e_disable_rx_dma(&priv->channel[i]); 3991 else 3992 mlx5e_enable_rx_dma(&priv->channel[i]); 3993 } 3994 } 3995 3996 static void 3997 mlx5e_add_hw_stats(struct mlx5e_priv *priv) 3998 { 3999 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 4000 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 4001 priv, 0, sysctl_firmware, "A", "HCA firmware version"); 4002 4003 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 4004 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0, 4005 "Board ID"); 4006 } 4007 4008 static int 4009 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS) 4010 { 4011 struct mlx5e_priv *priv = arg1; 4012 uint8_t temp[MLX5E_MAX_PRIORITY]; 4013 uint32_t tx_pfc; 4014 int err; 4015 int i; 4016 4017 PRIV_LOCK(priv); 4018 4019 tx_pfc = priv->params.tx_priority_flow_control; 4020 4021 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) 4022 temp[i] = (tx_pfc >> i) & 1; 4023 4024 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY); 4025 if (err || !req->newptr) 4026 goto done; 4027 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY); 4028 if (err) 4029 goto done; 4030 4031 priv->params.tx_priority_flow_control = 0; 4032 4033 /* range check input value */ 4034 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) { 4035 if (temp[i] > 1) { 4036 err = ERANGE; 4037 goto done; 4038 } 4039 priv->params.tx_priority_flow_control |= (temp[i] << i); 4040 } 4041 4042 /* check if update is required */ 4043 if (tx_pfc != priv->params.tx_priority_flow_control) 4044 err = -mlx5e_set_port_pfc(priv); 4045 done: 4046 if (err != 0) 4047 priv->params.tx_priority_flow_control= tx_pfc; 4048 PRIV_UNLOCK(priv); 4049 4050 return (err); 4051 } 4052 4053 static int 4054 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS) 4055 { 4056 struct mlx5e_priv *priv = arg1; 4057 uint8_t temp[MLX5E_MAX_PRIORITY]; 4058 uint32_t rx_pfc; 4059 int err; 4060 int i; 4061 4062 PRIV_LOCK(priv); 4063 4064 rx_pfc = priv->params.rx_priority_flow_control; 4065 4066 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) 4067 temp[i] = (rx_pfc >> i) & 1; 4068 4069 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY); 4070 if (err || !req->newptr) 4071 goto done; 4072 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY); 4073 if (err) 4074 goto done; 4075 4076 priv->params.rx_priority_flow_control = 0; 4077 4078 /* range check input value */ 4079 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) { 4080 if (temp[i] > 1) { 4081 err = ERANGE; 4082 goto done; 4083 } 4084 priv->params.rx_priority_flow_control |= (temp[i] << i); 4085 } 4086 4087 /* check if update is required */ 4088 if (rx_pfc != priv->params.rx_priority_flow_control) { 4089 err = -mlx5e_set_port_pfc(priv); 4090 if (err == 0 && priv->sw_is_port_buf_owner) 4091 err = mlx5e_update_buf_lossy(priv); 4092 } 4093 done: 4094 if (err != 0) 4095 priv->params.rx_priority_flow_control= rx_pfc; 4096 PRIV_UNLOCK(priv); 4097 4098 return (err); 4099 } 4100 4101 static void 4102 mlx5e_setup_pauseframes(struct mlx5e_priv *priv) 4103 { 4104 #if (__FreeBSD_version < 1100000) 4105 char path[96]; 4106 #endif 4107 int error; 4108 4109 /* enable pauseframes by default */ 4110 priv->params.tx_pauseframe_control = 1; 4111 priv->params.rx_pauseframe_control = 1; 4112 4113 /* disable ports flow control, PFC, by default */ 4114 priv->params.tx_priority_flow_control = 0; 4115 priv->params.rx_priority_flow_control = 0; 4116 4117 #if (__FreeBSD_version < 1100000) 4118 /* compute path for sysctl */ 4119 snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control", 4120 device_get_unit(priv->mdev->pdev->dev.bsddev)); 4121 4122 /* try to fetch tunable, if any */ 4123 TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control); 4124 4125 /* compute path for sysctl */ 4126 snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control", 4127 device_get_unit(priv->mdev->pdev->dev.bsddev)); 4128 4129 /* try to fetch tunable, if any */ 4130 TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control); 4131 #endif 4132 4133 /* register pauseframe SYSCTLs */ 4134 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4135 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN, 4136 &priv->params.tx_pauseframe_control, 0, 4137 "Set to enable TX pause frames. Clear to disable."); 4138 4139 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4140 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN, 4141 &priv->params.rx_pauseframe_control, 0, 4142 "Set to enable RX pause frames. Clear to disable."); 4143 4144 /* register priority flow control, PFC, SYSCTLs */ 4145 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4146 OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN | 4147 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU", 4148 "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable."); 4149 4150 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4151 OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN | 4152 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU", 4153 "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable."); 4154 4155 PRIV_LOCK(priv); 4156 4157 /* range check */ 4158 priv->params.tx_pauseframe_control = 4159 priv->params.tx_pauseframe_control ? 1 : 0; 4160 priv->params.rx_pauseframe_control = 4161 priv->params.rx_pauseframe_control ? 1 : 0; 4162 4163 /* update firmware */ 4164 error = mlx5e_set_port_pause_and_pfc(priv); 4165 if (error == -EINVAL) { 4166 mlx5_en_err(priv->ifp, 4167 "Global pauseframes must be disabled before enabling PFC.\n"); 4168 priv->params.rx_priority_flow_control = 0; 4169 priv->params.tx_priority_flow_control = 0; 4170 4171 /* update firmware */ 4172 (void) mlx5e_set_port_pause_and_pfc(priv); 4173 } 4174 PRIV_UNLOCK(priv); 4175 } 4176 4177 int 4178 mlx5e_ul_snd_tag_alloc(struct ifnet *ifp, 4179 union if_snd_tag_alloc_params *params, 4180 struct m_snd_tag **ppmt) 4181 { 4182 struct mlx5e_priv *priv; 4183 struct mlx5e_channel *pch; 4184 4185 priv = ifp->if_softc; 4186 4187 if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) { 4188 return (EOPNOTSUPP); 4189 } else { 4190 /* keep this code synced with mlx5e_select_queue() */ 4191 u32 ch = priv->params.num_channels; 4192 #ifdef RSS 4193 u32 temp; 4194 4195 if (rss_hash2bucket(params->hdr.flowid, 4196 params->hdr.flowtype, &temp) == 0) 4197 ch = temp % ch; 4198 else 4199 #endif 4200 ch = (params->hdr.flowid % 128) % ch; 4201 4202 /* 4203 * NOTE: The channels array is only freed at detach 4204 * and it safe to return a pointer to the send tag 4205 * inside the channels structure as long as we 4206 * reference the priv. 4207 */ 4208 pch = priv->channel + ch; 4209 4210 /* check if send queue is not running */ 4211 if (unlikely(pch->sq[0].running == 0)) 4212 return (ENXIO); 4213 m_snd_tag_ref(&pch->tag); 4214 *ppmt = &pch->tag; 4215 return (0); 4216 } 4217 } 4218 4219 int 4220 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params) 4221 { 4222 struct mlx5e_channel *pch = 4223 container_of(pmt, struct mlx5e_channel, tag); 4224 4225 params->unlimited.max_rate = -1ULL; 4226 params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]); 4227 return (0); 4228 } 4229 4230 void 4231 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt) 4232 { 4233 struct mlx5e_channel *pch = 4234 container_of(pmt, struct mlx5e_channel, tag); 4235 4236 complete(&pch->completion); 4237 } 4238 4239 static int 4240 mlx5e_snd_tag_alloc(struct ifnet *ifp, 4241 union if_snd_tag_alloc_params *params, 4242 struct m_snd_tag **ppmt) 4243 { 4244 4245 switch (params->hdr.type) { 4246 #ifdef RATELIMIT 4247 case IF_SND_TAG_TYPE_RATE_LIMIT: 4248 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt)); 4249 #ifdef KERN_TLS 4250 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT: 4251 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt)); 4252 #endif 4253 #endif 4254 case IF_SND_TAG_TYPE_UNLIMITED: 4255 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt)); 4256 #ifdef KERN_TLS 4257 case IF_SND_TAG_TYPE_TLS: 4258 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt)); 4259 #endif 4260 default: 4261 return (EOPNOTSUPP); 4262 } 4263 } 4264 4265 static int 4266 mlx5e_snd_tag_modify(struct m_snd_tag *pmt, union if_snd_tag_modify_params *params) 4267 { 4268 4269 switch (pmt->type) { 4270 #ifdef RATELIMIT 4271 case IF_SND_TAG_TYPE_RATE_LIMIT: 4272 return (mlx5e_rl_snd_tag_modify(pmt, params)); 4273 #ifdef KERN_TLS 4274 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT: 4275 return (mlx5e_tls_snd_tag_modify(pmt, params)); 4276 #endif 4277 #endif 4278 case IF_SND_TAG_TYPE_UNLIMITED: 4279 #ifdef KERN_TLS 4280 case IF_SND_TAG_TYPE_TLS: 4281 #endif 4282 default: 4283 return (EOPNOTSUPP); 4284 } 4285 } 4286 4287 static int 4288 mlx5e_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params) 4289 { 4290 4291 switch (pmt->type) { 4292 #ifdef RATELIMIT 4293 case IF_SND_TAG_TYPE_RATE_LIMIT: 4294 return (mlx5e_rl_snd_tag_query(pmt, params)); 4295 #ifdef KERN_TLS 4296 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT: 4297 return (mlx5e_tls_snd_tag_query(pmt, params)); 4298 #endif 4299 #endif 4300 case IF_SND_TAG_TYPE_UNLIMITED: 4301 return (mlx5e_ul_snd_tag_query(pmt, params)); 4302 #ifdef KERN_TLS 4303 case IF_SND_TAG_TYPE_TLS: 4304 return (mlx5e_tls_snd_tag_query(pmt, params)); 4305 #endif 4306 default: 4307 return (EOPNOTSUPP); 4308 } 4309 } 4310 4311 #ifdef RATELIMIT 4312 #define NUM_HDWR_RATES_MLX 13 4313 static const uint64_t adapter_rates_mlx[NUM_HDWR_RATES_MLX] = { 4314 135375, /* 1,083,000 */ 4315 180500, /* 1,444,000 */ 4316 270750, /* 2,166,000 */ 4317 361000, /* 2,888,000 */ 4318 541500, /* 4,332,000 */ 4319 721875, /* 5,775,000 */ 4320 1082875, /* 8,663,000 */ 4321 1443875, /* 11,551,000 */ 4322 2165750, /* 17,326,000 */ 4323 2887750, /* 23,102,000 */ 4324 4331625, /* 34,653,000 */ 4325 5775500, /* 46,204,000 */ 4326 8663125 /* 69,305,000 */ 4327 }; 4328 4329 static void 4330 mlx5e_ratelimit_query(struct ifnet *ifp __unused, struct if_ratelimit_query_results *q) 4331 { 4332 /* 4333 * This function needs updating by the driver maintainer! 4334 * For the MLX card there are currently (ConectX-4?) 13 4335 * pre-set rates and others i.e. ConnectX-5, 6, 7?? 4336 * 4337 * This will change based on later adapters 4338 * and this code should be updated to look at ifp 4339 * and figure out the specific adapter type 4340 * settings i.e. how many rates as well 4341 * as if they are fixed (as is shown here) or 4342 * if they are dynamic (example chelsio t4). Also if there 4343 * is a maximum number of flows that the adapter 4344 * can handle that too needs to be updated in 4345 * the max_flows field. 4346 */ 4347 q->rate_table = adapter_rates_mlx; 4348 q->flags = RT_IS_FIXED_TABLE; 4349 q->max_flows = 0; /* mlx has no limit */ 4350 q->number_of_rates = NUM_HDWR_RATES_MLX; 4351 q->min_segment_burst = 1; 4352 } 4353 #endif 4354 4355 static void 4356 mlx5e_snd_tag_free(struct m_snd_tag *pmt) 4357 { 4358 4359 switch (pmt->type) { 4360 #ifdef RATELIMIT 4361 case IF_SND_TAG_TYPE_RATE_LIMIT: 4362 mlx5e_rl_snd_tag_free(pmt); 4363 break; 4364 #ifdef KERN_TLS 4365 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT: 4366 mlx5e_tls_snd_tag_free(pmt); 4367 break; 4368 #endif 4369 #endif 4370 case IF_SND_TAG_TYPE_UNLIMITED: 4371 mlx5e_ul_snd_tag_free(pmt); 4372 break; 4373 #ifdef KERN_TLS 4374 case IF_SND_TAG_TYPE_TLS: 4375 mlx5e_tls_snd_tag_free(pmt); 4376 break; 4377 #endif 4378 default: 4379 break; 4380 } 4381 } 4382 4383 static void 4384 mlx5e_ifm_add(struct mlx5e_priv *priv, int type) 4385 { 4386 ifmedia_add(&priv->media, type | IFM_ETHER, 0, NULL); 4387 ifmedia_add(&priv->media, type | IFM_ETHER | 4388 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 4389 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_RXPAUSE, 0, NULL); 4390 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_TXPAUSE, 0, NULL); 4391 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX, 0, NULL); 4392 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX | 4393 IFM_ETH_RXPAUSE, 0, NULL); 4394 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX | 4395 IFM_ETH_TXPAUSE, 0, NULL); 4396 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX | 4397 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 4398 } 4399 4400 static void * 4401 mlx5e_create_ifp(struct mlx5_core_dev *mdev) 4402 { 4403 struct ifnet *ifp; 4404 struct mlx5e_priv *priv; 4405 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4); 4406 struct sysctl_oid_list *child; 4407 int ncv = mdev->priv.eq_table.num_comp_vectors; 4408 char unit[16]; 4409 struct pfil_head_args pa; 4410 int err; 4411 u32 eth_proto_cap; 4412 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 4413 bool ext; 4414 struct media media_entry = {}; 4415 4416 if (mlx5e_check_required_hca_cap(mdev)) { 4417 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n"); 4418 return (NULL); 4419 } 4420 4421 /* 4422 * Try to allocate the priv and make room for worst-case 4423 * number of channel structures: 4424 */ 4425 priv = malloc_domainset(sizeof(*priv) + 4426 (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors), 4427 M_MLX5EN, mlx5_dev_domainset(mdev), M_WAITOK | M_ZERO); 4428 4429 ifp = priv->ifp = if_alloc_dev(IFT_ETHER, mdev->pdev->dev.bsddev); 4430 if (ifp == NULL) { 4431 mlx5_core_err(mdev, "if_alloc() failed\n"); 4432 goto err_free_priv; 4433 } 4434 /* setup all static fields */ 4435 if (mlx5e_priv_static_init(priv, mdev, mdev->priv.eq_table.num_comp_vectors)) { 4436 mlx5_core_err(mdev, "mlx5e_priv_static_init() failed\n"); 4437 goto err_free_ifp; 4438 } 4439 4440 ifp->if_softc = priv; 4441 if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev)); 4442 ifp->if_mtu = ETHERMTU; 4443 ifp->if_init = mlx5e_open; 4444 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 4445 IFF_KNOWSEPOCH; 4446 ifp->if_ioctl = mlx5e_ioctl; 4447 ifp->if_transmit = mlx5e_xmit; 4448 ifp->if_qflush = if_qflush; 4449 #if (__FreeBSD_version >= 1100000) 4450 ifp->if_get_counter = mlx5e_get_counter; 4451 #endif 4452 ifp->if_snd.ifq_maxlen = ifqmaxlen; 4453 /* 4454 * Set driver features 4455 */ 4456 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6; 4457 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 4458 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER; 4459 ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU; 4460 ifp->if_capabilities |= IFCAP_LRO; 4461 ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO; 4462 ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP; 4463 ifp->if_capabilities |= IFCAP_MEXTPG; 4464 ifp->if_capabilities |= IFCAP_TXTLS4 | IFCAP_TXTLS6; 4465 #ifdef RATELIMIT 4466 ifp->if_capabilities |= IFCAP_TXRTLMT | IFCAP_TXTLS_RTLMT; 4467 #endif 4468 ifp->if_capabilities |= IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO; 4469 ifp->if_snd_tag_alloc = mlx5e_snd_tag_alloc; 4470 ifp->if_snd_tag_free = mlx5e_snd_tag_free; 4471 ifp->if_snd_tag_modify = mlx5e_snd_tag_modify; 4472 ifp->if_snd_tag_query = mlx5e_snd_tag_query; 4473 #ifdef RATELIMIT 4474 ifp->if_ratelimit_query = mlx5e_ratelimit_query; 4475 #endif 4476 /* set TSO limits so that we don't have to drop TX packets */ 4477 ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 4478 ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */; 4479 ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE; 4480 4481 ifp->if_capenable = ifp->if_capabilities; 4482 ifp->if_hwassist = 0; 4483 if (ifp->if_capenable & IFCAP_TSO) 4484 ifp->if_hwassist |= CSUM_TSO; 4485 if (ifp->if_capenable & IFCAP_TXCSUM) 4486 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP); 4487 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6) 4488 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 4489 if (ifp->if_capabilities & IFCAP_VXLAN_HWCSUM) 4490 ifp->if_hwassist |= CSUM_INNER_IP6_UDP | CSUM_INNER_IP6_TCP | 4491 CSUM_INNER_IP | CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP | 4492 CSUM_ENCAP_VXLAN; 4493 if (ifp->if_capabilities & IFCAP_VXLAN_HWTSO) 4494 ifp->if_hwassist |= CSUM_INNER_IP6_TSO | CSUM_INNER_IP_TSO; 4495 4496 /* ifnet sysctl tree */ 4497 sysctl_ctx_init(&priv->sysctl_ctx); 4498 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev), 4499 OID_AUTO, ifp->if_dname, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 4500 "MLX5 ethernet - interface name"); 4501 if (priv->sysctl_ifnet == NULL) { 4502 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4503 goto err_free_sysctl; 4504 } 4505 snprintf(unit, sizeof(unit), "%d", ifp->if_dunit); 4506 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4507 OID_AUTO, unit, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 4508 "MLX5 ethernet - interface unit"); 4509 if (priv->sysctl_ifnet == NULL) { 4510 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4511 goto err_free_sysctl; 4512 } 4513 4514 /* HW sysctl tree */ 4515 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev)); 4516 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child, 4517 OID_AUTO, "hw", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 4518 "MLX5 ethernet dev hw"); 4519 if (priv->sysctl_hw == NULL) { 4520 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4521 goto err_free_sysctl; 4522 } 4523 4524 err = mlx5e_build_ifp_priv(mdev, priv, ncv); 4525 if (err) { 4526 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err); 4527 goto err_free_sysctl; 4528 } 4529 4530 /* reuse mlx5core's watchdog workqueue */ 4531 priv->wq = mdev->priv.health.wq_watchdog; 4532 4533 err = mlx5_core_alloc_pd(mdev, &priv->pdn, 0); 4534 if (err) { 4535 mlx5_en_err(ifp, "mlx5_core_alloc_pd failed, %d\n", err); 4536 goto err_free_wq; 4537 } 4538 err = mlx5_alloc_transport_domain(mdev, &priv->tdn, 0); 4539 if (err) { 4540 mlx5_en_err(ifp, 4541 "mlx5_alloc_transport_domain failed, %d\n", err); 4542 goto err_dealloc_pd; 4543 } 4544 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr); 4545 if (err) { 4546 mlx5_en_err(ifp, "mlx5e_create_mkey failed, %d\n", err); 4547 goto err_dealloc_transport_domain; 4548 } 4549 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr); 4550 4551 /* check if we should generate a random MAC address */ 4552 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 && 4553 is_zero_ether_addr(dev_addr)) { 4554 random_ether_addr(dev_addr); 4555 mlx5_en_err(ifp, "Assigned random MAC address\n"); 4556 } 4557 4558 err = mlx5e_rl_init(priv); 4559 if (err) { 4560 mlx5_en_err(ifp, "mlx5e_rl_init failed, %d\n", err); 4561 goto err_create_mkey; 4562 } 4563 4564 err = mlx5e_tls_init(priv); 4565 if (err) { 4566 if_printf(ifp, "%s: mlx5e_tls_init failed\n", __func__); 4567 goto err_rl_init; 4568 } 4569 4570 /* set default MTU */ 4571 mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu); 4572 4573 /* Set default media status */ 4574 priv->media_status_last = IFM_AVALID; 4575 priv->media_active_last = IFM_ETHER | IFM_AUTO | IFM_FDX; 4576 4577 /* setup default pauseframes configuration */ 4578 mlx5e_setup_pauseframes(priv); 4579 4580 /* Setup supported medias */ 4581 if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) { 4582 ext = MLX5_CAP_PCAM_FEATURE(mdev, 4583 ptys_extended_ethernet); 4584 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 4585 eth_proto_capability); 4586 } else { 4587 ext = false; 4588 eth_proto_cap = 0; 4589 mlx5_en_err(ifp, "Query port media capability failed, %d\n", err); 4590 } 4591 4592 ifmedia_init(&priv->media, IFM_IMASK, 4593 mlx5e_media_change, mlx5e_media_status); 4594 4595 if (ext) { 4596 for (unsigned i = 0; i != MLX5E_EXT_LINK_SPEEDS_NUMBER; i++) { 4597 /* check if hardware has the right capability */ 4598 if (MLX5E_PROT_MASK(i) & ~eth_proto_cap) 4599 continue; 4600 for (unsigned j = 0; j != MLX5E_CABLE_TYPE_NUMBER; j++) { 4601 media_entry = mlx5e_ext_mode_table[i][j]; 4602 if (media_entry.subtype == 0) 4603 continue; 4604 /* check if this subtype was already added */ 4605 for (unsigned k = 0; k != i; k++) { 4606 /* check if hardware has the right capability */ 4607 if (MLX5E_PROT_MASK(k) & ~eth_proto_cap) 4608 continue; 4609 for (unsigned m = 0; m != MLX5E_CABLE_TYPE_NUMBER; m++) { 4610 if (media_entry.subtype == mlx5e_ext_mode_table[k][m].subtype) 4611 goto skip_ext_media; 4612 } 4613 } 4614 mlx5e_ifm_add(priv, media_entry.subtype); 4615 skip_ext_media:; 4616 } 4617 } 4618 } else { 4619 for (unsigned i = 0; i != MLX5E_LINK_SPEEDS_NUMBER; i++) { 4620 media_entry = mlx5e_mode_table[i]; 4621 if (media_entry.subtype == 0) 4622 continue; 4623 if (MLX5E_PROT_MASK(i) & ~eth_proto_cap) 4624 continue; 4625 /* check if this subtype was already added */ 4626 for (unsigned k = 0; k != i; k++) { 4627 if (media_entry.subtype == mlx5e_mode_table[k].subtype) 4628 goto skip_media; 4629 } 4630 mlx5e_ifm_add(priv, media_entry.subtype); 4631 4632 /* NOTE: 10G ER and LR shares the same entry */ 4633 if (media_entry.subtype == IFM_10G_ER) 4634 mlx5e_ifm_add(priv, IFM_10G_LR); 4635 skip_media:; 4636 } 4637 } 4638 4639 mlx5e_ifm_add(priv, IFM_AUTO); 4640 4641 /* Set autoselect by default */ 4642 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX | 4643 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE); 4644 4645 DEBUGNET_SET(ifp, mlx5_en); 4646 4647 ether_ifattach(ifp, dev_addr); 4648 4649 /* Register for VLAN events */ 4650 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config, 4651 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST); 4652 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig, 4653 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST); 4654 4655 /* Register for VxLAN events */ 4656 priv->vxlan_start = EVENTHANDLER_REGISTER(vxlan_start, 4657 mlx5e_vxlan_start, priv, EVENTHANDLER_PRI_ANY); 4658 priv->vxlan_stop = EVENTHANDLER_REGISTER(vxlan_stop, 4659 mlx5e_vxlan_stop, priv, EVENTHANDLER_PRI_ANY); 4660 4661 /* Link is down by default */ 4662 if_link_state_change(ifp, LINK_STATE_DOWN); 4663 4664 mlx5e_enable_async_events(priv); 4665 4666 mlx5e_add_hw_stats(priv); 4667 4668 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4669 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM, 4670 priv->stats.vport.arg); 4671 4672 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4673 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM, 4674 priv->stats.pport.arg); 4675 4676 mlx5e_create_ethtool(priv); 4677 4678 mtx_lock(&priv->async_events_mtx); 4679 mlx5e_update_stats(priv); 4680 mtx_unlock(&priv->async_events_mtx); 4681 4682 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4683 OID_AUTO, "rx_clbr_done", CTLFLAG_RD, 4684 &priv->clbr_done, 0, 4685 "RX timestamps calibration state"); 4686 callout_init(&priv->tstmp_clbr, CALLOUT_DIRECT); 4687 mlx5e_reset_calibration_callout(priv); 4688 4689 pa.pa_version = PFIL_VERSION; 4690 pa.pa_flags = PFIL_IN; 4691 pa.pa_type = PFIL_TYPE_ETHERNET; 4692 pa.pa_headname = ifp->if_xname; 4693 priv->pfil = pfil_head_register(&pa); 4694 4695 return (priv); 4696 4697 err_rl_init: 4698 mlx5e_rl_cleanup(priv); 4699 4700 err_create_mkey: 4701 mlx5_core_destroy_mkey(priv->mdev, &priv->mr); 4702 4703 err_dealloc_transport_domain: 4704 mlx5_dealloc_transport_domain(mdev, priv->tdn, 0); 4705 4706 err_dealloc_pd: 4707 mlx5_core_dealloc_pd(mdev, priv->pdn, 0); 4708 4709 err_free_wq: 4710 flush_workqueue(priv->wq); 4711 4712 err_free_sysctl: 4713 sysctl_ctx_free(&priv->sysctl_ctx); 4714 if (priv->sysctl_debug) 4715 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx); 4716 mlx5e_priv_static_destroy(priv, mdev, mdev->priv.eq_table.num_comp_vectors); 4717 4718 err_free_ifp: 4719 if_free(ifp); 4720 4721 err_free_priv: 4722 free(priv, M_MLX5EN); 4723 return (NULL); 4724 } 4725 4726 static void 4727 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv) 4728 { 4729 struct mlx5e_priv *priv = vpriv; 4730 struct ifnet *ifp = priv->ifp; 4731 4732 /* don't allow more IOCTLs */ 4733 priv->gone = 1; 4734 4735 /* XXX wait a bit to allow IOCTL handlers to complete */ 4736 pause("W", hz); 4737 4738 #ifdef RATELIMIT 4739 /* 4740 * The kernel can have reference(s) via the m_snd_tag's into 4741 * the ratelimit channels, and these must go away before 4742 * detaching: 4743 */ 4744 while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) { 4745 mlx5_en_err(priv->ifp, 4746 "Waiting for all ratelimit connections to terminate\n"); 4747 pause("W", hz); 4748 } 4749 #endif 4750 4751 #ifdef KERN_TLS 4752 /* wait for all TLS tags to get freed */ 4753 while (priv->tls.init != 0 && 4754 uma_zone_get_cur(priv->tls.zone) != 0) { 4755 mlx5_en_err(priv->ifp, 4756 "Waiting for all TLS connections to terminate\n"); 4757 pause("W", hz); 4758 } 4759 #endif 4760 /* wait for all unlimited send tags to complete */ 4761 mlx5e_priv_wait_for_completion(priv, mdev->priv.eq_table.num_comp_vectors); 4762 4763 /* stop watchdog timer */ 4764 callout_drain(&priv->watchdog); 4765 4766 callout_drain(&priv->tstmp_clbr); 4767 4768 if (priv->vlan_attach != NULL) 4769 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach); 4770 if (priv->vlan_detach != NULL) 4771 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach); 4772 if (priv->vxlan_start != NULL) 4773 EVENTHANDLER_DEREGISTER(vxlan_start, priv->vxlan_start); 4774 if (priv->vxlan_stop != NULL) 4775 EVENTHANDLER_DEREGISTER(vxlan_stop, priv->vxlan_stop); 4776 4777 /* make sure device gets closed */ 4778 PRIV_LOCK(priv); 4779 mlx5e_close_locked(ifp); 4780 PRIV_UNLOCK(priv); 4781 4782 /* deregister pfil */ 4783 if (priv->pfil != NULL) { 4784 pfil_head_unregister(priv->pfil); 4785 priv->pfil = NULL; 4786 } 4787 4788 /* unregister device */ 4789 ifmedia_removeall(&priv->media); 4790 ether_ifdetach(ifp); 4791 4792 mlx5e_tls_cleanup(priv); 4793 mlx5e_rl_cleanup(priv); 4794 4795 /* destroy all remaining sysctl nodes */ 4796 sysctl_ctx_free(&priv->stats.vport.ctx); 4797 sysctl_ctx_free(&priv->stats.pport.ctx); 4798 if (priv->sysctl_debug) 4799 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx); 4800 sysctl_ctx_free(&priv->sysctl_ctx); 4801 4802 mlx5_core_destroy_mkey(priv->mdev, &priv->mr); 4803 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn, 0); 4804 mlx5_core_dealloc_pd(priv->mdev, priv->pdn, 0); 4805 mlx5e_disable_async_events(priv); 4806 flush_workqueue(priv->wq); 4807 mlx5e_priv_static_destroy(priv, mdev, mdev->priv.eq_table.num_comp_vectors); 4808 if_free(ifp); 4809 free(priv, M_MLX5EN); 4810 } 4811 4812 #ifdef DEBUGNET 4813 static void 4814 mlx5_en_debugnet_init(struct ifnet *dev, int *nrxr, int *ncl, int *clsize) 4815 { 4816 struct mlx5e_priv *priv = if_getsoftc(dev); 4817 4818 PRIV_LOCK(priv); 4819 *nrxr = priv->params.num_channels; 4820 *ncl = DEBUGNET_MAX_IN_FLIGHT; 4821 *clsize = MLX5E_MAX_RX_BYTES; 4822 PRIV_UNLOCK(priv); 4823 } 4824 4825 static void 4826 mlx5_en_debugnet_event(struct ifnet *dev, enum debugnet_ev event) 4827 { 4828 } 4829 4830 static int 4831 mlx5_en_debugnet_transmit(struct ifnet *dev, struct mbuf *m) 4832 { 4833 struct mlx5e_priv *priv = if_getsoftc(dev); 4834 struct mlx5e_sq *sq; 4835 int err; 4836 4837 if ((if_getdrvflags(dev) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4838 IFF_DRV_RUNNING || (priv->media_status_last & IFM_ACTIVE) == 0) 4839 return (ENOENT); 4840 4841 sq = &priv->channel[0].sq[0]; 4842 4843 if (sq->running == 0) { 4844 m_freem(m); 4845 return (ENOENT); 4846 } 4847 4848 if (mlx5e_sq_xmit(sq, &m) != 0) { 4849 m_freem(m); 4850 err = ENOBUFS; 4851 } else { 4852 err = 0; 4853 } 4854 4855 if (likely(sq->doorbell.d64 != 0)) { 4856 mlx5e_tx_notify_hw(sq, sq->doorbell.d32); 4857 sq->doorbell.d64 = 0; 4858 } 4859 return (err); 4860 } 4861 4862 static int 4863 mlx5_en_debugnet_poll(struct ifnet *dev, int count) 4864 { 4865 struct mlx5e_priv *priv = if_getsoftc(dev); 4866 4867 if ((if_getdrvflags(dev) & IFF_DRV_RUNNING) == 0 || 4868 (priv->media_status_last & IFM_ACTIVE) == 0) 4869 return (ENOENT); 4870 4871 mlx5_poll_interrupts(priv->mdev); 4872 4873 return (0); 4874 } 4875 #endif /* DEBUGNET */ 4876 4877 static void * 4878 mlx5e_get_ifp(void *vpriv) 4879 { 4880 struct mlx5e_priv *priv = vpriv; 4881 4882 return (priv->ifp); 4883 } 4884 4885 static struct mlx5_interface mlx5e_interface = { 4886 .add = mlx5e_create_ifp, 4887 .remove = mlx5e_destroy_ifp, 4888 .event = mlx5e_async_event, 4889 .protocol = MLX5_INTERFACE_PROTOCOL_ETH, 4890 .get_dev = mlx5e_get_ifp, 4891 }; 4892 4893 void 4894 mlx5e_init(void) 4895 { 4896 mlx5_register_interface(&mlx5e_interface); 4897 } 4898 4899 void 4900 mlx5e_cleanup(void) 4901 { 4902 mlx5_unregister_interface(&mlx5e_interface); 4903 } 4904 4905 module_init_order(mlx5e_init, SI_ORDER_SIXTH); 4906 module_exit_order(mlx5e_cleanup, SI_ORDER_SIXTH); 4907 4908 #if (__FreeBSD_version >= 1100000) 4909 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1); 4910 #endif 4911 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1); 4912 MODULE_VERSION(mlx5en, 1); 4913