1 /*- 2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include "en.h" 29 30 #include <sys/sockio.h> 31 #include <machine/atomic.h> 32 33 #define ETH_DRIVER_VERSION "3.1.0-dev" 34 char mlx5e_version[] = "Mellanox Ethernet driver" 35 " (" ETH_DRIVER_VERSION ")"; 36 37 struct mlx5e_channel_param { 38 struct mlx5e_rq_param rq; 39 struct mlx5e_sq_param sq; 40 struct mlx5e_cq_param rx_cq; 41 struct mlx5e_cq_param tx_cq; 42 }; 43 44 static const struct { 45 u32 subtype; 46 u64 baudrate; 47 } mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = { 48 49 [MLX5E_1000BASE_CX_SGMII] = { 50 .subtype = IFM_1000_CX_SGMII, 51 .baudrate = IF_Mbps(1000ULL), 52 }, 53 [MLX5E_1000BASE_KX] = { 54 .subtype = IFM_1000_KX, 55 .baudrate = IF_Mbps(1000ULL), 56 }, 57 [MLX5E_10GBASE_CX4] = { 58 .subtype = IFM_10G_CX4, 59 .baudrate = IF_Gbps(10ULL), 60 }, 61 [MLX5E_10GBASE_KX4] = { 62 .subtype = IFM_10G_KX4, 63 .baudrate = IF_Gbps(10ULL), 64 }, 65 [MLX5E_10GBASE_KR] = { 66 .subtype = IFM_10G_KR, 67 .baudrate = IF_Gbps(10ULL), 68 }, 69 [MLX5E_20GBASE_KR2] = { 70 .subtype = IFM_20G_KR2, 71 .baudrate = IF_Gbps(20ULL), 72 }, 73 [MLX5E_40GBASE_CR4] = { 74 .subtype = IFM_40G_CR4, 75 .baudrate = IF_Gbps(40ULL), 76 }, 77 [MLX5E_40GBASE_KR4] = { 78 .subtype = IFM_40G_KR4, 79 .baudrate = IF_Gbps(40ULL), 80 }, 81 [MLX5E_56GBASE_R4] = { 82 .subtype = IFM_56G_R4, 83 .baudrate = IF_Gbps(56ULL), 84 }, 85 [MLX5E_10GBASE_CR] = { 86 .subtype = IFM_10G_CR1, 87 .baudrate = IF_Gbps(10ULL), 88 }, 89 [MLX5E_10GBASE_SR] = { 90 .subtype = IFM_10G_SR, 91 .baudrate = IF_Gbps(10ULL), 92 }, 93 [MLX5E_10GBASE_LR] = { 94 .subtype = IFM_10G_LR, 95 .baudrate = IF_Gbps(10ULL), 96 }, 97 [MLX5E_40GBASE_SR4] = { 98 .subtype = IFM_40G_SR4, 99 .baudrate = IF_Gbps(40ULL), 100 }, 101 [MLX5E_40GBASE_LR4] = { 102 .subtype = IFM_40G_LR4, 103 .baudrate = IF_Gbps(40ULL), 104 }, 105 [MLX5E_100GBASE_CR4] = { 106 .subtype = IFM_100G_CR4, 107 .baudrate = IF_Gbps(100ULL), 108 }, 109 [MLX5E_100GBASE_SR4] = { 110 .subtype = IFM_100G_SR4, 111 .baudrate = IF_Gbps(100ULL), 112 }, 113 [MLX5E_100GBASE_KR4] = { 114 .subtype = IFM_100G_KR4, 115 .baudrate = IF_Gbps(100ULL), 116 }, 117 [MLX5E_100GBASE_LR4] = { 118 .subtype = IFM_100G_LR4, 119 .baudrate = IF_Gbps(100ULL), 120 }, 121 [MLX5E_100BASE_TX] = { 122 .subtype = IFM_100_TX, 123 .baudrate = IF_Mbps(100ULL), 124 }, 125 [MLX5E_100BASE_T] = { 126 .subtype = IFM_100_T, 127 .baudrate = IF_Mbps(100ULL), 128 }, 129 [MLX5E_10GBASE_T] = { 130 .subtype = IFM_10G_T, 131 .baudrate = IF_Gbps(10ULL), 132 }, 133 [MLX5E_25GBASE_CR] = { 134 .subtype = IFM_25G_CR, 135 .baudrate = IF_Gbps(25ULL), 136 }, 137 [MLX5E_25GBASE_KR] = { 138 .subtype = IFM_25G_KR, 139 .baudrate = IF_Gbps(25ULL), 140 }, 141 [MLX5E_25GBASE_SR] = { 142 .subtype = IFM_25G_SR, 143 .baudrate = IF_Gbps(25ULL), 144 }, 145 [MLX5E_50GBASE_CR2] = { 146 .subtype = IFM_50G_CR2, 147 .baudrate = IF_Gbps(50ULL), 148 }, 149 [MLX5E_50GBASE_KR2] = { 150 .subtype = IFM_50G_KR2, 151 .baudrate = IF_Gbps(50ULL), 152 }, 153 }; 154 155 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet"); 156 157 static void 158 mlx5e_update_carrier(struct mlx5e_priv *priv) 159 { 160 struct mlx5_core_dev *mdev = priv->mdev; 161 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 162 u32 eth_proto_oper; 163 int error; 164 u8 port_state; 165 u8 i; 166 167 port_state = mlx5_query_vport_state(mdev, 168 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0); 169 170 if (port_state == VPORT_STATE_UP) { 171 priv->media_status_last |= IFM_ACTIVE; 172 } else { 173 priv->media_status_last &= ~IFM_ACTIVE; 174 priv->media_active_last = IFM_ETHER; 175 if_link_state_change(priv->ifp, LINK_STATE_DOWN); 176 return; 177 } 178 179 error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN); 180 if (error) { 181 priv->media_active_last = IFM_ETHER; 182 priv->ifp->if_baudrate = 1; 183 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n", 184 __func__, error); 185 return; 186 } 187 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper); 188 189 for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) { 190 if (mlx5e_mode_table[i].baudrate == 0) 191 continue; 192 if (MLX5E_PROT_MASK(i) & eth_proto_oper) { 193 priv->ifp->if_baudrate = 194 mlx5e_mode_table[i].baudrate; 195 priv->media_active_last = 196 mlx5e_mode_table[i].subtype | IFM_ETHER | IFM_FDX; 197 } 198 } 199 if_link_state_change(priv->ifp, LINK_STATE_UP); 200 } 201 202 static void 203 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr) 204 { 205 struct mlx5e_priv *priv = dev->if_softc; 206 207 ifmr->ifm_status = priv->media_status_last; 208 ifmr->ifm_active = priv->media_active_last | 209 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) | 210 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0); 211 212 } 213 214 static u32 215 mlx5e_find_link_mode(u32 subtype) 216 { 217 u32 i; 218 u32 link_mode = 0; 219 220 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) { 221 if (mlx5e_mode_table[i].baudrate == 0) 222 continue; 223 if (mlx5e_mode_table[i].subtype == subtype) 224 link_mode |= MLX5E_PROT_MASK(i); 225 } 226 227 return (link_mode); 228 } 229 230 static int 231 mlx5e_media_change(struct ifnet *dev) 232 { 233 struct mlx5e_priv *priv = dev->if_softc; 234 struct mlx5_core_dev *mdev = priv->mdev; 235 u32 eth_proto_cap; 236 u32 link_mode; 237 int was_opened; 238 int locked; 239 int error; 240 241 locked = PRIV_LOCKED(priv); 242 if (!locked) 243 PRIV_LOCK(priv); 244 245 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) { 246 error = EINVAL; 247 goto done; 248 } 249 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media)); 250 251 /* query supported capabilities */ 252 error = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN); 253 if (error != 0) { 254 if_printf(dev, "Query port media capability failed\n"); 255 goto done; 256 } 257 /* check for autoselect */ 258 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) { 259 link_mode = eth_proto_cap; 260 if (link_mode == 0) { 261 if_printf(dev, "Port media capability is zero\n"); 262 error = EINVAL; 263 goto done; 264 } 265 } else { 266 link_mode = link_mode & eth_proto_cap; 267 if (link_mode == 0) { 268 if_printf(dev, "Not supported link mode requested\n"); 269 error = EINVAL; 270 goto done; 271 } 272 } 273 /* update pauseframe control bits */ 274 priv->params.rx_pauseframe_control = 275 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0; 276 priv->params.tx_pauseframe_control = 277 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0; 278 279 /* check if device is opened */ 280 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 281 282 /* reconfigure the hardware */ 283 mlx5_set_port_status(mdev, MLX5_PORT_DOWN); 284 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN); 285 mlx5_set_port_pause(mdev, 1, 286 priv->params.rx_pauseframe_control, 287 priv->params.tx_pauseframe_control); 288 if (was_opened) 289 mlx5_set_port_status(mdev, MLX5_PORT_UP); 290 291 done: 292 if (!locked) 293 PRIV_UNLOCK(priv); 294 return (error); 295 } 296 297 static void 298 mlx5e_update_carrier_work(struct work_struct *work) 299 { 300 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 301 update_carrier_work); 302 303 PRIV_LOCK(priv); 304 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) 305 mlx5e_update_carrier(priv); 306 PRIV_UNLOCK(priv); 307 } 308 309 static void 310 mlx5e_update_pport_counters(struct mlx5e_priv *priv) 311 { 312 struct mlx5_core_dev *mdev = priv->mdev; 313 struct mlx5e_pport_stats *s = &priv->stats.pport; 314 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug; 315 u32 *in; 316 u32 *out; 317 u64 *ptr; 318 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 319 unsigned x; 320 unsigned y; 321 322 in = mlx5_vzalloc(sz); 323 out = mlx5_vzalloc(sz); 324 if (in == NULL || out == NULL) 325 goto free_out; 326 327 ptr = (uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set); 328 329 MLX5_SET(ppcnt_reg, in, local_port, 1); 330 331 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP); 332 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 333 for (x = y = 0; x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++) 334 s->arg[y] = be64toh(ptr[x]); 335 336 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP); 337 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 338 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++) 339 s->arg[y] = be64toh(ptr[x]); 340 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM + 341 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++) 342 s_debug->arg[y] = be64toh(ptr[x]); 343 344 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP); 345 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 346 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++) 347 s_debug->arg[y] = be64toh(ptr[x]); 348 349 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP); 350 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 351 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++) 352 s_debug->arg[y] = be64toh(ptr[x]); 353 free_out: 354 kvfree(in); 355 kvfree(out); 356 } 357 358 static void 359 mlx5e_update_stats_work(struct work_struct *work) 360 { 361 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 362 update_stats_work); 363 struct mlx5_core_dev *mdev = priv->mdev; 364 struct mlx5e_vport_stats *s = &priv->stats.vport; 365 struct mlx5e_rq_stats *rq_stats; 366 struct mlx5e_sq_stats *sq_stats; 367 struct buf_ring *sq_br; 368 #if (__FreeBSD_version < 1100000) 369 struct ifnet *ifp = priv->ifp; 370 #endif 371 372 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)]; 373 u32 *out; 374 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out); 375 u64 tso_packets = 0; 376 u64 tso_bytes = 0; 377 u64 tx_queue_dropped = 0; 378 u64 tx_defragged = 0; 379 u64 tx_offload_none = 0; 380 u64 lro_packets = 0; 381 u64 lro_bytes = 0; 382 u64 sw_lro_queued = 0; 383 u64 sw_lro_flushed = 0; 384 u64 rx_csum_none = 0; 385 u64 rx_wqe_err = 0; 386 u32 rx_out_of_buffer = 0; 387 int i; 388 int j; 389 390 PRIV_LOCK(priv); 391 out = mlx5_vzalloc(outlen); 392 if (out == NULL) 393 goto free_out; 394 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 395 goto free_out; 396 397 /* Collect firts the SW counters and then HW for consistency */ 398 for (i = 0; i < priv->params.num_channels; i++) { 399 struct mlx5e_rq *rq = &priv->channel[i]->rq; 400 401 rq_stats = &priv->channel[i]->rq.stats; 402 403 /* collect stats from LRO */ 404 rq_stats->sw_lro_queued = rq->lro.lro_queued; 405 rq_stats->sw_lro_flushed = rq->lro.lro_flushed; 406 sw_lro_queued += rq_stats->sw_lro_queued; 407 sw_lro_flushed += rq_stats->sw_lro_flushed; 408 lro_packets += rq_stats->lro_packets; 409 lro_bytes += rq_stats->lro_bytes; 410 rx_csum_none += rq_stats->csum_none; 411 rx_wqe_err += rq_stats->wqe_err; 412 413 for (j = 0; j < priv->num_tc; j++) { 414 sq_stats = &priv->channel[i]->sq[j].stats; 415 sq_br = priv->channel[i]->sq[j].br; 416 417 tso_packets += sq_stats->tso_packets; 418 tso_bytes += sq_stats->tso_bytes; 419 tx_queue_dropped += sq_stats->dropped; 420 tx_queue_dropped += sq_br->br_drops; 421 tx_defragged += sq_stats->defragged; 422 tx_offload_none += sq_stats->csum_offload_none; 423 } 424 } 425 426 /* update counters */ 427 s->tso_packets = tso_packets; 428 s->tso_bytes = tso_bytes; 429 s->tx_queue_dropped = tx_queue_dropped; 430 s->tx_defragged = tx_defragged; 431 s->lro_packets = lro_packets; 432 s->lro_bytes = lro_bytes; 433 s->sw_lro_queued = sw_lro_queued; 434 s->sw_lro_flushed = sw_lro_flushed; 435 s->rx_csum_none = rx_csum_none; 436 s->rx_wqe_err = rx_wqe_err; 437 438 /* HW counters */ 439 memset(in, 0, sizeof(in)); 440 441 MLX5_SET(query_vport_counter_in, in, opcode, 442 MLX5_CMD_OP_QUERY_VPORT_COUNTER); 443 MLX5_SET(query_vport_counter_in, in, op_mod, 0); 444 MLX5_SET(query_vport_counter_in, in, other_vport, 0); 445 446 memset(out, 0, outlen); 447 448 /* get number of out-of-buffer drops first */ 449 if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id, 450 &rx_out_of_buffer)) 451 goto free_out; 452 453 /* accumulate difference into a 64-bit counter */ 454 s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev); 455 s->rx_out_of_buffer_prev = rx_out_of_buffer; 456 457 /* get port statistics */ 458 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen)) 459 goto free_out; 460 461 #define MLX5_GET_CTR(out, x) \ 462 MLX5_GET64(query_vport_counter_out, out, x) 463 464 s->rx_error_packets = 465 MLX5_GET_CTR(out, received_errors.packets); 466 s->rx_error_bytes = 467 MLX5_GET_CTR(out, received_errors.octets); 468 s->tx_error_packets = 469 MLX5_GET_CTR(out, transmit_errors.packets); 470 s->tx_error_bytes = 471 MLX5_GET_CTR(out, transmit_errors.octets); 472 473 s->rx_unicast_packets = 474 MLX5_GET_CTR(out, received_eth_unicast.packets); 475 s->rx_unicast_bytes = 476 MLX5_GET_CTR(out, received_eth_unicast.octets); 477 s->tx_unicast_packets = 478 MLX5_GET_CTR(out, transmitted_eth_unicast.packets); 479 s->tx_unicast_bytes = 480 MLX5_GET_CTR(out, transmitted_eth_unicast.octets); 481 482 s->rx_multicast_packets = 483 MLX5_GET_CTR(out, received_eth_multicast.packets); 484 s->rx_multicast_bytes = 485 MLX5_GET_CTR(out, received_eth_multicast.octets); 486 s->tx_multicast_packets = 487 MLX5_GET_CTR(out, transmitted_eth_multicast.packets); 488 s->tx_multicast_bytes = 489 MLX5_GET_CTR(out, transmitted_eth_multicast.octets); 490 491 s->rx_broadcast_packets = 492 MLX5_GET_CTR(out, received_eth_broadcast.packets); 493 s->rx_broadcast_bytes = 494 MLX5_GET_CTR(out, received_eth_broadcast.octets); 495 s->tx_broadcast_packets = 496 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets); 497 s->tx_broadcast_bytes = 498 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets); 499 500 s->rx_packets = 501 s->rx_unicast_packets + 502 s->rx_multicast_packets + 503 s->rx_broadcast_packets - 504 s->rx_out_of_buffer; 505 s->rx_bytes = 506 s->rx_unicast_bytes + 507 s->rx_multicast_bytes + 508 s->rx_broadcast_bytes; 509 s->tx_packets = 510 s->tx_unicast_packets + 511 s->tx_multicast_packets + 512 s->tx_broadcast_packets; 513 s->tx_bytes = 514 s->tx_unicast_bytes + 515 s->tx_multicast_bytes + 516 s->tx_broadcast_bytes; 517 518 /* Update calculated offload counters */ 519 s->tx_csum_offload = s->tx_packets - tx_offload_none; 520 s->rx_csum_good = s->rx_packets - s->rx_csum_none; 521 522 /* Update per port counters */ 523 mlx5e_update_pport_counters(priv); 524 525 #if (__FreeBSD_version < 1100000) 526 /* no get_counters interface in fbsd 10 */ 527 ifp->if_ipackets = s->rx_packets; 528 ifp->if_ierrors = s->rx_error_packets; 529 ifp->if_iqdrops = s->rx_out_of_buffer; 530 ifp->if_opackets = s->tx_packets; 531 ifp->if_oerrors = s->tx_error_packets; 532 ifp->if_snd.ifq_drops = s->tx_queue_dropped; 533 ifp->if_ibytes = s->rx_bytes; 534 ifp->if_obytes = s->tx_bytes; 535 #endif 536 537 free_out: 538 kvfree(out); 539 PRIV_UNLOCK(priv); 540 } 541 542 static void 543 mlx5e_update_stats(void *arg) 544 { 545 struct mlx5e_priv *priv = arg; 546 547 schedule_work(&priv->update_stats_work); 548 549 callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv); 550 } 551 552 static void 553 mlx5e_async_event_sub(struct mlx5e_priv *priv, 554 enum mlx5_dev_event event) 555 { 556 switch (event) { 557 case MLX5_DEV_EVENT_PORT_UP: 558 case MLX5_DEV_EVENT_PORT_DOWN: 559 schedule_work(&priv->update_carrier_work); 560 break; 561 562 default: 563 break; 564 } 565 } 566 567 static void 568 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv, 569 enum mlx5_dev_event event, unsigned long param) 570 { 571 struct mlx5e_priv *priv = vpriv; 572 573 mtx_lock(&priv->async_events_mtx); 574 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state)) 575 mlx5e_async_event_sub(priv, event); 576 mtx_unlock(&priv->async_events_mtx); 577 } 578 579 static void 580 mlx5e_enable_async_events(struct mlx5e_priv *priv) 581 { 582 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 583 } 584 585 static void 586 mlx5e_disable_async_events(struct mlx5e_priv *priv) 587 { 588 mtx_lock(&priv->async_events_mtx); 589 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 590 mtx_unlock(&priv->async_events_mtx); 591 } 592 593 static const char *mlx5e_rq_stats_desc[] = { 594 MLX5E_RQ_STATS(MLX5E_STATS_DESC) 595 }; 596 597 static int 598 mlx5e_create_rq(struct mlx5e_channel *c, 599 struct mlx5e_rq_param *param, 600 struct mlx5e_rq *rq) 601 { 602 struct mlx5e_priv *priv = c->priv; 603 struct mlx5_core_dev *mdev = priv->mdev; 604 char buffer[16]; 605 void *rqc = param->rqc; 606 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); 607 int wq_sz; 608 int err; 609 int i; 610 611 /* Create DMA descriptor TAG */ 612 if ((err = -bus_dma_tag_create( 613 bus_get_dma_tag(mdev->pdev->dev.bsddev), 614 1, /* any alignment */ 615 0, /* no boundary */ 616 BUS_SPACE_MAXADDR, /* lowaddr */ 617 BUS_SPACE_MAXADDR, /* highaddr */ 618 NULL, NULL, /* filter, filterarg */ 619 MJUM16BYTES, /* maxsize */ 620 1, /* nsegments */ 621 MJUM16BYTES, /* maxsegsize */ 622 0, /* flags */ 623 NULL, NULL, /* lockfunc, lockfuncarg */ 624 &rq->dma_tag))) 625 goto done; 626 627 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, 628 &rq->wq_ctrl); 629 if (err) 630 goto err_free_dma_tag; 631 632 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR]; 633 634 if (priv->params.hw_lro_en) { 635 rq->wqe_sz = priv->params.lro_wqe_sz; 636 } else { 637 rq->wqe_sz = MLX5E_SW2MB_MTU(priv->ifp->if_mtu); 638 } 639 if (rq->wqe_sz > MJUM16BYTES) { 640 err = -ENOMEM; 641 goto err_rq_wq_destroy; 642 } else if (rq->wqe_sz > MJUM9BYTES) { 643 rq->wqe_sz = MJUM16BYTES; 644 } else if (rq->wqe_sz > MJUMPAGESIZE) { 645 rq->wqe_sz = MJUM9BYTES; 646 } else if (rq->wqe_sz > MCLBYTES) { 647 rq->wqe_sz = MJUMPAGESIZE; 648 } else { 649 rq->wqe_sz = MCLBYTES; 650 } 651 652 wq_sz = mlx5_wq_ll_get_size(&rq->wq); 653 654 err = -tcp_lro_init_args(&rq->lro, c->ifp, TCP_LRO_ENTRIES, wq_sz); 655 if (err) 656 goto err_rq_wq_destroy; 657 658 rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO); 659 if (rq->mbuf == NULL) { 660 err = -ENOMEM; 661 goto err_lro_init; 662 } 663 for (i = 0; i != wq_sz; i++) { 664 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i); 665 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN; 666 667 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map); 668 if (err != 0) { 669 while (i--) 670 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 671 goto err_rq_mbuf_free; 672 } 673 wqe->data.lkey = c->mkey_be; 674 wqe->data.byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING); 675 } 676 677 rq->ifp = c->ifp; 678 rq->channel = c; 679 rq->ix = c->ix; 680 681 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix); 682 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 683 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM, 684 rq->stats.arg); 685 return (0); 686 687 err_rq_mbuf_free: 688 free(rq->mbuf, M_MLX5EN); 689 err_lro_init: 690 tcp_lro_free(&rq->lro); 691 err_rq_wq_destroy: 692 mlx5_wq_destroy(&rq->wq_ctrl); 693 err_free_dma_tag: 694 bus_dma_tag_destroy(rq->dma_tag); 695 done: 696 return (err); 697 } 698 699 static void 700 mlx5e_destroy_rq(struct mlx5e_rq *rq) 701 { 702 int wq_sz; 703 int i; 704 705 /* destroy all sysctl nodes */ 706 sysctl_ctx_free(&rq->stats.ctx); 707 708 /* free leftover LRO packets, if any */ 709 tcp_lro_free(&rq->lro); 710 711 wq_sz = mlx5_wq_ll_get_size(&rq->wq); 712 for (i = 0; i != wq_sz; i++) { 713 if (rq->mbuf[i].mbuf != NULL) { 714 bus_dmamap_unload(rq->dma_tag, 715 rq->mbuf[i].dma_map); 716 m_freem(rq->mbuf[i].mbuf); 717 } 718 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 719 } 720 free(rq->mbuf, M_MLX5EN); 721 mlx5_wq_destroy(&rq->wq_ctrl); 722 } 723 724 static int 725 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param) 726 { 727 struct mlx5e_channel *c = rq->channel; 728 struct mlx5e_priv *priv = c->priv; 729 struct mlx5_core_dev *mdev = priv->mdev; 730 731 void *in; 732 void *rqc; 733 void *wq; 734 int inlen; 735 int err; 736 737 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 738 sizeof(u64) * rq->wq_ctrl.buf.npages; 739 in = mlx5_vzalloc(inlen); 740 if (in == NULL) 741 return (-ENOMEM); 742 743 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 744 wq = MLX5_ADDR_OF(rqc, rqc, wq); 745 746 memcpy(rqc, param->rqc, sizeof(param->rqc)); 747 748 MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn); 749 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 750 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 751 if (priv->counter_set_id >= 0) 752 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id); 753 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - 754 PAGE_SHIFT); 755 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); 756 757 mlx5_fill_page_array(&rq->wq_ctrl.buf, 758 (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 759 760 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); 761 762 kvfree(in); 763 764 return (err); 765 } 766 767 static int 768 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state) 769 { 770 struct mlx5e_channel *c = rq->channel; 771 struct mlx5e_priv *priv = c->priv; 772 struct mlx5_core_dev *mdev = priv->mdev; 773 774 void *in; 775 void *rqc; 776 int inlen; 777 int err; 778 779 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 780 in = mlx5_vzalloc(inlen); 781 if (in == NULL) 782 return (-ENOMEM); 783 784 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 785 786 MLX5_SET(modify_rq_in, in, rqn, rq->rqn); 787 MLX5_SET(modify_rq_in, in, rq_state, curr_state); 788 MLX5_SET(rqc, rqc, state, next_state); 789 790 err = mlx5_core_modify_rq(mdev, in, inlen); 791 792 kvfree(in); 793 794 return (err); 795 } 796 797 static void 798 mlx5e_disable_rq(struct mlx5e_rq *rq) 799 { 800 struct mlx5e_channel *c = rq->channel; 801 struct mlx5e_priv *priv = c->priv; 802 struct mlx5_core_dev *mdev = priv->mdev; 803 804 mlx5_core_destroy_rq(mdev, rq->rqn); 805 } 806 807 static int 808 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq) 809 { 810 struct mlx5e_channel *c = rq->channel; 811 struct mlx5e_priv *priv = c->priv; 812 struct mlx5_wq_ll *wq = &rq->wq; 813 int i; 814 815 for (i = 0; i < 1000; i++) { 816 if (wq->cur_sz >= priv->params.min_rx_wqes) 817 return (0); 818 819 msleep(4); 820 } 821 return (-ETIMEDOUT); 822 } 823 824 static int 825 mlx5e_open_rq(struct mlx5e_channel *c, 826 struct mlx5e_rq_param *param, 827 struct mlx5e_rq *rq) 828 { 829 int err; 830 831 err = mlx5e_create_rq(c, param, rq); 832 if (err) 833 return (err); 834 835 err = mlx5e_enable_rq(rq, param); 836 if (err) 837 goto err_destroy_rq; 838 839 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 840 if (err) 841 goto err_disable_rq; 842 843 c->rq.enabled = 1; 844 845 return (0); 846 847 err_disable_rq: 848 mlx5e_disable_rq(rq); 849 err_destroy_rq: 850 mlx5e_destroy_rq(rq); 851 852 return (err); 853 } 854 855 static void 856 mlx5e_close_rq(struct mlx5e_rq *rq) 857 { 858 mtx_lock(&rq->mtx); 859 rq->enabled = 0; 860 callout_stop(&rq->watchdog); 861 mtx_unlock(&rq->mtx); 862 863 callout_drain(&rq->watchdog); 864 865 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 866 } 867 868 static void 869 mlx5e_close_rq_wait(struct mlx5e_rq *rq) 870 { 871 /* wait till RQ is empty */ 872 while (!mlx5_wq_ll_is_empty(&rq->wq)) { 873 msleep(4); 874 rq->cq.mcq.comp(&rq->cq.mcq); 875 } 876 877 mlx5e_disable_rq(rq); 878 mlx5e_destroy_rq(rq); 879 } 880 881 void 882 mlx5e_free_sq_db(struct mlx5e_sq *sq) 883 { 884 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 885 int x; 886 887 for (x = 0; x != wq_sz; x++) 888 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 889 free(sq->mbuf, M_MLX5EN); 890 } 891 892 int 893 mlx5e_alloc_sq_db(struct mlx5e_sq *sq) 894 { 895 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 896 int err; 897 int x; 898 899 sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO); 900 if (sq->mbuf == NULL) 901 return (-ENOMEM); 902 903 /* Create DMA descriptor MAPs */ 904 for (x = 0; x != wq_sz; x++) { 905 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map); 906 if (err != 0) { 907 while (x--) 908 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 909 free(sq->mbuf, M_MLX5EN); 910 return (err); 911 } 912 } 913 return (0); 914 } 915 916 static const char *mlx5e_sq_stats_desc[] = { 917 MLX5E_SQ_STATS(MLX5E_STATS_DESC) 918 }; 919 920 static int 921 mlx5e_create_sq(struct mlx5e_channel *c, 922 int tc, 923 struct mlx5e_sq_param *param, 924 struct mlx5e_sq *sq) 925 { 926 struct mlx5e_priv *priv = c->priv; 927 struct mlx5_core_dev *mdev = priv->mdev; 928 char buffer[16]; 929 930 void *sqc = param->sqc; 931 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq); 932 #ifdef RSS 933 cpuset_t cpu_mask; 934 int cpu_id; 935 #endif 936 int err; 937 938 /* Create DMA descriptor TAG */ 939 if ((err = -bus_dma_tag_create( 940 bus_get_dma_tag(mdev->pdev->dev.bsddev), 941 1, /* any alignment */ 942 0, /* no boundary */ 943 BUS_SPACE_MAXADDR, /* lowaddr */ 944 BUS_SPACE_MAXADDR, /* highaddr */ 945 NULL, NULL, /* filter, filterarg */ 946 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */ 947 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */ 948 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */ 949 0, /* flags */ 950 NULL, NULL, /* lockfunc, lockfuncarg */ 951 &sq->dma_tag))) 952 goto done; 953 954 err = mlx5_alloc_map_uar(mdev, &sq->uar); 955 if (err) 956 goto err_free_dma_tag; 957 958 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, 959 &sq->wq_ctrl); 960 if (err) 961 goto err_unmap_free_uar; 962 963 sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; 964 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2; 965 966 err = mlx5e_alloc_sq_db(sq); 967 if (err) 968 goto err_sq_wq_destroy; 969 970 sq->mkey_be = c->mkey_be; 971 sq->ifp = priv->ifp; 972 sq->priv = priv; 973 sq->tc = tc; 974 975 sq->br = buf_ring_alloc(MLX5E_SQ_TX_QUEUE_SIZE, M_MLX5EN, 976 M_WAITOK, &sq->lock); 977 if (sq->br == NULL) { 978 if_printf(c->ifp, "%s: Failed allocating sq drbr buffer\n", 979 __func__); 980 err = -ENOMEM; 981 goto err_free_sq_db; 982 } 983 984 sq->sq_tq = taskqueue_create_fast("mlx5e_que", M_WAITOK, 985 taskqueue_thread_enqueue, &sq->sq_tq); 986 if (sq->sq_tq == NULL) { 987 if_printf(c->ifp, "%s: Failed allocating taskqueue\n", 988 __func__); 989 err = -ENOMEM; 990 goto err_free_drbr; 991 } 992 993 TASK_INIT(&sq->sq_task, 0, mlx5e_tx_que, sq); 994 #ifdef RSS 995 cpu_id = rss_getcpu(c->ix % rss_getnumbuckets()); 996 CPU_SETOF(cpu_id, &cpu_mask); 997 taskqueue_start_threads_cpuset(&sq->sq_tq, 1, PI_NET, &cpu_mask, 998 "%s TX SQ%d.%d CPU%d", c->ifp->if_xname, c->ix, tc, cpu_id); 999 #else 1000 taskqueue_start_threads(&sq->sq_tq, 1, PI_NET, 1001 "%s TX SQ%d.%d", c->ifp->if_xname, c->ix, tc); 1002 #endif 1003 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc); 1004 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 1005 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM, 1006 sq->stats.arg); 1007 1008 return (0); 1009 1010 err_free_drbr: 1011 buf_ring_free(sq->br, M_MLX5EN); 1012 err_free_sq_db: 1013 mlx5e_free_sq_db(sq); 1014 err_sq_wq_destroy: 1015 mlx5_wq_destroy(&sq->wq_ctrl); 1016 1017 err_unmap_free_uar: 1018 mlx5_unmap_free_uar(mdev, &sq->uar); 1019 1020 err_free_dma_tag: 1021 bus_dma_tag_destroy(sq->dma_tag); 1022 done: 1023 return (err); 1024 } 1025 1026 static void 1027 mlx5e_destroy_sq(struct mlx5e_sq *sq) 1028 { 1029 /* destroy all sysctl nodes */ 1030 sysctl_ctx_free(&sq->stats.ctx); 1031 1032 mlx5e_free_sq_db(sq); 1033 mlx5_wq_destroy(&sq->wq_ctrl); 1034 mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar); 1035 taskqueue_drain(sq->sq_tq, &sq->sq_task); 1036 taskqueue_free(sq->sq_tq); 1037 buf_ring_free(sq->br, M_MLX5EN); 1038 } 1039 1040 int 1041 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param, 1042 int tis_num) 1043 { 1044 void *in; 1045 void *sqc; 1046 void *wq; 1047 int inlen; 1048 int err; 1049 1050 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1051 sizeof(u64) * sq->wq_ctrl.buf.npages; 1052 in = mlx5_vzalloc(inlen); 1053 if (in == NULL) 1054 return (-ENOMEM); 1055 1056 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1057 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1058 1059 memcpy(sqc, param->sqc, sizeof(param->sqc)); 1060 1061 MLX5_SET(sqc, sqc, tis_num_0, tis_num); 1062 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn); 1063 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1064 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1065 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1066 1067 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1068 MLX5_SET(wq, wq, uar_page, sq->uar.index); 1069 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift - 1070 PAGE_SHIFT); 1071 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma); 1072 1073 mlx5_fill_page_array(&sq->wq_ctrl.buf, 1074 (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 1075 1076 err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn); 1077 1078 kvfree(in); 1079 1080 return (err); 1081 } 1082 1083 int 1084 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state) 1085 { 1086 void *in; 1087 void *sqc; 1088 int inlen; 1089 int err; 1090 1091 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 1092 in = mlx5_vzalloc(inlen); 1093 if (in == NULL) 1094 return (-ENOMEM); 1095 1096 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1097 1098 MLX5_SET(modify_sq_in, in, sqn, sq->sqn); 1099 MLX5_SET(modify_sq_in, in, sq_state, curr_state); 1100 MLX5_SET(sqc, sqc, state, next_state); 1101 1102 err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen); 1103 1104 kvfree(in); 1105 1106 return (err); 1107 } 1108 1109 void 1110 mlx5e_disable_sq(struct mlx5e_sq *sq) 1111 { 1112 1113 mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn); 1114 } 1115 1116 static int 1117 mlx5e_open_sq(struct mlx5e_channel *c, 1118 int tc, 1119 struct mlx5e_sq_param *param, 1120 struct mlx5e_sq *sq) 1121 { 1122 int err; 1123 1124 err = mlx5e_create_sq(c, tc, param, sq); 1125 if (err) 1126 return (err); 1127 1128 err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]); 1129 if (err) 1130 goto err_destroy_sq; 1131 1132 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY); 1133 if (err) 1134 goto err_disable_sq; 1135 1136 atomic_store_rel_int(&sq->queue_state, MLX5E_SQ_READY); 1137 1138 return (0); 1139 1140 err_disable_sq: 1141 mlx5e_disable_sq(sq); 1142 err_destroy_sq: 1143 mlx5e_destroy_sq(sq); 1144 1145 return (err); 1146 } 1147 1148 static void 1149 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep) 1150 { 1151 /* fill up remainder with NOPs */ 1152 while (sq->cev_counter != 0) { 1153 while (!mlx5e_sq_has_room_for(sq, 1)) { 1154 if (can_sleep != 0) { 1155 mtx_unlock(&sq->lock); 1156 msleep(4); 1157 mtx_lock(&sq->lock); 1158 } else { 1159 goto done; 1160 } 1161 } 1162 /* send a single NOP */ 1163 mlx5e_send_nop(sq, 1); 1164 wmb(); 1165 } 1166 done: 1167 /* Check if we need to write the doorbell */ 1168 if (likely(sq->doorbell.d64 != 0)) { 1169 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0); 1170 sq->doorbell.d64 = 0; 1171 } 1172 return; 1173 } 1174 1175 void 1176 mlx5e_sq_cev_timeout(void *arg) 1177 { 1178 struct mlx5e_sq *sq = arg; 1179 1180 mtx_assert(&sq->lock, MA_OWNED); 1181 1182 /* check next state */ 1183 switch (sq->cev_next_state) { 1184 case MLX5E_CEV_STATE_SEND_NOPS: 1185 /* fill TX ring with NOPs, if any */ 1186 mlx5e_sq_send_nops_locked(sq, 0); 1187 1188 /* check if completed */ 1189 if (sq->cev_counter == 0) { 1190 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL; 1191 return; 1192 } 1193 break; 1194 default: 1195 /* send NOPs on next timeout */ 1196 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS; 1197 break; 1198 } 1199 1200 /* restart timer */ 1201 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq); 1202 } 1203 1204 void 1205 mlx5e_drain_sq(struct mlx5e_sq *sq) 1206 { 1207 1208 mtx_lock(&sq->lock); 1209 /* teardown event factor timer, if any */ 1210 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS; 1211 callout_stop(&sq->cev_callout); 1212 1213 /* send dummy NOPs in order to flush the transmit ring */ 1214 mlx5e_sq_send_nops_locked(sq, 1); 1215 mtx_unlock(&sq->lock); 1216 1217 /* make sure it is safe to free the callout */ 1218 callout_drain(&sq->cev_callout); 1219 1220 /* error out remaining requests */ 1221 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR); 1222 1223 /* wait till SQ is empty */ 1224 mtx_lock(&sq->lock); 1225 while (sq->cc != sq->pc) { 1226 mtx_unlock(&sq->lock); 1227 msleep(4); 1228 sq->cq.mcq.comp(&sq->cq.mcq); 1229 mtx_lock(&sq->lock); 1230 } 1231 mtx_unlock(&sq->lock); 1232 } 1233 1234 static void 1235 mlx5e_close_sq_wait(struct mlx5e_sq *sq) 1236 { 1237 1238 mlx5e_drain_sq(sq); 1239 mlx5e_disable_sq(sq); 1240 mlx5e_destroy_sq(sq); 1241 } 1242 1243 static int 1244 mlx5e_create_cq(struct mlx5e_priv *priv, 1245 struct mlx5e_cq_param *param, 1246 struct mlx5e_cq *cq, 1247 mlx5e_cq_comp_t *comp, 1248 int eq_ix) 1249 { 1250 struct mlx5_core_dev *mdev = priv->mdev; 1251 struct mlx5_core_cq *mcq = &cq->mcq; 1252 int eqn_not_used; 1253 int irqn; 1254 int err; 1255 u32 i; 1256 1257 param->wq.buf_numa_node = 0; 1258 param->wq.db_numa_node = 0; 1259 1260 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, 1261 &cq->wq_ctrl); 1262 if (err) 1263 return (err); 1264 1265 mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn); 1266 1267 mcq->cqe_sz = 64; 1268 mcq->set_ci_db = cq->wq_ctrl.db.db; 1269 mcq->arm_db = cq->wq_ctrl.db.db + 1; 1270 *mcq->set_ci_db = 0; 1271 *mcq->arm_db = 0; 1272 mcq->vector = eq_ix; 1273 mcq->comp = comp; 1274 mcq->event = mlx5e_cq_error_event; 1275 mcq->irqn = irqn; 1276 mcq->uar = &priv->cq_uar; 1277 1278 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { 1279 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); 1280 1281 cqe->op_own = 0xf1; 1282 } 1283 1284 cq->priv = priv; 1285 1286 return (0); 1287 } 1288 1289 static void 1290 mlx5e_destroy_cq(struct mlx5e_cq *cq) 1291 { 1292 mlx5_wq_destroy(&cq->wq_ctrl); 1293 } 1294 1295 static int 1296 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix) 1297 { 1298 struct mlx5_core_cq *mcq = &cq->mcq; 1299 void *in; 1300 void *cqc; 1301 int inlen; 1302 int irqn_not_used; 1303 int eqn; 1304 int err; 1305 1306 inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 1307 sizeof(u64) * cq->wq_ctrl.buf.npages; 1308 in = mlx5_vzalloc(inlen); 1309 if (in == NULL) 1310 return (-ENOMEM); 1311 1312 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1313 1314 memcpy(cqc, param->cqc, sizeof(param->cqc)); 1315 1316 mlx5_fill_page_array(&cq->wq_ctrl.buf, 1317 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas)); 1318 1319 mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used); 1320 1321 MLX5_SET(cqc, cqc, c_eqn, eqn); 1322 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index); 1323 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - 1324 PAGE_SHIFT); 1325 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); 1326 1327 err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen); 1328 1329 kvfree(in); 1330 1331 if (err) 1332 return (err); 1333 1334 mlx5e_cq_arm(cq); 1335 1336 return (0); 1337 } 1338 1339 static void 1340 mlx5e_disable_cq(struct mlx5e_cq *cq) 1341 { 1342 1343 mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq); 1344 } 1345 1346 int 1347 mlx5e_open_cq(struct mlx5e_priv *priv, 1348 struct mlx5e_cq_param *param, 1349 struct mlx5e_cq *cq, 1350 mlx5e_cq_comp_t *comp, 1351 int eq_ix) 1352 { 1353 int err; 1354 1355 err = mlx5e_create_cq(priv, param, cq, comp, eq_ix); 1356 if (err) 1357 return (err); 1358 1359 err = mlx5e_enable_cq(cq, param, eq_ix); 1360 if (err) 1361 goto err_destroy_cq; 1362 1363 return (0); 1364 1365 err_destroy_cq: 1366 mlx5e_destroy_cq(cq); 1367 1368 return (err); 1369 } 1370 1371 void 1372 mlx5e_close_cq(struct mlx5e_cq *cq) 1373 { 1374 mlx5e_disable_cq(cq); 1375 mlx5e_destroy_cq(cq); 1376 } 1377 1378 static int 1379 mlx5e_open_tx_cqs(struct mlx5e_channel *c, 1380 struct mlx5e_channel_param *cparam) 1381 { 1382 int err; 1383 int tc; 1384 1385 for (tc = 0; tc < c->num_tc; tc++) { 1386 /* open completion queue */ 1387 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq, 1388 &mlx5e_tx_cq_comp, c->ix); 1389 if (err) 1390 goto err_close_tx_cqs; 1391 } 1392 return (0); 1393 1394 err_close_tx_cqs: 1395 for (tc--; tc >= 0; tc--) 1396 mlx5e_close_cq(&c->sq[tc].cq); 1397 1398 return (err); 1399 } 1400 1401 static void 1402 mlx5e_close_tx_cqs(struct mlx5e_channel *c) 1403 { 1404 int tc; 1405 1406 for (tc = 0; tc < c->num_tc; tc++) 1407 mlx5e_close_cq(&c->sq[tc].cq); 1408 } 1409 1410 static int 1411 mlx5e_open_sqs(struct mlx5e_channel *c, 1412 struct mlx5e_channel_param *cparam) 1413 { 1414 int err; 1415 int tc; 1416 1417 for (tc = 0; tc < c->num_tc; tc++) { 1418 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]); 1419 if (err) 1420 goto err_close_sqs; 1421 } 1422 1423 return (0); 1424 1425 err_close_sqs: 1426 for (tc--; tc >= 0; tc--) 1427 mlx5e_close_sq_wait(&c->sq[tc]); 1428 1429 return (err); 1430 } 1431 1432 static void 1433 mlx5e_close_sqs_wait(struct mlx5e_channel *c) 1434 { 1435 int tc; 1436 1437 for (tc = 0; tc < c->num_tc; tc++) 1438 mlx5e_close_sq_wait(&c->sq[tc]); 1439 } 1440 1441 static void 1442 mlx5e_chan_mtx_init(struct mlx5e_channel *c) 1443 { 1444 int tc; 1445 1446 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF); 1447 1448 callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0); 1449 1450 for (tc = 0; tc < c->num_tc; tc++) { 1451 struct mlx5e_sq *sq = c->sq + tc; 1452 1453 mtx_init(&sq->lock, "mlx5tx", MTX_NETWORK_LOCK, MTX_DEF); 1454 mtx_init(&sq->comp_lock, "mlx5comp", MTX_NETWORK_LOCK, 1455 MTX_DEF); 1456 1457 callout_init_mtx(&sq->cev_callout, &sq->lock, 0); 1458 1459 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact; 1460 1461 /* ensure the TX completion event factor is not zero */ 1462 if (sq->cev_factor == 0) 1463 sq->cev_factor = 1; 1464 } 1465 } 1466 1467 static void 1468 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c) 1469 { 1470 int tc; 1471 1472 mtx_destroy(&c->rq.mtx); 1473 1474 for (tc = 0; tc < c->num_tc; tc++) { 1475 mtx_destroy(&c->sq[tc].lock); 1476 mtx_destroy(&c->sq[tc].comp_lock); 1477 } 1478 } 1479 1480 static int 1481 mlx5e_open_channel(struct mlx5e_priv *priv, int ix, 1482 struct mlx5e_channel_param *cparam, 1483 struct mlx5e_channel *volatile *cp) 1484 { 1485 struct mlx5e_channel *c; 1486 int err; 1487 1488 c = malloc(sizeof(*c), M_MLX5EN, M_WAITOK | M_ZERO); 1489 if (c == NULL) 1490 return (-ENOMEM); 1491 1492 c->priv = priv; 1493 c->ix = ix; 1494 c->cpu = 0; 1495 c->ifp = priv->ifp; 1496 c->mkey_be = cpu_to_be32(priv->mr.key); 1497 c->num_tc = priv->num_tc; 1498 1499 /* init mutexes */ 1500 mlx5e_chan_mtx_init(c); 1501 1502 /* open transmit completion queue */ 1503 err = mlx5e_open_tx_cqs(c, cparam); 1504 if (err) 1505 goto err_free; 1506 1507 /* open receive completion queue */ 1508 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq, 1509 &mlx5e_rx_cq_comp, c->ix); 1510 if (err) 1511 goto err_close_tx_cqs; 1512 1513 err = mlx5e_open_sqs(c, cparam); 1514 if (err) 1515 goto err_close_rx_cq; 1516 1517 err = mlx5e_open_rq(c, &cparam->rq, &c->rq); 1518 if (err) 1519 goto err_close_sqs; 1520 1521 /* store channel pointer */ 1522 *cp = c; 1523 1524 /* poll receive queue initially */ 1525 c->rq.cq.mcq.comp(&c->rq.cq.mcq); 1526 1527 return (0); 1528 1529 err_close_sqs: 1530 mlx5e_close_sqs_wait(c); 1531 1532 err_close_rx_cq: 1533 mlx5e_close_cq(&c->rq.cq); 1534 1535 err_close_tx_cqs: 1536 mlx5e_close_tx_cqs(c); 1537 1538 err_free: 1539 /* destroy mutexes */ 1540 mlx5e_chan_mtx_destroy(c); 1541 free(c, M_MLX5EN); 1542 return (err); 1543 } 1544 1545 static void 1546 mlx5e_close_channel(struct mlx5e_channel *volatile *pp) 1547 { 1548 struct mlx5e_channel *c = *pp; 1549 1550 /* check if channel is already closed */ 1551 if (c == NULL) 1552 return; 1553 mlx5e_close_rq(&c->rq); 1554 } 1555 1556 static void 1557 mlx5e_close_channel_wait(struct mlx5e_channel *volatile *pp) 1558 { 1559 struct mlx5e_channel *c = *pp; 1560 1561 /* check if channel is already closed */ 1562 if (c == NULL) 1563 return; 1564 /* ensure channel pointer is no longer used */ 1565 *pp = NULL; 1566 1567 mlx5e_close_rq_wait(&c->rq); 1568 mlx5e_close_sqs_wait(c); 1569 mlx5e_close_cq(&c->rq.cq); 1570 mlx5e_close_tx_cqs(c); 1571 /* destroy mutexes */ 1572 mlx5e_chan_mtx_destroy(c); 1573 free(c, M_MLX5EN); 1574 } 1575 1576 static void 1577 mlx5e_build_rq_param(struct mlx5e_priv *priv, 1578 struct mlx5e_rq_param *param) 1579 { 1580 void *rqc = param->rqc; 1581 void *wq = MLX5_ADDR_OF(rqc, rqc, wq); 1582 1583 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); 1584 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1585 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe))); 1586 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size); 1587 MLX5_SET(wq, wq, pd, priv->pdn); 1588 1589 param->wq.buf_numa_node = 0; 1590 param->wq.db_numa_node = 0; 1591 param->wq.linear = 1; 1592 } 1593 1594 static void 1595 mlx5e_build_sq_param(struct mlx5e_priv *priv, 1596 struct mlx5e_sq_param *param) 1597 { 1598 void *sqc = param->sqc; 1599 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 1600 1601 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size); 1602 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1603 MLX5_SET(wq, wq, pd, priv->pdn); 1604 1605 param->wq.buf_numa_node = 0; 1606 param->wq.db_numa_node = 0; 1607 param->wq.linear = 1; 1608 } 1609 1610 static void 1611 mlx5e_build_common_cq_param(struct mlx5e_priv *priv, 1612 struct mlx5e_cq_param *param) 1613 { 1614 void *cqc = param->cqc; 1615 1616 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index); 1617 } 1618 1619 static void 1620 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, 1621 struct mlx5e_cq_param *param) 1622 { 1623 void *cqc = param->cqc; 1624 1625 1626 /* 1627 * TODO The sysctl to control on/off is a bool value for now, which means 1628 * we only support CSUM, once HASH is implemnted we'll need to address that. 1629 */ 1630 if (priv->params.cqe_zipping_en) { 1631 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM); 1632 MLX5_SET(cqc, cqc, cqe_compression_en, 1); 1633 } 1634 1635 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size); 1636 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec); 1637 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts); 1638 1639 switch (priv->params.rx_cq_moderation_mode) { 1640 case 0: 1641 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 1642 break; 1643 default: 1644 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 1645 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 1646 else 1647 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 1648 break; 1649 } 1650 1651 mlx5e_build_common_cq_param(priv, param); 1652 } 1653 1654 static void 1655 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv, 1656 struct mlx5e_cq_param *param) 1657 { 1658 void *cqc = param->cqc; 1659 1660 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size); 1661 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec); 1662 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts); 1663 1664 switch (priv->params.tx_cq_moderation_mode) { 1665 case 0: 1666 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 1667 break; 1668 default: 1669 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 1670 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 1671 else 1672 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 1673 break; 1674 } 1675 1676 mlx5e_build_common_cq_param(priv, param); 1677 } 1678 1679 static void 1680 mlx5e_build_channel_param(struct mlx5e_priv *priv, 1681 struct mlx5e_channel_param *cparam) 1682 { 1683 memset(cparam, 0, sizeof(*cparam)); 1684 1685 mlx5e_build_rq_param(priv, &cparam->rq); 1686 mlx5e_build_sq_param(priv, &cparam->sq); 1687 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq); 1688 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq); 1689 } 1690 1691 static int 1692 mlx5e_open_channels(struct mlx5e_priv *priv) 1693 { 1694 struct mlx5e_channel_param cparam; 1695 void *ptr; 1696 int err; 1697 int i; 1698 int j; 1699 1700 priv->channel = malloc(priv->params.num_channels * 1701 sizeof(struct mlx5e_channel *), M_MLX5EN, M_WAITOK | M_ZERO); 1702 if (priv->channel == NULL) 1703 return (-ENOMEM); 1704 1705 mlx5e_build_channel_param(priv, &cparam); 1706 for (i = 0; i < priv->params.num_channels; i++) { 1707 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]); 1708 if (err) 1709 goto err_close_channels; 1710 } 1711 1712 for (j = 0; j < priv->params.num_channels; j++) { 1713 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq); 1714 if (err) 1715 goto err_close_channels; 1716 } 1717 1718 return (0); 1719 1720 err_close_channels: 1721 for (i--; i >= 0; i--) { 1722 mlx5e_close_channel(&priv->channel[i]); 1723 mlx5e_close_channel_wait(&priv->channel[i]); 1724 } 1725 1726 /* remove "volatile" attribute from "channel" pointer */ 1727 ptr = __DECONST(void *, priv->channel); 1728 priv->channel = NULL; 1729 1730 free(ptr, M_MLX5EN); 1731 1732 return (err); 1733 } 1734 1735 static void 1736 mlx5e_close_channels(struct mlx5e_priv *priv) 1737 { 1738 void *ptr; 1739 int i; 1740 1741 if (priv->channel == NULL) 1742 return; 1743 1744 for (i = 0; i < priv->params.num_channels; i++) 1745 mlx5e_close_channel(&priv->channel[i]); 1746 for (i = 0; i < priv->params.num_channels; i++) 1747 mlx5e_close_channel_wait(&priv->channel[i]); 1748 1749 /* remove "volatile" attribute from "channel" pointer */ 1750 ptr = __DECONST(void *, priv->channel); 1751 priv->channel = NULL; 1752 1753 free(ptr, M_MLX5EN); 1754 } 1755 1756 static int 1757 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq) 1758 { 1759 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq, 1760 priv->params.tx_cq_moderation_usec, 1761 priv->params.tx_cq_moderation_pkts)); 1762 } 1763 1764 static int 1765 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq) 1766 { 1767 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq, 1768 priv->params.rx_cq_moderation_usec, 1769 priv->params.rx_cq_moderation_pkts)); 1770 } 1771 1772 static int 1773 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c) 1774 { 1775 int err; 1776 int i; 1777 1778 if (c == NULL) 1779 return (EINVAL); 1780 1781 err = mlx5e_refresh_rq_params(priv, &c->rq); 1782 if (err) 1783 goto done; 1784 1785 for (i = 0; i != c->num_tc; i++) { 1786 err = mlx5e_refresh_sq_params(priv, &c->sq[i]); 1787 if (err) 1788 goto done; 1789 } 1790 done: 1791 return (err); 1792 } 1793 1794 int 1795 mlx5e_refresh_channel_params(struct mlx5e_priv *priv) 1796 { 1797 int i; 1798 1799 if (priv->channel == NULL) 1800 return (EINVAL); 1801 1802 for (i = 0; i < priv->params.num_channels; i++) { 1803 int err; 1804 1805 err = mlx5e_refresh_channel_params_sub(priv, priv->channel[i]); 1806 if (err) 1807 return (err); 1808 } 1809 return (0); 1810 } 1811 1812 static int 1813 mlx5e_open_tis(struct mlx5e_priv *priv, int tc) 1814 { 1815 struct mlx5_core_dev *mdev = priv->mdev; 1816 u32 in[MLX5_ST_SZ_DW(create_tis_in)]; 1817 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1818 1819 memset(in, 0, sizeof(in)); 1820 1821 MLX5_SET(tisc, tisc, prio, tc); 1822 MLX5_SET(tisc, tisc, transport_domain, priv->tdn); 1823 1824 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc])); 1825 } 1826 1827 static void 1828 mlx5e_close_tis(struct mlx5e_priv *priv, int tc) 1829 { 1830 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]); 1831 } 1832 1833 static int 1834 mlx5e_open_tises(struct mlx5e_priv *priv) 1835 { 1836 int num_tc = priv->num_tc; 1837 int err; 1838 int tc; 1839 1840 for (tc = 0; tc < num_tc; tc++) { 1841 err = mlx5e_open_tis(priv, tc); 1842 if (err) 1843 goto err_close_tises; 1844 } 1845 1846 return (0); 1847 1848 err_close_tises: 1849 for (tc--; tc >= 0; tc--) 1850 mlx5e_close_tis(priv, tc); 1851 1852 return (err); 1853 } 1854 1855 static void 1856 mlx5e_close_tises(struct mlx5e_priv *priv) 1857 { 1858 int num_tc = priv->num_tc; 1859 int tc; 1860 1861 for (tc = 0; tc < num_tc; tc++) 1862 mlx5e_close_tis(priv, tc); 1863 } 1864 1865 static int 1866 mlx5e_open_rqt(struct mlx5e_priv *priv) 1867 { 1868 struct mlx5_core_dev *mdev = priv->mdev; 1869 u32 *in; 1870 u32 out[MLX5_ST_SZ_DW(create_rqt_out)]; 1871 void *rqtc; 1872 int inlen; 1873 int err; 1874 int sz; 1875 int i; 1876 1877 sz = 1 << priv->params.rx_hash_log_tbl_sz; 1878 1879 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 1880 in = mlx5_vzalloc(inlen); 1881 if (in == NULL) 1882 return (-ENOMEM); 1883 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1884 1885 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 1886 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 1887 1888 for (i = 0; i < sz; i++) { 1889 int ix; 1890 #ifdef RSS 1891 ix = rss_get_indirection_to_bucket(i); 1892 #else 1893 ix = i; 1894 #endif 1895 /* ensure we don't overflow */ 1896 ix %= priv->params.num_channels; 1897 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn); 1898 } 1899 1900 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1901 1902 memset(out, 0, sizeof(out)); 1903 err = mlx5_cmd_exec_check_status(mdev, in, inlen, out, sizeof(out)); 1904 if (!err) 1905 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn); 1906 1907 kvfree(in); 1908 1909 return (err); 1910 } 1911 1912 static void 1913 mlx5e_close_rqt(struct mlx5e_priv *priv) 1914 { 1915 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)]; 1916 u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)]; 1917 1918 memset(in, 0, sizeof(in)); 1919 1920 MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT); 1921 MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn); 1922 1923 mlx5_cmd_exec_check_status(priv->mdev, in, sizeof(in), out, 1924 sizeof(out)); 1925 } 1926 1927 static void 1928 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt) 1929 { 1930 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1931 __be32 *hkey; 1932 1933 MLX5_SET(tirc, tirc, transport_domain, priv->tdn); 1934 1935 #define ROUGH_MAX_L2_L3_HDR_SZ 256 1936 1937 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\ 1938 MLX5_HASH_FIELD_SEL_DST_IP) 1939 1940 #define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\ 1941 MLX5_HASH_FIELD_SEL_DST_IP |\ 1942 MLX5_HASH_FIELD_SEL_L4_SPORT |\ 1943 MLX5_HASH_FIELD_SEL_L4_DPORT) 1944 1945 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\ 1946 MLX5_HASH_FIELD_SEL_DST_IP |\ 1947 MLX5_HASH_FIELD_SEL_IPSEC_SPI) 1948 1949 if (priv->params.hw_lro_en) { 1950 MLX5_SET(tirc, tirc, lro_enable_mask, 1951 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | 1952 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO); 1953 MLX5_SET(tirc, tirc, lro_max_msg_sz, 1954 (priv->params.lro_wqe_sz - 1955 ROUGH_MAX_L2_L3_HDR_SZ) >> 8); 1956 /* TODO: add the option to choose timer value dynamically */ 1957 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, 1958 MLX5_CAP_ETH(priv->mdev, 1959 lro_timer_supported_periods[2])); 1960 } 1961 1962 /* setup parameters for hashing TIR type, if any */ 1963 switch (tt) { 1964 case MLX5E_TT_ANY: 1965 MLX5_SET(tirc, tirc, disp_type, 1966 MLX5_TIRC_DISP_TYPE_DIRECT); 1967 MLX5_SET(tirc, tirc, inline_rqn, 1968 priv->channel[0]->rq.rqn); 1969 break; 1970 default: 1971 MLX5_SET(tirc, tirc, disp_type, 1972 MLX5_TIRC_DISP_TYPE_INDIRECT); 1973 MLX5_SET(tirc, tirc, indirect_table, 1974 priv->rqtn); 1975 MLX5_SET(tirc, tirc, rx_hash_fn, 1976 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ); 1977 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1978 #ifdef RSS 1979 /* 1980 * The FreeBSD RSS implementation does currently not 1981 * support symmetric Toeplitz hashes: 1982 */ 1983 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0); 1984 rss_getkey((uint8_t *)hkey); 1985 #else 1986 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 1987 hkey[0] = cpu_to_be32(0xD181C62C); 1988 hkey[1] = cpu_to_be32(0xF7F4DB5B); 1989 hkey[2] = cpu_to_be32(0x1983A2FC); 1990 hkey[3] = cpu_to_be32(0x943E1ADB); 1991 hkey[4] = cpu_to_be32(0xD9389E6B); 1992 hkey[5] = cpu_to_be32(0xD1039C2C); 1993 hkey[6] = cpu_to_be32(0xA74499AD); 1994 hkey[7] = cpu_to_be32(0x593D56D9); 1995 hkey[8] = cpu_to_be32(0xF3253C06); 1996 hkey[9] = cpu_to_be32(0x2ADC1FFC); 1997 #endif 1998 break; 1999 } 2000 2001 switch (tt) { 2002 case MLX5E_TT_IPV4_TCP: 2003 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2004 MLX5_L3_PROT_TYPE_IPV4); 2005 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2006 MLX5_L4_PROT_TYPE_TCP); 2007 #ifdef RSS 2008 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) { 2009 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2010 MLX5_HASH_IP); 2011 } else 2012 #endif 2013 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2014 MLX5_HASH_ALL); 2015 break; 2016 2017 case MLX5E_TT_IPV6_TCP: 2018 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2019 MLX5_L3_PROT_TYPE_IPV6); 2020 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2021 MLX5_L4_PROT_TYPE_TCP); 2022 #ifdef RSS 2023 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) { 2024 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2025 MLX5_HASH_IP); 2026 } else 2027 #endif 2028 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2029 MLX5_HASH_ALL); 2030 break; 2031 2032 case MLX5E_TT_IPV4_UDP: 2033 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2034 MLX5_L3_PROT_TYPE_IPV4); 2035 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2036 MLX5_L4_PROT_TYPE_UDP); 2037 #ifdef RSS 2038 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) { 2039 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2040 MLX5_HASH_IP); 2041 } else 2042 #endif 2043 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2044 MLX5_HASH_ALL); 2045 break; 2046 2047 case MLX5E_TT_IPV6_UDP: 2048 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2049 MLX5_L3_PROT_TYPE_IPV6); 2050 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2051 MLX5_L4_PROT_TYPE_UDP); 2052 #ifdef RSS 2053 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) { 2054 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2055 MLX5_HASH_IP); 2056 } else 2057 #endif 2058 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2059 MLX5_HASH_ALL); 2060 break; 2061 2062 case MLX5E_TT_IPV4_IPSEC_AH: 2063 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2064 MLX5_L3_PROT_TYPE_IPV4); 2065 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2066 MLX5_HASH_IP_IPSEC_SPI); 2067 break; 2068 2069 case MLX5E_TT_IPV6_IPSEC_AH: 2070 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2071 MLX5_L3_PROT_TYPE_IPV6); 2072 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2073 MLX5_HASH_IP_IPSEC_SPI); 2074 break; 2075 2076 case MLX5E_TT_IPV4_IPSEC_ESP: 2077 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2078 MLX5_L3_PROT_TYPE_IPV4); 2079 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2080 MLX5_HASH_IP_IPSEC_SPI); 2081 break; 2082 2083 case MLX5E_TT_IPV6_IPSEC_ESP: 2084 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2085 MLX5_L3_PROT_TYPE_IPV6); 2086 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2087 MLX5_HASH_IP_IPSEC_SPI); 2088 break; 2089 2090 case MLX5E_TT_IPV4: 2091 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2092 MLX5_L3_PROT_TYPE_IPV4); 2093 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2094 MLX5_HASH_IP); 2095 break; 2096 2097 case MLX5E_TT_IPV6: 2098 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2099 MLX5_L3_PROT_TYPE_IPV6); 2100 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2101 MLX5_HASH_IP); 2102 break; 2103 2104 default: 2105 break; 2106 } 2107 } 2108 2109 static int 2110 mlx5e_open_tir(struct mlx5e_priv *priv, int tt) 2111 { 2112 struct mlx5_core_dev *mdev = priv->mdev; 2113 u32 *in; 2114 void *tirc; 2115 int inlen; 2116 int err; 2117 2118 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 2119 in = mlx5_vzalloc(inlen); 2120 if (in == NULL) 2121 return (-ENOMEM); 2122 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context); 2123 2124 mlx5e_build_tir_ctx(priv, tirc, tt); 2125 2126 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]); 2127 2128 kvfree(in); 2129 2130 return (err); 2131 } 2132 2133 static void 2134 mlx5e_close_tir(struct mlx5e_priv *priv, int tt) 2135 { 2136 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]); 2137 } 2138 2139 static int 2140 mlx5e_open_tirs(struct mlx5e_priv *priv) 2141 { 2142 int err; 2143 int i; 2144 2145 for (i = 0; i < MLX5E_NUM_TT; i++) { 2146 err = mlx5e_open_tir(priv, i); 2147 if (err) 2148 goto err_close_tirs; 2149 } 2150 2151 return (0); 2152 2153 err_close_tirs: 2154 for (i--; i >= 0; i--) 2155 mlx5e_close_tir(priv, i); 2156 2157 return (err); 2158 } 2159 2160 static void 2161 mlx5e_close_tirs(struct mlx5e_priv *priv) 2162 { 2163 int i; 2164 2165 for (i = 0; i < MLX5E_NUM_TT; i++) 2166 mlx5e_close_tir(priv, i); 2167 } 2168 2169 /* 2170 * SW MTU does not include headers, 2171 * HW MTU includes all headers and checksums. 2172 */ 2173 static int 2174 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu) 2175 { 2176 struct mlx5e_priv *priv = ifp->if_softc; 2177 struct mlx5_core_dev *mdev = priv->mdev; 2178 int hw_mtu; 2179 int err; 2180 2181 err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(sw_mtu)); 2182 if (err) { 2183 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n", 2184 __func__, sw_mtu, err); 2185 return (err); 2186 } 2187 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu); 2188 if (err) { 2189 if_printf(ifp, "Query port MTU, after setting new " 2190 "MTU value, failed\n"); 2191 } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) { 2192 err = -E2BIG, 2193 if_printf(ifp, "Port MTU %d is smaller than " 2194 "ifp mtu %d\n", hw_mtu, sw_mtu); 2195 } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) { 2196 err = -EINVAL; 2197 if_printf(ifp, "Port MTU %d is bigger than " 2198 "ifp mtu %d\n", hw_mtu, sw_mtu); 2199 } 2200 ifp->if_mtu = sw_mtu; 2201 return (err); 2202 } 2203 2204 int 2205 mlx5e_open_locked(struct ifnet *ifp) 2206 { 2207 struct mlx5e_priv *priv = ifp->if_softc; 2208 int err; 2209 u16 set_id; 2210 2211 /* check if already opened */ 2212 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 2213 return (0); 2214 2215 #ifdef RSS 2216 if (rss_getnumbuckets() > priv->params.num_channels) { 2217 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than " 2218 "channels(%u) available\n", rss_getnumbuckets(), 2219 priv->params.num_channels); 2220 } 2221 #endif 2222 err = mlx5e_open_tises(priv); 2223 if (err) { 2224 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n", 2225 __func__, err); 2226 return (err); 2227 } 2228 err = mlx5_vport_alloc_q_counter(priv->mdev, 2229 MLX5_INTERFACE_PROTOCOL_ETH, &set_id); 2230 if (err) { 2231 if_printf(priv->ifp, 2232 "%s: mlx5_vport_alloc_q_counter failed: %d\n", 2233 __func__, err); 2234 goto err_close_tises; 2235 } 2236 /* store counter set ID */ 2237 priv->counter_set_id = set_id; 2238 2239 err = mlx5e_open_channels(priv); 2240 if (err) { 2241 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n", 2242 __func__, err); 2243 goto err_dalloc_q_counter; 2244 } 2245 err = mlx5e_open_rqt(priv); 2246 if (err) { 2247 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n", 2248 __func__, err); 2249 goto err_close_channels; 2250 } 2251 err = mlx5e_open_tirs(priv); 2252 if (err) { 2253 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n", 2254 __func__, err); 2255 goto err_close_rqls; 2256 } 2257 err = mlx5e_open_flow_table(priv); 2258 if (err) { 2259 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n", 2260 __func__, err); 2261 goto err_close_tirs; 2262 } 2263 err = mlx5e_add_all_vlan_rules(priv); 2264 if (err) { 2265 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n", 2266 __func__, err); 2267 goto err_close_flow_table; 2268 } 2269 set_bit(MLX5E_STATE_OPENED, &priv->state); 2270 2271 mlx5e_update_carrier(priv); 2272 mlx5e_set_rx_mode_core(priv); 2273 2274 return (0); 2275 2276 err_close_flow_table: 2277 mlx5e_close_flow_table(priv); 2278 2279 err_close_tirs: 2280 mlx5e_close_tirs(priv); 2281 2282 err_close_rqls: 2283 mlx5e_close_rqt(priv); 2284 2285 err_close_channels: 2286 mlx5e_close_channels(priv); 2287 2288 err_dalloc_q_counter: 2289 mlx5_vport_dealloc_q_counter(priv->mdev, 2290 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 2291 2292 err_close_tises: 2293 mlx5e_close_tises(priv); 2294 2295 return (err); 2296 } 2297 2298 static void 2299 mlx5e_open(void *arg) 2300 { 2301 struct mlx5e_priv *priv = arg; 2302 2303 PRIV_LOCK(priv); 2304 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP)) 2305 if_printf(priv->ifp, 2306 "%s: Setting port status to up failed\n", 2307 __func__); 2308 2309 mlx5e_open_locked(priv->ifp); 2310 priv->ifp->if_drv_flags |= IFF_DRV_RUNNING; 2311 PRIV_UNLOCK(priv); 2312 } 2313 2314 int 2315 mlx5e_close_locked(struct ifnet *ifp) 2316 { 2317 struct mlx5e_priv *priv = ifp->if_softc; 2318 2319 /* check if already closed */ 2320 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 2321 return (0); 2322 2323 clear_bit(MLX5E_STATE_OPENED, &priv->state); 2324 2325 mlx5e_set_rx_mode_core(priv); 2326 mlx5e_del_all_vlan_rules(priv); 2327 if_link_state_change(priv->ifp, LINK_STATE_DOWN); 2328 mlx5e_close_flow_table(priv); 2329 mlx5e_close_tirs(priv); 2330 mlx5e_close_rqt(priv); 2331 mlx5e_close_channels(priv); 2332 mlx5_vport_dealloc_q_counter(priv->mdev, 2333 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 2334 mlx5e_close_tises(priv); 2335 2336 return (0); 2337 } 2338 2339 #if (__FreeBSD_version >= 1100000) 2340 static uint64_t 2341 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt) 2342 { 2343 struct mlx5e_priv *priv = ifp->if_softc; 2344 u64 retval; 2345 2346 /* PRIV_LOCK(priv); XXX not allowed */ 2347 switch (cnt) { 2348 case IFCOUNTER_IPACKETS: 2349 retval = priv->stats.vport.rx_packets; 2350 break; 2351 case IFCOUNTER_IERRORS: 2352 retval = priv->stats.vport.rx_error_packets; 2353 break; 2354 case IFCOUNTER_IQDROPS: 2355 retval = priv->stats.vport.rx_out_of_buffer; 2356 break; 2357 case IFCOUNTER_OPACKETS: 2358 retval = priv->stats.vport.tx_packets; 2359 break; 2360 case IFCOUNTER_OERRORS: 2361 retval = priv->stats.vport.tx_error_packets; 2362 break; 2363 case IFCOUNTER_IBYTES: 2364 retval = priv->stats.vport.rx_bytes; 2365 break; 2366 case IFCOUNTER_OBYTES: 2367 retval = priv->stats.vport.tx_bytes; 2368 break; 2369 case IFCOUNTER_IMCASTS: 2370 retval = priv->stats.vport.rx_multicast_packets; 2371 break; 2372 case IFCOUNTER_OMCASTS: 2373 retval = priv->stats.vport.tx_multicast_packets; 2374 break; 2375 case IFCOUNTER_OQDROPS: 2376 retval = priv->stats.vport.tx_queue_dropped; 2377 break; 2378 default: 2379 retval = if_get_counter_default(ifp, cnt); 2380 break; 2381 } 2382 /* PRIV_UNLOCK(priv); XXX not allowed */ 2383 return (retval); 2384 } 2385 #endif 2386 2387 static void 2388 mlx5e_set_rx_mode(struct ifnet *ifp) 2389 { 2390 struct mlx5e_priv *priv = ifp->if_softc; 2391 2392 schedule_work(&priv->set_rx_mode_work); 2393 } 2394 2395 static int 2396 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2397 { 2398 struct mlx5e_priv *priv; 2399 struct ifreq *ifr; 2400 struct ifi2creq i2c; 2401 int error = 0; 2402 int mask = 0; 2403 int size_read = 0; 2404 int module_num; 2405 int max_mtu; 2406 uint8_t read_addr; 2407 2408 priv = ifp->if_softc; 2409 2410 /* check if detaching */ 2411 if (priv == NULL || priv->gone != 0) 2412 return (ENXIO); 2413 2414 switch (command) { 2415 case SIOCSIFMTU: 2416 ifr = (struct ifreq *)data; 2417 2418 PRIV_LOCK(priv); 2419 mlx5_query_port_max_mtu(priv->mdev, &max_mtu); 2420 2421 if (ifr->ifr_mtu >= MLX5E_MTU_MIN && 2422 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) { 2423 int was_opened; 2424 2425 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 2426 if (was_opened) 2427 mlx5e_close_locked(ifp); 2428 2429 /* set new MTU */ 2430 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu); 2431 2432 if (was_opened) 2433 mlx5e_open_locked(ifp); 2434 } else { 2435 error = EINVAL; 2436 if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n", 2437 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu)); 2438 } 2439 PRIV_UNLOCK(priv); 2440 break; 2441 case SIOCSIFFLAGS: 2442 if ((ifp->if_flags & IFF_UP) && 2443 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 2444 mlx5e_set_rx_mode(ifp); 2445 break; 2446 } 2447 PRIV_LOCK(priv); 2448 if (ifp->if_flags & IFF_UP) { 2449 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2450 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 2451 mlx5e_open_locked(ifp); 2452 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2453 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP); 2454 } 2455 } else { 2456 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2457 mlx5_set_port_status(priv->mdev, 2458 MLX5_PORT_DOWN); 2459 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 2460 mlx5e_close_locked(ifp); 2461 mlx5e_update_carrier(priv); 2462 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2463 } 2464 } 2465 PRIV_UNLOCK(priv); 2466 break; 2467 case SIOCADDMULTI: 2468 case SIOCDELMULTI: 2469 mlx5e_set_rx_mode(ifp); 2470 break; 2471 case SIOCSIFMEDIA: 2472 case SIOCGIFMEDIA: 2473 case SIOCGIFXMEDIA: 2474 ifr = (struct ifreq *)data; 2475 error = ifmedia_ioctl(ifp, ifr, &priv->media, command); 2476 break; 2477 case SIOCSIFCAP: 2478 ifr = (struct ifreq *)data; 2479 PRIV_LOCK(priv); 2480 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2481 2482 if (mask & IFCAP_TXCSUM) { 2483 ifp->if_capenable ^= IFCAP_TXCSUM; 2484 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 2485 2486 if (IFCAP_TSO4 & ifp->if_capenable && 2487 !(IFCAP_TXCSUM & ifp->if_capenable)) { 2488 ifp->if_capenable &= ~IFCAP_TSO4; 2489 ifp->if_hwassist &= ~CSUM_IP_TSO; 2490 if_printf(ifp, 2491 "tso4 disabled due to -txcsum.\n"); 2492 } 2493 } 2494 if (mask & IFCAP_TXCSUM_IPV6) { 2495 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 2496 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 2497 2498 if (IFCAP_TSO6 & ifp->if_capenable && 2499 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 2500 ifp->if_capenable &= ~IFCAP_TSO6; 2501 ifp->if_hwassist &= ~CSUM_IP6_TSO; 2502 if_printf(ifp, 2503 "tso6 disabled due to -txcsum6.\n"); 2504 } 2505 } 2506 if (mask & IFCAP_RXCSUM) 2507 ifp->if_capenable ^= IFCAP_RXCSUM; 2508 if (mask & IFCAP_RXCSUM_IPV6) 2509 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 2510 if (mask & IFCAP_TSO4) { 2511 if (!(IFCAP_TSO4 & ifp->if_capenable) && 2512 !(IFCAP_TXCSUM & ifp->if_capenable)) { 2513 if_printf(ifp, "enable txcsum first.\n"); 2514 error = EAGAIN; 2515 goto out; 2516 } 2517 ifp->if_capenable ^= IFCAP_TSO4; 2518 ifp->if_hwassist ^= CSUM_IP_TSO; 2519 } 2520 if (mask & IFCAP_TSO6) { 2521 if (!(IFCAP_TSO6 & ifp->if_capenable) && 2522 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 2523 if_printf(ifp, "enable txcsum6 first.\n"); 2524 error = EAGAIN; 2525 goto out; 2526 } 2527 ifp->if_capenable ^= IFCAP_TSO6; 2528 ifp->if_hwassist ^= CSUM_IP6_TSO; 2529 } 2530 if (mask & IFCAP_VLAN_HWFILTER) { 2531 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) 2532 mlx5e_disable_vlan_filter(priv); 2533 else 2534 mlx5e_enable_vlan_filter(priv); 2535 2536 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER; 2537 } 2538 if (mask & IFCAP_VLAN_HWTAGGING) 2539 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2540 if (mask & IFCAP_WOL_MAGIC) 2541 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2542 2543 VLAN_CAPABILITIES(ifp); 2544 /* turn off LRO means also turn of HW LRO - if it's on */ 2545 if (mask & IFCAP_LRO) { 2546 int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 2547 bool need_restart = false; 2548 2549 ifp->if_capenable ^= IFCAP_LRO; 2550 if (!(ifp->if_capenable & IFCAP_LRO)) { 2551 if (priv->params.hw_lro_en) { 2552 priv->params.hw_lro_en = false; 2553 need_restart = true; 2554 /* Not sure this is the correct way */ 2555 priv->params_ethtool.hw_lro = priv->params.hw_lro_en; 2556 } 2557 } 2558 if (was_opened && need_restart) { 2559 mlx5e_close_locked(ifp); 2560 mlx5e_open_locked(ifp); 2561 } 2562 } 2563 out: 2564 PRIV_UNLOCK(priv); 2565 break; 2566 2567 case SIOCGI2C: 2568 ifr = (struct ifreq *)data; 2569 2570 /* 2571 * Copy from the user-space address ifr_data to the 2572 * kernel-space address i2c 2573 */ 2574 error = copyin(ifr->ifr_data, &i2c, sizeof(i2c)); 2575 if (error) 2576 break; 2577 2578 if (i2c.len > sizeof(i2c.data)) { 2579 error = EINVAL; 2580 break; 2581 } 2582 2583 PRIV_LOCK(priv); 2584 /* Get module_num which is required for the query_eeprom */ 2585 error = mlx5_query_module_num(priv->mdev, &module_num); 2586 if (error) { 2587 if_printf(ifp, "Query module num failed, eeprom " 2588 "reading is not supported\n"); 2589 error = EINVAL; 2590 goto err_i2c; 2591 } 2592 /* Check if module is present before doing an access */ 2593 if (mlx5_query_module_status(priv->mdev, module_num) != 2594 MLX5_MODULE_STATUS_PLUGGED) { 2595 error = EINVAL; 2596 goto err_i2c; 2597 } 2598 /* 2599 * Currently 0XA0 and 0xA2 are the only addresses permitted. 2600 * The internal conversion is as follows: 2601 */ 2602 if (i2c.dev_addr == 0xA0) 2603 read_addr = MLX5E_I2C_ADDR_LOW; 2604 else if (i2c.dev_addr == 0xA2) 2605 read_addr = MLX5E_I2C_ADDR_HIGH; 2606 else { 2607 if_printf(ifp, "Query eeprom failed, " 2608 "Invalid Address: %X\n", i2c.dev_addr); 2609 error = EINVAL; 2610 goto err_i2c; 2611 } 2612 error = mlx5_query_eeprom(priv->mdev, 2613 read_addr, MLX5E_EEPROM_LOW_PAGE, 2614 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num, 2615 (uint32_t *)i2c.data, &size_read); 2616 if (error) { 2617 if_printf(ifp, "Query eeprom failed, eeprom " 2618 "reading is not supported\n"); 2619 error = EINVAL; 2620 goto err_i2c; 2621 } 2622 2623 if (i2c.len > MLX5_EEPROM_MAX_BYTES) { 2624 error = mlx5_query_eeprom(priv->mdev, 2625 read_addr, MLX5E_EEPROM_LOW_PAGE, 2626 (uint32_t)(i2c.offset + size_read), 2627 (uint32_t)(i2c.len - size_read), module_num, 2628 (uint32_t *)(i2c.data + size_read), &size_read); 2629 } 2630 if (error) { 2631 if_printf(ifp, "Query eeprom failed, eeprom " 2632 "reading is not supported\n"); 2633 error = EINVAL; 2634 goto err_i2c; 2635 } 2636 2637 error = copyout(&i2c, ifr->ifr_data, sizeof(i2c)); 2638 err_i2c: 2639 PRIV_UNLOCK(priv); 2640 break; 2641 2642 default: 2643 error = ether_ioctl(ifp, command, data); 2644 break; 2645 } 2646 return (error); 2647 } 2648 2649 static int 2650 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev) 2651 { 2652 /* 2653 * TODO: uncoment once FW really sets all these bits if 2654 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap || 2655 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap || 2656 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return 2657 * -ENOTSUPP; 2658 */ 2659 2660 /* TODO: add more must-to-have features */ 2661 2662 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) 2663 return (-ENODEV); 2664 2665 return (0); 2666 } 2667 2668 static void 2669 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev, 2670 struct mlx5e_priv *priv, 2671 int num_comp_vectors) 2672 { 2673 /* 2674 * TODO: Consider link speed for setting "log_sq_size", 2675 * "log_rq_size" and "cq_moderation_xxx": 2676 */ 2677 priv->params.log_sq_size = 2678 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; 2679 priv->params.log_rq_size = 2680 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; 2681 priv->params.rx_cq_moderation_usec = 2682 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 2683 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE : 2684 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; 2685 priv->params.rx_cq_moderation_mode = 2686 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0; 2687 priv->params.rx_cq_moderation_pkts = 2688 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; 2689 priv->params.tx_cq_moderation_usec = 2690 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; 2691 priv->params.tx_cq_moderation_pkts = 2692 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; 2693 priv->params.min_rx_wqes = 2694 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES; 2695 priv->params.rx_hash_log_tbl_sz = 2696 (order_base_2(num_comp_vectors) > 2697 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ? 2698 order_base_2(num_comp_vectors) : 2699 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ; 2700 priv->params.num_tc = 1; 2701 priv->params.default_vlan_prio = 0; 2702 priv->counter_set_id = -1; 2703 2704 /* 2705 * hw lro is currently defaulted to off. when it won't anymore we 2706 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)" 2707 */ 2708 priv->params.hw_lro_en = false; 2709 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; 2710 2711 priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression); 2712 2713 priv->mdev = mdev; 2714 priv->params.num_channels = num_comp_vectors; 2715 priv->order_base_2_num_channels = order_base_2(num_comp_vectors); 2716 priv->queue_mapping_channel_mask = 2717 roundup_pow_of_two(num_comp_vectors) - 1; 2718 priv->num_tc = priv->params.num_tc; 2719 priv->default_vlan_prio = priv->params.default_vlan_prio; 2720 2721 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work); 2722 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); 2723 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); 2724 } 2725 2726 static int 2727 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn, 2728 struct mlx5_core_mr *mr) 2729 { 2730 struct ifnet *ifp = priv->ifp; 2731 struct mlx5_core_dev *mdev = priv->mdev; 2732 struct mlx5_create_mkey_mbox_in *in; 2733 int err; 2734 2735 in = mlx5_vzalloc(sizeof(*in)); 2736 if (in == NULL) { 2737 if_printf(ifp, "%s: failed to allocate inbox\n", __func__); 2738 return (-ENOMEM); 2739 } 2740 in->seg.flags = MLX5_PERM_LOCAL_WRITE | 2741 MLX5_PERM_LOCAL_READ | 2742 MLX5_ACCESS_MODE_PA; 2743 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64); 2744 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8); 2745 2746 err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL, 2747 NULL); 2748 if (err) 2749 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n", 2750 __func__, err); 2751 2752 kvfree(in); 2753 2754 return (err); 2755 } 2756 2757 static const char *mlx5e_vport_stats_desc[] = { 2758 MLX5E_VPORT_STATS(MLX5E_STATS_DESC) 2759 }; 2760 2761 static const char *mlx5e_pport_stats_desc[] = { 2762 MLX5E_PPORT_STATS(MLX5E_STATS_DESC) 2763 }; 2764 2765 static void 2766 mlx5e_priv_mtx_init(struct mlx5e_priv *priv) 2767 { 2768 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF); 2769 sx_init(&priv->state_lock, "mlx5state"); 2770 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0); 2771 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock); 2772 } 2773 2774 static void 2775 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv) 2776 { 2777 mtx_destroy(&priv->async_events_mtx); 2778 sx_destroy(&priv->state_lock); 2779 } 2780 2781 static int 2782 sysctl_firmware(SYSCTL_HANDLER_ARGS) 2783 { 2784 /* 2785 * %d.%d%.d the string format. 2786 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536. 2787 * We need at most 5 chars to store that. 2788 * It also has: two "." and NULL at the end, which means we need 18 2789 * (5*3 + 3) chars at most. 2790 */ 2791 char fw[18]; 2792 struct mlx5e_priv *priv = arg1; 2793 int error; 2794 2795 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev), 2796 fw_rev_sub(priv->mdev)); 2797 error = sysctl_handle_string(oidp, fw, sizeof(fw), req); 2798 return (error); 2799 } 2800 2801 static void 2802 mlx5e_add_hw_stats(struct mlx5e_priv *priv) 2803 { 2804 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 2805 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0, 2806 sysctl_firmware, "A", "HCA firmware version"); 2807 2808 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 2809 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0, 2810 "Board ID"); 2811 } 2812 2813 static void 2814 mlx5e_setup_pauseframes(struct mlx5e_priv *priv) 2815 { 2816 #if (__FreeBSD_version < 1100000) 2817 char path[64]; 2818 2819 #endif 2820 /* Only receiving pauseframes is enabled by default */ 2821 priv->params.tx_pauseframe_control = 0; 2822 priv->params.rx_pauseframe_control = 1; 2823 2824 #if (__FreeBSD_version < 1100000) 2825 /* compute path for sysctl */ 2826 snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control", 2827 device_get_unit(priv->mdev->pdev->dev.bsddev)); 2828 2829 /* try to fetch tunable, if any */ 2830 TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control); 2831 2832 /* compute path for sysctl */ 2833 snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control", 2834 device_get_unit(priv->mdev->pdev->dev.bsddev)); 2835 2836 /* try to fetch tunable, if any */ 2837 TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control); 2838 #endif 2839 2840 /* register pausframe SYSCTLs */ 2841 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 2842 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN, 2843 &priv->params.tx_pauseframe_control, 0, 2844 "Set to enable TX pause frames. Clear to disable."); 2845 2846 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 2847 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN, 2848 &priv->params.rx_pauseframe_control, 0, 2849 "Set to enable RX pause frames. Clear to disable."); 2850 2851 /* range check */ 2852 priv->params.tx_pauseframe_control = 2853 priv->params.tx_pauseframe_control ? 1 : 0; 2854 priv->params.rx_pauseframe_control = 2855 priv->params.rx_pauseframe_control ? 1 : 0; 2856 2857 /* update firmware */ 2858 mlx5_set_port_pause(priv->mdev, 1, 2859 priv->params.rx_pauseframe_control, 2860 priv->params.tx_pauseframe_control); 2861 } 2862 2863 static void * 2864 mlx5e_create_ifp(struct mlx5_core_dev *mdev) 2865 { 2866 static volatile int mlx5_en_unit; 2867 struct ifnet *ifp; 2868 struct mlx5e_priv *priv; 2869 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4); 2870 struct sysctl_oid_list *child; 2871 int ncv = mdev->priv.eq_table.num_comp_vectors; 2872 char unit[16]; 2873 int err; 2874 int i; 2875 u32 eth_proto_cap; 2876 2877 if (mlx5e_check_required_hca_cap(mdev)) { 2878 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n"); 2879 return (NULL); 2880 } 2881 priv = malloc(sizeof(*priv), M_MLX5EN, M_WAITOK | M_ZERO); 2882 if (priv == NULL) { 2883 mlx5_core_err(mdev, "malloc() failed\n"); 2884 return (NULL); 2885 } 2886 mlx5e_priv_mtx_init(priv); 2887 2888 ifp = priv->ifp = if_alloc(IFT_ETHER); 2889 if (ifp == NULL) { 2890 mlx5_core_err(mdev, "if_alloc() failed\n"); 2891 goto err_free_priv; 2892 } 2893 ifp->if_softc = priv; 2894 if_initname(ifp, "mce", atomic_fetchadd_int(&mlx5_en_unit, 1)); 2895 ifp->if_mtu = ETHERMTU; 2896 ifp->if_init = mlx5e_open; 2897 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2898 ifp->if_ioctl = mlx5e_ioctl; 2899 ifp->if_transmit = mlx5e_xmit; 2900 ifp->if_qflush = if_qflush; 2901 #if (__FreeBSD_version >= 1100000) 2902 ifp->if_get_counter = mlx5e_get_counter; 2903 #endif 2904 ifp->if_snd.ifq_maxlen = ifqmaxlen; 2905 /* 2906 * Set driver features 2907 */ 2908 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6; 2909 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 2910 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER; 2911 ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU; 2912 ifp->if_capabilities |= IFCAP_LRO; 2913 ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO; 2914 ifp->if_capabilities |= IFCAP_HWSTATS; 2915 2916 /* set TSO limits so that we don't have to drop TX packets */ 2917 ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 2918 ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */; 2919 ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE; 2920 2921 ifp->if_capenable = ifp->if_capabilities; 2922 ifp->if_hwassist = 0; 2923 if (ifp->if_capenable & IFCAP_TSO) 2924 ifp->if_hwassist |= CSUM_TSO; 2925 if (ifp->if_capenable & IFCAP_TXCSUM) 2926 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP); 2927 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6) 2928 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 2929 2930 /* ifnet sysctl tree */ 2931 sysctl_ctx_init(&priv->sysctl_ctx); 2932 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev), 2933 OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name"); 2934 if (priv->sysctl_ifnet == NULL) { 2935 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 2936 goto err_free_sysctl; 2937 } 2938 snprintf(unit, sizeof(unit), "%d", ifp->if_dunit); 2939 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 2940 OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit"); 2941 if (priv->sysctl_ifnet == NULL) { 2942 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 2943 goto err_free_sysctl; 2944 } 2945 2946 /* HW sysctl tree */ 2947 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev)); 2948 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child, 2949 OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw"); 2950 if (priv->sysctl_hw == NULL) { 2951 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 2952 goto err_free_sysctl; 2953 } 2954 mlx5e_build_ifp_priv(mdev, priv, ncv); 2955 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar); 2956 if (err) { 2957 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n", 2958 __func__, err); 2959 goto err_free_sysctl; 2960 } 2961 err = mlx5_core_alloc_pd(mdev, &priv->pdn); 2962 if (err) { 2963 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n", 2964 __func__, err); 2965 goto err_unmap_free_uar; 2966 } 2967 err = mlx5_alloc_transport_domain(mdev, &priv->tdn); 2968 if (err) { 2969 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n", 2970 __func__, err); 2971 goto err_dealloc_pd; 2972 } 2973 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr); 2974 if (err) { 2975 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n", 2976 __func__, err); 2977 goto err_dealloc_transport_domain; 2978 } 2979 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr); 2980 2981 /* check if we should generate a random MAC address */ 2982 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 && 2983 is_zero_ether_addr(dev_addr)) { 2984 random_ether_addr(dev_addr); 2985 if_printf(ifp, "Assigned random MAC address\n"); 2986 } 2987 2988 /* set default MTU */ 2989 mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu); 2990 2991 /* Set desc */ 2992 device_set_desc(mdev->pdev->dev.bsddev, mlx5e_version); 2993 2994 /* Set default media status */ 2995 priv->media_status_last = IFM_AVALID; 2996 priv->media_active_last = IFM_ETHER | IFM_AUTO | 2997 IFM_ETH_RXPAUSE | IFM_FDX; 2998 2999 /* setup default pauseframes configuration */ 3000 mlx5e_setup_pauseframes(priv); 3001 3002 err = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN); 3003 if (err) { 3004 eth_proto_cap = 0; 3005 if_printf(ifp, "%s: Query port media capability failed, %d\n", 3006 __func__, err); 3007 } 3008 3009 /* Setup supported medias */ 3010 ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK, 3011 mlx5e_media_change, mlx5e_media_status); 3012 3013 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) { 3014 if (mlx5e_mode_table[i].baudrate == 0) 3015 continue; 3016 if (MLX5E_PROT_MASK(i) & eth_proto_cap) { 3017 ifmedia_add(&priv->media, 3018 mlx5e_mode_table[i].subtype | 3019 IFM_ETHER, 0, NULL); 3020 ifmedia_add(&priv->media, 3021 mlx5e_mode_table[i].subtype | 3022 IFM_ETHER | IFM_FDX | 3023 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 3024 } 3025 } 3026 3027 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL); 3028 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX | 3029 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 3030 3031 /* Set autoselect by default */ 3032 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX | 3033 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE); 3034 ether_ifattach(ifp, dev_addr); 3035 3036 /* Register for VLAN events */ 3037 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config, 3038 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST); 3039 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig, 3040 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST); 3041 3042 /* Link is down by default */ 3043 if_link_state_change(ifp, LINK_STATE_DOWN); 3044 3045 mlx5e_enable_async_events(priv); 3046 3047 mlx5e_add_hw_stats(priv); 3048 3049 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 3050 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM, 3051 priv->stats.vport.arg); 3052 3053 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 3054 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM, 3055 priv->stats.pport.arg); 3056 3057 mlx5e_create_ethtool(priv); 3058 3059 mtx_lock(&priv->async_events_mtx); 3060 mlx5e_update_stats(priv); 3061 mtx_unlock(&priv->async_events_mtx); 3062 3063 return (priv); 3064 3065 err_dealloc_transport_domain: 3066 mlx5_dealloc_transport_domain(mdev, priv->tdn); 3067 3068 err_dealloc_pd: 3069 mlx5_core_dealloc_pd(mdev, priv->pdn); 3070 3071 err_unmap_free_uar: 3072 mlx5_unmap_free_uar(mdev, &priv->cq_uar); 3073 3074 err_free_sysctl: 3075 sysctl_ctx_free(&priv->sysctl_ctx); 3076 3077 if_free(ifp); 3078 3079 err_free_priv: 3080 mlx5e_priv_mtx_destroy(priv); 3081 free(priv, M_MLX5EN); 3082 return (NULL); 3083 } 3084 3085 static void 3086 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv) 3087 { 3088 struct mlx5e_priv *priv = vpriv; 3089 struct ifnet *ifp = priv->ifp; 3090 3091 /* don't allow more IOCTLs */ 3092 priv->gone = 1; 3093 3094 /* 3095 * Clear the device description to avoid use after free, 3096 * because the bsddev is not destroyed when this module is 3097 * unloaded: 3098 */ 3099 device_set_desc(mdev->pdev->dev.bsddev, NULL); 3100 3101 /* XXX wait a bit to allow IOCTL handlers to complete */ 3102 pause("W", hz); 3103 3104 /* stop watchdog timer */ 3105 callout_drain(&priv->watchdog); 3106 3107 if (priv->vlan_attach != NULL) 3108 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach); 3109 if (priv->vlan_detach != NULL) 3110 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach); 3111 3112 /* make sure device gets closed */ 3113 PRIV_LOCK(priv); 3114 mlx5e_close_locked(ifp); 3115 PRIV_UNLOCK(priv); 3116 3117 /* unregister device */ 3118 ifmedia_removeall(&priv->media); 3119 ether_ifdetach(ifp); 3120 if_free(ifp); 3121 3122 /* destroy all remaining sysctl nodes */ 3123 if (priv->sysctl_debug) 3124 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx); 3125 sysctl_ctx_free(&priv->stats.vport.ctx); 3126 sysctl_ctx_free(&priv->stats.pport.ctx); 3127 sysctl_ctx_free(&priv->sysctl_ctx); 3128 3129 mlx5_core_destroy_mkey(priv->mdev, &priv->mr); 3130 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn); 3131 mlx5_core_dealloc_pd(priv->mdev, priv->pdn); 3132 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar); 3133 mlx5e_disable_async_events(priv); 3134 flush_scheduled_work(); 3135 mlx5e_priv_mtx_destroy(priv); 3136 free(priv, M_MLX5EN); 3137 } 3138 3139 static void * 3140 mlx5e_get_ifp(void *vpriv) 3141 { 3142 struct mlx5e_priv *priv = vpriv; 3143 3144 return (priv->ifp); 3145 } 3146 3147 static struct mlx5_interface mlx5e_interface = { 3148 .add = mlx5e_create_ifp, 3149 .remove = mlx5e_destroy_ifp, 3150 .event = mlx5e_async_event, 3151 .protocol = MLX5_INTERFACE_PROTOCOL_ETH, 3152 .get_dev = mlx5e_get_ifp, 3153 }; 3154 3155 void 3156 mlx5e_init(void) 3157 { 3158 mlx5_register_interface(&mlx5e_interface); 3159 } 3160 3161 void 3162 mlx5e_cleanup(void) 3163 { 3164 mlx5_unregister_interface(&mlx5e_interface); 3165 } 3166 3167 module_init_order(mlx5e_init, SI_ORDER_THIRD); 3168 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD); 3169 3170 #if (__FreeBSD_version >= 1100000) 3171 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1); 3172 #endif 3173 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1); 3174 MODULE_VERSION(mlx5en, 1); 3175