1 /*- 2 * Copyright (c) 2015-2021 Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include "opt_kern_tls.h" 29 #include "opt_rss.h" 30 #include "opt_ratelimit.h" 31 32 #include <dev/mlx5/mlx5_en/en.h> 33 34 #include <sys/eventhandler.h> 35 #include <sys/sockio.h> 36 #include <machine/atomic.h> 37 38 #include <net/debugnet.h> 39 40 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs); 41 static if_snd_tag_query_t mlx5e_ul_snd_tag_query; 42 static if_snd_tag_free_t mlx5e_ul_snd_tag_free; 43 44 struct mlx5e_channel_param { 45 struct mlx5e_rq_param rq; 46 struct mlx5e_sq_param sq; 47 struct mlx5e_cq_param rx_cq; 48 struct mlx5e_cq_param tx_cq; 49 }; 50 51 struct media { 52 u32 subtype; 53 u64 baudrate; 54 }; 55 56 static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER] = 57 { 58 [MLX5E_1000BASE_CX_SGMII] = { 59 .subtype = IFM_1000_CX_SGMII, 60 .baudrate = IF_Mbps(1000ULL), 61 }, 62 [MLX5E_1000BASE_KX] = { 63 .subtype = IFM_1000_KX, 64 .baudrate = IF_Mbps(1000ULL), 65 }, 66 [MLX5E_10GBASE_CX4] = { 67 .subtype = IFM_10G_CX4, 68 .baudrate = IF_Gbps(10ULL), 69 }, 70 [MLX5E_10GBASE_KX4] = { 71 .subtype = IFM_10G_KX4, 72 .baudrate = IF_Gbps(10ULL), 73 }, 74 [MLX5E_10GBASE_KR] = { 75 .subtype = IFM_10G_KR, 76 .baudrate = IF_Gbps(10ULL), 77 }, 78 [MLX5E_20GBASE_KR2] = { 79 .subtype = IFM_20G_KR2, 80 .baudrate = IF_Gbps(20ULL), 81 }, 82 [MLX5E_40GBASE_CR4] = { 83 .subtype = IFM_40G_CR4, 84 .baudrate = IF_Gbps(40ULL), 85 }, 86 [MLX5E_40GBASE_KR4] = { 87 .subtype = IFM_40G_KR4, 88 .baudrate = IF_Gbps(40ULL), 89 }, 90 [MLX5E_56GBASE_R4] = { 91 .subtype = IFM_56G_R4, 92 .baudrate = IF_Gbps(56ULL), 93 }, 94 [MLX5E_10GBASE_CR] = { 95 .subtype = IFM_10G_CR1, 96 .baudrate = IF_Gbps(10ULL), 97 }, 98 [MLX5E_10GBASE_SR] = { 99 .subtype = IFM_10G_SR, 100 .baudrate = IF_Gbps(10ULL), 101 }, 102 [MLX5E_10GBASE_ER_LR] = { 103 .subtype = IFM_10G_ER, 104 .baudrate = IF_Gbps(10ULL), 105 }, 106 [MLX5E_40GBASE_SR4] = { 107 .subtype = IFM_40G_SR4, 108 .baudrate = IF_Gbps(40ULL), 109 }, 110 [MLX5E_40GBASE_LR4_ER4] = { 111 .subtype = IFM_40G_LR4, 112 .baudrate = IF_Gbps(40ULL), 113 }, 114 [MLX5E_100GBASE_CR4] = { 115 .subtype = IFM_100G_CR4, 116 .baudrate = IF_Gbps(100ULL), 117 }, 118 [MLX5E_100GBASE_SR4] = { 119 .subtype = IFM_100G_SR4, 120 .baudrate = IF_Gbps(100ULL), 121 }, 122 [MLX5E_100GBASE_KR4] = { 123 .subtype = IFM_100G_KR4, 124 .baudrate = IF_Gbps(100ULL), 125 }, 126 [MLX5E_100GBASE_LR4] = { 127 .subtype = IFM_100G_LR4, 128 .baudrate = IF_Gbps(100ULL), 129 }, 130 [MLX5E_100BASE_TX] = { 131 .subtype = IFM_100_TX, 132 .baudrate = IF_Mbps(100ULL), 133 }, 134 [MLX5E_1000BASE_T] = { 135 .subtype = IFM_1000_T, 136 .baudrate = IF_Mbps(1000ULL), 137 }, 138 [MLX5E_10GBASE_T] = { 139 .subtype = IFM_10G_T, 140 .baudrate = IF_Gbps(10ULL), 141 }, 142 [MLX5E_25GBASE_CR] = { 143 .subtype = IFM_25G_CR, 144 .baudrate = IF_Gbps(25ULL), 145 }, 146 [MLX5E_25GBASE_KR] = { 147 .subtype = IFM_25G_KR, 148 .baudrate = IF_Gbps(25ULL), 149 }, 150 [MLX5E_25GBASE_SR] = { 151 .subtype = IFM_25G_SR, 152 .baudrate = IF_Gbps(25ULL), 153 }, 154 [MLX5E_50GBASE_CR2] = { 155 .subtype = IFM_50G_CR2, 156 .baudrate = IF_Gbps(50ULL), 157 }, 158 [MLX5E_50GBASE_KR2] = { 159 .subtype = IFM_50G_KR2, 160 .baudrate = IF_Gbps(50ULL), 161 }, 162 [MLX5E_50GBASE_KR4] = { 163 .subtype = IFM_50G_KR4, 164 .baudrate = IF_Gbps(50ULL), 165 }, 166 }; 167 168 static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_CABLE_TYPE_NUMBER] = 169 { 170 /**/ 171 [MLX5E_SGMII_100M][MLX5E_CABLE_TYPE_UNKNOWN] = { 172 .subtype = IFM_100_SGMII, 173 .baudrate = IF_Mbps(100), 174 }, 175 176 /**/ 177 [MLX5E_1000BASE_X_SGMII][MLX5E_CABLE_TYPE_UNKNOWN] = { 178 .subtype = IFM_1000_CX, 179 .baudrate = IF_Mbps(1000), 180 }, 181 [MLX5E_1000BASE_X_SGMII][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 182 .subtype = IFM_1000_SX, 183 .baudrate = IF_Mbps(1000), 184 }, 185 186 /**/ 187 [MLX5E_5GBASE_R][MLX5E_CABLE_TYPE_UNKNOWN] = { 188 .subtype = IFM_5000_KR, 189 .baudrate = IF_Mbps(5000), 190 }, 191 [MLX5E_5GBASE_R][MLX5E_CABLE_TYPE_TWISTED_PAIR] = { 192 .subtype = IFM_5000_T, 193 .baudrate = IF_Mbps(5000), 194 }, 195 196 /**/ 197 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CABLE_TYPE_UNKNOWN] = { 198 .subtype = IFM_10G_KR, 199 .baudrate = IF_Gbps(10ULL), 200 }, 201 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 202 .subtype = IFM_10G_CR1, 203 .baudrate = IF_Gbps(10ULL), 204 }, 205 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 206 .subtype = IFM_10G_SR, 207 .baudrate = IF_Gbps(10ULL), 208 }, 209 210 /**/ 211 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CABLE_TYPE_UNKNOWN] = { 212 .subtype = IFM_40G_KR4, 213 .baudrate = IF_Gbps(40ULL), 214 }, 215 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 216 .subtype = IFM_40G_CR4, 217 .baudrate = IF_Gbps(40ULL), 218 }, 219 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 220 .subtype = IFM_40G_SR4, 221 .baudrate = IF_Gbps(40ULL), 222 }, 223 224 /**/ 225 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_UNKNOWN] = { 226 .subtype = IFM_25G_KR, 227 .baudrate = IF_Gbps(25ULL), 228 }, 229 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 230 .subtype = IFM_25G_CR, 231 .baudrate = IF_Gbps(25ULL), 232 }, 233 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 234 .subtype = IFM_25G_SR, 235 .baudrate = IF_Gbps(25ULL), 236 }, 237 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_TWISTED_PAIR] = { 238 .subtype = IFM_25G_T, 239 .baudrate = IF_Gbps(25ULL), 240 }, 241 242 /**/ 243 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CABLE_TYPE_UNKNOWN] = { 244 .subtype = IFM_50G_KR2, 245 .baudrate = IF_Gbps(50ULL), 246 }, 247 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 248 .subtype = IFM_50G_CR2, 249 .baudrate = IF_Gbps(50ULL), 250 }, 251 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 252 .subtype = IFM_50G_SR2, 253 .baudrate = IF_Gbps(50ULL), 254 }, 255 256 /**/ 257 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CABLE_TYPE_UNKNOWN] = { 258 .subtype = IFM_50G_KR_PAM4, 259 .baudrate = IF_Gbps(50ULL), 260 }, 261 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 262 .subtype = IFM_50G_CP, 263 .baudrate = IF_Gbps(50ULL), 264 }, 265 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 266 .subtype = IFM_50G_SR, 267 .baudrate = IF_Gbps(50ULL), 268 }, 269 270 /**/ 271 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CABLE_TYPE_UNKNOWN] = { 272 .subtype = IFM_100G_KR4, 273 .baudrate = IF_Gbps(100ULL), 274 }, 275 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 276 .subtype = IFM_100G_CR4, 277 .baudrate = IF_Gbps(100ULL), 278 }, 279 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 280 .subtype = IFM_100G_SR4, 281 .baudrate = IF_Gbps(100ULL), 282 }, 283 284 /**/ 285 [MLX5E_100GAUI_1_100GBASE_CR_KR][MLX5E_CABLE_TYPE_UNKNOWN] = { 286 .subtype = IFM_100G_KR_PAM4, 287 .baudrate = IF_Gbps(100ULL), 288 }, 289 [MLX5E_100GAUI_1_100GBASE_CR_KR][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 290 .subtype = IFM_100G_CR_PAM4, 291 .baudrate = IF_Gbps(100ULL), 292 }, 293 [MLX5E_100GAUI_1_100GBASE_CR_KR][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 294 .subtype = IFM_100G_SR2, /* XXX */ 295 .baudrate = IF_Gbps(100ULL), 296 }, 297 298 /**/ 299 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CABLE_TYPE_UNKNOWN] = { 300 .subtype = IFM_100G_KR4, 301 .baudrate = IF_Gbps(100ULL), 302 }, 303 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 304 .subtype = IFM_100G_CP2, 305 .baudrate = IF_Gbps(100ULL), 306 }, 307 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 308 .subtype = IFM_100G_SR2, 309 .baudrate = IF_Gbps(100ULL), 310 }, 311 312 /**/ 313 [MLX5E_200GAUI_2_200GBASE_CR2_KR2][MLX5E_CABLE_TYPE_UNKNOWN] = { 314 .subtype = IFM_200G_KR4_PAM4, /* XXX */ 315 .baudrate = IF_Gbps(200ULL), 316 }, 317 [MLX5E_200GAUI_2_200GBASE_CR2_KR2][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 318 .subtype = IFM_200G_CR4_PAM4, /* XXX */ 319 .baudrate = IF_Gbps(200ULL), 320 }, 321 [MLX5E_200GAUI_2_200GBASE_CR2_KR2][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 322 .subtype = IFM_200G_SR4, /* XXX */ 323 .baudrate = IF_Gbps(200ULL), 324 }, 325 326 /**/ 327 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CABLE_TYPE_UNKNOWN] = { 328 .subtype = IFM_200G_KR4_PAM4, 329 .baudrate = IF_Gbps(200ULL), 330 }, 331 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 332 .subtype = IFM_200G_CR4_PAM4, 333 .baudrate = IF_Gbps(200ULL), 334 }, 335 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 336 .subtype = IFM_200G_SR4, 337 .baudrate = IF_Gbps(200ULL), 338 }, 339 340 /**/ 341 [MLX5E_400GAUI_8][MLX5E_CABLE_TYPE_UNKNOWN] = { 342 .subtype = IFM_400G_LR8, /* XXX */ 343 .baudrate = IF_Gbps(400ULL), 344 }, 345 346 /**/ 347 [MLX5E_400GAUI_4_400GBASE_CR4_KR4][MLX5E_CABLE_TYPE_UNKNOWN] = { 348 .subtype = IFM_400G_LR8, /* XXX */ 349 .baudrate = IF_Gbps(400ULL), 350 }, 351 }; 352 353 static const struct if_snd_tag_sw mlx5e_ul_snd_tag_sw = { 354 .snd_tag_query = mlx5e_ul_snd_tag_query, 355 .snd_tag_free = mlx5e_ul_snd_tag_free, 356 .type = IF_SND_TAG_TYPE_UNLIMITED 357 }; 358 359 DEBUGNET_DEFINE(mlx5_en); 360 361 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet"); 362 363 static void 364 mlx5e_update_carrier(struct mlx5e_priv *priv) 365 { 366 struct mlx5_core_dev *mdev = priv->mdev; 367 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 368 u32 eth_proto_oper; 369 int error; 370 u8 i; 371 u8 cable_type; 372 u8 port_state; 373 u8 is_er_type; 374 bool ext; 375 struct media media_entry = {}; 376 377 port_state = mlx5_query_vport_state(mdev, 378 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0); 379 380 if (port_state == VPORT_STATE_UP) { 381 priv->media_status_last |= IFM_ACTIVE; 382 } else { 383 priv->media_status_last &= ~IFM_ACTIVE; 384 priv->media_active_last = IFM_ETHER; 385 if_link_state_change(priv->ifp, LINK_STATE_DOWN); 386 return; 387 } 388 389 error = mlx5_query_port_ptys(mdev, out, sizeof(out), 390 MLX5_PTYS_EN, 1); 391 if (error) { 392 priv->media_active_last = IFM_ETHER; 393 priv->ifp->if_baudrate = 1; 394 mlx5_en_err(priv->ifp, "query port ptys failed: 0x%x\n", 395 error); 396 return; 397 } 398 399 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet); 400 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 401 eth_proto_oper); 402 403 i = ilog2(eth_proto_oper); 404 405 if (ext) { 406 error = mlx5_query_pddr_cable_type(mdev, 1, &cable_type); 407 if (error != 0) { 408 /* use fallback entry */ 409 media_entry = mlx5e_ext_mode_table[i][MLX5E_CABLE_TYPE_UNKNOWN]; 410 411 mlx5_en_err(priv->ifp, 412 "query port pddr failed: %d\n", error); 413 } else { 414 media_entry = mlx5e_ext_mode_table[i][cable_type]; 415 416 /* check if we should use fallback entry */ 417 if (media_entry.subtype == 0) 418 media_entry = mlx5e_ext_mode_table[i][MLX5E_CABLE_TYPE_UNKNOWN]; 419 } 420 } else { 421 media_entry = mlx5e_mode_table[i]; 422 } 423 424 if (media_entry.subtype == 0) { 425 mlx5_en_err(priv->ifp, 426 "Could not find operational media subtype\n"); 427 return; 428 } 429 430 switch (media_entry.subtype) { 431 case IFM_10G_ER: 432 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type); 433 if (error != 0) { 434 mlx5_en_err(priv->ifp, 435 "query port pddr failed: %d\n", error); 436 } 437 if (error != 0 || is_er_type == 0) 438 media_entry.subtype = IFM_10G_LR; 439 break; 440 case IFM_40G_LR4: 441 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type); 442 if (error != 0) { 443 mlx5_en_err(priv->ifp, 444 "query port pddr failed: %d\n", error); 445 } 446 if (error == 0 && is_er_type != 0) 447 media_entry.subtype = IFM_40G_ER4; 448 break; 449 } 450 priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX; 451 priv->ifp->if_baudrate = media_entry.baudrate; 452 453 if_link_state_change(priv->ifp, LINK_STATE_UP); 454 } 455 456 static void 457 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr) 458 { 459 struct mlx5e_priv *priv = dev->if_softc; 460 461 ifmr->ifm_status = priv->media_status_last; 462 ifmr->ifm_current = ifmr->ifm_active = priv->media_active_last | 463 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) | 464 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0); 465 466 } 467 468 static u32 469 mlx5e_find_link_mode(u32 subtype, bool ext) 470 { 471 u32 link_mode = 0; 472 473 switch (subtype) { 474 case 0: 475 goto done; 476 case IFM_10G_LR: 477 subtype = IFM_10G_ER; 478 break; 479 case IFM_40G_ER4: 480 subtype = IFM_40G_LR4; 481 break; 482 default: 483 break; 484 } 485 486 if (ext) { 487 for (unsigned i = 0; i != MLX5E_EXT_LINK_SPEEDS_NUMBER; i++) { 488 for (unsigned j = 0; j != MLX5E_CABLE_TYPE_NUMBER; j++) { 489 if (mlx5e_ext_mode_table[i][j].subtype == subtype) 490 link_mode |= MLX5E_PROT_MASK(i); 491 } 492 } 493 } else { 494 for (unsigned i = 0; i != MLX5E_LINK_SPEEDS_NUMBER; i++) { 495 if (mlx5e_mode_table[i].subtype == subtype) 496 link_mode |= MLX5E_PROT_MASK(i); 497 } 498 } 499 done: 500 return (link_mode); 501 } 502 503 static int 504 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv) 505 { 506 return (mlx5_set_port_pause_and_pfc(priv->mdev, 1, 507 priv->params.rx_pauseframe_control, 508 priv->params.tx_pauseframe_control, 509 priv->params.rx_priority_flow_control, 510 priv->params.tx_priority_flow_control)); 511 } 512 513 static int 514 mlx5e_set_port_pfc(struct mlx5e_priv *priv) 515 { 516 int error; 517 518 if (priv->gone != 0) { 519 error = -ENXIO; 520 } else if (priv->params.rx_pauseframe_control || 521 priv->params.tx_pauseframe_control) { 522 mlx5_en_err(priv->ifp, 523 "Global pauseframes must be disabled before enabling PFC.\n"); 524 error = -EINVAL; 525 } else { 526 error = mlx5e_set_port_pause_and_pfc(priv); 527 } 528 return (error); 529 } 530 531 static int 532 mlx5e_media_change(struct ifnet *dev) 533 { 534 struct mlx5e_priv *priv = dev->if_softc; 535 struct mlx5_core_dev *mdev = priv->mdev; 536 u32 eth_proto_cap; 537 u32 link_mode; 538 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 539 int was_opened; 540 int locked; 541 int error; 542 bool ext; 543 544 locked = PRIV_LOCKED(priv); 545 if (!locked) 546 PRIV_LOCK(priv); 547 548 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) { 549 error = EINVAL; 550 goto done; 551 } 552 553 error = mlx5_query_port_ptys(mdev, out, sizeof(out), 554 MLX5_PTYS_EN, 1); 555 if (error != 0) { 556 mlx5_en_err(dev, "Query port media capability failed\n"); 557 goto done; 558 } 559 560 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet); 561 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext); 562 563 /* query supported capabilities */ 564 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 565 eth_proto_capability); 566 567 /* check for autoselect */ 568 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) { 569 link_mode = eth_proto_cap; 570 if (link_mode == 0) { 571 mlx5_en_err(dev, "Port media capability is zero\n"); 572 error = EINVAL; 573 goto done; 574 } 575 } else { 576 link_mode = link_mode & eth_proto_cap; 577 if (link_mode == 0) { 578 mlx5_en_err(dev, "Not supported link mode requested\n"); 579 error = EINVAL; 580 goto done; 581 } 582 } 583 if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) { 584 /* check if PFC is enabled */ 585 if (priv->params.rx_priority_flow_control || 586 priv->params.tx_priority_flow_control) { 587 mlx5_en_err(dev, "PFC must be disabled before enabling global pauseframes.\n"); 588 error = EINVAL; 589 goto done; 590 } 591 } 592 /* update pauseframe control bits */ 593 priv->params.rx_pauseframe_control = 594 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0; 595 priv->params.tx_pauseframe_control = 596 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0; 597 598 /* check if device is opened */ 599 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 600 601 /* reconfigure the hardware */ 602 mlx5_set_port_status(mdev, MLX5_PORT_DOWN); 603 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext); 604 error = -mlx5e_set_port_pause_and_pfc(priv); 605 if (was_opened) 606 mlx5_set_port_status(mdev, MLX5_PORT_UP); 607 608 done: 609 if (!locked) 610 PRIV_UNLOCK(priv); 611 return (error); 612 } 613 614 static void 615 mlx5e_update_carrier_work(struct work_struct *work) 616 { 617 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 618 update_carrier_work); 619 620 PRIV_LOCK(priv); 621 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) 622 mlx5e_update_carrier(priv); 623 PRIV_UNLOCK(priv); 624 } 625 626 #define MLX5E_PCIE_PERF_GET_64(a,b,c,d,e,f) \ 627 s_debug->c = MLX5_GET64(mpcnt_reg, out, counter_set.f.c); 628 629 #define MLX5E_PCIE_PERF_GET_32(a,b,c,d,e,f) \ 630 s_debug->c = MLX5_GET(mpcnt_reg, out, counter_set.f.c); 631 632 static void 633 mlx5e_update_pcie_counters(struct mlx5e_priv *priv) 634 { 635 struct mlx5_core_dev *mdev = priv->mdev; 636 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug; 637 const unsigned sz = MLX5_ST_SZ_BYTES(mpcnt_reg); 638 void *out; 639 void *in; 640 int err; 641 642 /* allocate firmware request structures */ 643 in = mlx5_vzalloc(sz); 644 out = mlx5_vzalloc(sz); 645 if (in == NULL || out == NULL) 646 goto free_out; 647 648 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP); 649 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 650 if (err != 0) 651 goto free_out; 652 653 MLX5E_PCIE_PERFORMANCE_COUNTERS_64(MLX5E_PCIE_PERF_GET_64) 654 MLX5E_PCIE_PERFORMANCE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 655 656 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP); 657 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 658 if (err != 0) 659 goto free_out; 660 661 MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 662 663 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_LANE_COUNTERS_GROUP); 664 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 665 if (err != 0) 666 goto free_out; 667 668 MLX5E_PCIE_LANE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 669 670 free_out: 671 /* free firmware request structures */ 672 kvfree(in); 673 kvfree(out); 674 } 675 676 /* 677 * This function reads the physical port counters from the firmware 678 * using a pre-defined layout defined by various MLX5E_PPORT_XXX() 679 * macros. The output is converted from big-endian 64-bit values into 680 * host endian ones and stored in the "priv->stats.pport" structure. 681 */ 682 static void 683 mlx5e_update_pport_counters(struct mlx5e_priv *priv) 684 { 685 struct mlx5_core_dev *mdev = priv->mdev; 686 struct mlx5e_pport_stats *s = &priv->stats.pport; 687 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug; 688 u32 *in; 689 u32 *out; 690 const u64 *ptr; 691 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 692 unsigned x; 693 unsigned y; 694 unsigned z; 695 696 /* allocate firmware request structures */ 697 in = mlx5_vzalloc(sz); 698 out = mlx5_vzalloc(sz); 699 if (in == NULL || out == NULL) 700 goto free_out; 701 702 /* 703 * Get pointer to the 64-bit counter set which is located at a 704 * fixed offset in the output firmware request structure: 705 */ 706 ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set); 707 708 MLX5_SET(ppcnt_reg, in, local_port, 1); 709 710 /* read IEEE802_3 counter group using predefined counter layout */ 711 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP); 712 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 713 for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM; 714 x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++) 715 s->arg[y] = be64toh(ptr[x]); 716 717 /* read RFC2819 counter group using predefined counter layout */ 718 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP); 719 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 720 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++) 721 s->arg[y] = be64toh(ptr[x]); 722 723 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM + 724 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++) 725 s_debug->arg[y] = be64toh(ptr[x]); 726 727 /* read RFC2863 counter group using predefined counter layout */ 728 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP); 729 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 730 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++) 731 s_debug->arg[y] = be64toh(ptr[x]); 732 733 /* read physical layer stats counter group using predefined counter layout */ 734 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP); 735 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 736 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++) 737 s_debug->arg[y] = be64toh(ptr[x]); 738 739 /* read Extended Ethernet counter group using predefined counter layout */ 740 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP); 741 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 742 for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++) 743 s_debug->arg[y] = be64toh(ptr[x]); 744 745 /* read Extended Statistical Group */ 746 if (MLX5_CAP_GEN(mdev, pcam_reg) && 747 MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) && 748 MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) { 749 /* read Extended Statistical counter group using predefined counter layout */ 750 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP); 751 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 752 753 for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++) 754 s_debug->arg[y] = be64toh(ptr[x]); 755 } 756 757 /* read PCIE counters */ 758 mlx5e_update_pcie_counters(priv); 759 760 /* read per-priority counters */ 761 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP); 762 763 /* iterate all the priorities */ 764 for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) { 765 MLX5_SET(ppcnt_reg, in, prio_tc, z); 766 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 767 768 /* read per priority stats counter group using predefined counter layout */ 769 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM / 770 MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++) 771 s->arg[y] = be64toh(ptr[x]); 772 } 773 774 free_out: 775 /* free firmware request structures */ 776 kvfree(in); 777 kvfree(out); 778 } 779 780 static void 781 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv) 782 { 783 u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {}; 784 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {}; 785 786 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard)) 787 return; 788 789 MLX5_SET(query_vnic_env_in, in, opcode, 790 MLX5_CMD_OP_QUERY_VNIC_ENV); 791 MLX5_SET(query_vnic_env_in, in, op_mod, 0); 792 MLX5_SET(query_vnic_env_in, in, other_vport, 0); 793 794 if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0) 795 return; 796 797 priv->stats.vport.rx_steer_missed_packets = 798 MLX5_GET64(query_vnic_env_out, out, 799 vport_env.nic_receive_steering_discard); 800 } 801 802 /* 803 * This function is called regularly to collect all statistics 804 * counters from the firmware. The values can be viewed through the 805 * sysctl interface. Execution is serialized using the priv's global 806 * configuration lock. 807 */ 808 static void 809 mlx5e_update_stats_locked(struct mlx5e_priv *priv) 810 { 811 struct mlx5_core_dev *mdev = priv->mdev; 812 struct mlx5e_vport_stats *s = &priv->stats.vport; 813 struct mlx5e_sq_stats *sq_stats; 814 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)]; 815 u32 *out; 816 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out); 817 u64 tso_packets = 0; 818 u64 tso_bytes = 0; 819 u64 tx_queue_dropped = 0; 820 u64 tx_defragged = 0; 821 u64 tx_offload_none = 0; 822 u64 lro_packets = 0; 823 u64 lro_bytes = 0; 824 u64 sw_lro_queued = 0; 825 u64 sw_lro_flushed = 0; 826 u64 rx_csum_none = 0; 827 u64 rx_wqe_err = 0; 828 u64 rx_packets = 0; 829 u64 rx_bytes = 0; 830 u64 rx_decrypted_error = 0; 831 u64 rx_decrypted_ok = 0; 832 u32 rx_out_of_buffer = 0; 833 int error; 834 int i; 835 int j; 836 837 out = mlx5_vzalloc(outlen); 838 if (out == NULL) 839 goto free_out; 840 841 /* Collect firts the SW counters and then HW for consistency */ 842 for (i = 0; i < priv->params.num_channels; i++) { 843 struct mlx5e_channel *pch = priv->channel + i; 844 struct mlx5e_rq *rq = &pch->rq; 845 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats; 846 847 /* collect stats from LRO */ 848 rq_stats->sw_lro_queued = rq->lro.lro_queued; 849 rq_stats->sw_lro_flushed = rq->lro.lro_flushed; 850 sw_lro_queued += rq_stats->sw_lro_queued; 851 sw_lro_flushed += rq_stats->sw_lro_flushed; 852 lro_packets += rq_stats->lro_packets; 853 lro_bytes += rq_stats->lro_bytes; 854 rx_csum_none += rq_stats->csum_none; 855 rx_wqe_err += rq_stats->wqe_err; 856 rx_packets += rq_stats->packets; 857 rx_bytes += rq_stats->bytes; 858 rx_decrypted_error += rq_stats->decrypted_error_packets; 859 rx_decrypted_ok += rq_stats->decrypted_ok_packets; 860 861 for (j = 0; j < priv->num_tc; j++) { 862 sq_stats = &pch->sq[j].stats; 863 864 tso_packets += sq_stats->tso_packets; 865 tso_bytes += sq_stats->tso_bytes; 866 tx_queue_dropped += sq_stats->dropped; 867 tx_queue_dropped += sq_stats->enobuf; 868 tx_defragged += sq_stats->defragged; 869 tx_offload_none += sq_stats->csum_offload_none; 870 } 871 } 872 873 #ifdef RATELIMIT 874 /* Collect statistics from all rate-limit queues */ 875 for (j = 0; j < priv->rl.param.tx_worker_threads_def; j++) { 876 struct mlx5e_rl_worker *rlw = priv->rl.workers + j; 877 878 for (i = 0; i < priv->rl.param.tx_channels_per_worker_def; i++) { 879 struct mlx5e_rl_channel *channel = rlw->channels + i; 880 struct mlx5e_sq *sq = channel->sq; 881 882 if (sq == NULL) 883 continue; 884 885 sq_stats = &sq->stats; 886 887 tso_packets += sq_stats->tso_packets; 888 tso_bytes += sq_stats->tso_bytes; 889 tx_queue_dropped += sq_stats->dropped; 890 tx_queue_dropped += sq_stats->enobuf; 891 tx_defragged += sq_stats->defragged; 892 tx_offload_none += sq_stats->csum_offload_none; 893 } 894 } 895 #endif 896 897 /* update counters */ 898 s->tso_packets = tso_packets; 899 s->tso_bytes = tso_bytes; 900 s->tx_queue_dropped = tx_queue_dropped; 901 s->tx_defragged = tx_defragged; 902 s->lro_packets = lro_packets; 903 s->lro_bytes = lro_bytes; 904 s->sw_lro_queued = sw_lro_queued; 905 s->sw_lro_flushed = sw_lro_flushed; 906 s->rx_csum_none = rx_csum_none; 907 s->rx_wqe_err = rx_wqe_err; 908 s->rx_packets = rx_packets; 909 s->rx_bytes = rx_bytes; 910 s->rx_decrypted_error_packets = rx_decrypted_error; 911 s->rx_decrypted_ok_packets = rx_decrypted_ok; 912 913 mlx5e_grp_vnic_env_update_stats(priv); 914 915 /* HW counters */ 916 memset(in, 0, sizeof(in)); 917 918 MLX5_SET(query_vport_counter_in, in, opcode, 919 MLX5_CMD_OP_QUERY_VPORT_COUNTER); 920 MLX5_SET(query_vport_counter_in, in, op_mod, 0); 921 MLX5_SET(query_vport_counter_in, in, other_vport, 0); 922 923 memset(out, 0, outlen); 924 925 /* get number of out-of-buffer drops first */ 926 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 && 927 mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id, 928 &rx_out_of_buffer) == 0) { 929 s->rx_out_of_buffer = rx_out_of_buffer; 930 } 931 932 /* get port statistics */ 933 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) { 934 #define MLX5_GET_CTR(out, x) \ 935 MLX5_GET64(query_vport_counter_out, out, x) 936 937 s->rx_error_packets = 938 MLX5_GET_CTR(out, received_errors.packets); 939 s->rx_error_bytes = 940 MLX5_GET_CTR(out, received_errors.octets); 941 s->tx_error_packets = 942 MLX5_GET_CTR(out, transmit_errors.packets); 943 s->tx_error_bytes = 944 MLX5_GET_CTR(out, transmit_errors.octets); 945 946 s->rx_unicast_packets = 947 MLX5_GET_CTR(out, received_eth_unicast.packets); 948 s->rx_unicast_bytes = 949 MLX5_GET_CTR(out, received_eth_unicast.octets); 950 s->tx_unicast_packets = 951 MLX5_GET_CTR(out, transmitted_eth_unicast.packets); 952 s->tx_unicast_bytes = 953 MLX5_GET_CTR(out, transmitted_eth_unicast.octets); 954 955 s->rx_multicast_packets = 956 MLX5_GET_CTR(out, received_eth_multicast.packets); 957 s->rx_multicast_bytes = 958 MLX5_GET_CTR(out, received_eth_multicast.octets); 959 s->tx_multicast_packets = 960 MLX5_GET_CTR(out, transmitted_eth_multicast.packets); 961 s->tx_multicast_bytes = 962 MLX5_GET_CTR(out, transmitted_eth_multicast.octets); 963 964 s->rx_broadcast_packets = 965 MLX5_GET_CTR(out, received_eth_broadcast.packets); 966 s->rx_broadcast_bytes = 967 MLX5_GET_CTR(out, received_eth_broadcast.octets); 968 s->tx_broadcast_packets = 969 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets); 970 s->tx_broadcast_bytes = 971 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets); 972 973 s->tx_packets = s->tx_unicast_packets + 974 s->tx_multicast_packets + s->tx_broadcast_packets; 975 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes + 976 s->tx_broadcast_bytes; 977 978 /* Update calculated offload counters */ 979 s->tx_csum_offload = s->tx_packets - tx_offload_none; 980 s->rx_csum_good = s->rx_packets - s->rx_csum_none; 981 } 982 983 /* Get physical port counters */ 984 mlx5e_update_pport_counters(priv); 985 986 s->tx_jumbo_packets = 987 priv->stats.port_stats_debug.tx_stat_p1519to2047octets + 988 priv->stats.port_stats_debug.tx_stat_p2048to4095octets + 989 priv->stats.port_stats_debug.tx_stat_p4096to8191octets + 990 priv->stats.port_stats_debug.tx_stat_p8192to10239octets; 991 992 free_out: 993 kvfree(out); 994 995 /* Update diagnostics, if any */ 996 if (priv->params_ethtool.diag_pci_enable || 997 priv->params_ethtool.diag_general_enable) { 998 error = mlx5_core_get_diagnostics_full(mdev, 999 priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL, 1000 priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL); 1001 if (error != 0) 1002 mlx5_en_err(priv->ifp, 1003 "Failed reading diagnostics: %d\n", error); 1004 } 1005 1006 /* Update FEC, if any */ 1007 error = mlx5e_fec_update(priv); 1008 if (error != 0 && error != EOPNOTSUPP) { 1009 mlx5_en_err(priv->ifp, 1010 "Updating FEC failed: %d\n", error); 1011 } 1012 1013 /* Update temperature, if any */ 1014 if (priv->params_ethtool.hw_num_temp != 0) { 1015 error = mlx5e_hw_temperature_update(priv); 1016 if (error != 0 && error != EOPNOTSUPP) { 1017 mlx5_en_err(priv->ifp, 1018 "Updating temperature failed: %d\n", error); 1019 } 1020 } 1021 } 1022 1023 static void 1024 mlx5e_update_stats_work(struct work_struct *work) 1025 { 1026 struct mlx5e_priv *priv; 1027 1028 priv = container_of(work, struct mlx5e_priv, update_stats_work); 1029 PRIV_LOCK(priv); 1030 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 && 1031 !test_bit(MLX5_INTERFACE_STATE_TEARDOWN, &priv->mdev->intf_state)) 1032 mlx5e_update_stats_locked(priv); 1033 PRIV_UNLOCK(priv); 1034 } 1035 1036 static void 1037 mlx5e_update_stats(void *arg) 1038 { 1039 struct mlx5e_priv *priv = arg; 1040 1041 queue_work(priv->wq, &priv->update_stats_work); 1042 1043 callout_reset(&priv->watchdog, hz / 4, &mlx5e_update_stats, priv); 1044 } 1045 1046 static void 1047 mlx5e_async_event_sub(struct mlx5e_priv *priv, 1048 enum mlx5_dev_event event) 1049 { 1050 switch (event) { 1051 case MLX5_DEV_EVENT_PORT_UP: 1052 case MLX5_DEV_EVENT_PORT_DOWN: 1053 queue_work(priv->wq, &priv->update_carrier_work); 1054 break; 1055 1056 default: 1057 break; 1058 } 1059 } 1060 1061 static void 1062 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv, 1063 enum mlx5_dev_event event, unsigned long param) 1064 { 1065 struct mlx5e_priv *priv = vpriv; 1066 1067 mtx_lock(&priv->async_events_mtx); 1068 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state)) 1069 mlx5e_async_event_sub(priv, event); 1070 mtx_unlock(&priv->async_events_mtx); 1071 } 1072 1073 static void 1074 mlx5e_enable_async_events(struct mlx5e_priv *priv) 1075 { 1076 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 1077 } 1078 1079 static void 1080 mlx5e_disable_async_events(struct mlx5e_priv *priv) 1081 { 1082 mtx_lock(&priv->async_events_mtx); 1083 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 1084 mtx_unlock(&priv->async_events_mtx); 1085 } 1086 1087 static void mlx5e_calibration_callout(void *arg); 1088 static int mlx5e_calibration_duration = 20; 1089 static int mlx5e_fast_calibration = 1; 1090 static int mlx5e_normal_calibration = 30; 1091 1092 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 1093 "MLX5 timestamp calibration parameters"); 1094 1095 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN, 1096 &mlx5e_calibration_duration, 0, 1097 "Duration of initial calibration"); 1098 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN, 1099 &mlx5e_fast_calibration, 0, 1100 "Recalibration interval during initial calibration"); 1101 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN, 1102 &mlx5e_normal_calibration, 0, 1103 "Recalibration interval during normal operations"); 1104 1105 /* 1106 * Ignites the calibration process. 1107 */ 1108 static void 1109 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv) 1110 { 1111 1112 if (priv->clbr_done == 0) 1113 mlx5e_calibration_callout(priv); 1114 else 1115 callout_reset_sbt_curcpu(&priv->tstmp_clbr, (priv->clbr_done < 1116 mlx5e_calibration_duration ? mlx5e_fast_calibration : 1117 mlx5e_normal_calibration) * SBT_1S, 0, 1118 mlx5e_calibration_callout, priv, C_DIRECT_EXEC); 1119 } 1120 1121 static uint64_t 1122 mlx5e_timespec2usec(const struct timespec *ts) 1123 { 1124 1125 return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec); 1126 } 1127 1128 static uint64_t 1129 mlx5e_hw_clock(struct mlx5e_priv *priv) 1130 { 1131 struct mlx5_init_seg *iseg; 1132 uint32_t hw_h, hw_h1, hw_l; 1133 1134 iseg = priv->mdev->iseg; 1135 do { 1136 hw_h = ioread32be(&iseg->internal_timer_h); 1137 hw_l = ioread32be(&iseg->internal_timer_l); 1138 hw_h1 = ioread32be(&iseg->internal_timer_h); 1139 } while (hw_h1 != hw_h); 1140 return (((uint64_t)hw_h << 32) | hw_l); 1141 } 1142 1143 /* 1144 * The calibration callout, it runs either in the context of the 1145 * thread which enables calibration, or in callout. It takes the 1146 * snapshot of system and adapter clocks, then advances the pointers to 1147 * the calibration point to allow rx path to read the consistent data 1148 * lockless. 1149 */ 1150 static void 1151 mlx5e_calibration_callout(void *arg) 1152 { 1153 struct mlx5e_priv *priv; 1154 struct mlx5e_clbr_point *next, *curr; 1155 struct timespec ts; 1156 int clbr_curr_next; 1157 1158 priv = arg; 1159 curr = &priv->clbr_points[priv->clbr_curr]; 1160 clbr_curr_next = priv->clbr_curr + 1; 1161 if (clbr_curr_next >= nitems(priv->clbr_points)) 1162 clbr_curr_next = 0; 1163 next = &priv->clbr_points[clbr_curr_next]; 1164 1165 next->base_prev = curr->base_curr; 1166 next->clbr_hw_prev = curr->clbr_hw_curr; 1167 1168 next->clbr_hw_curr = mlx5e_hw_clock(priv); 1169 if (((next->clbr_hw_curr - curr->clbr_hw_curr) >> MLX5E_TSTMP_PREC) == 1170 0) { 1171 if (priv->clbr_done != 0) { 1172 mlx5_en_err(priv->ifp, 1173 "HW failed tstmp frozen %#jx %#jx, disabling\n", 1174 next->clbr_hw_curr, curr->clbr_hw_prev); 1175 priv->clbr_done = 0; 1176 } 1177 atomic_store_rel_int(&curr->clbr_gen, 0); 1178 return; 1179 } 1180 1181 nanouptime(&ts); 1182 next->base_curr = mlx5e_timespec2usec(&ts); 1183 1184 curr->clbr_gen = 0; 1185 atomic_thread_fence_rel(); 1186 priv->clbr_curr = clbr_curr_next; 1187 atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen)); 1188 1189 if (priv->clbr_done < mlx5e_calibration_duration) 1190 priv->clbr_done++; 1191 mlx5e_reset_calibration_callout(priv); 1192 } 1193 1194 static const char *mlx5e_rq_stats_desc[] = { 1195 MLX5E_RQ_STATS(MLX5E_STATS_DESC) 1196 }; 1197 1198 static int 1199 mlx5e_create_rq(struct mlx5e_channel *c, 1200 struct mlx5e_rq_param *param, 1201 struct mlx5e_rq *rq) 1202 { 1203 struct mlx5e_priv *priv = c->priv; 1204 struct mlx5_core_dev *mdev = priv->mdev; 1205 char buffer[16]; 1206 void *rqc = param->rqc; 1207 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); 1208 int wq_sz; 1209 int err; 1210 int i; 1211 u32 nsegs, wqe_sz; 1212 1213 err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs); 1214 if (err != 0) 1215 goto done; 1216 1217 /* Create DMA descriptor TAG */ 1218 if ((err = -bus_dma_tag_create( 1219 bus_get_dma_tag(mdev->pdev->dev.bsddev), 1220 1, /* any alignment */ 1221 0, /* no boundary */ 1222 BUS_SPACE_MAXADDR, /* lowaddr */ 1223 BUS_SPACE_MAXADDR, /* highaddr */ 1224 NULL, NULL, /* filter, filterarg */ 1225 nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */ 1226 nsegs, /* nsegments */ 1227 nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */ 1228 0, /* flags */ 1229 NULL, NULL, /* lockfunc, lockfuncarg */ 1230 &rq->dma_tag))) 1231 goto done; 1232 1233 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, 1234 &rq->wq_ctrl); 1235 if (err) 1236 goto err_free_dma_tag; 1237 1238 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR]; 1239 1240 err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs); 1241 if (err != 0) 1242 goto err_rq_wq_destroy; 1243 1244 wq_sz = mlx5_wq_ll_get_size(&rq->wq); 1245 1246 err = -tcp_lro_init_args(&rq->lro, priv->ifp, TCP_LRO_ENTRIES, wq_sz); 1247 if (err) 1248 goto err_rq_wq_destroy; 1249 1250 rq->mbuf = malloc_domainset(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, 1251 mlx5_dev_domainset(mdev), M_WAITOK | M_ZERO); 1252 for (i = 0; i != wq_sz; i++) { 1253 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i); 1254 int j; 1255 1256 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map); 1257 if (err != 0) { 1258 while (i--) 1259 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 1260 goto err_rq_mbuf_free; 1261 } 1262 1263 /* set value for constant fields */ 1264 for (j = 0; j < rq->nsegs; j++) 1265 wqe->data[j].lkey = cpu_to_be32(priv->mr.key); 1266 } 1267 1268 INIT_WORK(&rq->dim.work, mlx5e_dim_work); 1269 if (priv->params.rx_cq_moderation_mode < 2) { 1270 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 1271 } else { 1272 void *cqc = container_of(param, 1273 struct mlx5e_channel_param, rq)->rx_cq.cqc; 1274 1275 switch (MLX5_GET(cqc, cqc, cq_period_mode)) { 1276 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE: 1277 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; 1278 break; 1279 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE: 1280 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE; 1281 break; 1282 default: 1283 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 1284 break; 1285 } 1286 } 1287 1288 rq->ifp = priv->ifp; 1289 rq->channel = c; 1290 rq->ix = c->ix; 1291 1292 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix); 1293 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 1294 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM, 1295 rq->stats.arg); 1296 return (0); 1297 1298 err_rq_mbuf_free: 1299 free(rq->mbuf, M_MLX5EN); 1300 tcp_lro_free(&rq->lro); 1301 err_rq_wq_destroy: 1302 mlx5_wq_destroy(&rq->wq_ctrl); 1303 err_free_dma_tag: 1304 bus_dma_tag_destroy(rq->dma_tag); 1305 done: 1306 return (err); 1307 } 1308 1309 static void 1310 mlx5e_destroy_rq(struct mlx5e_rq *rq) 1311 { 1312 int wq_sz; 1313 int i; 1314 1315 /* destroy all sysctl nodes */ 1316 sysctl_ctx_free(&rq->stats.ctx); 1317 1318 /* free leftover LRO packets, if any */ 1319 tcp_lro_free(&rq->lro); 1320 1321 wq_sz = mlx5_wq_ll_get_size(&rq->wq); 1322 for (i = 0; i != wq_sz; i++) { 1323 if (rq->mbuf[i].mbuf != NULL) { 1324 bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map); 1325 m_freem(rq->mbuf[i].mbuf); 1326 } 1327 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 1328 } 1329 free(rq->mbuf, M_MLX5EN); 1330 mlx5_wq_destroy(&rq->wq_ctrl); 1331 bus_dma_tag_destroy(rq->dma_tag); 1332 } 1333 1334 static int 1335 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param) 1336 { 1337 struct mlx5e_channel *c = rq->channel; 1338 struct mlx5e_priv *priv = c->priv; 1339 struct mlx5_core_dev *mdev = priv->mdev; 1340 void *in; 1341 void *rqc; 1342 void *wq; 1343 int inlen; 1344 int err; 1345 u8 ts_format; 1346 1347 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 1348 sizeof(u64) * rq->wq_ctrl.buf.npages; 1349 in = mlx5_vzalloc(inlen); 1350 if (in == NULL) 1351 return (-ENOMEM); 1352 1353 ts_format = mlx5_get_rq_default_ts(mdev); 1354 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1355 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1356 1357 memcpy(rqc, param->rqc, sizeof(param->rqc)); 1358 1359 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1360 MLX5_SET(rqc, rqc, ts_format, ts_format); 1361 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1362 if (priv->counter_set_id >= 0) 1363 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id); 1364 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - 1365 PAGE_SHIFT); 1366 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); 1367 1368 mlx5_fill_page_array(&rq->wq_ctrl.buf, 1369 (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 1370 1371 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); 1372 1373 kvfree(in); 1374 1375 return (err); 1376 } 1377 1378 static int 1379 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state) 1380 { 1381 struct mlx5e_channel *c = rq->channel; 1382 struct mlx5e_priv *priv = c->priv; 1383 struct mlx5_core_dev *mdev = priv->mdev; 1384 1385 void *in; 1386 void *rqc; 1387 int inlen; 1388 int err; 1389 1390 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 1391 in = mlx5_vzalloc(inlen); 1392 if (in == NULL) 1393 return (-ENOMEM); 1394 1395 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1396 1397 MLX5_SET(modify_rq_in, in, rqn, rq->rqn); 1398 MLX5_SET(modify_rq_in, in, rq_state, curr_state); 1399 MLX5_SET(rqc, rqc, state, next_state); 1400 1401 err = mlx5_core_modify_rq(mdev, in, inlen); 1402 1403 kvfree(in); 1404 1405 return (err); 1406 } 1407 1408 static void 1409 mlx5e_disable_rq(struct mlx5e_rq *rq) 1410 { 1411 struct mlx5e_channel *c = rq->channel; 1412 struct mlx5e_priv *priv = c->priv; 1413 struct mlx5_core_dev *mdev = priv->mdev; 1414 1415 mlx5_core_destroy_rq(mdev, rq->rqn); 1416 } 1417 1418 static int 1419 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq) 1420 { 1421 struct mlx5e_channel *c = rq->channel; 1422 struct mlx5e_priv *priv = c->priv; 1423 struct mlx5_wq_ll *wq = &rq->wq; 1424 int i; 1425 1426 for (i = 0; i < 1000; i++) { 1427 if (wq->cur_sz >= priv->params.min_rx_wqes) 1428 return (0); 1429 1430 msleep(4); 1431 } 1432 return (-ETIMEDOUT); 1433 } 1434 1435 static int 1436 mlx5e_open_rq(struct mlx5e_channel *c, 1437 struct mlx5e_rq_param *param, 1438 struct mlx5e_rq *rq) 1439 { 1440 int err; 1441 1442 err = mlx5e_create_rq(c, param, rq); 1443 if (err) 1444 return (err); 1445 1446 /* set CQN in RQ parameters */ 1447 MLX5_SET(rqc, param->rqc, cqn, c->rq.cq.mcq.cqn); 1448 1449 err = mlx5e_enable_rq(rq, param); 1450 if (err) 1451 goto err_destroy_rq; 1452 1453 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 1454 if (err) 1455 goto err_disable_rq; 1456 1457 c->rq.enabled = 1; 1458 1459 return (0); 1460 1461 err_disable_rq: 1462 mlx5e_disable_rq(rq); 1463 err_destroy_rq: 1464 mlx5e_destroy_rq(rq); 1465 1466 return (err); 1467 } 1468 1469 static void 1470 mlx5e_close_rq(struct mlx5e_rq *rq) 1471 { 1472 mtx_lock(&rq->mtx); 1473 rq->enabled = 0; 1474 callout_stop(&rq->watchdog); 1475 mtx_unlock(&rq->mtx); 1476 1477 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 1478 } 1479 1480 static void 1481 mlx5e_close_rq_wait(struct mlx5e_rq *rq) 1482 { 1483 1484 mlx5e_disable_rq(rq); 1485 mlx5e_close_cq(&rq->cq); 1486 cancel_work_sync(&rq->dim.work); 1487 mlx5e_destroy_rq(rq); 1488 } 1489 1490 /* 1491 * What is a drop RQ and why is it needed? 1492 * 1493 * The RSS indirection table, also called the RQT, selects the 1494 * destination RQ based on the receive queue number, RQN. The RQT is 1495 * frequently referred to by flow steering rules to distribute traffic 1496 * among multiple RQs. The problem is that the RQs cannot be destroyed 1497 * before the RQT referring them is destroyed too. Further, TLS RX 1498 * rules may still be referring to the RQT even if the link went 1499 * down. Because there is no magic RQN for dropping packets, we create 1500 * a dummy RQ, also called drop RQ, which sole purpose is to drop all 1501 * received packets. When the link goes down this RQN is filled in all 1502 * RQT entries, of the main RQT, so the real RQs which are about to be 1503 * destroyed can be released and the TLS RX rules can be sustained. 1504 */ 1505 static void 1506 mlx5e_open_drop_rq_comp(struct mlx5_core_cq *mcq __unused, struct mlx5_eqe *eqe __unused) 1507 { 1508 } 1509 1510 static int 1511 mlx5e_open_drop_rq(struct mlx5e_priv *priv, 1512 struct mlx5e_rq *drop_rq) 1513 { 1514 struct mlx5e_cq_param param_cq = {}; 1515 struct mlx5e_rq_param param_rq = {}; 1516 void *rqc_wq = MLX5_ADDR_OF(rqc, param_rq.rqc, wq); 1517 int err; 1518 1519 /* set channel pointer */ 1520 drop_rq->channel = priv->channel; 1521 1522 /* set basic CQ parameters needed */ 1523 MLX5_SET(cqc, param_cq.cqc, log_cq_size, 0); 1524 MLX5_SET(cqc, param_cq.cqc, uar_page, priv->mdev->priv.uar->index); 1525 1526 /* open receive completion queue */ 1527 err = mlx5e_open_cq(priv, ¶m_cq, &drop_rq->cq, 1528 &mlx5e_open_drop_rq_comp, 0); 1529 if (err) 1530 goto err_done; 1531 1532 /* set basic WQ parameters needed */ 1533 MLX5_SET(wq, rqc_wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); 1534 MLX5_SET(wq, rqc_wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1535 MLX5_SET(wq, rqc_wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) + sizeof(struct mlx5_wqe_data_seg))); 1536 MLX5_SET(wq, rqc_wq, log_wq_sz, 0); 1537 MLX5_SET(wq, rqc_wq, pd, priv->pdn); 1538 1539 param_rq.wq.linear = 1; 1540 1541 err = mlx5_wq_ll_create(priv->mdev, ¶m_rq.wq, rqc_wq, &drop_rq->wq, 1542 &drop_rq->wq_ctrl); 1543 if (err) 1544 goto err_close_cq; 1545 1546 /* set CQN in RQ parameters */ 1547 MLX5_SET(rqc, param_rq.rqc, cqn, drop_rq->cq.mcq.cqn); 1548 1549 err = mlx5e_enable_rq(drop_rq, ¶m_rq); 1550 if (err) 1551 goto err_wq_destroy; 1552 1553 err = mlx5e_modify_rq(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 1554 if (err) 1555 goto err_disable_rq; 1556 1557 return (err); 1558 1559 err_disable_rq: 1560 mlx5e_disable_rq(drop_rq); 1561 err_wq_destroy: 1562 mlx5_wq_destroy(&drop_rq->wq_ctrl); 1563 err_close_cq: 1564 mlx5e_close_cq(&drop_rq->cq); 1565 err_done: 1566 return (err); 1567 } 1568 1569 static void 1570 mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq) 1571 { 1572 mlx5e_modify_rq(drop_rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 1573 mlx5e_disable_rq(drop_rq); 1574 mlx5_wq_destroy(&drop_rq->wq_ctrl); 1575 mlx5e_close_cq(&drop_rq->cq); 1576 } 1577 1578 void 1579 mlx5e_free_sq_db(struct mlx5e_sq *sq) 1580 { 1581 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1582 int x; 1583 1584 for (x = 0; x != wq_sz; x++) { 1585 if (unlikely(sq->mbuf[x].p_refcount != NULL)) { 1586 atomic_add_int(sq->mbuf[x].p_refcount, -1); 1587 sq->mbuf[x].p_refcount = NULL; 1588 } 1589 if (sq->mbuf[x].mbuf != NULL) { 1590 bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map); 1591 m_freem(sq->mbuf[x].mbuf); 1592 } 1593 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 1594 } 1595 free(sq->mbuf, M_MLX5EN); 1596 } 1597 1598 int 1599 mlx5e_alloc_sq_db(struct mlx5e_sq *sq) 1600 { 1601 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1602 int err; 1603 int x; 1604 1605 sq->mbuf = malloc_domainset(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, 1606 mlx5_dev_domainset(sq->priv->mdev), M_WAITOK | M_ZERO); 1607 1608 /* Create DMA descriptor MAPs */ 1609 for (x = 0; x != wq_sz; x++) { 1610 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map); 1611 if (err != 0) { 1612 while (x--) 1613 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 1614 free(sq->mbuf, M_MLX5EN); 1615 return (err); 1616 } 1617 } 1618 return (0); 1619 } 1620 1621 static const char *mlx5e_sq_stats_desc[] = { 1622 MLX5E_SQ_STATS(MLX5E_STATS_DESC) 1623 }; 1624 1625 void 1626 mlx5e_update_sq_inline(struct mlx5e_sq *sq) 1627 { 1628 sq->max_inline = sq->priv->params.tx_max_inline; 1629 sq->min_inline_mode = sq->priv->params.tx_min_inline_mode; 1630 1631 /* 1632 * Check if trust state is DSCP or if inline mode is NONE which 1633 * indicates CX-5 or newer hardware. 1634 */ 1635 if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP || 1636 sq->min_inline_mode == MLX5_INLINE_MODE_NONE) { 1637 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert)) 1638 sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN; 1639 else 1640 sq->min_insert_caps = MLX5E_INSERT_NON_VLAN; 1641 } else { 1642 sq->min_insert_caps = 0; 1643 } 1644 } 1645 1646 static void 1647 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c) 1648 { 1649 int i; 1650 1651 for (i = 0; i != priv->num_tc; i++) { 1652 mtx_lock(&c->sq[i].lock); 1653 mlx5e_update_sq_inline(&c->sq[i]); 1654 mtx_unlock(&c->sq[i].lock); 1655 } 1656 } 1657 1658 void 1659 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv) 1660 { 1661 int i; 1662 1663 /* check if channels are closed */ 1664 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 1665 return; 1666 1667 for (i = 0; i < priv->params.num_channels; i++) 1668 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]); 1669 } 1670 1671 static int 1672 mlx5e_create_sq(struct mlx5e_channel *c, 1673 int tc, 1674 struct mlx5e_sq_param *param, 1675 struct mlx5e_sq *sq) 1676 { 1677 struct mlx5e_priv *priv = c->priv; 1678 struct mlx5_core_dev *mdev = priv->mdev; 1679 char buffer[16]; 1680 void *sqc = param->sqc; 1681 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq); 1682 int err; 1683 1684 /* Create DMA descriptor TAG */ 1685 if ((err = -bus_dma_tag_create( 1686 bus_get_dma_tag(mdev->pdev->dev.bsddev), 1687 1, /* any alignment */ 1688 0, /* no boundary */ 1689 BUS_SPACE_MAXADDR, /* lowaddr */ 1690 BUS_SPACE_MAXADDR, /* highaddr */ 1691 NULL, NULL, /* filter, filterarg */ 1692 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */ 1693 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */ 1694 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */ 1695 0, /* flags */ 1696 NULL, NULL, /* lockfunc, lockfuncarg */ 1697 &sq->dma_tag))) 1698 goto done; 1699 1700 sq->mkey_be = cpu_to_be32(priv->mr.key); 1701 sq->ifp = priv->ifp; 1702 sq->priv = priv; 1703 sq->tc = tc; 1704 1705 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, 1706 &sq->wq_ctrl); 1707 if (err) 1708 goto err_free_dma_tag; 1709 1710 sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; 1711 1712 err = mlx5e_alloc_sq_db(sq); 1713 if (err) 1714 goto err_sq_wq_destroy; 1715 1716 mlx5e_update_sq_inline(sq); 1717 1718 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc); 1719 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 1720 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM, 1721 sq->stats.arg); 1722 1723 return (0); 1724 1725 err_sq_wq_destroy: 1726 mlx5_wq_destroy(&sq->wq_ctrl); 1727 1728 err_free_dma_tag: 1729 bus_dma_tag_destroy(sq->dma_tag); 1730 done: 1731 return (err); 1732 } 1733 1734 static void 1735 mlx5e_destroy_sq(struct mlx5e_sq *sq) 1736 { 1737 /* destroy all sysctl nodes */ 1738 sysctl_ctx_free(&sq->stats.ctx); 1739 1740 mlx5e_free_sq_db(sq); 1741 mlx5_wq_destroy(&sq->wq_ctrl); 1742 bus_dma_tag_destroy(sq->dma_tag); 1743 } 1744 1745 int 1746 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param, 1747 const struct mlx5_sq_bfreg *bfreg, int tis_num) 1748 { 1749 void *in; 1750 void *sqc; 1751 void *wq; 1752 int inlen; 1753 int err; 1754 u8 ts_format; 1755 1756 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1757 sizeof(u64) * sq->wq_ctrl.buf.npages; 1758 in = mlx5_vzalloc(inlen); 1759 if (in == NULL) 1760 return (-ENOMEM); 1761 1762 sq->uar_map = bfreg->map; 1763 1764 ts_format = mlx5_get_sq_default_ts(sq->priv->mdev); 1765 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1766 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1767 1768 memcpy(sqc, param->sqc, sizeof(param->sqc)); 1769 1770 MLX5_SET(sqc, sqc, tis_num_0, tis_num); 1771 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn); 1772 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1773 MLX5_SET(sqc, sqc, ts_format, ts_format); 1774 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1775 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1776 MLX5_SET(sqc, sqc, allow_swp, 1); 1777 1778 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1779 MLX5_SET(wq, wq, uar_page, bfreg->index); 1780 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift - 1781 PAGE_SHIFT); 1782 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma); 1783 1784 mlx5_fill_page_array(&sq->wq_ctrl.buf, 1785 (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 1786 1787 err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn); 1788 1789 kvfree(in); 1790 1791 return (err); 1792 } 1793 1794 int 1795 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state) 1796 { 1797 void *in; 1798 void *sqc; 1799 int inlen; 1800 int err; 1801 1802 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 1803 in = mlx5_vzalloc(inlen); 1804 if (in == NULL) 1805 return (-ENOMEM); 1806 1807 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1808 1809 MLX5_SET(modify_sq_in, in, sqn, sq->sqn); 1810 MLX5_SET(modify_sq_in, in, sq_state, curr_state); 1811 MLX5_SET(sqc, sqc, state, next_state); 1812 1813 err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen); 1814 1815 kvfree(in); 1816 1817 return (err); 1818 } 1819 1820 void 1821 mlx5e_disable_sq(struct mlx5e_sq *sq) 1822 { 1823 1824 mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn); 1825 } 1826 1827 static int 1828 mlx5e_open_sq(struct mlx5e_channel *c, 1829 int tc, 1830 struct mlx5e_sq_param *param, 1831 struct mlx5e_sq *sq) 1832 { 1833 int err; 1834 1835 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact; 1836 1837 /* ensure the TX completion event factor is not zero */ 1838 if (sq->cev_factor == 0) 1839 sq->cev_factor = 1; 1840 1841 err = mlx5e_create_sq(c, tc, param, sq); 1842 if (err) 1843 return (err); 1844 1845 err = mlx5e_enable_sq(sq, param, &c->bfreg, c->priv->tisn[tc]); 1846 if (err) 1847 goto err_destroy_sq; 1848 1849 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY); 1850 if (err) 1851 goto err_disable_sq; 1852 1853 WRITE_ONCE(sq->running, 1); 1854 1855 return (0); 1856 1857 err_disable_sq: 1858 mlx5e_disable_sq(sq); 1859 err_destroy_sq: 1860 mlx5e_destroy_sq(sq); 1861 1862 return (err); 1863 } 1864 1865 static void 1866 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep) 1867 { 1868 /* fill up remainder with NOPs */ 1869 while (sq->cev_counter != 0) { 1870 while (!mlx5e_sq_has_room_for(sq, 1)) { 1871 if (can_sleep != 0) { 1872 mtx_unlock(&sq->lock); 1873 msleep(4); 1874 mtx_lock(&sq->lock); 1875 } else { 1876 goto done; 1877 } 1878 } 1879 /* send a single NOP */ 1880 mlx5e_send_nop(sq, 1); 1881 atomic_thread_fence_rel(); 1882 } 1883 done: 1884 mlx5e_tx_notify_hw(sq, false); 1885 } 1886 1887 void 1888 mlx5e_sq_cev_timeout(void *arg) 1889 { 1890 struct mlx5e_sq *sq = arg; 1891 1892 mtx_assert(&sq->lock, MA_OWNED); 1893 1894 /* check next state */ 1895 switch (sq->cev_next_state) { 1896 case MLX5E_CEV_STATE_SEND_NOPS: 1897 /* fill TX ring with NOPs, if any */ 1898 mlx5e_sq_send_nops_locked(sq, 0); 1899 1900 /* check if completed */ 1901 if (sq->cev_counter == 0) { 1902 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL; 1903 return; 1904 } 1905 break; 1906 default: 1907 /* send NOPs on next timeout */ 1908 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS; 1909 break; 1910 } 1911 1912 /* restart timer */ 1913 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq); 1914 } 1915 1916 void 1917 mlx5e_drain_sq(struct mlx5e_sq *sq) 1918 { 1919 int error; 1920 struct mlx5_core_dev *mdev= sq->priv->mdev; 1921 1922 /* 1923 * Check if already stopped. 1924 * 1925 * NOTE: Serialization of this function is managed by the 1926 * caller ensuring the priv's state lock is locked or in case 1927 * of rate limit support, a single thread manages drain and 1928 * resume of SQs. The "running" variable can therefore safely 1929 * be read without any locks. 1930 */ 1931 if (READ_ONCE(sq->running) == 0) 1932 return; 1933 1934 /* don't put more packets into the SQ */ 1935 WRITE_ONCE(sq->running, 0); 1936 1937 /* serialize access to DMA rings */ 1938 mtx_lock(&sq->lock); 1939 1940 /* teardown event factor timer, if any */ 1941 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS; 1942 callout_stop(&sq->cev_callout); 1943 1944 /* send dummy NOPs in order to flush the transmit ring */ 1945 mlx5e_sq_send_nops_locked(sq, 1); 1946 mtx_unlock(&sq->lock); 1947 1948 /* wait till SQ is empty or link is down */ 1949 mtx_lock(&sq->lock); 1950 while (sq->cc != sq->pc && 1951 (sq->priv->media_status_last & IFM_ACTIVE) != 0 && 1952 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR && 1953 pci_channel_offline(mdev->pdev) == 0) { 1954 mtx_unlock(&sq->lock); 1955 msleep(1); 1956 sq->cq.mcq.comp(&sq->cq.mcq, NULL); 1957 mtx_lock(&sq->lock); 1958 } 1959 mtx_unlock(&sq->lock); 1960 1961 /* error out remaining requests */ 1962 error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR); 1963 if (error != 0) { 1964 mlx5_en_err(sq->ifp, 1965 "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error); 1966 } 1967 1968 /* wait till SQ is empty */ 1969 mtx_lock(&sq->lock); 1970 while (sq->cc != sq->pc && 1971 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR && 1972 pci_channel_offline(mdev->pdev) == 0) { 1973 mtx_unlock(&sq->lock); 1974 msleep(1); 1975 sq->cq.mcq.comp(&sq->cq.mcq, NULL); 1976 mtx_lock(&sq->lock); 1977 } 1978 mtx_unlock(&sq->lock); 1979 } 1980 1981 static void 1982 mlx5e_close_sq_wait(struct mlx5e_sq *sq) 1983 { 1984 1985 mlx5e_drain_sq(sq); 1986 mlx5e_disable_sq(sq); 1987 mlx5e_destroy_sq(sq); 1988 } 1989 1990 static int 1991 mlx5e_create_cq(struct mlx5e_priv *priv, 1992 struct mlx5e_cq_param *param, 1993 struct mlx5e_cq *cq, 1994 mlx5e_cq_comp_t *comp, 1995 int eq_ix) 1996 { 1997 struct mlx5_core_dev *mdev = priv->mdev; 1998 struct mlx5_core_cq *mcq = &cq->mcq; 1999 int eqn_not_used; 2000 int irqn; 2001 int err; 2002 u32 i; 2003 2004 err = mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn); 2005 if (err) 2006 return (err); 2007 2008 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, 2009 &cq->wq_ctrl); 2010 if (err) 2011 return (err); 2012 2013 mcq->cqe_sz = 64; 2014 mcq->set_ci_db = cq->wq_ctrl.db.db; 2015 mcq->arm_db = cq->wq_ctrl.db.db + 1; 2016 *mcq->set_ci_db = 0; 2017 *mcq->arm_db = 0; 2018 mcq->vector = eq_ix; 2019 mcq->comp = comp; 2020 mcq->event = mlx5e_cq_error_event; 2021 mcq->irqn = irqn; 2022 2023 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { 2024 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); 2025 2026 cqe->op_own = 0xf1; 2027 } 2028 2029 cq->priv = priv; 2030 2031 return (0); 2032 } 2033 2034 static void 2035 mlx5e_destroy_cq(struct mlx5e_cq *cq) 2036 { 2037 mlx5_wq_destroy(&cq->wq_ctrl); 2038 } 2039 2040 static int 2041 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix) 2042 { 2043 struct mlx5_core_cq *mcq = &cq->mcq; 2044 u32 out[MLX5_ST_SZ_DW(create_cq_out)]; 2045 void *in; 2046 void *cqc; 2047 int inlen; 2048 int irqn_not_used; 2049 int eqn; 2050 int err; 2051 2052 inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 2053 sizeof(u64) * cq->wq_ctrl.buf.npages; 2054 in = mlx5_vzalloc(inlen); 2055 if (in == NULL) 2056 return (-ENOMEM); 2057 2058 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); 2059 2060 memcpy(cqc, param->cqc, sizeof(param->cqc)); 2061 2062 mlx5_fill_page_array(&cq->wq_ctrl.buf, 2063 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas)); 2064 2065 mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used); 2066 2067 MLX5_SET(cqc, cqc, c_eqn, eqn); 2068 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - 2069 PAGE_SHIFT); 2070 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); 2071 2072 err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen, out, sizeof(out)); 2073 2074 kvfree(in); 2075 2076 if (err) 2077 return (err); 2078 2079 mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock)); 2080 2081 return (0); 2082 } 2083 2084 static void 2085 mlx5e_disable_cq(struct mlx5e_cq *cq) 2086 { 2087 2088 mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq); 2089 } 2090 2091 int 2092 mlx5e_open_cq(struct mlx5e_priv *priv, 2093 struct mlx5e_cq_param *param, 2094 struct mlx5e_cq *cq, 2095 mlx5e_cq_comp_t *comp, 2096 int eq_ix) 2097 { 2098 int err; 2099 2100 err = mlx5e_create_cq(priv, param, cq, comp, eq_ix); 2101 if (err) 2102 return (err); 2103 2104 err = mlx5e_enable_cq(cq, param, eq_ix); 2105 if (err) 2106 goto err_destroy_cq; 2107 2108 return (0); 2109 2110 err_destroy_cq: 2111 mlx5e_destroy_cq(cq); 2112 2113 return (err); 2114 } 2115 2116 void 2117 mlx5e_close_cq(struct mlx5e_cq *cq) 2118 { 2119 mlx5e_disable_cq(cq); 2120 mlx5e_destroy_cq(cq); 2121 } 2122 2123 static int 2124 mlx5e_open_tx_cqs(struct mlx5e_channel *c, 2125 struct mlx5e_channel_param *cparam) 2126 { 2127 int err; 2128 int tc; 2129 2130 for (tc = 0; tc < c->priv->num_tc; tc++) { 2131 /* open completion queue */ 2132 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq, 2133 &mlx5e_tx_cq_comp, c->ix); 2134 if (err) 2135 goto err_close_tx_cqs; 2136 } 2137 return (0); 2138 2139 err_close_tx_cqs: 2140 for (tc--; tc >= 0; tc--) 2141 mlx5e_close_cq(&c->sq[tc].cq); 2142 2143 return (err); 2144 } 2145 2146 static void 2147 mlx5e_close_tx_cqs(struct mlx5e_channel *c) 2148 { 2149 int tc; 2150 2151 for (tc = 0; tc < c->priv->num_tc; tc++) 2152 mlx5e_close_cq(&c->sq[tc].cq); 2153 } 2154 2155 static int 2156 mlx5e_open_sqs(struct mlx5e_channel *c, 2157 struct mlx5e_channel_param *cparam) 2158 { 2159 int err; 2160 int tc; 2161 2162 for (tc = 0; tc < c->priv->num_tc; tc++) { 2163 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]); 2164 if (err) 2165 goto err_close_sqs; 2166 } 2167 2168 return (0); 2169 2170 err_close_sqs: 2171 for (tc--; tc >= 0; tc--) 2172 mlx5e_close_sq_wait(&c->sq[tc]); 2173 2174 return (err); 2175 } 2176 2177 static void 2178 mlx5e_close_sqs_wait(struct mlx5e_channel *c) 2179 { 2180 int tc; 2181 2182 for (tc = 0; tc < c->priv->num_tc; tc++) 2183 mlx5e_close_sq_wait(&c->sq[tc]); 2184 } 2185 2186 static void 2187 mlx5e_chan_static_init(struct mlx5e_priv *priv, struct mlx5e_channel *c, int ix) 2188 { 2189 int tc; 2190 2191 /* setup priv and channel number */ 2192 c->priv = priv; 2193 c->ix = ix; 2194 2195 /* setup send tag */ 2196 m_snd_tag_init(&c->tag, c->priv->ifp, &mlx5e_ul_snd_tag_sw); 2197 2198 init_completion(&c->completion); 2199 2200 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF); 2201 2202 callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0); 2203 2204 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) { 2205 struct mlx5e_sq *sq = c->sq + tc; 2206 2207 mtx_init(&sq->lock, "mlx5tx", 2208 MTX_NETWORK_LOCK " TX", MTX_DEF); 2209 mtx_init(&sq->comp_lock, "mlx5comp", 2210 MTX_NETWORK_LOCK " TX", MTX_DEF); 2211 2212 callout_init_mtx(&sq->cev_callout, &sq->lock, 0); 2213 } 2214 2215 mlx5e_iq_static_init(&c->iq); 2216 } 2217 2218 static void 2219 mlx5e_chan_wait_for_completion(struct mlx5e_channel *c) 2220 { 2221 2222 m_snd_tag_rele(&c->tag); 2223 wait_for_completion(&c->completion); 2224 } 2225 2226 static void 2227 mlx5e_priv_wait_for_completion(struct mlx5e_priv *priv, const uint32_t channels) 2228 { 2229 uint32_t x; 2230 2231 for (x = 0; x != channels; x++) 2232 mlx5e_chan_wait_for_completion(&priv->channel[x]); 2233 } 2234 2235 static void 2236 mlx5e_chan_static_destroy(struct mlx5e_channel *c) 2237 { 2238 int tc; 2239 2240 callout_drain(&c->rq.watchdog); 2241 2242 mtx_destroy(&c->rq.mtx); 2243 2244 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) { 2245 callout_drain(&c->sq[tc].cev_callout); 2246 mtx_destroy(&c->sq[tc].lock); 2247 mtx_destroy(&c->sq[tc].comp_lock); 2248 } 2249 2250 mlx5e_iq_static_destroy(&c->iq); 2251 } 2252 2253 static int 2254 mlx5e_open_channel(struct mlx5e_priv *priv, 2255 struct mlx5e_channel_param *cparam, 2256 struct mlx5e_channel *c) 2257 { 2258 struct epoch_tracker et; 2259 int i, err; 2260 2261 /* zero non-persistant data */ 2262 MLX5E_ZERO(&c->rq, mlx5e_rq_zero_start); 2263 for (i = 0; i != priv->num_tc; i++) 2264 MLX5E_ZERO(&c->sq[i], mlx5e_sq_zero_start); 2265 MLX5E_ZERO(&c->iq, mlx5e_iq_zero_start); 2266 2267 /* open transmit completion queue */ 2268 err = mlx5e_open_tx_cqs(c, cparam); 2269 if (err) 2270 goto err_free; 2271 2272 /* open receive completion queue */ 2273 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq, 2274 &mlx5e_rx_cq_comp, c->ix); 2275 if (err) 2276 goto err_close_tx_cqs; 2277 2278 err = mlx5e_open_sqs(c, cparam); 2279 if (err) 2280 goto err_close_rx_cq; 2281 2282 err = mlx5e_iq_open(c, &cparam->sq, &cparam->tx_cq, &c->iq); 2283 if (err) 2284 goto err_close_sqs; 2285 2286 err = mlx5e_open_rq(c, &cparam->rq, &c->rq); 2287 if (err) 2288 goto err_close_iq; 2289 2290 /* poll receive queue initially */ 2291 NET_EPOCH_ENTER(et); 2292 c->rq.cq.mcq.comp(&c->rq.cq.mcq, NULL); 2293 NET_EPOCH_EXIT(et); 2294 2295 return (0); 2296 2297 err_close_iq: 2298 mlx5e_iq_close(&c->iq); 2299 2300 err_close_sqs: 2301 mlx5e_close_sqs_wait(c); 2302 2303 err_close_rx_cq: 2304 mlx5e_close_cq(&c->rq.cq); 2305 2306 err_close_tx_cqs: 2307 mlx5e_close_tx_cqs(c); 2308 2309 err_free: 2310 return (err); 2311 } 2312 2313 static void 2314 mlx5e_close_channel(struct mlx5e_channel *c) 2315 { 2316 mlx5e_close_rq(&c->rq); 2317 } 2318 2319 static void 2320 mlx5e_close_channel_wait(struct mlx5e_channel *c) 2321 { 2322 mlx5e_close_rq_wait(&c->rq); 2323 mlx5e_iq_close(&c->iq); 2324 mlx5e_close_sqs_wait(c); 2325 mlx5e_close_tx_cqs(c); 2326 } 2327 2328 static int 2329 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs) 2330 { 2331 u32 r, n; 2332 2333 r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz : 2334 MLX5E_SW2MB_MTU(priv->ifp->if_mtu); 2335 if (r > MJUM16BYTES) 2336 return (-ENOMEM); 2337 2338 if (r > MJUM9BYTES) 2339 r = MJUM16BYTES; 2340 else if (r > MJUMPAGESIZE) 2341 r = MJUM9BYTES; 2342 else if (r > MCLBYTES) 2343 r = MJUMPAGESIZE; 2344 else 2345 r = MCLBYTES; 2346 2347 /* 2348 * n + 1 must be a power of two, because stride size must be. 2349 * Stride size is 16 * (n + 1), as the first segment is 2350 * control. 2351 */ 2352 for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++) 2353 ; 2354 2355 if (n > MLX5E_MAX_BUSDMA_RX_SEGS) 2356 return (-ENOMEM); 2357 2358 *wqe_sz = r; 2359 *nsegs = n; 2360 return (0); 2361 } 2362 2363 static void 2364 mlx5e_build_rq_param(struct mlx5e_priv *priv, 2365 struct mlx5e_rq_param *param) 2366 { 2367 void *rqc = param->rqc; 2368 void *wq = MLX5_ADDR_OF(rqc, rqc, wq); 2369 u32 wqe_sz, nsegs; 2370 2371 mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs); 2372 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); 2373 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 2374 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) + 2375 nsegs * sizeof(struct mlx5_wqe_data_seg))); 2376 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size); 2377 MLX5_SET(wq, wq, pd, priv->pdn); 2378 2379 param->wq.linear = 1; 2380 } 2381 2382 static void 2383 mlx5e_build_sq_param(struct mlx5e_priv *priv, 2384 struct mlx5e_sq_param *param) 2385 { 2386 void *sqc = param->sqc; 2387 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 2388 2389 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size); 2390 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 2391 MLX5_SET(wq, wq, pd, priv->pdn); 2392 2393 param->wq.linear = 1; 2394 } 2395 2396 static void 2397 mlx5e_build_common_cq_param(struct mlx5e_priv *priv, 2398 struct mlx5e_cq_param *param) 2399 { 2400 void *cqc = param->cqc; 2401 2402 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index); 2403 } 2404 2405 static void 2406 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr) 2407 { 2408 2409 *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE); 2410 2411 /* apply LRO restrictions */ 2412 if (priv->params.hw_lro_en && 2413 ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) { 2414 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO; 2415 } 2416 } 2417 2418 static void 2419 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, 2420 struct mlx5e_cq_param *param) 2421 { 2422 struct net_dim_cq_moder curr; 2423 void *cqc = param->cqc; 2424 2425 /* 2426 * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE 2427 * format is more beneficial for FreeBSD use case. 2428 * 2429 * Adding support for MLX5_CQE_FORMAT_CSUM will require changes 2430 * in mlx5e_decompress_cqe. 2431 */ 2432 if (priv->params.cqe_zipping_en) { 2433 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH); 2434 MLX5_SET(cqc, cqc, cqe_compression_en, 1); 2435 } 2436 2437 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size); 2438 2439 switch (priv->params.rx_cq_moderation_mode) { 2440 case 0: 2441 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec); 2442 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts); 2443 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2444 break; 2445 case 1: 2446 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec); 2447 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts); 2448 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2449 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2450 else 2451 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2452 break; 2453 case 2: 2454 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr); 2455 MLX5_SET(cqc, cqc, cq_period, curr.usec); 2456 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts); 2457 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2458 break; 2459 case 3: 2460 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr); 2461 MLX5_SET(cqc, cqc, cq_period, curr.usec); 2462 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts); 2463 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2464 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2465 else 2466 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2467 break; 2468 default: 2469 break; 2470 } 2471 2472 mlx5e_dim_build_cq_param(priv, param); 2473 2474 mlx5e_build_common_cq_param(priv, param); 2475 } 2476 2477 static void 2478 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv, 2479 struct mlx5e_cq_param *param) 2480 { 2481 void *cqc = param->cqc; 2482 2483 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size); 2484 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec); 2485 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts); 2486 2487 switch (priv->params.tx_cq_moderation_mode) { 2488 case 0: 2489 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2490 break; 2491 default: 2492 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2493 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2494 else 2495 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2496 break; 2497 } 2498 2499 mlx5e_build_common_cq_param(priv, param); 2500 } 2501 2502 static void 2503 mlx5e_build_channel_param(struct mlx5e_priv *priv, 2504 struct mlx5e_channel_param *cparam) 2505 { 2506 memset(cparam, 0, sizeof(*cparam)); 2507 2508 mlx5e_build_rq_param(priv, &cparam->rq); 2509 mlx5e_build_sq_param(priv, &cparam->sq); 2510 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq); 2511 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq); 2512 } 2513 2514 static int 2515 mlx5e_open_channels(struct mlx5e_priv *priv) 2516 { 2517 struct mlx5e_channel_param *cparam; 2518 int err; 2519 int i; 2520 int j; 2521 2522 cparam = malloc(sizeof(*cparam), M_MLX5EN, M_WAITOK); 2523 2524 mlx5e_build_channel_param(priv, cparam); 2525 for (i = 0; i < priv->params.num_channels; i++) { 2526 err = mlx5e_open_channel(priv, cparam, &priv->channel[i]); 2527 if (err) 2528 goto err_close_channels; 2529 2530 /* Bind interrupt vectors, if any. */ 2531 if (priv->params_ethtool.irq_cpu_base > -1) { 2532 cpuset_t cpuset; 2533 int cpu; 2534 int irq; 2535 int eqn; 2536 int nirq; 2537 2538 err = mlx5_vector2eqn(priv->mdev, i, 2539 &eqn, &nirq); 2540 2541 /* error here is non-fatal */ 2542 if (err != 0) 2543 continue; 2544 2545 irq = priv->mdev->priv.msix_arr[nirq].vector; 2546 cpu = (unsigned)(priv->params_ethtool.irq_cpu_base + 2547 i * priv->params_ethtool.irq_cpu_stride) % (unsigned)mp_ncpus; 2548 2549 CPU_ZERO(&cpuset); 2550 CPU_SET(cpu, &cpuset); 2551 intr_setaffinity(irq, CPU_WHICH_INTRHANDLER, &cpuset); 2552 } 2553 } 2554 2555 for (j = 0; j < priv->params.num_channels; j++) { 2556 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq); 2557 if (err) 2558 goto err_close_channels; 2559 } 2560 free(cparam, M_MLX5EN); 2561 return (0); 2562 2563 err_close_channels: 2564 while (i--) { 2565 mlx5e_close_channel(&priv->channel[i]); 2566 mlx5e_close_channel_wait(&priv->channel[i]); 2567 } 2568 free(cparam, M_MLX5EN); 2569 return (err); 2570 } 2571 2572 static void 2573 mlx5e_close_channels(struct mlx5e_priv *priv) 2574 { 2575 int i; 2576 2577 for (i = 0; i < priv->params.num_channels; i++) 2578 mlx5e_close_channel(&priv->channel[i]); 2579 for (i = 0; i < priv->params.num_channels; i++) 2580 mlx5e_close_channel_wait(&priv->channel[i]); 2581 } 2582 2583 static int 2584 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq) 2585 { 2586 2587 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) { 2588 uint8_t cq_mode; 2589 2590 switch (priv->params.tx_cq_moderation_mode) { 2591 case 0: 2592 case 2: 2593 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 2594 break; 2595 default: 2596 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE; 2597 break; 2598 } 2599 2600 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq, 2601 priv->params.tx_cq_moderation_usec, 2602 priv->params.tx_cq_moderation_pkts, 2603 cq_mode)); 2604 } 2605 2606 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq, 2607 priv->params.tx_cq_moderation_usec, 2608 priv->params.tx_cq_moderation_pkts)); 2609 } 2610 2611 static int 2612 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq) 2613 { 2614 2615 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) { 2616 uint8_t cq_mode; 2617 uint8_t dim_mode; 2618 int retval; 2619 2620 switch (priv->params.rx_cq_moderation_mode) { 2621 case 0: 2622 case 2: 2623 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 2624 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; 2625 break; 2626 default: 2627 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE; 2628 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE; 2629 break; 2630 } 2631 2632 /* tear down dynamic interrupt moderation */ 2633 mtx_lock(&rq->mtx); 2634 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 2635 mtx_unlock(&rq->mtx); 2636 2637 /* wait for dynamic interrupt moderation work task, if any */ 2638 cancel_work_sync(&rq->dim.work); 2639 2640 if (priv->params.rx_cq_moderation_mode >= 2) { 2641 struct net_dim_cq_moder curr; 2642 2643 mlx5e_get_default_profile(priv, dim_mode, &curr); 2644 2645 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq, 2646 curr.usec, curr.pkts, cq_mode); 2647 2648 /* set dynamic interrupt moderation mode and zero defaults */ 2649 mtx_lock(&rq->mtx); 2650 rq->dim.mode = dim_mode; 2651 rq->dim.state = 0; 2652 rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE; 2653 mtx_unlock(&rq->mtx); 2654 } else { 2655 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq, 2656 priv->params.rx_cq_moderation_usec, 2657 priv->params.rx_cq_moderation_pkts, 2658 cq_mode); 2659 } 2660 return (retval); 2661 } 2662 2663 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq, 2664 priv->params.rx_cq_moderation_usec, 2665 priv->params.rx_cq_moderation_pkts)); 2666 } 2667 2668 static int 2669 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c) 2670 { 2671 int err; 2672 int i; 2673 2674 err = mlx5e_refresh_rq_params(priv, &c->rq); 2675 if (err) 2676 goto done; 2677 2678 for (i = 0; i != priv->num_tc; i++) { 2679 err = mlx5e_refresh_sq_params(priv, &c->sq[i]); 2680 if (err) 2681 goto done; 2682 } 2683 done: 2684 return (err); 2685 } 2686 2687 int 2688 mlx5e_refresh_channel_params(struct mlx5e_priv *priv) 2689 { 2690 int i; 2691 2692 /* check if channels are closed */ 2693 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 2694 return (EINVAL); 2695 2696 for (i = 0; i < priv->params.num_channels; i++) { 2697 int err; 2698 2699 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]); 2700 if (err) 2701 return (err); 2702 } 2703 return (0); 2704 } 2705 2706 static int 2707 mlx5e_open_tis(struct mlx5e_priv *priv, int tc) 2708 { 2709 struct mlx5_core_dev *mdev = priv->mdev; 2710 u32 in[MLX5_ST_SZ_DW(create_tis_in)]; 2711 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 2712 2713 memset(in, 0, sizeof(in)); 2714 2715 MLX5_SET(tisc, tisc, prio, tc); 2716 MLX5_SET(tisc, tisc, transport_domain, priv->tdn); 2717 2718 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc])); 2719 } 2720 2721 static void 2722 mlx5e_close_tis(struct mlx5e_priv *priv, int tc) 2723 { 2724 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc], 0); 2725 } 2726 2727 static int 2728 mlx5e_open_tises(struct mlx5e_priv *priv) 2729 { 2730 int num_tc = priv->num_tc; 2731 int err; 2732 int tc; 2733 2734 for (tc = 0; tc < num_tc; tc++) { 2735 err = mlx5e_open_tis(priv, tc); 2736 if (err) 2737 goto err_close_tises; 2738 } 2739 2740 return (0); 2741 2742 err_close_tises: 2743 for (tc--; tc >= 0; tc--) 2744 mlx5e_close_tis(priv, tc); 2745 2746 return (err); 2747 } 2748 2749 static void 2750 mlx5e_close_tises(struct mlx5e_priv *priv) 2751 { 2752 int num_tc = priv->num_tc; 2753 int tc; 2754 2755 for (tc = 0; tc < num_tc; tc++) 2756 mlx5e_close_tis(priv, tc); 2757 } 2758 2759 static int 2760 mlx5e_open_default_rqt(struct mlx5e_priv *priv, u32 *prqtn, int sz) 2761 { 2762 u32 *in; 2763 void *rqtc; 2764 int inlen; 2765 int err; 2766 int i; 2767 2768 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 2769 in = mlx5_vzalloc(inlen); 2770 if (in == NULL) 2771 return (-ENOMEM); 2772 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 2773 2774 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 2775 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 2776 2777 for (i = 0; i != sz; i++) 2778 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn); 2779 2780 err = mlx5_core_create_rqt(priv->mdev, in, inlen, prqtn); 2781 kvfree(in); 2782 2783 return (err); 2784 } 2785 2786 static int 2787 mlx5e_open_rqts(struct mlx5e_priv *priv) 2788 { 2789 int err; 2790 int i; 2791 2792 err = mlx5e_open_default_rqt(priv, &priv->rqtn, 2793 1 << priv->params.rx_hash_log_tbl_sz); 2794 if (err) 2795 goto err_default; 2796 2797 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) { 2798 err = mlx5e_open_default_rqt(priv, &priv->channel[i].rqtn, 1); 2799 if (err) 2800 goto err_channel; 2801 } 2802 return (0); 2803 2804 err_channel: 2805 while (i--) 2806 mlx5_core_destroy_rqt(priv->mdev, priv->channel[i].rqtn, 0); 2807 2808 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn, 0); 2809 2810 err_default: 2811 return (err); 2812 } 2813 2814 static void 2815 mlx5e_close_rqts(struct mlx5e_priv *priv) 2816 { 2817 int i; 2818 2819 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) 2820 mlx5_core_destroy_rqt(priv->mdev, priv->channel[i].rqtn, 0); 2821 2822 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn, 0); 2823 } 2824 2825 static int 2826 mlx5e_activate_rqt(struct mlx5e_priv *priv) 2827 { 2828 u32 *in; 2829 void *rqtc; 2830 int inlen; 2831 int err; 2832 int sz; 2833 int i; 2834 2835 sz = 1 << priv->params.rx_hash_log_tbl_sz; 2836 2837 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz; 2838 in = mlx5_vzalloc(inlen); 2839 if (in == NULL) 2840 return (-ENOMEM); 2841 2842 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx); 2843 2844 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 2845 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1); 2846 2847 for (i = 0; i != sz; i++) { 2848 int ix; 2849 #ifdef RSS 2850 ix = rss_get_indirection_to_bucket(i); 2851 #else 2852 ix = i; 2853 #endif 2854 /* ensure we don't overflow */ 2855 ix %= priv->params.num_channels; 2856 2857 /* apply receive side scaling stride, if any */ 2858 ix -= ix % (int)priv->params.channels_rsss; 2859 2860 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn); 2861 } 2862 2863 err = mlx5_core_modify_rqt(priv->mdev, priv->rqtn, in, inlen); 2864 if (err) 2865 goto err_modify; 2866 2867 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32); 2868 2869 MLX5_SET(rqtc, rqtc, rqt_actual_size, 1); 2870 2871 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) { 2872 int ix; 2873 #ifdef RSS 2874 ix = rss_get_indirection_to_bucket(i); 2875 #else 2876 ix = i; 2877 #endif 2878 /* ensure we don't overflow */ 2879 ix %= priv->params.num_channels; 2880 2881 /* apply receive side scaling stride, if any */ 2882 ix -= ix % (int)priv->params.channels_rsss; 2883 2884 MLX5_SET(rqtc, rqtc, rq_num[0], priv->channel[ix].rq.rqn); 2885 2886 err = mlx5_core_modify_rqt(priv->mdev, priv->channel[i].rqtn, in, inlen); 2887 if (err) 2888 goto err_modify; 2889 } 2890 2891 err_modify: 2892 kvfree(in); 2893 return (err); 2894 } 2895 2896 static int 2897 mlx5e_deactivate_rqt(struct mlx5e_priv *priv) 2898 { 2899 u32 *in; 2900 void *rqtc; 2901 int inlen; 2902 int err; 2903 int sz; 2904 int i; 2905 2906 sz = 1 << priv->params.rx_hash_log_tbl_sz; 2907 2908 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz; 2909 in = mlx5_vzalloc(inlen); 2910 if (in == NULL) 2911 return (-ENOMEM); 2912 2913 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx); 2914 2915 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 2916 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1); 2917 2918 for (i = 0; i != sz; i++) 2919 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn); 2920 2921 err = mlx5_core_modify_rqt(priv->mdev, priv->rqtn, in, inlen); 2922 if (err) 2923 goto err_modify; 2924 2925 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32); 2926 2927 MLX5_SET(rqtc, rqtc, rqt_actual_size, 1); 2928 2929 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) { 2930 MLX5_SET(rqtc, rqtc, rq_num[0], priv->drop_rq.rqn); 2931 2932 err = mlx5_core_modify_rqt(priv->mdev, priv->channel[i].rqtn, in, inlen); 2933 if (err) 2934 goto err_modify; 2935 } 2936 2937 err_modify: 2938 kvfree(in); 2939 return (err); 2940 } 2941 2942 #define MLX5E_RSS_KEY_SIZE (10 * 4) /* bytes */ 2943 2944 static void 2945 mlx5e_get_rss_key(void *key_ptr) 2946 { 2947 #ifdef RSS 2948 rss_getkey(key_ptr); 2949 #else 2950 static const u32 rsskey[] = { 2951 cpu_to_be32(0xD181C62C), 2952 cpu_to_be32(0xF7F4DB5B), 2953 cpu_to_be32(0x1983A2FC), 2954 cpu_to_be32(0x943E1ADB), 2955 cpu_to_be32(0xD9389E6B), 2956 cpu_to_be32(0xD1039C2C), 2957 cpu_to_be32(0xA74499AD), 2958 cpu_to_be32(0x593D56D9), 2959 cpu_to_be32(0xF3253C06), 2960 cpu_to_be32(0x2ADC1FFC), 2961 }; 2962 CTASSERT(sizeof(rsskey) == MLX5E_RSS_KEY_SIZE); 2963 memcpy(key_ptr, rsskey, MLX5E_RSS_KEY_SIZE); 2964 #endif 2965 } 2966 2967 static void 2968 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt, bool inner_vxlan) 2969 { 2970 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 2971 void *hfsi = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 2972 void *hfs = inner_vxlan ? hfsi : hfso; 2973 __be32 *hkey; 2974 2975 MLX5_SET(tirc, tirc, transport_domain, priv->tdn); 2976 2977 #define ROUGH_MAX_L2_L3_HDR_SZ 256 2978 2979 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2980 MLX5_HASH_FIELD_SEL_DST_IP) 2981 2982 #define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2983 MLX5_HASH_FIELD_SEL_DST_IP |\ 2984 MLX5_HASH_FIELD_SEL_L4_SPORT |\ 2985 MLX5_HASH_FIELD_SEL_L4_DPORT) 2986 2987 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2988 MLX5_HASH_FIELD_SEL_DST_IP |\ 2989 MLX5_HASH_FIELD_SEL_IPSEC_SPI) 2990 2991 if (priv->params.hw_lro_en) { 2992 MLX5_SET(tirc, tirc, lro_enable_mask, 2993 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | 2994 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO); 2995 MLX5_SET(tirc, tirc, lro_max_msg_sz, 2996 (priv->params.lro_wqe_sz - 2997 ROUGH_MAX_L2_L3_HDR_SZ) >> 8); 2998 /* TODO: add the option to choose timer value dynamically */ 2999 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, 3000 MLX5_CAP_ETH(priv->mdev, 3001 lro_timer_supported_periods[2])); 3002 } 3003 3004 if (inner_vxlan) 3005 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 3006 3007 /* 3008 * All packets must go through the indirection table, RQT, 3009 * because it is not possible to modify the RQN of the TIR 3010 * for direct dispatchment after it is created, typically 3011 * when the link goes up and down. 3012 */ 3013 MLX5_SET(tirc, tirc, disp_type, 3014 MLX5_TIRC_DISP_TYPE_INDIRECT); 3015 MLX5_SET(tirc, tirc, indirect_table, 3016 priv->rqtn); 3017 MLX5_SET(tirc, tirc, rx_hash_fn, 3018 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ); 3019 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 3020 3021 CTASSERT(MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key) >= 3022 MLX5E_RSS_KEY_SIZE); 3023 #ifdef RSS 3024 /* 3025 * The FreeBSD RSS implementation does currently not 3026 * support symmetric Toeplitz hashes: 3027 */ 3028 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0); 3029 #else 3030 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 3031 #endif 3032 mlx5e_get_rss_key(hkey); 3033 3034 switch (tt) { 3035 case MLX5E_TT_IPV4_TCP: 3036 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3037 MLX5_L3_PROT_TYPE_IPV4); 3038 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type, 3039 MLX5_L4_PROT_TYPE_TCP); 3040 #ifdef RSS 3041 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) { 3042 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3043 MLX5_HASH_IP); 3044 } else 3045 #endif 3046 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3047 MLX5_HASH_ALL); 3048 break; 3049 3050 case MLX5E_TT_IPV6_TCP: 3051 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3052 MLX5_L3_PROT_TYPE_IPV6); 3053 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type, 3054 MLX5_L4_PROT_TYPE_TCP); 3055 #ifdef RSS 3056 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) { 3057 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3058 MLX5_HASH_IP); 3059 } else 3060 #endif 3061 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3062 MLX5_HASH_ALL); 3063 break; 3064 3065 case MLX5E_TT_IPV4_UDP: 3066 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3067 MLX5_L3_PROT_TYPE_IPV4); 3068 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type, 3069 MLX5_L4_PROT_TYPE_UDP); 3070 #ifdef RSS 3071 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) { 3072 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3073 MLX5_HASH_IP); 3074 } else 3075 #endif 3076 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3077 MLX5_HASH_ALL); 3078 break; 3079 3080 case MLX5E_TT_IPV6_UDP: 3081 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3082 MLX5_L3_PROT_TYPE_IPV6); 3083 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type, 3084 MLX5_L4_PROT_TYPE_UDP); 3085 #ifdef RSS 3086 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) { 3087 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3088 MLX5_HASH_IP); 3089 } else 3090 #endif 3091 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3092 MLX5_HASH_ALL); 3093 break; 3094 3095 case MLX5E_TT_IPV4_IPSEC_AH: 3096 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3097 MLX5_L3_PROT_TYPE_IPV4); 3098 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3099 MLX5_HASH_IP_IPSEC_SPI); 3100 break; 3101 3102 case MLX5E_TT_IPV6_IPSEC_AH: 3103 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3104 MLX5_L3_PROT_TYPE_IPV6); 3105 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3106 MLX5_HASH_IP_IPSEC_SPI); 3107 break; 3108 3109 case MLX5E_TT_IPV4_IPSEC_ESP: 3110 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3111 MLX5_L3_PROT_TYPE_IPV4); 3112 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3113 MLX5_HASH_IP_IPSEC_SPI); 3114 break; 3115 3116 case MLX5E_TT_IPV6_IPSEC_ESP: 3117 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3118 MLX5_L3_PROT_TYPE_IPV6); 3119 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3120 MLX5_HASH_IP_IPSEC_SPI); 3121 break; 3122 3123 case MLX5E_TT_IPV4: 3124 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3125 MLX5_L3_PROT_TYPE_IPV4); 3126 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3127 MLX5_HASH_IP); 3128 break; 3129 3130 case MLX5E_TT_IPV6: 3131 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3132 MLX5_L3_PROT_TYPE_IPV6); 3133 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3134 MLX5_HASH_IP); 3135 break; 3136 3137 default: 3138 break; 3139 } 3140 } 3141 3142 static int 3143 mlx5e_open_tir(struct mlx5e_priv *priv, int tt, bool inner_vxlan) 3144 { 3145 struct mlx5_core_dev *mdev = priv->mdev; 3146 u32 *in; 3147 void *tirc; 3148 int inlen; 3149 int err; 3150 3151 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 3152 in = mlx5_vzalloc(inlen); 3153 if (in == NULL) 3154 return (-ENOMEM); 3155 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context); 3156 3157 mlx5e_build_tir_ctx(priv, tirc, tt, inner_vxlan); 3158 3159 err = mlx5_core_create_tir(mdev, in, inlen, inner_vxlan ? 3160 &priv->tirn_inner_vxlan[tt] : &priv->tirn[tt]); 3161 3162 kvfree(in); 3163 3164 return (err); 3165 } 3166 3167 static void 3168 mlx5e_close_tir(struct mlx5e_priv *priv, int tt, bool inner_vxlan) 3169 { 3170 mlx5_core_destroy_tir(priv->mdev, inner_vxlan ? 3171 priv->tirn_inner_vxlan[tt] : priv->tirn[tt], 0); 3172 } 3173 3174 static int 3175 mlx5e_open_tirs(struct mlx5e_priv *priv) 3176 { 3177 int err; 3178 int i; 3179 3180 for (i = 0; i != 2 * MLX5E_NUM_TT; i++) { 3181 err = mlx5e_open_tir(priv, i / 2, (i % 2) ? true : false); 3182 if (err) 3183 goto err_close_tirs; 3184 } 3185 3186 return (0); 3187 3188 err_close_tirs: 3189 for (i--; i >= 0; i--) 3190 mlx5e_close_tir(priv, i / 2, (i % 2) ? true : false); 3191 3192 return (err); 3193 } 3194 3195 static void 3196 mlx5e_close_tirs(struct mlx5e_priv *priv) 3197 { 3198 int i; 3199 3200 for (i = 0; i != 2 * MLX5E_NUM_TT; i++) 3201 mlx5e_close_tir(priv, i / 2, (i % 2) ? true : false); 3202 } 3203 3204 /* 3205 * SW MTU does not include headers, 3206 * HW MTU includes all headers and checksums. 3207 */ 3208 static int 3209 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu) 3210 { 3211 struct mlx5e_priv *priv = ifp->if_softc; 3212 struct mlx5_core_dev *mdev = priv->mdev; 3213 int hw_mtu; 3214 int err; 3215 3216 hw_mtu = MLX5E_SW2HW_MTU(sw_mtu); 3217 3218 err = mlx5_set_port_mtu(mdev, hw_mtu); 3219 if (err) { 3220 mlx5_en_err(ifp, "mlx5_set_port_mtu failed setting %d, err=%d\n", 3221 sw_mtu, err); 3222 return (err); 3223 } 3224 3225 /* Update vport context MTU */ 3226 err = mlx5_set_vport_mtu(mdev, hw_mtu); 3227 if (err) { 3228 mlx5_en_err(ifp, 3229 "Failed updating vport context with MTU size, err=%d\n", 3230 err); 3231 } 3232 3233 ifp->if_mtu = sw_mtu; 3234 3235 err = mlx5_query_vport_mtu(mdev, &hw_mtu); 3236 if (err || !hw_mtu) { 3237 /* fallback to port oper mtu */ 3238 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu); 3239 } 3240 if (err) { 3241 mlx5_en_err(ifp, 3242 "Query port MTU, after setting new MTU value, failed\n"); 3243 return (err); 3244 } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) { 3245 err = -E2BIG, 3246 mlx5_en_err(ifp, 3247 "Port MTU %d is smaller than ifp mtu %d\n", 3248 hw_mtu, sw_mtu); 3249 } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) { 3250 err = -EINVAL; 3251 mlx5_en_err(ifp, 3252 "Port MTU %d is bigger than ifp mtu %d\n", 3253 hw_mtu, sw_mtu); 3254 } 3255 priv->params_ethtool.hw_mtu = hw_mtu; 3256 3257 /* compute MSB */ 3258 while (hw_mtu & (hw_mtu - 1)) 3259 hw_mtu &= (hw_mtu - 1); 3260 priv->params_ethtool.hw_mtu_msb = hw_mtu; 3261 3262 return (err); 3263 } 3264 3265 int 3266 mlx5e_open_locked(struct ifnet *ifp) 3267 { 3268 struct mlx5e_priv *priv = ifp->if_softc; 3269 int err; 3270 u16 set_id; 3271 3272 /* check if already opened */ 3273 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 3274 return (0); 3275 3276 #ifdef RSS 3277 if (rss_getnumbuckets() > priv->params.num_channels) { 3278 mlx5_en_info(ifp, 3279 "NOTE: There are more RSS buckets(%u) than channels(%u) available\n", 3280 rss_getnumbuckets(), priv->params.num_channels); 3281 } 3282 #endif 3283 err = mlx5e_open_tises(priv); 3284 if (err) { 3285 mlx5_en_err(ifp, "mlx5e_open_tises failed, %d\n", err); 3286 return (err); 3287 } 3288 err = mlx5_vport_alloc_q_counter(priv->mdev, 3289 MLX5_INTERFACE_PROTOCOL_ETH, &set_id); 3290 if (err) { 3291 mlx5_en_err(priv->ifp, 3292 "mlx5_vport_alloc_q_counter failed: %d\n", err); 3293 goto err_close_tises; 3294 } 3295 /* store counter set ID */ 3296 priv->counter_set_id = set_id; 3297 3298 err = mlx5e_open_channels(priv); 3299 if (err) { 3300 mlx5_en_err(ifp, 3301 "mlx5e_open_channels failed, %d\n", err); 3302 goto err_dalloc_q_counter; 3303 } 3304 err = mlx5e_activate_rqt(priv); 3305 if (err) { 3306 mlx5_en_err(ifp, "mlx5e_activate_rqt failed, %d\n", err); 3307 goto err_close_channels; 3308 } 3309 3310 set_bit(MLX5E_STATE_OPENED, &priv->state); 3311 3312 mlx5e_update_carrier(priv); 3313 3314 return (0); 3315 3316 err_close_channels: 3317 mlx5e_close_channels(priv); 3318 3319 err_dalloc_q_counter: 3320 mlx5_vport_dealloc_q_counter(priv->mdev, 3321 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 3322 3323 err_close_tises: 3324 mlx5e_close_tises(priv); 3325 3326 return (err); 3327 } 3328 3329 static void 3330 mlx5e_open(void *arg) 3331 { 3332 struct mlx5e_priv *priv = arg; 3333 3334 PRIV_LOCK(priv); 3335 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP)) 3336 mlx5_en_err(priv->ifp, 3337 "Setting port status to up failed\n"); 3338 3339 mlx5e_open_locked(priv->ifp); 3340 priv->ifp->if_drv_flags |= IFF_DRV_RUNNING; 3341 PRIV_UNLOCK(priv); 3342 } 3343 3344 int 3345 mlx5e_close_locked(struct ifnet *ifp) 3346 { 3347 struct mlx5e_priv *priv = ifp->if_softc; 3348 3349 /* check if already closed */ 3350 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3351 return (0); 3352 3353 clear_bit(MLX5E_STATE_OPENED, &priv->state); 3354 3355 if_link_state_change(priv->ifp, LINK_STATE_DOWN); 3356 3357 mlx5e_deactivate_rqt(priv); 3358 mlx5e_close_channels(priv); 3359 mlx5_vport_dealloc_q_counter(priv->mdev, 3360 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 3361 mlx5e_close_tises(priv); 3362 3363 return (0); 3364 } 3365 3366 static uint64_t 3367 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt) 3368 { 3369 struct mlx5e_priv *priv = ifp->if_softc; 3370 u64 retval; 3371 3372 /* PRIV_LOCK(priv); XXX not allowed */ 3373 switch (cnt) { 3374 case IFCOUNTER_IPACKETS: 3375 retval = priv->stats.vport.rx_packets; 3376 break; 3377 case IFCOUNTER_IERRORS: 3378 retval = priv->stats.pport.in_range_len_errors + 3379 priv->stats.pport.out_of_range_len + 3380 priv->stats.pport.too_long_errors + 3381 priv->stats.pport.check_seq_err + 3382 priv->stats.pport.alignment_err; 3383 break; 3384 case IFCOUNTER_IQDROPS: 3385 retval = priv->stats.vport.rx_out_of_buffer; 3386 break; 3387 case IFCOUNTER_OPACKETS: 3388 retval = priv->stats.vport.tx_packets; 3389 break; 3390 case IFCOUNTER_OERRORS: 3391 retval = priv->stats.port_stats_debug.out_discards; 3392 break; 3393 case IFCOUNTER_IBYTES: 3394 retval = priv->stats.vport.rx_bytes; 3395 break; 3396 case IFCOUNTER_OBYTES: 3397 retval = priv->stats.vport.tx_bytes; 3398 break; 3399 case IFCOUNTER_IMCASTS: 3400 retval = priv->stats.vport.rx_multicast_packets; 3401 break; 3402 case IFCOUNTER_OMCASTS: 3403 retval = priv->stats.vport.tx_multicast_packets; 3404 break; 3405 case IFCOUNTER_OQDROPS: 3406 retval = priv->stats.vport.tx_queue_dropped; 3407 break; 3408 case IFCOUNTER_COLLISIONS: 3409 retval = priv->stats.pport.collisions; 3410 break; 3411 default: 3412 retval = if_get_counter_default(ifp, cnt); 3413 break; 3414 } 3415 /* PRIV_UNLOCK(priv); XXX not allowed */ 3416 return (retval); 3417 } 3418 3419 static void 3420 mlx5e_set_rx_mode(struct ifnet *ifp) 3421 { 3422 struct mlx5e_priv *priv = ifp->if_softc; 3423 3424 queue_work(priv->wq, &priv->set_rx_mode_work); 3425 } 3426 3427 static int 3428 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3429 { 3430 struct mlx5e_priv *priv; 3431 struct ifreq *ifr; 3432 struct ifdownreason *ifdr; 3433 struct ifi2creq i2c; 3434 struct ifrsskey *ifrk; 3435 struct ifrsshash *ifrh; 3436 int error = 0; 3437 int mask = 0; 3438 int size_read = 0; 3439 int module_status; 3440 int module_num; 3441 int max_mtu; 3442 uint8_t read_addr; 3443 3444 priv = ifp->if_softc; 3445 3446 /* check if detaching */ 3447 if (priv == NULL || priv->gone != 0) 3448 return (ENXIO); 3449 3450 switch (command) { 3451 case SIOCSIFMTU: 3452 ifr = (struct ifreq *)data; 3453 3454 PRIV_LOCK(priv); 3455 mlx5_query_port_max_mtu(priv->mdev, &max_mtu); 3456 3457 if (ifr->ifr_mtu >= MLX5E_MTU_MIN && 3458 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) { 3459 int was_opened; 3460 3461 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 3462 if (was_opened) 3463 mlx5e_close_locked(ifp); 3464 3465 /* set new MTU */ 3466 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu); 3467 3468 if (was_opened) 3469 mlx5e_open_locked(ifp); 3470 } else { 3471 error = EINVAL; 3472 mlx5_en_err(ifp, 3473 "Invalid MTU value. Min val: %d, Max val: %d\n", 3474 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu)); 3475 } 3476 PRIV_UNLOCK(priv); 3477 break; 3478 case SIOCSIFFLAGS: 3479 if ((ifp->if_flags & IFF_UP) && 3480 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3481 mlx5e_set_rx_mode(ifp); 3482 break; 3483 } 3484 PRIV_LOCK(priv); 3485 if (ifp->if_flags & IFF_UP) { 3486 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3487 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3488 mlx5e_open_locked(ifp); 3489 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3490 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP); 3491 } 3492 } else { 3493 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3494 mlx5_set_port_status(priv->mdev, 3495 MLX5_PORT_DOWN); 3496 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 3497 mlx5e_close_locked(ifp); 3498 mlx5e_update_carrier(priv); 3499 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3500 } 3501 } 3502 PRIV_UNLOCK(priv); 3503 break; 3504 case SIOCADDMULTI: 3505 case SIOCDELMULTI: 3506 mlx5e_set_rx_mode(ifp); 3507 break; 3508 case SIOCSIFMEDIA: 3509 case SIOCGIFMEDIA: 3510 case SIOCGIFXMEDIA: 3511 ifr = (struct ifreq *)data; 3512 error = ifmedia_ioctl(ifp, ifr, &priv->media, command); 3513 break; 3514 case SIOCSIFCAP: 3515 ifr = (struct ifreq *)data; 3516 PRIV_LOCK(priv); 3517 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3518 3519 if (mask & IFCAP_TXCSUM) { 3520 ifp->if_capenable ^= IFCAP_TXCSUM; 3521 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 3522 3523 if (IFCAP_TSO4 & ifp->if_capenable && 3524 !(IFCAP_TXCSUM & ifp->if_capenable)) { 3525 mask &= ~IFCAP_TSO4; 3526 ifp->if_capenable &= ~IFCAP_TSO4; 3527 ifp->if_hwassist &= ~CSUM_IP_TSO; 3528 mlx5_en_err(ifp, 3529 "tso4 disabled due to -txcsum.\n"); 3530 } 3531 } 3532 if (mask & IFCAP_TXCSUM_IPV6) { 3533 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 3534 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 3535 3536 if (IFCAP_TSO6 & ifp->if_capenable && 3537 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 3538 mask &= ~IFCAP_TSO6; 3539 ifp->if_capenable &= ~IFCAP_TSO6; 3540 ifp->if_hwassist &= ~CSUM_IP6_TSO; 3541 mlx5_en_err(ifp, 3542 "tso6 disabled due to -txcsum6.\n"); 3543 } 3544 } 3545 if (mask & IFCAP_MEXTPG) 3546 ifp->if_capenable ^= IFCAP_MEXTPG; 3547 if (mask & IFCAP_TXTLS4) 3548 ifp->if_capenable ^= IFCAP_TXTLS4; 3549 if (mask & IFCAP_TXTLS6) 3550 ifp->if_capenable ^= IFCAP_TXTLS6; 3551 #ifdef RATELIMIT 3552 if (mask & IFCAP_TXTLS_RTLMT) 3553 ifp->if_capenable ^= IFCAP_TXTLS_RTLMT; 3554 #endif 3555 if (mask & IFCAP_RXCSUM) 3556 ifp->if_capenable ^= IFCAP_RXCSUM; 3557 if (mask & IFCAP_RXCSUM_IPV6) 3558 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 3559 if (mask & IFCAP_TSO4) { 3560 if (!(IFCAP_TSO4 & ifp->if_capenable) && 3561 !(IFCAP_TXCSUM & ifp->if_capenable)) { 3562 mlx5_en_err(ifp, "enable txcsum first.\n"); 3563 error = EAGAIN; 3564 goto out; 3565 } 3566 ifp->if_capenable ^= IFCAP_TSO4; 3567 ifp->if_hwassist ^= CSUM_IP_TSO; 3568 } 3569 if (mask & IFCAP_TSO6) { 3570 if (!(IFCAP_TSO6 & ifp->if_capenable) && 3571 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 3572 mlx5_en_err(ifp, "enable txcsum6 first.\n"); 3573 error = EAGAIN; 3574 goto out; 3575 } 3576 ifp->if_capenable ^= IFCAP_TSO6; 3577 ifp->if_hwassist ^= CSUM_IP6_TSO; 3578 } 3579 if (mask & IFCAP_VLAN_HWTSO) 3580 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3581 if (mask & IFCAP_VLAN_HWFILTER) { 3582 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) 3583 mlx5e_disable_vlan_filter(priv); 3584 else 3585 mlx5e_enable_vlan_filter(priv); 3586 3587 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER; 3588 } 3589 if (mask & IFCAP_VLAN_HWTAGGING) 3590 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3591 if (mask & IFCAP_WOL_MAGIC) 3592 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3593 if (mask & IFCAP_VXLAN_HWCSUM) { 3594 const bool was_enabled = 3595 (ifp->if_capenable & IFCAP_VXLAN_HWCSUM) != 0; 3596 if (was_enabled) 3597 mlx5e_del_all_vxlan_rules(priv); 3598 ifp->if_capenable ^= IFCAP_VXLAN_HWCSUM; 3599 ifp->if_hwassist ^= CSUM_INNER_IP | CSUM_INNER_IP_UDP | 3600 CSUM_INNER_IP_TCP | CSUM_INNER_IP6_UDP | 3601 CSUM_INNER_IP6_TCP; 3602 if (!was_enabled) { 3603 int err = mlx5e_add_all_vxlan_rules(priv); 3604 if (err != 0) { 3605 mlx5_en_err(ifp, 3606 "mlx5e_add_all_vxlan_rules() failed, %d (ignored)\n", err); 3607 } 3608 } 3609 } 3610 if (mask & IFCAP_VXLAN_HWTSO) { 3611 ifp->if_capenable ^= IFCAP_VXLAN_HWTSO; 3612 ifp->if_hwassist ^= CSUM_INNER_IP_TSO | 3613 CSUM_INNER_IP6_TSO; 3614 } 3615 3616 VLAN_CAPABILITIES(ifp); 3617 /* turn off LRO means also turn of HW LRO - if it's on */ 3618 if (mask & IFCAP_LRO) { 3619 int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 3620 bool need_restart = false; 3621 3622 ifp->if_capenable ^= IFCAP_LRO; 3623 3624 /* figure out if updating HW LRO is needed */ 3625 if (!(ifp->if_capenable & IFCAP_LRO)) { 3626 if (priv->params.hw_lro_en) { 3627 priv->params.hw_lro_en = false; 3628 need_restart = true; 3629 } 3630 } else { 3631 if (priv->params.hw_lro_en == false && 3632 priv->params_ethtool.hw_lro != 0) { 3633 priv->params.hw_lro_en = true; 3634 need_restart = true; 3635 } 3636 } 3637 if (was_opened && need_restart) { 3638 mlx5e_close_locked(ifp); 3639 mlx5e_open_locked(ifp); 3640 } 3641 } 3642 if (mask & IFCAP_HWRXTSTMP) { 3643 ifp->if_capenable ^= IFCAP_HWRXTSTMP; 3644 if (ifp->if_capenable & IFCAP_HWRXTSTMP) { 3645 if (priv->clbr_done == 0) 3646 mlx5e_reset_calibration_callout(priv); 3647 } else { 3648 callout_drain(&priv->tstmp_clbr); 3649 priv->clbr_done = 0; 3650 } 3651 } 3652 out: 3653 PRIV_UNLOCK(priv); 3654 break; 3655 3656 case SIOCGI2C: 3657 ifr = (struct ifreq *)data; 3658 3659 /* 3660 * Copy from the user-space address ifr_data to the 3661 * kernel-space address i2c 3662 */ 3663 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 3664 if (error) 3665 break; 3666 3667 if (i2c.len > sizeof(i2c.data)) { 3668 error = EINVAL; 3669 break; 3670 } 3671 3672 PRIV_LOCK(priv); 3673 /* Get module_num which is required for the query_eeprom */ 3674 error = mlx5_query_module_num(priv->mdev, &module_num); 3675 if (error) { 3676 mlx5_en_err(ifp, 3677 "Query module num failed, eeprom reading is not supported\n"); 3678 error = EINVAL; 3679 goto err_i2c; 3680 } 3681 /* Check if module is present before doing an access */ 3682 module_status = mlx5_query_module_status(priv->mdev, module_num); 3683 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED) { 3684 error = EINVAL; 3685 goto err_i2c; 3686 } 3687 /* 3688 * Currently 0XA0 and 0xA2 are the only addresses permitted. 3689 * The internal conversion is as follows: 3690 */ 3691 if (i2c.dev_addr == 0xA0) 3692 read_addr = MLX5_I2C_ADDR_LOW; 3693 else if (i2c.dev_addr == 0xA2) 3694 read_addr = MLX5_I2C_ADDR_HIGH; 3695 else { 3696 mlx5_en_err(ifp, 3697 "Query eeprom failed, Invalid Address: %X\n", 3698 i2c.dev_addr); 3699 error = EINVAL; 3700 goto err_i2c; 3701 } 3702 error = mlx5_query_eeprom(priv->mdev, 3703 read_addr, MLX5_EEPROM_LOW_PAGE, 3704 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num, 3705 (uint32_t *)i2c.data, &size_read); 3706 if (error) { 3707 mlx5_en_err(ifp, 3708 "Query eeprom failed, eeprom reading is not supported\n"); 3709 error = EINVAL; 3710 goto err_i2c; 3711 } 3712 3713 if (i2c.len > MLX5_EEPROM_MAX_BYTES) { 3714 error = mlx5_query_eeprom(priv->mdev, 3715 read_addr, MLX5_EEPROM_LOW_PAGE, 3716 (uint32_t)(i2c.offset + size_read), 3717 (uint32_t)(i2c.len - size_read), module_num, 3718 (uint32_t *)(i2c.data + size_read), &size_read); 3719 } 3720 if (error) { 3721 mlx5_en_err(ifp, 3722 "Query eeprom failed, eeprom reading is not supported\n"); 3723 error = EINVAL; 3724 goto err_i2c; 3725 } 3726 3727 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 3728 err_i2c: 3729 PRIV_UNLOCK(priv); 3730 break; 3731 case SIOCGIFDOWNREASON: 3732 ifdr = (struct ifdownreason *)data; 3733 bzero(ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg)); 3734 PRIV_LOCK(priv); 3735 error = -mlx5_query_pddr_troubleshooting_info(priv->mdev, NULL, 3736 ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg)); 3737 PRIV_UNLOCK(priv); 3738 if (error == 0) 3739 ifdr->ifdr_reason = IFDR_REASON_MSG; 3740 break; 3741 3742 case SIOCGIFRSSKEY: 3743 ifrk = (struct ifrsskey *)data; 3744 ifrk->ifrk_func = RSS_FUNC_TOEPLITZ; 3745 ifrk->ifrk_keylen = MLX5E_RSS_KEY_SIZE; 3746 CTASSERT(sizeof(ifrk->ifrk_key) >= MLX5E_RSS_KEY_SIZE); 3747 mlx5e_get_rss_key(ifrk->ifrk_key); 3748 break; 3749 3750 case SIOCGIFRSSHASH: 3751 ifrh = (struct ifrsshash *)data; 3752 ifrh->ifrh_func = RSS_FUNC_TOEPLITZ; 3753 ifrh->ifrh_types = 3754 RSS_TYPE_IPV4 | 3755 RSS_TYPE_TCP_IPV4 | 3756 RSS_TYPE_UDP_IPV4 | 3757 RSS_TYPE_IPV6 | 3758 RSS_TYPE_TCP_IPV6 | 3759 RSS_TYPE_UDP_IPV6; 3760 break; 3761 3762 default: 3763 error = ether_ioctl(ifp, command, data); 3764 break; 3765 } 3766 return (error); 3767 } 3768 3769 static int 3770 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev) 3771 { 3772 /* 3773 * TODO: uncoment once FW really sets all these bits if 3774 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap || 3775 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap || 3776 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return 3777 * -ENOTSUPP; 3778 */ 3779 3780 /* TODO: add more must-to-have features */ 3781 3782 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) 3783 return (-ENODEV); 3784 3785 return (0); 3786 } 3787 3788 static u16 3789 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev) 3790 { 3791 const int min_size = ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN; 3792 const int max_size = MLX5E_MAX_TX_INLINE; 3793 const int bf_buf_size = 3794 ((1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U) - 3795 (sizeof(struct mlx5e_tx_wqe) - 2); 3796 3797 /* verify against driver limits */ 3798 if (bf_buf_size > max_size) 3799 return (max_size); 3800 else if (bf_buf_size < min_size) 3801 return (min_size); 3802 else 3803 return (bf_buf_size); 3804 } 3805 3806 static int 3807 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev, 3808 struct mlx5e_priv *priv, 3809 int num_comp_vectors) 3810 { 3811 int err; 3812 3813 /* 3814 * TODO: Consider link speed for setting "log_sq_size", 3815 * "log_rq_size" and "cq_moderation_xxx": 3816 */ 3817 priv->params.log_sq_size = 3818 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; 3819 priv->params.log_rq_size = 3820 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; 3821 priv->params.rx_cq_moderation_usec = 3822 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 3823 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE : 3824 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; 3825 priv->params.rx_cq_moderation_mode = 3826 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0; 3827 priv->params.rx_cq_moderation_pkts = 3828 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; 3829 priv->params.tx_cq_moderation_usec = 3830 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; 3831 priv->params.tx_cq_moderation_pkts = 3832 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; 3833 priv->params.min_rx_wqes = 3834 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES; 3835 priv->params.rx_hash_log_tbl_sz = 3836 (order_base_2(num_comp_vectors) > 3837 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ? 3838 order_base_2(num_comp_vectors) : 3839 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ; 3840 priv->params.num_tc = 1; 3841 priv->params.default_vlan_prio = 0; 3842 priv->counter_set_id = -1; 3843 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev); 3844 3845 err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode); 3846 if (err) 3847 return (err); 3848 3849 /* 3850 * hw lro is currently defaulted to off. when it won't anymore we 3851 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)" 3852 */ 3853 priv->params.hw_lro_en = false; 3854 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; 3855 3856 /* 3857 * CQE zipping is currently defaulted to off. when it won't 3858 * anymore we will consider the HW capability: 3859 * "!!MLX5_CAP_GEN(mdev, cqe_compression)" 3860 */ 3861 priv->params.cqe_zipping_en = false; 3862 3863 priv->mdev = mdev; 3864 priv->params.num_channels = num_comp_vectors; 3865 priv->params.channels_rsss = 1; 3866 priv->order_base_2_num_channels = order_base_2(num_comp_vectors); 3867 priv->queue_mapping_channel_mask = 3868 roundup_pow_of_two(num_comp_vectors) - 1; 3869 priv->num_tc = priv->params.num_tc; 3870 priv->default_vlan_prio = priv->params.default_vlan_prio; 3871 3872 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work); 3873 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); 3874 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); 3875 3876 return (0); 3877 } 3878 3879 static void 3880 mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc) 3881 { 3882 bool ro_pci_enable = 3883 pci_get_relaxed_ordering_enabled(mdev->pdev->dev.bsddev); 3884 bool ro_write = MLX5_CAP_GEN(mdev, relaxed_ordering_write); 3885 bool ro_read = MLX5_CAP_GEN(mdev, relaxed_ordering_read); 3886 3887 MLX5_SET(mkc, mkc, relaxed_ordering_read, ro_pci_enable && ro_read); 3888 MLX5_SET(mkc, mkc, relaxed_ordering_write, ro_pci_enable && ro_write); 3889 } 3890 3891 static int 3892 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn, 3893 struct mlx5_core_mkey *mkey) 3894 { 3895 struct ifnet *ifp = priv->ifp; 3896 struct mlx5_core_dev *mdev = priv->mdev; 3897 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 3898 void *mkc; 3899 u32 *in; 3900 int err; 3901 3902 in = mlx5_vzalloc(inlen); 3903 if (in == NULL) { 3904 mlx5_en_err(ifp, "failed to allocate inbox\n"); 3905 return (-ENOMEM); 3906 } 3907 3908 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 3909 MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA); 3910 MLX5_SET(mkc, mkc, umr_en, 1); /* used by HW TLS */ 3911 MLX5_SET(mkc, mkc, lw, 1); 3912 MLX5_SET(mkc, mkc, lr, 1); 3913 mlx5e_mkey_set_relaxed_ordering(mdev, mkc); 3914 MLX5_SET(mkc, mkc, pd, pdn); 3915 MLX5_SET(mkc, mkc, length64, 1); 3916 MLX5_SET(mkc, mkc, qpn, 0xffffff); 3917 3918 err = mlx5_core_create_mkey(mdev, mkey, in, inlen); 3919 if (err) 3920 mlx5_en_err(ifp, "mlx5_core_create_mkey failed, %d\n", 3921 err); 3922 3923 kvfree(in); 3924 return (err); 3925 } 3926 3927 static const char *mlx5e_vport_stats_desc[] = { 3928 MLX5E_VPORT_STATS(MLX5E_STATS_DESC) 3929 }; 3930 3931 static const char *mlx5e_pport_stats_desc[] = { 3932 MLX5E_PPORT_STATS(MLX5E_STATS_DESC) 3933 }; 3934 3935 static int 3936 mlx5e_priv_static_init(struct mlx5e_priv *priv, struct mlx5_core_dev *mdev, 3937 const uint32_t channels) 3938 { 3939 uint32_t x; 3940 int err; 3941 3942 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF); 3943 sx_init(&priv->state_lock, "mlx5state"); 3944 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0); 3945 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock); 3946 for (x = 0; x != channels; x++) 3947 mlx5e_chan_static_init(priv, &priv->channel[x], x); 3948 3949 for (x = 0; x != channels; x++) { 3950 err = mlx5_alloc_bfreg(mdev, &priv->channel[x].bfreg, false, false); 3951 if (err) 3952 goto err_alloc_bfreg; 3953 } 3954 return (0); 3955 3956 err_alloc_bfreg: 3957 while (x--) 3958 mlx5_free_bfreg(mdev, &priv->channel[x].bfreg); 3959 3960 for (x = 0; x != channels; x++) 3961 mlx5e_chan_static_destroy(&priv->channel[x]); 3962 callout_drain(&priv->watchdog); 3963 mtx_destroy(&priv->async_events_mtx); 3964 sx_destroy(&priv->state_lock); 3965 return (err); 3966 } 3967 3968 static void 3969 mlx5e_priv_static_destroy(struct mlx5e_priv *priv, struct mlx5_core_dev *mdev, 3970 const uint32_t channels) 3971 { 3972 uint32_t x; 3973 3974 for (x = 0; x != channels; x++) 3975 mlx5_free_bfreg(mdev, &priv->channel[x].bfreg); 3976 for (x = 0; x != channels; x++) 3977 mlx5e_chan_static_destroy(&priv->channel[x]); 3978 callout_drain(&priv->watchdog); 3979 mtx_destroy(&priv->async_events_mtx); 3980 sx_destroy(&priv->state_lock); 3981 } 3982 3983 static int 3984 sysctl_firmware(SYSCTL_HANDLER_ARGS) 3985 { 3986 /* 3987 * %d.%d%.d the string format. 3988 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536. 3989 * We need at most 5 chars to store that. 3990 * It also has: two "." and NULL at the end, which means we need 18 3991 * (5*3 + 3) chars at most. 3992 */ 3993 char fw[18]; 3994 struct mlx5e_priv *priv = arg1; 3995 int error; 3996 3997 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev), 3998 fw_rev_sub(priv->mdev)); 3999 error = sysctl_handle_string(oidp, fw, sizeof(fw), req); 4000 return (error); 4001 } 4002 4003 static void 4004 mlx5e_disable_tx_dma(struct mlx5e_channel *ch) 4005 { 4006 int i; 4007 4008 for (i = 0; i < ch->priv->num_tc; i++) 4009 mlx5e_drain_sq(&ch->sq[i]); 4010 } 4011 4012 static void 4013 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq) 4014 { 4015 4016 sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP); 4017 sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8); 4018 mlx5e_tx_notify_hw(sq, true); 4019 } 4020 4021 void 4022 mlx5e_resume_sq(struct mlx5e_sq *sq) 4023 { 4024 int err; 4025 4026 /* check if already enabled */ 4027 if (READ_ONCE(sq->running) != 0) 4028 return; 4029 4030 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR, 4031 MLX5_SQC_STATE_RST); 4032 if (err != 0) { 4033 mlx5_en_err(sq->ifp, 4034 "mlx5e_modify_sq() from ERR to RST failed: %d\n", err); 4035 } 4036 4037 sq->cc = 0; 4038 sq->pc = 0; 4039 4040 /* reset doorbell prior to moving from RST to RDY */ 4041 mlx5e_reset_sq_doorbell_record(sq); 4042 4043 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, 4044 MLX5_SQC_STATE_RDY); 4045 if (err != 0) { 4046 mlx5_en_err(sq->ifp, 4047 "mlx5e_modify_sq() from RST to RDY failed: %d\n", err); 4048 } 4049 4050 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL; 4051 WRITE_ONCE(sq->running, 1); 4052 } 4053 4054 static void 4055 mlx5e_enable_tx_dma(struct mlx5e_channel *ch) 4056 { 4057 int i; 4058 4059 for (i = 0; i < ch->priv->num_tc; i++) 4060 mlx5e_resume_sq(&ch->sq[i]); 4061 } 4062 4063 static void 4064 mlx5e_disable_rx_dma(struct mlx5e_channel *ch) 4065 { 4066 struct mlx5e_rq *rq = &ch->rq; 4067 struct epoch_tracker et; 4068 int err; 4069 4070 mtx_lock(&rq->mtx); 4071 rq->enabled = 0; 4072 callout_stop(&rq->watchdog); 4073 mtx_unlock(&rq->mtx); 4074 4075 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 4076 if (err != 0) { 4077 mlx5_en_err(rq->ifp, 4078 "mlx5e_modify_rq() from RDY to RST failed: %d\n", err); 4079 } 4080 4081 while (!mlx5_wq_ll_is_empty(&rq->wq)) { 4082 msleep(1); 4083 NET_EPOCH_ENTER(et); 4084 rq->cq.mcq.comp(&rq->cq.mcq, NULL); 4085 NET_EPOCH_EXIT(et); 4086 } 4087 4088 /* 4089 * Transitioning into RST state will allow the FW to track less ERR state queues, 4090 * thus reducing the recv queue flushing time 4091 */ 4092 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST); 4093 if (err != 0) { 4094 mlx5_en_err(rq->ifp, 4095 "mlx5e_modify_rq() from ERR to RST failed: %d\n", err); 4096 } 4097 } 4098 4099 static void 4100 mlx5e_enable_rx_dma(struct mlx5e_channel *ch) 4101 { 4102 struct mlx5e_rq *rq = &ch->rq; 4103 struct epoch_tracker et; 4104 int err; 4105 4106 rq->wq.wqe_ctr = 0; 4107 mlx5_wq_ll_update_db_record(&rq->wq); 4108 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 4109 if (err != 0) { 4110 mlx5_en_err(rq->ifp, 4111 "mlx5e_modify_rq() from RST to RDY failed: %d\n", err); 4112 } 4113 4114 rq->enabled = 1; 4115 4116 NET_EPOCH_ENTER(et); 4117 rq->cq.mcq.comp(&rq->cq.mcq, NULL); 4118 NET_EPOCH_EXIT(et); 4119 } 4120 4121 void 4122 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value) 4123 { 4124 int i; 4125 4126 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 4127 return; 4128 4129 for (i = 0; i < priv->params.num_channels; i++) { 4130 if (value) 4131 mlx5e_disable_tx_dma(&priv->channel[i]); 4132 else 4133 mlx5e_enable_tx_dma(&priv->channel[i]); 4134 } 4135 } 4136 4137 void 4138 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value) 4139 { 4140 int i; 4141 4142 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 4143 return; 4144 4145 for (i = 0; i < priv->params.num_channels; i++) { 4146 if (value) 4147 mlx5e_disable_rx_dma(&priv->channel[i]); 4148 else 4149 mlx5e_enable_rx_dma(&priv->channel[i]); 4150 } 4151 } 4152 4153 static void 4154 mlx5e_add_hw_stats(struct mlx5e_priv *priv) 4155 { 4156 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 4157 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 4158 priv, 0, sysctl_firmware, "A", "HCA firmware version"); 4159 4160 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 4161 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0, 4162 "Board ID"); 4163 } 4164 4165 static int 4166 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS) 4167 { 4168 struct mlx5e_priv *priv = arg1; 4169 uint8_t temp[MLX5E_MAX_PRIORITY]; 4170 uint32_t tx_pfc; 4171 int err; 4172 int i; 4173 4174 PRIV_LOCK(priv); 4175 4176 tx_pfc = priv->params.tx_priority_flow_control; 4177 4178 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) 4179 temp[i] = (tx_pfc >> i) & 1; 4180 4181 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY); 4182 if (err || !req->newptr) 4183 goto done; 4184 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY); 4185 if (err) 4186 goto done; 4187 4188 priv->params.tx_priority_flow_control = 0; 4189 4190 /* range check input value */ 4191 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) { 4192 if (temp[i] > 1) { 4193 err = ERANGE; 4194 goto done; 4195 } 4196 priv->params.tx_priority_flow_control |= (temp[i] << i); 4197 } 4198 4199 /* check if update is required */ 4200 if (tx_pfc != priv->params.tx_priority_flow_control) 4201 err = -mlx5e_set_port_pfc(priv); 4202 done: 4203 if (err != 0) 4204 priv->params.tx_priority_flow_control= tx_pfc; 4205 PRIV_UNLOCK(priv); 4206 4207 return (err); 4208 } 4209 4210 static int 4211 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS) 4212 { 4213 struct mlx5e_priv *priv = arg1; 4214 uint8_t temp[MLX5E_MAX_PRIORITY]; 4215 uint32_t rx_pfc; 4216 int err; 4217 int i; 4218 4219 PRIV_LOCK(priv); 4220 4221 rx_pfc = priv->params.rx_priority_flow_control; 4222 4223 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) 4224 temp[i] = (rx_pfc >> i) & 1; 4225 4226 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY); 4227 if (err || !req->newptr) 4228 goto done; 4229 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY); 4230 if (err) 4231 goto done; 4232 4233 priv->params.rx_priority_flow_control = 0; 4234 4235 /* range check input value */ 4236 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) { 4237 if (temp[i] > 1) { 4238 err = ERANGE; 4239 goto done; 4240 } 4241 priv->params.rx_priority_flow_control |= (temp[i] << i); 4242 } 4243 4244 /* check if update is required */ 4245 if (rx_pfc != priv->params.rx_priority_flow_control) { 4246 err = -mlx5e_set_port_pfc(priv); 4247 if (err == 0 && priv->sw_is_port_buf_owner) 4248 err = mlx5e_update_buf_lossy(priv); 4249 } 4250 done: 4251 if (err != 0) 4252 priv->params.rx_priority_flow_control= rx_pfc; 4253 PRIV_UNLOCK(priv); 4254 4255 return (err); 4256 } 4257 4258 static void 4259 mlx5e_setup_pauseframes(struct mlx5e_priv *priv) 4260 { 4261 int error; 4262 4263 /* enable pauseframes by default */ 4264 priv->params.tx_pauseframe_control = 1; 4265 priv->params.rx_pauseframe_control = 1; 4266 4267 /* disable ports flow control, PFC, by default */ 4268 priv->params.tx_priority_flow_control = 0; 4269 priv->params.rx_priority_flow_control = 0; 4270 4271 /* register pauseframe SYSCTLs */ 4272 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4273 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN, 4274 &priv->params.tx_pauseframe_control, 0, 4275 "Set to enable TX pause frames. Clear to disable."); 4276 4277 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4278 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN, 4279 &priv->params.rx_pauseframe_control, 0, 4280 "Set to enable RX pause frames. Clear to disable."); 4281 4282 /* register priority flow control, PFC, SYSCTLs */ 4283 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4284 OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN | 4285 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU", 4286 "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable."); 4287 4288 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4289 OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN | 4290 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU", 4291 "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable."); 4292 4293 PRIV_LOCK(priv); 4294 4295 /* range check */ 4296 priv->params.tx_pauseframe_control = 4297 priv->params.tx_pauseframe_control ? 1 : 0; 4298 priv->params.rx_pauseframe_control = 4299 priv->params.rx_pauseframe_control ? 1 : 0; 4300 4301 /* update firmware */ 4302 error = mlx5e_set_port_pause_and_pfc(priv); 4303 if (error == -EINVAL) { 4304 mlx5_en_err(priv->ifp, 4305 "Global pauseframes must be disabled before enabling PFC.\n"); 4306 priv->params.rx_priority_flow_control = 0; 4307 priv->params.tx_priority_flow_control = 0; 4308 4309 /* update firmware */ 4310 (void) mlx5e_set_port_pause_and_pfc(priv); 4311 } 4312 PRIV_UNLOCK(priv); 4313 } 4314 4315 static int 4316 mlx5e_ul_snd_tag_alloc(struct ifnet *ifp, 4317 union if_snd_tag_alloc_params *params, 4318 struct m_snd_tag **ppmt) 4319 { 4320 struct mlx5e_priv *priv; 4321 struct mlx5e_channel *pch; 4322 4323 priv = ifp->if_softc; 4324 4325 if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) { 4326 return (EOPNOTSUPP); 4327 } else { 4328 /* keep this code synced with mlx5e_select_queue() */ 4329 u32 ch = priv->params.num_channels; 4330 #ifdef RSS 4331 u32 temp; 4332 4333 if (rss_hash2bucket(params->hdr.flowid, 4334 params->hdr.flowtype, &temp) == 0) 4335 ch = temp % ch; 4336 else 4337 #endif 4338 ch = (params->hdr.flowid % 128) % ch; 4339 4340 /* 4341 * NOTE: The channels array is only freed at detach 4342 * and it safe to return a pointer to the send tag 4343 * inside the channels structure as long as we 4344 * reference the priv. 4345 */ 4346 pch = priv->channel + ch; 4347 4348 /* check if send queue is not running */ 4349 if (unlikely(pch->sq[0].running == 0)) 4350 return (ENXIO); 4351 m_snd_tag_ref(&pch->tag); 4352 *ppmt = &pch->tag; 4353 return (0); 4354 } 4355 } 4356 4357 static int 4358 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params) 4359 { 4360 struct mlx5e_channel *pch = 4361 container_of(pmt, struct mlx5e_channel, tag); 4362 4363 params->unlimited.max_rate = -1ULL; 4364 params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]); 4365 return (0); 4366 } 4367 4368 static void 4369 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt) 4370 { 4371 struct mlx5e_channel *pch = 4372 container_of(pmt, struct mlx5e_channel, tag); 4373 4374 complete(&pch->completion); 4375 } 4376 4377 static int 4378 mlx5e_snd_tag_alloc(struct ifnet *ifp, 4379 union if_snd_tag_alloc_params *params, 4380 struct m_snd_tag **ppmt) 4381 { 4382 4383 switch (params->hdr.type) { 4384 #ifdef RATELIMIT 4385 case IF_SND_TAG_TYPE_RATE_LIMIT: 4386 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt)); 4387 #ifdef KERN_TLS 4388 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT: 4389 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt)); 4390 #endif 4391 #endif 4392 case IF_SND_TAG_TYPE_UNLIMITED: 4393 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt)); 4394 #ifdef KERN_TLS 4395 case IF_SND_TAG_TYPE_TLS: 4396 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt)); 4397 case IF_SND_TAG_TYPE_TLS_RX: 4398 return (mlx5e_tls_rx_snd_tag_alloc(ifp, params, ppmt)); 4399 #endif 4400 default: 4401 return (EOPNOTSUPP); 4402 } 4403 } 4404 4405 #ifdef RATELIMIT 4406 #define NUM_HDWR_RATES_MLX 13 4407 static const uint64_t adapter_rates_mlx[NUM_HDWR_RATES_MLX] = { 4408 135375, /* 1,083,000 */ 4409 180500, /* 1,444,000 */ 4410 270750, /* 2,166,000 */ 4411 361000, /* 2,888,000 */ 4412 541500, /* 4,332,000 */ 4413 721875, /* 5,775,000 */ 4414 1082875, /* 8,663,000 */ 4415 1443875, /* 11,551,000 */ 4416 2165750, /* 17,326,000 */ 4417 2887750, /* 23,102,000 */ 4418 4331625, /* 34,653,000 */ 4419 5775500, /* 46,204,000 */ 4420 8663125 /* 69,305,000 */ 4421 }; 4422 4423 static void 4424 mlx5e_ratelimit_query(struct ifnet *ifp __unused, struct if_ratelimit_query_results *q) 4425 { 4426 /* 4427 * This function needs updating by the driver maintainer! 4428 * For the MLX card there are currently (ConectX-4?) 13 4429 * pre-set rates and others i.e. ConnectX-5, 6, 7?? 4430 * 4431 * This will change based on later adapters 4432 * and this code should be updated to look at ifp 4433 * and figure out the specific adapter type 4434 * settings i.e. how many rates as well 4435 * as if they are fixed (as is shown here) or 4436 * if they are dynamic (example chelsio t4). Also if there 4437 * is a maximum number of flows that the adapter 4438 * can handle that too needs to be updated in 4439 * the max_flows field. 4440 */ 4441 q->rate_table = adapter_rates_mlx; 4442 q->flags = RT_IS_FIXED_TABLE; 4443 q->max_flows = 0; /* mlx has no limit */ 4444 q->number_of_rates = NUM_HDWR_RATES_MLX; 4445 q->min_segment_burst = 1; 4446 } 4447 #endif 4448 4449 static void 4450 mlx5e_ifm_add(struct mlx5e_priv *priv, int type) 4451 { 4452 ifmedia_add(&priv->media, type | IFM_ETHER, 0, NULL); 4453 ifmedia_add(&priv->media, type | IFM_ETHER | 4454 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 4455 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_RXPAUSE, 0, NULL); 4456 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_TXPAUSE, 0, NULL); 4457 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX, 0, NULL); 4458 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX | 4459 IFM_ETH_RXPAUSE, 0, NULL); 4460 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX | 4461 IFM_ETH_TXPAUSE, 0, NULL); 4462 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX | 4463 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 4464 } 4465 4466 static void * 4467 mlx5e_create_ifp(struct mlx5_core_dev *mdev) 4468 { 4469 struct ifnet *ifp; 4470 struct mlx5e_priv *priv; 4471 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4); 4472 struct sysctl_oid_list *child; 4473 int ncv = mdev->priv.eq_table.num_comp_vectors; 4474 char unit[16]; 4475 struct pfil_head_args pa; 4476 int err; 4477 u32 eth_proto_cap; 4478 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 4479 bool ext; 4480 struct media media_entry = {}; 4481 4482 if (mlx5e_check_required_hca_cap(mdev)) { 4483 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n"); 4484 return (NULL); 4485 } 4486 4487 /* 4488 * Try to allocate the priv and make room for worst-case 4489 * number of channel structures: 4490 */ 4491 priv = malloc_domainset(sizeof(*priv) + 4492 (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors), 4493 M_MLX5EN, mlx5_dev_domainset(mdev), M_WAITOK | M_ZERO); 4494 4495 ifp = priv->ifp = if_alloc_dev(IFT_ETHER, mdev->pdev->dev.bsddev); 4496 if (ifp == NULL) { 4497 mlx5_core_err(mdev, "if_alloc() failed\n"); 4498 goto err_free_priv; 4499 } 4500 /* setup all static fields */ 4501 if (mlx5e_priv_static_init(priv, mdev, mdev->priv.eq_table.num_comp_vectors)) { 4502 mlx5_core_err(mdev, "mlx5e_priv_static_init() failed\n"); 4503 goto err_free_ifp; 4504 } 4505 4506 ifp->if_softc = priv; 4507 if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev)); 4508 ifp->if_mtu = ETHERMTU; 4509 ifp->if_init = mlx5e_open; 4510 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 4511 IFF_KNOWSEPOCH; 4512 ifp->if_ioctl = mlx5e_ioctl; 4513 ifp->if_transmit = mlx5e_xmit; 4514 ifp->if_qflush = if_qflush; 4515 ifp->if_get_counter = mlx5e_get_counter; 4516 ifp->if_snd.ifq_maxlen = ifqmaxlen; 4517 /* 4518 * Set driver features 4519 */ 4520 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6; 4521 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 4522 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER; 4523 ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU; 4524 ifp->if_capabilities |= IFCAP_LRO; 4525 ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO; 4526 ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP; 4527 ifp->if_capabilities |= IFCAP_MEXTPG; 4528 ifp->if_capabilities |= IFCAP_TXTLS4 | IFCAP_TXTLS6; 4529 #ifdef RATELIMIT 4530 ifp->if_capabilities |= IFCAP_TXRTLMT | IFCAP_TXTLS_RTLMT; 4531 #endif 4532 ifp->if_capabilities |= IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO; 4533 ifp->if_snd_tag_alloc = mlx5e_snd_tag_alloc; 4534 #ifdef RATELIMIT 4535 ifp->if_ratelimit_query = mlx5e_ratelimit_query; 4536 #endif 4537 /* set TSO limits so that we don't have to drop TX packets */ 4538 ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 4539 ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */; 4540 ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE; 4541 4542 ifp->if_capenable = ifp->if_capabilities; 4543 ifp->if_hwassist = 0; 4544 if (ifp->if_capenable & IFCAP_TSO) 4545 ifp->if_hwassist |= CSUM_TSO; 4546 if (ifp->if_capenable & IFCAP_TXCSUM) 4547 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP); 4548 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6) 4549 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 4550 if (ifp->if_capabilities & IFCAP_VXLAN_HWCSUM) 4551 ifp->if_hwassist |= CSUM_INNER_IP6_UDP | CSUM_INNER_IP6_TCP | 4552 CSUM_INNER_IP | CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP | 4553 CSUM_ENCAP_VXLAN; 4554 if (ifp->if_capabilities & IFCAP_VXLAN_HWTSO) 4555 ifp->if_hwassist |= CSUM_INNER_IP6_TSO | CSUM_INNER_IP_TSO; 4556 4557 /* ifnet sysctl tree */ 4558 sysctl_ctx_init(&priv->sysctl_ctx); 4559 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev), 4560 OID_AUTO, ifp->if_dname, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 4561 "MLX5 ethernet - interface name"); 4562 if (priv->sysctl_ifnet == NULL) { 4563 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4564 goto err_free_sysctl; 4565 } 4566 snprintf(unit, sizeof(unit), "%d", ifp->if_dunit); 4567 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4568 OID_AUTO, unit, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 4569 "MLX5 ethernet - interface unit"); 4570 if (priv->sysctl_ifnet == NULL) { 4571 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4572 goto err_free_sysctl; 4573 } 4574 4575 /* HW sysctl tree */ 4576 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev)); 4577 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child, 4578 OID_AUTO, "hw", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 4579 "MLX5 ethernet dev hw"); 4580 if (priv->sysctl_hw == NULL) { 4581 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4582 goto err_free_sysctl; 4583 } 4584 4585 err = mlx5e_build_ifp_priv(mdev, priv, ncv); 4586 if (err) { 4587 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err); 4588 goto err_free_sysctl; 4589 } 4590 4591 /* reuse mlx5core's watchdog workqueue */ 4592 priv->wq = mdev->priv.health.wq_watchdog; 4593 4594 err = mlx5_core_alloc_pd(mdev, &priv->pdn, 0); 4595 if (err) { 4596 mlx5_en_err(ifp, "mlx5_core_alloc_pd failed, %d\n", err); 4597 goto err_free_wq; 4598 } 4599 err = mlx5_alloc_transport_domain(mdev, &priv->tdn, 0); 4600 if (err) { 4601 mlx5_en_err(ifp, 4602 "mlx5_alloc_transport_domain failed, %d\n", err); 4603 goto err_dealloc_pd; 4604 } 4605 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr); 4606 if (err) { 4607 mlx5_en_err(ifp, "mlx5e_create_mkey failed, %d\n", err); 4608 goto err_dealloc_transport_domain; 4609 } 4610 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr); 4611 4612 /* check if we should generate a random MAC address */ 4613 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 && 4614 is_zero_ether_addr(dev_addr)) { 4615 random_ether_addr(dev_addr); 4616 mlx5_en_err(ifp, "Assigned random MAC address\n"); 4617 } 4618 4619 err = mlx5e_rl_init(priv); 4620 if (err) { 4621 mlx5_en_err(ifp, "mlx5e_rl_init failed, %d\n", err); 4622 goto err_create_mkey; 4623 } 4624 4625 err = mlx5e_tls_init(priv); 4626 if (err) { 4627 if_printf(ifp, "%s: mlx5e_tls_init failed\n", __func__); 4628 goto err_rl_init; 4629 } 4630 4631 err = mlx5e_open_drop_rq(priv, &priv->drop_rq); 4632 if (err) { 4633 if_printf(ifp, "%s: mlx5e_open_drop_rq failed (%d)\n", __func__, err); 4634 goto err_tls_init; 4635 } 4636 4637 err = mlx5e_open_rqts(priv); 4638 if (err) { 4639 if_printf(ifp, "%s: mlx5e_open_rqts failed (%d)\n", __func__, err); 4640 goto err_open_drop_rq; 4641 } 4642 4643 err = mlx5e_open_tirs(priv); 4644 if (err) { 4645 mlx5_en_err(ifp, "mlx5e_open_tirs() failed, %d\n", err); 4646 goto err_open_rqts; 4647 } 4648 4649 err = mlx5e_open_flow_tables(priv); 4650 if (err) { 4651 if_printf(ifp, "%s: mlx5e_open_flow_tables failed (%d)\n", __func__, err); 4652 goto err_open_tirs; 4653 } 4654 4655 err = mlx5e_tls_rx_init(priv); 4656 if (err) { 4657 if_printf(ifp, "%s: mlx5e_tls_rx_init() failed, %d\n", __func__, err); 4658 goto err_open_flow_tables; 4659 } 4660 4661 /* set default MTU */ 4662 mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu); 4663 4664 /* Set default media status */ 4665 priv->media_status_last = IFM_AVALID; 4666 priv->media_active_last = IFM_ETHER | IFM_AUTO | IFM_FDX; 4667 4668 /* setup default pauseframes configuration */ 4669 mlx5e_setup_pauseframes(priv); 4670 4671 /* Setup supported medias */ 4672 if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) { 4673 ext = MLX5_CAP_PCAM_FEATURE(mdev, 4674 ptys_extended_ethernet); 4675 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 4676 eth_proto_capability); 4677 } else { 4678 ext = false; 4679 eth_proto_cap = 0; 4680 mlx5_en_err(ifp, "Query port media capability failed, %d\n", err); 4681 } 4682 4683 ifmedia_init(&priv->media, IFM_IMASK, 4684 mlx5e_media_change, mlx5e_media_status); 4685 4686 if (ext) { 4687 for (unsigned i = 0; i != MLX5E_EXT_LINK_SPEEDS_NUMBER; i++) { 4688 /* check if hardware has the right capability */ 4689 if (MLX5E_PROT_MASK(i) & ~eth_proto_cap) 4690 continue; 4691 for (unsigned j = 0; j != MLX5E_CABLE_TYPE_NUMBER; j++) { 4692 media_entry = mlx5e_ext_mode_table[i][j]; 4693 if (media_entry.subtype == 0) 4694 continue; 4695 /* check if this subtype was already added */ 4696 for (unsigned k = 0; k != i; k++) { 4697 /* check if hardware has the right capability */ 4698 if (MLX5E_PROT_MASK(k) & ~eth_proto_cap) 4699 continue; 4700 for (unsigned m = 0; m != MLX5E_CABLE_TYPE_NUMBER; m++) { 4701 if (media_entry.subtype == mlx5e_ext_mode_table[k][m].subtype) 4702 goto skip_ext_media; 4703 } 4704 } 4705 mlx5e_ifm_add(priv, media_entry.subtype); 4706 skip_ext_media:; 4707 } 4708 } 4709 } else { 4710 for (unsigned i = 0; i != MLX5E_LINK_SPEEDS_NUMBER; i++) { 4711 media_entry = mlx5e_mode_table[i]; 4712 if (media_entry.subtype == 0) 4713 continue; 4714 if (MLX5E_PROT_MASK(i) & ~eth_proto_cap) 4715 continue; 4716 /* check if this subtype was already added */ 4717 for (unsigned k = 0; k != i; k++) { 4718 if (media_entry.subtype == mlx5e_mode_table[k].subtype) 4719 goto skip_media; 4720 } 4721 mlx5e_ifm_add(priv, media_entry.subtype); 4722 4723 /* NOTE: 10G ER and LR shares the same entry */ 4724 if (media_entry.subtype == IFM_10G_ER) 4725 mlx5e_ifm_add(priv, IFM_10G_LR); 4726 skip_media:; 4727 } 4728 } 4729 4730 mlx5e_ifm_add(priv, IFM_AUTO); 4731 4732 /* Set autoselect by default */ 4733 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX | 4734 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE); 4735 4736 DEBUGNET_SET(ifp, mlx5_en); 4737 4738 ether_ifattach(ifp, dev_addr); 4739 4740 /* Register for VLAN events */ 4741 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config, 4742 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST); 4743 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig, 4744 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST); 4745 4746 /* Register for VxLAN events */ 4747 priv->vxlan_start = EVENTHANDLER_REGISTER(vxlan_start, 4748 mlx5e_vxlan_start, priv, EVENTHANDLER_PRI_ANY); 4749 priv->vxlan_stop = EVENTHANDLER_REGISTER(vxlan_stop, 4750 mlx5e_vxlan_stop, priv, EVENTHANDLER_PRI_ANY); 4751 4752 /* Link is down by default */ 4753 if_link_state_change(ifp, LINK_STATE_DOWN); 4754 4755 mlx5e_enable_async_events(priv); 4756 4757 mlx5e_add_hw_stats(priv); 4758 4759 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4760 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM, 4761 priv->stats.vport.arg); 4762 4763 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4764 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM, 4765 priv->stats.pport.arg); 4766 4767 mlx5e_create_ethtool(priv); 4768 4769 mtx_lock(&priv->async_events_mtx); 4770 mlx5e_update_stats(priv); 4771 mtx_unlock(&priv->async_events_mtx); 4772 4773 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4774 OID_AUTO, "rx_clbr_done", CTLFLAG_RD, 4775 &priv->clbr_done, 0, 4776 "RX timestamps calibration state"); 4777 callout_init(&priv->tstmp_clbr, 1); 4778 mlx5e_reset_calibration_callout(priv); 4779 4780 pa.pa_version = PFIL_VERSION; 4781 pa.pa_flags = PFIL_IN; 4782 pa.pa_type = PFIL_TYPE_ETHERNET; 4783 pa.pa_headname = ifp->if_xname; 4784 priv->pfil = pfil_head_register(&pa); 4785 4786 PRIV_LOCK(priv); 4787 err = mlx5e_open_flow_rules(priv); 4788 if (err) { 4789 mlx5_en_err(ifp, 4790 "mlx5e_open_flow_rules() failed, %d (ignored)\n", err); 4791 } 4792 PRIV_UNLOCK(priv); 4793 4794 return (priv); 4795 4796 err_open_flow_tables: 4797 mlx5e_close_flow_tables(priv); 4798 4799 err_open_tirs: 4800 mlx5e_close_tirs(priv); 4801 4802 err_open_rqts: 4803 mlx5e_close_rqts(priv); 4804 4805 err_open_drop_rq: 4806 mlx5e_close_drop_rq(&priv->drop_rq); 4807 4808 err_tls_init: 4809 mlx5e_tls_cleanup(priv); 4810 4811 err_rl_init: 4812 mlx5e_rl_cleanup(priv); 4813 4814 err_create_mkey: 4815 mlx5_core_destroy_mkey(priv->mdev, &priv->mr); 4816 4817 err_dealloc_transport_domain: 4818 mlx5_dealloc_transport_domain(mdev, priv->tdn, 0); 4819 4820 err_dealloc_pd: 4821 mlx5_core_dealloc_pd(mdev, priv->pdn, 0); 4822 4823 err_free_wq: 4824 flush_workqueue(priv->wq); 4825 4826 err_free_sysctl: 4827 sysctl_ctx_free(&priv->sysctl_ctx); 4828 if (priv->sysctl_debug) 4829 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx); 4830 mlx5e_priv_static_destroy(priv, mdev, mdev->priv.eq_table.num_comp_vectors); 4831 4832 err_free_ifp: 4833 if_free(ifp); 4834 4835 err_free_priv: 4836 free(priv, M_MLX5EN); 4837 return (NULL); 4838 } 4839 4840 static void 4841 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv) 4842 { 4843 struct mlx5e_priv *priv = vpriv; 4844 struct ifnet *ifp = priv->ifp; 4845 4846 /* don't allow more IOCTLs */ 4847 priv->gone = 1; 4848 4849 /* XXX wait a bit to allow IOCTL handlers to complete */ 4850 pause("W", hz); 4851 4852 #ifdef RATELIMIT 4853 /* 4854 * The kernel can have reference(s) via the m_snd_tag's into 4855 * the ratelimit channels, and these must go away before 4856 * detaching: 4857 */ 4858 while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) { 4859 mlx5_en_err(priv->ifp, 4860 "Waiting for all ratelimit connections to terminate\n"); 4861 pause("W", hz); 4862 } 4863 #endif 4864 4865 #ifdef KERN_TLS 4866 /* wait for all TLS tags to get freed */ 4867 while (priv->tls.init != 0 && 4868 uma_zone_get_cur(priv->tls.zone) != 0) { 4869 mlx5_en_err(priv->ifp, 4870 "Waiting for all TLS connections to terminate\n"); 4871 pause("W", hz); 4872 } 4873 4874 /* wait for all TLS RX tags to get freed */ 4875 while (priv->tls_rx.init != 0 && 4876 uma_zone_get_cur(priv->tls_rx.zone) != 0) { 4877 mlx5_en_err(priv->ifp, 4878 "Waiting for all TLS RX connections to terminate\n"); 4879 pause("W", hz); 4880 } 4881 #endif 4882 /* wait for all unlimited send tags to complete */ 4883 mlx5e_priv_wait_for_completion(priv, mdev->priv.eq_table.num_comp_vectors); 4884 4885 /* stop watchdog timer */ 4886 callout_drain(&priv->watchdog); 4887 4888 callout_drain(&priv->tstmp_clbr); 4889 4890 if (priv->vlan_attach != NULL) 4891 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach); 4892 if (priv->vlan_detach != NULL) 4893 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach); 4894 if (priv->vxlan_start != NULL) 4895 EVENTHANDLER_DEREGISTER(vxlan_start, priv->vxlan_start); 4896 if (priv->vxlan_stop != NULL) 4897 EVENTHANDLER_DEREGISTER(vxlan_stop, priv->vxlan_stop); 4898 4899 /* make sure device gets closed */ 4900 PRIV_LOCK(priv); 4901 mlx5e_close_locked(ifp); 4902 mlx5e_close_flow_rules(priv); 4903 PRIV_UNLOCK(priv); 4904 4905 /* deregister pfil */ 4906 if (priv->pfil != NULL) { 4907 pfil_head_unregister(priv->pfil); 4908 priv->pfil = NULL; 4909 } 4910 4911 /* unregister device */ 4912 ifmedia_removeall(&priv->media); 4913 ether_ifdetach(ifp); 4914 4915 mlx5e_tls_rx_cleanup(priv); 4916 mlx5e_close_flow_tables(priv); 4917 mlx5e_close_tirs(priv); 4918 mlx5e_close_rqts(priv); 4919 mlx5e_close_drop_rq(&priv->drop_rq); 4920 mlx5e_tls_cleanup(priv); 4921 mlx5e_rl_cleanup(priv); 4922 4923 /* destroy all remaining sysctl nodes */ 4924 sysctl_ctx_free(&priv->stats.vport.ctx); 4925 sysctl_ctx_free(&priv->stats.pport.ctx); 4926 if (priv->sysctl_debug) 4927 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx); 4928 sysctl_ctx_free(&priv->sysctl_ctx); 4929 4930 mlx5_core_destroy_mkey(priv->mdev, &priv->mr); 4931 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn, 0); 4932 mlx5_core_dealloc_pd(priv->mdev, priv->pdn, 0); 4933 mlx5e_disable_async_events(priv); 4934 flush_workqueue(priv->wq); 4935 mlx5e_priv_static_destroy(priv, mdev, mdev->priv.eq_table.num_comp_vectors); 4936 if_free(ifp); 4937 free(priv, M_MLX5EN); 4938 } 4939 4940 #ifdef DEBUGNET 4941 static void 4942 mlx5_en_debugnet_init(struct ifnet *dev, int *nrxr, int *ncl, int *clsize) 4943 { 4944 struct mlx5e_priv *priv = if_getsoftc(dev); 4945 4946 PRIV_LOCK(priv); 4947 *nrxr = priv->params.num_channels; 4948 *ncl = DEBUGNET_MAX_IN_FLIGHT; 4949 *clsize = MLX5E_MAX_RX_BYTES; 4950 PRIV_UNLOCK(priv); 4951 } 4952 4953 static void 4954 mlx5_en_debugnet_event(struct ifnet *dev, enum debugnet_ev event) 4955 { 4956 } 4957 4958 static int 4959 mlx5_en_debugnet_transmit(struct ifnet *dev, struct mbuf *m) 4960 { 4961 struct mlx5e_priv *priv = if_getsoftc(dev); 4962 struct mlx5e_sq *sq; 4963 int err; 4964 4965 if ((if_getdrvflags(dev) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4966 IFF_DRV_RUNNING || (priv->media_status_last & IFM_ACTIVE) == 0) 4967 return (ENOENT); 4968 4969 sq = &priv->channel[0].sq[0]; 4970 4971 if (sq->running == 0) { 4972 m_freem(m); 4973 return (ENOENT); 4974 } 4975 4976 if (mlx5e_sq_xmit(sq, &m) != 0) { 4977 m_freem(m); 4978 err = ENOBUFS; 4979 } else { 4980 err = 0; 4981 } 4982 4983 mlx5e_tx_notify_hw(sq, true); 4984 4985 return (err); 4986 } 4987 4988 static int 4989 mlx5_en_debugnet_poll(struct ifnet *dev, int count) 4990 { 4991 struct mlx5e_priv *priv = if_getsoftc(dev); 4992 4993 if ((if_getdrvflags(dev) & IFF_DRV_RUNNING) == 0 || 4994 (priv->media_status_last & IFM_ACTIVE) == 0) 4995 return (ENOENT); 4996 4997 mlx5_poll_interrupts(priv->mdev); 4998 4999 return (0); 5000 } 5001 #endif /* DEBUGNET */ 5002 5003 static void * 5004 mlx5e_get_ifp(void *vpriv) 5005 { 5006 struct mlx5e_priv *priv = vpriv; 5007 5008 return (priv->ifp); 5009 } 5010 5011 static struct mlx5_interface mlx5e_interface = { 5012 .add = mlx5e_create_ifp, 5013 .remove = mlx5e_destroy_ifp, 5014 .event = mlx5e_async_event, 5015 .protocol = MLX5_INTERFACE_PROTOCOL_ETH, 5016 .get_dev = mlx5e_get_ifp, 5017 }; 5018 5019 void 5020 mlx5e_init(void) 5021 { 5022 mlx5_register_interface(&mlx5e_interface); 5023 } 5024 5025 void 5026 mlx5e_cleanup(void) 5027 { 5028 mlx5_unregister_interface(&mlx5e_interface); 5029 } 5030 5031 module_init_order(mlx5e_init, SI_ORDER_SIXTH); 5032 module_exit_order(mlx5e_cleanup, SI_ORDER_SIXTH); 5033 5034 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1); 5035 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1); 5036 MODULE_VERSION(mlx5en, 1); 5037