1 /*- 2 * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include "opt_kern_tls.h" 29 30 #include "en.h" 31 32 #include <sys/eventhandler.h> 33 #include <sys/sockio.h> 34 #include <machine/atomic.h> 35 36 #include <net/debugnet.h> 37 38 #ifndef ETH_DRIVER_VERSION 39 #define ETH_DRIVER_VERSION "3.5.2" 40 #endif 41 #define DRIVER_RELDATE "September 2019" 42 43 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver " 44 ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n"; 45 46 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs); 47 48 struct mlx5e_channel_param { 49 struct mlx5e_rq_param rq; 50 struct mlx5e_sq_param sq; 51 struct mlx5e_cq_param rx_cq; 52 struct mlx5e_cq_param tx_cq; 53 }; 54 55 struct media { 56 u32 subtype; 57 u64 baudrate; 58 }; 59 60 static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = { 61 62 [MLX5E_1000BASE_CX_SGMII][MLX5E_SGMII] = { 63 .subtype = IFM_1000_CX_SGMII, 64 .baudrate = IF_Mbps(1000ULL), 65 }, 66 [MLX5E_1000BASE_KX][MLX5E_KX] = { 67 .subtype = IFM_1000_KX, 68 .baudrate = IF_Mbps(1000ULL), 69 }, 70 [MLX5E_10GBASE_CX4][MLX5E_CX4] = { 71 .subtype = IFM_10G_CX4, 72 .baudrate = IF_Gbps(10ULL), 73 }, 74 [MLX5E_10GBASE_KX4][MLX5E_KX4] = { 75 .subtype = IFM_10G_KX4, 76 .baudrate = IF_Gbps(10ULL), 77 }, 78 [MLX5E_10GBASE_KR][MLX5E_KR] = { 79 .subtype = IFM_10G_KR, 80 .baudrate = IF_Gbps(10ULL), 81 }, 82 [MLX5E_20GBASE_KR2][MLX5E_KR2] = { 83 .subtype = IFM_20G_KR2, 84 .baudrate = IF_Gbps(20ULL), 85 }, 86 [MLX5E_40GBASE_CR4][MLX5E_CR4] = { 87 .subtype = IFM_40G_CR4, 88 .baudrate = IF_Gbps(40ULL), 89 }, 90 [MLX5E_40GBASE_KR4][MLX5E_KR4] = { 91 .subtype = IFM_40G_KR4, 92 .baudrate = IF_Gbps(40ULL), 93 }, 94 [MLX5E_56GBASE_R4][MLX5E_R] = { 95 .subtype = IFM_56G_R4, 96 .baudrate = IF_Gbps(56ULL), 97 }, 98 [MLX5E_10GBASE_CR][MLX5E_CR1] = { 99 .subtype = IFM_10G_CR1, 100 .baudrate = IF_Gbps(10ULL), 101 }, 102 [MLX5E_10GBASE_SR][MLX5E_SR] = { 103 .subtype = IFM_10G_SR, 104 .baudrate = IF_Gbps(10ULL), 105 }, 106 [MLX5E_10GBASE_ER_LR][MLX5E_ER] = { 107 .subtype = IFM_10G_ER, 108 .baudrate = IF_Gbps(10ULL), 109 }, 110 [MLX5E_10GBASE_ER_LR][MLX5E_LR] = { 111 .subtype = IFM_10G_LR, 112 .baudrate = IF_Gbps(10ULL), 113 }, 114 [MLX5E_40GBASE_SR4][MLX5E_SR4] = { 115 .subtype = IFM_40G_SR4, 116 .baudrate = IF_Gbps(40ULL), 117 }, 118 [MLX5E_40GBASE_LR4_ER4][MLX5E_LR4] = { 119 .subtype = IFM_40G_LR4, 120 .baudrate = IF_Gbps(40ULL), 121 }, 122 [MLX5E_40GBASE_LR4_ER4][MLX5E_ER4] = { 123 .subtype = IFM_40G_ER4, 124 .baudrate = IF_Gbps(40ULL), 125 }, 126 [MLX5E_100GBASE_CR4][MLX5E_CR4] = { 127 .subtype = IFM_100G_CR4, 128 .baudrate = IF_Gbps(100ULL), 129 }, 130 [MLX5E_100GBASE_SR4][MLX5E_SR4] = { 131 .subtype = IFM_100G_SR4, 132 .baudrate = IF_Gbps(100ULL), 133 }, 134 [MLX5E_100GBASE_KR4][MLX5E_KR4] = { 135 .subtype = IFM_100G_KR4, 136 .baudrate = IF_Gbps(100ULL), 137 }, 138 [MLX5E_100GBASE_LR4][MLX5E_LR4] = { 139 .subtype = IFM_100G_LR4, 140 .baudrate = IF_Gbps(100ULL), 141 }, 142 [MLX5E_100BASE_TX][MLX5E_TX] = { 143 .subtype = IFM_100_TX, 144 .baudrate = IF_Mbps(100ULL), 145 }, 146 [MLX5E_1000BASE_T][MLX5E_T] = { 147 .subtype = IFM_1000_T, 148 .baudrate = IF_Mbps(1000ULL), 149 }, 150 [MLX5E_10GBASE_T][MLX5E_T] = { 151 .subtype = IFM_10G_T, 152 .baudrate = IF_Gbps(10ULL), 153 }, 154 [MLX5E_25GBASE_CR][MLX5E_CR] = { 155 .subtype = IFM_25G_CR, 156 .baudrate = IF_Gbps(25ULL), 157 }, 158 [MLX5E_25GBASE_KR][MLX5E_KR] = { 159 .subtype = IFM_25G_KR, 160 .baudrate = IF_Gbps(25ULL), 161 }, 162 [MLX5E_25GBASE_SR][MLX5E_SR] = { 163 .subtype = IFM_25G_SR, 164 .baudrate = IF_Gbps(25ULL), 165 }, 166 [MLX5E_50GBASE_CR2][MLX5E_CR2] = { 167 .subtype = IFM_50G_CR2, 168 .baudrate = IF_Gbps(50ULL), 169 }, 170 [MLX5E_50GBASE_KR2][MLX5E_KR2] = { 171 .subtype = IFM_50G_KR2, 172 .baudrate = IF_Gbps(50ULL), 173 }, 174 [MLX5E_50GBASE_KR4][MLX5E_KR4] = { 175 .subtype = IFM_50G_KR4, 176 .baudrate = IF_Gbps(50ULL), 177 }, 178 }; 179 180 static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = { 181 [MLX5E_SGMII_100M][MLX5E_SGMII] = { 182 .subtype = IFM_100_SGMII, 183 .baudrate = IF_Mbps(100), 184 }, 185 [MLX5E_1000BASE_X_SGMII][MLX5E_KX] = { 186 .subtype = IFM_1000_KX, 187 .baudrate = IF_Mbps(1000), 188 }, 189 [MLX5E_1000BASE_X_SGMII][MLX5E_CX_SGMII] = { 190 .subtype = IFM_1000_CX_SGMII, 191 .baudrate = IF_Mbps(1000), 192 }, 193 [MLX5E_1000BASE_X_SGMII][MLX5E_CX] = { 194 .subtype = IFM_1000_CX, 195 .baudrate = IF_Mbps(1000), 196 }, 197 [MLX5E_1000BASE_X_SGMII][MLX5E_LX] = { 198 .subtype = IFM_1000_LX, 199 .baudrate = IF_Mbps(1000), 200 }, 201 [MLX5E_1000BASE_X_SGMII][MLX5E_SX] = { 202 .subtype = IFM_1000_SX, 203 .baudrate = IF_Mbps(1000), 204 }, 205 [MLX5E_1000BASE_X_SGMII][MLX5E_T] = { 206 .subtype = IFM_1000_T, 207 .baudrate = IF_Mbps(1000), 208 }, 209 [MLX5E_5GBASE_R][MLX5E_T] = { 210 .subtype = IFM_5000_T, 211 .baudrate = IF_Mbps(5000), 212 }, 213 [MLX5E_5GBASE_R][MLX5E_KR] = { 214 .subtype = IFM_5000_KR, 215 .baudrate = IF_Mbps(5000), 216 }, 217 [MLX5E_5GBASE_R][MLX5E_KR1] = { 218 .subtype = IFM_5000_KR1, 219 .baudrate = IF_Mbps(5000), 220 }, 221 [MLX5E_5GBASE_R][MLX5E_KR_S] = { 222 .subtype = IFM_5000_KR_S, 223 .baudrate = IF_Mbps(5000), 224 }, 225 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_ER] = { 226 .subtype = IFM_10G_ER, 227 .baudrate = IF_Gbps(10ULL), 228 }, 229 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_KR] = { 230 .subtype = IFM_10G_KR, 231 .baudrate = IF_Gbps(10ULL), 232 }, 233 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_LR] = { 234 .subtype = IFM_10G_LR, 235 .baudrate = IF_Gbps(10ULL), 236 }, 237 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_SR] = { 238 .subtype = IFM_10G_SR, 239 .baudrate = IF_Gbps(10ULL), 240 }, 241 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_T] = { 242 .subtype = IFM_10G_T, 243 .baudrate = IF_Gbps(10ULL), 244 }, 245 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_AOC] = { 246 .subtype = IFM_10G_AOC, 247 .baudrate = IF_Gbps(10ULL), 248 }, 249 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CR1] = { 250 .subtype = IFM_10G_CR1, 251 .baudrate = IF_Gbps(10ULL), 252 }, 253 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CR4] = { 254 .subtype = IFM_40G_CR4, 255 .baudrate = IF_Gbps(40ULL), 256 }, 257 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_KR4] = { 258 .subtype = IFM_40G_KR4, 259 .baudrate = IF_Gbps(40ULL), 260 }, 261 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_LR4] = { 262 .subtype = IFM_40G_LR4, 263 .baudrate = IF_Gbps(40ULL), 264 }, 265 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_SR4] = { 266 .subtype = IFM_40G_SR4, 267 .baudrate = IF_Gbps(40ULL), 268 }, 269 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_ER4] = { 270 .subtype = IFM_40G_ER4, 271 .baudrate = IF_Gbps(40ULL), 272 }, 273 274 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR] = { 275 .subtype = IFM_25G_CR, 276 .baudrate = IF_Gbps(25ULL), 277 }, 278 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR] = { 279 .subtype = IFM_25G_KR, 280 .baudrate = IF_Gbps(25ULL), 281 }, 282 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_SR] = { 283 .subtype = IFM_25G_SR, 284 .baudrate = IF_Gbps(25ULL), 285 }, 286 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_ACC] = { 287 .subtype = IFM_25G_ACC, 288 .baudrate = IF_Gbps(25ULL), 289 }, 290 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_AOC] = { 291 .subtype = IFM_25G_AOC, 292 .baudrate = IF_Gbps(25ULL), 293 }, 294 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR1] = { 295 .subtype = IFM_25G_CR1, 296 .baudrate = IF_Gbps(25ULL), 297 }, 298 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR_S] = { 299 .subtype = IFM_25G_CR_S, 300 .baudrate = IF_Gbps(25ULL), 301 }, 302 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR1] = { 303 .subtype = IFM_5000_KR1, 304 .baudrate = IF_Gbps(25ULL), 305 }, 306 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR_S] = { 307 .subtype = IFM_25G_KR_S, 308 .baudrate = IF_Gbps(25ULL), 309 }, 310 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_LR] = { 311 .subtype = IFM_25G_LR, 312 .baudrate = IF_Gbps(25ULL), 313 }, 314 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_T] = { 315 .subtype = IFM_25G_T, 316 .baudrate = IF_Gbps(25ULL), 317 }, 318 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CR2] = { 319 .subtype = IFM_50G_CR2, 320 .baudrate = IF_Gbps(50ULL), 321 }, 322 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_KR2] = { 323 .subtype = IFM_50G_KR2, 324 .baudrate = IF_Gbps(50ULL), 325 }, 326 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_KR4] = { 327 .subtype = IFM_50G_KR4, 328 .baudrate = IF_Gbps(50ULL), 329 }, 330 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_SR2] = { 331 .subtype = IFM_50G_SR2, 332 .baudrate = IF_Gbps(50ULL), 333 }, 334 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_LR2] = { 335 .subtype = IFM_50G_LR2, 336 .baudrate = IF_Gbps(50ULL), 337 }, 338 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_LR] = { 339 .subtype = IFM_50G_LR, 340 .baudrate = IF_Gbps(50ULL), 341 }, 342 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_SR] = { 343 .subtype = IFM_50G_SR, 344 .baudrate = IF_Gbps(50ULL), 345 }, 346 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CP] = { 347 .subtype = IFM_50G_CP, 348 .baudrate = IF_Gbps(50ULL), 349 }, 350 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_FR] = { 351 .subtype = IFM_50G_FR, 352 .baudrate = IF_Gbps(50ULL), 353 }, 354 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_KR_PAM4] = { 355 .subtype = IFM_50G_KR_PAM4, 356 .baudrate = IF_Gbps(50ULL), 357 }, 358 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CR4] = { 359 .subtype = IFM_100G_CR4, 360 .baudrate = IF_Gbps(100ULL), 361 }, 362 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_KR4] = { 363 .subtype = IFM_100G_KR4, 364 .baudrate = IF_Gbps(100ULL), 365 }, 366 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_LR4] = { 367 .subtype = IFM_100G_LR4, 368 .baudrate = IF_Gbps(100ULL), 369 }, 370 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_SR4] = { 371 .subtype = IFM_100G_SR4, 372 .baudrate = IF_Gbps(100ULL), 373 }, 374 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_SR2] = { 375 .subtype = IFM_100G_SR2, 376 .baudrate = IF_Gbps(100ULL), 377 }, 378 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CP2] = { 379 .subtype = IFM_100G_CP2, 380 .baudrate = IF_Gbps(100ULL), 381 }, 382 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_KR2_PAM4] = { 383 .subtype = IFM_100G_KR2_PAM4, 384 .baudrate = IF_Gbps(100ULL), 385 }, 386 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_DR4] = { 387 .subtype = IFM_200G_DR4, 388 .baudrate = IF_Gbps(200ULL), 389 }, 390 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_LR4] = { 391 .subtype = IFM_200G_LR4, 392 .baudrate = IF_Gbps(200ULL), 393 }, 394 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_SR4] = { 395 .subtype = IFM_200G_SR4, 396 .baudrate = IF_Gbps(200ULL), 397 }, 398 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_FR4] = { 399 .subtype = IFM_200G_FR4, 400 .baudrate = IF_Gbps(200ULL), 401 }, 402 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CR4_PAM4] = { 403 .subtype = IFM_200G_CR4_PAM4, 404 .baudrate = IF_Gbps(200ULL), 405 }, 406 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_KR4_PAM4] = { 407 .subtype = IFM_200G_KR4_PAM4, 408 .baudrate = IF_Gbps(200ULL), 409 }, 410 }; 411 412 DEBUGNET_DEFINE(mlx5_en); 413 414 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet"); 415 416 static void 417 mlx5e_update_carrier(struct mlx5e_priv *priv) 418 { 419 struct mlx5_core_dev *mdev = priv->mdev; 420 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 421 u32 eth_proto_oper; 422 int error; 423 u8 port_state; 424 u8 is_er_type; 425 u8 i, j; 426 bool ext; 427 struct media media_entry = {}; 428 429 port_state = mlx5_query_vport_state(mdev, 430 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0); 431 432 if (port_state == VPORT_STATE_UP) { 433 priv->media_status_last |= IFM_ACTIVE; 434 } else { 435 priv->media_status_last &= ~IFM_ACTIVE; 436 priv->media_active_last = IFM_ETHER; 437 if_link_state_change(priv->ifp, LINK_STATE_DOWN); 438 return; 439 } 440 441 error = mlx5_query_port_ptys(mdev, out, sizeof(out), 442 MLX5_PTYS_EN, 1); 443 if (error) { 444 priv->media_active_last = IFM_ETHER; 445 priv->ifp->if_baudrate = 1; 446 mlx5_en_err(priv->ifp, "query port ptys failed: 0x%x\n", 447 error); 448 return; 449 } 450 451 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet); 452 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 453 eth_proto_oper); 454 455 i = ilog2(eth_proto_oper); 456 457 for (j = 0; j != MLX5E_LINK_MODES_NUMBER; j++) { 458 media_entry = ext ? mlx5e_ext_mode_table[i][j] : 459 mlx5e_mode_table[i][j]; 460 if (media_entry.baudrate != 0) 461 break; 462 } 463 464 if (media_entry.subtype == 0) { 465 mlx5_en_err(priv->ifp, 466 "Could not find operational media subtype\n"); 467 return; 468 } 469 470 switch (media_entry.subtype) { 471 case IFM_10G_ER: 472 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type); 473 if (error != 0) { 474 mlx5_en_err(priv->ifp, 475 "query port pddr failed: %d\n", error); 476 } 477 if (error != 0 || is_er_type == 0) 478 media_entry.subtype = IFM_10G_LR; 479 break; 480 case IFM_40G_LR4: 481 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type); 482 if (error != 0) { 483 mlx5_en_err(priv->ifp, 484 "query port pddr failed: %d\n", error); 485 } 486 if (error == 0 && is_er_type != 0) 487 media_entry.subtype = IFM_40G_ER4; 488 break; 489 } 490 priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX; 491 priv->ifp->if_baudrate = media_entry.baudrate; 492 493 if_link_state_change(priv->ifp, LINK_STATE_UP); 494 } 495 496 static void 497 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr) 498 { 499 struct mlx5e_priv *priv = dev->if_softc; 500 501 ifmr->ifm_status = priv->media_status_last; 502 ifmr->ifm_current = ifmr->ifm_active = priv->media_active_last | 503 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) | 504 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0); 505 506 } 507 508 static u32 509 mlx5e_find_link_mode(u32 subtype, bool ext) 510 { 511 u32 i; 512 u32 j; 513 u32 link_mode = 0; 514 u32 speeds_num = 0; 515 struct media media_entry = {}; 516 517 switch (subtype) { 518 case IFM_10G_LR: 519 subtype = IFM_10G_ER; 520 break; 521 case IFM_40G_ER4: 522 subtype = IFM_40G_LR4; 523 break; 524 } 525 526 speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER : 527 MLX5E_LINK_SPEEDS_NUMBER; 528 529 for (i = 0; i != speeds_num; i++) { 530 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) { 531 media_entry = ext ? mlx5e_ext_mode_table[i][j] : 532 mlx5e_mode_table[i][j]; 533 if (media_entry.baudrate == 0) 534 continue; 535 if (media_entry.subtype == subtype) { 536 link_mode |= MLX5E_PROT_MASK(i); 537 } 538 } 539 } 540 541 return (link_mode); 542 } 543 544 static int 545 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv) 546 { 547 return (mlx5_set_port_pause_and_pfc(priv->mdev, 1, 548 priv->params.rx_pauseframe_control, 549 priv->params.tx_pauseframe_control, 550 priv->params.rx_priority_flow_control, 551 priv->params.tx_priority_flow_control)); 552 } 553 554 static int 555 mlx5e_set_port_pfc(struct mlx5e_priv *priv) 556 { 557 int error; 558 559 if (priv->gone != 0) { 560 error = -ENXIO; 561 } else if (priv->params.rx_pauseframe_control || 562 priv->params.tx_pauseframe_control) { 563 mlx5_en_err(priv->ifp, 564 "Global pauseframes must be disabled before enabling PFC.\n"); 565 error = -EINVAL; 566 } else { 567 error = mlx5e_set_port_pause_and_pfc(priv); 568 } 569 return (error); 570 } 571 572 static int 573 mlx5e_media_change(struct ifnet *dev) 574 { 575 struct mlx5e_priv *priv = dev->if_softc; 576 struct mlx5_core_dev *mdev = priv->mdev; 577 u32 eth_proto_cap; 578 u32 link_mode; 579 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 580 int was_opened; 581 int locked; 582 int error; 583 bool ext; 584 585 locked = PRIV_LOCKED(priv); 586 if (!locked) 587 PRIV_LOCK(priv); 588 589 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) { 590 error = EINVAL; 591 goto done; 592 } 593 594 error = mlx5_query_port_ptys(mdev, out, sizeof(out), 595 MLX5_PTYS_EN, 1); 596 if (error != 0) { 597 mlx5_en_err(dev, "Query port media capability failed\n"); 598 goto done; 599 } 600 601 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet); 602 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext); 603 604 /* query supported capabilities */ 605 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 606 eth_proto_capability); 607 608 /* check for autoselect */ 609 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) { 610 link_mode = eth_proto_cap; 611 if (link_mode == 0) { 612 mlx5_en_err(dev, "Port media capability is zero\n"); 613 error = EINVAL; 614 goto done; 615 } 616 } else { 617 link_mode = link_mode & eth_proto_cap; 618 if (link_mode == 0) { 619 mlx5_en_err(dev, "Not supported link mode requested\n"); 620 error = EINVAL; 621 goto done; 622 } 623 } 624 if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) { 625 /* check if PFC is enabled */ 626 if (priv->params.rx_priority_flow_control || 627 priv->params.tx_priority_flow_control) { 628 mlx5_en_err(dev, "PFC must be disabled before enabling global pauseframes.\n"); 629 error = EINVAL; 630 goto done; 631 } 632 } 633 /* update pauseframe control bits */ 634 priv->params.rx_pauseframe_control = 635 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0; 636 priv->params.tx_pauseframe_control = 637 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0; 638 639 /* check if device is opened */ 640 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 641 642 /* reconfigure the hardware */ 643 mlx5_set_port_status(mdev, MLX5_PORT_DOWN); 644 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext); 645 error = -mlx5e_set_port_pause_and_pfc(priv); 646 if (was_opened) 647 mlx5_set_port_status(mdev, MLX5_PORT_UP); 648 649 done: 650 if (!locked) 651 PRIV_UNLOCK(priv); 652 return (error); 653 } 654 655 static void 656 mlx5e_update_carrier_work(struct work_struct *work) 657 { 658 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 659 update_carrier_work); 660 661 PRIV_LOCK(priv); 662 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) 663 mlx5e_update_carrier(priv); 664 PRIV_UNLOCK(priv); 665 } 666 667 #define MLX5E_PCIE_PERF_GET_64(a,b,c,d,e,f) \ 668 s_debug->c = MLX5_GET64(mpcnt_reg, out, counter_set.f.c); 669 670 #define MLX5E_PCIE_PERF_GET_32(a,b,c,d,e,f) \ 671 s_debug->c = MLX5_GET(mpcnt_reg, out, counter_set.f.c); 672 673 static void 674 mlx5e_update_pcie_counters(struct mlx5e_priv *priv) 675 { 676 struct mlx5_core_dev *mdev = priv->mdev; 677 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug; 678 const unsigned sz = MLX5_ST_SZ_BYTES(mpcnt_reg); 679 void *out; 680 void *in; 681 int err; 682 683 /* allocate firmware request structures */ 684 in = mlx5_vzalloc(sz); 685 out = mlx5_vzalloc(sz); 686 if (in == NULL || out == NULL) 687 goto free_out; 688 689 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP); 690 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 691 if (err != 0) 692 goto free_out; 693 694 MLX5E_PCIE_PERFORMANCE_COUNTERS_64(MLX5E_PCIE_PERF_GET_64) 695 MLX5E_PCIE_PERFORMANCE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 696 697 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP); 698 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 699 if (err != 0) 700 goto free_out; 701 702 MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 703 704 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_LANE_COUNTERS_GROUP); 705 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 706 if (err != 0) 707 goto free_out; 708 709 MLX5E_PCIE_LANE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 710 711 free_out: 712 /* free firmware request structures */ 713 kvfree(in); 714 kvfree(out); 715 } 716 717 /* 718 * This function reads the physical port counters from the firmware 719 * using a pre-defined layout defined by various MLX5E_PPORT_XXX() 720 * macros. The output is converted from big-endian 64-bit values into 721 * host endian ones and stored in the "priv->stats.pport" structure. 722 */ 723 static void 724 mlx5e_update_pport_counters(struct mlx5e_priv *priv) 725 { 726 struct mlx5_core_dev *mdev = priv->mdev; 727 struct mlx5e_pport_stats *s = &priv->stats.pport; 728 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug; 729 u32 *in; 730 u32 *out; 731 const u64 *ptr; 732 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 733 unsigned x; 734 unsigned y; 735 unsigned z; 736 737 /* allocate firmware request structures */ 738 in = mlx5_vzalloc(sz); 739 out = mlx5_vzalloc(sz); 740 if (in == NULL || out == NULL) 741 goto free_out; 742 743 /* 744 * Get pointer to the 64-bit counter set which is located at a 745 * fixed offset in the output firmware request structure: 746 */ 747 ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set); 748 749 MLX5_SET(ppcnt_reg, in, local_port, 1); 750 751 /* read IEEE802_3 counter group using predefined counter layout */ 752 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP); 753 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 754 for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM; 755 x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++) 756 s->arg[y] = be64toh(ptr[x]); 757 758 /* read RFC2819 counter group using predefined counter layout */ 759 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP); 760 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 761 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++) 762 s->arg[y] = be64toh(ptr[x]); 763 764 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM + 765 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++) 766 s_debug->arg[y] = be64toh(ptr[x]); 767 768 /* read RFC2863 counter group using predefined counter layout */ 769 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP); 770 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 771 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++) 772 s_debug->arg[y] = be64toh(ptr[x]); 773 774 /* read physical layer stats counter group using predefined counter layout */ 775 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP); 776 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 777 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++) 778 s_debug->arg[y] = be64toh(ptr[x]); 779 780 /* read Extended Ethernet counter group using predefined counter layout */ 781 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP); 782 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 783 for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++) 784 s_debug->arg[y] = be64toh(ptr[x]); 785 786 /* read Extended Statistical Group */ 787 if (MLX5_CAP_GEN(mdev, pcam_reg) && 788 MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) && 789 MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) { 790 /* read Extended Statistical counter group using predefined counter layout */ 791 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP); 792 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 793 794 for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++) 795 s_debug->arg[y] = be64toh(ptr[x]); 796 } 797 798 /* read PCIE counters */ 799 mlx5e_update_pcie_counters(priv); 800 801 /* read per-priority counters */ 802 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP); 803 804 /* iterate all the priorities */ 805 for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) { 806 MLX5_SET(ppcnt_reg, in, prio_tc, z); 807 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 808 809 /* read per priority stats counter group using predefined counter layout */ 810 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM / 811 MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++) 812 s->arg[y] = be64toh(ptr[x]); 813 } 814 815 free_out: 816 /* free firmware request structures */ 817 kvfree(in); 818 kvfree(out); 819 } 820 821 static void 822 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv) 823 { 824 u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {}; 825 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {}; 826 827 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard)) 828 return; 829 830 MLX5_SET(query_vnic_env_in, in, opcode, 831 MLX5_CMD_OP_QUERY_VNIC_ENV); 832 MLX5_SET(query_vnic_env_in, in, op_mod, 0); 833 MLX5_SET(query_vnic_env_in, in, other_vport, 0); 834 835 if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0) 836 return; 837 838 priv->stats.vport.rx_steer_missed_packets = 839 MLX5_GET64(query_vnic_env_out, out, 840 vport_env.nic_receive_steering_discard); 841 } 842 843 /* 844 * This function is called regularly to collect all statistics 845 * counters from the firmware. The values can be viewed through the 846 * sysctl interface. Execution is serialized using the priv's global 847 * configuration lock. 848 */ 849 static void 850 mlx5e_update_stats_locked(struct mlx5e_priv *priv) 851 { 852 struct mlx5_core_dev *mdev = priv->mdev; 853 struct mlx5e_vport_stats *s = &priv->stats.vport; 854 struct mlx5e_sq_stats *sq_stats; 855 #if (__FreeBSD_version < 1100000) 856 struct ifnet *ifp = priv->ifp; 857 #endif 858 859 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)]; 860 u32 *out; 861 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out); 862 u64 tso_packets = 0; 863 u64 tso_bytes = 0; 864 u64 tx_queue_dropped = 0; 865 u64 tx_defragged = 0; 866 u64 tx_offload_none = 0; 867 u64 lro_packets = 0; 868 u64 lro_bytes = 0; 869 u64 sw_lro_queued = 0; 870 u64 sw_lro_flushed = 0; 871 u64 rx_csum_none = 0; 872 u64 rx_wqe_err = 0; 873 u64 rx_packets = 0; 874 u64 rx_bytes = 0; 875 u32 rx_out_of_buffer = 0; 876 int error; 877 int i; 878 int j; 879 880 out = mlx5_vzalloc(outlen); 881 if (out == NULL) 882 goto free_out; 883 884 /* Collect firts the SW counters and then HW for consistency */ 885 for (i = 0; i < priv->params.num_channels; i++) { 886 struct mlx5e_channel *pch = priv->channel + i; 887 struct mlx5e_rq *rq = &pch->rq; 888 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats; 889 890 /* collect stats from LRO */ 891 rq_stats->sw_lro_queued = rq->lro.lro_queued; 892 rq_stats->sw_lro_flushed = rq->lro.lro_flushed; 893 sw_lro_queued += rq_stats->sw_lro_queued; 894 sw_lro_flushed += rq_stats->sw_lro_flushed; 895 lro_packets += rq_stats->lro_packets; 896 lro_bytes += rq_stats->lro_bytes; 897 rx_csum_none += rq_stats->csum_none; 898 rx_wqe_err += rq_stats->wqe_err; 899 rx_packets += rq_stats->packets; 900 rx_bytes += rq_stats->bytes; 901 902 for (j = 0; j < priv->num_tc; j++) { 903 sq_stats = &pch->sq[j].stats; 904 905 tso_packets += sq_stats->tso_packets; 906 tso_bytes += sq_stats->tso_bytes; 907 tx_queue_dropped += sq_stats->dropped; 908 tx_queue_dropped += sq_stats->enobuf; 909 tx_defragged += sq_stats->defragged; 910 tx_offload_none += sq_stats->csum_offload_none; 911 } 912 } 913 914 #ifdef RATELIMIT 915 /* Collect statistics from all rate-limit queues */ 916 for (j = 0; j < priv->rl.param.tx_worker_threads_def; j++) { 917 struct mlx5e_rl_worker *rlw = priv->rl.workers + j; 918 919 for (i = 0; i < priv->rl.param.tx_channels_per_worker_def; i++) { 920 struct mlx5e_rl_channel *channel = rlw->channels + i; 921 struct mlx5e_sq *sq = channel->sq; 922 923 if (sq == NULL) 924 continue; 925 926 sq_stats = &sq->stats; 927 928 tso_packets += sq_stats->tso_packets; 929 tso_bytes += sq_stats->tso_bytes; 930 tx_queue_dropped += sq_stats->dropped; 931 tx_queue_dropped += sq_stats->enobuf; 932 tx_defragged += sq_stats->defragged; 933 tx_offload_none += sq_stats->csum_offload_none; 934 } 935 } 936 #endif 937 938 /* update counters */ 939 s->tso_packets = tso_packets; 940 s->tso_bytes = tso_bytes; 941 s->tx_queue_dropped = tx_queue_dropped; 942 s->tx_defragged = tx_defragged; 943 s->lro_packets = lro_packets; 944 s->lro_bytes = lro_bytes; 945 s->sw_lro_queued = sw_lro_queued; 946 s->sw_lro_flushed = sw_lro_flushed; 947 s->rx_csum_none = rx_csum_none; 948 s->rx_wqe_err = rx_wqe_err; 949 s->rx_packets = rx_packets; 950 s->rx_bytes = rx_bytes; 951 952 mlx5e_grp_vnic_env_update_stats(priv); 953 954 /* HW counters */ 955 memset(in, 0, sizeof(in)); 956 957 MLX5_SET(query_vport_counter_in, in, opcode, 958 MLX5_CMD_OP_QUERY_VPORT_COUNTER); 959 MLX5_SET(query_vport_counter_in, in, op_mod, 0); 960 MLX5_SET(query_vport_counter_in, in, other_vport, 0); 961 962 memset(out, 0, outlen); 963 964 /* get number of out-of-buffer drops first */ 965 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 && 966 mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id, 967 &rx_out_of_buffer) == 0) { 968 s->rx_out_of_buffer = rx_out_of_buffer; 969 } 970 971 /* get port statistics */ 972 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) { 973 #define MLX5_GET_CTR(out, x) \ 974 MLX5_GET64(query_vport_counter_out, out, x) 975 976 s->rx_error_packets = 977 MLX5_GET_CTR(out, received_errors.packets); 978 s->rx_error_bytes = 979 MLX5_GET_CTR(out, received_errors.octets); 980 s->tx_error_packets = 981 MLX5_GET_CTR(out, transmit_errors.packets); 982 s->tx_error_bytes = 983 MLX5_GET_CTR(out, transmit_errors.octets); 984 985 s->rx_unicast_packets = 986 MLX5_GET_CTR(out, received_eth_unicast.packets); 987 s->rx_unicast_bytes = 988 MLX5_GET_CTR(out, received_eth_unicast.octets); 989 s->tx_unicast_packets = 990 MLX5_GET_CTR(out, transmitted_eth_unicast.packets); 991 s->tx_unicast_bytes = 992 MLX5_GET_CTR(out, transmitted_eth_unicast.octets); 993 994 s->rx_multicast_packets = 995 MLX5_GET_CTR(out, received_eth_multicast.packets); 996 s->rx_multicast_bytes = 997 MLX5_GET_CTR(out, received_eth_multicast.octets); 998 s->tx_multicast_packets = 999 MLX5_GET_CTR(out, transmitted_eth_multicast.packets); 1000 s->tx_multicast_bytes = 1001 MLX5_GET_CTR(out, transmitted_eth_multicast.octets); 1002 1003 s->rx_broadcast_packets = 1004 MLX5_GET_CTR(out, received_eth_broadcast.packets); 1005 s->rx_broadcast_bytes = 1006 MLX5_GET_CTR(out, received_eth_broadcast.octets); 1007 s->tx_broadcast_packets = 1008 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets); 1009 s->tx_broadcast_bytes = 1010 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets); 1011 1012 s->tx_packets = s->tx_unicast_packets + 1013 s->tx_multicast_packets + s->tx_broadcast_packets; 1014 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes + 1015 s->tx_broadcast_bytes; 1016 1017 /* Update calculated offload counters */ 1018 s->tx_csum_offload = s->tx_packets - tx_offload_none; 1019 s->rx_csum_good = s->rx_packets - s->rx_csum_none; 1020 } 1021 1022 /* Get physical port counters */ 1023 mlx5e_update_pport_counters(priv); 1024 1025 s->tx_jumbo_packets = 1026 priv->stats.port_stats_debug.tx_stat_p1519to2047octets + 1027 priv->stats.port_stats_debug.tx_stat_p2048to4095octets + 1028 priv->stats.port_stats_debug.tx_stat_p4096to8191octets + 1029 priv->stats.port_stats_debug.tx_stat_p8192to10239octets; 1030 1031 #if (__FreeBSD_version < 1100000) 1032 /* no get_counters interface in fbsd 10 */ 1033 ifp->if_ipackets = s->rx_packets; 1034 ifp->if_ierrors = priv->stats.pport.in_range_len_errors + 1035 priv->stats.pport.out_of_range_len + 1036 priv->stats.pport.too_long_errors + 1037 priv->stats.pport.check_seq_err + 1038 priv->stats.pport.alignment_err; 1039 ifp->if_iqdrops = s->rx_out_of_buffer; 1040 ifp->if_opackets = s->tx_packets; 1041 ifp->if_oerrors = priv->stats.port_stats_debug.out_discards; 1042 ifp->if_snd.ifq_drops = s->tx_queue_dropped; 1043 ifp->if_ibytes = s->rx_bytes; 1044 ifp->if_obytes = s->tx_bytes; 1045 ifp->if_collisions = 1046 priv->stats.pport.collisions; 1047 #endif 1048 1049 free_out: 1050 kvfree(out); 1051 1052 /* Update diagnostics, if any */ 1053 if (priv->params_ethtool.diag_pci_enable || 1054 priv->params_ethtool.diag_general_enable) { 1055 error = mlx5_core_get_diagnostics_full(mdev, 1056 priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL, 1057 priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL); 1058 if (error != 0) 1059 mlx5_en_err(priv->ifp, 1060 "Failed reading diagnostics: %d\n", error); 1061 } 1062 1063 /* Update FEC, if any */ 1064 error = mlx5e_fec_update(priv); 1065 if (error != 0 && error != EOPNOTSUPP) { 1066 mlx5_en_err(priv->ifp, 1067 "Updating FEC failed: %d\n", error); 1068 } 1069 1070 /* Update temperature, if any */ 1071 if (priv->params_ethtool.hw_num_temp != 0) { 1072 error = mlx5e_hw_temperature_update(priv); 1073 if (error != 0 && error != EOPNOTSUPP) { 1074 mlx5_en_err(priv->ifp, 1075 "Updating temperature failed: %d\n", error); 1076 } 1077 } 1078 } 1079 1080 static void 1081 mlx5e_update_stats_work(struct work_struct *work) 1082 { 1083 struct mlx5e_priv *priv; 1084 1085 priv = container_of(work, struct mlx5e_priv, update_stats_work); 1086 PRIV_LOCK(priv); 1087 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 && 1088 !test_bit(MLX5_INTERFACE_STATE_TEARDOWN, &priv->mdev->intf_state)) 1089 mlx5e_update_stats_locked(priv); 1090 PRIV_UNLOCK(priv); 1091 } 1092 1093 static void 1094 mlx5e_update_stats(void *arg) 1095 { 1096 struct mlx5e_priv *priv = arg; 1097 1098 queue_work(priv->wq, &priv->update_stats_work); 1099 1100 callout_reset(&priv->watchdog, hz / 4, &mlx5e_update_stats, priv); 1101 } 1102 1103 static void 1104 mlx5e_async_event_sub(struct mlx5e_priv *priv, 1105 enum mlx5_dev_event event) 1106 { 1107 switch (event) { 1108 case MLX5_DEV_EVENT_PORT_UP: 1109 case MLX5_DEV_EVENT_PORT_DOWN: 1110 queue_work(priv->wq, &priv->update_carrier_work); 1111 break; 1112 1113 default: 1114 break; 1115 } 1116 } 1117 1118 static void 1119 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv, 1120 enum mlx5_dev_event event, unsigned long param) 1121 { 1122 struct mlx5e_priv *priv = vpriv; 1123 1124 mtx_lock(&priv->async_events_mtx); 1125 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state)) 1126 mlx5e_async_event_sub(priv, event); 1127 mtx_unlock(&priv->async_events_mtx); 1128 } 1129 1130 static void 1131 mlx5e_enable_async_events(struct mlx5e_priv *priv) 1132 { 1133 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 1134 } 1135 1136 static void 1137 mlx5e_disable_async_events(struct mlx5e_priv *priv) 1138 { 1139 mtx_lock(&priv->async_events_mtx); 1140 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 1141 mtx_unlock(&priv->async_events_mtx); 1142 } 1143 1144 static void mlx5e_calibration_callout(void *arg); 1145 static int mlx5e_calibration_duration = 20; 1146 static int mlx5e_fast_calibration = 1; 1147 static int mlx5e_normal_calibration = 30; 1148 1149 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 1150 "MLX5 timestamp calibration parameteres"); 1151 1152 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN, 1153 &mlx5e_calibration_duration, 0, 1154 "Duration of initial calibration"); 1155 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN, 1156 &mlx5e_fast_calibration, 0, 1157 "Recalibration interval during initial calibration"); 1158 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN, 1159 &mlx5e_normal_calibration, 0, 1160 "Recalibration interval during normal operations"); 1161 1162 /* 1163 * Ignites the calibration process. 1164 */ 1165 static void 1166 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv) 1167 { 1168 1169 if (priv->clbr_done == 0) 1170 mlx5e_calibration_callout(priv); 1171 else 1172 callout_reset_curcpu(&priv->tstmp_clbr, (priv->clbr_done < 1173 mlx5e_calibration_duration ? mlx5e_fast_calibration : 1174 mlx5e_normal_calibration) * hz, mlx5e_calibration_callout, 1175 priv); 1176 } 1177 1178 static uint64_t 1179 mlx5e_timespec2usec(const struct timespec *ts) 1180 { 1181 1182 return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec); 1183 } 1184 1185 static uint64_t 1186 mlx5e_hw_clock(struct mlx5e_priv *priv) 1187 { 1188 struct mlx5_init_seg *iseg; 1189 uint32_t hw_h, hw_h1, hw_l; 1190 1191 iseg = priv->mdev->iseg; 1192 do { 1193 hw_h = ioread32be(&iseg->internal_timer_h); 1194 hw_l = ioread32be(&iseg->internal_timer_l); 1195 hw_h1 = ioread32be(&iseg->internal_timer_h); 1196 } while (hw_h1 != hw_h); 1197 return (((uint64_t)hw_h << 32) | hw_l); 1198 } 1199 1200 /* 1201 * The calibration callout, it runs either in the context of the 1202 * thread which enables calibration, or in callout. It takes the 1203 * snapshot of system and adapter clocks, then advances the pointers to 1204 * the calibration point to allow rx path to read the consistent data 1205 * lockless. 1206 */ 1207 static void 1208 mlx5e_calibration_callout(void *arg) 1209 { 1210 struct mlx5e_priv *priv; 1211 struct mlx5e_clbr_point *next, *curr; 1212 struct timespec ts; 1213 int clbr_curr_next; 1214 1215 priv = arg; 1216 curr = &priv->clbr_points[priv->clbr_curr]; 1217 clbr_curr_next = priv->clbr_curr + 1; 1218 if (clbr_curr_next >= nitems(priv->clbr_points)) 1219 clbr_curr_next = 0; 1220 next = &priv->clbr_points[clbr_curr_next]; 1221 1222 next->base_prev = curr->base_curr; 1223 next->clbr_hw_prev = curr->clbr_hw_curr; 1224 1225 next->clbr_hw_curr = mlx5e_hw_clock(priv); 1226 if (((next->clbr_hw_curr - curr->clbr_hw_curr) >> MLX5E_TSTMP_PREC) == 1227 0) { 1228 if (priv->clbr_done != 0) { 1229 mlx5_en_err(priv->ifp, 1230 "HW failed tstmp frozen %#jx %#jx, disabling\n", 1231 next->clbr_hw_curr, curr->clbr_hw_prev); 1232 priv->clbr_done = 0; 1233 } 1234 atomic_store_rel_int(&curr->clbr_gen, 0); 1235 return; 1236 } 1237 1238 nanouptime(&ts); 1239 next->base_curr = mlx5e_timespec2usec(&ts); 1240 1241 curr->clbr_gen = 0; 1242 atomic_thread_fence_rel(); 1243 priv->clbr_curr = clbr_curr_next; 1244 atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen)); 1245 1246 if (priv->clbr_done < mlx5e_calibration_duration) 1247 priv->clbr_done++; 1248 mlx5e_reset_calibration_callout(priv); 1249 } 1250 1251 static const char *mlx5e_rq_stats_desc[] = { 1252 MLX5E_RQ_STATS(MLX5E_STATS_DESC) 1253 }; 1254 1255 static int 1256 mlx5e_create_rq(struct mlx5e_channel *c, 1257 struct mlx5e_rq_param *param, 1258 struct mlx5e_rq *rq) 1259 { 1260 struct mlx5e_priv *priv = c->priv; 1261 struct mlx5_core_dev *mdev = priv->mdev; 1262 char buffer[16]; 1263 void *rqc = param->rqc; 1264 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); 1265 int wq_sz; 1266 int err; 1267 int i; 1268 u32 nsegs, wqe_sz; 1269 1270 err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs); 1271 if (err != 0) 1272 goto done; 1273 1274 /* Create DMA descriptor TAG */ 1275 if ((err = -bus_dma_tag_create( 1276 bus_get_dma_tag(mdev->pdev->dev.bsddev), 1277 1, /* any alignment */ 1278 0, /* no boundary */ 1279 BUS_SPACE_MAXADDR, /* lowaddr */ 1280 BUS_SPACE_MAXADDR, /* highaddr */ 1281 NULL, NULL, /* filter, filterarg */ 1282 nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */ 1283 nsegs, /* nsegments */ 1284 nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */ 1285 0, /* flags */ 1286 NULL, NULL, /* lockfunc, lockfuncarg */ 1287 &rq->dma_tag))) 1288 goto done; 1289 1290 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, 1291 &rq->wq_ctrl); 1292 if (err) 1293 goto err_free_dma_tag; 1294 1295 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR]; 1296 1297 err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs); 1298 if (err != 0) 1299 goto err_rq_wq_destroy; 1300 1301 wq_sz = mlx5_wq_ll_get_size(&rq->wq); 1302 1303 err = -tcp_lro_init_args(&rq->lro, priv->ifp, TCP_LRO_ENTRIES, wq_sz); 1304 if (err) 1305 goto err_rq_wq_destroy; 1306 1307 rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO); 1308 for (i = 0; i != wq_sz; i++) { 1309 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i); 1310 int j; 1311 1312 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map); 1313 if (err != 0) { 1314 while (i--) 1315 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 1316 goto err_rq_mbuf_free; 1317 } 1318 1319 /* set value for constant fields */ 1320 for (j = 0; j < rq->nsegs; j++) 1321 wqe->data[j].lkey = cpu_to_be32(priv->mr.key); 1322 } 1323 1324 INIT_WORK(&rq->dim.work, mlx5e_dim_work); 1325 if (priv->params.rx_cq_moderation_mode < 2) { 1326 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 1327 } else { 1328 void *cqc = container_of(param, 1329 struct mlx5e_channel_param, rq)->rx_cq.cqc; 1330 1331 switch (MLX5_GET(cqc, cqc, cq_period_mode)) { 1332 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE: 1333 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; 1334 break; 1335 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE: 1336 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE; 1337 break; 1338 default: 1339 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 1340 break; 1341 } 1342 } 1343 1344 rq->ifp = priv->ifp; 1345 rq->channel = c; 1346 rq->ix = c->ix; 1347 1348 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix); 1349 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 1350 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM, 1351 rq->stats.arg); 1352 return (0); 1353 1354 err_rq_mbuf_free: 1355 free(rq->mbuf, M_MLX5EN); 1356 tcp_lro_free(&rq->lro); 1357 err_rq_wq_destroy: 1358 mlx5_wq_destroy(&rq->wq_ctrl); 1359 err_free_dma_tag: 1360 bus_dma_tag_destroy(rq->dma_tag); 1361 done: 1362 return (err); 1363 } 1364 1365 static void 1366 mlx5e_destroy_rq(struct mlx5e_rq *rq) 1367 { 1368 int wq_sz; 1369 int i; 1370 1371 /* destroy all sysctl nodes */ 1372 sysctl_ctx_free(&rq->stats.ctx); 1373 1374 /* free leftover LRO packets, if any */ 1375 tcp_lro_free(&rq->lro); 1376 1377 wq_sz = mlx5_wq_ll_get_size(&rq->wq); 1378 for (i = 0; i != wq_sz; i++) { 1379 if (rq->mbuf[i].mbuf != NULL) { 1380 bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map); 1381 m_freem(rq->mbuf[i].mbuf); 1382 } 1383 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 1384 } 1385 free(rq->mbuf, M_MLX5EN); 1386 mlx5_wq_destroy(&rq->wq_ctrl); 1387 bus_dma_tag_destroy(rq->dma_tag); 1388 } 1389 1390 static int 1391 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param) 1392 { 1393 struct mlx5e_channel *c = rq->channel; 1394 struct mlx5e_priv *priv = c->priv; 1395 struct mlx5_core_dev *mdev = priv->mdev; 1396 1397 void *in; 1398 void *rqc; 1399 void *wq; 1400 int inlen; 1401 int err; 1402 1403 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 1404 sizeof(u64) * rq->wq_ctrl.buf.npages; 1405 in = mlx5_vzalloc(inlen); 1406 if (in == NULL) 1407 return (-ENOMEM); 1408 1409 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1410 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1411 1412 memcpy(rqc, param->rqc, sizeof(param->rqc)); 1413 1414 MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn); 1415 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1416 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1417 if (priv->counter_set_id >= 0) 1418 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id); 1419 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - 1420 PAGE_SHIFT); 1421 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); 1422 1423 mlx5_fill_page_array(&rq->wq_ctrl.buf, 1424 (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 1425 1426 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); 1427 1428 kvfree(in); 1429 1430 return (err); 1431 } 1432 1433 static int 1434 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state) 1435 { 1436 struct mlx5e_channel *c = rq->channel; 1437 struct mlx5e_priv *priv = c->priv; 1438 struct mlx5_core_dev *mdev = priv->mdev; 1439 1440 void *in; 1441 void *rqc; 1442 int inlen; 1443 int err; 1444 1445 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 1446 in = mlx5_vzalloc(inlen); 1447 if (in == NULL) 1448 return (-ENOMEM); 1449 1450 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1451 1452 MLX5_SET(modify_rq_in, in, rqn, rq->rqn); 1453 MLX5_SET(modify_rq_in, in, rq_state, curr_state); 1454 MLX5_SET(rqc, rqc, state, next_state); 1455 1456 err = mlx5_core_modify_rq(mdev, in, inlen); 1457 1458 kvfree(in); 1459 1460 return (err); 1461 } 1462 1463 static void 1464 mlx5e_disable_rq(struct mlx5e_rq *rq) 1465 { 1466 struct mlx5e_channel *c = rq->channel; 1467 struct mlx5e_priv *priv = c->priv; 1468 struct mlx5_core_dev *mdev = priv->mdev; 1469 1470 mlx5_core_destroy_rq(mdev, rq->rqn); 1471 } 1472 1473 static int 1474 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq) 1475 { 1476 struct mlx5e_channel *c = rq->channel; 1477 struct mlx5e_priv *priv = c->priv; 1478 struct mlx5_wq_ll *wq = &rq->wq; 1479 int i; 1480 1481 for (i = 0; i < 1000; i++) { 1482 if (wq->cur_sz >= priv->params.min_rx_wqes) 1483 return (0); 1484 1485 msleep(4); 1486 } 1487 return (-ETIMEDOUT); 1488 } 1489 1490 static int 1491 mlx5e_open_rq(struct mlx5e_channel *c, 1492 struct mlx5e_rq_param *param, 1493 struct mlx5e_rq *rq) 1494 { 1495 int err; 1496 1497 err = mlx5e_create_rq(c, param, rq); 1498 if (err) 1499 return (err); 1500 1501 err = mlx5e_enable_rq(rq, param); 1502 if (err) 1503 goto err_destroy_rq; 1504 1505 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 1506 if (err) 1507 goto err_disable_rq; 1508 1509 c->rq.enabled = 1; 1510 1511 return (0); 1512 1513 err_disable_rq: 1514 mlx5e_disable_rq(rq); 1515 err_destroy_rq: 1516 mlx5e_destroy_rq(rq); 1517 1518 return (err); 1519 } 1520 1521 static void 1522 mlx5e_close_rq(struct mlx5e_rq *rq) 1523 { 1524 mtx_lock(&rq->mtx); 1525 rq->enabled = 0; 1526 callout_stop(&rq->watchdog); 1527 mtx_unlock(&rq->mtx); 1528 1529 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 1530 } 1531 1532 static void 1533 mlx5e_close_rq_wait(struct mlx5e_rq *rq) 1534 { 1535 1536 mlx5e_disable_rq(rq); 1537 mlx5e_close_cq(&rq->cq); 1538 cancel_work_sync(&rq->dim.work); 1539 mlx5e_destroy_rq(rq); 1540 } 1541 1542 void 1543 mlx5e_free_sq_db(struct mlx5e_sq *sq) 1544 { 1545 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1546 int x; 1547 1548 for (x = 0; x != wq_sz; x++) { 1549 if (unlikely(sq->mbuf[x].p_refcount != NULL)) { 1550 atomic_add_int(sq->mbuf[x].p_refcount, -1); 1551 sq->mbuf[x].p_refcount = NULL; 1552 } 1553 if (sq->mbuf[x].mbuf != NULL) { 1554 bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map); 1555 m_freem(sq->mbuf[x].mbuf); 1556 } 1557 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 1558 } 1559 free(sq->mbuf, M_MLX5EN); 1560 } 1561 1562 int 1563 mlx5e_alloc_sq_db(struct mlx5e_sq *sq) 1564 { 1565 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1566 int err; 1567 int x; 1568 1569 sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO); 1570 1571 /* Create DMA descriptor MAPs */ 1572 for (x = 0; x != wq_sz; x++) { 1573 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map); 1574 if (err != 0) { 1575 while (x--) 1576 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 1577 free(sq->mbuf, M_MLX5EN); 1578 return (err); 1579 } 1580 } 1581 return (0); 1582 } 1583 1584 static const char *mlx5e_sq_stats_desc[] = { 1585 MLX5E_SQ_STATS(MLX5E_STATS_DESC) 1586 }; 1587 1588 void 1589 mlx5e_update_sq_inline(struct mlx5e_sq *sq) 1590 { 1591 sq->max_inline = sq->priv->params.tx_max_inline; 1592 sq->min_inline_mode = sq->priv->params.tx_min_inline_mode; 1593 1594 /* 1595 * Check if trust state is DSCP or if inline mode is NONE which 1596 * indicates CX-5 or newer hardware. 1597 */ 1598 if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP || 1599 sq->min_inline_mode == MLX5_INLINE_MODE_NONE) { 1600 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert)) 1601 sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN; 1602 else 1603 sq->min_insert_caps = MLX5E_INSERT_NON_VLAN; 1604 } else { 1605 sq->min_insert_caps = 0; 1606 } 1607 } 1608 1609 static void 1610 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c) 1611 { 1612 int i; 1613 1614 for (i = 0; i != priv->num_tc; i++) { 1615 mtx_lock(&c->sq[i].lock); 1616 mlx5e_update_sq_inline(&c->sq[i]); 1617 mtx_unlock(&c->sq[i].lock); 1618 } 1619 } 1620 1621 void 1622 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv) 1623 { 1624 int i; 1625 1626 /* check if channels are closed */ 1627 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 1628 return; 1629 1630 for (i = 0; i < priv->params.num_channels; i++) 1631 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]); 1632 } 1633 1634 static int 1635 mlx5e_create_sq(struct mlx5e_channel *c, 1636 int tc, 1637 struct mlx5e_sq_param *param, 1638 struct mlx5e_sq *sq) 1639 { 1640 struct mlx5e_priv *priv = c->priv; 1641 struct mlx5_core_dev *mdev = priv->mdev; 1642 char buffer[16]; 1643 void *sqc = param->sqc; 1644 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq); 1645 int err; 1646 1647 /* Create DMA descriptor TAG */ 1648 if ((err = -bus_dma_tag_create( 1649 bus_get_dma_tag(mdev->pdev->dev.bsddev), 1650 1, /* any alignment */ 1651 0, /* no boundary */ 1652 BUS_SPACE_MAXADDR, /* lowaddr */ 1653 BUS_SPACE_MAXADDR, /* highaddr */ 1654 NULL, NULL, /* filter, filterarg */ 1655 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */ 1656 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */ 1657 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */ 1658 0, /* flags */ 1659 NULL, NULL, /* lockfunc, lockfuncarg */ 1660 &sq->dma_tag))) 1661 goto done; 1662 1663 err = mlx5_alloc_map_uar(mdev, &sq->uar); 1664 if (err) 1665 goto err_free_dma_tag; 1666 1667 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, 1668 &sq->wq_ctrl); 1669 if (err) 1670 goto err_unmap_free_uar; 1671 1672 sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; 1673 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2; 1674 1675 err = mlx5e_alloc_sq_db(sq); 1676 if (err) 1677 goto err_sq_wq_destroy; 1678 1679 sq->mkey_be = cpu_to_be32(priv->mr.key); 1680 sq->ifp = priv->ifp; 1681 sq->priv = priv; 1682 sq->tc = tc; 1683 1684 mlx5e_update_sq_inline(sq); 1685 1686 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc); 1687 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 1688 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM, 1689 sq->stats.arg); 1690 1691 return (0); 1692 1693 err_sq_wq_destroy: 1694 mlx5_wq_destroy(&sq->wq_ctrl); 1695 1696 err_unmap_free_uar: 1697 mlx5_unmap_free_uar(mdev, &sq->uar); 1698 1699 err_free_dma_tag: 1700 bus_dma_tag_destroy(sq->dma_tag); 1701 done: 1702 return (err); 1703 } 1704 1705 static void 1706 mlx5e_destroy_sq(struct mlx5e_sq *sq) 1707 { 1708 /* destroy all sysctl nodes */ 1709 sysctl_ctx_free(&sq->stats.ctx); 1710 1711 mlx5e_free_sq_db(sq); 1712 mlx5_wq_destroy(&sq->wq_ctrl); 1713 mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar); 1714 bus_dma_tag_destroy(sq->dma_tag); 1715 } 1716 1717 int 1718 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param, 1719 int tis_num) 1720 { 1721 void *in; 1722 void *sqc; 1723 void *wq; 1724 int inlen; 1725 int err; 1726 1727 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1728 sizeof(u64) * sq->wq_ctrl.buf.npages; 1729 in = mlx5_vzalloc(inlen); 1730 if (in == NULL) 1731 return (-ENOMEM); 1732 1733 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1734 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1735 1736 memcpy(sqc, param->sqc, sizeof(param->sqc)); 1737 1738 MLX5_SET(sqc, sqc, tis_num_0, tis_num); 1739 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn); 1740 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1741 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1742 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1743 1744 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1745 MLX5_SET(wq, wq, uar_page, sq->uar.index); 1746 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift - 1747 PAGE_SHIFT); 1748 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma); 1749 1750 mlx5_fill_page_array(&sq->wq_ctrl.buf, 1751 (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 1752 1753 err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn); 1754 1755 kvfree(in); 1756 1757 return (err); 1758 } 1759 1760 int 1761 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state) 1762 { 1763 void *in; 1764 void *sqc; 1765 int inlen; 1766 int err; 1767 1768 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 1769 in = mlx5_vzalloc(inlen); 1770 if (in == NULL) 1771 return (-ENOMEM); 1772 1773 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1774 1775 MLX5_SET(modify_sq_in, in, sqn, sq->sqn); 1776 MLX5_SET(modify_sq_in, in, sq_state, curr_state); 1777 MLX5_SET(sqc, sqc, state, next_state); 1778 1779 err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen); 1780 1781 kvfree(in); 1782 1783 return (err); 1784 } 1785 1786 void 1787 mlx5e_disable_sq(struct mlx5e_sq *sq) 1788 { 1789 1790 mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn); 1791 } 1792 1793 static int 1794 mlx5e_open_sq(struct mlx5e_channel *c, 1795 int tc, 1796 struct mlx5e_sq_param *param, 1797 struct mlx5e_sq *sq) 1798 { 1799 int err; 1800 1801 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact; 1802 1803 /* ensure the TX completion event factor is not zero */ 1804 if (sq->cev_factor == 0) 1805 sq->cev_factor = 1; 1806 1807 err = mlx5e_create_sq(c, tc, param, sq); 1808 if (err) 1809 return (err); 1810 1811 err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]); 1812 if (err) 1813 goto err_destroy_sq; 1814 1815 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY); 1816 if (err) 1817 goto err_disable_sq; 1818 1819 WRITE_ONCE(sq->running, 1); 1820 1821 return (0); 1822 1823 err_disable_sq: 1824 mlx5e_disable_sq(sq); 1825 err_destroy_sq: 1826 mlx5e_destroy_sq(sq); 1827 1828 return (err); 1829 } 1830 1831 static void 1832 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep) 1833 { 1834 /* fill up remainder with NOPs */ 1835 while (sq->cev_counter != 0) { 1836 while (!mlx5e_sq_has_room_for(sq, 1)) { 1837 if (can_sleep != 0) { 1838 mtx_unlock(&sq->lock); 1839 msleep(4); 1840 mtx_lock(&sq->lock); 1841 } else { 1842 goto done; 1843 } 1844 } 1845 /* send a single NOP */ 1846 mlx5e_send_nop(sq, 1); 1847 atomic_thread_fence_rel(); 1848 } 1849 done: 1850 /* Check if we need to write the doorbell */ 1851 if (likely(sq->doorbell.d64 != 0)) { 1852 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0); 1853 sq->doorbell.d64 = 0; 1854 } 1855 } 1856 1857 void 1858 mlx5e_sq_cev_timeout(void *arg) 1859 { 1860 struct mlx5e_sq *sq = arg; 1861 1862 mtx_assert(&sq->lock, MA_OWNED); 1863 1864 /* check next state */ 1865 switch (sq->cev_next_state) { 1866 case MLX5E_CEV_STATE_SEND_NOPS: 1867 /* fill TX ring with NOPs, if any */ 1868 mlx5e_sq_send_nops_locked(sq, 0); 1869 1870 /* check if completed */ 1871 if (sq->cev_counter == 0) { 1872 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL; 1873 return; 1874 } 1875 break; 1876 default: 1877 /* send NOPs on next timeout */ 1878 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS; 1879 break; 1880 } 1881 1882 /* restart timer */ 1883 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq); 1884 } 1885 1886 void 1887 mlx5e_drain_sq(struct mlx5e_sq *sq) 1888 { 1889 int error; 1890 struct mlx5_core_dev *mdev= sq->priv->mdev; 1891 1892 /* 1893 * Check if already stopped. 1894 * 1895 * NOTE: Serialization of this function is managed by the 1896 * caller ensuring the priv's state lock is locked or in case 1897 * of rate limit support, a single thread manages drain and 1898 * resume of SQs. The "running" variable can therefore safely 1899 * be read without any locks. 1900 */ 1901 if (READ_ONCE(sq->running) == 0) 1902 return; 1903 1904 /* don't put more packets into the SQ */ 1905 WRITE_ONCE(sq->running, 0); 1906 1907 /* serialize access to DMA rings */ 1908 mtx_lock(&sq->lock); 1909 1910 /* teardown event factor timer, if any */ 1911 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS; 1912 callout_stop(&sq->cev_callout); 1913 1914 /* send dummy NOPs in order to flush the transmit ring */ 1915 mlx5e_sq_send_nops_locked(sq, 1); 1916 mtx_unlock(&sq->lock); 1917 1918 /* wait till SQ is empty or link is down */ 1919 mtx_lock(&sq->lock); 1920 while (sq->cc != sq->pc && 1921 (sq->priv->media_status_last & IFM_ACTIVE) != 0 && 1922 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1923 mtx_unlock(&sq->lock); 1924 msleep(1); 1925 sq->cq.mcq.comp(&sq->cq.mcq, NULL); 1926 mtx_lock(&sq->lock); 1927 } 1928 mtx_unlock(&sq->lock); 1929 1930 /* error out remaining requests */ 1931 error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR); 1932 if (error != 0) { 1933 mlx5_en_err(sq->ifp, 1934 "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error); 1935 } 1936 1937 /* wait till SQ is empty */ 1938 mtx_lock(&sq->lock); 1939 while (sq->cc != sq->pc && 1940 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1941 mtx_unlock(&sq->lock); 1942 msleep(1); 1943 sq->cq.mcq.comp(&sq->cq.mcq, NULL); 1944 mtx_lock(&sq->lock); 1945 } 1946 mtx_unlock(&sq->lock); 1947 } 1948 1949 static void 1950 mlx5e_close_sq_wait(struct mlx5e_sq *sq) 1951 { 1952 1953 mlx5e_drain_sq(sq); 1954 mlx5e_disable_sq(sq); 1955 mlx5e_destroy_sq(sq); 1956 } 1957 1958 static int 1959 mlx5e_create_cq(struct mlx5e_priv *priv, 1960 struct mlx5e_cq_param *param, 1961 struct mlx5e_cq *cq, 1962 mlx5e_cq_comp_t *comp, 1963 int eq_ix) 1964 { 1965 struct mlx5_core_dev *mdev = priv->mdev; 1966 struct mlx5_core_cq *mcq = &cq->mcq; 1967 int eqn_not_used; 1968 int irqn; 1969 int err; 1970 u32 i; 1971 1972 param->wq.buf_numa_node = 0; 1973 param->wq.db_numa_node = 0; 1974 1975 err = mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn); 1976 if (err) 1977 return (err); 1978 1979 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, 1980 &cq->wq_ctrl); 1981 if (err) 1982 return (err); 1983 1984 mcq->cqe_sz = 64; 1985 mcq->set_ci_db = cq->wq_ctrl.db.db; 1986 mcq->arm_db = cq->wq_ctrl.db.db + 1; 1987 *mcq->set_ci_db = 0; 1988 *mcq->arm_db = 0; 1989 mcq->vector = eq_ix; 1990 mcq->comp = comp; 1991 mcq->event = mlx5e_cq_error_event; 1992 mcq->irqn = irqn; 1993 mcq->uar = &priv->cq_uar; 1994 1995 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { 1996 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); 1997 1998 cqe->op_own = 0xf1; 1999 } 2000 2001 cq->priv = priv; 2002 2003 return (0); 2004 } 2005 2006 static void 2007 mlx5e_destroy_cq(struct mlx5e_cq *cq) 2008 { 2009 mlx5_wq_destroy(&cq->wq_ctrl); 2010 } 2011 2012 static int 2013 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix) 2014 { 2015 struct mlx5_core_cq *mcq = &cq->mcq; 2016 u32 out[MLX5_ST_SZ_DW(create_cq_out)]; 2017 void *in; 2018 void *cqc; 2019 int inlen; 2020 int irqn_not_used; 2021 int eqn; 2022 int err; 2023 2024 inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 2025 sizeof(u64) * cq->wq_ctrl.buf.npages; 2026 in = mlx5_vzalloc(inlen); 2027 if (in == NULL) 2028 return (-ENOMEM); 2029 2030 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); 2031 2032 memcpy(cqc, param->cqc, sizeof(param->cqc)); 2033 2034 mlx5_fill_page_array(&cq->wq_ctrl.buf, 2035 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas)); 2036 2037 mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used); 2038 2039 MLX5_SET(cqc, cqc, c_eqn, eqn); 2040 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index); 2041 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - 2042 PAGE_SHIFT); 2043 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); 2044 2045 err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen, out, sizeof(out)); 2046 2047 kvfree(in); 2048 2049 if (err) 2050 return (err); 2051 2052 mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock)); 2053 2054 return (0); 2055 } 2056 2057 static void 2058 mlx5e_disable_cq(struct mlx5e_cq *cq) 2059 { 2060 2061 mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq); 2062 } 2063 2064 int 2065 mlx5e_open_cq(struct mlx5e_priv *priv, 2066 struct mlx5e_cq_param *param, 2067 struct mlx5e_cq *cq, 2068 mlx5e_cq_comp_t *comp, 2069 int eq_ix) 2070 { 2071 int err; 2072 2073 err = mlx5e_create_cq(priv, param, cq, comp, eq_ix); 2074 if (err) 2075 return (err); 2076 2077 err = mlx5e_enable_cq(cq, param, eq_ix); 2078 if (err) 2079 goto err_destroy_cq; 2080 2081 return (0); 2082 2083 err_destroy_cq: 2084 mlx5e_destroy_cq(cq); 2085 2086 return (err); 2087 } 2088 2089 void 2090 mlx5e_close_cq(struct mlx5e_cq *cq) 2091 { 2092 mlx5e_disable_cq(cq); 2093 mlx5e_destroy_cq(cq); 2094 } 2095 2096 static int 2097 mlx5e_open_tx_cqs(struct mlx5e_channel *c, 2098 struct mlx5e_channel_param *cparam) 2099 { 2100 int err; 2101 int tc; 2102 2103 for (tc = 0; tc < c->priv->num_tc; tc++) { 2104 /* open completion queue */ 2105 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq, 2106 &mlx5e_tx_cq_comp, c->ix); 2107 if (err) 2108 goto err_close_tx_cqs; 2109 } 2110 return (0); 2111 2112 err_close_tx_cqs: 2113 for (tc--; tc >= 0; tc--) 2114 mlx5e_close_cq(&c->sq[tc].cq); 2115 2116 return (err); 2117 } 2118 2119 static void 2120 mlx5e_close_tx_cqs(struct mlx5e_channel *c) 2121 { 2122 int tc; 2123 2124 for (tc = 0; tc < c->priv->num_tc; tc++) 2125 mlx5e_close_cq(&c->sq[tc].cq); 2126 } 2127 2128 static int 2129 mlx5e_open_sqs(struct mlx5e_channel *c, 2130 struct mlx5e_channel_param *cparam) 2131 { 2132 int err; 2133 int tc; 2134 2135 for (tc = 0; tc < c->priv->num_tc; tc++) { 2136 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]); 2137 if (err) 2138 goto err_close_sqs; 2139 } 2140 2141 return (0); 2142 2143 err_close_sqs: 2144 for (tc--; tc >= 0; tc--) 2145 mlx5e_close_sq_wait(&c->sq[tc]); 2146 2147 return (err); 2148 } 2149 2150 static void 2151 mlx5e_close_sqs_wait(struct mlx5e_channel *c) 2152 { 2153 int tc; 2154 2155 for (tc = 0; tc < c->priv->num_tc; tc++) 2156 mlx5e_close_sq_wait(&c->sq[tc]); 2157 } 2158 2159 static void 2160 mlx5e_chan_static_init(struct mlx5e_priv *priv, struct mlx5e_channel *c, int ix) 2161 { 2162 int tc; 2163 2164 /* setup priv and channel number */ 2165 c->priv = priv; 2166 c->ix = ix; 2167 2168 /* setup send tag */ 2169 m_snd_tag_init(&c->tag, c->priv->ifp, IF_SND_TAG_TYPE_UNLIMITED); 2170 2171 init_completion(&c->completion); 2172 2173 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF); 2174 2175 callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0); 2176 2177 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) { 2178 struct mlx5e_sq *sq = c->sq + tc; 2179 2180 mtx_init(&sq->lock, "mlx5tx", 2181 MTX_NETWORK_LOCK " TX", MTX_DEF); 2182 mtx_init(&sq->comp_lock, "mlx5comp", 2183 MTX_NETWORK_LOCK " TX", MTX_DEF); 2184 2185 callout_init_mtx(&sq->cev_callout, &sq->lock, 0); 2186 } 2187 } 2188 2189 static void 2190 mlx5e_chan_wait_for_completion(struct mlx5e_channel *c) 2191 { 2192 2193 m_snd_tag_rele(&c->tag); 2194 wait_for_completion(&c->completion); 2195 } 2196 2197 static void 2198 mlx5e_priv_wait_for_completion(struct mlx5e_priv *priv, const uint32_t channels) 2199 { 2200 uint32_t x; 2201 2202 for (x = 0; x != channels; x++) 2203 mlx5e_chan_wait_for_completion(&priv->channel[x]); 2204 } 2205 2206 static void 2207 mlx5e_chan_static_destroy(struct mlx5e_channel *c) 2208 { 2209 int tc; 2210 2211 callout_drain(&c->rq.watchdog); 2212 2213 mtx_destroy(&c->rq.mtx); 2214 2215 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) { 2216 callout_drain(&c->sq[tc].cev_callout); 2217 mtx_destroy(&c->sq[tc].lock); 2218 mtx_destroy(&c->sq[tc].comp_lock); 2219 } 2220 } 2221 2222 static int 2223 mlx5e_open_channel(struct mlx5e_priv *priv, 2224 struct mlx5e_channel_param *cparam, 2225 struct mlx5e_channel *c) 2226 { 2227 struct epoch_tracker et; 2228 int i, err; 2229 2230 /* zero non-persistant data */ 2231 MLX5E_ZERO(&c->rq, mlx5e_rq_zero_start); 2232 for (i = 0; i != priv->num_tc; i++) 2233 MLX5E_ZERO(&c->sq[i], mlx5e_sq_zero_start); 2234 2235 /* open transmit completion queue */ 2236 err = mlx5e_open_tx_cqs(c, cparam); 2237 if (err) 2238 goto err_free; 2239 2240 /* open receive completion queue */ 2241 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq, 2242 &mlx5e_rx_cq_comp, c->ix); 2243 if (err) 2244 goto err_close_tx_cqs; 2245 2246 err = mlx5e_open_sqs(c, cparam); 2247 if (err) 2248 goto err_close_rx_cq; 2249 2250 err = mlx5e_open_rq(c, &cparam->rq, &c->rq); 2251 if (err) 2252 goto err_close_sqs; 2253 2254 /* poll receive queue initially */ 2255 NET_EPOCH_ENTER(et); 2256 c->rq.cq.mcq.comp(&c->rq.cq.mcq, NULL); 2257 NET_EPOCH_EXIT(et); 2258 2259 return (0); 2260 2261 err_close_sqs: 2262 mlx5e_close_sqs_wait(c); 2263 2264 err_close_rx_cq: 2265 mlx5e_close_cq(&c->rq.cq); 2266 2267 err_close_tx_cqs: 2268 mlx5e_close_tx_cqs(c); 2269 2270 err_free: 2271 return (err); 2272 } 2273 2274 static void 2275 mlx5e_close_channel(struct mlx5e_channel *c) 2276 { 2277 mlx5e_close_rq(&c->rq); 2278 } 2279 2280 static void 2281 mlx5e_close_channel_wait(struct mlx5e_channel *c) 2282 { 2283 mlx5e_close_rq_wait(&c->rq); 2284 mlx5e_close_sqs_wait(c); 2285 mlx5e_close_tx_cqs(c); 2286 } 2287 2288 static int 2289 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs) 2290 { 2291 u32 r, n; 2292 2293 r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz : 2294 MLX5E_SW2MB_MTU(priv->ifp->if_mtu); 2295 if (r > MJUM16BYTES) 2296 return (-ENOMEM); 2297 2298 if (r > MJUM9BYTES) 2299 r = MJUM16BYTES; 2300 else if (r > MJUMPAGESIZE) 2301 r = MJUM9BYTES; 2302 else if (r > MCLBYTES) 2303 r = MJUMPAGESIZE; 2304 else 2305 r = MCLBYTES; 2306 2307 /* 2308 * n + 1 must be a power of two, because stride size must be. 2309 * Stride size is 16 * (n + 1), as the first segment is 2310 * control. 2311 */ 2312 for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++) 2313 ; 2314 2315 if (n > MLX5E_MAX_BUSDMA_RX_SEGS) 2316 return (-ENOMEM); 2317 2318 *wqe_sz = r; 2319 *nsegs = n; 2320 return (0); 2321 } 2322 2323 static void 2324 mlx5e_build_rq_param(struct mlx5e_priv *priv, 2325 struct mlx5e_rq_param *param) 2326 { 2327 void *rqc = param->rqc; 2328 void *wq = MLX5_ADDR_OF(rqc, rqc, wq); 2329 u32 wqe_sz, nsegs; 2330 2331 mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs); 2332 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); 2333 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 2334 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) + 2335 nsegs * sizeof(struct mlx5_wqe_data_seg))); 2336 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size); 2337 MLX5_SET(wq, wq, pd, priv->pdn); 2338 2339 param->wq.buf_numa_node = 0; 2340 param->wq.db_numa_node = 0; 2341 param->wq.linear = 1; 2342 } 2343 2344 static void 2345 mlx5e_build_sq_param(struct mlx5e_priv *priv, 2346 struct mlx5e_sq_param *param) 2347 { 2348 void *sqc = param->sqc; 2349 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 2350 2351 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size); 2352 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 2353 MLX5_SET(wq, wq, pd, priv->pdn); 2354 2355 param->wq.buf_numa_node = 0; 2356 param->wq.db_numa_node = 0; 2357 param->wq.linear = 1; 2358 } 2359 2360 static void 2361 mlx5e_build_common_cq_param(struct mlx5e_priv *priv, 2362 struct mlx5e_cq_param *param) 2363 { 2364 void *cqc = param->cqc; 2365 2366 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index); 2367 } 2368 2369 static void 2370 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr) 2371 { 2372 2373 *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE); 2374 2375 /* apply LRO restrictions */ 2376 if (priv->params.hw_lro_en && 2377 ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) { 2378 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO; 2379 } 2380 } 2381 2382 static void 2383 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, 2384 struct mlx5e_cq_param *param) 2385 { 2386 struct net_dim_cq_moder curr; 2387 void *cqc = param->cqc; 2388 2389 /* 2390 * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE 2391 * format is more beneficial for FreeBSD use case. 2392 * 2393 * Adding support for MLX5_CQE_FORMAT_CSUM will require changes 2394 * in mlx5e_decompress_cqe. 2395 */ 2396 if (priv->params.cqe_zipping_en) { 2397 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH); 2398 MLX5_SET(cqc, cqc, cqe_compression_en, 1); 2399 } 2400 2401 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size); 2402 2403 switch (priv->params.rx_cq_moderation_mode) { 2404 case 0: 2405 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec); 2406 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts); 2407 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2408 break; 2409 case 1: 2410 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec); 2411 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts); 2412 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2413 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2414 else 2415 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2416 break; 2417 case 2: 2418 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr); 2419 MLX5_SET(cqc, cqc, cq_period, curr.usec); 2420 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts); 2421 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2422 break; 2423 case 3: 2424 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr); 2425 MLX5_SET(cqc, cqc, cq_period, curr.usec); 2426 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts); 2427 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2428 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2429 else 2430 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2431 break; 2432 default: 2433 break; 2434 } 2435 2436 mlx5e_dim_build_cq_param(priv, param); 2437 2438 mlx5e_build_common_cq_param(priv, param); 2439 } 2440 2441 static void 2442 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv, 2443 struct mlx5e_cq_param *param) 2444 { 2445 void *cqc = param->cqc; 2446 2447 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size); 2448 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec); 2449 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts); 2450 2451 switch (priv->params.tx_cq_moderation_mode) { 2452 case 0: 2453 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2454 break; 2455 default: 2456 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2457 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2458 else 2459 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2460 break; 2461 } 2462 2463 mlx5e_build_common_cq_param(priv, param); 2464 } 2465 2466 static void 2467 mlx5e_build_channel_param(struct mlx5e_priv *priv, 2468 struct mlx5e_channel_param *cparam) 2469 { 2470 memset(cparam, 0, sizeof(*cparam)); 2471 2472 mlx5e_build_rq_param(priv, &cparam->rq); 2473 mlx5e_build_sq_param(priv, &cparam->sq); 2474 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq); 2475 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq); 2476 } 2477 2478 static int 2479 mlx5e_open_channels(struct mlx5e_priv *priv) 2480 { 2481 struct mlx5e_channel_param *cparam; 2482 int err; 2483 int i; 2484 int j; 2485 2486 cparam = malloc(sizeof(*cparam), M_MLX5EN, M_WAITOK); 2487 2488 mlx5e_build_channel_param(priv, cparam); 2489 for (i = 0; i < priv->params.num_channels; i++) { 2490 err = mlx5e_open_channel(priv, cparam, &priv->channel[i]); 2491 if (err) 2492 goto err_close_channels; 2493 } 2494 2495 for (j = 0; j < priv->params.num_channels; j++) { 2496 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq); 2497 if (err) 2498 goto err_close_channels; 2499 } 2500 free(cparam, M_MLX5EN); 2501 return (0); 2502 2503 err_close_channels: 2504 while (i--) { 2505 mlx5e_close_channel(&priv->channel[i]); 2506 mlx5e_close_channel_wait(&priv->channel[i]); 2507 } 2508 free(cparam, M_MLX5EN); 2509 return (err); 2510 } 2511 2512 static void 2513 mlx5e_close_channels(struct mlx5e_priv *priv) 2514 { 2515 int i; 2516 2517 for (i = 0; i < priv->params.num_channels; i++) 2518 mlx5e_close_channel(&priv->channel[i]); 2519 for (i = 0; i < priv->params.num_channels; i++) 2520 mlx5e_close_channel_wait(&priv->channel[i]); 2521 } 2522 2523 static int 2524 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq) 2525 { 2526 2527 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) { 2528 uint8_t cq_mode; 2529 2530 switch (priv->params.tx_cq_moderation_mode) { 2531 case 0: 2532 case 2: 2533 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 2534 break; 2535 default: 2536 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE; 2537 break; 2538 } 2539 2540 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq, 2541 priv->params.tx_cq_moderation_usec, 2542 priv->params.tx_cq_moderation_pkts, 2543 cq_mode)); 2544 } 2545 2546 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq, 2547 priv->params.tx_cq_moderation_usec, 2548 priv->params.tx_cq_moderation_pkts)); 2549 } 2550 2551 static int 2552 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq) 2553 { 2554 2555 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) { 2556 uint8_t cq_mode; 2557 uint8_t dim_mode; 2558 int retval; 2559 2560 switch (priv->params.rx_cq_moderation_mode) { 2561 case 0: 2562 case 2: 2563 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 2564 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; 2565 break; 2566 default: 2567 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE; 2568 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE; 2569 break; 2570 } 2571 2572 /* tear down dynamic interrupt moderation */ 2573 mtx_lock(&rq->mtx); 2574 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 2575 mtx_unlock(&rq->mtx); 2576 2577 /* wait for dynamic interrupt moderation work task, if any */ 2578 cancel_work_sync(&rq->dim.work); 2579 2580 if (priv->params.rx_cq_moderation_mode >= 2) { 2581 struct net_dim_cq_moder curr; 2582 2583 mlx5e_get_default_profile(priv, dim_mode, &curr); 2584 2585 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq, 2586 curr.usec, curr.pkts, cq_mode); 2587 2588 /* set dynamic interrupt moderation mode and zero defaults */ 2589 mtx_lock(&rq->mtx); 2590 rq->dim.mode = dim_mode; 2591 rq->dim.state = 0; 2592 rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE; 2593 mtx_unlock(&rq->mtx); 2594 } else { 2595 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq, 2596 priv->params.rx_cq_moderation_usec, 2597 priv->params.rx_cq_moderation_pkts, 2598 cq_mode); 2599 } 2600 return (retval); 2601 } 2602 2603 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq, 2604 priv->params.rx_cq_moderation_usec, 2605 priv->params.rx_cq_moderation_pkts)); 2606 } 2607 2608 static int 2609 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c) 2610 { 2611 int err; 2612 int i; 2613 2614 err = mlx5e_refresh_rq_params(priv, &c->rq); 2615 if (err) 2616 goto done; 2617 2618 for (i = 0; i != priv->num_tc; i++) { 2619 err = mlx5e_refresh_sq_params(priv, &c->sq[i]); 2620 if (err) 2621 goto done; 2622 } 2623 done: 2624 return (err); 2625 } 2626 2627 int 2628 mlx5e_refresh_channel_params(struct mlx5e_priv *priv) 2629 { 2630 int i; 2631 2632 /* check if channels are closed */ 2633 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 2634 return (EINVAL); 2635 2636 for (i = 0; i < priv->params.num_channels; i++) { 2637 int err; 2638 2639 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]); 2640 if (err) 2641 return (err); 2642 } 2643 return (0); 2644 } 2645 2646 static int 2647 mlx5e_open_tis(struct mlx5e_priv *priv, int tc) 2648 { 2649 struct mlx5_core_dev *mdev = priv->mdev; 2650 u32 in[MLX5_ST_SZ_DW(create_tis_in)]; 2651 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 2652 2653 memset(in, 0, sizeof(in)); 2654 2655 MLX5_SET(tisc, tisc, prio, tc); 2656 MLX5_SET(tisc, tisc, transport_domain, priv->tdn); 2657 2658 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc])); 2659 } 2660 2661 static void 2662 mlx5e_close_tis(struct mlx5e_priv *priv, int tc) 2663 { 2664 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]); 2665 } 2666 2667 static int 2668 mlx5e_open_tises(struct mlx5e_priv *priv) 2669 { 2670 int num_tc = priv->num_tc; 2671 int err; 2672 int tc; 2673 2674 for (tc = 0; tc < num_tc; tc++) { 2675 err = mlx5e_open_tis(priv, tc); 2676 if (err) 2677 goto err_close_tises; 2678 } 2679 2680 return (0); 2681 2682 err_close_tises: 2683 for (tc--; tc >= 0; tc--) 2684 mlx5e_close_tis(priv, tc); 2685 2686 return (err); 2687 } 2688 2689 static void 2690 mlx5e_close_tises(struct mlx5e_priv *priv) 2691 { 2692 int num_tc = priv->num_tc; 2693 int tc; 2694 2695 for (tc = 0; tc < num_tc; tc++) 2696 mlx5e_close_tis(priv, tc); 2697 } 2698 2699 static int 2700 mlx5e_open_rqt(struct mlx5e_priv *priv) 2701 { 2702 struct mlx5_core_dev *mdev = priv->mdev; 2703 u32 *in; 2704 u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 2705 void *rqtc; 2706 int inlen; 2707 int err; 2708 int sz; 2709 int i; 2710 2711 sz = 1 << priv->params.rx_hash_log_tbl_sz; 2712 2713 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 2714 in = mlx5_vzalloc(inlen); 2715 if (in == NULL) 2716 return (-ENOMEM); 2717 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 2718 2719 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 2720 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 2721 2722 for (i = 0; i < sz; i++) { 2723 int ix = i; 2724 #ifdef RSS 2725 ix = rss_get_indirection_to_bucket(ix); 2726 #endif 2727 /* ensure we don't overflow */ 2728 ix %= priv->params.num_channels; 2729 2730 /* apply receive side scaling stride, if any */ 2731 ix -= ix % (int)priv->params.channels_rsss; 2732 2733 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn); 2734 } 2735 2736 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 2737 2738 err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out)); 2739 if (!err) 2740 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn); 2741 2742 kvfree(in); 2743 2744 return (err); 2745 } 2746 2747 static void 2748 mlx5e_close_rqt(struct mlx5e_priv *priv) 2749 { 2750 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0}; 2751 u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0}; 2752 2753 MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT); 2754 MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn); 2755 2756 mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)); 2757 } 2758 2759 static void 2760 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt) 2761 { 2762 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 2763 __be32 *hkey; 2764 2765 MLX5_SET(tirc, tirc, transport_domain, priv->tdn); 2766 2767 #define ROUGH_MAX_L2_L3_HDR_SZ 256 2768 2769 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2770 MLX5_HASH_FIELD_SEL_DST_IP) 2771 2772 #define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2773 MLX5_HASH_FIELD_SEL_DST_IP |\ 2774 MLX5_HASH_FIELD_SEL_L4_SPORT |\ 2775 MLX5_HASH_FIELD_SEL_L4_DPORT) 2776 2777 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2778 MLX5_HASH_FIELD_SEL_DST_IP |\ 2779 MLX5_HASH_FIELD_SEL_IPSEC_SPI) 2780 2781 if (priv->params.hw_lro_en) { 2782 MLX5_SET(tirc, tirc, lro_enable_mask, 2783 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | 2784 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO); 2785 MLX5_SET(tirc, tirc, lro_max_msg_sz, 2786 (priv->params.lro_wqe_sz - 2787 ROUGH_MAX_L2_L3_HDR_SZ) >> 8); 2788 /* TODO: add the option to choose timer value dynamically */ 2789 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, 2790 MLX5_CAP_ETH(priv->mdev, 2791 lro_timer_supported_periods[2])); 2792 } 2793 2794 /* setup parameters for hashing TIR type, if any */ 2795 switch (tt) { 2796 case MLX5E_TT_ANY: 2797 MLX5_SET(tirc, tirc, disp_type, 2798 MLX5_TIRC_DISP_TYPE_DIRECT); 2799 MLX5_SET(tirc, tirc, inline_rqn, 2800 priv->channel[0].rq.rqn); 2801 break; 2802 default: 2803 MLX5_SET(tirc, tirc, disp_type, 2804 MLX5_TIRC_DISP_TYPE_INDIRECT); 2805 MLX5_SET(tirc, tirc, indirect_table, 2806 priv->rqtn); 2807 MLX5_SET(tirc, tirc, rx_hash_fn, 2808 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ); 2809 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 2810 #ifdef RSS 2811 /* 2812 * The FreeBSD RSS implementation does currently not 2813 * support symmetric Toeplitz hashes: 2814 */ 2815 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0); 2816 rss_getkey((uint8_t *)hkey); 2817 #else 2818 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 2819 hkey[0] = cpu_to_be32(0xD181C62C); 2820 hkey[1] = cpu_to_be32(0xF7F4DB5B); 2821 hkey[2] = cpu_to_be32(0x1983A2FC); 2822 hkey[3] = cpu_to_be32(0x943E1ADB); 2823 hkey[4] = cpu_to_be32(0xD9389E6B); 2824 hkey[5] = cpu_to_be32(0xD1039C2C); 2825 hkey[6] = cpu_to_be32(0xA74499AD); 2826 hkey[7] = cpu_to_be32(0x593D56D9); 2827 hkey[8] = cpu_to_be32(0xF3253C06); 2828 hkey[9] = cpu_to_be32(0x2ADC1FFC); 2829 #endif 2830 break; 2831 } 2832 2833 switch (tt) { 2834 case MLX5E_TT_IPV4_TCP: 2835 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2836 MLX5_L3_PROT_TYPE_IPV4); 2837 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2838 MLX5_L4_PROT_TYPE_TCP); 2839 #ifdef RSS 2840 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) { 2841 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2842 MLX5_HASH_IP); 2843 } else 2844 #endif 2845 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2846 MLX5_HASH_ALL); 2847 break; 2848 2849 case MLX5E_TT_IPV6_TCP: 2850 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2851 MLX5_L3_PROT_TYPE_IPV6); 2852 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2853 MLX5_L4_PROT_TYPE_TCP); 2854 #ifdef RSS 2855 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) { 2856 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2857 MLX5_HASH_IP); 2858 } else 2859 #endif 2860 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2861 MLX5_HASH_ALL); 2862 break; 2863 2864 case MLX5E_TT_IPV4_UDP: 2865 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2866 MLX5_L3_PROT_TYPE_IPV4); 2867 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2868 MLX5_L4_PROT_TYPE_UDP); 2869 #ifdef RSS 2870 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) { 2871 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2872 MLX5_HASH_IP); 2873 } else 2874 #endif 2875 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2876 MLX5_HASH_ALL); 2877 break; 2878 2879 case MLX5E_TT_IPV6_UDP: 2880 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2881 MLX5_L3_PROT_TYPE_IPV6); 2882 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2883 MLX5_L4_PROT_TYPE_UDP); 2884 #ifdef RSS 2885 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) { 2886 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2887 MLX5_HASH_IP); 2888 } else 2889 #endif 2890 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2891 MLX5_HASH_ALL); 2892 break; 2893 2894 case MLX5E_TT_IPV4_IPSEC_AH: 2895 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2896 MLX5_L3_PROT_TYPE_IPV4); 2897 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2898 MLX5_HASH_IP_IPSEC_SPI); 2899 break; 2900 2901 case MLX5E_TT_IPV6_IPSEC_AH: 2902 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2903 MLX5_L3_PROT_TYPE_IPV6); 2904 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2905 MLX5_HASH_IP_IPSEC_SPI); 2906 break; 2907 2908 case MLX5E_TT_IPV4_IPSEC_ESP: 2909 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2910 MLX5_L3_PROT_TYPE_IPV4); 2911 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2912 MLX5_HASH_IP_IPSEC_SPI); 2913 break; 2914 2915 case MLX5E_TT_IPV6_IPSEC_ESP: 2916 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2917 MLX5_L3_PROT_TYPE_IPV6); 2918 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2919 MLX5_HASH_IP_IPSEC_SPI); 2920 break; 2921 2922 case MLX5E_TT_IPV4: 2923 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2924 MLX5_L3_PROT_TYPE_IPV4); 2925 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2926 MLX5_HASH_IP); 2927 break; 2928 2929 case MLX5E_TT_IPV6: 2930 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2931 MLX5_L3_PROT_TYPE_IPV6); 2932 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2933 MLX5_HASH_IP); 2934 break; 2935 2936 default: 2937 break; 2938 } 2939 } 2940 2941 static int 2942 mlx5e_open_tir(struct mlx5e_priv *priv, int tt) 2943 { 2944 struct mlx5_core_dev *mdev = priv->mdev; 2945 u32 *in; 2946 void *tirc; 2947 int inlen; 2948 int err; 2949 2950 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 2951 in = mlx5_vzalloc(inlen); 2952 if (in == NULL) 2953 return (-ENOMEM); 2954 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context); 2955 2956 mlx5e_build_tir_ctx(priv, tirc, tt); 2957 2958 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]); 2959 2960 kvfree(in); 2961 2962 return (err); 2963 } 2964 2965 static void 2966 mlx5e_close_tir(struct mlx5e_priv *priv, int tt) 2967 { 2968 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]); 2969 } 2970 2971 static int 2972 mlx5e_open_tirs(struct mlx5e_priv *priv) 2973 { 2974 int err; 2975 int i; 2976 2977 for (i = 0; i < MLX5E_NUM_TT; i++) { 2978 err = mlx5e_open_tir(priv, i); 2979 if (err) 2980 goto err_close_tirs; 2981 } 2982 2983 return (0); 2984 2985 err_close_tirs: 2986 for (i--; i >= 0; i--) 2987 mlx5e_close_tir(priv, i); 2988 2989 return (err); 2990 } 2991 2992 static void 2993 mlx5e_close_tirs(struct mlx5e_priv *priv) 2994 { 2995 int i; 2996 2997 for (i = 0; i < MLX5E_NUM_TT; i++) 2998 mlx5e_close_tir(priv, i); 2999 } 3000 3001 /* 3002 * SW MTU does not include headers, 3003 * HW MTU includes all headers and checksums. 3004 */ 3005 static int 3006 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu) 3007 { 3008 struct mlx5e_priv *priv = ifp->if_softc; 3009 struct mlx5_core_dev *mdev = priv->mdev; 3010 int hw_mtu; 3011 int err; 3012 3013 hw_mtu = MLX5E_SW2HW_MTU(sw_mtu); 3014 3015 err = mlx5_set_port_mtu(mdev, hw_mtu); 3016 if (err) { 3017 mlx5_en_err(ifp, "mlx5_set_port_mtu failed setting %d, err=%d\n", 3018 sw_mtu, err); 3019 return (err); 3020 } 3021 3022 /* Update vport context MTU */ 3023 err = mlx5_set_vport_mtu(mdev, hw_mtu); 3024 if (err) { 3025 mlx5_en_err(ifp, 3026 "Failed updating vport context with MTU size, err=%d\n", 3027 err); 3028 } 3029 3030 ifp->if_mtu = sw_mtu; 3031 3032 err = mlx5_query_vport_mtu(mdev, &hw_mtu); 3033 if (err || !hw_mtu) { 3034 /* fallback to port oper mtu */ 3035 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu); 3036 } 3037 if (err) { 3038 mlx5_en_err(ifp, 3039 "Query port MTU, after setting new MTU value, failed\n"); 3040 return (err); 3041 } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) { 3042 err = -E2BIG, 3043 mlx5_en_err(ifp, 3044 "Port MTU %d is smaller than ifp mtu %d\n", 3045 hw_mtu, sw_mtu); 3046 } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) { 3047 err = -EINVAL; 3048 mlx5_en_err(ifp, 3049 "Port MTU %d is bigger than ifp mtu %d\n", 3050 hw_mtu, sw_mtu); 3051 } 3052 priv->params_ethtool.hw_mtu = hw_mtu; 3053 3054 /* compute MSB */ 3055 while (hw_mtu & (hw_mtu - 1)) 3056 hw_mtu &= (hw_mtu - 1); 3057 priv->params_ethtool.hw_mtu_msb = hw_mtu; 3058 3059 return (err); 3060 } 3061 3062 int 3063 mlx5e_open_locked(struct ifnet *ifp) 3064 { 3065 struct mlx5e_priv *priv = ifp->if_softc; 3066 int err; 3067 u16 set_id; 3068 3069 /* check if already opened */ 3070 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 3071 return (0); 3072 3073 #ifdef RSS 3074 if (rss_getnumbuckets() > priv->params.num_channels) { 3075 mlx5_en_info(ifp, 3076 "NOTE: There are more RSS buckets(%u) than channels(%u) available\n", 3077 rss_getnumbuckets(), priv->params.num_channels); 3078 } 3079 #endif 3080 err = mlx5e_open_tises(priv); 3081 if (err) { 3082 mlx5_en_err(ifp, "mlx5e_open_tises failed, %d\n", err); 3083 return (err); 3084 } 3085 err = mlx5_vport_alloc_q_counter(priv->mdev, 3086 MLX5_INTERFACE_PROTOCOL_ETH, &set_id); 3087 if (err) { 3088 mlx5_en_err(priv->ifp, 3089 "mlx5_vport_alloc_q_counter failed: %d\n", err); 3090 goto err_close_tises; 3091 } 3092 /* store counter set ID */ 3093 priv->counter_set_id = set_id; 3094 3095 err = mlx5e_open_channels(priv); 3096 if (err) { 3097 mlx5_en_err(ifp, 3098 "mlx5e_open_channels failed, %d\n", err); 3099 goto err_dalloc_q_counter; 3100 } 3101 err = mlx5e_open_rqt(priv); 3102 if (err) { 3103 mlx5_en_err(ifp, "mlx5e_open_rqt failed, %d\n", err); 3104 goto err_close_channels; 3105 } 3106 err = mlx5e_open_tirs(priv); 3107 if (err) { 3108 mlx5_en_err(ifp, "mlx5e_open_tir failed, %d\n", err); 3109 goto err_close_rqls; 3110 } 3111 err = mlx5e_open_flow_table(priv); 3112 if (err) { 3113 mlx5_en_err(ifp, 3114 "mlx5e_open_flow_table failed, %d\n", err); 3115 goto err_close_tirs; 3116 } 3117 err = mlx5e_add_all_vlan_rules(priv); 3118 if (err) { 3119 mlx5_en_err(ifp, 3120 "mlx5e_add_all_vlan_rules failed, %d\n", err); 3121 goto err_close_flow_table; 3122 } 3123 set_bit(MLX5E_STATE_OPENED, &priv->state); 3124 3125 mlx5e_update_carrier(priv); 3126 mlx5e_set_rx_mode_core(priv); 3127 3128 return (0); 3129 3130 err_close_flow_table: 3131 mlx5e_close_flow_table(priv); 3132 3133 err_close_tirs: 3134 mlx5e_close_tirs(priv); 3135 3136 err_close_rqls: 3137 mlx5e_close_rqt(priv); 3138 3139 err_close_channels: 3140 mlx5e_close_channels(priv); 3141 3142 err_dalloc_q_counter: 3143 mlx5_vport_dealloc_q_counter(priv->mdev, 3144 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 3145 3146 err_close_tises: 3147 mlx5e_close_tises(priv); 3148 3149 return (err); 3150 } 3151 3152 static void 3153 mlx5e_open(void *arg) 3154 { 3155 struct mlx5e_priv *priv = arg; 3156 3157 PRIV_LOCK(priv); 3158 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP)) 3159 mlx5_en_err(priv->ifp, 3160 "Setting port status to up failed\n"); 3161 3162 mlx5e_open_locked(priv->ifp); 3163 priv->ifp->if_drv_flags |= IFF_DRV_RUNNING; 3164 PRIV_UNLOCK(priv); 3165 } 3166 3167 int 3168 mlx5e_close_locked(struct ifnet *ifp) 3169 { 3170 struct mlx5e_priv *priv = ifp->if_softc; 3171 3172 /* check if already closed */ 3173 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3174 return (0); 3175 3176 clear_bit(MLX5E_STATE_OPENED, &priv->state); 3177 3178 mlx5e_set_rx_mode_core(priv); 3179 mlx5e_del_all_vlan_rules(priv); 3180 if_link_state_change(priv->ifp, LINK_STATE_DOWN); 3181 mlx5e_close_flow_table(priv); 3182 mlx5e_close_tirs(priv); 3183 mlx5e_close_rqt(priv); 3184 mlx5e_close_channels(priv); 3185 mlx5_vport_dealloc_q_counter(priv->mdev, 3186 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 3187 mlx5e_close_tises(priv); 3188 3189 return (0); 3190 } 3191 3192 #if (__FreeBSD_version >= 1100000) 3193 static uint64_t 3194 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt) 3195 { 3196 struct mlx5e_priv *priv = ifp->if_softc; 3197 u64 retval; 3198 3199 /* PRIV_LOCK(priv); XXX not allowed */ 3200 switch (cnt) { 3201 case IFCOUNTER_IPACKETS: 3202 retval = priv->stats.vport.rx_packets; 3203 break; 3204 case IFCOUNTER_IERRORS: 3205 retval = priv->stats.pport.in_range_len_errors + 3206 priv->stats.pport.out_of_range_len + 3207 priv->stats.pport.too_long_errors + 3208 priv->stats.pport.check_seq_err + 3209 priv->stats.pport.alignment_err; 3210 break; 3211 case IFCOUNTER_IQDROPS: 3212 retval = priv->stats.vport.rx_out_of_buffer; 3213 break; 3214 case IFCOUNTER_OPACKETS: 3215 retval = priv->stats.vport.tx_packets; 3216 break; 3217 case IFCOUNTER_OERRORS: 3218 retval = priv->stats.port_stats_debug.out_discards; 3219 break; 3220 case IFCOUNTER_IBYTES: 3221 retval = priv->stats.vport.rx_bytes; 3222 break; 3223 case IFCOUNTER_OBYTES: 3224 retval = priv->stats.vport.tx_bytes; 3225 break; 3226 case IFCOUNTER_IMCASTS: 3227 retval = priv->stats.vport.rx_multicast_packets; 3228 break; 3229 case IFCOUNTER_OMCASTS: 3230 retval = priv->stats.vport.tx_multicast_packets; 3231 break; 3232 case IFCOUNTER_OQDROPS: 3233 retval = priv->stats.vport.tx_queue_dropped; 3234 break; 3235 case IFCOUNTER_COLLISIONS: 3236 retval = priv->stats.pport.collisions; 3237 break; 3238 default: 3239 retval = if_get_counter_default(ifp, cnt); 3240 break; 3241 } 3242 /* PRIV_UNLOCK(priv); XXX not allowed */ 3243 return (retval); 3244 } 3245 #endif 3246 3247 static void 3248 mlx5e_set_rx_mode(struct ifnet *ifp) 3249 { 3250 struct mlx5e_priv *priv = ifp->if_softc; 3251 3252 queue_work(priv->wq, &priv->set_rx_mode_work); 3253 } 3254 3255 static int 3256 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3257 { 3258 struct mlx5e_priv *priv; 3259 struct ifreq *ifr; 3260 struct ifdownreason *ifdr; 3261 struct ifi2creq i2c; 3262 int error = 0; 3263 int mask = 0; 3264 int size_read = 0; 3265 int module_status; 3266 int module_num; 3267 int max_mtu; 3268 uint8_t read_addr; 3269 3270 priv = ifp->if_softc; 3271 3272 /* check if detaching */ 3273 if (priv == NULL || priv->gone != 0) 3274 return (ENXIO); 3275 3276 switch (command) { 3277 case SIOCSIFMTU: 3278 ifr = (struct ifreq *)data; 3279 3280 PRIV_LOCK(priv); 3281 mlx5_query_port_max_mtu(priv->mdev, &max_mtu); 3282 3283 if (ifr->ifr_mtu >= MLX5E_MTU_MIN && 3284 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) { 3285 int was_opened; 3286 3287 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 3288 if (was_opened) 3289 mlx5e_close_locked(ifp); 3290 3291 /* set new MTU */ 3292 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu); 3293 3294 if (was_opened) 3295 mlx5e_open_locked(ifp); 3296 } else { 3297 error = EINVAL; 3298 mlx5_en_err(ifp, 3299 "Invalid MTU value. Min val: %d, Max val: %d\n", 3300 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu)); 3301 } 3302 PRIV_UNLOCK(priv); 3303 break; 3304 case SIOCSIFFLAGS: 3305 if ((ifp->if_flags & IFF_UP) && 3306 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3307 mlx5e_set_rx_mode(ifp); 3308 break; 3309 } 3310 PRIV_LOCK(priv); 3311 if (ifp->if_flags & IFF_UP) { 3312 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3313 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3314 mlx5e_open_locked(ifp); 3315 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3316 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP); 3317 } 3318 } else { 3319 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3320 mlx5_set_port_status(priv->mdev, 3321 MLX5_PORT_DOWN); 3322 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 3323 mlx5e_close_locked(ifp); 3324 mlx5e_update_carrier(priv); 3325 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3326 } 3327 } 3328 PRIV_UNLOCK(priv); 3329 break; 3330 case SIOCADDMULTI: 3331 case SIOCDELMULTI: 3332 mlx5e_set_rx_mode(ifp); 3333 break; 3334 case SIOCSIFMEDIA: 3335 case SIOCGIFMEDIA: 3336 case SIOCGIFXMEDIA: 3337 ifr = (struct ifreq *)data; 3338 error = ifmedia_ioctl(ifp, ifr, &priv->media, command); 3339 break; 3340 case SIOCSIFCAP: 3341 ifr = (struct ifreq *)data; 3342 PRIV_LOCK(priv); 3343 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3344 3345 if (mask & IFCAP_TXCSUM) { 3346 ifp->if_capenable ^= IFCAP_TXCSUM; 3347 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 3348 3349 if (IFCAP_TSO4 & ifp->if_capenable && 3350 !(IFCAP_TXCSUM & ifp->if_capenable)) { 3351 mask &= ~IFCAP_TSO4; 3352 ifp->if_capenable &= ~IFCAP_TSO4; 3353 ifp->if_hwassist &= ~CSUM_IP_TSO; 3354 mlx5_en_err(ifp, 3355 "tso4 disabled due to -txcsum.\n"); 3356 } 3357 } 3358 if (mask & IFCAP_TXCSUM_IPV6) { 3359 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 3360 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 3361 3362 if (IFCAP_TSO6 & ifp->if_capenable && 3363 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 3364 mask &= ~IFCAP_TSO6; 3365 ifp->if_capenable &= ~IFCAP_TSO6; 3366 ifp->if_hwassist &= ~CSUM_IP6_TSO; 3367 mlx5_en_err(ifp, 3368 "tso6 disabled due to -txcsum6.\n"); 3369 } 3370 } 3371 if (mask & IFCAP_NOMAP) 3372 ifp->if_capenable ^= IFCAP_NOMAP; 3373 if (mask & IFCAP_TXTLS4) 3374 ifp->if_capenable ^= IFCAP_TXTLS4; 3375 if (mask & IFCAP_TXTLS6) 3376 ifp->if_capenable ^= IFCAP_TXTLS6; 3377 #ifdef RATELIMIT 3378 if (mask & IFCAP_TXTLS_RTLMT) 3379 ifp->if_capenable ^= IFCAP_TXTLS_RTLMT; 3380 #endif 3381 if (mask & IFCAP_RXCSUM) 3382 ifp->if_capenable ^= IFCAP_RXCSUM; 3383 if (mask & IFCAP_RXCSUM_IPV6) 3384 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 3385 if (mask & IFCAP_TSO4) { 3386 if (!(IFCAP_TSO4 & ifp->if_capenable) && 3387 !(IFCAP_TXCSUM & ifp->if_capenable)) { 3388 mlx5_en_err(ifp, "enable txcsum first.\n"); 3389 error = EAGAIN; 3390 goto out; 3391 } 3392 ifp->if_capenable ^= IFCAP_TSO4; 3393 ifp->if_hwassist ^= CSUM_IP_TSO; 3394 } 3395 if (mask & IFCAP_TSO6) { 3396 if (!(IFCAP_TSO6 & ifp->if_capenable) && 3397 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 3398 mlx5_en_err(ifp, "enable txcsum6 first.\n"); 3399 error = EAGAIN; 3400 goto out; 3401 } 3402 ifp->if_capenable ^= IFCAP_TSO6; 3403 ifp->if_hwassist ^= CSUM_IP6_TSO; 3404 } 3405 if (mask & IFCAP_VLAN_HWFILTER) { 3406 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) 3407 mlx5e_disable_vlan_filter(priv); 3408 else 3409 mlx5e_enable_vlan_filter(priv); 3410 3411 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER; 3412 } 3413 if (mask & IFCAP_VLAN_HWTAGGING) 3414 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3415 if (mask & IFCAP_WOL_MAGIC) 3416 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3417 3418 VLAN_CAPABILITIES(ifp); 3419 /* turn off LRO means also turn of HW LRO - if it's on */ 3420 if (mask & IFCAP_LRO) { 3421 int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 3422 bool need_restart = false; 3423 3424 ifp->if_capenable ^= IFCAP_LRO; 3425 3426 /* figure out if updating HW LRO is needed */ 3427 if (!(ifp->if_capenable & IFCAP_LRO)) { 3428 if (priv->params.hw_lro_en) { 3429 priv->params.hw_lro_en = false; 3430 need_restart = true; 3431 } 3432 } else { 3433 if (priv->params.hw_lro_en == false && 3434 priv->params_ethtool.hw_lro != 0) { 3435 priv->params.hw_lro_en = true; 3436 need_restart = true; 3437 } 3438 } 3439 if (was_opened && need_restart) { 3440 mlx5e_close_locked(ifp); 3441 mlx5e_open_locked(ifp); 3442 } 3443 } 3444 if (mask & IFCAP_HWRXTSTMP) { 3445 ifp->if_capenable ^= IFCAP_HWRXTSTMP; 3446 if (ifp->if_capenable & IFCAP_HWRXTSTMP) { 3447 if (priv->clbr_done == 0) 3448 mlx5e_reset_calibration_callout(priv); 3449 } else { 3450 callout_drain(&priv->tstmp_clbr); 3451 priv->clbr_done = 0; 3452 } 3453 } 3454 out: 3455 PRIV_UNLOCK(priv); 3456 break; 3457 3458 case SIOCGI2C: 3459 ifr = (struct ifreq *)data; 3460 3461 /* 3462 * Copy from the user-space address ifr_data to the 3463 * kernel-space address i2c 3464 */ 3465 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 3466 if (error) 3467 break; 3468 3469 if (i2c.len > sizeof(i2c.data)) { 3470 error = EINVAL; 3471 break; 3472 } 3473 3474 PRIV_LOCK(priv); 3475 /* Get module_num which is required for the query_eeprom */ 3476 error = mlx5_query_module_num(priv->mdev, &module_num); 3477 if (error) { 3478 mlx5_en_err(ifp, 3479 "Query module num failed, eeprom reading is not supported\n"); 3480 error = EINVAL; 3481 goto err_i2c; 3482 } 3483 /* Check if module is present before doing an access */ 3484 module_status = mlx5_query_module_status(priv->mdev, module_num); 3485 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED) { 3486 error = EINVAL; 3487 goto err_i2c; 3488 } 3489 /* 3490 * Currently 0XA0 and 0xA2 are the only addresses permitted. 3491 * The internal conversion is as follows: 3492 */ 3493 if (i2c.dev_addr == 0xA0) 3494 read_addr = MLX5_I2C_ADDR_LOW; 3495 else if (i2c.dev_addr == 0xA2) 3496 read_addr = MLX5_I2C_ADDR_HIGH; 3497 else { 3498 mlx5_en_err(ifp, 3499 "Query eeprom failed, Invalid Address: %X\n", 3500 i2c.dev_addr); 3501 error = EINVAL; 3502 goto err_i2c; 3503 } 3504 error = mlx5_query_eeprom(priv->mdev, 3505 read_addr, MLX5_EEPROM_LOW_PAGE, 3506 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num, 3507 (uint32_t *)i2c.data, &size_read); 3508 if (error) { 3509 mlx5_en_err(ifp, 3510 "Query eeprom failed, eeprom reading is not supported\n"); 3511 error = EINVAL; 3512 goto err_i2c; 3513 } 3514 3515 if (i2c.len > MLX5_EEPROM_MAX_BYTES) { 3516 error = mlx5_query_eeprom(priv->mdev, 3517 read_addr, MLX5_EEPROM_LOW_PAGE, 3518 (uint32_t)(i2c.offset + size_read), 3519 (uint32_t)(i2c.len - size_read), module_num, 3520 (uint32_t *)(i2c.data + size_read), &size_read); 3521 } 3522 if (error) { 3523 mlx5_en_err(ifp, 3524 "Query eeprom failed, eeprom reading is not supported\n"); 3525 error = EINVAL; 3526 goto err_i2c; 3527 } 3528 3529 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 3530 err_i2c: 3531 PRIV_UNLOCK(priv); 3532 break; 3533 case SIOCGIFDOWNREASON: 3534 ifdr = (struct ifdownreason *)data; 3535 bzero(ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg)); 3536 PRIV_LOCK(priv); 3537 error = -mlx5_query_pddr_troubleshooting_info(priv->mdev, NULL, 3538 ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg)); 3539 PRIV_UNLOCK(priv); 3540 if (error == 0) 3541 ifdr->ifdr_reason = IFDR_REASON_MSG; 3542 break; 3543 3544 default: 3545 error = ether_ioctl(ifp, command, data); 3546 break; 3547 } 3548 return (error); 3549 } 3550 3551 static int 3552 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev) 3553 { 3554 /* 3555 * TODO: uncoment once FW really sets all these bits if 3556 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap || 3557 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap || 3558 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return 3559 * -ENOTSUPP; 3560 */ 3561 3562 /* TODO: add more must-to-have features */ 3563 3564 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) 3565 return (-ENODEV); 3566 3567 return (0); 3568 } 3569 3570 static u16 3571 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev) 3572 { 3573 const int min_size = ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN; 3574 const int max_size = MLX5E_MAX_TX_INLINE; 3575 const int bf_buf_size = 3576 ((1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U) - 3577 (sizeof(struct mlx5e_tx_wqe) - 2); 3578 3579 /* verify against driver limits */ 3580 if (bf_buf_size > max_size) 3581 return (max_size); 3582 else if (bf_buf_size < min_size) 3583 return (min_size); 3584 else 3585 return (bf_buf_size); 3586 } 3587 3588 static int 3589 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev, 3590 struct mlx5e_priv *priv, 3591 int num_comp_vectors) 3592 { 3593 int err; 3594 3595 /* 3596 * TODO: Consider link speed for setting "log_sq_size", 3597 * "log_rq_size" and "cq_moderation_xxx": 3598 */ 3599 priv->params.log_sq_size = 3600 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; 3601 priv->params.log_rq_size = 3602 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; 3603 priv->params.rx_cq_moderation_usec = 3604 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 3605 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE : 3606 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; 3607 priv->params.rx_cq_moderation_mode = 3608 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0; 3609 priv->params.rx_cq_moderation_pkts = 3610 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; 3611 priv->params.tx_cq_moderation_usec = 3612 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; 3613 priv->params.tx_cq_moderation_pkts = 3614 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; 3615 priv->params.min_rx_wqes = 3616 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES; 3617 priv->params.rx_hash_log_tbl_sz = 3618 (order_base_2(num_comp_vectors) > 3619 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ? 3620 order_base_2(num_comp_vectors) : 3621 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ; 3622 priv->params.num_tc = 1; 3623 priv->params.default_vlan_prio = 0; 3624 priv->counter_set_id = -1; 3625 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev); 3626 3627 err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode); 3628 if (err) 3629 return (err); 3630 3631 /* 3632 * hw lro is currently defaulted to off. when it won't anymore we 3633 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)" 3634 */ 3635 priv->params.hw_lro_en = false; 3636 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; 3637 3638 /* 3639 * CQE zipping is currently defaulted to off. when it won't 3640 * anymore we will consider the HW capability: 3641 * "!!MLX5_CAP_GEN(mdev, cqe_compression)" 3642 */ 3643 priv->params.cqe_zipping_en = false; 3644 3645 priv->mdev = mdev; 3646 priv->params.num_channels = num_comp_vectors; 3647 priv->params.channels_rsss = 1; 3648 priv->order_base_2_num_channels = order_base_2(num_comp_vectors); 3649 priv->queue_mapping_channel_mask = 3650 roundup_pow_of_two(num_comp_vectors) - 1; 3651 priv->num_tc = priv->params.num_tc; 3652 priv->default_vlan_prio = priv->params.default_vlan_prio; 3653 3654 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work); 3655 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); 3656 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); 3657 3658 return (0); 3659 } 3660 3661 static int 3662 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn, 3663 struct mlx5_core_mr *mkey) 3664 { 3665 struct ifnet *ifp = priv->ifp; 3666 struct mlx5_core_dev *mdev = priv->mdev; 3667 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 3668 void *mkc; 3669 u32 *in; 3670 int err; 3671 3672 in = mlx5_vzalloc(inlen); 3673 if (in == NULL) { 3674 mlx5_en_err(ifp, "failed to allocate inbox\n"); 3675 return (-ENOMEM); 3676 } 3677 3678 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 3679 MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA); 3680 MLX5_SET(mkc, mkc, umr_en, 1); /* used by HW TLS */ 3681 MLX5_SET(mkc, mkc, lw, 1); 3682 MLX5_SET(mkc, mkc, lr, 1); 3683 3684 MLX5_SET(mkc, mkc, pd, pdn); 3685 MLX5_SET(mkc, mkc, length64, 1); 3686 MLX5_SET(mkc, mkc, qpn, 0xffffff); 3687 3688 err = mlx5_core_create_mkey(mdev, mkey, in, inlen); 3689 if (err) 3690 mlx5_en_err(ifp, "mlx5_core_create_mkey failed, %d\n", 3691 err); 3692 3693 kvfree(in); 3694 return (err); 3695 } 3696 3697 static const char *mlx5e_vport_stats_desc[] = { 3698 MLX5E_VPORT_STATS(MLX5E_STATS_DESC) 3699 }; 3700 3701 static const char *mlx5e_pport_stats_desc[] = { 3702 MLX5E_PPORT_STATS(MLX5E_STATS_DESC) 3703 }; 3704 3705 static void 3706 mlx5e_priv_static_init(struct mlx5e_priv *priv, const uint32_t channels) 3707 { 3708 uint32_t x; 3709 3710 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF); 3711 sx_init(&priv->state_lock, "mlx5state"); 3712 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0); 3713 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock); 3714 for (x = 0; x != channels; x++) 3715 mlx5e_chan_static_init(priv, &priv->channel[x], x); 3716 } 3717 3718 static void 3719 mlx5e_priv_static_destroy(struct mlx5e_priv *priv, const uint32_t channels) 3720 { 3721 uint32_t x; 3722 3723 for (x = 0; x != channels; x++) 3724 mlx5e_chan_static_destroy(&priv->channel[x]); 3725 callout_drain(&priv->watchdog); 3726 mtx_destroy(&priv->async_events_mtx); 3727 sx_destroy(&priv->state_lock); 3728 } 3729 3730 static int 3731 sysctl_firmware(SYSCTL_HANDLER_ARGS) 3732 { 3733 /* 3734 * %d.%d%.d the string format. 3735 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536. 3736 * We need at most 5 chars to store that. 3737 * It also has: two "." and NULL at the end, which means we need 18 3738 * (5*3 + 3) chars at most. 3739 */ 3740 char fw[18]; 3741 struct mlx5e_priv *priv = arg1; 3742 int error; 3743 3744 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev), 3745 fw_rev_sub(priv->mdev)); 3746 error = sysctl_handle_string(oidp, fw, sizeof(fw), req); 3747 return (error); 3748 } 3749 3750 static void 3751 mlx5e_disable_tx_dma(struct mlx5e_channel *ch) 3752 { 3753 int i; 3754 3755 for (i = 0; i < ch->priv->num_tc; i++) 3756 mlx5e_drain_sq(&ch->sq[i]); 3757 } 3758 3759 static void 3760 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq) 3761 { 3762 3763 sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP); 3764 sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8); 3765 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0); 3766 sq->doorbell.d64 = 0; 3767 } 3768 3769 void 3770 mlx5e_resume_sq(struct mlx5e_sq *sq) 3771 { 3772 int err; 3773 3774 /* check if already enabled */ 3775 if (READ_ONCE(sq->running) != 0) 3776 return; 3777 3778 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR, 3779 MLX5_SQC_STATE_RST); 3780 if (err != 0) { 3781 mlx5_en_err(sq->ifp, 3782 "mlx5e_modify_sq() from ERR to RST failed: %d\n", err); 3783 } 3784 3785 sq->cc = 0; 3786 sq->pc = 0; 3787 3788 /* reset doorbell prior to moving from RST to RDY */ 3789 mlx5e_reset_sq_doorbell_record(sq); 3790 3791 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, 3792 MLX5_SQC_STATE_RDY); 3793 if (err != 0) { 3794 mlx5_en_err(sq->ifp, 3795 "mlx5e_modify_sq() from RST to RDY failed: %d\n", err); 3796 } 3797 3798 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL; 3799 WRITE_ONCE(sq->running, 1); 3800 } 3801 3802 static void 3803 mlx5e_enable_tx_dma(struct mlx5e_channel *ch) 3804 { 3805 int i; 3806 3807 for (i = 0; i < ch->priv->num_tc; i++) 3808 mlx5e_resume_sq(&ch->sq[i]); 3809 } 3810 3811 static void 3812 mlx5e_disable_rx_dma(struct mlx5e_channel *ch) 3813 { 3814 struct mlx5e_rq *rq = &ch->rq; 3815 struct epoch_tracker et; 3816 int err; 3817 3818 mtx_lock(&rq->mtx); 3819 rq->enabled = 0; 3820 callout_stop(&rq->watchdog); 3821 mtx_unlock(&rq->mtx); 3822 3823 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 3824 if (err != 0) { 3825 mlx5_en_err(rq->ifp, 3826 "mlx5e_modify_rq() from RDY to RST failed: %d\n", err); 3827 } 3828 3829 while (!mlx5_wq_ll_is_empty(&rq->wq)) { 3830 msleep(1); 3831 NET_EPOCH_ENTER(et); 3832 rq->cq.mcq.comp(&rq->cq.mcq, NULL); 3833 NET_EPOCH_EXIT(et); 3834 } 3835 3836 /* 3837 * Transitioning into RST state will allow the FW to track less ERR state queues, 3838 * thus reducing the recv queue flushing time 3839 */ 3840 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST); 3841 if (err != 0) { 3842 mlx5_en_err(rq->ifp, 3843 "mlx5e_modify_rq() from ERR to RST failed: %d\n", err); 3844 } 3845 } 3846 3847 static void 3848 mlx5e_enable_rx_dma(struct mlx5e_channel *ch) 3849 { 3850 struct mlx5e_rq *rq = &ch->rq; 3851 struct epoch_tracker et; 3852 int err; 3853 3854 rq->wq.wqe_ctr = 0; 3855 mlx5_wq_ll_update_db_record(&rq->wq); 3856 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 3857 if (err != 0) { 3858 mlx5_en_err(rq->ifp, 3859 "mlx5e_modify_rq() from RST to RDY failed: %d\n", err); 3860 } 3861 3862 rq->enabled = 1; 3863 3864 NET_EPOCH_ENTER(et); 3865 rq->cq.mcq.comp(&rq->cq.mcq, NULL); 3866 NET_EPOCH_EXIT(et); 3867 } 3868 3869 void 3870 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value) 3871 { 3872 int i; 3873 3874 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3875 return; 3876 3877 for (i = 0; i < priv->params.num_channels; i++) { 3878 if (value) 3879 mlx5e_disable_tx_dma(&priv->channel[i]); 3880 else 3881 mlx5e_enable_tx_dma(&priv->channel[i]); 3882 } 3883 } 3884 3885 void 3886 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value) 3887 { 3888 int i; 3889 3890 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3891 return; 3892 3893 for (i = 0; i < priv->params.num_channels; i++) { 3894 if (value) 3895 mlx5e_disable_rx_dma(&priv->channel[i]); 3896 else 3897 mlx5e_enable_rx_dma(&priv->channel[i]); 3898 } 3899 } 3900 3901 static void 3902 mlx5e_add_hw_stats(struct mlx5e_priv *priv) 3903 { 3904 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 3905 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 3906 priv, 0, sysctl_firmware, "A", "HCA firmware version"); 3907 3908 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 3909 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0, 3910 "Board ID"); 3911 } 3912 3913 static int 3914 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS) 3915 { 3916 struct mlx5e_priv *priv = arg1; 3917 uint8_t temp[MLX5E_MAX_PRIORITY]; 3918 uint32_t tx_pfc; 3919 int err; 3920 int i; 3921 3922 PRIV_LOCK(priv); 3923 3924 tx_pfc = priv->params.tx_priority_flow_control; 3925 3926 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) 3927 temp[i] = (tx_pfc >> i) & 1; 3928 3929 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY); 3930 if (err || !req->newptr) 3931 goto done; 3932 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY); 3933 if (err) 3934 goto done; 3935 3936 priv->params.tx_priority_flow_control = 0; 3937 3938 /* range check input value */ 3939 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) { 3940 if (temp[i] > 1) { 3941 err = ERANGE; 3942 goto done; 3943 } 3944 priv->params.tx_priority_flow_control |= (temp[i] << i); 3945 } 3946 3947 /* check if update is required */ 3948 if (tx_pfc != priv->params.tx_priority_flow_control) 3949 err = -mlx5e_set_port_pfc(priv); 3950 done: 3951 if (err != 0) 3952 priv->params.tx_priority_flow_control= tx_pfc; 3953 PRIV_UNLOCK(priv); 3954 3955 return (err); 3956 } 3957 3958 static int 3959 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS) 3960 { 3961 struct mlx5e_priv *priv = arg1; 3962 uint8_t temp[MLX5E_MAX_PRIORITY]; 3963 uint32_t rx_pfc; 3964 int err; 3965 int i; 3966 3967 PRIV_LOCK(priv); 3968 3969 rx_pfc = priv->params.rx_priority_flow_control; 3970 3971 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) 3972 temp[i] = (rx_pfc >> i) & 1; 3973 3974 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY); 3975 if (err || !req->newptr) 3976 goto done; 3977 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY); 3978 if (err) 3979 goto done; 3980 3981 priv->params.rx_priority_flow_control = 0; 3982 3983 /* range check input value */ 3984 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) { 3985 if (temp[i] > 1) { 3986 err = ERANGE; 3987 goto done; 3988 } 3989 priv->params.rx_priority_flow_control |= (temp[i] << i); 3990 } 3991 3992 /* check if update is required */ 3993 if (rx_pfc != priv->params.rx_priority_flow_control) { 3994 err = -mlx5e_set_port_pfc(priv); 3995 if (err == 0 && priv->sw_is_port_buf_owner) 3996 err = mlx5e_update_buf_lossy(priv); 3997 } 3998 done: 3999 if (err != 0) 4000 priv->params.rx_priority_flow_control= rx_pfc; 4001 PRIV_UNLOCK(priv); 4002 4003 return (err); 4004 } 4005 4006 static void 4007 mlx5e_setup_pauseframes(struct mlx5e_priv *priv) 4008 { 4009 #if (__FreeBSD_version < 1100000) 4010 char path[96]; 4011 #endif 4012 int error; 4013 4014 /* enable pauseframes by default */ 4015 priv->params.tx_pauseframe_control = 1; 4016 priv->params.rx_pauseframe_control = 1; 4017 4018 /* disable ports flow control, PFC, by default */ 4019 priv->params.tx_priority_flow_control = 0; 4020 priv->params.rx_priority_flow_control = 0; 4021 4022 #if (__FreeBSD_version < 1100000) 4023 /* compute path for sysctl */ 4024 snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control", 4025 device_get_unit(priv->mdev->pdev->dev.bsddev)); 4026 4027 /* try to fetch tunable, if any */ 4028 TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control); 4029 4030 /* compute path for sysctl */ 4031 snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control", 4032 device_get_unit(priv->mdev->pdev->dev.bsddev)); 4033 4034 /* try to fetch tunable, if any */ 4035 TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control); 4036 #endif 4037 4038 /* register pauseframe SYSCTLs */ 4039 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4040 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN, 4041 &priv->params.tx_pauseframe_control, 0, 4042 "Set to enable TX pause frames. Clear to disable."); 4043 4044 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4045 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN, 4046 &priv->params.rx_pauseframe_control, 0, 4047 "Set to enable RX pause frames. Clear to disable."); 4048 4049 /* register priority flow control, PFC, SYSCTLs */ 4050 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4051 OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN | 4052 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU", 4053 "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable."); 4054 4055 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4056 OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN | 4057 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU", 4058 "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable."); 4059 4060 PRIV_LOCK(priv); 4061 4062 /* range check */ 4063 priv->params.tx_pauseframe_control = 4064 priv->params.tx_pauseframe_control ? 1 : 0; 4065 priv->params.rx_pauseframe_control = 4066 priv->params.rx_pauseframe_control ? 1 : 0; 4067 4068 /* update firmware */ 4069 error = mlx5e_set_port_pause_and_pfc(priv); 4070 if (error == -EINVAL) { 4071 mlx5_en_err(priv->ifp, 4072 "Global pauseframes must be disabled before enabling PFC.\n"); 4073 priv->params.rx_priority_flow_control = 0; 4074 priv->params.tx_priority_flow_control = 0; 4075 4076 /* update firmware */ 4077 (void) mlx5e_set_port_pause_and_pfc(priv); 4078 } 4079 PRIV_UNLOCK(priv); 4080 } 4081 4082 int 4083 mlx5e_ul_snd_tag_alloc(struct ifnet *ifp, 4084 union if_snd_tag_alloc_params *params, 4085 struct m_snd_tag **ppmt) 4086 { 4087 struct mlx5e_priv *priv; 4088 struct mlx5e_channel *pch; 4089 4090 priv = ifp->if_softc; 4091 4092 if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) { 4093 return (EOPNOTSUPP); 4094 } else { 4095 /* keep this code synced with mlx5e_select_queue() */ 4096 u32 ch = priv->params.num_channels; 4097 #ifdef RSS 4098 u32 temp; 4099 4100 if (rss_hash2bucket(params->hdr.flowid, 4101 params->hdr.flowtype, &temp) == 0) 4102 ch = temp % ch; 4103 else 4104 #endif 4105 ch = (params->hdr.flowid % 128) % ch; 4106 4107 /* 4108 * NOTE: The channels array is only freed at detach 4109 * and it safe to return a pointer to the send tag 4110 * inside the channels structure as long as we 4111 * reference the priv. 4112 */ 4113 pch = priv->channel + ch; 4114 4115 /* check if send queue is not running */ 4116 if (unlikely(pch->sq[0].running == 0)) 4117 return (ENXIO); 4118 m_snd_tag_ref(&pch->tag); 4119 *ppmt = &pch->tag; 4120 return (0); 4121 } 4122 } 4123 4124 int 4125 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params) 4126 { 4127 struct mlx5e_channel *pch = 4128 container_of(pmt, struct mlx5e_channel, tag); 4129 4130 params->unlimited.max_rate = -1ULL; 4131 params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]); 4132 return (0); 4133 } 4134 4135 void 4136 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt) 4137 { 4138 struct mlx5e_channel *pch = 4139 container_of(pmt, struct mlx5e_channel, tag); 4140 4141 complete(&pch->completion); 4142 } 4143 4144 static int 4145 mlx5e_snd_tag_alloc(struct ifnet *ifp, 4146 union if_snd_tag_alloc_params *params, 4147 struct m_snd_tag **ppmt) 4148 { 4149 4150 switch (params->hdr.type) { 4151 #ifdef RATELIMIT 4152 case IF_SND_TAG_TYPE_RATE_LIMIT: 4153 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt)); 4154 #ifdef KERN_TLS 4155 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT: 4156 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt)); 4157 #endif 4158 #endif 4159 case IF_SND_TAG_TYPE_UNLIMITED: 4160 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt)); 4161 #ifdef KERN_TLS 4162 case IF_SND_TAG_TYPE_TLS: 4163 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt)); 4164 #endif 4165 default: 4166 return (EOPNOTSUPP); 4167 } 4168 } 4169 4170 static int 4171 mlx5e_snd_tag_modify(struct m_snd_tag *pmt, union if_snd_tag_modify_params *params) 4172 { 4173 4174 switch (pmt->type) { 4175 #ifdef RATELIMIT 4176 case IF_SND_TAG_TYPE_RATE_LIMIT: 4177 return (mlx5e_rl_snd_tag_modify(pmt, params)); 4178 #ifdef KERN_TLS 4179 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT: 4180 return (mlx5e_tls_snd_tag_modify(pmt, params)); 4181 #endif 4182 #endif 4183 case IF_SND_TAG_TYPE_UNLIMITED: 4184 #ifdef KERN_TLS 4185 case IF_SND_TAG_TYPE_TLS: 4186 #endif 4187 default: 4188 return (EOPNOTSUPP); 4189 } 4190 } 4191 4192 static int 4193 mlx5e_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params) 4194 { 4195 4196 switch (pmt->type) { 4197 #ifdef RATELIMIT 4198 case IF_SND_TAG_TYPE_RATE_LIMIT: 4199 return (mlx5e_rl_snd_tag_query(pmt, params)); 4200 #ifdef KERN_TLS 4201 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT: 4202 return (mlx5e_tls_snd_tag_query(pmt, params)); 4203 #endif 4204 #endif 4205 case IF_SND_TAG_TYPE_UNLIMITED: 4206 return (mlx5e_ul_snd_tag_query(pmt, params)); 4207 #ifdef KERN_TLS 4208 case IF_SND_TAG_TYPE_TLS: 4209 return (mlx5e_tls_snd_tag_query(pmt, params)); 4210 #endif 4211 default: 4212 return (EOPNOTSUPP); 4213 } 4214 } 4215 4216 #ifdef RATELIMIT 4217 #define NUM_HDWR_RATES_MLX 13 4218 static const uint64_t adapter_rates_mlx[NUM_HDWR_RATES_MLX] = { 4219 135375, /* 1,083,000 */ 4220 180500, /* 1,444,000 */ 4221 270750, /* 2,166,000 */ 4222 361000, /* 2,888,000 */ 4223 541500, /* 4,332,000 */ 4224 721875, /* 5,775,000 */ 4225 1082875, /* 8,663,000 */ 4226 1443875, /* 11,551,000 */ 4227 2165750, /* 17,326,000 */ 4228 2887750, /* 23,102,000 */ 4229 4331625, /* 34,653,000 */ 4230 5775500, /* 46,204,000 */ 4231 8663125 /* 69,305,000 */ 4232 }; 4233 4234 static void 4235 mlx5e_ratelimit_query(struct ifnet *ifp __unused, struct if_ratelimit_query_results *q) 4236 { 4237 /* 4238 * This function needs updating by the driver maintainer! 4239 * For the MLX card there are currently (ConectX-4?) 13 4240 * pre-set rates and others i.e. ConnectX-5, 6, 7?? 4241 * 4242 * This will change based on later adapters 4243 * and this code should be updated to look at ifp 4244 * and figure out the specific adapter type 4245 * settings i.e. how many rates as well 4246 * as if they are fixed (as is shown here) or 4247 * if they are dynamic (example chelsio t4). Also if there 4248 * is a maximum number of flows that the adapter 4249 * can handle that too needs to be updated in 4250 * the max_flows field. 4251 */ 4252 q->rate_table = adapter_rates_mlx; 4253 q->flags = RT_IS_FIXED_TABLE; 4254 q->max_flows = 0; /* mlx has no limit */ 4255 q->number_of_rates = NUM_HDWR_RATES_MLX; 4256 q->min_segment_burst = 1; 4257 } 4258 #endif 4259 4260 static void 4261 mlx5e_snd_tag_free(struct m_snd_tag *pmt) 4262 { 4263 4264 switch (pmt->type) { 4265 #ifdef RATELIMIT 4266 case IF_SND_TAG_TYPE_RATE_LIMIT: 4267 mlx5e_rl_snd_tag_free(pmt); 4268 break; 4269 #ifdef KERN_TLS 4270 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT: 4271 mlx5e_tls_snd_tag_free(pmt); 4272 break; 4273 #endif 4274 #endif 4275 case IF_SND_TAG_TYPE_UNLIMITED: 4276 mlx5e_ul_snd_tag_free(pmt); 4277 break; 4278 #ifdef KERN_TLS 4279 case IF_SND_TAG_TYPE_TLS: 4280 mlx5e_tls_snd_tag_free(pmt); 4281 break; 4282 #endif 4283 default: 4284 break; 4285 } 4286 } 4287 4288 static void 4289 mlx5e_ifm_add(struct mlx5e_priv *priv, int type) 4290 { 4291 ifmedia_add(&priv->media, type | IFM_ETHER, 0, NULL); 4292 ifmedia_add(&priv->media, type | IFM_ETHER | 4293 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 4294 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_RXPAUSE, 0, NULL); 4295 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_TXPAUSE, 0, NULL); 4296 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX, 0, NULL); 4297 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX | 4298 IFM_ETH_RXPAUSE, 0, NULL); 4299 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX | 4300 IFM_ETH_TXPAUSE, 0, NULL); 4301 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX | 4302 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 4303 } 4304 4305 static void * 4306 mlx5e_create_ifp(struct mlx5_core_dev *mdev) 4307 { 4308 struct ifnet *ifp; 4309 struct mlx5e_priv *priv; 4310 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4); 4311 u8 connector_type; 4312 struct sysctl_oid_list *child; 4313 int ncv = mdev->priv.eq_table.num_comp_vectors; 4314 char unit[16]; 4315 struct pfil_head_args pa; 4316 int err; 4317 int i,j; 4318 u32 eth_proto_cap; 4319 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 4320 bool ext = 0; 4321 u32 speeds_num; 4322 struct media media_entry = {}; 4323 4324 if (mlx5e_check_required_hca_cap(mdev)) { 4325 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n"); 4326 return (NULL); 4327 } 4328 /* 4329 * Try to allocate the priv and make room for worst-case 4330 * number of channel structures: 4331 */ 4332 priv = malloc(sizeof(*priv) + 4333 (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors), 4334 M_MLX5EN, M_WAITOK | M_ZERO); 4335 4336 ifp = priv->ifp = if_alloc_dev(IFT_ETHER, mdev->pdev->dev.bsddev); 4337 if (ifp == NULL) { 4338 mlx5_core_err(mdev, "if_alloc() failed\n"); 4339 goto err_free_priv; 4340 } 4341 /* setup all static fields */ 4342 mlx5e_priv_static_init(priv, mdev->priv.eq_table.num_comp_vectors); 4343 4344 ifp->if_softc = priv; 4345 if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev)); 4346 ifp->if_mtu = ETHERMTU; 4347 ifp->if_init = mlx5e_open; 4348 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 4349 IFF_KNOWSEPOCH; 4350 ifp->if_ioctl = mlx5e_ioctl; 4351 ifp->if_transmit = mlx5e_xmit; 4352 ifp->if_qflush = if_qflush; 4353 #if (__FreeBSD_version >= 1100000) 4354 ifp->if_get_counter = mlx5e_get_counter; 4355 #endif 4356 ifp->if_snd.ifq_maxlen = ifqmaxlen; 4357 /* 4358 * Set driver features 4359 */ 4360 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6; 4361 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 4362 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER; 4363 ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU; 4364 ifp->if_capabilities |= IFCAP_LRO; 4365 ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO; 4366 ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP; 4367 ifp->if_capabilities |= IFCAP_NOMAP; 4368 ifp->if_capabilities |= IFCAP_TXTLS4 | IFCAP_TXTLS6; 4369 #ifdef RATELIMIT 4370 ifp->if_capabilities |= IFCAP_TXRTLMT | IFCAP_TXTLS_RTLMT; 4371 #endif 4372 ifp->if_snd_tag_alloc = mlx5e_snd_tag_alloc; 4373 ifp->if_snd_tag_free = mlx5e_snd_tag_free; 4374 ifp->if_snd_tag_modify = mlx5e_snd_tag_modify; 4375 ifp->if_snd_tag_query = mlx5e_snd_tag_query; 4376 #ifdef RATELIMIT 4377 ifp->if_ratelimit_query = mlx5e_ratelimit_query; 4378 #endif 4379 /* set TSO limits so that we don't have to drop TX packets */ 4380 ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 4381 ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */; 4382 ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE; 4383 4384 ifp->if_capenable = ifp->if_capabilities; 4385 ifp->if_hwassist = 0; 4386 if (ifp->if_capenable & IFCAP_TSO) 4387 ifp->if_hwassist |= CSUM_TSO; 4388 if (ifp->if_capenable & IFCAP_TXCSUM) 4389 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP); 4390 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6) 4391 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 4392 4393 /* ifnet sysctl tree */ 4394 sysctl_ctx_init(&priv->sysctl_ctx); 4395 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev), 4396 OID_AUTO, ifp->if_dname, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 4397 "MLX5 ethernet - interface name"); 4398 if (priv->sysctl_ifnet == NULL) { 4399 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4400 goto err_free_sysctl; 4401 } 4402 snprintf(unit, sizeof(unit), "%d", ifp->if_dunit); 4403 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4404 OID_AUTO, unit, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 4405 "MLX5 ethernet - interface unit"); 4406 if (priv->sysctl_ifnet == NULL) { 4407 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4408 goto err_free_sysctl; 4409 } 4410 4411 /* HW sysctl tree */ 4412 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev)); 4413 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child, 4414 OID_AUTO, "hw", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 4415 "MLX5 ethernet dev hw"); 4416 if (priv->sysctl_hw == NULL) { 4417 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4418 goto err_free_sysctl; 4419 } 4420 4421 err = mlx5e_build_ifp_priv(mdev, priv, ncv); 4422 if (err) { 4423 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err); 4424 goto err_free_sysctl; 4425 } 4426 4427 /* reuse mlx5core's watchdog workqueue */ 4428 priv->wq = mdev->priv.health.wq_watchdog; 4429 4430 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar); 4431 if (err) { 4432 mlx5_en_err(ifp, "mlx5_alloc_map_uar failed, %d\n", err); 4433 goto err_free_wq; 4434 } 4435 err = mlx5_core_alloc_pd(mdev, &priv->pdn); 4436 if (err) { 4437 mlx5_en_err(ifp, "mlx5_core_alloc_pd failed, %d\n", err); 4438 goto err_unmap_free_uar; 4439 } 4440 err = mlx5_alloc_transport_domain(mdev, &priv->tdn); 4441 if (err) { 4442 mlx5_en_err(ifp, 4443 "mlx5_alloc_transport_domain failed, %d\n", err); 4444 goto err_dealloc_pd; 4445 } 4446 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr); 4447 if (err) { 4448 mlx5_en_err(ifp, "mlx5e_create_mkey failed, %d\n", err); 4449 goto err_dealloc_transport_domain; 4450 } 4451 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr); 4452 4453 /* check if we should generate a random MAC address */ 4454 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 && 4455 is_zero_ether_addr(dev_addr)) { 4456 random_ether_addr(dev_addr); 4457 mlx5_en_err(ifp, "Assigned random MAC address\n"); 4458 } 4459 4460 err = mlx5e_rl_init(priv); 4461 if (err) { 4462 mlx5_en_err(ifp, "mlx5e_rl_init failed, %d\n", err); 4463 goto err_create_mkey; 4464 } 4465 4466 err = mlx5e_tls_init(priv); 4467 if (err) { 4468 if_printf(ifp, "%s: mlx5e_tls_init failed\n", __func__); 4469 goto err_rl_init; 4470 } 4471 4472 /* set default MTU */ 4473 mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu); 4474 4475 /* Set default media status */ 4476 priv->media_status_last = IFM_AVALID; 4477 priv->media_active_last = IFM_ETHER | IFM_AUTO | IFM_FDX; 4478 4479 /* setup default pauseframes configuration */ 4480 mlx5e_setup_pauseframes(priv); 4481 4482 /* Setup supported medias */ 4483 //TODO: If we failed to query ptys is it ok to proceed?? 4484 if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) { 4485 ext = MLX5_CAP_PCAM_FEATURE(mdev, 4486 ptys_extended_ethernet); 4487 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 4488 eth_proto_capability); 4489 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type)) 4490 connector_type = MLX5_GET(ptys_reg, out, 4491 connector_type); 4492 } else { 4493 eth_proto_cap = 0; 4494 mlx5_en_err(ifp, "Query port media capability failed, %d\n", err); 4495 } 4496 4497 ifmedia_init(&priv->media, IFM_IMASK, 4498 mlx5e_media_change, mlx5e_media_status); 4499 4500 speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER : MLX5E_LINK_SPEEDS_NUMBER; 4501 for (i = 0; i != speeds_num; i++) { 4502 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) { 4503 media_entry = ext ? mlx5e_ext_mode_table[i][j] : 4504 mlx5e_mode_table[i][j]; 4505 if (media_entry.baudrate == 0) 4506 continue; 4507 if (MLX5E_PROT_MASK(i) & eth_proto_cap) 4508 mlx5e_ifm_add(priv, media_entry.subtype); 4509 } 4510 } 4511 4512 mlx5e_ifm_add(priv, IFM_AUTO); 4513 4514 /* Set autoselect by default */ 4515 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX | 4516 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE); 4517 4518 DEBUGNET_SET(ifp, mlx5_en); 4519 4520 ether_ifattach(ifp, dev_addr); 4521 4522 /* Register for VLAN events */ 4523 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config, 4524 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST); 4525 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig, 4526 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST); 4527 4528 /* Link is down by default */ 4529 if_link_state_change(ifp, LINK_STATE_DOWN); 4530 4531 mlx5e_enable_async_events(priv); 4532 4533 mlx5e_add_hw_stats(priv); 4534 4535 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4536 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM, 4537 priv->stats.vport.arg); 4538 4539 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4540 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM, 4541 priv->stats.pport.arg); 4542 4543 mlx5e_create_ethtool(priv); 4544 4545 mtx_lock(&priv->async_events_mtx); 4546 mlx5e_update_stats(priv); 4547 mtx_unlock(&priv->async_events_mtx); 4548 4549 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4550 OID_AUTO, "rx_clbr_done", CTLFLAG_RD, 4551 &priv->clbr_done, 0, 4552 "RX timestamps calibration state"); 4553 callout_init(&priv->tstmp_clbr, CALLOUT_DIRECT); 4554 mlx5e_reset_calibration_callout(priv); 4555 4556 pa.pa_version = PFIL_VERSION; 4557 pa.pa_flags = PFIL_IN; 4558 pa.pa_type = PFIL_TYPE_ETHERNET; 4559 pa.pa_headname = ifp->if_xname; 4560 priv->pfil = pfil_head_register(&pa); 4561 4562 return (priv); 4563 4564 err_rl_init: 4565 mlx5e_rl_cleanup(priv); 4566 4567 err_create_mkey: 4568 mlx5_core_destroy_mkey(priv->mdev, &priv->mr); 4569 4570 err_dealloc_transport_domain: 4571 mlx5_dealloc_transport_domain(mdev, priv->tdn); 4572 4573 err_dealloc_pd: 4574 mlx5_core_dealloc_pd(mdev, priv->pdn); 4575 4576 err_unmap_free_uar: 4577 mlx5_unmap_free_uar(mdev, &priv->cq_uar); 4578 4579 err_free_wq: 4580 flush_workqueue(priv->wq); 4581 4582 err_free_sysctl: 4583 sysctl_ctx_free(&priv->sysctl_ctx); 4584 if (priv->sysctl_debug) 4585 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx); 4586 mlx5e_priv_static_destroy(priv, mdev->priv.eq_table.num_comp_vectors); 4587 if_free(ifp); 4588 4589 err_free_priv: 4590 free(priv, M_MLX5EN); 4591 return (NULL); 4592 } 4593 4594 static void 4595 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv) 4596 { 4597 struct mlx5e_priv *priv = vpriv; 4598 struct ifnet *ifp = priv->ifp; 4599 4600 /* don't allow more IOCTLs */ 4601 priv->gone = 1; 4602 4603 /* XXX wait a bit to allow IOCTL handlers to complete */ 4604 pause("W", hz); 4605 4606 #ifdef RATELIMIT 4607 /* 4608 * The kernel can have reference(s) via the m_snd_tag's into 4609 * the ratelimit channels, and these must go away before 4610 * detaching: 4611 */ 4612 while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) { 4613 mlx5_en_err(priv->ifp, 4614 "Waiting for all ratelimit connections to terminate\n"); 4615 pause("W", hz); 4616 } 4617 #endif 4618 /* wait for all unlimited send tags to complete */ 4619 mlx5e_priv_wait_for_completion(priv, mdev->priv.eq_table.num_comp_vectors); 4620 4621 /* stop watchdog timer */ 4622 callout_drain(&priv->watchdog); 4623 4624 callout_drain(&priv->tstmp_clbr); 4625 4626 if (priv->vlan_attach != NULL) 4627 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach); 4628 if (priv->vlan_detach != NULL) 4629 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach); 4630 4631 /* make sure device gets closed */ 4632 PRIV_LOCK(priv); 4633 mlx5e_close_locked(ifp); 4634 PRIV_UNLOCK(priv); 4635 4636 /* deregister pfil */ 4637 if (priv->pfil != NULL) { 4638 pfil_head_unregister(priv->pfil); 4639 priv->pfil = NULL; 4640 } 4641 4642 /* unregister device */ 4643 ifmedia_removeall(&priv->media); 4644 ether_ifdetach(ifp); 4645 4646 mlx5e_tls_cleanup(priv); 4647 mlx5e_rl_cleanup(priv); 4648 4649 /* destroy all remaining sysctl nodes */ 4650 sysctl_ctx_free(&priv->stats.vport.ctx); 4651 sysctl_ctx_free(&priv->stats.pport.ctx); 4652 if (priv->sysctl_debug) 4653 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx); 4654 sysctl_ctx_free(&priv->sysctl_ctx); 4655 4656 mlx5_core_destroy_mkey(priv->mdev, &priv->mr); 4657 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn); 4658 mlx5_core_dealloc_pd(priv->mdev, priv->pdn); 4659 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar); 4660 mlx5e_disable_async_events(priv); 4661 flush_workqueue(priv->wq); 4662 mlx5e_priv_static_destroy(priv, mdev->priv.eq_table.num_comp_vectors); 4663 if_free(ifp); 4664 free(priv, M_MLX5EN); 4665 } 4666 4667 #ifdef DEBUGNET 4668 static void 4669 mlx5_en_debugnet_init(struct ifnet *dev, int *nrxr, int *ncl, int *clsize) 4670 { 4671 struct mlx5e_priv *priv = if_getsoftc(dev); 4672 4673 PRIV_LOCK(priv); 4674 *nrxr = priv->params.num_channels; 4675 *ncl = DEBUGNET_MAX_IN_FLIGHT; 4676 *clsize = MLX5E_MAX_RX_BYTES; 4677 PRIV_UNLOCK(priv); 4678 } 4679 4680 static void 4681 mlx5_en_debugnet_event(struct ifnet *dev, enum debugnet_ev event) 4682 { 4683 } 4684 4685 static int 4686 mlx5_en_debugnet_transmit(struct ifnet *dev, struct mbuf *m) 4687 { 4688 struct mlx5e_priv *priv = if_getsoftc(dev); 4689 struct mlx5e_sq *sq; 4690 int err; 4691 4692 if ((if_getdrvflags(dev) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4693 IFF_DRV_RUNNING || (priv->media_status_last & IFM_ACTIVE) == 0) 4694 return (ENOENT); 4695 4696 sq = &priv->channel[0].sq[0]; 4697 4698 if (sq->running == 0) { 4699 m_freem(m); 4700 return (ENOENT); 4701 } 4702 4703 if (mlx5e_sq_xmit(sq, &m) != 0) { 4704 m_freem(m); 4705 err = ENOBUFS; 4706 } else { 4707 err = 0; 4708 } 4709 4710 if (likely(sq->doorbell.d64 != 0)) { 4711 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0); 4712 sq->doorbell.d64 = 0; 4713 } 4714 return (err); 4715 } 4716 4717 static int 4718 mlx5_en_debugnet_poll(struct ifnet *dev, int count) 4719 { 4720 struct mlx5e_priv *priv = if_getsoftc(dev); 4721 4722 if ((if_getdrvflags(dev) & IFF_DRV_RUNNING) == 0 || 4723 (priv->media_status_last & IFM_ACTIVE) == 0) 4724 return (ENOENT); 4725 4726 mlx5_poll_interrupts(priv->mdev); 4727 4728 return (0); 4729 } 4730 #endif /* DEBUGNET */ 4731 4732 static void * 4733 mlx5e_get_ifp(void *vpriv) 4734 { 4735 struct mlx5e_priv *priv = vpriv; 4736 4737 return (priv->ifp); 4738 } 4739 4740 static struct mlx5_interface mlx5e_interface = { 4741 .add = mlx5e_create_ifp, 4742 .remove = mlx5e_destroy_ifp, 4743 .event = mlx5e_async_event, 4744 .protocol = MLX5_INTERFACE_PROTOCOL_ETH, 4745 .get_dev = mlx5e_get_ifp, 4746 }; 4747 4748 void 4749 mlx5e_init(void) 4750 { 4751 mlx5_register_interface(&mlx5e_interface); 4752 } 4753 4754 void 4755 mlx5e_cleanup(void) 4756 { 4757 mlx5_unregister_interface(&mlx5e_interface); 4758 } 4759 4760 static void 4761 mlx5e_show_version(void __unused *arg) 4762 { 4763 4764 printf("%s", mlx5e_version); 4765 } 4766 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL); 4767 4768 module_init_order(mlx5e_init, SI_ORDER_SIXTH); 4769 module_exit_order(mlx5e_cleanup, SI_ORDER_SIXTH); 4770 4771 #if (__FreeBSD_version >= 1100000) 4772 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1); 4773 #endif 4774 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1); 4775 MODULE_VERSION(mlx5en, 1); 4776