1 /*- 2 * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include "opt_kern_tls.h" 29 30 #include "en.h" 31 32 #include <sys/eventhandler.h> 33 #include <sys/sockio.h> 34 #include <machine/atomic.h> 35 36 #ifndef ETH_DRIVER_VERSION 37 #define ETH_DRIVER_VERSION "3.5.2" 38 #endif 39 #define DRIVER_RELDATE "September 2019" 40 41 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver " 42 ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n"; 43 44 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs); 45 46 struct mlx5e_channel_param { 47 struct mlx5e_rq_param rq; 48 struct mlx5e_sq_param sq; 49 struct mlx5e_cq_param rx_cq; 50 struct mlx5e_cq_param tx_cq; 51 }; 52 53 struct media { 54 u32 subtype; 55 u64 baudrate; 56 }; 57 58 static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = { 59 60 [MLX5E_1000BASE_CX_SGMII][MLX5E_SGMII] = { 61 .subtype = IFM_1000_CX_SGMII, 62 .baudrate = IF_Mbps(1000ULL), 63 }, 64 [MLX5E_1000BASE_KX][MLX5E_KX] = { 65 .subtype = IFM_1000_KX, 66 .baudrate = IF_Mbps(1000ULL), 67 }, 68 [MLX5E_10GBASE_CX4][MLX5E_CX4] = { 69 .subtype = IFM_10G_CX4, 70 .baudrate = IF_Gbps(10ULL), 71 }, 72 [MLX5E_10GBASE_KX4][MLX5E_KX4] = { 73 .subtype = IFM_10G_KX4, 74 .baudrate = IF_Gbps(10ULL), 75 }, 76 [MLX5E_10GBASE_KR][MLX5E_KR] = { 77 .subtype = IFM_10G_KR, 78 .baudrate = IF_Gbps(10ULL), 79 }, 80 [MLX5E_20GBASE_KR2][MLX5E_KR2] = { 81 .subtype = IFM_20G_KR2, 82 .baudrate = IF_Gbps(20ULL), 83 }, 84 [MLX5E_40GBASE_CR4][MLX5E_CR4] = { 85 .subtype = IFM_40G_CR4, 86 .baudrate = IF_Gbps(40ULL), 87 }, 88 [MLX5E_40GBASE_KR4][MLX5E_KR4] = { 89 .subtype = IFM_40G_KR4, 90 .baudrate = IF_Gbps(40ULL), 91 }, 92 [MLX5E_56GBASE_R4][MLX5E_R] = { 93 .subtype = IFM_56G_R4, 94 .baudrate = IF_Gbps(56ULL), 95 }, 96 [MLX5E_10GBASE_CR][MLX5E_CR1] = { 97 .subtype = IFM_10G_CR1, 98 .baudrate = IF_Gbps(10ULL), 99 }, 100 [MLX5E_10GBASE_SR][MLX5E_SR] = { 101 .subtype = IFM_10G_SR, 102 .baudrate = IF_Gbps(10ULL), 103 }, 104 [MLX5E_10GBASE_ER_LR][MLX5E_ER] = { 105 .subtype = IFM_10G_ER, 106 .baudrate = IF_Gbps(10ULL), 107 }, 108 [MLX5E_10GBASE_ER_LR][MLX5E_LR] = { 109 .subtype = IFM_10G_LR, 110 .baudrate = IF_Gbps(10ULL), 111 }, 112 [MLX5E_40GBASE_SR4][MLX5E_SR4] = { 113 .subtype = IFM_40G_SR4, 114 .baudrate = IF_Gbps(40ULL), 115 }, 116 [MLX5E_40GBASE_LR4_ER4][MLX5E_LR4] = { 117 .subtype = IFM_40G_LR4, 118 .baudrate = IF_Gbps(40ULL), 119 }, 120 [MLX5E_40GBASE_LR4_ER4][MLX5E_ER4] = { 121 .subtype = IFM_40G_ER4, 122 .baudrate = IF_Gbps(40ULL), 123 }, 124 [MLX5E_100GBASE_CR4][MLX5E_CR4] = { 125 .subtype = IFM_100G_CR4, 126 .baudrate = IF_Gbps(100ULL), 127 }, 128 [MLX5E_100GBASE_SR4][MLX5E_SR4] = { 129 .subtype = IFM_100G_SR4, 130 .baudrate = IF_Gbps(100ULL), 131 }, 132 [MLX5E_100GBASE_KR4][MLX5E_KR4] = { 133 .subtype = IFM_100G_KR4, 134 .baudrate = IF_Gbps(100ULL), 135 }, 136 [MLX5E_100GBASE_LR4][MLX5E_LR4] = { 137 .subtype = IFM_100G_LR4, 138 .baudrate = IF_Gbps(100ULL), 139 }, 140 [MLX5E_100BASE_TX][MLX5E_TX] = { 141 .subtype = IFM_100_TX, 142 .baudrate = IF_Mbps(100ULL), 143 }, 144 [MLX5E_1000BASE_T][MLX5E_T] = { 145 .subtype = IFM_1000_T, 146 .baudrate = IF_Mbps(1000ULL), 147 }, 148 [MLX5E_10GBASE_T][MLX5E_T] = { 149 .subtype = IFM_10G_T, 150 .baudrate = IF_Gbps(10ULL), 151 }, 152 [MLX5E_25GBASE_CR][MLX5E_CR] = { 153 .subtype = IFM_25G_CR, 154 .baudrate = IF_Gbps(25ULL), 155 }, 156 [MLX5E_25GBASE_KR][MLX5E_KR] = { 157 .subtype = IFM_25G_KR, 158 .baudrate = IF_Gbps(25ULL), 159 }, 160 [MLX5E_25GBASE_SR][MLX5E_SR] = { 161 .subtype = IFM_25G_SR, 162 .baudrate = IF_Gbps(25ULL), 163 }, 164 [MLX5E_50GBASE_CR2][MLX5E_CR2] = { 165 .subtype = IFM_50G_CR2, 166 .baudrate = IF_Gbps(50ULL), 167 }, 168 [MLX5E_50GBASE_KR2][MLX5E_KR2] = { 169 .subtype = IFM_50G_KR2, 170 .baudrate = IF_Gbps(50ULL), 171 }, 172 }; 173 174 static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = { 175 [MLX5E_SGMII_100M][MLX5E_SGMII] = { 176 .subtype = IFM_100_SGMII, 177 .baudrate = IF_Mbps(100), 178 }, 179 [MLX5E_1000BASE_X_SGMII][MLX5E_KX] = { 180 .subtype = IFM_1000_KX, 181 .baudrate = IF_Mbps(1000), 182 }, 183 [MLX5E_1000BASE_X_SGMII][MLX5E_CX_SGMII] = { 184 .subtype = IFM_1000_CX_SGMII, 185 .baudrate = IF_Mbps(1000), 186 }, 187 [MLX5E_1000BASE_X_SGMII][MLX5E_CX] = { 188 .subtype = IFM_1000_CX, 189 .baudrate = IF_Mbps(1000), 190 }, 191 [MLX5E_1000BASE_X_SGMII][MLX5E_LX] = { 192 .subtype = IFM_1000_LX, 193 .baudrate = IF_Mbps(1000), 194 }, 195 [MLX5E_1000BASE_X_SGMII][MLX5E_SX] = { 196 .subtype = IFM_1000_SX, 197 .baudrate = IF_Mbps(1000), 198 }, 199 [MLX5E_1000BASE_X_SGMII][MLX5E_T] = { 200 .subtype = IFM_1000_T, 201 .baudrate = IF_Mbps(1000), 202 }, 203 [MLX5E_5GBASE_R][MLX5E_T] = { 204 .subtype = IFM_5000_T, 205 .baudrate = IF_Mbps(5000), 206 }, 207 [MLX5E_5GBASE_R][MLX5E_KR] = { 208 .subtype = IFM_5000_KR, 209 .baudrate = IF_Mbps(5000), 210 }, 211 [MLX5E_5GBASE_R][MLX5E_KR1] = { 212 .subtype = IFM_5000_KR1, 213 .baudrate = IF_Mbps(5000), 214 }, 215 [MLX5E_5GBASE_R][MLX5E_KR_S] = { 216 .subtype = IFM_5000_KR_S, 217 .baudrate = IF_Mbps(5000), 218 }, 219 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_ER] = { 220 .subtype = IFM_10G_ER, 221 .baudrate = IF_Gbps(10ULL), 222 }, 223 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_KR] = { 224 .subtype = IFM_10G_KR, 225 .baudrate = IF_Gbps(10ULL), 226 }, 227 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_LR] = { 228 .subtype = IFM_10G_LR, 229 .baudrate = IF_Gbps(10ULL), 230 }, 231 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_SR] = { 232 .subtype = IFM_10G_SR, 233 .baudrate = IF_Gbps(10ULL), 234 }, 235 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_T] = { 236 .subtype = IFM_10G_T, 237 .baudrate = IF_Gbps(10ULL), 238 }, 239 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_AOC] = { 240 .subtype = IFM_10G_AOC, 241 .baudrate = IF_Gbps(10ULL), 242 }, 243 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CR1] = { 244 .subtype = IFM_10G_CR1, 245 .baudrate = IF_Gbps(10ULL), 246 }, 247 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CR4] = { 248 .subtype = IFM_40G_CR4, 249 .baudrate = IF_Gbps(40ULL), 250 }, 251 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_KR4] = { 252 .subtype = IFM_40G_KR4, 253 .baudrate = IF_Gbps(40ULL), 254 }, 255 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_LR4] = { 256 .subtype = IFM_40G_LR4, 257 .baudrate = IF_Gbps(40ULL), 258 }, 259 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_SR4] = { 260 .subtype = IFM_40G_SR4, 261 .baudrate = IF_Gbps(40ULL), 262 }, 263 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_ER4] = { 264 .subtype = IFM_40G_ER4, 265 .baudrate = IF_Gbps(40ULL), 266 }, 267 268 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR] = { 269 .subtype = IFM_25G_CR, 270 .baudrate = IF_Gbps(25ULL), 271 }, 272 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR] = { 273 .subtype = IFM_25G_KR, 274 .baudrate = IF_Gbps(25ULL), 275 }, 276 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_SR] = { 277 .subtype = IFM_25G_SR, 278 .baudrate = IF_Gbps(25ULL), 279 }, 280 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_ACC] = { 281 .subtype = IFM_25G_ACC, 282 .baudrate = IF_Gbps(25ULL), 283 }, 284 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_AOC] = { 285 .subtype = IFM_25G_AOC, 286 .baudrate = IF_Gbps(25ULL), 287 }, 288 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR1] = { 289 .subtype = IFM_25G_CR1, 290 .baudrate = IF_Gbps(25ULL), 291 }, 292 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR_S] = { 293 .subtype = IFM_25G_CR_S, 294 .baudrate = IF_Gbps(25ULL), 295 }, 296 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR1] = { 297 .subtype = IFM_5000_KR1, 298 .baudrate = IF_Gbps(25ULL), 299 }, 300 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR_S] = { 301 .subtype = IFM_25G_KR_S, 302 .baudrate = IF_Gbps(25ULL), 303 }, 304 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_LR] = { 305 .subtype = IFM_25G_LR, 306 .baudrate = IF_Gbps(25ULL), 307 }, 308 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_T] = { 309 .subtype = IFM_25G_T, 310 .baudrate = IF_Gbps(25ULL), 311 }, 312 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CR2] = { 313 .subtype = IFM_50G_CR2, 314 .baudrate = IF_Gbps(50ULL), 315 }, 316 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_KR2] = { 317 .subtype = IFM_50G_KR2, 318 .baudrate = IF_Gbps(50ULL), 319 }, 320 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_SR2] = { 321 .subtype = IFM_50G_SR2, 322 .baudrate = IF_Gbps(50ULL), 323 }, 324 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_LR2] = { 325 .subtype = IFM_50G_LR2, 326 .baudrate = IF_Gbps(50ULL), 327 }, 328 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_LR] = { 329 .subtype = IFM_50G_LR, 330 .baudrate = IF_Gbps(50ULL), 331 }, 332 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_SR] = { 333 .subtype = IFM_50G_SR, 334 .baudrate = IF_Gbps(50ULL), 335 }, 336 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CP] = { 337 .subtype = IFM_50G_CP, 338 .baudrate = IF_Gbps(50ULL), 339 }, 340 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_FR] = { 341 .subtype = IFM_50G_FR, 342 .baudrate = IF_Gbps(50ULL), 343 }, 344 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_KR_PAM4] = { 345 .subtype = IFM_50G_KR_PAM4, 346 .baudrate = IF_Gbps(50ULL), 347 }, 348 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CR4] = { 349 .subtype = IFM_100G_CR4, 350 .baudrate = IF_Gbps(100ULL), 351 }, 352 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_KR4] = { 353 .subtype = IFM_100G_KR4, 354 .baudrate = IF_Gbps(100ULL), 355 }, 356 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_LR4] = { 357 .subtype = IFM_100G_LR4, 358 .baudrate = IF_Gbps(100ULL), 359 }, 360 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_SR4] = { 361 .subtype = IFM_100G_SR4, 362 .baudrate = IF_Gbps(100ULL), 363 }, 364 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_SR2] = { 365 .subtype = IFM_100G_SR2, 366 .baudrate = IF_Gbps(100ULL), 367 }, 368 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CP2] = { 369 .subtype = IFM_100G_CP2, 370 .baudrate = IF_Gbps(100ULL), 371 }, 372 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_KR2_PAM4] = { 373 .subtype = IFM_100G_KR2_PAM4, 374 .baudrate = IF_Gbps(100ULL), 375 }, 376 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_DR4] = { 377 .subtype = IFM_200G_DR4, 378 .baudrate = IF_Gbps(200ULL), 379 }, 380 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_LR4] = { 381 .subtype = IFM_200G_LR4, 382 .baudrate = IF_Gbps(200ULL), 383 }, 384 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_SR4] = { 385 .subtype = IFM_200G_SR4, 386 .baudrate = IF_Gbps(200ULL), 387 }, 388 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_FR4] = { 389 .subtype = IFM_200G_FR4, 390 .baudrate = IF_Gbps(200ULL), 391 }, 392 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CR4_PAM4] = { 393 .subtype = IFM_200G_CR4_PAM4, 394 .baudrate = IF_Gbps(200ULL), 395 }, 396 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_KR4_PAM4] = { 397 .subtype = IFM_200G_KR4_PAM4, 398 .baudrate = IF_Gbps(200ULL), 399 }, 400 }; 401 402 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet"); 403 404 static void 405 mlx5e_update_carrier(struct mlx5e_priv *priv) 406 { 407 struct mlx5_core_dev *mdev = priv->mdev; 408 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 409 u32 eth_proto_oper; 410 int error; 411 u8 port_state; 412 u8 is_er_type; 413 u8 i, j; 414 bool ext; 415 struct media media_entry = {}; 416 417 port_state = mlx5_query_vport_state(mdev, 418 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0); 419 420 if (port_state == VPORT_STATE_UP) { 421 priv->media_status_last |= IFM_ACTIVE; 422 } else { 423 priv->media_status_last &= ~IFM_ACTIVE; 424 priv->media_active_last = IFM_ETHER; 425 if_link_state_change(priv->ifp, LINK_STATE_DOWN); 426 return; 427 } 428 429 error = mlx5_query_port_ptys(mdev, out, sizeof(out), 430 MLX5_PTYS_EN, 1); 431 if (error) { 432 priv->media_active_last = IFM_ETHER; 433 priv->ifp->if_baudrate = 1; 434 mlx5_en_err(priv->ifp, "query port ptys failed: 0x%x\n", 435 error); 436 return; 437 } 438 439 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet); 440 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 441 eth_proto_oper); 442 443 i = ilog2(eth_proto_oper); 444 445 for (j = 0; j != MLX5E_LINK_MODES_NUMBER; j++) { 446 media_entry = ext ? mlx5e_ext_mode_table[i][j] : 447 mlx5e_mode_table[i][j]; 448 if (media_entry.baudrate != 0) 449 break; 450 } 451 452 if (media_entry.subtype == 0) { 453 mlx5_en_err(priv->ifp, 454 "Could not find operational media subtype\n"); 455 return; 456 } 457 458 switch (media_entry.subtype) { 459 case IFM_10G_ER: 460 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type); 461 if (error != 0) { 462 mlx5_en_err(priv->ifp, 463 "query port pddr failed: %d\n", error); 464 } 465 if (error != 0 || is_er_type == 0) 466 media_entry.subtype = IFM_10G_LR; 467 break; 468 case IFM_40G_LR4: 469 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type); 470 if (error != 0) { 471 mlx5_en_err(priv->ifp, 472 "query port pddr failed: %d\n", error); 473 } 474 if (error == 0 && is_er_type != 0) 475 media_entry.subtype = IFM_40G_ER4; 476 break; 477 } 478 priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX; 479 priv->ifp->if_baudrate = media_entry.baudrate; 480 481 if_link_state_change(priv->ifp, LINK_STATE_UP); 482 } 483 484 static void 485 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr) 486 { 487 struct mlx5e_priv *priv = dev->if_softc; 488 489 ifmr->ifm_status = priv->media_status_last; 490 ifmr->ifm_active = priv->media_active_last | 491 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) | 492 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0); 493 494 } 495 496 static u32 497 mlx5e_find_link_mode(u32 subtype, bool ext) 498 { 499 u32 i; 500 u32 j; 501 u32 link_mode = 0; 502 u32 speeds_num = 0; 503 struct media media_entry = {}; 504 505 switch (subtype) { 506 case IFM_10G_LR: 507 subtype = IFM_10G_ER; 508 break; 509 case IFM_40G_ER4: 510 subtype = IFM_40G_LR4; 511 break; 512 } 513 514 speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER : 515 MLX5E_LINK_SPEEDS_NUMBER; 516 517 for (i = 0; i != speeds_num; i++) { 518 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) { 519 media_entry = ext ? mlx5e_ext_mode_table[i][j] : 520 mlx5e_mode_table[i][j]; 521 if (media_entry.baudrate == 0) 522 continue; 523 if (media_entry.subtype == subtype) { 524 link_mode |= MLX5E_PROT_MASK(i); 525 } 526 } 527 } 528 529 return (link_mode); 530 } 531 532 static int 533 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv) 534 { 535 return (mlx5_set_port_pause_and_pfc(priv->mdev, 1, 536 priv->params.rx_pauseframe_control, 537 priv->params.tx_pauseframe_control, 538 priv->params.rx_priority_flow_control, 539 priv->params.tx_priority_flow_control)); 540 } 541 542 static int 543 mlx5e_set_port_pfc(struct mlx5e_priv *priv) 544 { 545 int error; 546 547 if (priv->gone != 0) { 548 error = -ENXIO; 549 } else if (priv->params.rx_pauseframe_control || 550 priv->params.tx_pauseframe_control) { 551 mlx5_en_err(priv->ifp, 552 "Global pauseframes must be disabled before enabling PFC.\n"); 553 error = -EINVAL; 554 } else { 555 error = mlx5e_set_port_pause_and_pfc(priv); 556 } 557 return (error); 558 } 559 560 static int 561 mlx5e_media_change(struct ifnet *dev) 562 { 563 struct mlx5e_priv *priv = dev->if_softc; 564 struct mlx5_core_dev *mdev = priv->mdev; 565 u32 eth_proto_cap; 566 u32 link_mode; 567 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 568 int was_opened; 569 int locked; 570 int error; 571 bool ext; 572 573 locked = PRIV_LOCKED(priv); 574 if (!locked) 575 PRIV_LOCK(priv); 576 577 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) { 578 error = EINVAL; 579 goto done; 580 } 581 582 error = mlx5_query_port_ptys(mdev, out, sizeof(out), 583 MLX5_PTYS_EN, 1); 584 if (error != 0) { 585 mlx5_en_err(dev, "Query port media capability failed\n"); 586 goto done; 587 } 588 589 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet); 590 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext); 591 592 /* query supported capabilities */ 593 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 594 eth_proto_capability); 595 596 /* check for autoselect */ 597 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) { 598 link_mode = eth_proto_cap; 599 if (link_mode == 0) { 600 mlx5_en_err(dev, "Port media capability is zero\n"); 601 error = EINVAL; 602 goto done; 603 } 604 } else { 605 link_mode = link_mode & eth_proto_cap; 606 if (link_mode == 0) { 607 mlx5_en_err(dev, "Not supported link mode requested\n"); 608 error = EINVAL; 609 goto done; 610 } 611 } 612 if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) { 613 /* check if PFC is enabled */ 614 if (priv->params.rx_priority_flow_control || 615 priv->params.tx_priority_flow_control) { 616 mlx5_en_err(dev, "PFC must be disabled before enabling global pauseframes.\n"); 617 error = EINVAL; 618 goto done; 619 } 620 } 621 /* update pauseframe control bits */ 622 priv->params.rx_pauseframe_control = 623 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0; 624 priv->params.tx_pauseframe_control = 625 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0; 626 627 /* check if device is opened */ 628 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 629 630 /* reconfigure the hardware */ 631 mlx5_set_port_status(mdev, MLX5_PORT_DOWN); 632 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext); 633 error = -mlx5e_set_port_pause_and_pfc(priv); 634 if (was_opened) 635 mlx5_set_port_status(mdev, MLX5_PORT_UP); 636 637 done: 638 if (!locked) 639 PRIV_UNLOCK(priv); 640 return (error); 641 } 642 643 static void 644 mlx5e_update_carrier_work(struct work_struct *work) 645 { 646 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 647 update_carrier_work); 648 649 PRIV_LOCK(priv); 650 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) 651 mlx5e_update_carrier(priv); 652 PRIV_UNLOCK(priv); 653 } 654 655 #define MLX5E_PCIE_PERF_GET_64(a,b,c,d,e,f) \ 656 s_debug->c = MLX5_GET64(mpcnt_reg, out, counter_set.f.c); 657 658 #define MLX5E_PCIE_PERF_GET_32(a,b,c,d,e,f) \ 659 s_debug->c = MLX5_GET(mpcnt_reg, out, counter_set.f.c); 660 661 static void 662 mlx5e_update_pcie_counters(struct mlx5e_priv *priv) 663 { 664 struct mlx5_core_dev *mdev = priv->mdev; 665 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug; 666 const unsigned sz = MLX5_ST_SZ_BYTES(mpcnt_reg); 667 void *out; 668 void *in; 669 int err; 670 671 /* allocate firmware request structures */ 672 in = mlx5_vzalloc(sz); 673 out = mlx5_vzalloc(sz); 674 if (in == NULL || out == NULL) 675 goto free_out; 676 677 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP); 678 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 679 if (err != 0) 680 goto free_out; 681 682 MLX5E_PCIE_PERFORMANCE_COUNTERS_64(MLX5E_PCIE_PERF_GET_64) 683 MLX5E_PCIE_PERFORMANCE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 684 685 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP); 686 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 687 if (err != 0) 688 goto free_out; 689 690 MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 691 692 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_LANE_COUNTERS_GROUP); 693 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 694 if (err != 0) 695 goto free_out; 696 697 MLX5E_PCIE_LANE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 698 699 free_out: 700 /* free firmware request structures */ 701 kvfree(in); 702 kvfree(out); 703 } 704 705 /* 706 * This function reads the physical port counters from the firmware 707 * using a pre-defined layout defined by various MLX5E_PPORT_XXX() 708 * macros. The output is converted from big-endian 64-bit values into 709 * host endian ones and stored in the "priv->stats.pport" structure. 710 */ 711 static void 712 mlx5e_update_pport_counters(struct mlx5e_priv *priv) 713 { 714 struct mlx5_core_dev *mdev = priv->mdev; 715 struct mlx5e_pport_stats *s = &priv->stats.pport; 716 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug; 717 u32 *in; 718 u32 *out; 719 const u64 *ptr; 720 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 721 unsigned x; 722 unsigned y; 723 unsigned z; 724 725 /* allocate firmware request structures */ 726 in = mlx5_vzalloc(sz); 727 out = mlx5_vzalloc(sz); 728 if (in == NULL || out == NULL) 729 goto free_out; 730 731 /* 732 * Get pointer to the 64-bit counter set which is located at a 733 * fixed offset in the output firmware request structure: 734 */ 735 ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set); 736 737 MLX5_SET(ppcnt_reg, in, local_port, 1); 738 739 /* read IEEE802_3 counter group using predefined counter layout */ 740 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP); 741 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 742 for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM; 743 x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++) 744 s->arg[y] = be64toh(ptr[x]); 745 746 /* read RFC2819 counter group using predefined counter layout */ 747 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP); 748 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 749 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++) 750 s->arg[y] = be64toh(ptr[x]); 751 752 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM + 753 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++) 754 s_debug->arg[y] = be64toh(ptr[x]); 755 756 /* read RFC2863 counter group using predefined counter layout */ 757 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP); 758 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 759 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++) 760 s_debug->arg[y] = be64toh(ptr[x]); 761 762 /* read physical layer stats counter group using predefined counter layout */ 763 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP); 764 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 765 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++) 766 s_debug->arg[y] = be64toh(ptr[x]); 767 768 /* read Extended Ethernet counter group using predefined counter layout */ 769 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP); 770 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 771 for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++) 772 s_debug->arg[y] = be64toh(ptr[x]); 773 774 /* read Extended Statistical Group */ 775 if (MLX5_CAP_GEN(mdev, pcam_reg) && 776 MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) && 777 MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) { 778 /* read Extended Statistical counter group using predefined counter layout */ 779 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP); 780 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 781 782 for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++) 783 s_debug->arg[y] = be64toh(ptr[x]); 784 } 785 786 /* read PCIE counters */ 787 mlx5e_update_pcie_counters(priv); 788 789 /* read per-priority counters */ 790 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP); 791 792 /* iterate all the priorities */ 793 for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) { 794 MLX5_SET(ppcnt_reg, in, prio_tc, z); 795 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 796 797 /* read per priority stats counter group using predefined counter layout */ 798 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM / 799 MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++) 800 s->arg[y] = be64toh(ptr[x]); 801 } 802 803 free_out: 804 /* free firmware request structures */ 805 kvfree(in); 806 kvfree(out); 807 } 808 809 static void 810 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv) 811 { 812 u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {}; 813 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {}; 814 815 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard)) 816 return; 817 818 MLX5_SET(query_vnic_env_in, in, opcode, 819 MLX5_CMD_OP_QUERY_VNIC_ENV); 820 MLX5_SET(query_vnic_env_in, in, op_mod, 0); 821 MLX5_SET(query_vnic_env_in, in, other_vport, 0); 822 823 if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0) 824 return; 825 826 priv->stats.vport.rx_steer_missed_packets = 827 MLX5_GET64(query_vnic_env_out, out, 828 vport_env.nic_receive_steering_discard); 829 } 830 831 /* 832 * This function is called regularly to collect all statistics 833 * counters from the firmware. The values can be viewed through the 834 * sysctl interface. Execution is serialized using the priv's global 835 * configuration lock. 836 */ 837 static void 838 mlx5e_update_stats_locked(struct mlx5e_priv *priv) 839 { 840 struct mlx5_core_dev *mdev = priv->mdev; 841 struct mlx5e_vport_stats *s = &priv->stats.vport; 842 struct mlx5e_sq_stats *sq_stats; 843 struct buf_ring *sq_br; 844 #if (__FreeBSD_version < 1100000) 845 struct ifnet *ifp = priv->ifp; 846 #endif 847 848 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)]; 849 u32 *out; 850 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out); 851 u64 tso_packets = 0; 852 u64 tso_bytes = 0; 853 u64 tx_queue_dropped = 0; 854 u64 tx_defragged = 0; 855 u64 tx_offload_none = 0; 856 u64 lro_packets = 0; 857 u64 lro_bytes = 0; 858 u64 sw_lro_queued = 0; 859 u64 sw_lro_flushed = 0; 860 u64 rx_csum_none = 0; 861 u64 rx_wqe_err = 0; 862 u64 rx_packets = 0; 863 u64 rx_bytes = 0; 864 u32 rx_out_of_buffer = 0; 865 int error; 866 int i; 867 int j; 868 869 out = mlx5_vzalloc(outlen); 870 if (out == NULL) 871 goto free_out; 872 873 /* Collect firts the SW counters and then HW for consistency */ 874 for (i = 0; i < priv->params.num_channels; i++) { 875 struct mlx5e_channel *pch = priv->channel + i; 876 struct mlx5e_rq *rq = &pch->rq; 877 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats; 878 879 /* collect stats from LRO */ 880 rq_stats->sw_lro_queued = rq->lro.lro_queued; 881 rq_stats->sw_lro_flushed = rq->lro.lro_flushed; 882 sw_lro_queued += rq_stats->sw_lro_queued; 883 sw_lro_flushed += rq_stats->sw_lro_flushed; 884 lro_packets += rq_stats->lro_packets; 885 lro_bytes += rq_stats->lro_bytes; 886 rx_csum_none += rq_stats->csum_none; 887 rx_wqe_err += rq_stats->wqe_err; 888 rx_packets += rq_stats->packets; 889 rx_bytes += rq_stats->bytes; 890 891 for (j = 0; j < priv->num_tc; j++) { 892 sq_stats = &pch->sq[j].stats; 893 sq_br = pch->sq[j].br; 894 895 tso_packets += sq_stats->tso_packets; 896 tso_bytes += sq_stats->tso_bytes; 897 tx_queue_dropped += sq_stats->dropped; 898 if (sq_br != NULL) 899 tx_queue_dropped += sq_br->br_drops; 900 tx_defragged += sq_stats->defragged; 901 tx_offload_none += sq_stats->csum_offload_none; 902 } 903 } 904 905 /* update counters */ 906 s->tso_packets = tso_packets; 907 s->tso_bytes = tso_bytes; 908 s->tx_queue_dropped = tx_queue_dropped; 909 s->tx_defragged = tx_defragged; 910 s->lro_packets = lro_packets; 911 s->lro_bytes = lro_bytes; 912 s->sw_lro_queued = sw_lro_queued; 913 s->sw_lro_flushed = sw_lro_flushed; 914 s->rx_csum_none = rx_csum_none; 915 s->rx_wqe_err = rx_wqe_err; 916 s->rx_packets = rx_packets; 917 s->rx_bytes = rx_bytes; 918 919 mlx5e_grp_vnic_env_update_stats(priv); 920 921 /* HW counters */ 922 memset(in, 0, sizeof(in)); 923 924 MLX5_SET(query_vport_counter_in, in, opcode, 925 MLX5_CMD_OP_QUERY_VPORT_COUNTER); 926 MLX5_SET(query_vport_counter_in, in, op_mod, 0); 927 MLX5_SET(query_vport_counter_in, in, other_vport, 0); 928 929 memset(out, 0, outlen); 930 931 /* get number of out-of-buffer drops first */ 932 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 && 933 mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id, 934 &rx_out_of_buffer) == 0) { 935 s->rx_out_of_buffer = rx_out_of_buffer; 936 } 937 938 /* get port statistics */ 939 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) { 940 #define MLX5_GET_CTR(out, x) \ 941 MLX5_GET64(query_vport_counter_out, out, x) 942 943 s->rx_error_packets = 944 MLX5_GET_CTR(out, received_errors.packets); 945 s->rx_error_bytes = 946 MLX5_GET_CTR(out, received_errors.octets); 947 s->tx_error_packets = 948 MLX5_GET_CTR(out, transmit_errors.packets); 949 s->tx_error_bytes = 950 MLX5_GET_CTR(out, transmit_errors.octets); 951 952 s->rx_unicast_packets = 953 MLX5_GET_CTR(out, received_eth_unicast.packets); 954 s->rx_unicast_bytes = 955 MLX5_GET_CTR(out, received_eth_unicast.octets); 956 s->tx_unicast_packets = 957 MLX5_GET_CTR(out, transmitted_eth_unicast.packets); 958 s->tx_unicast_bytes = 959 MLX5_GET_CTR(out, transmitted_eth_unicast.octets); 960 961 s->rx_multicast_packets = 962 MLX5_GET_CTR(out, received_eth_multicast.packets); 963 s->rx_multicast_bytes = 964 MLX5_GET_CTR(out, received_eth_multicast.octets); 965 s->tx_multicast_packets = 966 MLX5_GET_CTR(out, transmitted_eth_multicast.packets); 967 s->tx_multicast_bytes = 968 MLX5_GET_CTR(out, transmitted_eth_multicast.octets); 969 970 s->rx_broadcast_packets = 971 MLX5_GET_CTR(out, received_eth_broadcast.packets); 972 s->rx_broadcast_bytes = 973 MLX5_GET_CTR(out, received_eth_broadcast.octets); 974 s->tx_broadcast_packets = 975 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets); 976 s->tx_broadcast_bytes = 977 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets); 978 979 s->tx_packets = s->tx_unicast_packets + 980 s->tx_multicast_packets + s->tx_broadcast_packets; 981 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes + 982 s->tx_broadcast_bytes; 983 984 /* Update calculated offload counters */ 985 s->tx_csum_offload = s->tx_packets - tx_offload_none; 986 s->rx_csum_good = s->rx_packets - s->rx_csum_none; 987 } 988 989 /* Get physical port counters */ 990 mlx5e_update_pport_counters(priv); 991 992 s->tx_jumbo_packets = 993 priv->stats.port_stats_debug.tx_stat_p1519to2047octets + 994 priv->stats.port_stats_debug.tx_stat_p2048to4095octets + 995 priv->stats.port_stats_debug.tx_stat_p4096to8191octets + 996 priv->stats.port_stats_debug.tx_stat_p8192to10239octets; 997 998 #if (__FreeBSD_version < 1100000) 999 /* no get_counters interface in fbsd 10 */ 1000 ifp->if_ipackets = s->rx_packets; 1001 ifp->if_ierrors = priv->stats.pport.in_range_len_errors + 1002 priv->stats.pport.out_of_range_len + 1003 priv->stats.pport.too_long_errors + 1004 priv->stats.pport.check_seq_err + 1005 priv->stats.pport.alignment_err; 1006 ifp->if_iqdrops = s->rx_out_of_buffer; 1007 ifp->if_opackets = s->tx_packets; 1008 ifp->if_oerrors = priv->stats.port_stats_debug.out_discards; 1009 ifp->if_snd.ifq_drops = s->tx_queue_dropped; 1010 ifp->if_ibytes = s->rx_bytes; 1011 ifp->if_obytes = s->tx_bytes; 1012 ifp->if_collisions = 1013 priv->stats.pport.collisions; 1014 #endif 1015 1016 free_out: 1017 kvfree(out); 1018 1019 /* Update diagnostics, if any */ 1020 if (priv->params_ethtool.diag_pci_enable || 1021 priv->params_ethtool.diag_general_enable) { 1022 error = mlx5_core_get_diagnostics_full(mdev, 1023 priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL, 1024 priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL); 1025 if (error != 0) 1026 mlx5_en_err(priv->ifp, 1027 "Failed reading diagnostics: %d\n", error); 1028 } 1029 1030 /* Update FEC, if any */ 1031 error = mlx5e_fec_update(priv); 1032 if (error != 0 && error != EOPNOTSUPP) { 1033 mlx5_en_err(priv->ifp, 1034 "Updating FEC failed: %d\n", error); 1035 } 1036 } 1037 1038 static void 1039 mlx5e_update_stats_work(struct work_struct *work) 1040 { 1041 struct mlx5e_priv *priv; 1042 1043 priv = container_of(work, struct mlx5e_priv, update_stats_work); 1044 PRIV_LOCK(priv); 1045 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 && 1046 !test_bit(MLX5_INTERFACE_STATE_TEARDOWN, &priv->mdev->intf_state)) 1047 mlx5e_update_stats_locked(priv); 1048 PRIV_UNLOCK(priv); 1049 } 1050 1051 static void 1052 mlx5e_update_stats(void *arg) 1053 { 1054 struct mlx5e_priv *priv = arg; 1055 1056 queue_work(priv->wq, &priv->update_stats_work); 1057 1058 callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv); 1059 } 1060 1061 static void 1062 mlx5e_async_event_sub(struct mlx5e_priv *priv, 1063 enum mlx5_dev_event event) 1064 { 1065 switch (event) { 1066 case MLX5_DEV_EVENT_PORT_UP: 1067 case MLX5_DEV_EVENT_PORT_DOWN: 1068 queue_work(priv->wq, &priv->update_carrier_work); 1069 break; 1070 1071 default: 1072 break; 1073 } 1074 } 1075 1076 static void 1077 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv, 1078 enum mlx5_dev_event event, unsigned long param) 1079 { 1080 struct mlx5e_priv *priv = vpriv; 1081 1082 mtx_lock(&priv->async_events_mtx); 1083 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state)) 1084 mlx5e_async_event_sub(priv, event); 1085 mtx_unlock(&priv->async_events_mtx); 1086 } 1087 1088 static void 1089 mlx5e_enable_async_events(struct mlx5e_priv *priv) 1090 { 1091 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 1092 } 1093 1094 static void 1095 mlx5e_disable_async_events(struct mlx5e_priv *priv) 1096 { 1097 mtx_lock(&priv->async_events_mtx); 1098 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 1099 mtx_unlock(&priv->async_events_mtx); 1100 } 1101 1102 static void mlx5e_calibration_callout(void *arg); 1103 static int mlx5e_calibration_duration = 20; 1104 static int mlx5e_fast_calibration = 1; 1105 static int mlx5e_normal_calibration = 30; 1106 1107 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW, 0, 1108 "MLX5 timestamp calibration parameteres"); 1109 1110 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN, 1111 &mlx5e_calibration_duration, 0, 1112 "Duration of initial calibration"); 1113 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN, 1114 &mlx5e_fast_calibration, 0, 1115 "Recalibration interval during initial calibration"); 1116 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN, 1117 &mlx5e_normal_calibration, 0, 1118 "Recalibration interval during normal operations"); 1119 1120 /* 1121 * Ignites the calibration process. 1122 */ 1123 static void 1124 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv) 1125 { 1126 1127 if (priv->clbr_done == 0) 1128 mlx5e_calibration_callout(priv); 1129 else 1130 callout_reset_curcpu(&priv->tstmp_clbr, (priv->clbr_done < 1131 mlx5e_calibration_duration ? mlx5e_fast_calibration : 1132 mlx5e_normal_calibration) * hz, mlx5e_calibration_callout, 1133 priv); 1134 } 1135 1136 static uint64_t 1137 mlx5e_timespec2usec(const struct timespec *ts) 1138 { 1139 1140 return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec); 1141 } 1142 1143 static uint64_t 1144 mlx5e_hw_clock(struct mlx5e_priv *priv) 1145 { 1146 struct mlx5_init_seg *iseg; 1147 uint32_t hw_h, hw_h1, hw_l; 1148 1149 iseg = priv->mdev->iseg; 1150 do { 1151 hw_h = ioread32be(&iseg->internal_timer_h); 1152 hw_l = ioread32be(&iseg->internal_timer_l); 1153 hw_h1 = ioread32be(&iseg->internal_timer_h); 1154 } while (hw_h1 != hw_h); 1155 return (((uint64_t)hw_h << 32) | hw_l); 1156 } 1157 1158 /* 1159 * The calibration callout, it runs either in the context of the 1160 * thread which enables calibration, or in callout. It takes the 1161 * snapshot of system and adapter clocks, then advances the pointers to 1162 * the calibration point to allow rx path to read the consistent data 1163 * lockless. 1164 */ 1165 static void 1166 mlx5e_calibration_callout(void *arg) 1167 { 1168 struct mlx5e_priv *priv; 1169 struct mlx5e_clbr_point *next, *curr; 1170 struct timespec ts; 1171 int clbr_curr_next; 1172 1173 priv = arg; 1174 curr = &priv->clbr_points[priv->clbr_curr]; 1175 clbr_curr_next = priv->clbr_curr + 1; 1176 if (clbr_curr_next >= nitems(priv->clbr_points)) 1177 clbr_curr_next = 0; 1178 next = &priv->clbr_points[clbr_curr_next]; 1179 1180 next->base_prev = curr->base_curr; 1181 next->clbr_hw_prev = curr->clbr_hw_curr; 1182 1183 next->clbr_hw_curr = mlx5e_hw_clock(priv); 1184 if (((next->clbr_hw_curr - curr->clbr_hw_curr) >> MLX5E_TSTMP_PREC) == 1185 0) { 1186 if (priv->clbr_done != 0) { 1187 mlx5_en_err(priv->ifp, 1188 "HW failed tstmp frozen %#jx %#jx, disabling\n", 1189 next->clbr_hw_curr, curr->clbr_hw_prev); 1190 priv->clbr_done = 0; 1191 } 1192 atomic_store_rel_int(&curr->clbr_gen, 0); 1193 return; 1194 } 1195 1196 nanouptime(&ts); 1197 next->base_curr = mlx5e_timespec2usec(&ts); 1198 1199 curr->clbr_gen = 0; 1200 atomic_thread_fence_rel(); 1201 priv->clbr_curr = clbr_curr_next; 1202 atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen)); 1203 1204 if (priv->clbr_done < mlx5e_calibration_duration) 1205 priv->clbr_done++; 1206 mlx5e_reset_calibration_callout(priv); 1207 } 1208 1209 static const char *mlx5e_rq_stats_desc[] = { 1210 MLX5E_RQ_STATS(MLX5E_STATS_DESC) 1211 }; 1212 1213 static int 1214 mlx5e_create_rq(struct mlx5e_channel *c, 1215 struct mlx5e_rq_param *param, 1216 struct mlx5e_rq *rq) 1217 { 1218 struct mlx5e_priv *priv = c->priv; 1219 struct mlx5_core_dev *mdev = priv->mdev; 1220 char buffer[16]; 1221 void *rqc = param->rqc; 1222 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); 1223 int wq_sz; 1224 int err; 1225 int i; 1226 u32 nsegs, wqe_sz; 1227 1228 err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs); 1229 if (err != 0) 1230 goto done; 1231 1232 /* Create DMA descriptor TAG */ 1233 if ((err = -bus_dma_tag_create( 1234 bus_get_dma_tag(mdev->pdev->dev.bsddev), 1235 1, /* any alignment */ 1236 0, /* no boundary */ 1237 BUS_SPACE_MAXADDR, /* lowaddr */ 1238 BUS_SPACE_MAXADDR, /* highaddr */ 1239 NULL, NULL, /* filter, filterarg */ 1240 nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */ 1241 nsegs, /* nsegments */ 1242 nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */ 1243 0, /* flags */ 1244 NULL, NULL, /* lockfunc, lockfuncarg */ 1245 &rq->dma_tag))) 1246 goto done; 1247 1248 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, 1249 &rq->wq_ctrl); 1250 if (err) 1251 goto err_free_dma_tag; 1252 1253 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR]; 1254 1255 err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs); 1256 if (err != 0) 1257 goto err_rq_wq_destroy; 1258 1259 wq_sz = mlx5_wq_ll_get_size(&rq->wq); 1260 1261 err = -tcp_lro_init_args(&rq->lro, priv->ifp, TCP_LRO_ENTRIES, wq_sz); 1262 if (err) 1263 goto err_rq_wq_destroy; 1264 1265 rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO); 1266 for (i = 0; i != wq_sz; i++) { 1267 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i); 1268 int j; 1269 1270 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map); 1271 if (err != 0) { 1272 while (i--) 1273 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 1274 goto err_rq_mbuf_free; 1275 } 1276 1277 /* set value for constant fields */ 1278 for (j = 0; j < rq->nsegs; j++) 1279 wqe->data[j].lkey = cpu_to_be32(priv->mr.key); 1280 } 1281 1282 INIT_WORK(&rq->dim.work, mlx5e_dim_work); 1283 if (priv->params.rx_cq_moderation_mode < 2) { 1284 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 1285 } else { 1286 void *cqc = container_of(param, 1287 struct mlx5e_channel_param, rq)->rx_cq.cqc; 1288 1289 switch (MLX5_GET(cqc, cqc, cq_period_mode)) { 1290 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE: 1291 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; 1292 break; 1293 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE: 1294 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE; 1295 break; 1296 default: 1297 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 1298 break; 1299 } 1300 } 1301 1302 rq->ifp = priv->ifp; 1303 rq->channel = c; 1304 rq->ix = c->ix; 1305 1306 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix); 1307 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 1308 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM, 1309 rq->stats.arg); 1310 return (0); 1311 1312 err_rq_mbuf_free: 1313 free(rq->mbuf, M_MLX5EN); 1314 tcp_lro_free(&rq->lro); 1315 err_rq_wq_destroy: 1316 mlx5_wq_destroy(&rq->wq_ctrl); 1317 err_free_dma_tag: 1318 bus_dma_tag_destroy(rq->dma_tag); 1319 done: 1320 return (err); 1321 } 1322 1323 static void 1324 mlx5e_destroy_rq(struct mlx5e_rq *rq) 1325 { 1326 int wq_sz; 1327 int i; 1328 1329 /* destroy all sysctl nodes */ 1330 sysctl_ctx_free(&rq->stats.ctx); 1331 1332 /* free leftover LRO packets, if any */ 1333 tcp_lro_free(&rq->lro); 1334 1335 wq_sz = mlx5_wq_ll_get_size(&rq->wq); 1336 for (i = 0; i != wq_sz; i++) { 1337 if (rq->mbuf[i].mbuf != NULL) { 1338 bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map); 1339 m_freem(rq->mbuf[i].mbuf); 1340 } 1341 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 1342 } 1343 free(rq->mbuf, M_MLX5EN); 1344 mlx5_wq_destroy(&rq->wq_ctrl); 1345 bus_dma_tag_destroy(rq->dma_tag); 1346 } 1347 1348 static int 1349 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param) 1350 { 1351 struct mlx5e_channel *c = rq->channel; 1352 struct mlx5e_priv *priv = c->priv; 1353 struct mlx5_core_dev *mdev = priv->mdev; 1354 1355 void *in; 1356 void *rqc; 1357 void *wq; 1358 int inlen; 1359 int err; 1360 1361 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 1362 sizeof(u64) * rq->wq_ctrl.buf.npages; 1363 in = mlx5_vzalloc(inlen); 1364 if (in == NULL) 1365 return (-ENOMEM); 1366 1367 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1368 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1369 1370 memcpy(rqc, param->rqc, sizeof(param->rqc)); 1371 1372 MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn); 1373 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1374 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1375 if (priv->counter_set_id >= 0) 1376 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id); 1377 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - 1378 PAGE_SHIFT); 1379 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); 1380 1381 mlx5_fill_page_array(&rq->wq_ctrl.buf, 1382 (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 1383 1384 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); 1385 1386 kvfree(in); 1387 1388 return (err); 1389 } 1390 1391 static int 1392 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state) 1393 { 1394 struct mlx5e_channel *c = rq->channel; 1395 struct mlx5e_priv *priv = c->priv; 1396 struct mlx5_core_dev *mdev = priv->mdev; 1397 1398 void *in; 1399 void *rqc; 1400 int inlen; 1401 int err; 1402 1403 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 1404 in = mlx5_vzalloc(inlen); 1405 if (in == NULL) 1406 return (-ENOMEM); 1407 1408 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1409 1410 MLX5_SET(modify_rq_in, in, rqn, rq->rqn); 1411 MLX5_SET(modify_rq_in, in, rq_state, curr_state); 1412 MLX5_SET(rqc, rqc, state, next_state); 1413 1414 err = mlx5_core_modify_rq(mdev, in, inlen); 1415 1416 kvfree(in); 1417 1418 return (err); 1419 } 1420 1421 static void 1422 mlx5e_disable_rq(struct mlx5e_rq *rq) 1423 { 1424 struct mlx5e_channel *c = rq->channel; 1425 struct mlx5e_priv *priv = c->priv; 1426 struct mlx5_core_dev *mdev = priv->mdev; 1427 1428 mlx5_core_destroy_rq(mdev, rq->rqn); 1429 } 1430 1431 static int 1432 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq) 1433 { 1434 struct mlx5e_channel *c = rq->channel; 1435 struct mlx5e_priv *priv = c->priv; 1436 struct mlx5_wq_ll *wq = &rq->wq; 1437 int i; 1438 1439 for (i = 0; i < 1000; i++) { 1440 if (wq->cur_sz >= priv->params.min_rx_wqes) 1441 return (0); 1442 1443 msleep(4); 1444 } 1445 return (-ETIMEDOUT); 1446 } 1447 1448 static int 1449 mlx5e_open_rq(struct mlx5e_channel *c, 1450 struct mlx5e_rq_param *param, 1451 struct mlx5e_rq *rq) 1452 { 1453 int err; 1454 1455 err = mlx5e_create_rq(c, param, rq); 1456 if (err) 1457 return (err); 1458 1459 err = mlx5e_enable_rq(rq, param); 1460 if (err) 1461 goto err_destroy_rq; 1462 1463 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 1464 if (err) 1465 goto err_disable_rq; 1466 1467 c->rq.enabled = 1; 1468 1469 return (0); 1470 1471 err_disable_rq: 1472 mlx5e_disable_rq(rq); 1473 err_destroy_rq: 1474 mlx5e_destroy_rq(rq); 1475 1476 return (err); 1477 } 1478 1479 static void 1480 mlx5e_close_rq(struct mlx5e_rq *rq) 1481 { 1482 mtx_lock(&rq->mtx); 1483 rq->enabled = 0; 1484 callout_stop(&rq->watchdog); 1485 mtx_unlock(&rq->mtx); 1486 1487 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 1488 } 1489 1490 static void 1491 mlx5e_close_rq_wait(struct mlx5e_rq *rq) 1492 { 1493 1494 mlx5e_disable_rq(rq); 1495 mlx5e_close_cq(&rq->cq); 1496 cancel_work_sync(&rq->dim.work); 1497 mlx5e_destroy_rq(rq); 1498 } 1499 1500 void 1501 mlx5e_free_sq_db(struct mlx5e_sq *sq) 1502 { 1503 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1504 int x; 1505 1506 for (x = 0; x != wq_sz; x++) { 1507 if (unlikely(sq->mbuf[x].p_refcount != NULL)) { 1508 atomic_add_int(sq->mbuf[x].p_refcount, -1); 1509 sq->mbuf[x].p_refcount = NULL; 1510 } 1511 if (sq->mbuf[x].mbuf != NULL) { 1512 bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map); 1513 m_freem(sq->mbuf[x].mbuf); 1514 } 1515 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 1516 } 1517 free(sq->mbuf, M_MLX5EN); 1518 } 1519 1520 int 1521 mlx5e_alloc_sq_db(struct mlx5e_sq *sq) 1522 { 1523 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1524 int err; 1525 int x; 1526 1527 sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO); 1528 1529 /* Create DMA descriptor MAPs */ 1530 for (x = 0; x != wq_sz; x++) { 1531 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map); 1532 if (err != 0) { 1533 while (x--) 1534 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 1535 free(sq->mbuf, M_MLX5EN); 1536 return (err); 1537 } 1538 } 1539 return (0); 1540 } 1541 1542 static const char *mlx5e_sq_stats_desc[] = { 1543 MLX5E_SQ_STATS(MLX5E_STATS_DESC) 1544 }; 1545 1546 void 1547 mlx5e_update_sq_inline(struct mlx5e_sq *sq) 1548 { 1549 sq->max_inline = sq->priv->params.tx_max_inline; 1550 sq->min_inline_mode = sq->priv->params.tx_min_inline_mode; 1551 1552 /* 1553 * Check if trust state is DSCP or if inline mode is NONE which 1554 * indicates CX-5 or newer hardware. 1555 */ 1556 if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP || 1557 sq->min_inline_mode == MLX5_INLINE_MODE_NONE) { 1558 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert)) 1559 sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN; 1560 else 1561 sq->min_insert_caps = MLX5E_INSERT_NON_VLAN; 1562 } else { 1563 sq->min_insert_caps = 0; 1564 } 1565 } 1566 1567 static void 1568 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c) 1569 { 1570 int i; 1571 1572 for (i = 0; i != priv->num_tc; i++) { 1573 mtx_lock(&c->sq[i].lock); 1574 mlx5e_update_sq_inline(&c->sq[i]); 1575 mtx_unlock(&c->sq[i].lock); 1576 } 1577 } 1578 1579 void 1580 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv) 1581 { 1582 int i; 1583 1584 /* check if channels are closed */ 1585 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 1586 return; 1587 1588 for (i = 0; i < priv->params.num_channels; i++) 1589 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]); 1590 } 1591 1592 static int 1593 mlx5e_create_sq(struct mlx5e_channel *c, 1594 int tc, 1595 struct mlx5e_sq_param *param, 1596 struct mlx5e_sq *sq) 1597 { 1598 struct mlx5e_priv *priv = c->priv; 1599 struct mlx5_core_dev *mdev = priv->mdev; 1600 char buffer[16]; 1601 void *sqc = param->sqc; 1602 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq); 1603 int err; 1604 1605 /* Create DMA descriptor TAG */ 1606 if ((err = -bus_dma_tag_create( 1607 bus_get_dma_tag(mdev->pdev->dev.bsddev), 1608 1, /* any alignment */ 1609 0, /* no boundary */ 1610 BUS_SPACE_MAXADDR, /* lowaddr */ 1611 BUS_SPACE_MAXADDR, /* highaddr */ 1612 NULL, NULL, /* filter, filterarg */ 1613 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */ 1614 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */ 1615 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */ 1616 0, /* flags */ 1617 NULL, NULL, /* lockfunc, lockfuncarg */ 1618 &sq->dma_tag))) 1619 goto done; 1620 1621 err = mlx5_alloc_map_uar(mdev, &sq->uar); 1622 if (err) 1623 goto err_free_dma_tag; 1624 1625 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, 1626 &sq->wq_ctrl); 1627 if (err) 1628 goto err_unmap_free_uar; 1629 1630 sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; 1631 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2; 1632 1633 err = mlx5e_alloc_sq_db(sq); 1634 if (err) 1635 goto err_sq_wq_destroy; 1636 1637 sq->mkey_be = cpu_to_be32(priv->mr.key); 1638 sq->ifp = priv->ifp; 1639 sq->priv = priv; 1640 sq->tc = tc; 1641 1642 mlx5e_update_sq_inline(sq); 1643 1644 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc); 1645 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 1646 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM, 1647 sq->stats.arg); 1648 1649 return (0); 1650 1651 err_sq_wq_destroy: 1652 mlx5_wq_destroy(&sq->wq_ctrl); 1653 1654 err_unmap_free_uar: 1655 mlx5_unmap_free_uar(mdev, &sq->uar); 1656 1657 err_free_dma_tag: 1658 bus_dma_tag_destroy(sq->dma_tag); 1659 done: 1660 return (err); 1661 } 1662 1663 static void 1664 mlx5e_destroy_sq(struct mlx5e_sq *sq) 1665 { 1666 /* destroy all sysctl nodes */ 1667 sysctl_ctx_free(&sq->stats.ctx); 1668 1669 mlx5e_free_sq_db(sq); 1670 mlx5_wq_destroy(&sq->wq_ctrl); 1671 mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar); 1672 bus_dma_tag_destroy(sq->dma_tag); 1673 } 1674 1675 int 1676 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param, 1677 int tis_num) 1678 { 1679 void *in; 1680 void *sqc; 1681 void *wq; 1682 int inlen; 1683 int err; 1684 1685 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1686 sizeof(u64) * sq->wq_ctrl.buf.npages; 1687 in = mlx5_vzalloc(inlen); 1688 if (in == NULL) 1689 return (-ENOMEM); 1690 1691 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1692 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1693 1694 memcpy(sqc, param->sqc, sizeof(param->sqc)); 1695 1696 MLX5_SET(sqc, sqc, tis_num_0, tis_num); 1697 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn); 1698 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1699 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1700 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1701 1702 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1703 MLX5_SET(wq, wq, uar_page, sq->uar.index); 1704 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift - 1705 PAGE_SHIFT); 1706 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma); 1707 1708 mlx5_fill_page_array(&sq->wq_ctrl.buf, 1709 (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 1710 1711 err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn); 1712 1713 kvfree(in); 1714 1715 return (err); 1716 } 1717 1718 int 1719 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state) 1720 { 1721 void *in; 1722 void *sqc; 1723 int inlen; 1724 int err; 1725 1726 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 1727 in = mlx5_vzalloc(inlen); 1728 if (in == NULL) 1729 return (-ENOMEM); 1730 1731 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1732 1733 MLX5_SET(modify_sq_in, in, sqn, sq->sqn); 1734 MLX5_SET(modify_sq_in, in, sq_state, curr_state); 1735 MLX5_SET(sqc, sqc, state, next_state); 1736 1737 err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen); 1738 1739 kvfree(in); 1740 1741 return (err); 1742 } 1743 1744 void 1745 mlx5e_disable_sq(struct mlx5e_sq *sq) 1746 { 1747 1748 mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn); 1749 } 1750 1751 static int 1752 mlx5e_open_sq(struct mlx5e_channel *c, 1753 int tc, 1754 struct mlx5e_sq_param *param, 1755 struct mlx5e_sq *sq) 1756 { 1757 int err; 1758 1759 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact; 1760 1761 /* ensure the TX completion event factor is not zero */ 1762 if (sq->cev_factor == 0) 1763 sq->cev_factor = 1; 1764 1765 err = mlx5e_create_sq(c, tc, param, sq); 1766 if (err) 1767 return (err); 1768 1769 err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]); 1770 if (err) 1771 goto err_destroy_sq; 1772 1773 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY); 1774 if (err) 1775 goto err_disable_sq; 1776 1777 WRITE_ONCE(sq->running, 1); 1778 1779 return (0); 1780 1781 err_disable_sq: 1782 mlx5e_disable_sq(sq); 1783 err_destroy_sq: 1784 mlx5e_destroy_sq(sq); 1785 1786 return (err); 1787 } 1788 1789 static void 1790 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep) 1791 { 1792 /* fill up remainder with NOPs */ 1793 while (sq->cev_counter != 0) { 1794 while (!mlx5e_sq_has_room_for(sq, 1)) { 1795 if (can_sleep != 0) { 1796 mtx_unlock(&sq->lock); 1797 msleep(4); 1798 mtx_lock(&sq->lock); 1799 } else { 1800 goto done; 1801 } 1802 } 1803 /* send a single NOP */ 1804 mlx5e_send_nop(sq, 1); 1805 atomic_thread_fence_rel(); 1806 } 1807 done: 1808 /* Check if we need to write the doorbell */ 1809 if (likely(sq->doorbell.d64 != 0)) { 1810 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0); 1811 sq->doorbell.d64 = 0; 1812 } 1813 } 1814 1815 void 1816 mlx5e_sq_cev_timeout(void *arg) 1817 { 1818 struct mlx5e_sq *sq = arg; 1819 1820 mtx_assert(&sq->lock, MA_OWNED); 1821 1822 /* check next state */ 1823 switch (sq->cev_next_state) { 1824 case MLX5E_CEV_STATE_SEND_NOPS: 1825 /* fill TX ring with NOPs, if any */ 1826 mlx5e_sq_send_nops_locked(sq, 0); 1827 1828 /* check if completed */ 1829 if (sq->cev_counter == 0) { 1830 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL; 1831 return; 1832 } 1833 break; 1834 default: 1835 /* send NOPs on next timeout */ 1836 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS; 1837 break; 1838 } 1839 1840 /* restart timer */ 1841 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq); 1842 } 1843 1844 void 1845 mlx5e_drain_sq(struct mlx5e_sq *sq) 1846 { 1847 int error; 1848 struct mlx5_core_dev *mdev= sq->priv->mdev; 1849 1850 /* 1851 * Check if already stopped. 1852 * 1853 * NOTE: Serialization of this function is managed by the 1854 * caller ensuring the priv's state lock is locked or in case 1855 * of rate limit support, a single thread manages drain and 1856 * resume of SQs. The "running" variable can therefore safely 1857 * be read without any locks. 1858 */ 1859 if (READ_ONCE(sq->running) == 0) 1860 return; 1861 1862 /* don't put more packets into the SQ */ 1863 WRITE_ONCE(sq->running, 0); 1864 1865 /* serialize access to DMA rings */ 1866 mtx_lock(&sq->lock); 1867 1868 /* teardown event factor timer, if any */ 1869 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS; 1870 callout_stop(&sq->cev_callout); 1871 1872 /* send dummy NOPs in order to flush the transmit ring */ 1873 mlx5e_sq_send_nops_locked(sq, 1); 1874 mtx_unlock(&sq->lock); 1875 1876 /* wait till SQ is empty or link is down */ 1877 mtx_lock(&sq->lock); 1878 while (sq->cc != sq->pc && 1879 (sq->priv->media_status_last & IFM_ACTIVE) != 0 && 1880 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1881 mtx_unlock(&sq->lock); 1882 msleep(1); 1883 sq->cq.mcq.comp(&sq->cq.mcq); 1884 mtx_lock(&sq->lock); 1885 } 1886 mtx_unlock(&sq->lock); 1887 1888 /* error out remaining requests */ 1889 error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR); 1890 if (error != 0) { 1891 mlx5_en_err(sq->ifp, 1892 "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error); 1893 } 1894 1895 /* wait till SQ is empty */ 1896 mtx_lock(&sq->lock); 1897 while (sq->cc != sq->pc && 1898 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1899 mtx_unlock(&sq->lock); 1900 msleep(1); 1901 sq->cq.mcq.comp(&sq->cq.mcq); 1902 mtx_lock(&sq->lock); 1903 } 1904 mtx_unlock(&sq->lock); 1905 } 1906 1907 static void 1908 mlx5e_close_sq_wait(struct mlx5e_sq *sq) 1909 { 1910 1911 mlx5e_drain_sq(sq); 1912 mlx5e_disable_sq(sq); 1913 mlx5e_destroy_sq(sq); 1914 } 1915 1916 static int 1917 mlx5e_create_cq(struct mlx5e_priv *priv, 1918 struct mlx5e_cq_param *param, 1919 struct mlx5e_cq *cq, 1920 mlx5e_cq_comp_t *comp, 1921 int eq_ix) 1922 { 1923 struct mlx5_core_dev *mdev = priv->mdev; 1924 struct mlx5_core_cq *mcq = &cq->mcq; 1925 int eqn_not_used; 1926 int irqn; 1927 int err; 1928 u32 i; 1929 1930 param->wq.buf_numa_node = 0; 1931 param->wq.db_numa_node = 0; 1932 1933 err = mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn); 1934 if (err) 1935 return (err); 1936 1937 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, 1938 &cq->wq_ctrl); 1939 if (err) 1940 return (err); 1941 1942 mcq->cqe_sz = 64; 1943 mcq->set_ci_db = cq->wq_ctrl.db.db; 1944 mcq->arm_db = cq->wq_ctrl.db.db + 1; 1945 *mcq->set_ci_db = 0; 1946 *mcq->arm_db = 0; 1947 mcq->vector = eq_ix; 1948 mcq->comp = comp; 1949 mcq->event = mlx5e_cq_error_event; 1950 mcq->irqn = irqn; 1951 mcq->uar = &priv->cq_uar; 1952 1953 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { 1954 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); 1955 1956 cqe->op_own = 0xf1; 1957 } 1958 1959 cq->priv = priv; 1960 1961 return (0); 1962 } 1963 1964 static void 1965 mlx5e_destroy_cq(struct mlx5e_cq *cq) 1966 { 1967 mlx5_wq_destroy(&cq->wq_ctrl); 1968 } 1969 1970 static int 1971 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix) 1972 { 1973 struct mlx5_core_cq *mcq = &cq->mcq; 1974 void *in; 1975 void *cqc; 1976 int inlen; 1977 int irqn_not_used; 1978 int eqn; 1979 int err; 1980 1981 inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 1982 sizeof(u64) * cq->wq_ctrl.buf.npages; 1983 in = mlx5_vzalloc(inlen); 1984 if (in == NULL) 1985 return (-ENOMEM); 1986 1987 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1988 1989 memcpy(cqc, param->cqc, sizeof(param->cqc)); 1990 1991 mlx5_fill_page_array(&cq->wq_ctrl.buf, 1992 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas)); 1993 1994 mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used); 1995 1996 MLX5_SET(cqc, cqc, c_eqn, eqn); 1997 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index); 1998 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - 1999 PAGE_SHIFT); 2000 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); 2001 2002 err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen); 2003 2004 kvfree(in); 2005 2006 if (err) 2007 return (err); 2008 2009 mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock)); 2010 2011 return (0); 2012 } 2013 2014 static void 2015 mlx5e_disable_cq(struct mlx5e_cq *cq) 2016 { 2017 2018 mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq); 2019 } 2020 2021 int 2022 mlx5e_open_cq(struct mlx5e_priv *priv, 2023 struct mlx5e_cq_param *param, 2024 struct mlx5e_cq *cq, 2025 mlx5e_cq_comp_t *comp, 2026 int eq_ix) 2027 { 2028 int err; 2029 2030 err = mlx5e_create_cq(priv, param, cq, comp, eq_ix); 2031 if (err) 2032 return (err); 2033 2034 err = mlx5e_enable_cq(cq, param, eq_ix); 2035 if (err) 2036 goto err_destroy_cq; 2037 2038 return (0); 2039 2040 err_destroy_cq: 2041 mlx5e_destroy_cq(cq); 2042 2043 return (err); 2044 } 2045 2046 void 2047 mlx5e_close_cq(struct mlx5e_cq *cq) 2048 { 2049 mlx5e_disable_cq(cq); 2050 mlx5e_destroy_cq(cq); 2051 } 2052 2053 static int 2054 mlx5e_open_tx_cqs(struct mlx5e_channel *c, 2055 struct mlx5e_channel_param *cparam) 2056 { 2057 int err; 2058 int tc; 2059 2060 for (tc = 0; tc < c->priv->num_tc; tc++) { 2061 /* open completion queue */ 2062 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq, 2063 &mlx5e_tx_cq_comp, c->ix); 2064 if (err) 2065 goto err_close_tx_cqs; 2066 } 2067 return (0); 2068 2069 err_close_tx_cqs: 2070 for (tc--; tc >= 0; tc--) 2071 mlx5e_close_cq(&c->sq[tc].cq); 2072 2073 return (err); 2074 } 2075 2076 static void 2077 mlx5e_close_tx_cqs(struct mlx5e_channel *c) 2078 { 2079 int tc; 2080 2081 for (tc = 0; tc < c->priv->num_tc; tc++) 2082 mlx5e_close_cq(&c->sq[tc].cq); 2083 } 2084 2085 static int 2086 mlx5e_open_sqs(struct mlx5e_channel *c, 2087 struct mlx5e_channel_param *cparam) 2088 { 2089 int err; 2090 int tc; 2091 2092 for (tc = 0; tc < c->priv->num_tc; tc++) { 2093 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]); 2094 if (err) 2095 goto err_close_sqs; 2096 } 2097 2098 return (0); 2099 2100 err_close_sqs: 2101 for (tc--; tc >= 0; tc--) 2102 mlx5e_close_sq_wait(&c->sq[tc]); 2103 2104 return (err); 2105 } 2106 2107 static void 2108 mlx5e_close_sqs_wait(struct mlx5e_channel *c) 2109 { 2110 int tc; 2111 2112 for (tc = 0; tc < c->priv->num_tc; tc++) 2113 mlx5e_close_sq_wait(&c->sq[tc]); 2114 } 2115 2116 static void 2117 mlx5e_chan_static_init(struct mlx5e_priv *priv, struct mlx5e_channel *c, int ix) 2118 { 2119 int tc; 2120 2121 /* setup priv and channel number */ 2122 c->priv = priv; 2123 c->ix = ix; 2124 2125 /* setup send tag */ 2126 c->tag.type = IF_SND_TAG_TYPE_UNLIMITED; 2127 m_snd_tag_init(&c->tag.m_snd_tag, c->priv->ifp); 2128 2129 init_completion(&c->completion); 2130 2131 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF); 2132 2133 callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0); 2134 2135 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) { 2136 struct mlx5e_sq *sq = c->sq + tc; 2137 2138 mtx_init(&sq->lock, "mlx5tx", 2139 MTX_NETWORK_LOCK " TX", MTX_DEF); 2140 mtx_init(&sq->comp_lock, "mlx5comp", 2141 MTX_NETWORK_LOCK " TX", MTX_DEF); 2142 2143 callout_init_mtx(&sq->cev_callout, &sq->lock, 0); 2144 } 2145 } 2146 2147 static void 2148 mlx5e_chan_wait_for_completion(struct mlx5e_channel *c) 2149 { 2150 2151 m_snd_tag_rele(&c->tag.m_snd_tag); 2152 wait_for_completion(&c->completion); 2153 } 2154 2155 static void 2156 mlx5e_priv_wait_for_completion(struct mlx5e_priv *priv, const uint32_t channels) 2157 { 2158 uint32_t x; 2159 2160 for (x = 0; x != channels; x++) 2161 mlx5e_chan_wait_for_completion(&priv->channel[x]); 2162 } 2163 2164 static void 2165 mlx5e_chan_static_destroy(struct mlx5e_channel *c) 2166 { 2167 int tc; 2168 2169 callout_drain(&c->rq.watchdog); 2170 2171 mtx_destroy(&c->rq.mtx); 2172 2173 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) { 2174 callout_drain(&c->sq[tc].cev_callout); 2175 mtx_destroy(&c->sq[tc].lock); 2176 mtx_destroy(&c->sq[tc].comp_lock); 2177 } 2178 } 2179 2180 static int 2181 mlx5e_open_channel(struct mlx5e_priv *priv, 2182 struct mlx5e_channel_param *cparam, 2183 struct mlx5e_channel *c) 2184 { 2185 struct epoch_tracker et; 2186 int i, err; 2187 2188 /* zero non-persistant data */ 2189 MLX5E_ZERO(&c->rq, mlx5e_rq_zero_start); 2190 for (i = 0; i != priv->num_tc; i++) 2191 MLX5E_ZERO(&c->sq[i], mlx5e_sq_zero_start); 2192 2193 /* open transmit completion queue */ 2194 err = mlx5e_open_tx_cqs(c, cparam); 2195 if (err) 2196 goto err_free; 2197 2198 /* open receive completion queue */ 2199 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq, 2200 &mlx5e_rx_cq_comp, c->ix); 2201 if (err) 2202 goto err_close_tx_cqs; 2203 2204 err = mlx5e_open_sqs(c, cparam); 2205 if (err) 2206 goto err_close_rx_cq; 2207 2208 err = mlx5e_open_rq(c, &cparam->rq, &c->rq); 2209 if (err) 2210 goto err_close_sqs; 2211 2212 /* poll receive queue initially */ 2213 NET_EPOCH_ENTER(et); 2214 c->rq.cq.mcq.comp(&c->rq.cq.mcq); 2215 NET_EPOCH_EXIT(et); 2216 2217 return (0); 2218 2219 err_close_sqs: 2220 mlx5e_close_sqs_wait(c); 2221 2222 err_close_rx_cq: 2223 mlx5e_close_cq(&c->rq.cq); 2224 2225 err_close_tx_cqs: 2226 mlx5e_close_tx_cqs(c); 2227 2228 err_free: 2229 return (err); 2230 } 2231 2232 static void 2233 mlx5e_close_channel(struct mlx5e_channel *c) 2234 { 2235 mlx5e_close_rq(&c->rq); 2236 } 2237 2238 static void 2239 mlx5e_close_channel_wait(struct mlx5e_channel *c) 2240 { 2241 mlx5e_close_rq_wait(&c->rq); 2242 mlx5e_close_sqs_wait(c); 2243 mlx5e_close_tx_cqs(c); 2244 } 2245 2246 static int 2247 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs) 2248 { 2249 u32 r, n; 2250 2251 r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz : 2252 MLX5E_SW2MB_MTU(priv->ifp->if_mtu); 2253 if (r > MJUM16BYTES) 2254 return (-ENOMEM); 2255 2256 if (r > MJUM9BYTES) 2257 r = MJUM16BYTES; 2258 else if (r > MJUMPAGESIZE) 2259 r = MJUM9BYTES; 2260 else if (r > MCLBYTES) 2261 r = MJUMPAGESIZE; 2262 else 2263 r = MCLBYTES; 2264 2265 /* 2266 * n + 1 must be a power of two, because stride size must be. 2267 * Stride size is 16 * (n + 1), as the first segment is 2268 * control. 2269 */ 2270 for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++) 2271 ; 2272 2273 if (n > MLX5E_MAX_BUSDMA_RX_SEGS) 2274 return (-ENOMEM); 2275 2276 *wqe_sz = r; 2277 *nsegs = n; 2278 return (0); 2279 } 2280 2281 static void 2282 mlx5e_build_rq_param(struct mlx5e_priv *priv, 2283 struct mlx5e_rq_param *param) 2284 { 2285 void *rqc = param->rqc; 2286 void *wq = MLX5_ADDR_OF(rqc, rqc, wq); 2287 u32 wqe_sz, nsegs; 2288 2289 mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs); 2290 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); 2291 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 2292 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) + 2293 nsegs * sizeof(struct mlx5_wqe_data_seg))); 2294 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size); 2295 MLX5_SET(wq, wq, pd, priv->pdn); 2296 2297 param->wq.buf_numa_node = 0; 2298 param->wq.db_numa_node = 0; 2299 param->wq.linear = 1; 2300 } 2301 2302 static void 2303 mlx5e_build_sq_param(struct mlx5e_priv *priv, 2304 struct mlx5e_sq_param *param) 2305 { 2306 void *sqc = param->sqc; 2307 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 2308 2309 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size); 2310 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 2311 MLX5_SET(wq, wq, pd, priv->pdn); 2312 2313 param->wq.buf_numa_node = 0; 2314 param->wq.db_numa_node = 0; 2315 param->wq.linear = 1; 2316 } 2317 2318 static void 2319 mlx5e_build_common_cq_param(struct mlx5e_priv *priv, 2320 struct mlx5e_cq_param *param) 2321 { 2322 void *cqc = param->cqc; 2323 2324 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index); 2325 } 2326 2327 static void 2328 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr) 2329 { 2330 2331 *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE); 2332 2333 /* apply LRO restrictions */ 2334 if (priv->params.hw_lro_en && 2335 ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) { 2336 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO; 2337 } 2338 } 2339 2340 static void 2341 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, 2342 struct mlx5e_cq_param *param) 2343 { 2344 struct net_dim_cq_moder curr; 2345 void *cqc = param->cqc; 2346 2347 /* 2348 * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE 2349 * format is more beneficial for FreeBSD use case. 2350 * 2351 * Adding support for MLX5_CQE_FORMAT_CSUM will require changes 2352 * in mlx5e_decompress_cqe. 2353 */ 2354 if (priv->params.cqe_zipping_en) { 2355 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH); 2356 MLX5_SET(cqc, cqc, cqe_compression_en, 1); 2357 } 2358 2359 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size); 2360 2361 switch (priv->params.rx_cq_moderation_mode) { 2362 case 0: 2363 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec); 2364 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts); 2365 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2366 break; 2367 case 1: 2368 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec); 2369 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts); 2370 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2371 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2372 else 2373 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2374 break; 2375 case 2: 2376 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr); 2377 MLX5_SET(cqc, cqc, cq_period, curr.usec); 2378 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts); 2379 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2380 break; 2381 case 3: 2382 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr); 2383 MLX5_SET(cqc, cqc, cq_period, curr.usec); 2384 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts); 2385 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2386 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2387 else 2388 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2389 break; 2390 default: 2391 break; 2392 } 2393 2394 mlx5e_dim_build_cq_param(priv, param); 2395 2396 mlx5e_build_common_cq_param(priv, param); 2397 } 2398 2399 static void 2400 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv, 2401 struct mlx5e_cq_param *param) 2402 { 2403 void *cqc = param->cqc; 2404 2405 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size); 2406 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec); 2407 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts); 2408 2409 switch (priv->params.tx_cq_moderation_mode) { 2410 case 0: 2411 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2412 break; 2413 default: 2414 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2415 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2416 else 2417 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2418 break; 2419 } 2420 2421 mlx5e_build_common_cq_param(priv, param); 2422 } 2423 2424 static void 2425 mlx5e_build_channel_param(struct mlx5e_priv *priv, 2426 struct mlx5e_channel_param *cparam) 2427 { 2428 memset(cparam, 0, sizeof(*cparam)); 2429 2430 mlx5e_build_rq_param(priv, &cparam->rq); 2431 mlx5e_build_sq_param(priv, &cparam->sq); 2432 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq); 2433 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq); 2434 } 2435 2436 static int 2437 mlx5e_open_channels(struct mlx5e_priv *priv) 2438 { 2439 struct mlx5e_channel_param *cparam; 2440 int err; 2441 int i; 2442 int j; 2443 2444 cparam = malloc(sizeof(*cparam), M_MLX5EN, M_WAITOK); 2445 2446 mlx5e_build_channel_param(priv, cparam); 2447 for (i = 0; i < priv->params.num_channels; i++) { 2448 err = mlx5e_open_channel(priv, cparam, &priv->channel[i]); 2449 if (err) 2450 goto err_close_channels; 2451 } 2452 2453 for (j = 0; j < priv->params.num_channels; j++) { 2454 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq); 2455 if (err) 2456 goto err_close_channels; 2457 } 2458 free(cparam, M_MLX5EN); 2459 return (0); 2460 2461 err_close_channels: 2462 while (i--) { 2463 mlx5e_close_channel(&priv->channel[i]); 2464 mlx5e_close_channel_wait(&priv->channel[i]); 2465 } 2466 free(cparam, M_MLX5EN); 2467 return (err); 2468 } 2469 2470 static void 2471 mlx5e_close_channels(struct mlx5e_priv *priv) 2472 { 2473 int i; 2474 2475 for (i = 0; i < priv->params.num_channels; i++) 2476 mlx5e_close_channel(&priv->channel[i]); 2477 for (i = 0; i < priv->params.num_channels; i++) 2478 mlx5e_close_channel_wait(&priv->channel[i]); 2479 } 2480 2481 static int 2482 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq) 2483 { 2484 2485 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) { 2486 uint8_t cq_mode; 2487 2488 switch (priv->params.tx_cq_moderation_mode) { 2489 case 0: 2490 case 2: 2491 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 2492 break; 2493 default: 2494 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE; 2495 break; 2496 } 2497 2498 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq, 2499 priv->params.tx_cq_moderation_usec, 2500 priv->params.tx_cq_moderation_pkts, 2501 cq_mode)); 2502 } 2503 2504 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq, 2505 priv->params.tx_cq_moderation_usec, 2506 priv->params.tx_cq_moderation_pkts)); 2507 } 2508 2509 static int 2510 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq) 2511 { 2512 2513 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) { 2514 uint8_t cq_mode; 2515 uint8_t dim_mode; 2516 int retval; 2517 2518 switch (priv->params.rx_cq_moderation_mode) { 2519 case 0: 2520 case 2: 2521 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 2522 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; 2523 break; 2524 default: 2525 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE; 2526 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE; 2527 break; 2528 } 2529 2530 /* tear down dynamic interrupt moderation */ 2531 mtx_lock(&rq->mtx); 2532 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 2533 mtx_unlock(&rq->mtx); 2534 2535 /* wait for dynamic interrupt moderation work task, if any */ 2536 cancel_work_sync(&rq->dim.work); 2537 2538 if (priv->params.rx_cq_moderation_mode >= 2) { 2539 struct net_dim_cq_moder curr; 2540 2541 mlx5e_get_default_profile(priv, dim_mode, &curr); 2542 2543 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq, 2544 curr.usec, curr.pkts, cq_mode); 2545 2546 /* set dynamic interrupt moderation mode and zero defaults */ 2547 mtx_lock(&rq->mtx); 2548 rq->dim.mode = dim_mode; 2549 rq->dim.state = 0; 2550 rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE; 2551 mtx_unlock(&rq->mtx); 2552 } else { 2553 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq, 2554 priv->params.rx_cq_moderation_usec, 2555 priv->params.rx_cq_moderation_pkts, 2556 cq_mode); 2557 } 2558 return (retval); 2559 } 2560 2561 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq, 2562 priv->params.rx_cq_moderation_usec, 2563 priv->params.rx_cq_moderation_pkts)); 2564 } 2565 2566 static int 2567 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c) 2568 { 2569 int err; 2570 int i; 2571 2572 err = mlx5e_refresh_rq_params(priv, &c->rq); 2573 if (err) 2574 goto done; 2575 2576 for (i = 0; i != priv->num_tc; i++) { 2577 err = mlx5e_refresh_sq_params(priv, &c->sq[i]); 2578 if (err) 2579 goto done; 2580 } 2581 done: 2582 return (err); 2583 } 2584 2585 int 2586 mlx5e_refresh_channel_params(struct mlx5e_priv *priv) 2587 { 2588 int i; 2589 2590 /* check if channels are closed */ 2591 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 2592 return (EINVAL); 2593 2594 for (i = 0; i < priv->params.num_channels; i++) { 2595 int err; 2596 2597 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]); 2598 if (err) 2599 return (err); 2600 } 2601 return (0); 2602 } 2603 2604 static int 2605 mlx5e_open_tis(struct mlx5e_priv *priv, int tc) 2606 { 2607 struct mlx5_core_dev *mdev = priv->mdev; 2608 u32 in[MLX5_ST_SZ_DW(create_tis_in)]; 2609 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 2610 2611 memset(in, 0, sizeof(in)); 2612 2613 MLX5_SET(tisc, tisc, prio, tc); 2614 MLX5_SET(tisc, tisc, transport_domain, priv->tdn); 2615 2616 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc])); 2617 } 2618 2619 static void 2620 mlx5e_close_tis(struct mlx5e_priv *priv, int tc) 2621 { 2622 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]); 2623 } 2624 2625 static int 2626 mlx5e_open_tises(struct mlx5e_priv *priv) 2627 { 2628 int num_tc = priv->num_tc; 2629 int err; 2630 int tc; 2631 2632 for (tc = 0; tc < num_tc; tc++) { 2633 err = mlx5e_open_tis(priv, tc); 2634 if (err) 2635 goto err_close_tises; 2636 } 2637 2638 return (0); 2639 2640 err_close_tises: 2641 for (tc--; tc >= 0; tc--) 2642 mlx5e_close_tis(priv, tc); 2643 2644 return (err); 2645 } 2646 2647 static void 2648 mlx5e_close_tises(struct mlx5e_priv *priv) 2649 { 2650 int num_tc = priv->num_tc; 2651 int tc; 2652 2653 for (tc = 0; tc < num_tc; tc++) 2654 mlx5e_close_tis(priv, tc); 2655 } 2656 2657 static int 2658 mlx5e_open_rqt(struct mlx5e_priv *priv) 2659 { 2660 struct mlx5_core_dev *mdev = priv->mdev; 2661 u32 *in; 2662 u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 2663 void *rqtc; 2664 int inlen; 2665 int err; 2666 int sz; 2667 int i; 2668 2669 sz = 1 << priv->params.rx_hash_log_tbl_sz; 2670 2671 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 2672 in = mlx5_vzalloc(inlen); 2673 if (in == NULL) 2674 return (-ENOMEM); 2675 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 2676 2677 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 2678 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 2679 2680 for (i = 0; i < sz; i++) { 2681 int ix = i; 2682 #ifdef RSS 2683 ix = rss_get_indirection_to_bucket(ix); 2684 #endif 2685 /* ensure we don't overflow */ 2686 ix %= priv->params.num_channels; 2687 2688 /* apply receive side scaling stride, if any */ 2689 ix -= ix % (int)priv->params.channels_rsss; 2690 2691 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn); 2692 } 2693 2694 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 2695 2696 err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out)); 2697 if (!err) 2698 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn); 2699 2700 kvfree(in); 2701 2702 return (err); 2703 } 2704 2705 static void 2706 mlx5e_close_rqt(struct mlx5e_priv *priv) 2707 { 2708 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0}; 2709 u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0}; 2710 2711 MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT); 2712 MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn); 2713 2714 mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)); 2715 } 2716 2717 static void 2718 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt) 2719 { 2720 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 2721 __be32 *hkey; 2722 2723 MLX5_SET(tirc, tirc, transport_domain, priv->tdn); 2724 2725 #define ROUGH_MAX_L2_L3_HDR_SZ 256 2726 2727 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2728 MLX5_HASH_FIELD_SEL_DST_IP) 2729 2730 #define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2731 MLX5_HASH_FIELD_SEL_DST_IP |\ 2732 MLX5_HASH_FIELD_SEL_L4_SPORT |\ 2733 MLX5_HASH_FIELD_SEL_L4_DPORT) 2734 2735 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2736 MLX5_HASH_FIELD_SEL_DST_IP |\ 2737 MLX5_HASH_FIELD_SEL_IPSEC_SPI) 2738 2739 if (priv->params.hw_lro_en) { 2740 MLX5_SET(tirc, tirc, lro_enable_mask, 2741 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | 2742 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO); 2743 MLX5_SET(tirc, tirc, lro_max_msg_sz, 2744 (priv->params.lro_wqe_sz - 2745 ROUGH_MAX_L2_L3_HDR_SZ) >> 8); 2746 /* TODO: add the option to choose timer value dynamically */ 2747 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, 2748 MLX5_CAP_ETH(priv->mdev, 2749 lro_timer_supported_periods[2])); 2750 } 2751 2752 /* setup parameters for hashing TIR type, if any */ 2753 switch (tt) { 2754 case MLX5E_TT_ANY: 2755 MLX5_SET(tirc, tirc, disp_type, 2756 MLX5_TIRC_DISP_TYPE_DIRECT); 2757 MLX5_SET(tirc, tirc, inline_rqn, 2758 priv->channel[0].rq.rqn); 2759 break; 2760 default: 2761 MLX5_SET(tirc, tirc, disp_type, 2762 MLX5_TIRC_DISP_TYPE_INDIRECT); 2763 MLX5_SET(tirc, tirc, indirect_table, 2764 priv->rqtn); 2765 MLX5_SET(tirc, tirc, rx_hash_fn, 2766 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ); 2767 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 2768 #ifdef RSS 2769 /* 2770 * The FreeBSD RSS implementation does currently not 2771 * support symmetric Toeplitz hashes: 2772 */ 2773 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0); 2774 rss_getkey((uint8_t *)hkey); 2775 #else 2776 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 2777 hkey[0] = cpu_to_be32(0xD181C62C); 2778 hkey[1] = cpu_to_be32(0xF7F4DB5B); 2779 hkey[2] = cpu_to_be32(0x1983A2FC); 2780 hkey[3] = cpu_to_be32(0x943E1ADB); 2781 hkey[4] = cpu_to_be32(0xD9389E6B); 2782 hkey[5] = cpu_to_be32(0xD1039C2C); 2783 hkey[6] = cpu_to_be32(0xA74499AD); 2784 hkey[7] = cpu_to_be32(0x593D56D9); 2785 hkey[8] = cpu_to_be32(0xF3253C06); 2786 hkey[9] = cpu_to_be32(0x2ADC1FFC); 2787 #endif 2788 break; 2789 } 2790 2791 switch (tt) { 2792 case MLX5E_TT_IPV4_TCP: 2793 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2794 MLX5_L3_PROT_TYPE_IPV4); 2795 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2796 MLX5_L4_PROT_TYPE_TCP); 2797 #ifdef RSS 2798 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) { 2799 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2800 MLX5_HASH_IP); 2801 } else 2802 #endif 2803 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2804 MLX5_HASH_ALL); 2805 break; 2806 2807 case MLX5E_TT_IPV6_TCP: 2808 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2809 MLX5_L3_PROT_TYPE_IPV6); 2810 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2811 MLX5_L4_PROT_TYPE_TCP); 2812 #ifdef RSS 2813 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) { 2814 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2815 MLX5_HASH_IP); 2816 } else 2817 #endif 2818 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2819 MLX5_HASH_ALL); 2820 break; 2821 2822 case MLX5E_TT_IPV4_UDP: 2823 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2824 MLX5_L3_PROT_TYPE_IPV4); 2825 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2826 MLX5_L4_PROT_TYPE_UDP); 2827 #ifdef RSS 2828 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) { 2829 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2830 MLX5_HASH_IP); 2831 } else 2832 #endif 2833 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2834 MLX5_HASH_ALL); 2835 break; 2836 2837 case MLX5E_TT_IPV6_UDP: 2838 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2839 MLX5_L3_PROT_TYPE_IPV6); 2840 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2841 MLX5_L4_PROT_TYPE_UDP); 2842 #ifdef RSS 2843 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) { 2844 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2845 MLX5_HASH_IP); 2846 } else 2847 #endif 2848 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2849 MLX5_HASH_ALL); 2850 break; 2851 2852 case MLX5E_TT_IPV4_IPSEC_AH: 2853 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2854 MLX5_L3_PROT_TYPE_IPV4); 2855 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2856 MLX5_HASH_IP_IPSEC_SPI); 2857 break; 2858 2859 case MLX5E_TT_IPV6_IPSEC_AH: 2860 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2861 MLX5_L3_PROT_TYPE_IPV6); 2862 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2863 MLX5_HASH_IP_IPSEC_SPI); 2864 break; 2865 2866 case MLX5E_TT_IPV4_IPSEC_ESP: 2867 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2868 MLX5_L3_PROT_TYPE_IPV4); 2869 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2870 MLX5_HASH_IP_IPSEC_SPI); 2871 break; 2872 2873 case MLX5E_TT_IPV6_IPSEC_ESP: 2874 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2875 MLX5_L3_PROT_TYPE_IPV6); 2876 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2877 MLX5_HASH_IP_IPSEC_SPI); 2878 break; 2879 2880 case MLX5E_TT_IPV4: 2881 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2882 MLX5_L3_PROT_TYPE_IPV4); 2883 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2884 MLX5_HASH_IP); 2885 break; 2886 2887 case MLX5E_TT_IPV6: 2888 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2889 MLX5_L3_PROT_TYPE_IPV6); 2890 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2891 MLX5_HASH_IP); 2892 break; 2893 2894 default: 2895 break; 2896 } 2897 } 2898 2899 static int 2900 mlx5e_open_tir(struct mlx5e_priv *priv, int tt) 2901 { 2902 struct mlx5_core_dev *mdev = priv->mdev; 2903 u32 *in; 2904 void *tirc; 2905 int inlen; 2906 int err; 2907 2908 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 2909 in = mlx5_vzalloc(inlen); 2910 if (in == NULL) 2911 return (-ENOMEM); 2912 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context); 2913 2914 mlx5e_build_tir_ctx(priv, tirc, tt); 2915 2916 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]); 2917 2918 kvfree(in); 2919 2920 return (err); 2921 } 2922 2923 static void 2924 mlx5e_close_tir(struct mlx5e_priv *priv, int tt) 2925 { 2926 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]); 2927 } 2928 2929 static int 2930 mlx5e_open_tirs(struct mlx5e_priv *priv) 2931 { 2932 int err; 2933 int i; 2934 2935 for (i = 0; i < MLX5E_NUM_TT; i++) { 2936 err = mlx5e_open_tir(priv, i); 2937 if (err) 2938 goto err_close_tirs; 2939 } 2940 2941 return (0); 2942 2943 err_close_tirs: 2944 for (i--; i >= 0; i--) 2945 mlx5e_close_tir(priv, i); 2946 2947 return (err); 2948 } 2949 2950 static void 2951 mlx5e_close_tirs(struct mlx5e_priv *priv) 2952 { 2953 int i; 2954 2955 for (i = 0; i < MLX5E_NUM_TT; i++) 2956 mlx5e_close_tir(priv, i); 2957 } 2958 2959 /* 2960 * SW MTU does not include headers, 2961 * HW MTU includes all headers and checksums. 2962 */ 2963 static int 2964 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu) 2965 { 2966 struct mlx5e_priv *priv = ifp->if_softc; 2967 struct mlx5_core_dev *mdev = priv->mdev; 2968 int hw_mtu; 2969 int err; 2970 2971 hw_mtu = MLX5E_SW2HW_MTU(sw_mtu); 2972 2973 err = mlx5_set_port_mtu(mdev, hw_mtu); 2974 if (err) { 2975 mlx5_en_err(ifp, "mlx5_set_port_mtu failed setting %d, err=%d\n", 2976 sw_mtu, err); 2977 return (err); 2978 } 2979 2980 /* Update vport context MTU */ 2981 err = mlx5_set_vport_mtu(mdev, hw_mtu); 2982 if (err) { 2983 mlx5_en_err(ifp, 2984 "Failed updating vport context with MTU size, err=%d\n", 2985 err); 2986 } 2987 2988 ifp->if_mtu = sw_mtu; 2989 2990 err = mlx5_query_vport_mtu(mdev, &hw_mtu); 2991 if (err || !hw_mtu) { 2992 /* fallback to port oper mtu */ 2993 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu); 2994 } 2995 if (err) { 2996 mlx5_en_err(ifp, 2997 "Query port MTU, after setting new MTU value, failed\n"); 2998 return (err); 2999 } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) { 3000 err = -E2BIG, 3001 mlx5_en_err(ifp, 3002 "Port MTU %d is smaller than ifp mtu %d\n", 3003 hw_mtu, sw_mtu); 3004 } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) { 3005 err = -EINVAL; 3006 mlx5_en_err(ifp, 3007 "Port MTU %d is bigger than ifp mtu %d\n", 3008 hw_mtu, sw_mtu); 3009 } 3010 priv->params_ethtool.hw_mtu = hw_mtu; 3011 3012 /* compute MSB */ 3013 while (hw_mtu & (hw_mtu - 1)) 3014 hw_mtu &= (hw_mtu - 1); 3015 priv->params_ethtool.hw_mtu_msb = hw_mtu; 3016 3017 return (err); 3018 } 3019 3020 int 3021 mlx5e_open_locked(struct ifnet *ifp) 3022 { 3023 struct mlx5e_priv *priv = ifp->if_softc; 3024 int err; 3025 u16 set_id; 3026 3027 /* check if already opened */ 3028 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 3029 return (0); 3030 3031 #ifdef RSS 3032 if (rss_getnumbuckets() > priv->params.num_channels) { 3033 mlx5_en_info(ifp, 3034 "NOTE: There are more RSS buckets(%u) than channels(%u) available\n", 3035 rss_getnumbuckets(), priv->params.num_channels); 3036 } 3037 #endif 3038 err = mlx5e_open_tises(priv); 3039 if (err) { 3040 mlx5_en_err(ifp, "mlx5e_open_tises failed, %d\n", err); 3041 return (err); 3042 } 3043 err = mlx5_vport_alloc_q_counter(priv->mdev, 3044 MLX5_INTERFACE_PROTOCOL_ETH, &set_id); 3045 if (err) { 3046 mlx5_en_err(priv->ifp, 3047 "mlx5_vport_alloc_q_counter failed: %d\n", err); 3048 goto err_close_tises; 3049 } 3050 /* store counter set ID */ 3051 priv->counter_set_id = set_id; 3052 3053 err = mlx5e_open_channels(priv); 3054 if (err) { 3055 mlx5_en_err(ifp, 3056 "mlx5e_open_channels failed, %d\n", err); 3057 goto err_dalloc_q_counter; 3058 } 3059 err = mlx5e_open_rqt(priv); 3060 if (err) { 3061 mlx5_en_err(ifp, "mlx5e_open_rqt failed, %d\n", err); 3062 goto err_close_channels; 3063 } 3064 err = mlx5e_open_tirs(priv); 3065 if (err) { 3066 mlx5_en_err(ifp, "mlx5e_open_tir failed, %d\n", err); 3067 goto err_close_rqls; 3068 } 3069 err = mlx5e_open_flow_table(priv); 3070 if (err) { 3071 mlx5_en_err(ifp, 3072 "mlx5e_open_flow_table failed, %d\n", err); 3073 goto err_close_tirs; 3074 } 3075 err = mlx5e_add_all_vlan_rules(priv); 3076 if (err) { 3077 mlx5_en_err(ifp, 3078 "mlx5e_add_all_vlan_rules failed, %d\n", err); 3079 goto err_close_flow_table; 3080 } 3081 set_bit(MLX5E_STATE_OPENED, &priv->state); 3082 3083 mlx5e_update_carrier(priv); 3084 mlx5e_set_rx_mode_core(priv); 3085 3086 return (0); 3087 3088 err_close_flow_table: 3089 mlx5e_close_flow_table(priv); 3090 3091 err_close_tirs: 3092 mlx5e_close_tirs(priv); 3093 3094 err_close_rqls: 3095 mlx5e_close_rqt(priv); 3096 3097 err_close_channels: 3098 mlx5e_close_channels(priv); 3099 3100 err_dalloc_q_counter: 3101 mlx5_vport_dealloc_q_counter(priv->mdev, 3102 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 3103 3104 err_close_tises: 3105 mlx5e_close_tises(priv); 3106 3107 return (err); 3108 } 3109 3110 static void 3111 mlx5e_open(void *arg) 3112 { 3113 struct mlx5e_priv *priv = arg; 3114 3115 PRIV_LOCK(priv); 3116 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP)) 3117 mlx5_en_err(priv->ifp, 3118 "Setting port status to up failed\n"); 3119 3120 mlx5e_open_locked(priv->ifp); 3121 priv->ifp->if_drv_flags |= IFF_DRV_RUNNING; 3122 PRIV_UNLOCK(priv); 3123 } 3124 3125 int 3126 mlx5e_close_locked(struct ifnet *ifp) 3127 { 3128 struct mlx5e_priv *priv = ifp->if_softc; 3129 3130 /* check if already closed */ 3131 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3132 return (0); 3133 3134 clear_bit(MLX5E_STATE_OPENED, &priv->state); 3135 3136 mlx5e_set_rx_mode_core(priv); 3137 mlx5e_del_all_vlan_rules(priv); 3138 if_link_state_change(priv->ifp, LINK_STATE_DOWN); 3139 mlx5e_close_flow_table(priv); 3140 mlx5e_close_tirs(priv); 3141 mlx5e_close_rqt(priv); 3142 mlx5e_close_channels(priv); 3143 mlx5_vport_dealloc_q_counter(priv->mdev, 3144 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 3145 mlx5e_close_tises(priv); 3146 3147 return (0); 3148 } 3149 3150 #if (__FreeBSD_version >= 1100000) 3151 static uint64_t 3152 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt) 3153 { 3154 struct mlx5e_priv *priv = ifp->if_softc; 3155 u64 retval; 3156 3157 /* PRIV_LOCK(priv); XXX not allowed */ 3158 switch (cnt) { 3159 case IFCOUNTER_IPACKETS: 3160 retval = priv->stats.vport.rx_packets; 3161 break; 3162 case IFCOUNTER_IERRORS: 3163 retval = priv->stats.pport.in_range_len_errors + 3164 priv->stats.pport.out_of_range_len + 3165 priv->stats.pport.too_long_errors + 3166 priv->stats.pport.check_seq_err + 3167 priv->stats.pport.alignment_err; 3168 break; 3169 case IFCOUNTER_IQDROPS: 3170 retval = priv->stats.vport.rx_out_of_buffer; 3171 break; 3172 case IFCOUNTER_OPACKETS: 3173 retval = priv->stats.vport.tx_packets; 3174 break; 3175 case IFCOUNTER_OERRORS: 3176 retval = priv->stats.port_stats_debug.out_discards; 3177 break; 3178 case IFCOUNTER_IBYTES: 3179 retval = priv->stats.vport.rx_bytes; 3180 break; 3181 case IFCOUNTER_OBYTES: 3182 retval = priv->stats.vport.tx_bytes; 3183 break; 3184 case IFCOUNTER_IMCASTS: 3185 retval = priv->stats.vport.rx_multicast_packets; 3186 break; 3187 case IFCOUNTER_OMCASTS: 3188 retval = priv->stats.vport.tx_multicast_packets; 3189 break; 3190 case IFCOUNTER_OQDROPS: 3191 retval = priv->stats.vport.tx_queue_dropped; 3192 break; 3193 case IFCOUNTER_COLLISIONS: 3194 retval = priv->stats.pport.collisions; 3195 break; 3196 default: 3197 retval = if_get_counter_default(ifp, cnt); 3198 break; 3199 } 3200 /* PRIV_UNLOCK(priv); XXX not allowed */ 3201 return (retval); 3202 } 3203 #endif 3204 3205 static void 3206 mlx5e_set_rx_mode(struct ifnet *ifp) 3207 { 3208 struct mlx5e_priv *priv = ifp->if_softc; 3209 3210 queue_work(priv->wq, &priv->set_rx_mode_work); 3211 } 3212 3213 static int 3214 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3215 { 3216 struct mlx5e_priv *priv; 3217 struct ifreq *ifr; 3218 struct ifi2creq i2c; 3219 int error = 0; 3220 int mask = 0; 3221 int size_read = 0; 3222 int module_status; 3223 int module_num; 3224 int max_mtu; 3225 uint8_t read_addr; 3226 3227 priv = ifp->if_softc; 3228 3229 /* check if detaching */ 3230 if (priv == NULL || priv->gone != 0) 3231 return (ENXIO); 3232 3233 switch (command) { 3234 case SIOCSIFMTU: 3235 ifr = (struct ifreq *)data; 3236 3237 PRIV_LOCK(priv); 3238 mlx5_query_port_max_mtu(priv->mdev, &max_mtu); 3239 3240 if (ifr->ifr_mtu >= MLX5E_MTU_MIN && 3241 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) { 3242 int was_opened; 3243 3244 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 3245 if (was_opened) 3246 mlx5e_close_locked(ifp); 3247 3248 /* set new MTU */ 3249 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu); 3250 3251 if (was_opened) 3252 mlx5e_open_locked(ifp); 3253 } else { 3254 error = EINVAL; 3255 mlx5_en_err(ifp, 3256 "Invalid MTU value. Min val: %d, Max val: %d\n", 3257 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu)); 3258 } 3259 PRIV_UNLOCK(priv); 3260 break; 3261 case SIOCSIFFLAGS: 3262 if ((ifp->if_flags & IFF_UP) && 3263 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3264 mlx5e_set_rx_mode(ifp); 3265 break; 3266 } 3267 PRIV_LOCK(priv); 3268 if (ifp->if_flags & IFF_UP) { 3269 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3270 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3271 mlx5e_open_locked(ifp); 3272 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3273 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP); 3274 } 3275 } else { 3276 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3277 mlx5_set_port_status(priv->mdev, 3278 MLX5_PORT_DOWN); 3279 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 3280 mlx5e_close_locked(ifp); 3281 mlx5e_update_carrier(priv); 3282 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3283 } 3284 } 3285 PRIV_UNLOCK(priv); 3286 break; 3287 case SIOCADDMULTI: 3288 case SIOCDELMULTI: 3289 mlx5e_set_rx_mode(ifp); 3290 break; 3291 case SIOCSIFMEDIA: 3292 case SIOCGIFMEDIA: 3293 case SIOCGIFXMEDIA: 3294 ifr = (struct ifreq *)data; 3295 error = ifmedia_ioctl(ifp, ifr, &priv->media, command); 3296 break; 3297 case SIOCSIFCAP: 3298 ifr = (struct ifreq *)data; 3299 PRIV_LOCK(priv); 3300 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3301 3302 if (mask & IFCAP_TXCSUM) { 3303 ifp->if_capenable ^= IFCAP_TXCSUM; 3304 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 3305 3306 if (IFCAP_TSO4 & ifp->if_capenable && 3307 !(IFCAP_TXCSUM & ifp->if_capenable)) { 3308 ifp->if_capenable &= ~IFCAP_TSO4; 3309 ifp->if_hwassist &= ~CSUM_IP_TSO; 3310 mlx5_en_err(ifp, 3311 "tso4 disabled due to -txcsum.\n"); 3312 } 3313 } 3314 if (mask & IFCAP_TXCSUM_IPV6) { 3315 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 3316 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 3317 3318 if (IFCAP_TSO6 & ifp->if_capenable && 3319 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 3320 ifp->if_capenable &= ~IFCAP_TSO6; 3321 ifp->if_hwassist &= ~CSUM_IP6_TSO; 3322 mlx5_en_err(ifp, 3323 "tso6 disabled due to -txcsum6.\n"); 3324 } 3325 } 3326 if (mask & IFCAP_NOMAP) 3327 ifp->if_capenable ^= IFCAP_NOMAP; 3328 if (mask & IFCAP_TXTLS4) 3329 ifp->if_capenable ^= IFCAP_TXTLS4; 3330 if (mask & IFCAP_TXTLS6) 3331 ifp->if_capenable ^= IFCAP_TXTLS6; 3332 if (mask & IFCAP_RXCSUM) 3333 ifp->if_capenable ^= IFCAP_RXCSUM; 3334 if (mask & IFCAP_RXCSUM_IPV6) 3335 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 3336 if (mask & IFCAP_TSO4) { 3337 if (!(IFCAP_TSO4 & ifp->if_capenable) && 3338 !(IFCAP_TXCSUM & ifp->if_capenable)) { 3339 mlx5_en_err(ifp, "enable txcsum first.\n"); 3340 error = EAGAIN; 3341 goto out; 3342 } 3343 ifp->if_capenable ^= IFCAP_TSO4; 3344 ifp->if_hwassist ^= CSUM_IP_TSO; 3345 } 3346 if (mask & IFCAP_TSO6) { 3347 if (!(IFCAP_TSO6 & ifp->if_capenable) && 3348 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 3349 mlx5_en_err(ifp, "enable txcsum6 first.\n"); 3350 error = EAGAIN; 3351 goto out; 3352 } 3353 ifp->if_capenable ^= IFCAP_TSO6; 3354 ifp->if_hwassist ^= CSUM_IP6_TSO; 3355 } 3356 if (mask & IFCAP_VLAN_HWFILTER) { 3357 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) 3358 mlx5e_disable_vlan_filter(priv); 3359 else 3360 mlx5e_enable_vlan_filter(priv); 3361 3362 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER; 3363 } 3364 if (mask & IFCAP_VLAN_HWTAGGING) 3365 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3366 if (mask & IFCAP_WOL_MAGIC) 3367 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3368 3369 VLAN_CAPABILITIES(ifp); 3370 /* turn off LRO means also turn of HW LRO - if it's on */ 3371 if (mask & IFCAP_LRO) { 3372 int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 3373 bool need_restart = false; 3374 3375 ifp->if_capenable ^= IFCAP_LRO; 3376 3377 /* figure out if updating HW LRO is needed */ 3378 if (!(ifp->if_capenable & IFCAP_LRO)) { 3379 if (priv->params.hw_lro_en) { 3380 priv->params.hw_lro_en = false; 3381 need_restart = true; 3382 } 3383 } else { 3384 if (priv->params.hw_lro_en == false && 3385 priv->params_ethtool.hw_lro != 0) { 3386 priv->params.hw_lro_en = true; 3387 need_restart = true; 3388 } 3389 } 3390 if (was_opened && need_restart) { 3391 mlx5e_close_locked(ifp); 3392 mlx5e_open_locked(ifp); 3393 } 3394 } 3395 if (mask & IFCAP_HWRXTSTMP) { 3396 ifp->if_capenable ^= IFCAP_HWRXTSTMP; 3397 if (ifp->if_capenable & IFCAP_HWRXTSTMP) { 3398 if (priv->clbr_done == 0) 3399 mlx5e_reset_calibration_callout(priv); 3400 } else { 3401 callout_drain(&priv->tstmp_clbr); 3402 priv->clbr_done = 0; 3403 } 3404 } 3405 out: 3406 PRIV_UNLOCK(priv); 3407 break; 3408 3409 case SIOCGI2C: 3410 ifr = (struct ifreq *)data; 3411 3412 /* 3413 * Copy from the user-space address ifr_data to the 3414 * kernel-space address i2c 3415 */ 3416 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 3417 if (error) 3418 break; 3419 3420 if (i2c.len > sizeof(i2c.data)) { 3421 error = EINVAL; 3422 break; 3423 } 3424 3425 PRIV_LOCK(priv); 3426 /* Get module_num which is required for the query_eeprom */ 3427 error = mlx5_query_module_num(priv->mdev, &module_num); 3428 if (error) { 3429 mlx5_en_err(ifp, 3430 "Query module num failed, eeprom reading is not supported\n"); 3431 error = EINVAL; 3432 goto err_i2c; 3433 } 3434 /* Check if module is present before doing an access */ 3435 module_status = mlx5_query_module_status(priv->mdev, module_num); 3436 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED) { 3437 error = EINVAL; 3438 goto err_i2c; 3439 } 3440 /* 3441 * Currently 0XA0 and 0xA2 are the only addresses permitted. 3442 * The internal conversion is as follows: 3443 */ 3444 if (i2c.dev_addr == 0xA0) 3445 read_addr = MLX5_I2C_ADDR_LOW; 3446 else if (i2c.dev_addr == 0xA2) 3447 read_addr = MLX5_I2C_ADDR_HIGH; 3448 else { 3449 mlx5_en_err(ifp, 3450 "Query eeprom failed, Invalid Address: %X\n", 3451 i2c.dev_addr); 3452 error = EINVAL; 3453 goto err_i2c; 3454 } 3455 error = mlx5_query_eeprom(priv->mdev, 3456 read_addr, MLX5_EEPROM_LOW_PAGE, 3457 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num, 3458 (uint32_t *)i2c.data, &size_read); 3459 if (error) { 3460 mlx5_en_err(ifp, 3461 "Query eeprom failed, eeprom reading is not supported\n"); 3462 error = EINVAL; 3463 goto err_i2c; 3464 } 3465 3466 if (i2c.len > MLX5_EEPROM_MAX_BYTES) { 3467 error = mlx5_query_eeprom(priv->mdev, 3468 read_addr, MLX5_EEPROM_LOW_PAGE, 3469 (uint32_t)(i2c.offset + size_read), 3470 (uint32_t)(i2c.len - size_read), module_num, 3471 (uint32_t *)(i2c.data + size_read), &size_read); 3472 } 3473 if (error) { 3474 mlx5_en_err(ifp, 3475 "Query eeprom failed, eeprom reading is not supported\n"); 3476 error = EINVAL; 3477 goto err_i2c; 3478 } 3479 3480 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 3481 err_i2c: 3482 PRIV_UNLOCK(priv); 3483 break; 3484 3485 default: 3486 error = ether_ioctl(ifp, command, data); 3487 break; 3488 } 3489 return (error); 3490 } 3491 3492 static int 3493 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev) 3494 { 3495 /* 3496 * TODO: uncoment once FW really sets all these bits if 3497 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap || 3498 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap || 3499 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return 3500 * -ENOTSUPP; 3501 */ 3502 3503 /* TODO: add more must-to-have features */ 3504 3505 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) 3506 return (-ENODEV); 3507 3508 return (0); 3509 } 3510 3511 static u16 3512 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev) 3513 { 3514 uint32_t bf_buf_size = (1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U; 3515 3516 bf_buf_size -= sizeof(struct mlx5e_tx_wqe) - 2; 3517 3518 /* verify against driver hardware limit */ 3519 if (bf_buf_size > MLX5E_MAX_TX_INLINE) 3520 bf_buf_size = MLX5E_MAX_TX_INLINE; 3521 3522 return (bf_buf_size); 3523 } 3524 3525 static int 3526 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev, 3527 struct mlx5e_priv *priv, 3528 int num_comp_vectors) 3529 { 3530 int err; 3531 3532 /* 3533 * TODO: Consider link speed for setting "log_sq_size", 3534 * "log_rq_size" and "cq_moderation_xxx": 3535 */ 3536 priv->params.log_sq_size = 3537 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; 3538 priv->params.log_rq_size = 3539 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; 3540 priv->params.rx_cq_moderation_usec = 3541 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 3542 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE : 3543 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; 3544 priv->params.rx_cq_moderation_mode = 3545 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0; 3546 priv->params.rx_cq_moderation_pkts = 3547 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; 3548 priv->params.tx_cq_moderation_usec = 3549 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; 3550 priv->params.tx_cq_moderation_pkts = 3551 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; 3552 priv->params.min_rx_wqes = 3553 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES; 3554 priv->params.rx_hash_log_tbl_sz = 3555 (order_base_2(num_comp_vectors) > 3556 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ? 3557 order_base_2(num_comp_vectors) : 3558 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ; 3559 priv->params.num_tc = 1; 3560 priv->params.default_vlan_prio = 0; 3561 priv->counter_set_id = -1; 3562 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev); 3563 3564 err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode); 3565 if (err) 3566 return (err); 3567 3568 /* 3569 * hw lro is currently defaulted to off. when it won't anymore we 3570 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)" 3571 */ 3572 priv->params.hw_lro_en = false; 3573 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; 3574 3575 /* 3576 * CQE zipping is currently defaulted to off. when it won't 3577 * anymore we will consider the HW capability: 3578 * "!!MLX5_CAP_GEN(mdev, cqe_compression)" 3579 */ 3580 priv->params.cqe_zipping_en = false; 3581 3582 priv->mdev = mdev; 3583 priv->params.num_channels = num_comp_vectors; 3584 priv->params.channels_rsss = 1; 3585 priv->order_base_2_num_channels = order_base_2(num_comp_vectors); 3586 priv->queue_mapping_channel_mask = 3587 roundup_pow_of_two(num_comp_vectors) - 1; 3588 priv->num_tc = priv->params.num_tc; 3589 priv->default_vlan_prio = priv->params.default_vlan_prio; 3590 3591 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work); 3592 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); 3593 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); 3594 3595 return (0); 3596 } 3597 3598 static int 3599 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn, 3600 struct mlx5_core_mr *mkey) 3601 { 3602 struct ifnet *ifp = priv->ifp; 3603 struct mlx5_core_dev *mdev = priv->mdev; 3604 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 3605 void *mkc; 3606 u32 *in; 3607 int err; 3608 3609 in = mlx5_vzalloc(inlen); 3610 if (in == NULL) { 3611 mlx5_en_err(ifp, "failed to allocate inbox\n"); 3612 return (-ENOMEM); 3613 } 3614 3615 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 3616 MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA); 3617 MLX5_SET(mkc, mkc, umr_en, 1); /* used by HW TLS */ 3618 MLX5_SET(mkc, mkc, lw, 1); 3619 MLX5_SET(mkc, mkc, lr, 1); 3620 3621 MLX5_SET(mkc, mkc, pd, pdn); 3622 MLX5_SET(mkc, mkc, length64, 1); 3623 MLX5_SET(mkc, mkc, qpn, 0xffffff); 3624 3625 err = mlx5_core_create_mkey(mdev, mkey, in, inlen); 3626 if (err) 3627 mlx5_en_err(ifp, "mlx5_core_create_mkey failed, %d\n", 3628 err); 3629 3630 kvfree(in); 3631 return (err); 3632 } 3633 3634 static const char *mlx5e_vport_stats_desc[] = { 3635 MLX5E_VPORT_STATS(MLX5E_STATS_DESC) 3636 }; 3637 3638 static const char *mlx5e_pport_stats_desc[] = { 3639 MLX5E_PPORT_STATS(MLX5E_STATS_DESC) 3640 }; 3641 3642 static void 3643 mlx5e_priv_static_init(struct mlx5e_priv *priv, const uint32_t channels) 3644 { 3645 uint32_t x; 3646 3647 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF); 3648 sx_init(&priv->state_lock, "mlx5state"); 3649 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0); 3650 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock); 3651 for (x = 0; x != channels; x++) 3652 mlx5e_chan_static_init(priv, &priv->channel[x], x); 3653 } 3654 3655 static void 3656 mlx5e_priv_static_destroy(struct mlx5e_priv *priv, const uint32_t channels) 3657 { 3658 uint32_t x; 3659 3660 for (x = 0; x != channels; x++) 3661 mlx5e_chan_static_destroy(&priv->channel[x]); 3662 callout_drain(&priv->watchdog); 3663 mtx_destroy(&priv->async_events_mtx); 3664 sx_destroy(&priv->state_lock); 3665 } 3666 3667 static int 3668 sysctl_firmware(SYSCTL_HANDLER_ARGS) 3669 { 3670 /* 3671 * %d.%d%.d the string format. 3672 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536. 3673 * We need at most 5 chars to store that. 3674 * It also has: two "." and NULL at the end, which means we need 18 3675 * (5*3 + 3) chars at most. 3676 */ 3677 char fw[18]; 3678 struct mlx5e_priv *priv = arg1; 3679 int error; 3680 3681 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev), 3682 fw_rev_sub(priv->mdev)); 3683 error = sysctl_handle_string(oidp, fw, sizeof(fw), req); 3684 return (error); 3685 } 3686 3687 static void 3688 mlx5e_disable_tx_dma(struct mlx5e_channel *ch) 3689 { 3690 int i; 3691 3692 for (i = 0; i < ch->priv->num_tc; i++) 3693 mlx5e_drain_sq(&ch->sq[i]); 3694 } 3695 3696 static void 3697 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq) 3698 { 3699 3700 sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP); 3701 sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8); 3702 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0); 3703 sq->doorbell.d64 = 0; 3704 } 3705 3706 void 3707 mlx5e_resume_sq(struct mlx5e_sq *sq) 3708 { 3709 int err; 3710 3711 /* check if already enabled */ 3712 if (READ_ONCE(sq->running) != 0) 3713 return; 3714 3715 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR, 3716 MLX5_SQC_STATE_RST); 3717 if (err != 0) { 3718 mlx5_en_err(sq->ifp, 3719 "mlx5e_modify_sq() from ERR to RST failed: %d\n", err); 3720 } 3721 3722 sq->cc = 0; 3723 sq->pc = 0; 3724 3725 /* reset doorbell prior to moving from RST to RDY */ 3726 mlx5e_reset_sq_doorbell_record(sq); 3727 3728 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, 3729 MLX5_SQC_STATE_RDY); 3730 if (err != 0) { 3731 mlx5_en_err(sq->ifp, 3732 "mlx5e_modify_sq() from RST to RDY failed: %d\n", err); 3733 } 3734 3735 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL; 3736 WRITE_ONCE(sq->running, 1); 3737 } 3738 3739 static void 3740 mlx5e_enable_tx_dma(struct mlx5e_channel *ch) 3741 { 3742 int i; 3743 3744 for (i = 0; i < ch->priv->num_tc; i++) 3745 mlx5e_resume_sq(&ch->sq[i]); 3746 } 3747 3748 static void 3749 mlx5e_disable_rx_dma(struct mlx5e_channel *ch) 3750 { 3751 struct mlx5e_rq *rq = &ch->rq; 3752 struct epoch_tracker et; 3753 int err; 3754 3755 mtx_lock(&rq->mtx); 3756 rq->enabled = 0; 3757 callout_stop(&rq->watchdog); 3758 mtx_unlock(&rq->mtx); 3759 3760 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 3761 if (err != 0) { 3762 mlx5_en_err(rq->ifp, 3763 "mlx5e_modify_rq() from RDY to RST failed: %d\n", err); 3764 } 3765 3766 while (!mlx5_wq_ll_is_empty(&rq->wq)) { 3767 msleep(1); 3768 NET_EPOCH_ENTER(et); 3769 rq->cq.mcq.comp(&rq->cq.mcq); 3770 NET_EPOCH_EXIT(et); 3771 } 3772 3773 /* 3774 * Transitioning into RST state will allow the FW to track less ERR state queues, 3775 * thus reducing the recv queue flushing time 3776 */ 3777 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST); 3778 if (err != 0) { 3779 mlx5_en_err(rq->ifp, 3780 "mlx5e_modify_rq() from ERR to RST failed: %d\n", err); 3781 } 3782 } 3783 3784 static void 3785 mlx5e_enable_rx_dma(struct mlx5e_channel *ch) 3786 { 3787 struct mlx5e_rq *rq = &ch->rq; 3788 struct epoch_tracker et; 3789 int err; 3790 3791 rq->wq.wqe_ctr = 0; 3792 mlx5_wq_ll_update_db_record(&rq->wq); 3793 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 3794 if (err != 0) { 3795 mlx5_en_err(rq->ifp, 3796 "mlx5e_modify_rq() from RST to RDY failed: %d\n", err); 3797 } 3798 3799 rq->enabled = 1; 3800 3801 NET_EPOCH_ENTER(et); 3802 rq->cq.mcq.comp(&rq->cq.mcq); 3803 NET_EPOCH_EXIT(et); 3804 } 3805 3806 void 3807 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value) 3808 { 3809 int i; 3810 3811 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3812 return; 3813 3814 for (i = 0; i < priv->params.num_channels; i++) { 3815 if (value) 3816 mlx5e_disable_tx_dma(&priv->channel[i]); 3817 else 3818 mlx5e_enable_tx_dma(&priv->channel[i]); 3819 } 3820 } 3821 3822 void 3823 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value) 3824 { 3825 int i; 3826 3827 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3828 return; 3829 3830 for (i = 0; i < priv->params.num_channels; i++) { 3831 if (value) 3832 mlx5e_disable_rx_dma(&priv->channel[i]); 3833 else 3834 mlx5e_enable_rx_dma(&priv->channel[i]); 3835 } 3836 } 3837 3838 static void 3839 mlx5e_add_hw_stats(struct mlx5e_priv *priv) 3840 { 3841 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 3842 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0, 3843 sysctl_firmware, "A", "HCA firmware version"); 3844 3845 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 3846 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0, 3847 "Board ID"); 3848 } 3849 3850 static int 3851 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS) 3852 { 3853 struct mlx5e_priv *priv = arg1; 3854 uint8_t temp[MLX5E_MAX_PRIORITY]; 3855 uint32_t tx_pfc; 3856 int err; 3857 int i; 3858 3859 PRIV_LOCK(priv); 3860 3861 tx_pfc = priv->params.tx_priority_flow_control; 3862 3863 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) 3864 temp[i] = (tx_pfc >> i) & 1; 3865 3866 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY); 3867 if (err || !req->newptr) 3868 goto done; 3869 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY); 3870 if (err) 3871 goto done; 3872 3873 priv->params.tx_priority_flow_control = 0; 3874 3875 /* range check input value */ 3876 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) { 3877 if (temp[i] > 1) { 3878 err = ERANGE; 3879 goto done; 3880 } 3881 priv->params.tx_priority_flow_control |= (temp[i] << i); 3882 } 3883 3884 /* check if update is required */ 3885 if (tx_pfc != priv->params.tx_priority_flow_control) 3886 err = -mlx5e_set_port_pfc(priv); 3887 done: 3888 if (err != 0) 3889 priv->params.tx_priority_flow_control= tx_pfc; 3890 PRIV_UNLOCK(priv); 3891 3892 return (err); 3893 } 3894 3895 static int 3896 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS) 3897 { 3898 struct mlx5e_priv *priv = arg1; 3899 uint8_t temp[MLX5E_MAX_PRIORITY]; 3900 uint32_t rx_pfc; 3901 int err; 3902 int i; 3903 3904 PRIV_LOCK(priv); 3905 3906 rx_pfc = priv->params.rx_priority_flow_control; 3907 3908 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) 3909 temp[i] = (rx_pfc >> i) & 1; 3910 3911 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY); 3912 if (err || !req->newptr) 3913 goto done; 3914 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY); 3915 if (err) 3916 goto done; 3917 3918 priv->params.rx_priority_flow_control = 0; 3919 3920 /* range check input value */ 3921 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) { 3922 if (temp[i] > 1) { 3923 err = ERANGE; 3924 goto done; 3925 } 3926 priv->params.rx_priority_flow_control |= (temp[i] << i); 3927 } 3928 3929 /* check if update is required */ 3930 if (rx_pfc != priv->params.rx_priority_flow_control) { 3931 err = -mlx5e_set_port_pfc(priv); 3932 if (err == 0 && priv->sw_is_port_buf_owner) 3933 err = mlx5e_update_buf_lossy(priv); 3934 } 3935 done: 3936 if (err != 0) 3937 priv->params.rx_priority_flow_control= rx_pfc; 3938 PRIV_UNLOCK(priv); 3939 3940 return (err); 3941 } 3942 3943 static void 3944 mlx5e_setup_pauseframes(struct mlx5e_priv *priv) 3945 { 3946 #if (__FreeBSD_version < 1100000) 3947 char path[96]; 3948 #endif 3949 int error; 3950 3951 /* enable pauseframes by default */ 3952 priv->params.tx_pauseframe_control = 1; 3953 priv->params.rx_pauseframe_control = 1; 3954 3955 /* disable ports flow control, PFC, by default */ 3956 priv->params.tx_priority_flow_control = 0; 3957 priv->params.rx_priority_flow_control = 0; 3958 3959 #if (__FreeBSD_version < 1100000) 3960 /* compute path for sysctl */ 3961 snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control", 3962 device_get_unit(priv->mdev->pdev->dev.bsddev)); 3963 3964 /* try to fetch tunable, if any */ 3965 TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control); 3966 3967 /* compute path for sysctl */ 3968 snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control", 3969 device_get_unit(priv->mdev->pdev->dev.bsddev)); 3970 3971 /* try to fetch tunable, if any */ 3972 TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control); 3973 #endif 3974 3975 /* register pauseframe SYSCTLs */ 3976 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 3977 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN, 3978 &priv->params.tx_pauseframe_control, 0, 3979 "Set to enable TX pause frames. Clear to disable."); 3980 3981 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 3982 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN, 3983 &priv->params.rx_pauseframe_control, 0, 3984 "Set to enable RX pause frames. Clear to disable."); 3985 3986 /* register priority flow control, PFC, SYSCTLs */ 3987 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 3988 OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN | 3989 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU", 3990 "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable."); 3991 3992 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 3993 OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN | 3994 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU", 3995 "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable."); 3996 3997 PRIV_LOCK(priv); 3998 3999 /* range check */ 4000 priv->params.tx_pauseframe_control = 4001 priv->params.tx_pauseframe_control ? 1 : 0; 4002 priv->params.rx_pauseframe_control = 4003 priv->params.rx_pauseframe_control ? 1 : 0; 4004 4005 /* update firmware */ 4006 error = mlx5e_set_port_pause_and_pfc(priv); 4007 if (error == -EINVAL) { 4008 mlx5_en_err(priv->ifp, 4009 "Global pauseframes must be disabled before enabling PFC.\n"); 4010 priv->params.rx_priority_flow_control = 0; 4011 priv->params.tx_priority_flow_control = 0; 4012 4013 /* update firmware */ 4014 (void) mlx5e_set_port_pause_and_pfc(priv); 4015 } 4016 PRIV_UNLOCK(priv); 4017 } 4018 4019 int 4020 mlx5e_ul_snd_tag_alloc(struct ifnet *ifp, 4021 union if_snd_tag_alloc_params *params, 4022 struct m_snd_tag **ppmt) 4023 { 4024 struct mlx5e_priv *priv; 4025 struct mlx5e_channel *pch; 4026 4027 priv = ifp->if_softc; 4028 4029 if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) { 4030 return (EOPNOTSUPP); 4031 } else { 4032 /* keep this code synced with mlx5e_select_queue() */ 4033 u32 ch = priv->params.num_channels; 4034 #ifdef RSS 4035 u32 temp; 4036 4037 if (rss_hash2bucket(params->hdr.flowid, 4038 params->hdr.flowtype, &temp) == 0) 4039 ch = temp % ch; 4040 else 4041 #endif 4042 ch = (params->hdr.flowid % 128) % ch; 4043 4044 /* 4045 * NOTE: The channels array is only freed at detach 4046 * and it safe to return a pointer to the send tag 4047 * inside the channels structure as long as we 4048 * reference the priv. 4049 */ 4050 pch = priv->channel + ch; 4051 4052 /* check if send queue is not running */ 4053 if (unlikely(pch->sq[0].running == 0)) 4054 return (ENXIO); 4055 m_snd_tag_ref(&pch->tag.m_snd_tag); 4056 *ppmt = &pch->tag.m_snd_tag; 4057 return (0); 4058 } 4059 } 4060 4061 int 4062 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params) 4063 { 4064 struct mlx5e_channel *pch = 4065 container_of(pmt, struct mlx5e_channel, tag.m_snd_tag); 4066 4067 params->unlimited.max_rate = -1ULL; 4068 params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]); 4069 return (0); 4070 } 4071 4072 void 4073 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt) 4074 { 4075 struct mlx5e_channel *pch = 4076 container_of(pmt, struct mlx5e_channel, tag.m_snd_tag); 4077 4078 complete(&pch->completion); 4079 } 4080 4081 static int 4082 mlx5e_snd_tag_alloc(struct ifnet *ifp, 4083 union if_snd_tag_alloc_params *params, 4084 struct m_snd_tag **ppmt) 4085 { 4086 4087 switch (params->hdr.type) { 4088 #ifdef RATELIMIT 4089 case IF_SND_TAG_TYPE_RATE_LIMIT: 4090 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt)); 4091 #if defined(KERN_TLS) && defined(IF_SND_TAG_TYPE_TLS_RATE_LIMIT) 4092 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT: 4093 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt)); 4094 #endif 4095 #endif 4096 case IF_SND_TAG_TYPE_UNLIMITED: 4097 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt)); 4098 #ifdef KERN_TLS 4099 case IF_SND_TAG_TYPE_TLS: 4100 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt)); 4101 #endif 4102 default: 4103 return (EOPNOTSUPP); 4104 } 4105 } 4106 4107 static int 4108 mlx5e_snd_tag_modify(struct m_snd_tag *pmt, union if_snd_tag_modify_params *params) 4109 { 4110 struct mlx5e_snd_tag *tag = 4111 container_of(pmt, struct mlx5e_snd_tag, m_snd_tag); 4112 4113 switch (tag->type) { 4114 #ifdef RATELIMIT 4115 case IF_SND_TAG_TYPE_RATE_LIMIT: 4116 return (mlx5e_rl_snd_tag_modify(pmt, params)); 4117 #if defined(KERN_TLS) && defined(IF_SND_TAG_TYPE_TLS_RATE_LIMIT) 4118 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT: 4119 return (mlx5e_tls_snd_tag_modify(pmt, params)); 4120 #endif 4121 #endif 4122 case IF_SND_TAG_TYPE_UNLIMITED: 4123 #ifdef KERN_TLS 4124 case IF_SND_TAG_TYPE_TLS: 4125 #endif 4126 default: 4127 return (EOPNOTSUPP); 4128 } 4129 } 4130 4131 static int 4132 mlx5e_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params) 4133 { 4134 struct mlx5e_snd_tag *tag = 4135 container_of(pmt, struct mlx5e_snd_tag, m_snd_tag); 4136 4137 switch (tag->type) { 4138 #ifdef RATELIMIT 4139 case IF_SND_TAG_TYPE_RATE_LIMIT: 4140 return (mlx5e_rl_snd_tag_query(pmt, params)); 4141 #if defined(KERN_TLS) && defined(IF_SND_TAG_TYPE_TLS_RATE_LIMIT) 4142 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT: 4143 return (mlx5e_tls_snd_tag_query(pmt, params)); 4144 #endif 4145 #endif 4146 case IF_SND_TAG_TYPE_UNLIMITED: 4147 return (mlx5e_ul_snd_tag_query(pmt, params)); 4148 #ifdef KERN_TLS 4149 case IF_SND_TAG_TYPE_TLS: 4150 return (mlx5e_tls_snd_tag_query(pmt, params)); 4151 #endif 4152 default: 4153 return (EOPNOTSUPP); 4154 } 4155 } 4156 4157 #ifdef RATELIMIT 4158 #define NUM_HDWR_RATES_MLX 13 4159 static const uint64_t adapter_rates_mlx[NUM_HDWR_RATES_MLX] = { 4160 135375, /* 1,083,000 */ 4161 180500, /* 1,444,000 */ 4162 270750, /* 2,166,000 */ 4163 361000, /* 2,888,000 */ 4164 541500, /* 4,332,000 */ 4165 721875, /* 5,775,000 */ 4166 1082875, /* 8,663,000 */ 4167 1443875, /* 11,551,000 */ 4168 2165750, /* 17,326,000 */ 4169 2887750, /* 23,102,000 */ 4170 4331625, /* 34,653,000 */ 4171 5775500, /* 46,204,000 */ 4172 8663125 /* 69,305,000 */ 4173 }; 4174 4175 static void 4176 mlx5e_ratelimit_query(struct ifnet *ifp __unused, struct if_ratelimit_query_results *q) 4177 { 4178 /* 4179 * This function needs updating by the driver maintainer! 4180 * For the MLX card there are currently (ConectX-4?) 13 4181 * pre-set rates and others i.e. ConnectX-5, 6, 7?? 4182 * 4183 * This will change based on later adapters 4184 * and this code should be updated to look at ifp 4185 * and figure out the specific adapter type 4186 * settings i.e. how many rates as well 4187 * as if they are fixed (as is shown here) or 4188 * if they are dynamic (example chelsio t4). Also if there 4189 * is a maximum number of flows that the adapter 4190 * can handle that too needs to be updated in 4191 * the max_flows field. 4192 */ 4193 q->rate_table = adapter_rates_mlx; 4194 q->flags = RT_IS_FIXED_TABLE; 4195 q->max_flows = 0; /* mlx has no limit */ 4196 q->number_of_rates = NUM_HDWR_RATES_MLX; 4197 q->min_segment_burst = 1; 4198 } 4199 #endif 4200 4201 static void 4202 mlx5e_snd_tag_free(struct m_snd_tag *pmt) 4203 { 4204 struct mlx5e_snd_tag *tag = 4205 container_of(pmt, struct mlx5e_snd_tag, m_snd_tag); 4206 4207 switch (tag->type) { 4208 #ifdef RATELIMIT 4209 case IF_SND_TAG_TYPE_RATE_LIMIT: 4210 mlx5e_rl_snd_tag_free(pmt); 4211 break; 4212 #if defined(KERN_TLS) && defined(IF_SND_TAG_TYPE_TLS_RATE_LIMIT) 4213 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT: 4214 mlx5e_tls_snd_tag_free(pmt); 4215 break; 4216 #endif 4217 #endif 4218 case IF_SND_TAG_TYPE_UNLIMITED: 4219 mlx5e_ul_snd_tag_free(pmt); 4220 break; 4221 #ifdef KERN_TLS 4222 case IF_SND_TAG_TYPE_TLS: 4223 mlx5e_tls_snd_tag_free(pmt); 4224 break; 4225 #endif 4226 default: 4227 break; 4228 } 4229 } 4230 4231 static void * 4232 mlx5e_create_ifp(struct mlx5_core_dev *mdev) 4233 { 4234 struct ifnet *ifp; 4235 struct mlx5e_priv *priv; 4236 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4); 4237 u8 connector_type; 4238 struct sysctl_oid_list *child; 4239 int ncv = mdev->priv.eq_table.num_comp_vectors; 4240 char unit[16]; 4241 struct pfil_head_args pa; 4242 int err; 4243 int i,j; 4244 u32 eth_proto_cap; 4245 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 4246 bool ext = 0; 4247 u32 speeds_num; 4248 struct media media_entry = {}; 4249 4250 if (mlx5e_check_required_hca_cap(mdev)) { 4251 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n"); 4252 return (NULL); 4253 } 4254 /* 4255 * Try to allocate the priv and make room for worst-case 4256 * number of channel structures: 4257 */ 4258 priv = malloc(sizeof(*priv) + 4259 (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors), 4260 M_MLX5EN, M_WAITOK | M_ZERO); 4261 4262 ifp = priv->ifp = if_alloc_dev(IFT_ETHER, mdev->pdev->dev.bsddev); 4263 if (ifp == NULL) { 4264 mlx5_core_err(mdev, "if_alloc() failed\n"); 4265 goto err_free_priv; 4266 } 4267 /* setup all static fields */ 4268 mlx5e_priv_static_init(priv, mdev->priv.eq_table.num_comp_vectors); 4269 4270 ifp->if_softc = priv; 4271 if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev)); 4272 ifp->if_mtu = ETHERMTU; 4273 ifp->if_init = mlx5e_open; 4274 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 4275 ifp->if_ioctl = mlx5e_ioctl; 4276 ifp->if_transmit = mlx5e_xmit; 4277 ifp->if_qflush = if_qflush; 4278 #if (__FreeBSD_version >= 1100000) 4279 ifp->if_get_counter = mlx5e_get_counter; 4280 #endif 4281 ifp->if_snd.ifq_maxlen = ifqmaxlen; 4282 /* 4283 * Set driver features 4284 */ 4285 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6; 4286 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 4287 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER; 4288 ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU; 4289 ifp->if_capabilities |= IFCAP_LRO; 4290 ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO; 4291 ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP; 4292 ifp->if_capabilities |= IFCAP_NOMAP; 4293 ifp->if_capabilities |= IFCAP_TXTLS4 | IFCAP_TXTLS6; 4294 ifp->if_capabilities |= IFCAP_TXRTLMT; 4295 ifp->if_snd_tag_alloc = mlx5e_snd_tag_alloc; 4296 ifp->if_snd_tag_free = mlx5e_snd_tag_free; 4297 ifp->if_snd_tag_modify = mlx5e_snd_tag_modify; 4298 ifp->if_snd_tag_query = mlx5e_snd_tag_query; 4299 #ifdef RATELIMIT 4300 ifp->if_ratelimit_query = mlx5e_ratelimit_query; 4301 #endif 4302 /* set TSO limits so that we don't have to drop TX packets */ 4303 ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 4304 ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */; 4305 ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE; 4306 4307 ifp->if_capenable = ifp->if_capabilities; 4308 ifp->if_hwassist = 0; 4309 if (ifp->if_capenable & IFCAP_TSO) 4310 ifp->if_hwassist |= CSUM_TSO; 4311 if (ifp->if_capenable & IFCAP_TXCSUM) 4312 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP); 4313 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6) 4314 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 4315 4316 /* ifnet sysctl tree */ 4317 sysctl_ctx_init(&priv->sysctl_ctx); 4318 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev), 4319 OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name"); 4320 if (priv->sysctl_ifnet == NULL) { 4321 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4322 goto err_free_sysctl; 4323 } 4324 snprintf(unit, sizeof(unit), "%d", ifp->if_dunit); 4325 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4326 OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit"); 4327 if (priv->sysctl_ifnet == NULL) { 4328 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4329 goto err_free_sysctl; 4330 } 4331 4332 /* HW sysctl tree */ 4333 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev)); 4334 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child, 4335 OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw"); 4336 if (priv->sysctl_hw == NULL) { 4337 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4338 goto err_free_sysctl; 4339 } 4340 4341 err = mlx5e_build_ifp_priv(mdev, priv, ncv); 4342 if (err) { 4343 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err); 4344 goto err_free_sysctl; 4345 } 4346 4347 /* reuse mlx5core's watchdog workqueue */ 4348 priv->wq = mdev->priv.health.wq_watchdog; 4349 4350 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar); 4351 if (err) { 4352 mlx5_en_err(ifp, "mlx5_alloc_map_uar failed, %d\n", err); 4353 goto err_free_wq; 4354 } 4355 err = mlx5_core_alloc_pd(mdev, &priv->pdn); 4356 if (err) { 4357 mlx5_en_err(ifp, "mlx5_core_alloc_pd failed, %d\n", err); 4358 goto err_unmap_free_uar; 4359 } 4360 err = mlx5_alloc_transport_domain(mdev, &priv->tdn); 4361 if (err) { 4362 mlx5_en_err(ifp, 4363 "mlx5_alloc_transport_domain failed, %d\n", err); 4364 goto err_dealloc_pd; 4365 } 4366 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr); 4367 if (err) { 4368 mlx5_en_err(ifp, "mlx5e_create_mkey failed, %d\n", err); 4369 goto err_dealloc_transport_domain; 4370 } 4371 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr); 4372 4373 /* check if we should generate a random MAC address */ 4374 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 && 4375 is_zero_ether_addr(dev_addr)) { 4376 random_ether_addr(dev_addr); 4377 mlx5_en_err(ifp, "Assigned random MAC address\n"); 4378 } 4379 4380 err = mlx5e_rl_init(priv); 4381 if (err) { 4382 mlx5_en_err(ifp, "mlx5e_rl_init failed, %d\n", err); 4383 goto err_create_mkey; 4384 } 4385 4386 err = mlx5e_tls_init(priv); 4387 if (err) { 4388 if_printf(ifp, "%s: mlx5e_tls_init failed\n", __func__); 4389 goto err_rl_init; 4390 } 4391 4392 /* set default MTU */ 4393 mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu); 4394 4395 /* Set default media status */ 4396 priv->media_status_last = IFM_AVALID; 4397 priv->media_active_last = IFM_ETHER | IFM_AUTO | 4398 IFM_ETH_RXPAUSE | IFM_FDX; 4399 4400 /* setup default pauseframes configuration */ 4401 mlx5e_setup_pauseframes(priv); 4402 4403 /* Setup supported medias */ 4404 //TODO: If we failed to query ptys is it ok to proceed?? 4405 if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) { 4406 ext = MLX5_CAP_PCAM_FEATURE(mdev, 4407 ptys_extended_ethernet); 4408 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 4409 eth_proto_capability); 4410 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type)) 4411 connector_type = MLX5_GET(ptys_reg, out, 4412 connector_type); 4413 } else { 4414 eth_proto_cap = 0; 4415 mlx5_en_err(ifp, "Query port media capability failed, %d\n", err); 4416 } 4417 4418 ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK, 4419 mlx5e_media_change, mlx5e_media_status); 4420 4421 speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER : MLX5E_LINK_SPEEDS_NUMBER; 4422 for (i = 0; i != speeds_num; i++) { 4423 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) { 4424 media_entry = ext ? mlx5e_ext_mode_table[i][j] : 4425 mlx5e_mode_table[i][j]; 4426 if (media_entry.baudrate == 0) 4427 continue; 4428 if (MLX5E_PROT_MASK(i) & eth_proto_cap) { 4429 ifmedia_add(&priv->media, 4430 media_entry.subtype | 4431 IFM_ETHER, 0, NULL); 4432 ifmedia_add(&priv->media, 4433 media_entry.subtype | 4434 IFM_ETHER | IFM_FDX | 4435 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 4436 } 4437 } 4438 } 4439 4440 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL); 4441 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX | 4442 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 4443 4444 /* Set autoselect by default */ 4445 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX | 4446 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE); 4447 ether_ifattach(ifp, dev_addr); 4448 4449 /* Register for VLAN events */ 4450 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config, 4451 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST); 4452 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig, 4453 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST); 4454 4455 /* Link is down by default */ 4456 if_link_state_change(ifp, LINK_STATE_DOWN); 4457 4458 mlx5e_enable_async_events(priv); 4459 4460 mlx5e_add_hw_stats(priv); 4461 4462 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4463 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM, 4464 priv->stats.vport.arg); 4465 4466 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4467 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM, 4468 priv->stats.pport.arg); 4469 4470 mlx5e_create_ethtool(priv); 4471 4472 mtx_lock(&priv->async_events_mtx); 4473 mlx5e_update_stats(priv); 4474 mtx_unlock(&priv->async_events_mtx); 4475 4476 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4477 OID_AUTO, "rx_clbr_done", CTLFLAG_RD, 4478 &priv->clbr_done, 0, 4479 "RX timestamps calibration state"); 4480 callout_init(&priv->tstmp_clbr, CALLOUT_DIRECT); 4481 mlx5e_reset_calibration_callout(priv); 4482 4483 pa.pa_version = PFIL_VERSION; 4484 pa.pa_flags = PFIL_IN; 4485 pa.pa_type = PFIL_TYPE_ETHERNET; 4486 pa.pa_headname = ifp->if_xname; 4487 priv->pfil = pfil_head_register(&pa); 4488 4489 return (priv); 4490 4491 err_rl_init: 4492 mlx5e_rl_cleanup(priv); 4493 4494 err_create_mkey: 4495 mlx5_core_destroy_mkey(priv->mdev, &priv->mr); 4496 4497 err_dealloc_transport_domain: 4498 mlx5_dealloc_transport_domain(mdev, priv->tdn); 4499 4500 err_dealloc_pd: 4501 mlx5_core_dealloc_pd(mdev, priv->pdn); 4502 4503 err_unmap_free_uar: 4504 mlx5_unmap_free_uar(mdev, &priv->cq_uar); 4505 4506 err_free_wq: 4507 flush_workqueue(priv->wq); 4508 4509 err_free_sysctl: 4510 sysctl_ctx_free(&priv->sysctl_ctx); 4511 if (priv->sysctl_debug) 4512 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx); 4513 mlx5e_priv_static_destroy(priv, mdev->priv.eq_table.num_comp_vectors); 4514 if_free(ifp); 4515 4516 err_free_priv: 4517 free(priv, M_MLX5EN); 4518 return (NULL); 4519 } 4520 4521 static void 4522 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv) 4523 { 4524 struct mlx5e_priv *priv = vpriv; 4525 struct ifnet *ifp = priv->ifp; 4526 4527 /* don't allow more IOCTLs */ 4528 priv->gone = 1; 4529 4530 /* XXX wait a bit to allow IOCTL handlers to complete */ 4531 pause("W", hz); 4532 4533 #ifdef RATELIMIT 4534 /* 4535 * The kernel can have reference(s) via the m_snd_tag's into 4536 * the ratelimit channels, and these must go away before 4537 * detaching: 4538 */ 4539 while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) { 4540 mlx5_en_err(priv->ifp, 4541 "Waiting for all ratelimit connections to terminate\n"); 4542 pause("W", hz); 4543 } 4544 #endif 4545 /* wait for all unlimited send tags to complete */ 4546 mlx5e_priv_wait_for_completion(priv, mdev->priv.eq_table.num_comp_vectors); 4547 4548 /* stop watchdog timer */ 4549 callout_drain(&priv->watchdog); 4550 4551 callout_drain(&priv->tstmp_clbr); 4552 4553 if (priv->vlan_attach != NULL) 4554 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach); 4555 if (priv->vlan_detach != NULL) 4556 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach); 4557 4558 /* make sure device gets closed */ 4559 PRIV_LOCK(priv); 4560 mlx5e_close_locked(ifp); 4561 PRIV_UNLOCK(priv); 4562 4563 /* deregister pfil */ 4564 if (priv->pfil != NULL) { 4565 pfil_head_unregister(priv->pfil); 4566 priv->pfil = NULL; 4567 } 4568 4569 /* unregister device */ 4570 ifmedia_removeall(&priv->media); 4571 ether_ifdetach(ifp); 4572 4573 mlx5e_tls_cleanup(priv); 4574 mlx5e_rl_cleanup(priv); 4575 4576 /* destroy all remaining sysctl nodes */ 4577 sysctl_ctx_free(&priv->stats.vport.ctx); 4578 sysctl_ctx_free(&priv->stats.pport.ctx); 4579 if (priv->sysctl_debug) 4580 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx); 4581 sysctl_ctx_free(&priv->sysctl_ctx); 4582 4583 mlx5_core_destroy_mkey(priv->mdev, &priv->mr); 4584 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn); 4585 mlx5_core_dealloc_pd(priv->mdev, priv->pdn); 4586 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar); 4587 mlx5e_disable_async_events(priv); 4588 flush_workqueue(priv->wq); 4589 mlx5e_priv_static_destroy(priv, mdev->priv.eq_table.num_comp_vectors); 4590 if_free(ifp); 4591 free(priv, M_MLX5EN); 4592 } 4593 4594 static void * 4595 mlx5e_get_ifp(void *vpriv) 4596 { 4597 struct mlx5e_priv *priv = vpriv; 4598 4599 return (priv->ifp); 4600 } 4601 4602 static struct mlx5_interface mlx5e_interface = { 4603 .add = mlx5e_create_ifp, 4604 .remove = mlx5e_destroy_ifp, 4605 .event = mlx5e_async_event, 4606 .protocol = MLX5_INTERFACE_PROTOCOL_ETH, 4607 .get_dev = mlx5e_get_ifp, 4608 }; 4609 4610 void 4611 mlx5e_init(void) 4612 { 4613 mlx5_register_interface(&mlx5e_interface); 4614 } 4615 4616 void 4617 mlx5e_cleanup(void) 4618 { 4619 mlx5_unregister_interface(&mlx5e_interface); 4620 } 4621 4622 static void 4623 mlx5e_show_version(void __unused *arg) 4624 { 4625 4626 printf("%s", mlx5e_version); 4627 } 4628 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL); 4629 4630 module_init_order(mlx5e_init, SI_ORDER_THIRD); 4631 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD); 4632 4633 #if (__FreeBSD_version >= 1100000) 4634 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1); 4635 #endif 4636 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1); 4637 MODULE_VERSION(mlx5en, 1); 4638