1 /*- 2 * Copyright (c) 2015-2021 Mellanox Technologies. All rights reserved. 3 * Copyright (c) 2022 NVIDIA corporation & affiliates. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include "opt_ipsec.h" 28 #include "opt_kern_tls.h" 29 #include "opt_rss.h" 30 #include "opt_ratelimit.h" 31 32 #include <dev/mlx5/mlx5_en/en.h> 33 34 #include <sys/eventhandler.h> 35 #include <sys/sockio.h> 36 #include <machine/atomic.h> 37 38 #include <net/debugnet.h> 39 #include <netipsec/keydb.h> 40 #include <netipsec/ipsec_offload.h> 41 42 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs); 43 static if_snd_tag_query_t mlx5e_ul_snd_tag_query; 44 static if_snd_tag_free_t mlx5e_ul_snd_tag_free; 45 46 struct mlx5e_channel_param { 47 struct mlx5e_rq_param rq; 48 struct mlx5e_sq_param sq; 49 struct mlx5e_cq_param rx_cq; 50 struct mlx5e_cq_param tx_cq; 51 }; 52 53 struct media { 54 u32 subtype; 55 u64 baudrate; 56 }; 57 58 static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER] = 59 { 60 [MLX5E_1000BASE_CX_SGMII] = { 61 .subtype = IFM_1000_CX_SGMII, 62 .baudrate = IF_Mbps(1000ULL), 63 }, 64 [MLX5E_1000BASE_KX] = { 65 .subtype = IFM_1000_KX, 66 .baudrate = IF_Mbps(1000ULL), 67 }, 68 [MLX5E_10GBASE_CX4] = { 69 .subtype = IFM_10G_CX4, 70 .baudrate = IF_Gbps(10ULL), 71 }, 72 [MLX5E_10GBASE_KX4] = { 73 .subtype = IFM_10G_KX4, 74 .baudrate = IF_Gbps(10ULL), 75 }, 76 [MLX5E_10GBASE_KR] = { 77 .subtype = IFM_10G_KR, 78 .baudrate = IF_Gbps(10ULL), 79 }, 80 [MLX5E_20GBASE_KR2] = { 81 .subtype = IFM_20G_KR2, 82 .baudrate = IF_Gbps(20ULL), 83 }, 84 [MLX5E_40GBASE_CR4] = { 85 .subtype = IFM_40G_CR4, 86 .baudrate = IF_Gbps(40ULL), 87 }, 88 [MLX5E_40GBASE_KR4] = { 89 .subtype = IFM_40G_KR4, 90 .baudrate = IF_Gbps(40ULL), 91 }, 92 [MLX5E_56GBASE_R4] = { 93 .subtype = IFM_56G_R4, 94 .baudrate = IF_Gbps(56ULL), 95 }, 96 [MLX5E_10GBASE_CR] = { 97 .subtype = IFM_10G_CR1, 98 .baudrate = IF_Gbps(10ULL), 99 }, 100 [MLX5E_10GBASE_SR] = { 101 .subtype = IFM_10G_SR, 102 .baudrate = IF_Gbps(10ULL), 103 }, 104 [MLX5E_10GBASE_ER_LR] = { 105 .subtype = IFM_10G_ER, 106 .baudrate = IF_Gbps(10ULL), 107 }, 108 [MLX5E_40GBASE_SR4] = { 109 .subtype = IFM_40G_SR4, 110 .baudrate = IF_Gbps(40ULL), 111 }, 112 [MLX5E_40GBASE_LR4_ER4] = { 113 .subtype = IFM_40G_LR4, 114 .baudrate = IF_Gbps(40ULL), 115 }, 116 [MLX5E_100GBASE_CR4] = { 117 .subtype = IFM_100G_CR4, 118 .baudrate = IF_Gbps(100ULL), 119 }, 120 [MLX5E_100GBASE_SR4] = { 121 .subtype = IFM_100G_SR4, 122 .baudrate = IF_Gbps(100ULL), 123 }, 124 [MLX5E_100GBASE_KR4] = { 125 .subtype = IFM_100G_KR4, 126 .baudrate = IF_Gbps(100ULL), 127 }, 128 [MLX5E_100GBASE_LR4] = { 129 .subtype = IFM_100G_LR4, 130 .baudrate = IF_Gbps(100ULL), 131 }, 132 [MLX5E_100BASE_TX] = { 133 .subtype = IFM_100_TX, 134 .baudrate = IF_Mbps(100ULL), 135 }, 136 [MLX5E_1000BASE_T] = { 137 .subtype = IFM_1000_T, 138 .baudrate = IF_Mbps(1000ULL), 139 }, 140 [MLX5E_10GBASE_T] = { 141 .subtype = IFM_10G_T, 142 .baudrate = IF_Gbps(10ULL), 143 }, 144 [MLX5E_25GBASE_CR] = { 145 .subtype = IFM_25G_CR, 146 .baudrate = IF_Gbps(25ULL), 147 }, 148 [MLX5E_25GBASE_KR] = { 149 .subtype = IFM_25G_KR, 150 .baudrate = IF_Gbps(25ULL), 151 }, 152 [MLX5E_25GBASE_SR] = { 153 .subtype = IFM_25G_SR, 154 .baudrate = IF_Gbps(25ULL), 155 }, 156 [MLX5E_50GBASE_CR2] = { 157 .subtype = IFM_50G_CR2, 158 .baudrate = IF_Gbps(50ULL), 159 }, 160 [MLX5E_50GBASE_KR2] = { 161 .subtype = IFM_50G_KR2, 162 .baudrate = IF_Gbps(50ULL), 163 }, 164 [MLX5E_50GBASE_KR4] = { 165 .subtype = IFM_50G_KR4, 166 .baudrate = IF_Gbps(50ULL), 167 }, 168 }; 169 170 static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_CABLE_TYPE_NUMBER] = 171 { 172 /**/ 173 [MLX5E_SGMII_100M][MLX5E_CABLE_TYPE_UNKNOWN] = { 174 .subtype = IFM_100_SGMII, 175 .baudrate = IF_Mbps(100), 176 }, 177 178 /**/ 179 [MLX5E_1000BASE_X_SGMII][MLX5E_CABLE_TYPE_UNKNOWN] = { 180 .subtype = IFM_1000_CX, 181 .baudrate = IF_Mbps(1000), 182 }, 183 [MLX5E_1000BASE_X_SGMII][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 184 .subtype = IFM_1000_SX, 185 .baudrate = IF_Mbps(1000), 186 }, 187 188 /**/ 189 [MLX5E_5GBASE_R][MLX5E_CABLE_TYPE_UNKNOWN] = { 190 .subtype = IFM_5000_KR, 191 .baudrate = IF_Mbps(5000), 192 }, 193 [MLX5E_5GBASE_R][MLX5E_CABLE_TYPE_TWISTED_PAIR] = { 194 .subtype = IFM_5000_T, 195 .baudrate = IF_Mbps(5000), 196 }, 197 198 /**/ 199 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CABLE_TYPE_UNKNOWN] = { 200 .subtype = IFM_10G_KR, 201 .baudrate = IF_Gbps(10ULL), 202 }, 203 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 204 .subtype = IFM_10G_CR1, 205 .baudrate = IF_Gbps(10ULL), 206 }, 207 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 208 .subtype = IFM_10G_SR, 209 .baudrate = IF_Gbps(10ULL), 210 }, 211 212 /**/ 213 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CABLE_TYPE_UNKNOWN] = { 214 .subtype = IFM_40G_KR4, 215 .baudrate = IF_Gbps(40ULL), 216 }, 217 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 218 .subtype = IFM_40G_CR4, 219 .baudrate = IF_Gbps(40ULL), 220 }, 221 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 222 .subtype = IFM_40G_SR4, 223 .baudrate = IF_Gbps(40ULL), 224 }, 225 226 /**/ 227 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_UNKNOWN] = { 228 .subtype = IFM_25G_KR, 229 .baudrate = IF_Gbps(25ULL), 230 }, 231 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 232 .subtype = IFM_25G_CR, 233 .baudrate = IF_Gbps(25ULL), 234 }, 235 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 236 .subtype = IFM_25G_SR, 237 .baudrate = IF_Gbps(25ULL), 238 }, 239 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_TWISTED_PAIR] = { 240 .subtype = IFM_25G_T, 241 .baudrate = IF_Gbps(25ULL), 242 }, 243 244 /**/ 245 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CABLE_TYPE_UNKNOWN] = { 246 .subtype = IFM_50G_KR2, 247 .baudrate = IF_Gbps(50ULL), 248 }, 249 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 250 .subtype = IFM_50G_CR2, 251 .baudrate = IF_Gbps(50ULL), 252 }, 253 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 254 .subtype = IFM_50G_SR2, 255 .baudrate = IF_Gbps(50ULL), 256 }, 257 258 /**/ 259 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CABLE_TYPE_UNKNOWN] = { 260 .subtype = IFM_50G_KR_PAM4, 261 .baudrate = IF_Gbps(50ULL), 262 }, 263 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 264 .subtype = IFM_50G_CP, 265 .baudrate = IF_Gbps(50ULL), 266 }, 267 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 268 .subtype = IFM_50G_SR, 269 .baudrate = IF_Gbps(50ULL), 270 }, 271 272 /**/ 273 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CABLE_TYPE_UNKNOWN] = { 274 .subtype = IFM_100G_KR4, 275 .baudrate = IF_Gbps(100ULL), 276 }, 277 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 278 .subtype = IFM_100G_CR4, 279 .baudrate = IF_Gbps(100ULL), 280 }, 281 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 282 .subtype = IFM_100G_SR4, 283 .baudrate = IF_Gbps(100ULL), 284 }, 285 286 /**/ 287 [MLX5E_100GAUI_1_100GBASE_CR_KR][MLX5E_CABLE_TYPE_UNKNOWN] = { 288 .subtype = IFM_100G_KR_PAM4, 289 .baudrate = IF_Gbps(100ULL), 290 }, 291 [MLX5E_100GAUI_1_100GBASE_CR_KR][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 292 .subtype = IFM_100G_CR_PAM4, 293 .baudrate = IF_Gbps(100ULL), 294 }, 295 [MLX5E_100GAUI_1_100GBASE_CR_KR][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 296 .subtype = IFM_100G_SR2, /* XXX */ 297 .baudrate = IF_Gbps(100ULL), 298 }, 299 300 /**/ 301 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CABLE_TYPE_UNKNOWN] = { 302 .subtype = IFM_100G_KR4, 303 .baudrate = IF_Gbps(100ULL), 304 }, 305 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 306 .subtype = IFM_100G_CP2, 307 .baudrate = IF_Gbps(100ULL), 308 }, 309 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 310 .subtype = IFM_100G_SR2, 311 .baudrate = IF_Gbps(100ULL), 312 }, 313 314 /**/ 315 [MLX5E_200GAUI_2_200GBASE_CR2_KR2][MLX5E_CABLE_TYPE_UNKNOWN] = { 316 .subtype = IFM_200G_KR4_PAM4, /* XXX */ 317 .baudrate = IF_Gbps(200ULL), 318 }, 319 [MLX5E_200GAUI_2_200GBASE_CR2_KR2][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 320 .subtype = IFM_200G_CR4_PAM4, /* XXX */ 321 .baudrate = IF_Gbps(200ULL), 322 }, 323 [MLX5E_200GAUI_2_200GBASE_CR2_KR2][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 324 .subtype = IFM_200G_SR4, /* XXX */ 325 .baudrate = IF_Gbps(200ULL), 326 }, 327 328 /**/ 329 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CABLE_TYPE_UNKNOWN] = { 330 .subtype = IFM_200G_KR4_PAM4, 331 .baudrate = IF_Gbps(200ULL), 332 }, 333 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = { 334 .subtype = IFM_200G_CR4_PAM4, 335 .baudrate = IF_Gbps(200ULL), 336 }, 337 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = { 338 .subtype = IFM_200G_SR4, 339 .baudrate = IF_Gbps(200ULL), 340 }, 341 342 /**/ 343 [MLX5E_400GAUI_8][MLX5E_CABLE_TYPE_UNKNOWN] = { 344 .subtype = IFM_400G_LR8, /* XXX */ 345 .baudrate = IF_Gbps(400ULL), 346 }, 347 348 /**/ 349 [MLX5E_400GAUI_4_400GBASE_CR4_KR4][MLX5E_CABLE_TYPE_UNKNOWN] = { 350 .subtype = IFM_400G_LR8, /* XXX */ 351 .baudrate = IF_Gbps(400ULL), 352 }, 353 }; 354 355 static const struct if_snd_tag_sw mlx5e_ul_snd_tag_sw = { 356 .snd_tag_query = mlx5e_ul_snd_tag_query, 357 .snd_tag_free = mlx5e_ul_snd_tag_free, 358 .type = IF_SND_TAG_TYPE_UNLIMITED 359 }; 360 361 DEBUGNET_DEFINE(mlx5_en); 362 363 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet"); 364 365 static void 366 mlx5e_update_carrier(struct mlx5e_priv *priv) 367 { 368 struct mlx5_core_dev *mdev = priv->mdev; 369 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 370 u32 eth_proto_oper; 371 int error; 372 u8 i; 373 u8 cable_type; 374 u8 port_state; 375 u8 is_er_type; 376 bool ext; 377 struct media media_entry = {}; 378 379 port_state = mlx5_query_vport_state(mdev, 380 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0); 381 382 if (port_state == VPORT_STATE_UP) { 383 priv->media_status_last |= IFM_ACTIVE; 384 } else { 385 priv->media_status_last &= ~IFM_ACTIVE; 386 priv->media_active_last = IFM_ETHER; 387 if_link_state_change(priv->ifp, LINK_STATE_DOWN); 388 return; 389 } 390 391 error = mlx5_query_port_ptys(mdev, out, sizeof(out), 392 MLX5_PTYS_EN, 1); 393 if (error) { 394 priv->media_active_last = IFM_ETHER; 395 if_setbaudrate(priv->ifp, 1); 396 mlx5_en_err(priv->ifp, "query port ptys failed: 0x%x\n", 397 error); 398 return; 399 } 400 401 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet); 402 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 403 eth_proto_oper); 404 405 i = ilog2(eth_proto_oper); 406 407 if (ext) { 408 error = mlx5_query_pddr_cable_type(mdev, 1, &cable_type); 409 if (error != 0) { 410 /* use fallback entry */ 411 media_entry = mlx5e_ext_mode_table[i][MLX5E_CABLE_TYPE_UNKNOWN]; 412 413 mlx5_en_err(priv->ifp, 414 "query port pddr failed: %d\n", error); 415 } else { 416 media_entry = mlx5e_ext_mode_table[i][cable_type]; 417 418 /* check if we should use fallback entry */ 419 if (media_entry.subtype == 0) 420 media_entry = mlx5e_ext_mode_table[i][MLX5E_CABLE_TYPE_UNKNOWN]; 421 } 422 } else { 423 media_entry = mlx5e_mode_table[i]; 424 } 425 426 if (media_entry.subtype == 0) { 427 mlx5_en_err(priv->ifp, 428 "Could not find operational media subtype\n"); 429 return; 430 } 431 432 switch (media_entry.subtype) { 433 case IFM_10G_ER: 434 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type); 435 if (error != 0) { 436 mlx5_en_err(priv->ifp, 437 "query port pddr failed: %d\n", error); 438 } 439 if (error != 0 || is_er_type == 0) 440 media_entry.subtype = IFM_10G_LR; 441 break; 442 case IFM_40G_LR4: 443 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type); 444 if (error != 0) { 445 mlx5_en_err(priv->ifp, 446 "query port pddr failed: %d\n", error); 447 } 448 if (error == 0 && is_er_type != 0) 449 media_entry.subtype = IFM_40G_ER4; 450 break; 451 } 452 priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX; 453 if_setbaudrate(priv->ifp, media_entry.baudrate); 454 455 if_link_state_change(priv->ifp, LINK_STATE_UP); 456 } 457 458 static void 459 mlx5e_media_status(if_t dev, struct ifmediareq *ifmr) 460 { 461 struct mlx5e_priv *priv = if_getsoftc(dev); 462 463 ifmr->ifm_status = priv->media_status_last; 464 ifmr->ifm_current = ifmr->ifm_active = priv->media_active_last | 465 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) | 466 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0); 467 468 } 469 470 static u32 471 mlx5e_find_link_mode(u32 subtype, bool ext) 472 { 473 u32 link_mode = 0; 474 475 switch (subtype) { 476 case 0: 477 goto done; 478 case IFM_10G_LR: 479 subtype = IFM_10G_ER; 480 break; 481 case IFM_40G_ER4: 482 subtype = IFM_40G_LR4; 483 break; 484 default: 485 break; 486 } 487 488 if (ext) { 489 for (unsigned i = 0; i != MLX5E_EXT_LINK_SPEEDS_NUMBER; i++) { 490 for (unsigned j = 0; j != MLX5E_CABLE_TYPE_NUMBER; j++) { 491 if (mlx5e_ext_mode_table[i][j].subtype == subtype) 492 link_mode |= MLX5E_PROT_MASK(i); 493 } 494 } 495 } else { 496 for (unsigned i = 0; i != MLX5E_LINK_SPEEDS_NUMBER; i++) { 497 if (mlx5e_mode_table[i].subtype == subtype) 498 link_mode |= MLX5E_PROT_MASK(i); 499 } 500 } 501 done: 502 return (link_mode); 503 } 504 505 static int 506 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv) 507 { 508 return (mlx5_set_port_pause_and_pfc(priv->mdev, 1, 509 priv->params.rx_pauseframe_control, 510 priv->params.tx_pauseframe_control, 511 priv->params.rx_priority_flow_control, 512 priv->params.tx_priority_flow_control)); 513 } 514 515 static int 516 mlx5e_set_port_pfc(struct mlx5e_priv *priv) 517 { 518 int error; 519 520 if (priv->gone != 0) { 521 error = -ENXIO; 522 } else if (priv->params.rx_pauseframe_control || 523 priv->params.tx_pauseframe_control) { 524 mlx5_en_err(priv->ifp, 525 "Global pauseframes must be disabled before enabling PFC.\n"); 526 error = -EINVAL; 527 } else { 528 error = mlx5e_set_port_pause_and_pfc(priv); 529 } 530 return (error); 531 } 532 533 static int 534 mlx5e_media_change(if_t dev) 535 { 536 struct mlx5e_priv *priv = if_getsoftc(dev); 537 struct mlx5_core_dev *mdev = priv->mdev; 538 u32 eth_proto_cap; 539 u32 link_mode; 540 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 541 int was_opened; 542 int locked; 543 int error; 544 bool ext; 545 546 locked = PRIV_LOCKED(priv); 547 if (!locked) 548 PRIV_LOCK(priv); 549 550 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) { 551 error = EINVAL; 552 goto done; 553 } 554 555 error = mlx5_query_port_ptys(mdev, out, sizeof(out), 556 MLX5_PTYS_EN, 1); 557 if (error != 0) { 558 mlx5_en_err(dev, "Query port media capability failed\n"); 559 goto done; 560 } 561 562 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet); 563 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext); 564 565 /* query supported capabilities */ 566 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 567 eth_proto_capability); 568 569 /* check for autoselect */ 570 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) { 571 link_mode = eth_proto_cap; 572 if (link_mode == 0) { 573 mlx5_en_err(dev, "Port media capability is zero\n"); 574 error = EINVAL; 575 goto done; 576 } 577 } else { 578 link_mode = link_mode & eth_proto_cap; 579 if (link_mode == 0) { 580 mlx5_en_err(dev, "Not supported link mode requested\n"); 581 error = EINVAL; 582 goto done; 583 } 584 } 585 if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) { 586 /* check if PFC is enabled */ 587 if (priv->params.rx_priority_flow_control || 588 priv->params.tx_priority_flow_control) { 589 mlx5_en_err(dev, "PFC must be disabled before enabling global pauseframes.\n"); 590 error = EINVAL; 591 goto done; 592 } 593 } 594 /* update pauseframe control bits */ 595 priv->params.rx_pauseframe_control = 596 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0; 597 priv->params.tx_pauseframe_control = 598 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0; 599 600 /* check if device is opened */ 601 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 602 603 /* reconfigure the hardware */ 604 mlx5_set_port_status(mdev, MLX5_PORT_DOWN); 605 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext); 606 error = -mlx5e_set_port_pause_and_pfc(priv); 607 if (was_opened) 608 mlx5_set_port_status(mdev, MLX5_PORT_UP); 609 610 done: 611 if (!locked) 612 PRIV_UNLOCK(priv); 613 return (error); 614 } 615 616 static void 617 mlx5e_update_carrier_work(struct work_struct *work) 618 { 619 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 620 update_carrier_work); 621 622 PRIV_LOCK(priv); 623 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) 624 mlx5e_update_carrier(priv); 625 PRIV_UNLOCK(priv); 626 } 627 628 #define MLX5E_PCIE_PERF_GET_64(a,b,c,d,e,f) \ 629 s_debug->c = MLX5_GET64(mpcnt_reg, out, counter_set.f.c); 630 631 #define MLX5E_PCIE_PERF_GET_32(a,b,c,d,e,f) \ 632 s_debug->c = MLX5_GET(mpcnt_reg, out, counter_set.f.c); 633 634 static void 635 mlx5e_update_pcie_counters(struct mlx5e_priv *priv) 636 { 637 struct mlx5_core_dev *mdev = priv->mdev; 638 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug; 639 const unsigned sz = MLX5_ST_SZ_BYTES(mpcnt_reg); 640 void *out; 641 void *in; 642 int err; 643 644 /* allocate firmware request structures */ 645 in = mlx5_vzalloc(sz); 646 out = mlx5_vzalloc(sz); 647 if (in == NULL || out == NULL) 648 goto free_out; 649 650 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP); 651 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 652 if (err != 0) 653 goto free_out; 654 655 MLX5E_PCIE_PERFORMANCE_COUNTERS_64(MLX5E_PCIE_PERF_GET_64) 656 MLX5E_PCIE_PERFORMANCE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 657 658 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP); 659 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 660 if (err != 0) 661 goto free_out; 662 663 MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 664 665 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_LANE_COUNTERS_GROUP); 666 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 667 if (err != 0) 668 goto free_out; 669 670 MLX5E_PCIE_LANE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 671 672 free_out: 673 /* free firmware request structures */ 674 kvfree(in); 675 kvfree(out); 676 } 677 678 /* 679 * This function reads the physical port counters from the firmware 680 * using a pre-defined layout defined by various MLX5E_PPORT_XXX() 681 * macros. The output is converted from big-endian 64-bit values into 682 * host endian ones and stored in the "priv->stats.pport" structure. 683 */ 684 static void 685 mlx5e_update_pport_counters(struct mlx5e_priv *priv) 686 { 687 struct mlx5_core_dev *mdev = priv->mdev; 688 struct mlx5e_pport_stats *s = &priv->stats.pport; 689 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug; 690 u32 *in; 691 u32 *out; 692 const u64 *ptr; 693 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 694 unsigned x; 695 unsigned y; 696 unsigned z; 697 698 /* allocate firmware request structures */ 699 in = mlx5_vzalloc(sz); 700 out = mlx5_vzalloc(sz); 701 if (in == NULL || out == NULL) 702 goto free_out; 703 704 /* 705 * Get pointer to the 64-bit counter set which is located at a 706 * fixed offset in the output firmware request structure: 707 */ 708 ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set); 709 710 MLX5_SET(ppcnt_reg, in, local_port, 1); 711 712 /* read IEEE802_3 counter group using predefined counter layout */ 713 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP); 714 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 715 for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM; 716 x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++) 717 s->arg[y] = be64toh(ptr[x]); 718 719 /* read RFC2819 counter group using predefined counter layout */ 720 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP); 721 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 722 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++) 723 s->arg[y] = be64toh(ptr[x]); 724 725 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM + 726 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++) 727 s_debug->arg[y] = be64toh(ptr[x]); 728 729 /* read RFC2863 counter group using predefined counter layout */ 730 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP); 731 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 732 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++) 733 s_debug->arg[y] = be64toh(ptr[x]); 734 735 /* read physical layer stats counter group using predefined counter layout */ 736 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP); 737 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 738 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++) 739 s_debug->arg[y] = be64toh(ptr[x]); 740 741 /* read Extended Ethernet counter group using predefined counter layout */ 742 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP); 743 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 744 for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++) 745 s_debug->arg[y] = be64toh(ptr[x]); 746 747 /* read Extended Statistical Group */ 748 if (MLX5_CAP_GEN(mdev, pcam_reg) && 749 MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) && 750 MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) { 751 /* read Extended Statistical counter group using predefined counter layout */ 752 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP); 753 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 754 755 for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++) 756 s_debug->arg[y] = be64toh(ptr[x]); 757 } 758 759 /* read PCIE counters */ 760 mlx5e_update_pcie_counters(priv); 761 762 /* read per-priority counters */ 763 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP); 764 765 /* iterate all the priorities */ 766 for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) { 767 MLX5_SET(ppcnt_reg, in, prio_tc, z); 768 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 769 770 /* read per priority stats counter group using predefined counter layout */ 771 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM / 772 MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++) 773 s->arg[y] = be64toh(ptr[x]); 774 } 775 776 free_out: 777 /* free firmware request structures */ 778 kvfree(in); 779 kvfree(out); 780 } 781 782 static void 783 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv) 784 { 785 u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {}; 786 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {}; 787 788 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard)) 789 return; 790 791 MLX5_SET(query_vnic_env_in, in, opcode, 792 MLX5_CMD_OP_QUERY_VNIC_ENV); 793 MLX5_SET(query_vnic_env_in, in, op_mod, 0); 794 MLX5_SET(query_vnic_env_in, in, other_vport, 0); 795 796 if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0) 797 return; 798 799 priv->stats.vport.rx_steer_missed_packets = 800 MLX5_GET64(query_vnic_env_out, out, 801 vport_env.nic_receive_steering_discard); 802 } 803 804 /* 805 * This function is called regularly to collect all statistics 806 * counters from the firmware. The values can be viewed through the 807 * sysctl interface. Execution is serialized using the priv's global 808 * configuration lock. 809 */ 810 static void 811 mlx5e_update_stats_locked(struct mlx5e_priv *priv) 812 { 813 struct mlx5_core_dev *mdev = priv->mdev; 814 struct mlx5e_vport_stats *s = &priv->stats.vport; 815 struct mlx5e_sq_stats *sq_stats; 816 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)]; 817 u32 *out; 818 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out); 819 u64 tso_packets = 0; 820 u64 tso_bytes = 0; 821 u64 tx_queue_dropped = 0; 822 u64 tx_defragged = 0; 823 u64 tx_offload_none = 0; 824 u64 lro_packets = 0; 825 u64 lro_bytes = 0; 826 u64 sw_lro_queued = 0; 827 u64 sw_lro_flushed = 0; 828 u64 rx_csum_none = 0; 829 u64 rx_wqe_err = 0; 830 u64 rx_packets = 0; 831 u64 rx_bytes = 0; 832 u64 rx_decrypted_error = 0; 833 u64 rx_decrypted_ok = 0; 834 u32 rx_out_of_buffer = 0; 835 int error; 836 int i; 837 int j; 838 839 out = mlx5_vzalloc(outlen); 840 if (out == NULL) 841 goto free_out; 842 843 /* Collect firts the SW counters and then HW for consistency */ 844 for (i = 0; i < priv->params.num_channels; i++) { 845 struct mlx5e_channel *pch = priv->channel + i; 846 struct mlx5e_rq *rq = &pch->rq; 847 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats; 848 849 /* collect stats from LRO */ 850 rq_stats->sw_lro_queued = rq->lro.lro_queued; 851 rq_stats->sw_lro_flushed = rq->lro.lro_flushed; 852 sw_lro_queued += rq_stats->sw_lro_queued; 853 sw_lro_flushed += rq_stats->sw_lro_flushed; 854 lro_packets += rq_stats->lro_packets; 855 lro_bytes += rq_stats->lro_bytes; 856 rx_csum_none += rq_stats->csum_none; 857 rx_wqe_err += rq_stats->wqe_err; 858 rx_packets += rq_stats->packets; 859 rx_bytes += rq_stats->bytes; 860 rx_decrypted_error += rq_stats->decrypted_error_packets; 861 rx_decrypted_ok += rq_stats->decrypted_ok_packets; 862 863 for (j = 0; j < priv->num_tc; j++) { 864 sq_stats = &pch->sq[j].stats; 865 866 tso_packets += sq_stats->tso_packets; 867 tso_bytes += sq_stats->tso_bytes; 868 tx_queue_dropped += sq_stats->dropped; 869 tx_queue_dropped += sq_stats->enobuf; 870 tx_defragged += sq_stats->defragged; 871 tx_offload_none += sq_stats->csum_offload_none; 872 } 873 } 874 875 #ifdef RATELIMIT 876 /* Collect statistics from all rate-limit queues */ 877 for (j = 0; j < priv->rl.param.tx_worker_threads_def; j++) { 878 struct mlx5e_rl_worker *rlw = priv->rl.workers + j; 879 880 for (i = 0; i < priv->rl.param.tx_channels_per_worker_def; i++) { 881 struct mlx5e_rl_channel *channel = rlw->channels + i; 882 struct mlx5e_sq *sq = channel->sq; 883 884 if (sq == NULL) 885 continue; 886 887 sq_stats = &sq->stats; 888 889 tso_packets += sq_stats->tso_packets; 890 tso_bytes += sq_stats->tso_bytes; 891 tx_queue_dropped += sq_stats->dropped; 892 tx_queue_dropped += sq_stats->enobuf; 893 tx_defragged += sq_stats->defragged; 894 tx_offload_none += sq_stats->csum_offload_none; 895 } 896 } 897 #endif 898 899 /* update counters */ 900 s->tso_packets = tso_packets; 901 s->tso_bytes = tso_bytes; 902 s->tx_queue_dropped = tx_queue_dropped; 903 s->tx_defragged = tx_defragged; 904 s->lro_packets = lro_packets; 905 s->lro_bytes = lro_bytes; 906 s->sw_lro_queued = sw_lro_queued; 907 s->sw_lro_flushed = sw_lro_flushed; 908 s->rx_csum_none = rx_csum_none; 909 s->rx_wqe_err = rx_wqe_err; 910 s->rx_packets = rx_packets; 911 s->rx_bytes = rx_bytes; 912 s->rx_decrypted_error_packets = rx_decrypted_error; 913 s->rx_decrypted_ok_packets = rx_decrypted_ok; 914 915 mlx5e_grp_vnic_env_update_stats(priv); 916 917 /* HW counters */ 918 memset(in, 0, sizeof(in)); 919 920 MLX5_SET(query_vport_counter_in, in, opcode, 921 MLX5_CMD_OP_QUERY_VPORT_COUNTER); 922 MLX5_SET(query_vport_counter_in, in, op_mod, 0); 923 MLX5_SET(query_vport_counter_in, in, other_vport, 0); 924 925 memset(out, 0, outlen); 926 927 /* get number of out-of-buffer drops first */ 928 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 && 929 mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id, 930 &rx_out_of_buffer) == 0) { 931 s->rx_out_of_buffer = rx_out_of_buffer; 932 } 933 934 /* get port statistics */ 935 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) { 936 #define MLX5_GET_CTR(out, x) \ 937 MLX5_GET64(query_vport_counter_out, out, x) 938 939 s->rx_error_packets = 940 MLX5_GET_CTR(out, received_errors.packets); 941 s->rx_error_bytes = 942 MLX5_GET_CTR(out, received_errors.octets); 943 s->tx_error_packets = 944 MLX5_GET_CTR(out, transmit_errors.packets); 945 s->tx_error_bytes = 946 MLX5_GET_CTR(out, transmit_errors.octets); 947 948 s->rx_unicast_packets = 949 MLX5_GET_CTR(out, received_eth_unicast.packets); 950 s->rx_unicast_bytes = 951 MLX5_GET_CTR(out, received_eth_unicast.octets); 952 s->tx_unicast_packets = 953 MLX5_GET_CTR(out, transmitted_eth_unicast.packets); 954 s->tx_unicast_bytes = 955 MLX5_GET_CTR(out, transmitted_eth_unicast.octets); 956 957 s->rx_multicast_packets = 958 MLX5_GET_CTR(out, received_eth_multicast.packets); 959 s->rx_multicast_bytes = 960 MLX5_GET_CTR(out, received_eth_multicast.octets); 961 s->tx_multicast_packets = 962 MLX5_GET_CTR(out, transmitted_eth_multicast.packets); 963 s->tx_multicast_bytes = 964 MLX5_GET_CTR(out, transmitted_eth_multicast.octets); 965 966 s->rx_broadcast_packets = 967 MLX5_GET_CTR(out, received_eth_broadcast.packets); 968 s->rx_broadcast_bytes = 969 MLX5_GET_CTR(out, received_eth_broadcast.octets); 970 s->tx_broadcast_packets = 971 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets); 972 s->tx_broadcast_bytes = 973 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets); 974 975 s->tx_packets = s->tx_unicast_packets + 976 s->tx_multicast_packets + s->tx_broadcast_packets; 977 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes + 978 s->tx_broadcast_bytes; 979 980 /* Update calculated offload counters */ 981 s->tx_csum_offload = s->tx_packets - tx_offload_none; 982 s->rx_csum_good = s->rx_packets - s->rx_csum_none; 983 } 984 985 /* Get physical port counters */ 986 mlx5e_update_pport_counters(priv); 987 988 s->tx_jumbo_packets = 989 priv->stats.port_stats_debug.tx_stat_p1519to2047octets + 990 priv->stats.port_stats_debug.tx_stat_p2048to4095octets + 991 priv->stats.port_stats_debug.tx_stat_p4096to8191octets + 992 priv->stats.port_stats_debug.tx_stat_p8192to10239octets; 993 994 free_out: 995 kvfree(out); 996 997 /* Update diagnostics, if any */ 998 if (priv->params_ethtool.diag_pci_enable || 999 priv->params_ethtool.diag_general_enable) { 1000 error = mlx5_core_get_diagnostics_full(mdev, 1001 priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL, 1002 priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL); 1003 if (error != 0) 1004 mlx5_en_err(priv->ifp, 1005 "Failed reading diagnostics: %d\n", error); 1006 } 1007 1008 /* Update FEC, if any */ 1009 error = mlx5e_fec_update(priv); 1010 if (error != 0 && error != EOPNOTSUPP) { 1011 mlx5_en_err(priv->ifp, 1012 "Updating FEC failed: %d\n", error); 1013 } 1014 1015 /* Update temperature, if any */ 1016 if (priv->params_ethtool.hw_num_temp != 0) { 1017 error = mlx5e_hw_temperature_update(priv); 1018 if (error != 0 && error != EOPNOTSUPP) { 1019 mlx5_en_err(priv->ifp, 1020 "Updating temperature failed: %d\n", error); 1021 } 1022 } 1023 } 1024 1025 static void 1026 mlx5e_update_stats_work(struct work_struct *work) 1027 { 1028 struct mlx5e_priv *priv; 1029 1030 priv = container_of(work, struct mlx5e_priv, update_stats_work); 1031 PRIV_LOCK(priv); 1032 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 && 1033 !test_bit(MLX5_INTERFACE_STATE_TEARDOWN, &priv->mdev->intf_state)) 1034 mlx5e_update_stats_locked(priv); 1035 PRIV_UNLOCK(priv); 1036 } 1037 1038 static void 1039 mlx5e_update_stats(void *arg) 1040 { 1041 struct mlx5e_priv *priv = arg; 1042 1043 queue_work(priv->wq, &priv->update_stats_work); 1044 1045 callout_reset(&priv->watchdog, hz / 4, &mlx5e_update_stats, priv); 1046 } 1047 1048 static void 1049 mlx5e_async_event_sub(struct mlx5e_priv *priv, 1050 enum mlx5_dev_event event) 1051 { 1052 switch (event) { 1053 case MLX5_DEV_EVENT_PORT_UP: 1054 case MLX5_DEV_EVENT_PORT_DOWN: 1055 queue_work(priv->wq, &priv->update_carrier_work); 1056 break; 1057 1058 default: 1059 break; 1060 } 1061 } 1062 1063 static void 1064 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv, 1065 enum mlx5_dev_event event, unsigned long param) 1066 { 1067 struct mlx5e_priv *priv = vpriv; 1068 1069 mtx_lock(&priv->async_events_mtx); 1070 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state)) 1071 mlx5e_async_event_sub(priv, event); 1072 mtx_unlock(&priv->async_events_mtx); 1073 } 1074 1075 static void 1076 mlx5e_enable_async_events(struct mlx5e_priv *priv) 1077 { 1078 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 1079 } 1080 1081 static void 1082 mlx5e_disable_async_events(struct mlx5e_priv *priv) 1083 { 1084 mtx_lock(&priv->async_events_mtx); 1085 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 1086 mtx_unlock(&priv->async_events_mtx); 1087 } 1088 1089 static void mlx5e_calibration_callout(void *arg); 1090 static int mlx5e_calibration_duration = 20; 1091 static int mlx5e_fast_calibration = 1; 1092 static int mlx5e_normal_calibration = 30; 1093 1094 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 1095 "MLX5 timestamp calibration parameters"); 1096 1097 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN, 1098 &mlx5e_calibration_duration, 0, 1099 "Duration of initial calibration"); 1100 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN, 1101 &mlx5e_fast_calibration, 0, 1102 "Recalibration interval during initial calibration"); 1103 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN, 1104 &mlx5e_normal_calibration, 0, 1105 "Recalibration interval during normal operations"); 1106 1107 /* 1108 * Ignites the calibration process. 1109 */ 1110 static void 1111 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv) 1112 { 1113 1114 if (priv->clbr_done == 0) 1115 mlx5e_calibration_callout(priv); 1116 else 1117 callout_reset_sbt_curcpu(&priv->tstmp_clbr, (priv->clbr_done < 1118 mlx5e_calibration_duration ? mlx5e_fast_calibration : 1119 mlx5e_normal_calibration) * SBT_1S, 0, 1120 mlx5e_calibration_callout, priv, C_DIRECT_EXEC); 1121 } 1122 1123 static uint64_t 1124 mlx5e_timespec2usec(const struct timespec *ts) 1125 { 1126 1127 return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec); 1128 } 1129 1130 static uint64_t 1131 mlx5e_hw_clock(struct mlx5e_priv *priv) 1132 { 1133 struct mlx5_init_seg *iseg; 1134 uint32_t hw_h, hw_h1, hw_l; 1135 1136 iseg = priv->mdev->iseg; 1137 do { 1138 hw_h = ioread32be(&iseg->internal_timer_h); 1139 hw_l = ioread32be(&iseg->internal_timer_l); 1140 hw_h1 = ioread32be(&iseg->internal_timer_h); 1141 } while (hw_h1 != hw_h); 1142 return (((uint64_t)hw_h << 32) | hw_l); 1143 } 1144 1145 /* 1146 * The calibration callout, it runs either in the context of the 1147 * thread which enables calibration, or in callout. It takes the 1148 * snapshot of system and adapter clocks, then advances the pointers to 1149 * the calibration point to allow rx path to read the consistent data 1150 * lockless. 1151 */ 1152 static void 1153 mlx5e_calibration_callout(void *arg) 1154 { 1155 struct mlx5e_priv *priv; 1156 struct mlx5e_clbr_point *next, *curr; 1157 struct timespec ts; 1158 int clbr_curr_next; 1159 1160 priv = arg; 1161 curr = &priv->clbr_points[priv->clbr_curr]; 1162 clbr_curr_next = priv->clbr_curr + 1; 1163 if (clbr_curr_next >= nitems(priv->clbr_points)) 1164 clbr_curr_next = 0; 1165 next = &priv->clbr_points[clbr_curr_next]; 1166 1167 next->base_prev = curr->base_curr; 1168 next->clbr_hw_prev = curr->clbr_hw_curr; 1169 1170 next->clbr_hw_curr = mlx5e_hw_clock(priv); 1171 if (((next->clbr_hw_curr - curr->clbr_hw_curr) >> MLX5E_TSTMP_PREC) == 1172 0) { 1173 if (priv->clbr_done != 0) { 1174 mlx5_en_err(priv->ifp, 1175 "HW failed tstmp frozen %#jx %#jx, disabling\n", 1176 next->clbr_hw_curr, curr->clbr_hw_prev); 1177 priv->clbr_done = 0; 1178 } 1179 atomic_store_rel_int(&curr->clbr_gen, 0); 1180 return; 1181 } 1182 1183 nanouptime(&ts); 1184 next->base_curr = mlx5e_timespec2usec(&ts); 1185 1186 curr->clbr_gen = 0; 1187 atomic_thread_fence_rel(); 1188 priv->clbr_curr = clbr_curr_next; 1189 atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen)); 1190 1191 if (priv->clbr_done < mlx5e_calibration_duration) 1192 priv->clbr_done++; 1193 mlx5e_reset_calibration_callout(priv); 1194 } 1195 1196 static const char *mlx5e_rq_stats_desc[] = { 1197 MLX5E_RQ_STATS(MLX5E_STATS_DESC) 1198 }; 1199 1200 static int 1201 mlx5e_create_rq(struct mlx5e_channel *c, 1202 struct mlx5e_rq_param *param, 1203 struct mlx5e_rq *rq) 1204 { 1205 struct mlx5e_priv *priv = c->priv; 1206 struct mlx5_core_dev *mdev = priv->mdev; 1207 char buffer[16]; 1208 void *rqc = param->rqc; 1209 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); 1210 int wq_sz; 1211 int err; 1212 int i; 1213 u32 nsegs, wqe_sz; 1214 1215 err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs); 1216 if (err != 0) 1217 goto done; 1218 1219 /* Create DMA descriptor TAG */ 1220 if ((err = -bus_dma_tag_create( 1221 bus_get_dma_tag(mdev->pdev->dev.bsddev), 1222 1, /* any alignment */ 1223 0, /* no boundary */ 1224 BUS_SPACE_MAXADDR, /* lowaddr */ 1225 BUS_SPACE_MAXADDR, /* highaddr */ 1226 NULL, NULL, /* filter, filterarg */ 1227 nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */ 1228 nsegs, /* nsegments */ 1229 nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */ 1230 0, /* flags */ 1231 NULL, NULL, /* lockfunc, lockfuncarg */ 1232 &rq->dma_tag))) 1233 goto done; 1234 1235 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, 1236 &rq->wq_ctrl); 1237 if (err) 1238 goto err_free_dma_tag; 1239 1240 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR]; 1241 1242 err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs); 1243 if (err != 0) 1244 goto err_rq_wq_destroy; 1245 1246 wq_sz = mlx5_wq_ll_get_size(&rq->wq); 1247 1248 err = -tcp_lro_init_args(&rq->lro, priv->ifp, TCP_LRO_ENTRIES, wq_sz); 1249 if (err) 1250 goto err_rq_wq_destroy; 1251 1252 rq->mbuf = malloc_domainset(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, 1253 mlx5_dev_domainset(mdev), M_WAITOK | M_ZERO); 1254 for (i = 0; i != wq_sz; i++) { 1255 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i); 1256 int j; 1257 1258 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map); 1259 if (err != 0) { 1260 while (i--) 1261 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 1262 goto err_rq_mbuf_free; 1263 } 1264 1265 /* set value for constant fields */ 1266 for (j = 0; j < rq->nsegs; j++) 1267 wqe->data[j].lkey = cpu_to_be32(priv->mr.key); 1268 } 1269 1270 INIT_WORK(&rq->dim.work, mlx5e_dim_work); 1271 if (priv->params.rx_cq_moderation_mode < 2) { 1272 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 1273 } else { 1274 void *cqc = container_of(param, 1275 struct mlx5e_channel_param, rq)->rx_cq.cqc; 1276 1277 switch (MLX5_GET(cqc, cqc, cq_period_mode)) { 1278 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE: 1279 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; 1280 break; 1281 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE: 1282 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE; 1283 break; 1284 default: 1285 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 1286 break; 1287 } 1288 } 1289 1290 rq->ifp = priv->ifp; 1291 rq->channel = c; 1292 rq->ix = c->ix; 1293 1294 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix); 1295 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 1296 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM, 1297 rq->stats.arg); 1298 return (0); 1299 1300 err_rq_mbuf_free: 1301 free(rq->mbuf, M_MLX5EN); 1302 tcp_lro_free(&rq->lro); 1303 err_rq_wq_destroy: 1304 mlx5_wq_destroy(&rq->wq_ctrl); 1305 err_free_dma_tag: 1306 bus_dma_tag_destroy(rq->dma_tag); 1307 done: 1308 return (err); 1309 } 1310 1311 static void 1312 mlx5e_destroy_rq(struct mlx5e_rq *rq) 1313 { 1314 int wq_sz; 1315 int i; 1316 1317 /* destroy all sysctl nodes */ 1318 sysctl_ctx_free(&rq->stats.ctx); 1319 1320 /* free leftover LRO packets, if any */ 1321 tcp_lro_free(&rq->lro); 1322 1323 wq_sz = mlx5_wq_ll_get_size(&rq->wq); 1324 for (i = 0; i != wq_sz; i++) { 1325 if (rq->mbuf[i].mbuf != NULL) { 1326 bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map); 1327 m_freem(rq->mbuf[i].mbuf); 1328 } 1329 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 1330 } 1331 free(rq->mbuf, M_MLX5EN); 1332 mlx5_wq_destroy(&rq->wq_ctrl); 1333 bus_dma_tag_destroy(rq->dma_tag); 1334 } 1335 1336 static int 1337 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param) 1338 { 1339 struct mlx5e_channel *c = rq->channel; 1340 struct mlx5e_priv *priv = c->priv; 1341 struct mlx5_core_dev *mdev = priv->mdev; 1342 void *in; 1343 void *rqc; 1344 void *wq; 1345 int inlen; 1346 int err; 1347 u8 ts_format; 1348 1349 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 1350 sizeof(u64) * rq->wq_ctrl.buf.npages; 1351 in = mlx5_vzalloc(inlen); 1352 if (in == NULL) 1353 return (-ENOMEM); 1354 1355 ts_format = mlx5_get_rq_default_ts(mdev); 1356 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1357 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1358 1359 memcpy(rqc, param->rqc, sizeof(param->rqc)); 1360 1361 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1362 MLX5_SET(rqc, rqc, ts_format, ts_format); 1363 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1364 if (priv->counter_set_id >= 0) 1365 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id); 1366 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - 1367 MLX5_ADAPTER_PAGE_SHIFT); 1368 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); 1369 1370 mlx5_fill_page_array(&rq->wq_ctrl.buf, 1371 (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 1372 1373 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); 1374 1375 kvfree(in); 1376 1377 return (err); 1378 } 1379 1380 static int 1381 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state) 1382 { 1383 struct mlx5e_channel *c = rq->channel; 1384 struct mlx5e_priv *priv = c->priv; 1385 struct mlx5_core_dev *mdev = priv->mdev; 1386 1387 void *in; 1388 void *rqc; 1389 int inlen; 1390 int err; 1391 1392 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 1393 in = mlx5_vzalloc(inlen); 1394 if (in == NULL) 1395 return (-ENOMEM); 1396 1397 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1398 1399 MLX5_SET(modify_rq_in, in, rqn, rq->rqn); 1400 MLX5_SET(modify_rq_in, in, rq_state, curr_state); 1401 MLX5_SET(rqc, rqc, state, next_state); 1402 1403 err = mlx5_core_modify_rq(mdev, in, inlen); 1404 1405 kvfree(in); 1406 1407 return (err); 1408 } 1409 1410 static void 1411 mlx5e_disable_rq(struct mlx5e_rq *rq) 1412 { 1413 struct mlx5e_channel *c = rq->channel; 1414 struct mlx5e_priv *priv = c->priv; 1415 struct mlx5_core_dev *mdev = priv->mdev; 1416 1417 mlx5_core_destroy_rq(mdev, rq->rqn); 1418 } 1419 1420 static int 1421 mlx5e_open_rq(struct mlx5e_channel *c, 1422 struct mlx5e_rq_param *param, 1423 struct mlx5e_rq *rq) 1424 { 1425 int err; 1426 1427 err = mlx5e_create_rq(c, param, rq); 1428 if (err) 1429 return (err); 1430 1431 /* set CQN in RQ parameters */ 1432 MLX5_SET(rqc, param->rqc, cqn, c->rq.cq.mcq.cqn); 1433 1434 err = mlx5e_enable_rq(rq, param); 1435 if (err) 1436 goto err_destroy_rq; 1437 1438 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 1439 if (err) 1440 goto err_disable_rq; 1441 1442 c->rq.enabled = 1; 1443 1444 return (0); 1445 1446 err_disable_rq: 1447 mlx5e_disable_rq(rq); 1448 err_destroy_rq: 1449 mlx5e_destroy_rq(rq); 1450 1451 return (err); 1452 } 1453 1454 static void 1455 mlx5e_close_rq(struct mlx5e_rq *rq) 1456 { 1457 mtx_lock(&rq->mtx); 1458 rq->enabled = 0; 1459 callout_stop(&rq->watchdog); 1460 mtx_unlock(&rq->mtx); 1461 1462 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 1463 } 1464 1465 static void 1466 mlx5e_close_rq_wait(struct mlx5e_rq *rq) 1467 { 1468 1469 mlx5e_disable_rq(rq); 1470 mlx5e_close_cq(&rq->cq); 1471 cancel_work_sync(&rq->dim.work); 1472 mlx5e_destroy_rq(rq); 1473 } 1474 1475 /* 1476 * What is a drop RQ and why is it needed? 1477 * 1478 * The RSS indirection table, also called the RQT, selects the 1479 * destination RQ based on the receive queue number, RQN. The RQT is 1480 * frequently referred to by flow steering rules to distribute traffic 1481 * among multiple RQs. The problem is that the RQs cannot be destroyed 1482 * before the RQT referring them is destroyed too. Further, TLS RX 1483 * rules may still be referring to the RQT even if the link went 1484 * down. Because there is no magic RQN for dropping packets, we create 1485 * a dummy RQ, also called drop RQ, which sole purpose is to drop all 1486 * received packets. When the link goes down this RQN is filled in all 1487 * RQT entries, of the main RQT, so the real RQs which are about to be 1488 * destroyed can be released and the TLS RX rules can be sustained. 1489 */ 1490 static void 1491 mlx5e_open_drop_rq_comp(struct mlx5_core_cq *mcq __unused, struct mlx5_eqe *eqe __unused) 1492 { 1493 } 1494 1495 static int 1496 mlx5e_open_drop_rq(struct mlx5e_priv *priv, 1497 struct mlx5e_rq *drop_rq) 1498 { 1499 struct mlx5e_cq_param param_cq = {}; 1500 struct mlx5e_rq_param param_rq = {}; 1501 void *rqc_wq = MLX5_ADDR_OF(rqc, param_rq.rqc, wq); 1502 int err; 1503 1504 /* set channel pointer */ 1505 drop_rq->channel = priv->channel; 1506 1507 /* set basic CQ parameters needed */ 1508 MLX5_SET(cqc, param_cq.cqc, log_cq_size, 0); 1509 MLX5_SET(cqc, param_cq.cqc, uar_page, priv->mdev->priv.uar->index); 1510 1511 /* open receive completion queue */ 1512 err = mlx5e_open_cq(priv, ¶m_cq, &drop_rq->cq, 1513 &mlx5e_open_drop_rq_comp, 0); 1514 if (err) 1515 goto err_done; 1516 1517 /* set basic WQ parameters needed */ 1518 MLX5_SET(wq, rqc_wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); 1519 MLX5_SET(wq, rqc_wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 1520 MLX5_SET(wq, rqc_wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) + sizeof(struct mlx5_wqe_data_seg))); 1521 MLX5_SET(wq, rqc_wq, log_wq_sz, 0); 1522 MLX5_SET(wq, rqc_wq, pd, priv->pdn); 1523 1524 param_rq.wq.linear = 1; 1525 1526 err = mlx5_wq_ll_create(priv->mdev, ¶m_rq.wq, rqc_wq, &drop_rq->wq, 1527 &drop_rq->wq_ctrl); 1528 if (err) 1529 goto err_close_cq; 1530 1531 /* set CQN in RQ parameters */ 1532 MLX5_SET(rqc, param_rq.rqc, cqn, drop_rq->cq.mcq.cqn); 1533 1534 err = mlx5e_enable_rq(drop_rq, ¶m_rq); 1535 if (err) 1536 goto err_wq_destroy; 1537 1538 err = mlx5e_modify_rq(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 1539 if (err) 1540 goto err_disable_rq; 1541 1542 return (err); 1543 1544 err_disable_rq: 1545 mlx5e_disable_rq(drop_rq); 1546 err_wq_destroy: 1547 mlx5_wq_destroy(&drop_rq->wq_ctrl); 1548 err_close_cq: 1549 mlx5e_close_cq(&drop_rq->cq); 1550 err_done: 1551 return (err); 1552 } 1553 1554 static void 1555 mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq) 1556 { 1557 mlx5e_modify_rq(drop_rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 1558 mlx5e_disable_rq(drop_rq); 1559 mlx5_wq_destroy(&drop_rq->wq_ctrl); 1560 mlx5e_close_cq(&drop_rq->cq); 1561 } 1562 1563 void 1564 mlx5e_free_sq_db(struct mlx5e_sq *sq) 1565 { 1566 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1567 int x; 1568 1569 for (x = 0; x != wq_sz; x++) { 1570 if (sq->mbuf[x].mbuf != NULL) { 1571 bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map); 1572 m_freem(sq->mbuf[x].mbuf); 1573 } 1574 if (sq->mbuf[x].mst != NULL) { 1575 m_snd_tag_rele(sq->mbuf[x].mst); 1576 sq->mbuf[x].mst = NULL; 1577 } 1578 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 1579 } 1580 free(sq->mbuf, M_MLX5EN); 1581 } 1582 1583 int 1584 mlx5e_alloc_sq_db(struct mlx5e_sq *sq) 1585 { 1586 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1587 int err; 1588 int x; 1589 1590 sq->mbuf = malloc_domainset(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, 1591 mlx5_dev_domainset(sq->priv->mdev), M_WAITOK | M_ZERO); 1592 1593 /* Create DMA descriptor MAPs */ 1594 for (x = 0; x != wq_sz; x++) { 1595 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map); 1596 if (err != 0) { 1597 while (x--) 1598 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 1599 free(sq->mbuf, M_MLX5EN); 1600 return (err); 1601 } 1602 } 1603 return (0); 1604 } 1605 1606 static const char *mlx5e_sq_stats_desc[] = { 1607 MLX5E_SQ_STATS(MLX5E_STATS_DESC) 1608 }; 1609 1610 void 1611 mlx5e_update_sq_inline(struct mlx5e_sq *sq) 1612 { 1613 sq->max_inline = sq->priv->params.tx_max_inline; 1614 sq->min_inline_mode = sq->priv->params.tx_min_inline_mode; 1615 1616 /* 1617 * Check if trust state is DSCP or if inline mode is NONE which 1618 * indicates CX-5 or newer hardware. 1619 */ 1620 if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP || 1621 sq->min_inline_mode == MLX5_INLINE_MODE_NONE) { 1622 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert)) 1623 sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN; 1624 else 1625 sq->min_insert_caps = MLX5E_INSERT_NON_VLAN; 1626 } else { 1627 sq->min_insert_caps = 0; 1628 } 1629 } 1630 1631 static void 1632 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c) 1633 { 1634 int i; 1635 1636 for (i = 0; i != priv->num_tc; i++) { 1637 mtx_lock(&c->sq[i].lock); 1638 mlx5e_update_sq_inline(&c->sq[i]); 1639 mtx_unlock(&c->sq[i].lock); 1640 } 1641 } 1642 1643 void 1644 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv) 1645 { 1646 int i; 1647 1648 /* check if channels are closed */ 1649 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 1650 return; 1651 1652 for (i = 0; i < priv->params.num_channels; i++) 1653 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]); 1654 } 1655 1656 static int 1657 mlx5e_create_sq(struct mlx5e_channel *c, 1658 int tc, 1659 struct mlx5e_sq_param *param, 1660 struct mlx5e_sq *sq) 1661 { 1662 struct mlx5e_priv *priv = c->priv; 1663 struct mlx5_core_dev *mdev = priv->mdev; 1664 char buffer[16]; 1665 void *sqc = param->sqc; 1666 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq); 1667 int err; 1668 1669 /* Create DMA descriptor TAG */ 1670 if ((err = -bus_dma_tag_create( 1671 bus_get_dma_tag(mdev->pdev->dev.bsddev), 1672 1, /* any alignment */ 1673 0, /* no boundary */ 1674 BUS_SPACE_MAXADDR, /* lowaddr */ 1675 BUS_SPACE_MAXADDR, /* highaddr */ 1676 NULL, NULL, /* filter, filterarg */ 1677 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */ 1678 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */ 1679 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */ 1680 0, /* flags */ 1681 NULL, NULL, /* lockfunc, lockfuncarg */ 1682 &sq->dma_tag))) 1683 goto done; 1684 1685 sq->mkey_be = cpu_to_be32(priv->mr.key); 1686 sq->ifp = priv->ifp; 1687 sq->priv = priv; 1688 sq->tc = tc; 1689 1690 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, 1691 &sq->wq_ctrl); 1692 if (err) 1693 goto err_free_dma_tag; 1694 1695 sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; 1696 1697 err = mlx5e_alloc_sq_db(sq); 1698 if (err) 1699 goto err_sq_wq_destroy; 1700 1701 mlx5e_update_sq_inline(sq); 1702 1703 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc); 1704 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 1705 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM, 1706 sq->stats.arg); 1707 1708 return (0); 1709 1710 err_sq_wq_destroy: 1711 mlx5_wq_destroy(&sq->wq_ctrl); 1712 1713 err_free_dma_tag: 1714 bus_dma_tag_destroy(sq->dma_tag); 1715 done: 1716 return (err); 1717 } 1718 1719 static void 1720 mlx5e_destroy_sq(struct mlx5e_sq *sq) 1721 { 1722 /* destroy all sysctl nodes */ 1723 sysctl_ctx_free(&sq->stats.ctx); 1724 1725 mlx5e_free_sq_db(sq); 1726 mlx5_wq_destroy(&sq->wq_ctrl); 1727 bus_dma_tag_destroy(sq->dma_tag); 1728 } 1729 1730 int 1731 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param, 1732 const struct mlx5_sq_bfreg *bfreg, int tis_num) 1733 { 1734 void *in; 1735 void *sqc; 1736 void *wq; 1737 int inlen; 1738 int err; 1739 u8 ts_format; 1740 1741 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1742 sizeof(u64) * sq->wq_ctrl.buf.npages; 1743 in = mlx5_vzalloc(inlen); 1744 if (in == NULL) 1745 return (-ENOMEM); 1746 1747 sq->uar_map = bfreg->map; 1748 1749 ts_format = mlx5_get_sq_default_ts(sq->priv->mdev); 1750 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1751 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1752 1753 memcpy(sqc, param->sqc, sizeof(param->sqc)); 1754 1755 MLX5_SET(sqc, sqc, tis_num_0, tis_num); 1756 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn); 1757 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1758 MLX5_SET(sqc, sqc, ts_format, ts_format); 1759 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1760 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1761 MLX5_SET(sqc, sqc, allow_swp, 1); 1762 1763 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1764 MLX5_SET(wq, wq, uar_page, bfreg->index); 1765 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift - 1766 MLX5_ADAPTER_PAGE_SHIFT); 1767 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma); 1768 1769 mlx5_fill_page_array(&sq->wq_ctrl.buf, 1770 (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 1771 1772 err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn); 1773 1774 kvfree(in); 1775 1776 return (err); 1777 } 1778 1779 int 1780 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state) 1781 { 1782 void *in; 1783 void *sqc; 1784 int inlen; 1785 int err; 1786 1787 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 1788 in = mlx5_vzalloc(inlen); 1789 if (in == NULL) 1790 return (-ENOMEM); 1791 1792 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1793 1794 MLX5_SET(modify_sq_in, in, sqn, sq->sqn); 1795 MLX5_SET(modify_sq_in, in, sq_state, curr_state); 1796 MLX5_SET(sqc, sqc, state, next_state); 1797 1798 err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen); 1799 1800 kvfree(in); 1801 1802 return (err); 1803 } 1804 1805 void 1806 mlx5e_disable_sq(struct mlx5e_sq *sq) 1807 { 1808 1809 mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn); 1810 } 1811 1812 static int 1813 mlx5e_open_sq(struct mlx5e_channel *c, 1814 int tc, 1815 struct mlx5e_sq_param *param, 1816 struct mlx5e_sq *sq) 1817 { 1818 int err; 1819 1820 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact; 1821 1822 /* ensure the TX completion event factor is not zero */ 1823 if (sq->cev_factor == 0) 1824 sq->cev_factor = 1; 1825 1826 err = mlx5e_create_sq(c, tc, param, sq); 1827 if (err) 1828 return (err); 1829 1830 err = mlx5e_enable_sq(sq, param, &c->bfreg, c->priv->tisn[tc]); 1831 if (err) 1832 goto err_destroy_sq; 1833 1834 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY); 1835 if (err) 1836 goto err_disable_sq; 1837 1838 WRITE_ONCE(sq->running, 1); 1839 1840 return (0); 1841 1842 err_disable_sq: 1843 mlx5e_disable_sq(sq); 1844 err_destroy_sq: 1845 mlx5e_destroy_sq(sq); 1846 1847 return (err); 1848 } 1849 1850 static void 1851 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep) 1852 { 1853 /* fill up remainder with NOPs */ 1854 while (sq->cev_counter != 0) { 1855 while (!mlx5e_sq_has_room_for(sq, 1)) { 1856 if (can_sleep != 0) { 1857 mtx_unlock(&sq->lock); 1858 msleep(4); 1859 mtx_lock(&sq->lock); 1860 } else { 1861 goto done; 1862 } 1863 } 1864 /* send a single NOP */ 1865 mlx5e_send_nop(sq, 1); 1866 atomic_thread_fence_rel(); 1867 } 1868 done: 1869 mlx5e_tx_notify_hw(sq, false); 1870 } 1871 1872 void 1873 mlx5e_sq_cev_timeout(void *arg) 1874 { 1875 struct mlx5e_sq *sq = arg; 1876 1877 mtx_assert(&sq->lock, MA_OWNED); 1878 1879 /* check next state */ 1880 switch (sq->cev_next_state) { 1881 case MLX5E_CEV_STATE_SEND_NOPS: 1882 /* fill TX ring with NOPs, if any */ 1883 mlx5e_sq_send_nops_locked(sq, 0); 1884 1885 /* check if completed */ 1886 if (sq->cev_counter == 0) { 1887 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL; 1888 return; 1889 } 1890 break; 1891 default: 1892 /* send NOPs on next timeout */ 1893 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS; 1894 break; 1895 } 1896 1897 /* restart timer */ 1898 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq); 1899 } 1900 1901 void 1902 mlx5e_drain_sq(struct mlx5e_sq *sq) 1903 { 1904 int error; 1905 struct mlx5_core_dev *mdev= sq->priv->mdev; 1906 1907 /* 1908 * Check if already stopped. 1909 * 1910 * NOTE: Serialization of this function is managed by the 1911 * caller ensuring the priv's state lock is locked or in case 1912 * of rate limit support, a single thread manages drain and 1913 * resume of SQs. The "running" variable can therefore safely 1914 * be read without any locks. 1915 */ 1916 if (READ_ONCE(sq->running) == 0) 1917 return; 1918 1919 /* don't put more packets into the SQ */ 1920 WRITE_ONCE(sq->running, 0); 1921 1922 /* serialize access to DMA rings */ 1923 mtx_lock(&sq->lock); 1924 1925 /* teardown event factor timer, if any */ 1926 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS; 1927 callout_stop(&sq->cev_callout); 1928 1929 /* send dummy NOPs in order to flush the transmit ring */ 1930 mlx5e_sq_send_nops_locked(sq, 1); 1931 mtx_unlock(&sq->lock); 1932 1933 /* wait till SQ is empty or link is down */ 1934 mtx_lock(&sq->lock); 1935 while (sq->cc != sq->pc && 1936 (sq->priv->media_status_last & IFM_ACTIVE) != 0 && 1937 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR && 1938 pci_channel_offline(mdev->pdev) == 0) { 1939 mtx_unlock(&sq->lock); 1940 msleep(1); 1941 sq->cq.mcq.comp(&sq->cq.mcq, NULL); 1942 mtx_lock(&sq->lock); 1943 } 1944 mtx_unlock(&sq->lock); 1945 1946 /* error out remaining requests */ 1947 error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR); 1948 if (error != 0) { 1949 mlx5_en_err(sq->ifp, 1950 "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error); 1951 } 1952 1953 /* wait till SQ is empty */ 1954 mtx_lock(&sq->lock); 1955 while (sq->cc != sq->pc && 1956 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR && 1957 pci_channel_offline(mdev->pdev) == 0) { 1958 mtx_unlock(&sq->lock); 1959 msleep(1); 1960 sq->cq.mcq.comp(&sq->cq.mcq, NULL); 1961 mtx_lock(&sq->lock); 1962 } 1963 mtx_unlock(&sq->lock); 1964 } 1965 1966 static void 1967 mlx5e_close_sq_wait(struct mlx5e_sq *sq) 1968 { 1969 1970 mlx5e_drain_sq(sq); 1971 mlx5e_disable_sq(sq); 1972 mlx5e_destroy_sq(sq); 1973 } 1974 1975 static int 1976 mlx5e_create_cq(struct mlx5e_priv *priv, 1977 struct mlx5e_cq_param *param, 1978 struct mlx5e_cq *cq, 1979 mlx5e_cq_comp_t *comp, 1980 int eq_ix) 1981 { 1982 struct mlx5_core_dev *mdev = priv->mdev; 1983 struct mlx5_core_cq *mcq = &cq->mcq; 1984 int eqn_not_used; 1985 int irqn; 1986 int err; 1987 u32 i; 1988 1989 err = mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn); 1990 if (err) 1991 return (err); 1992 1993 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, 1994 &cq->wq_ctrl); 1995 if (err) 1996 return (err); 1997 1998 mcq->cqe_sz = 64; 1999 mcq->set_ci_db = cq->wq_ctrl.db.db; 2000 mcq->arm_db = cq->wq_ctrl.db.db + 1; 2001 *mcq->set_ci_db = 0; 2002 *mcq->arm_db = 0; 2003 mcq->vector = eq_ix; 2004 mcq->comp = comp; 2005 mcq->event = mlx5e_cq_error_event; 2006 mcq->irqn = irqn; 2007 2008 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { 2009 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); 2010 2011 cqe->op_own = 0xf1; 2012 } 2013 2014 cq->priv = priv; 2015 2016 return (0); 2017 } 2018 2019 static void 2020 mlx5e_destroy_cq(struct mlx5e_cq *cq) 2021 { 2022 mlx5_wq_destroy(&cq->wq_ctrl); 2023 } 2024 2025 static int 2026 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix) 2027 { 2028 struct mlx5_core_cq *mcq = &cq->mcq; 2029 u32 out[MLX5_ST_SZ_DW(create_cq_out)]; 2030 void *in; 2031 void *cqc; 2032 int inlen; 2033 int irqn_not_used; 2034 int eqn; 2035 int err; 2036 2037 inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 2038 sizeof(u64) * cq->wq_ctrl.buf.npages; 2039 in = mlx5_vzalloc(inlen); 2040 if (in == NULL) 2041 return (-ENOMEM); 2042 2043 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); 2044 2045 memcpy(cqc, param->cqc, sizeof(param->cqc)); 2046 2047 mlx5_fill_page_array(&cq->wq_ctrl.buf, 2048 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas)); 2049 2050 mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used); 2051 2052 MLX5_SET(cqc, cqc, c_eqn, eqn); 2053 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - 2054 MLX5_ADAPTER_PAGE_SHIFT); 2055 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); 2056 2057 err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen, out, sizeof(out)); 2058 2059 kvfree(in); 2060 2061 if (err) 2062 return (err); 2063 2064 mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock)); 2065 2066 return (0); 2067 } 2068 2069 static void 2070 mlx5e_disable_cq(struct mlx5e_cq *cq) 2071 { 2072 2073 mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq); 2074 } 2075 2076 int 2077 mlx5e_open_cq(struct mlx5e_priv *priv, 2078 struct mlx5e_cq_param *param, 2079 struct mlx5e_cq *cq, 2080 mlx5e_cq_comp_t *comp, 2081 int eq_ix) 2082 { 2083 int err; 2084 2085 err = mlx5e_create_cq(priv, param, cq, comp, eq_ix); 2086 if (err) 2087 return (err); 2088 2089 err = mlx5e_enable_cq(cq, param, eq_ix); 2090 if (err) 2091 goto err_destroy_cq; 2092 2093 return (0); 2094 2095 err_destroy_cq: 2096 mlx5e_destroy_cq(cq); 2097 2098 return (err); 2099 } 2100 2101 void 2102 mlx5e_close_cq(struct mlx5e_cq *cq) 2103 { 2104 mlx5e_disable_cq(cq); 2105 mlx5e_destroy_cq(cq); 2106 } 2107 2108 static int 2109 mlx5e_open_tx_cqs(struct mlx5e_channel *c, 2110 struct mlx5e_channel_param *cparam) 2111 { 2112 int err; 2113 int tc; 2114 2115 for (tc = 0; tc < c->priv->num_tc; tc++) { 2116 /* open completion queue */ 2117 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq, 2118 &mlx5e_tx_cq_comp, c->ix); 2119 if (err) 2120 goto err_close_tx_cqs; 2121 } 2122 return (0); 2123 2124 err_close_tx_cqs: 2125 for (tc--; tc >= 0; tc--) 2126 mlx5e_close_cq(&c->sq[tc].cq); 2127 2128 return (err); 2129 } 2130 2131 static void 2132 mlx5e_close_tx_cqs(struct mlx5e_channel *c) 2133 { 2134 int tc; 2135 2136 for (tc = 0; tc < c->priv->num_tc; tc++) 2137 mlx5e_close_cq(&c->sq[tc].cq); 2138 } 2139 2140 static int 2141 mlx5e_open_sqs(struct mlx5e_channel *c, 2142 struct mlx5e_channel_param *cparam) 2143 { 2144 int err; 2145 int tc; 2146 2147 for (tc = 0; tc < c->priv->num_tc; tc++) { 2148 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]); 2149 if (err) 2150 goto err_close_sqs; 2151 } 2152 2153 return (0); 2154 2155 err_close_sqs: 2156 for (tc--; tc >= 0; tc--) 2157 mlx5e_close_sq_wait(&c->sq[tc]); 2158 2159 return (err); 2160 } 2161 2162 static void 2163 mlx5e_close_sqs_wait(struct mlx5e_channel *c) 2164 { 2165 int tc; 2166 2167 for (tc = 0; tc < c->priv->num_tc; tc++) 2168 mlx5e_close_sq_wait(&c->sq[tc]); 2169 } 2170 2171 static void 2172 mlx5e_chan_static_init(struct mlx5e_priv *priv, struct mlx5e_channel *c, int ix) 2173 { 2174 int tc; 2175 2176 /* setup priv and channel number */ 2177 c->priv = priv; 2178 c->ix = ix; 2179 2180 /* setup send tag */ 2181 m_snd_tag_init(&c->tag, c->priv->ifp, &mlx5e_ul_snd_tag_sw); 2182 2183 init_completion(&c->completion); 2184 2185 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF); 2186 2187 callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0); 2188 2189 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) { 2190 struct mlx5e_sq *sq = c->sq + tc; 2191 2192 mtx_init(&sq->lock, "mlx5tx", 2193 MTX_NETWORK_LOCK " TX", MTX_DEF); 2194 mtx_init(&sq->comp_lock, "mlx5comp", 2195 MTX_NETWORK_LOCK " TX", MTX_DEF); 2196 2197 callout_init_mtx(&sq->cev_callout, &sq->lock, 0); 2198 } 2199 2200 mlx5e_iq_static_init(&c->iq); 2201 } 2202 2203 static void 2204 mlx5e_chan_wait_for_completion(struct mlx5e_channel *c) 2205 { 2206 2207 m_snd_tag_rele(&c->tag); 2208 wait_for_completion(&c->completion); 2209 } 2210 2211 static void 2212 mlx5e_priv_wait_for_completion(struct mlx5e_priv *priv, const uint32_t channels) 2213 { 2214 uint32_t x; 2215 2216 for (x = 0; x != channels; x++) 2217 mlx5e_chan_wait_for_completion(&priv->channel[x]); 2218 } 2219 2220 static void 2221 mlx5e_chan_static_destroy(struct mlx5e_channel *c) 2222 { 2223 int tc; 2224 2225 callout_drain(&c->rq.watchdog); 2226 2227 mtx_destroy(&c->rq.mtx); 2228 2229 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) { 2230 callout_drain(&c->sq[tc].cev_callout); 2231 mtx_destroy(&c->sq[tc].lock); 2232 mtx_destroy(&c->sq[tc].comp_lock); 2233 } 2234 2235 mlx5e_iq_static_destroy(&c->iq); 2236 } 2237 2238 static int 2239 mlx5e_open_channel(struct mlx5e_priv *priv, 2240 struct mlx5e_channel_param *cparam, 2241 struct mlx5e_channel *c) 2242 { 2243 struct epoch_tracker et; 2244 int i, err; 2245 2246 /* zero non-persistent data */ 2247 MLX5E_ZERO(&c->rq, mlx5e_rq_zero_start); 2248 for (i = 0; i != priv->num_tc; i++) 2249 MLX5E_ZERO(&c->sq[i], mlx5e_sq_zero_start); 2250 MLX5E_ZERO(&c->iq, mlx5e_iq_zero_start); 2251 2252 /* open transmit completion queue */ 2253 err = mlx5e_open_tx_cqs(c, cparam); 2254 if (err) 2255 goto err_free; 2256 2257 /* open receive completion queue */ 2258 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq, 2259 &mlx5e_rx_cq_comp, c->ix); 2260 if (err) 2261 goto err_close_tx_cqs; 2262 2263 err = mlx5e_open_sqs(c, cparam); 2264 if (err) 2265 goto err_close_rx_cq; 2266 2267 err = mlx5e_iq_open(c, &cparam->sq, &cparam->tx_cq, &c->iq); 2268 if (err) 2269 goto err_close_sqs; 2270 2271 err = mlx5e_open_rq(c, &cparam->rq, &c->rq); 2272 if (err) 2273 goto err_close_iq; 2274 2275 /* poll receive queue initially */ 2276 NET_EPOCH_ENTER(et); 2277 c->rq.cq.mcq.comp(&c->rq.cq.mcq, NULL); 2278 NET_EPOCH_EXIT(et); 2279 2280 return (0); 2281 2282 err_close_iq: 2283 mlx5e_iq_close(&c->iq); 2284 2285 err_close_sqs: 2286 mlx5e_close_sqs_wait(c); 2287 2288 err_close_rx_cq: 2289 mlx5e_close_cq(&c->rq.cq); 2290 2291 err_close_tx_cqs: 2292 mlx5e_close_tx_cqs(c); 2293 2294 err_free: 2295 return (err); 2296 } 2297 2298 static void 2299 mlx5e_close_channel(struct mlx5e_channel *c) 2300 { 2301 mlx5e_close_rq(&c->rq); 2302 } 2303 2304 static void 2305 mlx5e_close_channel_wait(struct mlx5e_channel *c) 2306 { 2307 mlx5e_close_rq_wait(&c->rq); 2308 mlx5e_iq_close(&c->iq); 2309 mlx5e_close_sqs_wait(c); 2310 mlx5e_close_tx_cqs(c); 2311 } 2312 2313 static int 2314 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs) 2315 { 2316 u32 r, n; 2317 2318 r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz : 2319 MLX5E_SW2MB_MTU(if_getmtu(priv->ifp)); 2320 if (r > MJUM16BYTES) 2321 return (-ENOMEM); 2322 2323 if (r > MJUM9BYTES) 2324 r = MJUM16BYTES; 2325 else if (r > MJUMPAGESIZE) 2326 r = MJUM9BYTES; 2327 else if (r > MCLBYTES) 2328 r = MJUMPAGESIZE; 2329 else 2330 r = MCLBYTES; 2331 2332 /* 2333 * n + 1 must be a power of two, because stride size must be. 2334 * Stride size is 16 * (n + 1), as the first segment is 2335 * control. 2336 */ 2337 n = roundup_pow_of_two(1 + howmany(r, MLX5E_MAX_RX_BYTES)) - 1; 2338 if (n > MLX5E_MAX_BUSDMA_RX_SEGS) 2339 return (-ENOMEM); 2340 2341 *wqe_sz = r; 2342 *nsegs = n; 2343 return (0); 2344 } 2345 2346 static void 2347 mlx5e_build_rq_param(struct mlx5e_priv *priv, 2348 struct mlx5e_rq_param *param) 2349 { 2350 void *rqc = param->rqc; 2351 void *wq = MLX5_ADDR_OF(rqc, rqc, wq); 2352 u32 wqe_sz, nsegs; 2353 2354 mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs); 2355 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); 2356 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 2357 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) + 2358 nsegs * sizeof(struct mlx5_wqe_data_seg))); 2359 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size); 2360 MLX5_SET(wq, wq, pd, priv->pdn); 2361 2362 param->wq.linear = 1; 2363 } 2364 2365 static void 2366 mlx5e_build_sq_param(struct mlx5e_priv *priv, 2367 struct mlx5e_sq_param *param) 2368 { 2369 void *sqc = param->sqc; 2370 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 2371 2372 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size); 2373 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 2374 MLX5_SET(wq, wq, pd, priv->pdn); 2375 2376 param->wq.linear = 1; 2377 } 2378 2379 static void 2380 mlx5e_build_common_cq_param(struct mlx5e_priv *priv, 2381 struct mlx5e_cq_param *param) 2382 { 2383 void *cqc = param->cqc; 2384 2385 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index); 2386 } 2387 2388 static void 2389 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr) 2390 { 2391 2392 *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE); 2393 2394 /* apply LRO restrictions */ 2395 if (priv->params.hw_lro_en && 2396 ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) { 2397 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO; 2398 } 2399 } 2400 2401 static void 2402 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, 2403 struct mlx5e_cq_param *param) 2404 { 2405 struct net_dim_cq_moder curr; 2406 void *cqc = param->cqc; 2407 2408 /* 2409 * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE 2410 * format is more beneficial for FreeBSD use case. 2411 * 2412 * Adding support for MLX5_CQE_FORMAT_CSUM will require changes 2413 * in mlx5e_decompress_cqe. 2414 */ 2415 if (priv->params.cqe_zipping_en) { 2416 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH); 2417 MLX5_SET(cqc, cqc, cqe_compression_en, 1); 2418 } 2419 2420 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size); 2421 2422 switch (priv->params.rx_cq_moderation_mode) { 2423 case 0: 2424 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec); 2425 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts); 2426 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2427 break; 2428 case 1: 2429 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec); 2430 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts); 2431 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2432 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2433 else 2434 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2435 break; 2436 case 2: 2437 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr); 2438 MLX5_SET(cqc, cqc, cq_period, curr.usec); 2439 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts); 2440 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2441 break; 2442 case 3: 2443 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr); 2444 MLX5_SET(cqc, cqc, cq_period, curr.usec); 2445 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts); 2446 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2447 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2448 else 2449 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2450 break; 2451 default: 2452 break; 2453 } 2454 2455 mlx5e_dim_build_cq_param(priv, param); 2456 2457 mlx5e_build_common_cq_param(priv, param); 2458 } 2459 2460 static void 2461 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv, 2462 struct mlx5e_cq_param *param) 2463 { 2464 void *cqc = param->cqc; 2465 2466 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size); 2467 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec); 2468 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts); 2469 2470 switch (priv->params.tx_cq_moderation_mode) { 2471 case 0: 2472 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2473 break; 2474 default: 2475 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2476 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2477 else 2478 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2479 break; 2480 } 2481 2482 mlx5e_build_common_cq_param(priv, param); 2483 } 2484 2485 static void 2486 mlx5e_build_channel_param(struct mlx5e_priv *priv, 2487 struct mlx5e_channel_param *cparam) 2488 { 2489 memset(cparam, 0, sizeof(*cparam)); 2490 2491 mlx5e_build_rq_param(priv, &cparam->rq); 2492 mlx5e_build_sq_param(priv, &cparam->sq); 2493 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq); 2494 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq); 2495 } 2496 2497 static int 2498 mlx5e_open_channels(struct mlx5e_priv *priv) 2499 { 2500 struct mlx5e_channel_param *cparam; 2501 int err; 2502 int i; 2503 2504 cparam = malloc(sizeof(*cparam), M_MLX5EN, M_WAITOK); 2505 2506 mlx5e_build_channel_param(priv, cparam); 2507 for (i = 0; i < priv->params.num_channels; i++) { 2508 err = mlx5e_open_channel(priv, cparam, &priv->channel[i]); 2509 if (err) 2510 goto err_close_channels; 2511 2512 /* Bind interrupt vectors, if any. */ 2513 if (priv->params_ethtool.irq_cpu_base > -1) { 2514 cpuset_t cpuset; 2515 int cpu; 2516 int irq; 2517 int eqn; 2518 int nirq; 2519 2520 err = mlx5_vector2eqn(priv->mdev, i, 2521 &eqn, &nirq); 2522 2523 /* error here is non-fatal */ 2524 if (err != 0) 2525 continue; 2526 2527 irq = priv->mdev->priv.msix_arr[nirq].vector; 2528 cpu = (unsigned)(priv->params_ethtool.irq_cpu_base + 2529 i * priv->params_ethtool.irq_cpu_stride) % (unsigned)mp_ncpus; 2530 2531 CPU_ZERO(&cpuset); 2532 CPU_SET(cpu, &cpuset); 2533 intr_setaffinity(irq, CPU_WHICH_INTRHANDLER, &cpuset); 2534 } 2535 } 2536 free(cparam, M_MLX5EN); 2537 return (0); 2538 2539 err_close_channels: 2540 while (i--) { 2541 mlx5e_close_channel(&priv->channel[i]); 2542 mlx5e_close_channel_wait(&priv->channel[i]); 2543 } 2544 free(cparam, M_MLX5EN); 2545 return (err); 2546 } 2547 2548 static void 2549 mlx5e_close_channels(struct mlx5e_priv *priv) 2550 { 2551 int i; 2552 2553 for (i = 0; i < priv->params.num_channels; i++) 2554 mlx5e_close_channel(&priv->channel[i]); 2555 for (i = 0; i < priv->params.num_channels; i++) 2556 mlx5e_close_channel_wait(&priv->channel[i]); 2557 } 2558 2559 static int 2560 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq) 2561 { 2562 2563 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) { 2564 uint8_t cq_mode; 2565 2566 switch (priv->params.tx_cq_moderation_mode) { 2567 case 0: 2568 case 2: 2569 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 2570 break; 2571 default: 2572 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE; 2573 break; 2574 } 2575 2576 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq, 2577 priv->params.tx_cq_moderation_usec, 2578 priv->params.tx_cq_moderation_pkts, 2579 cq_mode)); 2580 } 2581 2582 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq, 2583 priv->params.tx_cq_moderation_usec, 2584 priv->params.tx_cq_moderation_pkts)); 2585 } 2586 2587 static int 2588 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq) 2589 { 2590 2591 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) { 2592 uint8_t cq_mode; 2593 uint8_t dim_mode; 2594 int retval; 2595 2596 switch (priv->params.rx_cq_moderation_mode) { 2597 case 0: 2598 case 2: 2599 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 2600 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; 2601 break; 2602 default: 2603 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE; 2604 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE; 2605 break; 2606 } 2607 2608 /* tear down dynamic interrupt moderation */ 2609 mtx_lock(&rq->mtx); 2610 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 2611 mtx_unlock(&rq->mtx); 2612 2613 /* wait for dynamic interrupt moderation work task, if any */ 2614 cancel_work_sync(&rq->dim.work); 2615 2616 if (priv->params.rx_cq_moderation_mode >= 2) { 2617 struct net_dim_cq_moder curr; 2618 2619 mlx5e_get_default_profile(priv, dim_mode, &curr); 2620 2621 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq, 2622 curr.usec, curr.pkts, cq_mode); 2623 2624 /* set dynamic interrupt moderation mode and zero defaults */ 2625 mtx_lock(&rq->mtx); 2626 rq->dim.mode = dim_mode; 2627 rq->dim.state = 0; 2628 rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE; 2629 mtx_unlock(&rq->mtx); 2630 } else { 2631 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq, 2632 priv->params.rx_cq_moderation_usec, 2633 priv->params.rx_cq_moderation_pkts, 2634 cq_mode); 2635 } 2636 return (retval); 2637 } 2638 2639 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq, 2640 priv->params.rx_cq_moderation_usec, 2641 priv->params.rx_cq_moderation_pkts)); 2642 } 2643 2644 static int 2645 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c) 2646 { 2647 int err; 2648 int i; 2649 2650 err = mlx5e_refresh_rq_params(priv, &c->rq); 2651 if (err) 2652 goto done; 2653 2654 for (i = 0; i != priv->num_tc; i++) { 2655 err = mlx5e_refresh_sq_params(priv, &c->sq[i]); 2656 if (err) 2657 goto done; 2658 } 2659 done: 2660 return (err); 2661 } 2662 2663 int 2664 mlx5e_refresh_channel_params(struct mlx5e_priv *priv) 2665 { 2666 int i; 2667 2668 /* check if channels are closed */ 2669 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 2670 return (EINVAL); 2671 2672 for (i = 0; i < priv->params.num_channels; i++) { 2673 int err; 2674 2675 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]); 2676 if (err) 2677 return (err); 2678 } 2679 return (0); 2680 } 2681 2682 static int 2683 mlx5e_open_tis(struct mlx5e_priv *priv, int tc) 2684 { 2685 struct mlx5_core_dev *mdev = priv->mdev; 2686 u32 in[MLX5_ST_SZ_DW(create_tis_in)]; 2687 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 2688 2689 memset(in, 0, sizeof(in)); 2690 2691 MLX5_SET(tisc, tisc, prio, tc); 2692 MLX5_SET(tisc, tisc, transport_domain, priv->tdn); 2693 2694 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc])); 2695 } 2696 2697 static void 2698 mlx5e_close_tis(struct mlx5e_priv *priv, int tc) 2699 { 2700 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc], 0); 2701 } 2702 2703 static int 2704 mlx5e_open_tises(struct mlx5e_priv *priv) 2705 { 2706 int num_tc = priv->num_tc; 2707 int err; 2708 int tc; 2709 2710 for (tc = 0; tc < num_tc; tc++) { 2711 err = mlx5e_open_tis(priv, tc); 2712 if (err) 2713 goto err_close_tises; 2714 } 2715 2716 return (0); 2717 2718 err_close_tises: 2719 for (tc--; tc >= 0; tc--) 2720 mlx5e_close_tis(priv, tc); 2721 2722 return (err); 2723 } 2724 2725 static void 2726 mlx5e_close_tises(struct mlx5e_priv *priv) 2727 { 2728 int num_tc = priv->num_tc; 2729 int tc; 2730 2731 for (tc = 0; tc < num_tc; tc++) 2732 mlx5e_close_tis(priv, tc); 2733 } 2734 2735 static int 2736 mlx5e_open_default_rqt(struct mlx5e_priv *priv, u32 *prqtn, int sz) 2737 { 2738 u32 *in; 2739 void *rqtc; 2740 int inlen; 2741 int err; 2742 int i; 2743 2744 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 2745 in = mlx5_vzalloc(inlen); 2746 if (in == NULL) 2747 return (-ENOMEM); 2748 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 2749 2750 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 2751 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 2752 2753 for (i = 0; i != sz; i++) 2754 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn); 2755 2756 err = mlx5_core_create_rqt(priv->mdev, in, inlen, prqtn); 2757 kvfree(in); 2758 2759 return (err); 2760 } 2761 2762 static int 2763 mlx5e_open_rqts(struct mlx5e_priv *priv) 2764 { 2765 int err; 2766 int i; 2767 2768 err = mlx5e_open_default_rqt(priv, &priv->rqtn, 2769 1 << priv->params.rx_hash_log_tbl_sz); 2770 if (err) 2771 goto err_default; 2772 2773 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) { 2774 err = mlx5e_open_default_rqt(priv, &priv->channel[i].rqtn, 1); 2775 if (err) 2776 goto err_channel; 2777 } 2778 return (0); 2779 2780 err_channel: 2781 while (i--) 2782 mlx5_core_destroy_rqt(priv->mdev, priv->channel[i].rqtn, 0); 2783 2784 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn, 0); 2785 2786 err_default: 2787 return (err); 2788 } 2789 2790 static void 2791 mlx5e_close_rqts(struct mlx5e_priv *priv) 2792 { 2793 int i; 2794 2795 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) 2796 mlx5_core_destroy_rqt(priv->mdev, priv->channel[i].rqtn, 0); 2797 2798 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn, 0); 2799 } 2800 2801 static int 2802 mlx5e_activate_rqt(struct mlx5e_priv *priv) 2803 { 2804 u32 *in; 2805 void *rqtc; 2806 int inlen; 2807 int err; 2808 int sz; 2809 int i; 2810 2811 sz = 1 << priv->params.rx_hash_log_tbl_sz; 2812 2813 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz; 2814 in = mlx5_vzalloc(inlen); 2815 if (in == NULL) 2816 return (-ENOMEM); 2817 2818 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx); 2819 2820 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 2821 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1); 2822 2823 for (i = 0; i != sz; i++) { 2824 int ix; 2825 #ifdef RSS 2826 ix = rss_get_indirection_to_bucket(i); 2827 #else 2828 ix = i; 2829 #endif 2830 /* ensure we don't overflow */ 2831 ix %= priv->params.num_channels; 2832 2833 /* apply receive side scaling stride, if any */ 2834 ix -= ix % (int)priv->params.channels_rsss; 2835 2836 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn); 2837 } 2838 2839 err = mlx5_core_modify_rqt(priv->mdev, priv->rqtn, in, inlen); 2840 if (err) 2841 goto err_modify; 2842 2843 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32); 2844 2845 MLX5_SET(rqtc, rqtc, rqt_actual_size, 1); 2846 2847 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) { 2848 int ix; 2849 #ifdef RSS 2850 ix = rss_get_indirection_to_bucket(i); 2851 #else 2852 ix = i; 2853 #endif 2854 /* ensure we don't overflow */ 2855 ix %= priv->params.num_channels; 2856 2857 /* apply receive side scaling stride, if any */ 2858 ix -= ix % (int)priv->params.channels_rsss; 2859 2860 MLX5_SET(rqtc, rqtc, rq_num[0], priv->channel[ix].rq.rqn); 2861 2862 err = mlx5_core_modify_rqt(priv->mdev, priv->channel[i].rqtn, in, inlen); 2863 if (err) 2864 goto err_modify; 2865 } 2866 2867 err_modify: 2868 kvfree(in); 2869 return (err); 2870 } 2871 2872 static int 2873 mlx5e_deactivate_rqt(struct mlx5e_priv *priv) 2874 { 2875 u32 *in; 2876 void *rqtc; 2877 int inlen; 2878 int err; 2879 int sz; 2880 int i; 2881 2882 sz = 1 << priv->params.rx_hash_log_tbl_sz; 2883 2884 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz; 2885 in = mlx5_vzalloc(inlen); 2886 if (in == NULL) 2887 return (-ENOMEM); 2888 2889 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx); 2890 2891 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 2892 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1); 2893 2894 for (i = 0; i != sz; i++) 2895 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn); 2896 2897 err = mlx5_core_modify_rqt(priv->mdev, priv->rqtn, in, inlen); 2898 if (err) 2899 goto err_modify; 2900 2901 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32); 2902 2903 MLX5_SET(rqtc, rqtc, rqt_actual_size, 1); 2904 2905 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) { 2906 MLX5_SET(rqtc, rqtc, rq_num[0], priv->drop_rq.rqn); 2907 2908 err = mlx5_core_modify_rqt(priv->mdev, priv->channel[i].rqtn, in, inlen); 2909 if (err) 2910 goto err_modify; 2911 } 2912 2913 err_modify: 2914 kvfree(in); 2915 return (err); 2916 } 2917 2918 #define MLX5E_RSS_KEY_SIZE (10 * 4) /* bytes */ 2919 2920 static void 2921 mlx5e_get_rss_key(void *key_ptr) 2922 { 2923 #ifdef RSS 2924 rss_getkey(key_ptr); 2925 #else 2926 static const u32 rsskey[] = { 2927 cpu_to_be32(0xD181C62C), 2928 cpu_to_be32(0xF7F4DB5B), 2929 cpu_to_be32(0x1983A2FC), 2930 cpu_to_be32(0x943E1ADB), 2931 cpu_to_be32(0xD9389E6B), 2932 cpu_to_be32(0xD1039C2C), 2933 cpu_to_be32(0xA74499AD), 2934 cpu_to_be32(0x593D56D9), 2935 cpu_to_be32(0xF3253C06), 2936 cpu_to_be32(0x2ADC1FFC), 2937 }; 2938 CTASSERT(sizeof(rsskey) == MLX5E_RSS_KEY_SIZE); 2939 memcpy(key_ptr, rsskey, MLX5E_RSS_KEY_SIZE); 2940 #endif 2941 } 2942 2943 static void 2944 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt, bool inner_vxlan) 2945 { 2946 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 2947 void *hfsi = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); 2948 void *hfs = inner_vxlan ? hfsi : hfso; 2949 __be32 *hkey; 2950 2951 MLX5_SET(tirc, tirc, transport_domain, priv->tdn); 2952 2953 #define ROUGH_MAX_L2_L3_HDR_SZ 256 2954 2955 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2956 MLX5_HASH_FIELD_SEL_DST_IP) 2957 2958 #define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2959 MLX5_HASH_FIELD_SEL_DST_IP |\ 2960 MLX5_HASH_FIELD_SEL_L4_SPORT |\ 2961 MLX5_HASH_FIELD_SEL_L4_DPORT) 2962 2963 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2964 MLX5_HASH_FIELD_SEL_DST_IP |\ 2965 MLX5_HASH_FIELD_SEL_IPSEC_SPI) 2966 2967 if (priv->params.hw_lro_en) { 2968 MLX5_SET(tirc, tirc, lro_enable_mask, 2969 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | 2970 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO); 2971 MLX5_SET(tirc, tirc, lro_max_msg_sz, 2972 (priv->params.lro_wqe_sz - 2973 ROUGH_MAX_L2_L3_HDR_SZ) >> 8); 2974 /* TODO: add the option to choose timer value dynamically */ 2975 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, 2976 MLX5_CAP_ETH(priv->mdev, 2977 lro_timer_supported_periods[2])); 2978 } 2979 2980 if (inner_vxlan) 2981 MLX5_SET(tirc, tirc, tunneled_offload_en, 1); 2982 2983 /* 2984 * All packets must go through the indirection table, RQT, 2985 * because it is not possible to modify the RQN of the TIR 2986 * for direct dispatchment after it is created, typically 2987 * when the link goes up and down. 2988 */ 2989 MLX5_SET(tirc, tirc, disp_type, 2990 MLX5_TIRC_DISP_TYPE_INDIRECT); 2991 MLX5_SET(tirc, tirc, indirect_table, 2992 priv->rqtn); 2993 MLX5_SET(tirc, tirc, rx_hash_fn, 2994 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ); 2995 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 2996 2997 CTASSERT(MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key) >= 2998 MLX5E_RSS_KEY_SIZE); 2999 #ifdef RSS 3000 /* 3001 * The FreeBSD RSS implementation does currently not 3002 * support symmetric Toeplitz hashes: 3003 */ 3004 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0); 3005 #else 3006 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 3007 #endif 3008 mlx5e_get_rss_key(hkey); 3009 3010 switch (tt) { 3011 case MLX5E_TT_IPV4_TCP: 3012 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3013 MLX5_L3_PROT_TYPE_IPV4); 3014 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type, 3015 MLX5_L4_PROT_TYPE_TCP); 3016 #ifdef RSS 3017 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) { 3018 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3019 MLX5_HASH_IP); 3020 } else 3021 #endif 3022 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3023 MLX5_HASH_ALL); 3024 break; 3025 3026 case MLX5E_TT_IPV6_TCP: 3027 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3028 MLX5_L3_PROT_TYPE_IPV6); 3029 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type, 3030 MLX5_L4_PROT_TYPE_TCP); 3031 #ifdef RSS 3032 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) { 3033 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3034 MLX5_HASH_IP); 3035 } else 3036 #endif 3037 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3038 MLX5_HASH_ALL); 3039 break; 3040 3041 case MLX5E_TT_IPV4_UDP: 3042 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3043 MLX5_L3_PROT_TYPE_IPV4); 3044 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type, 3045 MLX5_L4_PROT_TYPE_UDP); 3046 #ifdef RSS 3047 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) { 3048 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3049 MLX5_HASH_IP); 3050 } else 3051 #endif 3052 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3053 MLX5_HASH_ALL); 3054 break; 3055 3056 case MLX5E_TT_IPV6_UDP: 3057 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3058 MLX5_L3_PROT_TYPE_IPV6); 3059 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type, 3060 MLX5_L4_PROT_TYPE_UDP); 3061 #ifdef RSS 3062 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) { 3063 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3064 MLX5_HASH_IP); 3065 } else 3066 #endif 3067 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3068 MLX5_HASH_ALL); 3069 break; 3070 3071 case MLX5E_TT_IPV4_IPSEC_AH: 3072 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3073 MLX5_L3_PROT_TYPE_IPV4); 3074 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3075 MLX5_HASH_IP_IPSEC_SPI); 3076 break; 3077 3078 case MLX5E_TT_IPV6_IPSEC_AH: 3079 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3080 MLX5_L3_PROT_TYPE_IPV6); 3081 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3082 MLX5_HASH_IP_IPSEC_SPI); 3083 break; 3084 3085 case MLX5E_TT_IPV4_IPSEC_ESP: 3086 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3087 MLX5_L3_PROT_TYPE_IPV4); 3088 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3089 MLX5_HASH_IP_IPSEC_SPI); 3090 break; 3091 3092 case MLX5E_TT_IPV6_IPSEC_ESP: 3093 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3094 MLX5_L3_PROT_TYPE_IPV6); 3095 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3096 MLX5_HASH_IP_IPSEC_SPI); 3097 break; 3098 3099 case MLX5E_TT_IPV4: 3100 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3101 MLX5_L3_PROT_TYPE_IPV4); 3102 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3103 MLX5_HASH_IP); 3104 break; 3105 3106 case MLX5E_TT_IPV6: 3107 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type, 3108 MLX5_L3_PROT_TYPE_IPV6); 3109 MLX5_SET(rx_hash_field_select, hfs, selected_fields, 3110 MLX5_HASH_IP); 3111 break; 3112 3113 default: 3114 break; 3115 } 3116 } 3117 3118 static int 3119 mlx5e_open_tir(struct mlx5e_priv *priv, int tt, bool inner_vxlan) 3120 { 3121 struct mlx5_core_dev *mdev = priv->mdev; 3122 u32 *in; 3123 void *tirc; 3124 int inlen; 3125 int err; 3126 3127 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 3128 in = mlx5_vzalloc(inlen); 3129 if (in == NULL) 3130 return (-ENOMEM); 3131 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context); 3132 3133 mlx5e_build_tir_ctx(priv, tirc, tt, inner_vxlan); 3134 3135 err = mlx5_core_create_tir(mdev, in, inlen, inner_vxlan ? 3136 &priv->tirn_inner_vxlan[tt] : &priv->tirn[tt]); 3137 3138 kvfree(in); 3139 3140 return (err); 3141 } 3142 3143 static void 3144 mlx5e_close_tir(struct mlx5e_priv *priv, int tt, bool inner_vxlan) 3145 { 3146 mlx5_core_destroy_tir(priv->mdev, inner_vxlan ? 3147 priv->tirn_inner_vxlan[tt] : priv->tirn[tt], 0); 3148 } 3149 3150 static int 3151 mlx5e_open_tirs(struct mlx5e_priv *priv) 3152 { 3153 int err; 3154 int i; 3155 3156 for (i = 0; i != 2 * MLX5E_NUM_TT; i++) { 3157 err = mlx5e_open_tir(priv, i / 2, (i % 2) ? true : false); 3158 if (err) 3159 goto err_close_tirs; 3160 } 3161 3162 return (0); 3163 3164 err_close_tirs: 3165 for (i--; i >= 0; i--) 3166 mlx5e_close_tir(priv, i / 2, (i % 2) ? true : false); 3167 3168 return (err); 3169 } 3170 3171 static void 3172 mlx5e_close_tirs(struct mlx5e_priv *priv) 3173 { 3174 int i; 3175 3176 for (i = 0; i != 2 * MLX5E_NUM_TT; i++) 3177 mlx5e_close_tir(priv, i / 2, (i % 2) ? true : false); 3178 } 3179 3180 /* 3181 * SW MTU does not include headers, 3182 * HW MTU includes all headers and checksums. 3183 */ 3184 static int 3185 mlx5e_set_dev_port_mtu(if_t ifp, int sw_mtu) 3186 { 3187 struct mlx5e_priv *priv = if_getsoftc(ifp); 3188 struct mlx5_core_dev *mdev = priv->mdev; 3189 int hw_mtu; 3190 int err; 3191 3192 hw_mtu = MLX5E_SW2HW_MTU(sw_mtu); 3193 3194 err = mlx5_set_port_mtu(mdev, hw_mtu); 3195 if (err) { 3196 mlx5_en_err(ifp, "mlx5_set_port_mtu failed setting %d, err=%d\n", 3197 sw_mtu, err); 3198 return (err); 3199 } 3200 3201 /* Update vport context MTU */ 3202 err = mlx5_set_vport_mtu(mdev, hw_mtu); 3203 if (err) { 3204 mlx5_en_err(ifp, 3205 "Failed updating vport context with MTU size, err=%d\n", 3206 err); 3207 } 3208 3209 if_setmtu(ifp, sw_mtu); 3210 3211 err = mlx5_query_vport_mtu(mdev, &hw_mtu); 3212 if (err || !hw_mtu) { 3213 /* fallback to port oper mtu */ 3214 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu); 3215 } 3216 if (err) { 3217 mlx5_en_err(ifp, 3218 "Query port MTU, after setting new MTU value, failed\n"); 3219 return (err); 3220 } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) { 3221 err = -E2BIG, 3222 mlx5_en_err(ifp, 3223 "Port MTU %d is smaller than ifp mtu %d\n", 3224 hw_mtu, sw_mtu); 3225 } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) { 3226 err = -EINVAL; 3227 mlx5_en_err(ifp, 3228 "Port MTU %d is bigger than ifp mtu %d\n", 3229 hw_mtu, sw_mtu); 3230 } 3231 priv->params_ethtool.hw_mtu = hw_mtu; 3232 3233 /* compute MSB */ 3234 while (hw_mtu & (hw_mtu - 1)) 3235 hw_mtu &= (hw_mtu - 1); 3236 priv->params_ethtool.hw_mtu_msb = hw_mtu; 3237 3238 return (err); 3239 } 3240 3241 int 3242 mlx5e_open_locked(if_t ifp) 3243 { 3244 struct mlx5e_priv *priv = if_getsoftc(ifp); 3245 int err; 3246 u16 set_id; 3247 3248 /* check if already opened */ 3249 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 3250 return (0); 3251 3252 #ifdef RSS 3253 if (rss_getnumbuckets() > priv->params.num_channels) { 3254 mlx5_en_info(ifp, 3255 "NOTE: There are more RSS buckets(%u) than channels(%u) available\n", 3256 rss_getnumbuckets(), priv->params.num_channels); 3257 } 3258 #endif 3259 err = mlx5e_open_tises(priv); 3260 if (err) { 3261 mlx5_en_err(ifp, "mlx5e_open_tises failed, %d\n", err); 3262 return (err); 3263 } 3264 err = mlx5_vport_alloc_q_counter(priv->mdev, 3265 MLX5_INTERFACE_PROTOCOL_ETH, &set_id); 3266 if (err) { 3267 mlx5_en_err(priv->ifp, 3268 "mlx5_vport_alloc_q_counter failed: %d\n", err); 3269 goto err_close_tises; 3270 } 3271 /* store counter set ID */ 3272 priv->counter_set_id = set_id; 3273 3274 err = mlx5e_open_channels(priv); 3275 if (err) { 3276 mlx5_en_err(ifp, 3277 "mlx5e_open_channels failed, %d\n", err); 3278 goto err_dalloc_q_counter; 3279 } 3280 err = mlx5e_activate_rqt(priv); 3281 if (err) { 3282 mlx5_en_err(ifp, "mlx5e_activate_rqt failed, %d\n", err); 3283 goto err_close_channels; 3284 } 3285 3286 set_bit(MLX5E_STATE_OPENED, &priv->state); 3287 3288 mlx5e_update_carrier(priv); 3289 3290 return (0); 3291 3292 err_close_channels: 3293 mlx5e_close_channels(priv); 3294 3295 err_dalloc_q_counter: 3296 mlx5_vport_dealloc_q_counter(priv->mdev, 3297 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 3298 3299 err_close_tises: 3300 mlx5e_close_tises(priv); 3301 3302 return (err); 3303 } 3304 3305 static void 3306 mlx5e_open(void *arg) 3307 { 3308 struct mlx5e_priv *priv = arg; 3309 3310 PRIV_LOCK(priv); 3311 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP)) 3312 mlx5_en_err(priv->ifp, 3313 "Setting port status to up failed\n"); 3314 3315 mlx5e_open_locked(priv->ifp); 3316 if_setdrvflagbits(priv->ifp, IFF_DRV_RUNNING, 0); 3317 PRIV_UNLOCK(priv); 3318 } 3319 3320 int 3321 mlx5e_close_locked(if_t ifp) 3322 { 3323 struct mlx5e_priv *priv = if_getsoftc(ifp); 3324 3325 /* check if already closed */ 3326 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3327 return (0); 3328 3329 clear_bit(MLX5E_STATE_OPENED, &priv->state); 3330 3331 if_link_state_change(priv->ifp, LINK_STATE_DOWN); 3332 3333 mlx5e_deactivate_rqt(priv); 3334 mlx5e_close_channels(priv); 3335 mlx5_vport_dealloc_q_counter(priv->mdev, 3336 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 3337 mlx5e_close_tises(priv); 3338 3339 return (0); 3340 } 3341 3342 static uint64_t 3343 mlx5e_get_counter(if_t ifp, ift_counter cnt) 3344 { 3345 struct mlx5e_priv *priv = if_getsoftc(ifp); 3346 u64 retval; 3347 3348 /* PRIV_LOCK(priv); XXX not allowed */ 3349 switch (cnt) { 3350 case IFCOUNTER_IPACKETS: 3351 retval = priv->stats.vport.rx_packets; 3352 break; 3353 case IFCOUNTER_IERRORS: 3354 retval = priv->stats.pport.in_range_len_errors + 3355 priv->stats.pport.out_of_range_len + 3356 priv->stats.pport.too_long_errors + 3357 priv->stats.pport.check_seq_err + 3358 priv->stats.pport.alignment_err; 3359 break; 3360 case IFCOUNTER_IQDROPS: 3361 retval = priv->stats.vport.rx_out_of_buffer; 3362 break; 3363 case IFCOUNTER_OPACKETS: 3364 retval = priv->stats.vport.tx_packets; 3365 break; 3366 case IFCOUNTER_OERRORS: 3367 retval = priv->stats.port_stats_debug.out_discards; 3368 break; 3369 case IFCOUNTER_IBYTES: 3370 retval = priv->stats.vport.rx_bytes; 3371 break; 3372 case IFCOUNTER_OBYTES: 3373 retval = priv->stats.vport.tx_bytes; 3374 break; 3375 case IFCOUNTER_IMCASTS: 3376 retval = priv->stats.vport.rx_multicast_packets; 3377 break; 3378 case IFCOUNTER_OMCASTS: 3379 retval = priv->stats.vport.tx_multicast_packets; 3380 break; 3381 case IFCOUNTER_OQDROPS: 3382 retval = priv->stats.vport.tx_queue_dropped; 3383 break; 3384 case IFCOUNTER_COLLISIONS: 3385 retval = priv->stats.pport.collisions; 3386 break; 3387 default: 3388 retval = if_get_counter_default(ifp, cnt); 3389 break; 3390 } 3391 /* PRIV_UNLOCK(priv); XXX not allowed */ 3392 return (retval); 3393 } 3394 3395 static void 3396 mlx5e_set_rx_mode(if_t ifp) 3397 { 3398 struct mlx5e_priv *priv = if_getsoftc(ifp); 3399 3400 queue_work(priv->wq, &priv->set_rx_mode_work); 3401 } 3402 3403 static int 3404 mlx5e_ioctl(if_t ifp, u_long command, caddr_t data) 3405 { 3406 struct mlx5e_priv *priv; 3407 struct ifreq *ifr; 3408 struct ifdownreason *ifdr; 3409 struct ifi2creq i2c; 3410 struct ifrsskey *ifrk; 3411 struct ifrsshash *ifrh; 3412 struct siocsifcapnv_driver_data *drv_ioctl_data, drv_ioctl_data_d; 3413 int error = 0; 3414 int mask; 3415 int size_read = 0; 3416 int module_status; 3417 int module_num; 3418 int max_mtu; 3419 uint8_t read_addr; 3420 3421 priv = if_getsoftc(ifp); 3422 3423 /* check if detaching */ 3424 if (priv == NULL || priv->gone != 0) 3425 return (ENXIO); 3426 3427 switch (command) { 3428 case SIOCSIFMTU: 3429 ifr = (struct ifreq *)data; 3430 3431 PRIV_LOCK(priv); 3432 mlx5_query_port_max_mtu(priv->mdev, &max_mtu); 3433 3434 if (ifr->ifr_mtu >= MLX5E_MTU_MIN && 3435 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) { 3436 int was_opened; 3437 3438 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 3439 if (was_opened) 3440 mlx5e_close_locked(ifp); 3441 3442 /* set new MTU */ 3443 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu); 3444 3445 if (was_opened) 3446 mlx5e_open_locked(ifp); 3447 } else { 3448 error = EINVAL; 3449 mlx5_en_err(ifp, 3450 "Invalid MTU value. Min val: %d, Max val: %d\n", 3451 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu)); 3452 } 3453 PRIV_UNLOCK(priv); 3454 break; 3455 case SIOCSIFFLAGS: 3456 if ((if_getflags(ifp) & IFF_UP) && 3457 (if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 3458 mlx5e_set_rx_mode(ifp); 3459 break; 3460 } 3461 PRIV_LOCK(priv); 3462 if (if_getflags(ifp) & IFF_UP) { 3463 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 3464 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3465 mlx5e_open_locked(ifp); 3466 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 3467 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP); 3468 } 3469 } else { 3470 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3471 mlx5_set_port_status(priv->mdev, 3472 MLX5_PORT_DOWN); 3473 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 3474 mlx5e_close_locked(ifp); 3475 mlx5e_update_carrier(priv); 3476 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3477 } 3478 } 3479 PRIV_UNLOCK(priv); 3480 break; 3481 case SIOCADDMULTI: 3482 case SIOCDELMULTI: 3483 mlx5e_set_rx_mode(ifp); 3484 break; 3485 case SIOCSIFMEDIA: 3486 case SIOCGIFMEDIA: 3487 case SIOCGIFXMEDIA: 3488 ifr = (struct ifreq *)data; 3489 error = ifmedia_ioctl(ifp, ifr, &priv->media, command); 3490 break; 3491 case SIOCGIFCAPNV: 3492 error = 0; 3493 break; 3494 case SIOCSIFCAP: 3495 ifr = (struct ifreq *)data; 3496 drv_ioctl_data = &drv_ioctl_data_d; 3497 drv_ioctl_data->reqcap = ifr->ifr_reqcap; 3498 PRIV_LOCK(priv); 3499 drv_ioctl_data->reqcap2 = if_getcapenable2(ifp); 3500 drv_ioctl_data->nvcap = NULL; 3501 goto siocsifcap_driver; 3502 case SIOCSIFCAPNV: 3503 drv_ioctl_data = (struct siocsifcapnv_driver_data *)data; 3504 PRIV_LOCK(priv); 3505 siocsifcap_driver: 3506 mask = drv_ioctl_data->reqcap ^ if_getcapenable(ifp); 3507 3508 if (mask & IFCAP_TXCSUM) { 3509 if_togglecapenable(ifp, IFCAP_TXCSUM); 3510 if_togglehwassist(ifp, (CSUM_TCP | CSUM_UDP | CSUM_IP)); 3511 3512 if (IFCAP_TSO4 & if_getcapenable(ifp) && 3513 !(IFCAP_TXCSUM & if_getcapenable(ifp))) { 3514 mask &= ~IFCAP_TSO4; 3515 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 3516 if_sethwassistbits(ifp, 0, CSUM_IP_TSO); 3517 mlx5_en_err(ifp, 3518 "tso4 disabled due to -txcsum.\n"); 3519 } 3520 } 3521 if (mask & IFCAP_TXCSUM_IPV6) { 3522 if_togglecapenable(ifp, IFCAP_TXCSUM_IPV6); 3523 if_togglehwassist(ifp, (CSUM_UDP_IPV6 | CSUM_TCP_IPV6)); 3524 3525 if (IFCAP_TSO6 & if_getcapenable(ifp) && 3526 !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) { 3527 mask &= ~IFCAP_TSO6; 3528 if_setcapenablebit(ifp, 0, IFCAP_TSO6); 3529 if_sethwassistbits(ifp, 0, CSUM_IP6_TSO); 3530 mlx5_en_err(ifp, 3531 "tso6 disabled due to -txcsum6.\n"); 3532 } 3533 } 3534 if (mask & IFCAP_MEXTPG) 3535 if_togglecapenable(ifp, IFCAP_MEXTPG); 3536 if (mask & IFCAP_TXTLS4) 3537 if_togglecapenable(ifp, IFCAP_TXTLS4); 3538 if (mask & IFCAP_TXTLS6) 3539 if_togglecapenable(ifp, IFCAP_TXTLS6); 3540 #ifdef RATELIMIT 3541 if (mask & IFCAP_TXTLS_RTLMT) 3542 if_togglecapenable(ifp, IFCAP_TXTLS_RTLMT); 3543 #endif 3544 if (mask & IFCAP_RXCSUM) 3545 if_togglecapenable(ifp, IFCAP_RXCSUM); 3546 if (mask & IFCAP_RXCSUM_IPV6) 3547 if_togglecapenable(ifp, IFCAP_RXCSUM_IPV6); 3548 if (mask & IFCAP_TSO4) { 3549 if (!(IFCAP_TSO4 & if_getcapenable(ifp)) && 3550 !(IFCAP_TXCSUM & if_getcapenable(ifp))) { 3551 mlx5_en_err(ifp, "enable txcsum first.\n"); 3552 error = EAGAIN; 3553 goto out; 3554 } 3555 if_togglecapenable(ifp, IFCAP_TSO4); 3556 if_togglehwassist(ifp, CSUM_IP_TSO); 3557 } 3558 if (mask & IFCAP_TSO6) { 3559 if (!(IFCAP_TSO6 & if_getcapenable(ifp)) && 3560 !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) { 3561 mlx5_en_err(ifp, "enable txcsum6 first.\n"); 3562 error = EAGAIN; 3563 goto out; 3564 } 3565 if_togglecapenable(ifp, IFCAP_TSO6); 3566 if_togglehwassist(ifp, CSUM_IP6_TSO); 3567 } 3568 if (mask & IFCAP_VLAN_HWTSO) 3569 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 3570 if (mask & IFCAP_VLAN_HWFILTER) { 3571 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 3572 mlx5e_disable_vlan_filter(priv); 3573 else 3574 mlx5e_enable_vlan_filter(priv); 3575 3576 if_togglecapenable(ifp, IFCAP_VLAN_HWFILTER); 3577 } 3578 if (mask & IFCAP_VLAN_HWTAGGING) 3579 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 3580 if (mask & IFCAP_WOL_MAGIC) 3581 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 3582 if (mask & IFCAP_VXLAN_HWCSUM) { 3583 const bool was_enabled = 3584 (if_getcapenable(ifp) & IFCAP_VXLAN_HWCSUM) != 0; 3585 if (was_enabled) 3586 mlx5e_del_all_vxlan_rules(priv); 3587 if_togglecapenable(ifp, IFCAP_VXLAN_HWCSUM); 3588 if_togglehwassist(ifp, CSUM_INNER_IP | CSUM_INNER_IP_UDP | 3589 CSUM_INNER_IP_TCP | CSUM_INNER_IP6_UDP | 3590 CSUM_INNER_IP6_TCP); 3591 if (!was_enabled) { 3592 int err = mlx5e_add_all_vxlan_rules(priv); 3593 if (err != 0) { 3594 mlx5_en_err(ifp, 3595 "mlx5e_add_all_vxlan_rules() failed, %d (ignored)\n", err); 3596 } 3597 } 3598 } 3599 if (mask & IFCAP_VXLAN_HWTSO) { 3600 if_togglecapenable(ifp, IFCAP_VXLAN_HWTSO); 3601 if_togglehwassist(ifp, CSUM_INNER_IP_TSO | 3602 CSUM_INNER_IP6_TSO); 3603 } 3604 3605 VLAN_CAPABILITIES(ifp); 3606 /* turn off LRO means also turn of HW LRO - if it's on */ 3607 if (mask & IFCAP_LRO) { 3608 int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 3609 bool need_restart = false; 3610 3611 if_togglecapenable(ifp, IFCAP_LRO); 3612 3613 /* figure out if updating HW LRO is needed */ 3614 if (!(if_getcapenable(ifp) & IFCAP_LRO)) { 3615 if (priv->params.hw_lro_en) { 3616 priv->params.hw_lro_en = false; 3617 need_restart = true; 3618 } 3619 } else { 3620 if (priv->params.hw_lro_en == false && 3621 priv->params_ethtool.hw_lro != 0) { 3622 priv->params.hw_lro_en = true; 3623 need_restart = true; 3624 } 3625 } 3626 if (was_opened && need_restart) { 3627 mlx5e_close_locked(ifp); 3628 mlx5e_open_locked(ifp); 3629 } 3630 } 3631 if (mask & IFCAP_HWRXTSTMP) { 3632 if_togglecapenable(ifp, IFCAP_HWRXTSTMP); 3633 if (if_getcapenable(ifp) & IFCAP_HWRXTSTMP) { 3634 if (priv->clbr_done == 0) 3635 mlx5e_reset_calibration_callout(priv); 3636 } else { 3637 callout_drain(&priv->tstmp_clbr); 3638 priv->clbr_done = 0; 3639 } 3640 } 3641 mask = drv_ioctl_data->reqcap2 ^ if_getcapenable2(ifp); 3642 if ((mask & IFCAP2_BIT(IFCAP2_RXTLS4)) != 0) 3643 if_togglecapenable2(ifp, IFCAP2_BIT(IFCAP2_RXTLS4)); 3644 if ((mask & IFCAP2_BIT(IFCAP2_RXTLS6)) != 0) 3645 if_togglecapenable2(ifp, IFCAP2_BIT(IFCAP2_RXTLS6)); 3646 #ifdef IPSEC_OFFLOAD 3647 if ((mask & IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD)) != 0) { 3648 bool was_enabled = (if_getcapenable2(ifp) & 3649 IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD)) != 0; 3650 mlx5e_close_locked(ifp); 3651 if (was_enabled) 3652 ipsec_accel_on_ifdown(priv->ifp); 3653 if_togglecapenable2(ifp, 3654 IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD)); 3655 mlx5e_open_locked(ifp); 3656 } 3657 #endif 3658 out: 3659 PRIV_UNLOCK(priv); 3660 break; 3661 3662 case SIOCGI2C: 3663 ifr = (struct ifreq *)data; 3664 3665 /* 3666 * Copy from the user-space address ifr_data to the 3667 * kernel-space address i2c 3668 */ 3669 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 3670 if (error) 3671 break; 3672 3673 if (i2c.len > sizeof(i2c.data)) { 3674 error = EINVAL; 3675 break; 3676 } 3677 3678 PRIV_LOCK(priv); 3679 /* Get module_num which is required for the query_eeprom */ 3680 error = mlx5_query_module_num(priv->mdev, &module_num); 3681 if (error) { 3682 mlx5_en_err(ifp, 3683 "Query module num failed, eeprom reading is not supported\n"); 3684 error = EINVAL; 3685 goto err_i2c; 3686 } 3687 /* Check if module is present before doing an access */ 3688 module_status = mlx5_query_module_status(priv->mdev, module_num); 3689 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED) { 3690 if (bootverbose) 3691 mlx5_en_err(ifp, 3692 "Query module %d status: not plugged (%d), " 3693 "eeprom reading is not supported\n", 3694 module_num, module_status); 3695 error = EINVAL; 3696 goto err_i2c; 3697 } 3698 /* 3699 * Currently 0XA0 and 0xA2 are the only addresses permitted. 3700 * The internal conversion is as follows: 3701 */ 3702 if (i2c.dev_addr == 0xA0) 3703 read_addr = MLX5_I2C_ADDR_LOW; 3704 else if (i2c.dev_addr == 0xA2) 3705 read_addr = MLX5_I2C_ADDR_HIGH; 3706 else { 3707 mlx5_en_err(ifp, 3708 "Query eeprom failed, Invalid Address: %X\n", 3709 i2c.dev_addr); 3710 error = EINVAL; 3711 goto err_i2c; 3712 } 3713 error = mlx5_query_eeprom(priv->mdev, 3714 read_addr, MLX5_EEPROM_LOW_PAGE, 3715 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num, 3716 (uint32_t *)i2c.data, &size_read); 3717 if (error) { 3718 mlx5_en_err(ifp, 3719 "Query eeprom failed, eeprom reading is not supported\n"); 3720 error = EINVAL; 3721 goto err_i2c; 3722 } 3723 3724 if (i2c.len > MLX5_EEPROM_MAX_BYTES) { 3725 error = mlx5_query_eeprom(priv->mdev, 3726 read_addr, MLX5_EEPROM_LOW_PAGE, 3727 (uint32_t)(i2c.offset + size_read), 3728 (uint32_t)(i2c.len - size_read), module_num, 3729 (uint32_t *)(i2c.data + size_read), &size_read); 3730 } 3731 if (error) { 3732 mlx5_en_err(ifp, 3733 "Query eeprom failed, eeprom reading is not supported\n"); 3734 error = EINVAL; 3735 goto err_i2c; 3736 } 3737 3738 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 3739 err_i2c: 3740 PRIV_UNLOCK(priv); 3741 break; 3742 case SIOCGIFDOWNREASON: 3743 ifdr = (struct ifdownreason *)data; 3744 bzero(ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg)); 3745 PRIV_LOCK(priv); 3746 error = -mlx5_query_pddr_troubleshooting_info(priv->mdev, NULL, 3747 ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg)); 3748 PRIV_UNLOCK(priv); 3749 if (error == 0) 3750 ifdr->ifdr_reason = IFDR_REASON_MSG; 3751 break; 3752 3753 case SIOCGIFRSSKEY: 3754 ifrk = (struct ifrsskey *)data; 3755 ifrk->ifrk_func = RSS_FUNC_TOEPLITZ; 3756 ifrk->ifrk_keylen = MLX5E_RSS_KEY_SIZE; 3757 CTASSERT(sizeof(ifrk->ifrk_key) >= MLX5E_RSS_KEY_SIZE); 3758 mlx5e_get_rss_key(ifrk->ifrk_key); 3759 break; 3760 3761 case SIOCGIFRSSHASH: 3762 ifrh = (struct ifrsshash *)data; 3763 ifrh->ifrh_func = RSS_FUNC_TOEPLITZ; 3764 ifrh->ifrh_types = 3765 RSS_TYPE_IPV4 | 3766 RSS_TYPE_TCP_IPV4 | 3767 RSS_TYPE_UDP_IPV4 | 3768 RSS_TYPE_IPV6 | 3769 RSS_TYPE_TCP_IPV6 | 3770 RSS_TYPE_UDP_IPV6; 3771 break; 3772 3773 default: 3774 error = ether_ioctl(ifp, command, data); 3775 break; 3776 } 3777 return (error); 3778 } 3779 3780 static int 3781 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev) 3782 { 3783 /* 3784 * TODO: uncoment once FW really sets all these bits if 3785 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap || 3786 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap || 3787 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return 3788 * -ENOTSUPP; 3789 */ 3790 3791 /* TODO: add more must-to-have features */ 3792 3793 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) 3794 return (-ENODEV); 3795 3796 return (0); 3797 } 3798 3799 static u16 3800 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev) 3801 { 3802 const int min_size = ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN; 3803 const int max_size = MLX5E_MAX_TX_INLINE; 3804 const int bf_buf_size = 3805 ((1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U) - 3806 (sizeof(struct mlx5e_tx_wqe) - 2); 3807 3808 /* verify against driver limits */ 3809 if (bf_buf_size > max_size) 3810 return (max_size); 3811 else if (bf_buf_size < min_size) 3812 return (min_size); 3813 else 3814 return (bf_buf_size); 3815 } 3816 3817 static int 3818 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev, 3819 struct mlx5e_priv *priv, 3820 int num_comp_vectors) 3821 { 3822 int err; 3823 3824 /* 3825 * TODO: Consider link speed for setting "log_sq_size", 3826 * "log_rq_size" and "cq_moderation_xxx": 3827 */ 3828 priv->params.log_sq_size = 3829 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; 3830 priv->params.log_rq_size = 3831 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; 3832 priv->params.rx_cq_moderation_usec = 3833 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 3834 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE : 3835 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; 3836 priv->params.rx_cq_moderation_mode = 3837 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0; 3838 priv->params.rx_cq_moderation_pkts = 3839 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; 3840 priv->params.tx_cq_moderation_usec = 3841 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; 3842 priv->params.tx_cq_moderation_pkts = 3843 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; 3844 priv->params.rx_hash_log_tbl_sz = 3845 (order_base_2(num_comp_vectors) > 3846 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ? 3847 order_base_2(num_comp_vectors) : 3848 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ; 3849 priv->params.num_tc = 1; 3850 priv->params.default_vlan_prio = 0; 3851 priv->counter_set_id = -1; 3852 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev); 3853 3854 err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode); 3855 if (err) 3856 return (err); 3857 3858 /* 3859 * hw lro is currently defaulted to off. when it won't anymore we 3860 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)" 3861 */ 3862 priv->params.hw_lro_en = false; 3863 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; 3864 3865 /* 3866 * CQE zipping is off, because the per-packet 32-bit Toeplitz hash 3867 * is then not supported. The 32-bit Toeplitz hash is needed to 3868 * correctly demultiplex incoming traffic into the expected 3869 * network queues. 3870 */ 3871 priv->params.cqe_zipping_en = false; 3872 3873 priv->mdev = mdev; 3874 priv->params.num_channels = num_comp_vectors; 3875 priv->params.channels_rsss = 1; 3876 priv->order_base_2_num_channels = order_base_2(num_comp_vectors); 3877 priv->queue_mapping_channel_mask = 3878 roundup_pow_of_two(num_comp_vectors) - 1; 3879 priv->num_tc = priv->params.num_tc; 3880 priv->default_vlan_prio = priv->params.default_vlan_prio; 3881 3882 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work); 3883 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); 3884 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); 3885 3886 return (0); 3887 } 3888 3889 static void 3890 mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc) 3891 { 3892 bool ro_pci_enable = 3893 pci_get_relaxed_ordering_enabled(mdev->pdev->dev.bsddev); 3894 bool ro_write = MLX5_CAP_GEN(mdev, relaxed_ordering_write); 3895 bool ro_read = MLX5_CAP_GEN(mdev, relaxed_ordering_read); 3896 3897 MLX5_SET(mkc, mkc, relaxed_ordering_read, ro_pci_enable && ro_read); 3898 MLX5_SET(mkc, mkc, relaxed_ordering_write, ro_pci_enable && ro_write); 3899 } 3900 3901 static int 3902 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn, 3903 struct mlx5_core_mkey *mkey) 3904 { 3905 if_t ifp = priv->ifp; 3906 struct mlx5_core_dev *mdev = priv->mdev; 3907 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 3908 void *mkc; 3909 u32 *in; 3910 int err; 3911 3912 in = mlx5_vzalloc(inlen); 3913 if (in == NULL) { 3914 mlx5_en_err(ifp, "failed to allocate inbox\n"); 3915 return (-ENOMEM); 3916 } 3917 3918 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 3919 MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA); 3920 MLX5_SET(mkc, mkc, umr_en, 1); /* used by HW TLS */ 3921 MLX5_SET(mkc, mkc, lw, 1); 3922 MLX5_SET(mkc, mkc, lr, 1); 3923 mlx5e_mkey_set_relaxed_ordering(mdev, mkc); 3924 MLX5_SET(mkc, mkc, pd, pdn); 3925 MLX5_SET(mkc, mkc, length64, 1); 3926 MLX5_SET(mkc, mkc, qpn, 0xffffff); 3927 3928 err = mlx5_core_create_mkey(mdev, mkey, in, inlen); 3929 if (err) 3930 mlx5_en_err(ifp, "mlx5_core_create_mkey failed, %d\n", 3931 err); 3932 3933 kvfree(in); 3934 return (err); 3935 } 3936 3937 static const char *mlx5e_vport_stats_desc[] = { 3938 MLX5E_VPORT_STATS(MLX5E_STATS_DESC) 3939 }; 3940 3941 static const char *mlx5e_pport_stats_desc[] = { 3942 MLX5E_PPORT_STATS(MLX5E_STATS_DESC) 3943 }; 3944 3945 static int 3946 mlx5e_priv_static_init(struct mlx5e_priv *priv, struct mlx5_core_dev *mdev, 3947 const uint32_t channels) 3948 { 3949 uint32_t x; 3950 int err; 3951 3952 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF); 3953 sx_init(&priv->state_lock, "mlx5state"); 3954 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0); 3955 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock); 3956 for (x = 0; x != channels; x++) 3957 mlx5e_chan_static_init(priv, &priv->channel[x], x); 3958 3959 for (x = 0; x != channels; x++) { 3960 err = mlx5_alloc_bfreg(mdev, &priv->channel[x].bfreg, false, false); 3961 if (err) 3962 goto err_alloc_bfreg; 3963 } 3964 return (0); 3965 3966 err_alloc_bfreg: 3967 while (x--) 3968 mlx5_free_bfreg(mdev, &priv->channel[x].bfreg); 3969 3970 for (x = 0; x != channels; x++) 3971 mlx5e_chan_static_destroy(&priv->channel[x]); 3972 callout_drain(&priv->watchdog); 3973 mtx_destroy(&priv->async_events_mtx); 3974 sx_destroy(&priv->state_lock); 3975 return (err); 3976 } 3977 3978 static void 3979 mlx5e_priv_static_destroy(struct mlx5e_priv *priv, struct mlx5_core_dev *mdev, 3980 const uint32_t channels) 3981 { 3982 uint32_t x; 3983 3984 for (x = 0; x != channels; x++) 3985 mlx5_free_bfreg(mdev, &priv->channel[x].bfreg); 3986 for (x = 0; x != channels; x++) 3987 mlx5e_chan_static_destroy(&priv->channel[x]); 3988 callout_drain(&priv->watchdog); 3989 mtx_destroy(&priv->async_events_mtx); 3990 sx_destroy(&priv->state_lock); 3991 } 3992 3993 static int 3994 sysctl_firmware(SYSCTL_HANDLER_ARGS) 3995 { 3996 /* 3997 * %d.%d%.d the string format. 3998 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536. 3999 * We need at most 5 chars to store that. 4000 * It also has: two "." and NULL at the end, which means we need 18 4001 * (5*3 + 3) chars at most. 4002 */ 4003 char fw[18]; 4004 struct mlx5e_priv *priv = arg1; 4005 int error; 4006 4007 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev), 4008 fw_rev_sub(priv->mdev)); 4009 error = sysctl_handle_string(oidp, fw, sizeof(fw), req); 4010 return (error); 4011 } 4012 4013 static void 4014 mlx5e_disable_tx_dma(struct mlx5e_channel *ch) 4015 { 4016 int i; 4017 4018 for (i = 0; i < ch->priv->num_tc; i++) 4019 mlx5e_drain_sq(&ch->sq[i]); 4020 } 4021 4022 static void 4023 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq) 4024 { 4025 4026 sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP); 4027 sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8); 4028 mlx5e_tx_notify_hw(sq, true); 4029 } 4030 4031 void 4032 mlx5e_resume_sq(struct mlx5e_sq *sq) 4033 { 4034 int err; 4035 4036 /* check if already enabled */ 4037 if (READ_ONCE(sq->running) != 0) 4038 return; 4039 4040 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR, 4041 MLX5_SQC_STATE_RST); 4042 if (err != 0) { 4043 mlx5_en_err(sq->ifp, 4044 "mlx5e_modify_sq() from ERR to RST failed: %d\n", err); 4045 } 4046 4047 sq->cc = 0; 4048 sq->pc = 0; 4049 4050 /* reset doorbell prior to moving from RST to RDY */ 4051 mlx5e_reset_sq_doorbell_record(sq); 4052 4053 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, 4054 MLX5_SQC_STATE_RDY); 4055 if (err != 0) { 4056 mlx5_en_err(sq->ifp, 4057 "mlx5e_modify_sq() from RST to RDY failed: %d\n", err); 4058 } 4059 4060 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL; 4061 WRITE_ONCE(sq->running, 1); 4062 } 4063 4064 static void 4065 mlx5e_enable_tx_dma(struct mlx5e_channel *ch) 4066 { 4067 int i; 4068 4069 for (i = 0; i < ch->priv->num_tc; i++) 4070 mlx5e_resume_sq(&ch->sq[i]); 4071 } 4072 4073 static void 4074 mlx5e_disable_rx_dma(struct mlx5e_channel *ch) 4075 { 4076 struct mlx5e_rq *rq = &ch->rq; 4077 struct epoch_tracker et; 4078 int err; 4079 4080 mtx_lock(&rq->mtx); 4081 rq->enabled = 0; 4082 callout_stop(&rq->watchdog); 4083 mtx_unlock(&rq->mtx); 4084 4085 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 4086 if (err != 0) { 4087 mlx5_en_err(rq->ifp, 4088 "mlx5e_modify_rq() from RDY to RST failed: %d\n", err); 4089 } 4090 4091 while (!mlx5_wq_ll_is_empty(&rq->wq)) { 4092 msleep(1); 4093 NET_EPOCH_ENTER(et); 4094 rq->cq.mcq.comp(&rq->cq.mcq, NULL); 4095 NET_EPOCH_EXIT(et); 4096 } 4097 4098 /* 4099 * Transitioning into RST state will allow the FW to track less ERR state queues, 4100 * thus reducing the recv queue flushing time 4101 */ 4102 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST); 4103 if (err != 0) { 4104 mlx5_en_err(rq->ifp, 4105 "mlx5e_modify_rq() from ERR to RST failed: %d\n", err); 4106 } 4107 } 4108 4109 static void 4110 mlx5e_enable_rx_dma(struct mlx5e_channel *ch) 4111 { 4112 struct mlx5e_rq *rq = &ch->rq; 4113 struct epoch_tracker et; 4114 int err; 4115 4116 rq->wq.wqe_ctr = 0; 4117 mlx5_wq_ll_update_db_record(&rq->wq); 4118 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 4119 if (err != 0) { 4120 mlx5_en_err(rq->ifp, 4121 "mlx5e_modify_rq() from RST to RDY failed: %d\n", err); 4122 } 4123 4124 rq->enabled = 1; 4125 4126 NET_EPOCH_ENTER(et); 4127 rq->cq.mcq.comp(&rq->cq.mcq, NULL); 4128 NET_EPOCH_EXIT(et); 4129 } 4130 4131 void 4132 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value) 4133 { 4134 int i; 4135 4136 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 4137 return; 4138 4139 for (i = 0; i < priv->params.num_channels; i++) { 4140 if (value) 4141 mlx5e_disable_tx_dma(&priv->channel[i]); 4142 else 4143 mlx5e_enable_tx_dma(&priv->channel[i]); 4144 } 4145 } 4146 4147 void 4148 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value) 4149 { 4150 int i; 4151 4152 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 4153 return; 4154 4155 for (i = 0; i < priv->params.num_channels; i++) { 4156 if (value) 4157 mlx5e_disable_rx_dma(&priv->channel[i]); 4158 else 4159 mlx5e_enable_rx_dma(&priv->channel[i]); 4160 } 4161 } 4162 4163 static void 4164 mlx5e_add_hw_stats(struct mlx5e_priv *priv) 4165 { 4166 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 4167 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 4168 priv, 0, sysctl_firmware, "A", "HCA firmware version"); 4169 4170 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 4171 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0, 4172 "Board ID"); 4173 } 4174 4175 static int 4176 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS) 4177 { 4178 struct mlx5e_priv *priv = arg1; 4179 uint8_t temp[MLX5E_MAX_PRIORITY]; 4180 uint32_t tx_pfc; 4181 int err; 4182 int i; 4183 4184 PRIV_LOCK(priv); 4185 4186 tx_pfc = priv->params.tx_priority_flow_control; 4187 4188 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) 4189 temp[i] = (tx_pfc >> i) & 1; 4190 4191 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY); 4192 if (err || !req->newptr) 4193 goto done; 4194 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY); 4195 if (err) 4196 goto done; 4197 4198 priv->params.tx_priority_flow_control = 0; 4199 4200 /* range check input value */ 4201 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) { 4202 if (temp[i] > 1) { 4203 err = ERANGE; 4204 goto done; 4205 } 4206 priv->params.tx_priority_flow_control |= (temp[i] << i); 4207 } 4208 4209 /* check if update is required */ 4210 if (tx_pfc != priv->params.tx_priority_flow_control) 4211 err = -mlx5e_set_port_pfc(priv); 4212 done: 4213 if (err != 0) 4214 priv->params.tx_priority_flow_control= tx_pfc; 4215 PRIV_UNLOCK(priv); 4216 4217 return (err); 4218 } 4219 4220 static int 4221 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS) 4222 { 4223 struct mlx5e_priv *priv = arg1; 4224 uint8_t temp[MLX5E_MAX_PRIORITY]; 4225 uint32_t rx_pfc; 4226 int err; 4227 int i; 4228 4229 PRIV_LOCK(priv); 4230 4231 rx_pfc = priv->params.rx_priority_flow_control; 4232 4233 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) 4234 temp[i] = (rx_pfc >> i) & 1; 4235 4236 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY); 4237 if (err || !req->newptr) 4238 goto done; 4239 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY); 4240 if (err) 4241 goto done; 4242 4243 priv->params.rx_priority_flow_control = 0; 4244 4245 /* range check input value */ 4246 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) { 4247 if (temp[i] > 1) { 4248 err = ERANGE; 4249 goto done; 4250 } 4251 priv->params.rx_priority_flow_control |= (temp[i] << i); 4252 } 4253 4254 /* check if update is required */ 4255 if (rx_pfc != priv->params.rx_priority_flow_control) { 4256 err = -mlx5e_set_port_pfc(priv); 4257 if (err == 0 && priv->sw_is_port_buf_owner) 4258 err = mlx5e_update_buf_lossy(priv); 4259 } 4260 done: 4261 if (err != 0) 4262 priv->params.rx_priority_flow_control= rx_pfc; 4263 PRIV_UNLOCK(priv); 4264 4265 return (err); 4266 } 4267 4268 static void 4269 mlx5e_setup_pauseframes(struct mlx5e_priv *priv) 4270 { 4271 int error; 4272 4273 /* enable pauseframes by default */ 4274 priv->params.tx_pauseframe_control = 1; 4275 priv->params.rx_pauseframe_control = 1; 4276 4277 /* disable ports flow control, PFC, by default */ 4278 priv->params.tx_priority_flow_control = 0; 4279 priv->params.rx_priority_flow_control = 0; 4280 4281 /* register pauseframe SYSCTLs */ 4282 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4283 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN, 4284 &priv->params.tx_pauseframe_control, 0, 4285 "Set to enable TX pause frames. Clear to disable."); 4286 4287 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4288 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN, 4289 &priv->params.rx_pauseframe_control, 0, 4290 "Set to enable RX pause frames. Clear to disable."); 4291 4292 /* register priority flow control, PFC, SYSCTLs */ 4293 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4294 OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN | 4295 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU", 4296 "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable."); 4297 4298 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4299 OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN | 4300 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU", 4301 "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable."); 4302 4303 PRIV_LOCK(priv); 4304 4305 /* range check */ 4306 priv->params.tx_pauseframe_control = 4307 priv->params.tx_pauseframe_control ? 1 : 0; 4308 priv->params.rx_pauseframe_control = 4309 priv->params.rx_pauseframe_control ? 1 : 0; 4310 4311 /* update firmware */ 4312 error = mlx5e_set_port_pause_and_pfc(priv); 4313 if (error == -EINVAL) { 4314 mlx5_en_err(priv->ifp, 4315 "Global pauseframes must be disabled before enabling PFC.\n"); 4316 priv->params.rx_priority_flow_control = 0; 4317 priv->params.tx_priority_flow_control = 0; 4318 4319 /* update firmware */ 4320 (void) mlx5e_set_port_pause_and_pfc(priv); 4321 } 4322 PRIV_UNLOCK(priv); 4323 } 4324 4325 static int 4326 mlx5e_ul_snd_tag_alloc(if_t ifp, 4327 union if_snd_tag_alloc_params *params, 4328 struct m_snd_tag **ppmt) 4329 { 4330 struct mlx5e_priv *priv; 4331 struct mlx5e_channel *pch; 4332 4333 priv = if_getsoftc(ifp); 4334 4335 if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) { 4336 return (EOPNOTSUPP); 4337 } else { 4338 /* keep this code synced with mlx5e_select_queue() */ 4339 u32 ch = priv->params.num_channels; 4340 #ifdef RSS 4341 u32 temp; 4342 4343 if (rss_hash2bucket(params->hdr.flowid, 4344 params->hdr.flowtype, &temp) == 0) 4345 ch = temp % ch; 4346 else 4347 #endif 4348 ch = (params->hdr.flowid % 128) % ch; 4349 4350 /* 4351 * NOTE: The channels array is only freed at detach 4352 * and it safe to return a pointer to the send tag 4353 * inside the channels structure as long as we 4354 * reference the priv. 4355 */ 4356 pch = priv->channel + ch; 4357 4358 /* check if send queue is not running */ 4359 if (unlikely(pch->sq[0].running == 0)) 4360 return (ENXIO); 4361 m_snd_tag_ref(&pch->tag); 4362 *ppmt = &pch->tag; 4363 return (0); 4364 } 4365 } 4366 4367 static int 4368 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params) 4369 { 4370 struct mlx5e_channel *pch = 4371 container_of(pmt, struct mlx5e_channel, tag); 4372 4373 params->unlimited.max_rate = -1ULL; 4374 params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]); 4375 return (0); 4376 } 4377 4378 static void 4379 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt) 4380 { 4381 struct mlx5e_channel *pch = 4382 container_of(pmt, struct mlx5e_channel, tag); 4383 4384 complete(&pch->completion); 4385 } 4386 4387 static int 4388 mlx5e_snd_tag_alloc(if_t ifp, 4389 union if_snd_tag_alloc_params *params, 4390 struct m_snd_tag **ppmt) 4391 { 4392 4393 switch (params->hdr.type) { 4394 #ifdef RATELIMIT 4395 case IF_SND_TAG_TYPE_RATE_LIMIT: 4396 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt)); 4397 #ifdef KERN_TLS 4398 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT: 4399 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt)); 4400 #endif 4401 #endif 4402 case IF_SND_TAG_TYPE_UNLIMITED: 4403 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt)); 4404 #ifdef KERN_TLS 4405 case IF_SND_TAG_TYPE_TLS: 4406 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt)); 4407 case IF_SND_TAG_TYPE_TLS_RX: 4408 return (mlx5e_tls_rx_snd_tag_alloc(ifp, params, ppmt)); 4409 #endif 4410 default: 4411 return (EOPNOTSUPP); 4412 } 4413 } 4414 4415 #ifdef RATELIMIT 4416 #define NUM_HDWR_RATES_MLX 13 4417 static const uint64_t adapter_rates_mlx[NUM_HDWR_RATES_MLX] = { 4418 135375, /* 1,083,000 */ 4419 180500, /* 1,444,000 */ 4420 270750, /* 2,166,000 */ 4421 361000, /* 2,888,000 */ 4422 541500, /* 4,332,000 */ 4423 721875, /* 5,775,000 */ 4424 1082875, /* 8,663,000 */ 4425 1443875, /* 11,551,000 */ 4426 2165750, /* 17,326,000 */ 4427 2887750, /* 23,102,000 */ 4428 4331625, /* 34,653,000 */ 4429 5775500, /* 46,204,000 */ 4430 8663125 /* 69,305,000 */ 4431 }; 4432 4433 static void 4434 mlx5e_ratelimit_query(if_t ifp __unused, struct if_ratelimit_query_results *q) 4435 { 4436 /* 4437 * This function needs updating by the driver maintainer! 4438 * For the MLX card there are currently (ConectX-4?) 13 4439 * pre-set rates and others i.e. ConnectX-5, 6, 7?? 4440 * 4441 * This will change based on later adapters 4442 * and this code should be updated to look at ifp 4443 * and figure out the specific adapter type 4444 * settings i.e. how many rates as well 4445 * as if they are fixed (as is shown here) or 4446 * if they are dynamic (example chelsio t4). Also if there 4447 * is a maximum number of flows that the adapter 4448 * can handle that too needs to be updated in 4449 * the max_flows field. 4450 */ 4451 q->rate_table = adapter_rates_mlx; 4452 q->flags = RT_IS_FIXED_TABLE; 4453 q->max_flows = 0; /* mlx has no limit */ 4454 q->number_of_rates = NUM_HDWR_RATES_MLX; 4455 q->min_segment_burst = 1; 4456 } 4457 #endif 4458 4459 static void 4460 mlx5e_ifm_add(struct mlx5e_priv *priv, int type) 4461 { 4462 ifmedia_add(&priv->media, type | IFM_ETHER, 0, NULL); 4463 ifmedia_add(&priv->media, type | IFM_ETHER | 4464 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 4465 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_RXPAUSE, 0, NULL); 4466 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_TXPAUSE, 0, NULL); 4467 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX, 0, NULL); 4468 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX | 4469 IFM_ETH_RXPAUSE, 0, NULL); 4470 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX | 4471 IFM_ETH_TXPAUSE, 0, NULL); 4472 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX | 4473 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 4474 } 4475 4476 static void * 4477 mlx5e_create_ifp(struct mlx5_core_dev *mdev) 4478 { 4479 if_t ifp; 4480 struct mlx5e_priv *priv; 4481 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4); 4482 struct sysctl_oid_list *child; 4483 int ncv = mdev->priv.eq_table.num_comp_vectors; 4484 char unit[16]; 4485 struct pfil_head_args pa; 4486 int err; 4487 u32 eth_proto_cap; 4488 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 4489 bool ext; 4490 struct media media_entry = {}; 4491 4492 if (mlx5e_check_required_hca_cap(mdev)) { 4493 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n"); 4494 return (NULL); 4495 } 4496 4497 /* 4498 * Try to allocate the priv and make room for worst-case 4499 * number of channel structures: 4500 */ 4501 priv = malloc_domainset(sizeof(*priv) + 4502 (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors), 4503 M_MLX5EN, mlx5_dev_domainset(mdev), M_WAITOK | M_ZERO); 4504 4505 ifp = priv->ifp = if_alloc_dev(IFT_ETHER, mdev->pdev->dev.bsddev); 4506 /* setup all static fields */ 4507 if (mlx5e_priv_static_init(priv, mdev, mdev->priv.eq_table.num_comp_vectors)) { 4508 mlx5_core_err(mdev, "mlx5e_priv_static_init() failed\n"); 4509 goto err_free_ifp; 4510 } 4511 4512 if_setsoftc(ifp, priv); 4513 if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev)); 4514 if_setmtu(ifp, ETHERMTU); 4515 if_setinitfn(ifp, mlx5e_open); 4516 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 4517 if_setioctlfn(ifp, mlx5e_ioctl); 4518 if_settransmitfn(ifp, mlx5e_xmit); 4519 if_setqflushfn(ifp, if_qflush); 4520 if_setgetcounterfn(ifp, mlx5e_get_counter); 4521 if_setsendqlen(ifp, ifqmaxlen); 4522 /* 4523 * Set driver features 4524 */ 4525 if_setcapabilities(ifp, IFCAP_NV); 4526 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6, 0); 4527 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING, 0); 4528 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER, 0); 4529 if_setcapabilitiesbit(ifp, IFCAP_LINKSTATE | IFCAP_JUMBO_MTU, 0); 4530 if_setcapabilitiesbit(ifp, IFCAP_LRO, 0); 4531 if_setcapabilitiesbit(ifp, IFCAP_TSO | IFCAP_VLAN_HWTSO, 0); 4532 if_setcapabilitiesbit(ifp, IFCAP_HWSTATS | IFCAP_HWRXTSTMP, 0); 4533 if_setcapabilitiesbit(ifp, IFCAP_MEXTPG, 0); 4534 if_setcapabilitiesbit(ifp, IFCAP_TXTLS4 | IFCAP_TXTLS6, 0); 4535 #ifdef RATELIMIT 4536 if_setcapabilitiesbit(ifp, IFCAP_TXRTLMT | IFCAP_TXTLS_RTLMT, 0); 4537 #endif 4538 if_setcapabilitiesbit(ifp, IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO, 0); 4539 if_setcapabilities2bit(ifp, IFCAP2_BIT(IFCAP2_RXTLS4) | 4540 IFCAP2_BIT(IFCAP2_RXTLS6), 0); 4541 4542 if (mlx5_ipsec_device_caps(mdev) & MLX5_IPSEC_CAP_PACKET_OFFLOAD) 4543 if_setcapabilities2bit(ifp, IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD), 4544 0); 4545 4546 if_setsndtagallocfn(ifp, mlx5e_snd_tag_alloc); 4547 #ifdef RATELIMIT 4548 if_setratelimitqueryfn(ifp, mlx5e_ratelimit_query); 4549 #endif 4550 /* set TSO limits so that we don't have to drop TX packets */ 4551 if_sethwtsomax(ifp, MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN)); 4552 if_sethwtsomaxsegcount(ifp, MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */); 4553 if_sethwtsomaxsegsize(ifp, MLX5E_MAX_TX_MBUF_SIZE); 4554 4555 if_setcapenable(ifp, if_getcapabilities(ifp)); 4556 if_setcapenable2(ifp, if_getcapabilities2(ifp)); 4557 if_sethwassist(ifp, 0); 4558 if (if_getcapenable(ifp) & IFCAP_TSO) 4559 if_sethwassistbits(ifp, CSUM_TSO, 0); 4560 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 4561 if_sethwassistbits(ifp, (CSUM_TCP | CSUM_UDP | CSUM_IP), 0); 4562 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 4563 if_sethwassistbits(ifp, (CSUM_UDP_IPV6 | CSUM_TCP_IPV6), 0); 4564 if (if_getcapabilities(ifp) & IFCAP_VXLAN_HWCSUM) 4565 if_sethwassistbits(ifp, CSUM_INNER_IP6_UDP | CSUM_INNER_IP6_TCP | 4566 CSUM_INNER_IP | CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP | 4567 CSUM_ENCAP_VXLAN, 0); 4568 if (if_getcapabilities(ifp) & IFCAP_VXLAN_HWTSO) 4569 if_sethwassistbits(ifp, CSUM_INNER_IP6_TSO | CSUM_INNER_IP_TSO, 0); 4570 4571 /* ifnet sysctl tree */ 4572 sysctl_ctx_init(&priv->sysctl_ctx); 4573 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev), 4574 OID_AUTO, if_getdname(ifp), CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 4575 "MLX5 ethernet - interface name"); 4576 if (priv->sysctl_ifnet == NULL) { 4577 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4578 goto err_free_sysctl; 4579 } 4580 snprintf(unit, sizeof(unit), "%d", if_getdunit(ifp)); 4581 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4582 OID_AUTO, unit, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 4583 "MLX5 ethernet - interface unit"); 4584 if (priv->sysctl_ifnet == NULL) { 4585 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4586 goto err_free_sysctl; 4587 } 4588 4589 /* HW sysctl tree */ 4590 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev)); 4591 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child, 4592 OID_AUTO, "hw", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 4593 "MLX5 ethernet dev hw"); 4594 if (priv->sysctl_hw == NULL) { 4595 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4596 goto err_free_sysctl; 4597 } 4598 4599 err = mlx5e_build_ifp_priv(mdev, priv, ncv); 4600 if (err) { 4601 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err); 4602 goto err_free_sysctl; 4603 } 4604 4605 /* reuse mlx5core's watchdog workqueue */ 4606 priv->wq = mdev->priv.health.wq_watchdog; 4607 4608 err = mlx5_core_alloc_pd(mdev, &priv->pdn, 0); 4609 if (err) { 4610 mlx5_en_err(ifp, "mlx5_core_alloc_pd failed, %d\n", err); 4611 goto err_free_wq; 4612 } 4613 err = mlx5_alloc_transport_domain(mdev, &priv->tdn, 0); 4614 if (err) { 4615 mlx5_en_err(ifp, 4616 "mlx5_alloc_transport_domain failed, %d\n", err); 4617 goto err_dealloc_pd; 4618 } 4619 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr); 4620 if (err) { 4621 mlx5_en_err(ifp, "mlx5e_create_mkey failed, %d\n", err); 4622 goto err_dealloc_transport_domain; 4623 } 4624 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr); 4625 4626 /* check if we should generate a random MAC address */ 4627 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 && 4628 is_zero_ether_addr(dev_addr)) { 4629 random_ether_addr(dev_addr); 4630 mlx5_en_err(ifp, "Assigned random MAC address\n"); 4631 } 4632 4633 err = mlx5e_rl_init(priv); 4634 if (err) { 4635 mlx5_en_err(ifp, "mlx5e_rl_init failed, %d\n", err); 4636 goto err_create_mkey; 4637 } 4638 4639 err = mlx5e_tls_init(priv); 4640 if (err) { 4641 if_printf(ifp, "%s: mlx5e_tls_init failed\n", __func__); 4642 goto err_rl_init; 4643 } 4644 4645 if ((if_getcapenable2(ifp) & IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD)) != 0) { 4646 err = mlx5e_ipsec_init(priv); 4647 if (err) { 4648 if_printf(ifp, "%s: mlx5e_tls_init failed\n", __func__); 4649 goto err_tls_init; 4650 } 4651 } 4652 4653 err = mlx5e_open_drop_rq(priv, &priv->drop_rq); 4654 if (err) { 4655 if_printf(ifp, "%s: mlx5e_open_drop_rq failed (%d)\n", __func__, err); 4656 goto err_ipsec_init; 4657 } 4658 4659 err = mlx5e_open_rqts(priv); 4660 if (err) { 4661 if_printf(ifp, "%s: mlx5e_open_rqts failed (%d)\n", __func__, err); 4662 goto err_open_drop_rq; 4663 } 4664 4665 err = mlx5e_open_tirs(priv); 4666 if (err) { 4667 mlx5_en_err(ifp, "mlx5e_open_tirs() failed, %d\n", err); 4668 goto err_open_rqts; 4669 } 4670 4671 err = mlx5e_open_flow_tables(priv); 4672 if (err) { 4673 if_printf(ifp, "%s: mlx5e_open_flow_tables failed (%d)\n", __func__, err); 4674 goto err_open_tirs; 4675 } 4676 4677 err = mlx5e_tls_rx_init(priv); 4678 if (err) { 4679 if_printf(ifp, "%s: mlx5e_tls_rx_init() failed, %d\n", __func__, err); 4680 goto err_open_flow_tables; 4681 } 4682 4683 /* set default MTU */ 4684 mlx5e_set_dev_port_mtu(ifp, if_getmtu(ifp)); 4685 4686 /* Set default media status */ 4687 priv->media_status_last = IFM_AVALID; 4688 priv->media_active_last = IFM_ETHER | IFM_AUTO | IFM_FDX; 4689 4690 /* setup default pauseframes configuration */ 4691 mlx5e_setup_pauseframes(priv); 4692 4693 /* Setup supported medias */ 4694 if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) { 4695 ext = MLX5_CAP_PCAM_FEATURE(mdev, 4696 ptys_extended_ethernet); 4697 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 4698 eth_proto_capability); 4699 } else { 4700 ext = false; 4701 eth_proto_cap = 0; 4702 mlx5_en_err(ifp, "Query port media capability failed, %d\n", err); 4703 } 4704 4705 ifmedia_init(&priv->media, IFM_IMASK, 4706 mlx5e_media_change, mlx5e_media_status); 4707 4708 if (ext) { 4709 for (unsigned i = 0; i != MLX5E_EXT_LINK_SPEEDS_NUMBER; i++) { 4710 /* check if hardware has the right capability */ 4711 if (MLX5E_PROT_MASK(i) & ~eth_proto_cap) 4712 continue; 4713 for (unsigned j = 0; j != MLX5E_CABLE_TYPE_NUMBER; j++) { 4714 media_entry = mlx5e_ext_mode_table[i][j]; 4715 if (media_entry.subtype == 0) 4716 continue; 4717 /* check if this subtype was already added */ 4718 for (unsigned k = 0; k != i; k++) { 4719 /* check if hardware has the right capability */ 4720 if (MLX5E_PROT_MASK(k) & ~eth_proto_cap) 4721 continue; 4722 for (unsigned m = 0; m != MLX5E_CABLE_TYPE_NUMBER; m++) { 4723 if (media_entry.subtype == mlx5e_ext_mode_table[k][m].subtype) 4724 goto skip_ext_media; 4725 } 4726 } 4727 mlx5e_ifm_add(priv, media_entry.subtype); 4728 skip_ext_media:; 4729 } 4730 } 4731 } else { 4732 for (unsigned i = 0; i != MLX5E_LINK_SPEEDS_NUMBER; i++) { 4733 media_entry = mlx5e_mode_table[i]; 4734 if (media_entry.subtype == 0) 4735 continue; 4736 if (MLX5E_PROT_MASK(i) & ~eth_proto_cap) 4737 continue; 4738 /* check if this subtype was already added */ 4739 for (unsigned k = 0; k != i; k++) { 4740 if (media_entry.subtype == mlx5e_mode_table[k].subtype) 4741 goto skip_media; 4742 } 4743 mlx5e_ifm_add(priv, media_entry.subtype); 4744 4745 /* NOTE: 10G ER and LR shares the same entry */ 4746 if (media_entry.subtype == IFM_10G_ER) 4747 mlx5e_ifm_add(priv, IFM_10G_LR); 4748 skip_media:; 4749 } 4750 } 4751 4752 mlx5e_ifm_add(priv, IFM_AUTO); 4753 4754 /* Set autoselect by default */ 4755 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX | 4756 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE); 4757 4758 DEBUGNET_SET(ifp, mlx5_en); 4759 4760 ether_ifattach(ifp, dev_addr); 4761 4762 /* Register for VLAN events */ 4763 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config, 4764 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST); 4765 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig, 4766 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST); 4767 4768 /* Register for VxLAN events */ 4769 priv->vxlan_start = EVENTHANDLER_REGISTER(vxlan_start, 4770 mlx5e_vxlan_start, priv, EVENTHANDLER_PRI_ANY); 4771 priv->vxlan_stop = EVENTHANDLER_REGISTER(vxlan_stop, 4772 mlx5e_vxlan_stop, priv, EVENTHANDLER_PRI_ANY); 4773 4774 /* Link is down by default */ 4775 if_link_state_change(ifp, LINK_STATE_DOWN); 4776 4777 mlx5e_enable_async_events(priv); 4778 4779 mlx5e_add_hw_stats(priv); 4780 4781 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4782 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM, 4783 priv->stats.vport.arg); 4784 4785 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4786 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM, 4787 priv->stats.pport.arg); 4788 4789 mlx5e_create_ethtool(priv); 4790 4791 mtx_lock(&priv->async_events_mtx); 4792 mlx5e_update_stats(priv); 4793 mtx_unlock(&priv->async_events_mtx); 4794 4795 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4796 OID_AUTO, "rx_clbr_done", CTLFLAG_RD, 4797 &priv->clbr_done, 0, 4798 "RX timestamps calibration state"); 4799 callout_init(&priv->tstmp_clbr, 1); 4800 /* Pull out the frequency of the clock in hz */ 4801 priv->cclk = (uint64_t)MLX5_CAP_GEN(mdev, device_frequency_khz) * 1000ULL; 4802 mlx5e_reset_calibration_callout(priv); 4803 4804 pa.pa_version = PFIL_VERSION; 4805 pa.pa_flags = PFIL_IN; 4806 pa.pa_type = PFIL_TYPE_ETHERNET; 4807 pa.pa_headname = if_name(ifp); 4808 priv->pfil = pfil_head_register(&pa); 4809 4810 PRIV_LOCK(priv); 4811 err = mlx5e_open_flow_rules(priv); 4812 if (err) { 4813 mlx5_en_err(ifp, 4814 "mlx5e_open_flow_rules() failed, %d (ignored)\n", err); 4815 } 4816 PRIV_UNLOCK(priv); 4817 4818 return (priv); 4819 4820 err_open_flow_tables: 4821 mlx5e_close_flow_tables(priv); 4822 4823 err_open_tirs: 4824 mlx5e_close_tirs(priv); 4825 4826 err_open_rqts: 4827 mlx5e_close_rqts(priv); 4828 4829 err_open_drop_rq: 4830 mlx5e_close_drop_rq(&priv->drop_rq); 4831 4832 err_ipsec_init: 4833 mlx5e_ipsec_cleanup(priv); 4834 4835 err_tls_init: 4836 mlx5e_tls_cleanup(priv); 4837 4838 err_rl_init: 4839 mlx5e_rl_cleanup(priv); 4840 4841 err_create_mkey: 4842 mlx5_core_destroy_mkey(priv->mdev, &priv->mr); 4843 4844 err_dealloc_transport_domain: 4845 mlx5_dealloc_transport_domain(mdev, priv->tdn, 0); 4846 4847 err_dealloc_pd: 4848 mlx5_core_dealloc_pd(mdev, priv->pdn, 0); 4849 4850 err_free_wq: 4851 flush_workqueue(priv->wq); 4852 4853 err_free_sysctl: 4854 sysctl_ctx_free(&priv->sysctl_ctx); 4855 if (priv->sysctl_debug) 4856 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx); 4857 mlx5e_priv_static_destroy(priv, mdev, mdev->priv.eq_table.num_comp_vectors); 4858 4859 err_free_ifp: 4860 if_free(ifp); 4861 free(priv, M_MLX5EN); 4862 return (NULL); 4863 } 4864 4865 static void 4866 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv) 4867 { 4868 struct mlx5e_priv *priv = vpriv; 4869 if_t ifp = priv->ifp; 4870 4871 /* don't allow more IOCTLs */ 4872 priv->gone = 1; 4873 4874 /* XXX wait a bit to allow IOCTL handlers to complete */ 4875 pause("W", hz); 4876 4877 #ifdef RATELIMIT 4878 /* 4879 * The kernel can have reference(s) via the m_snd_tag's into 4880 * the ratelimit channels, and these must go away before 4881 * detaching: 4882 */ 4883 while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) { 4884 mlx5_en_err(priv->ifp, 4885 "Waiting for all ratelimit connections to terminate\n"); 4886 pause("W", hz); 4887 } 4888 #endif 4889 4890 #ifdef KERN_TLS 4891 /* wait for all TLS tags to get freed */ 4892 while (priv->tls.init != 0 && 4893 uma_zone_get_cur(priv->tls.zone) != 0) { 4894 mlx5_en_err(priv->ifp, 4895 "Waiting for all TLS connections to terminate\n"); 4896 pause("W", hz); 4897 } 4898 4899 /* wait for all TLS RX tags to get freed */ 4900 while (priv->tls_rx.init != 0 && 4901 uma_zone_get_cur(priv->tls_rx.zone) != 0) { 4902 mlx5_en_err(priv->ifp, 4903 "Waiting for all TLS RX connections to terminate\n"); 4904 pause("W", hz); 4905 } 4906 #endif 4907 /* wait for all unlimited send tags to complete */ 4908 mlx5e_priv_wait_for_completion(priv, mdev->priv.eq_table.num_comp_vectors); 4909 4910 /* stop watchdog timer */ 4911 callout_drain(&priv->watchdog); 4912 4913 callout_drain(&priv->tstmp_clbr); 4914 4915 if (priv->vlan_attach != NULL) 4916 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach); 4917 if (priv->vlan_detach != NULL) 4918 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach); 4919 if (priv->vxlan_start != NULL) 4920 EVENTHANDLER_DEREGISTER(vxlan_start, priv->vxlan_start); 4921 if (priv->vxlan_stop != NULL) 4922 EVENTHANDLER_DEREGISTER(vxlan_stop, priv->vxlan_stop); 4923 4924 /* make sure device gets closed */ 4925 PRIV_LOCK(priv); 4926 mlx5e_close_locked(ifp); 4927 mlx5e_close_flow_rules(priv); 4928 PRIV_UNLOCK(priv); 4929 4930 /* deregister pfil */ 4931 if (priv->pfil != NULL) { 4932 pfil_head_unregister(priv->pfil); 4933 priv->pfil = NULL; 4934 } 4935 4936 /* unregister device */ 4937 ifmedia_removeall(&priv->media); 4938 ether_ifdetach(ifp); 4939 4940 mlx5e_tls_rx_cleanup(priv); 4941 #ifdef IPSEC_OFFLOAD 4942 ipsec_accel_on_ifdown(priv->ifp); 4943 #endif 4944 mlx5e_close_flow_tables(priv); 4945 mlx5e_close_tirs(priv); 4946 mlx5e_close_rqts(priv); 4947 mlx5e_close_drop_rq(&priv->drop_rq); 4948 mlx5e_ipsec_cleanup(priv); 4949 mlx5e_tls_cleanup(priv); 4950 mlx5e_rl_cleanup(priv); 4951 4952 /* destroy all remaining sysctl nodes */ 4953 sysctl_ctx_free(&priv->stats.vport.ctx); 4954 sysctl_ctx_free(&priv->stats.pport.ctx); 4955 if (priv->sysctl_debug) 4956 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx); 4957 sysctl_ctx_free(&priv->sysctl_ctx); 4958 4959 mlx5_core_destroy_mkey(priv->mdev, &priv->mr); 4960 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn, 0); 4961 mlx5_core_dealloc_pd(priv->mdev, priv->pdn, 0); 4962 mlx5e_disable_async_events(priv); 4963 flush_workqueue(priv->wq); 4964 mlx5e_priv_static_destroy(priv, mdev, mdev->priv.eq_table.num_comp_vectors); 4965 if_free(ifp); 4966 free(priv, M_MLX5EN); 4967 } 4968 4969 #ifdef DEBUGNET 4970 static void 4971 mlx5_en_debugnet_init(if_t dev, int *nrxr, int *ncl, int *clsize) 4972 { 4973 struct mlx5e_priv *priv = if_getsoftc(dev); 4974 4975 PRIV_LOCK(priv); 4976 *nrxr = priv->params.num_channels; 4977 *ncl = DEBUGNET_MAX_IN_FLIGHT; 4978 *clsize = MLX5E_MAX_RX_BYTES; 4979 PRIV_UNLOCK(priv); 4980 } 4981 4982 static void 4983 mlx5_en_debugnet_event(if_t dev, enum debugnet_ev event) 4984 { 4985 } 4986 4987 static int 4988 mlx5_en_debugnet_transmit(if_t dev, struct mbuf *m) 4989 { 4990 struct mlx5e_priv *priv = if_getsoftc(dev); 4991 struct mlx5e_sq *sq; 4992 int err; 4993 4994 if ((if_getdrvflags(dev) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4995 IFF_DRV_RUNNING || (priv->media_status_last & IFM_ACTIVE) == 0) 4996 return (ENOENT); 4997 4998 sq = &priv->channel[0].sq[0]; 4999 5000 if (sq->running == 0) { 5001 m_freem(m); 5002 return (ENOENT); 5003 } 5004 5005 if (mlx5e_sq_xmit(sq, &m) != 0) { 5006 m_freem(m); 5007 err = ENOBUFS; 5008 } else { 5009 err = 0; 5010 } 5011 5012 mlx5e_tx_notify_hw(sq, true); 5013 5014 return (err); 5015 } 5016 5017 static int 5018 mlx5_en_debugnet_poll(if_t dev, int count) 5019 { 5020 struct mlx5e_priv *priv = if_getsoftc(dev); 5021 5022 if ((if_getdrvflags(dev) & IFF_DRV_RUNNING) == 0 || 5023 (priv->media_status_last & IFM_ACTIVE) == 0) 5024 return (ENOENT); 5025 5026 mlx5_poll_interrupts(priv->mdev); 5027 5028 return (0); 5029 } 5030 #endif /* DEBUGNET */ 5031 5032 static void * 5033 mlx5e_get_ifp(void *vpriv) 5034 { 5035 struct mlx5e_priv *priv = vpriv; 5036 5037 return (priv->ifp); 5038 } 5039 5040 static struct mlx5_interface mlx5e_interface = { 5041 .add = mlx5e_create_ifp, 5042 .remove = mlx5e_destroy_ifp, 5043 .event = mlx5e_async_event, 5044 .protocol = MLX5_INTERFACE_PROTOCOL_ETH, 5045 .get_dev = mlx5e_get_ifp, 5046 }; 5047 5048 void 5049 mlx5e_init(void) 5050 { 5051 mlx5_register_interface(&mlx5e_interface); 5052 } 5053 5054 void 5055 mlx5e_cleanup(void) 5056 { 5057 mlx5_unregister_interface(&mlx5e_interface); 5058 } 5059 5060 module_init_order(mlx5e_init, SI_ORDER_SIXTH); 5061 module_exit_order(mlx5e_cleanup, SI_ORDER_SIXTH); 5062 5063 MODULE_DEPEND(mlx5en, ipsec, 1, 1, 1); 5064 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1); 5065 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1); 5066 MODULE_VERSION(mlx5en, 1); 5067