1 /*- 2 * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include "en.h" 29 30 #include <sys/eventhandler.h> 31 #include <sys/sockio.h> 32 #include <machine/atomic.h> 33 34 #ifndef ETH_DRIVER_VERSION 35 #define ETH_DRIVER_VERSION "3.5.2" 36 #endif 37 #define DRIVER_RELDATE "September 2019" 38 39 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver " 40 ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n"; 41 42 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs); 43 44 struct mlx5e_channel_param { 45 struct mlx5e_rq_param rq; 46 struct mlx5e_sq_param sq; 47 struct mlx5e_cq_param rx_cq; 48 struct mlx5e_cq_param tx_cq; 49 }; 50 51 struct media { 52 u32 subtype; 53 u64 baudrate; 54 }; 55 56 static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = { 57 58 [MLX5E_1000BASE_CX_SGMII][MLX5E_SGMII] = { 59 .subtype = IFM_1000_CX_SGMII, 60 .baudrate = IF_Mbps(1000ULL), 61 }, 62 [MLX5E_1000BASE_KX][MLX5E_KX] = { 63 .subtype = IFM_1000_KX, 64 .baudrate = IF_Mbps(1000ULL), 65 }, 66 [MLX5E_10GBASE_CX4][MLX5E_CX4] = { 67 .subtype = IFM_10G_CX4, 68 .baudrate = IF_Gbps(10ULL), 69 }, 70 [MLX5E_10GBASE_KX4][MLX5E_KX4] = { 71 .subtype = IFM_10G_KX4, 72 .baudrate = IF_Gbps(10ULL), 73 }, 74 [MLX5E_10GBASE_KR][MLX5E_KR] = { 75 .subtype = IFM_10G_KR, 76 .baudrate = IF_Gbps(10ULL), 77 }, 78 [MLX5E_20GBASE_KR2][MLX5E_KR2] = { 79 .subtype = IFM_20G_KR2, 80 .baudrate = IF_Gbps(20ULL), 81 }, 82 [MLX5E_40GBASE_CR4][MLX5E_CR4] = { 83 .subtype = IFM_40G_CR4, 84 .baudrate = IF_Gbps(40ULL), 85 }, 86 [MLX5E_40GBASE_KR4][MLX5E_KR4] = { 87 .subtype = IFM_40G_KR4, 88 .baudrate = IF_Gbps(40ULL), 89 }, 90 [MLX5E_56GBASE_R4][MLX5E_R] = { 91 .subtype = IFM_56G_R4, 92 .baudrate = IF_Gbps(56ULL), 93 }, 94 [MLX5E_10GBASE_CR][MLX5E_CR1] = { 95 .subtype = IFM_10G_CR1, 96 .baudrate = IF_Gbps(10ULL), 97 }, 98 [MLX5E_10GBASE_SR][MLX5E_SR] = { 99 .subtype = IFM_10G_SR, 100 .baudrate = IF_Gbps(10ULL), 101 }, 102 [MLX5E_10GBASE_ER_LR][MLX5E_ER] = { 103 .subtype = IFM_10G_ER, 104 .baudrate = IF_Gbps(10ULL), 105 }, 106 [MLX5E_10GBASE_ER_LR][MLX5E_LR] = { 107 .subtype = IFM_10G_LR, 108 .baudrate = IF_Gbps(10ULL), 109 }, 110 [MLX5E_40GBASE_SR4][MLX5E_SR4] = { 111 .subtype = IFM_40G_SR4, 112 .baudrate = IF_Gbps(40ULL), 113 }, 114 [MLX5E_40GBASE_LR4_ER4][MLX5E_LR4] = { 115 .subtype = IFM_40G_LR4, 116 .baudrate = IF_Gbps(40ULL), 117 }, 118 [MLX5E_40GBASE_LR4_ER4][MLX5E_ER4] = { 119 .subtype = IFM_40G_ER4, 120 .baudrate = IF_Gbps(40ULL), 121 }, 122 [MLX5E_100GBASE_CR4][MLX5E_CR4] = { 123 .subtype = IFM_100G_CR4, 124 .baudrate = IF_Gbps(100ULL), 125 }, 126 [MLX5E_100GBASE_SR4][MLX5E_SR4] = { 127 .subtype = IFM_100G_SR4, 128 .baudrate = IF_Gbps(100ULL), 129 }, 130 [MLX5E_100GBASE_KR4][MLX5E_KR4] = { 131 .subtype = IFM_100G_KR4, 132 .baudrate = IF_Gbps(100ULL), 133 }, 134 [MLX5E_100GBASE_LR4][MLX5E_LR4] = { 135 .subtype = IFM_100G_LR4, 136 .baudrate = IF_Gbps(100ULL), 137 }, 138 [MLX5E_100BASE_TX][MLX5E_TX] = { 139 .subtype = IFM_100_TX, 140 .baudrate = IF_Mbps(100ULL), 141 }, 142 [MLX5E_1000BASE_T][MLX5E_T] = { 143 .subtype = IFM_1000_T, 144 .baudrate = IF_Mbps(1000ULL), 145 }, 146 [MLX5E_10GBASE_T][MLX5E_T] = { 147 .subtype = IFM_10G_T, 148 .baudrate = IF_Gbps(10ULL), 149 }, 150 [MLX5E_25GBASE_CR][MLX5E_CR] = { 151 .subtype = IFM_25G_CR, 152 .baudrate = IF_Gbps(25ULL), 153 }, 154 [MLX5E_25GBASE_KR][MLX5E_KR] = { 155 .subtype = IFM_25G_KR, 156 .baudrate = IF_Gbps(25ULL), 157 }, 158 [MLX5E_25GBASE_SR][MLX5E_SR] = { 159 .subtype = IFM_25G_SR, 160 .baudrate = IF_Gbps(25ULL), 161 }, 162 [MLX5E_50GBASE_CR2][MLX5E_CR2] = { 163 .subtype = IFM_50G_CR2, 164 .baudrate = IF_Gbps(50ULL), 165 }, 166 [MLX5E_50GBASE_KR2][MLX5E_KR2] = { 167 .subtype = IFM_50G_KR2, 168 .baudrate = IF_Gbps(50ULL), 169 }, 170 }; 171 172 static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = { 173 [MLX5E_SGMII_100M][MLX5E_SGMII] = { 174 .subtype = IFM_100_SGMII, 175 .baudrate = IF_Mbps(100), 176 }, 177 [MLX5E_1000BASE_X_SGMII][MLX5E_KX] = { 178 .subtype = IFM_1000_KX, 179 .baudrate = IF_Mbps(1000), 180 }, 181 [MLX5E_1000BASE_X_SGMII][MLX5E_CX_SGMII] = { 182 .subtype = IFM_1000_CX_SGMII, 183 .baudrate = IF_Mbps(1000), 184 }, 185 [MLX5E_1000BASE_X_SGMII][MLX5E_CX] = { 186 .subtype = IFM_1000_CX, 187 .baudrate = IF_Mbps(1000), 188 }, 189 [MLX5E_1000BASE_X_SGMII][MLX5E_LX] = { 190 .subtype = IFM_1000_LX, 191 .baudrate = IF_Mbps(1000), 192 }, 193 [MLX5E_1000BASE_X_SGMII][MLX5E_SX] = { 194 .subtype = IFM_1000_SX, 195 .baudrate = IF_Mbps(1000), 196 }, 197 [MLX5E_1000BASE_X_SGMII][MLX5E_T] = { 198 .subtype = IFM_1000_T, 199 .baudrate = IF_Mbps(1000), 200 }, 201 [MLX5E_5GBASE_R][MLX5E_T] = { 202 .subtype = IFM_5000_T, 203 .baudrate = IF_Mbps(5000), 204 }, 205 [MLX5E_5GBASE_R][MLX5E_KR] = { 206 .subtype = IFM_5000_KR, 207 .baudrate = IF_Mbps(5000), 208 }, 209 [MLX5E_5GBASE_R][MLX5E_KR1] = { 210 .subtype = IFM_5000_KR1, 211 .baudrate = IF_Mbps(5000), 212 }, 213 [MLX5E_5GBASE_R][MLX5E_KR_S] = { 214 .subtype = IFM_5000_KR_S, 215 .baudrate = IF_Mbps(5000), 216 }, 217 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_ER] = { 218 .subtype = IFM_10G_ER, 219 .baudrate = IF_Gbps(10ULL), 220 }, 221 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_KR] = { 222 .subtype = IFM_10G_KR, 223 .baudrate = IF_Gbps(10ULL), 224 }, 225 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_LR] = { 226 .subtype = IFM_10G_LR, 227 .baudrate = IF_Gbps(10ULL), 228 }, 229 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_SR] = { 230 .subtype = IFM_10G_SR, 231 .baudrate = IF_Gbps(10ULL), 232 }, 233 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_T] = { 234 .subtype = IFM_10G_T, 235 .baudrate = IF_Gbps(10ULL), 236 }, 237 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_AOC] = { 238 .subtype = IFM_10G_AOC, 239 .baudrate = IF_Gbps(10ULL), 240 }, 241 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CR1] = { 242 .subtype = IFM_10G_CR1, 243 .baudrate = IF_Gbps(10ULL), 244 }, 245 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CR4] = { 246 .subtype = IFM_40G_CR4, 247 .baudrate = IF_Gbps(40ULL), 248 }, 249 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_KR4] = { 250 .subtype = IFM_40G_KR4, 251 .baudrate = IF_Gbps(40ULL), 252 }, 253 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_LR4] = { 254 .subtype = IFM_40G_LR4, 255 .baudrate = IF_Gbps(40ULL), 256 }, 257 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_SR4] = { 258 .subtype = IFM_40G_SR4, 259 .baudrate = IF_Gbps(40ULL), 260 }, 261 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_ER4] = { 262 .subtype = IFM_40G_ER4, 263 .baudrate = IF_Gbps(40ULL), 264 }, 265 266 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR] = { 267 .subtype = IFM_25G_CR, 268 .baudrate = IF_Gbps(25ULL), 269 }, 270 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR] = { 271 .subtype = IFM_25G_KR, 272 .baudrate = IF_Gbps(25ULL), 273 }, 274 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_SR] = { 275 .subtype = IFM_25G_SR, 276 .baudrate = IF_Gbps(25ULL), 277 }, 278 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_ACC] = { 279 .subtype = IFM_25G_ACC, 280 .baudrate = IF_Gbps(25ULL), 281 }, 282 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_AOC] = { 283 .subtype = IFM_25G_AOC, 284 .baudrate = IF_Gbps(25ULL), 285 }, 286 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR1] = { 287 .subtype = IFM_25G_CR1, 288 .baudrate = IF_Gbps(25ULL), 289 }, 290 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR_S] = { 291 .subtype = IFM_25G_CR_S, 292 .baudrate = IF_Gbps(25ULL), 293 }, 294 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR1] = { 295 .subtype = IFM_5000_KR1, 296 .baudrate = IF_Gbps(25ULL), 297 }, 298 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR_S] = { 299 .subtype = IFM_25G_KR_S, 300 .baudrate = IF_Gbps(25ULL), 301 }, 302 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_LR] = { 303 .subtype = IFM_25G_LR, 304 .baudrate = IF_Gbps(25ULL), 305 }, 306 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_T] = { 307 .subtype = IFM_25G_T, 308 .baudrate = IF_Gbps(25ULL), 309 }, 310 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CR2] = { 311 .subtype = IFM_50G_CR2, 312 .baudrate = IF_Gbps(50ULL), 313 }, 314 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_KR2] = { 315 .subtype = IFM_50G_KR2, 316 .baudrate = IF_Gbps(50ULL), 317 }, 318 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_SR2] = { 319 .subtype = IFM_50G_SR2, 320 .baudrate = IF_Gbps(50ULL), 321 }, 322 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_LR2] = { 323 .subtype = IFM_50G_LR2, 324 .baudrate = IF_Gbps(50ULL), 325 }, 326 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_LR] = { 327 .subtype = IFM_50G_LR, 328 .baudrate = IF_Gbps(50ULL), 329 }, 330 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_SR] = { 331 .subtype = IFM_50G_SR, 332 .baudrate = IF_Gbps(50ULL), 333 }, 334 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CP] = { 335 .subtype = IFM_50G_CP, 336 .baudrate = IF_Gbps(50ULL), 337 }, 338 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_FR] = { 339 .subtype = IFM_50G_FR, 340 .baudrate = IF_Gbps(50ULL), 341 }, 342 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_KR_PAM4] = { 343 .subtype = IFM_50G_KR_PAM4, 344 .baudrate = IF_Gbps(50ULL), 345 }, 346 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CR4] = { 347 .subtype = IFM_100G_CR4, 348 .baudrate = IF_Gbps(100ULL), 349 }, 350 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_KR4] = { 351 .subtype = IFM_100G_KR4, 352 .baudrate = IF_Gbps(100ULL), 353 }, 354 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_LR4] = { 355 .subtype = IFM_100G_LR4, 356 .baudrate = IF_Gbps(100ULL), 357 }, 358 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_SR4] = { 359 .subtype = IFM_100G_SR4, 360 .baudrate = IF_Gbps(100ULL), 361 }, 362 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_SR2] = { 363 .subtype = IFM_100G_SR2, 364 .baudrate = IF_Gbps(100ULL), 365 }, 366 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CP2] = { 367 .subtype = IFM_100G_CP2, 368 .baudrate = IF_Gbps(100ULL), 369 }, 370 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_KR2_PAM4] = { 371 .subtype = IFM_100G_KR2_PAM4, 372 .baudrate = IF_Gbps(100ULL), 373 }, 374 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_DR4] = { 375 .subtype = IFM_200G_DR4, 376 .baudrate = IF_Gbps(200ULL), 377 }, 378 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_LR4] = { 379 .subtype = IFM_200G_LR4, 380 .baudrate = IF_Gbps(200ULL), 381 }, 382 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_SR4] = { 383 .subtype = IFM_200G_SR4, 384 .baudrate = IF_Gbps(200ULL), 385 }, 386 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_FR4] = { 387 .subtype = IFM_200G_FR4, 388 .baudrate = IF_Gbps(200ULL), 389 }, 390 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CR4_PAM4] = { 391 .subtype = IFM_200G_CR4_PAM4, 392 .baudrate = IF_Gbps(200ULL), 393 }, 394 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_KR4_PAM4] = { 395 .subtype = IFM_200G_KR4_PAM4, 396 .baudrate = IF_Gbps(200ULL), 397 }, 398 }; 399 400 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet"); 401 402 static void 403 mlx5e_update_carrier(struct mlx5e_priv *priv) 404 { 405 struct mlx5_core_dev *mdev = priv->mdev; 406 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 407 u32 eth_proto_oper; 408 int error; 409 u8 port_state; 410 u8 is_er_type; 411 u8 i, j; 412 bool ext; 413 struct media media_entry = {}; 414 415 port_state = mlx5_query_vport_state(mdev, 416 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0); 417 418 if (port_state == VPORT_STATE_UP) { 419 priv->media_status_last |= IFM_ACTIVE; 420 } else { 421 priv->media_status_last &= ~IFM_ACTIVE; 422 priv->media_active_last = IFM_ETHER; 423 if_link_state_change(priv->ifp, LINK_STATE_DOWN); 424 return; 425 } 426 427 error = mlx5_query_port_ptys(mdev, out, sizeof(out), 428 MLX5_PTYS_EN, 1); 429 if (error) { 430 priv->media_active_last = IFM_ETHER; 431 priv->ifp->if_baudrate = 1; 432 mlx5_en_err(priv->ifp, "query port ptys failed: 0x%x\n", 433 error); 434 return; 435 } 436 437 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet); 438 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 439 eth_proto_oper); 440 441 i = ilog2(eth_proto_oper); 442 443 for (j = 0; j != MLX5E_LINK_MODES_NUMBER; j++) { 444 media_entry = ext ? mlx5e_ext_mode_table[i][j] : 445 mlx5e_mode_table[i][j]; 446 if (media_entry.baudrate != 0) 447 break; 448 } 449 450 if (media_entry.subtype == 0) { 451 mlx5_en_err(priv->ifp, 452 "Could not find operational media subtype\n"); 453 return; 454 } 455 456 switch (media_entry.subtype) { 457 case IFM_10G_ER: 458 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type); 459 if (error != 0) { 460 mlx5_en_err(priv->ifp, 461 "query port pddr failed: %d\n", error); 462 } 463 if (error != 0 || is_er_type == 0) 464 media_entry.subtype = IFM_10G_LR; 465 break; 466 case IFM_40G_LR4: 467 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type); 468 if (error != 0) { 469 mlx5_en_err(priv->ifp, 470 "query port pddr failed: %d\n", error); 471 } 472 if (error == 0 && is_er_type != 0) 473 media_entry.subtype = IFM_40G_ER4; 474 break; 475 } 476 priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX; 477 priv->ifp->if_baudrate = media_entry.baudrate; 478 479 if_link_state_change(priv->ifp, LINK_STATE_UP); 480 } 481 482 static void 483 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr) 484 { 485 struct mlx5e_priv *priv = dev->if_softc; 486 487 ifmr->ifm_status = priv->media_status_last; 488 ifmr->ifm_active = priv->media_active_last | 489 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) | 490 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0); 491 492 } 493 494 static u32 495 mlx5e_find_link_mode(u32 subtype, bool ext) 496 { 497 u32 i; 498 u32 j; 499 u32 link_mode = 0; 500 u32 speeds_num = 0; 501 struct media media_entry = {}; 502 503 switch (subtype) { 504 case IFM_10G_LR: 505 subtype = IFM_10G_ER; 506 break; 507 case IFM_40G_ER4: 508 subtype = IFM_40G_LR4; 509 break; 510 } 511 512 speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER : 513 MLX5E_LINK_SPEEDS_NUMBER; 514 515 for (i = 0; i != speeds_num; i++) { 516 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) { 517 media_entry = ext ? mlx5e_ext_mode_table[i][j] : 518 mlx5e_mode_table[i][j]; 519 if (media_entry.baudrate == 0) 520 continue; 521 if (media_entry.subtype == subtype) { 522 link_mode |= MLX5E_PROT_MASK(i); 523 } 524 } 525 } 526 527 return (link_mode); 528 } 529 530 static int 531 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv) 532 { 533 return (mlx5_set_port_pause_and_pfc(priv->mdev, 1, 534 priv->params.rx_pauseframe_control, 535 priv->params.tx_pauseframe_control, 536 priv->params.rx_priority_flow_control, 537 priv->params.tx_priority_flow_control)); 538 } 539 540 static int 541 mlx5e_set_port_pfc(struct mlx5e_priv *priv) 542 { 543 int error; 544 545 if (priv->gone != 0) { 546 error = -ENXIO; 547 } else if (priv->params.rx_pauseframe_control || 548 priv->params.tx_pauseframe_control) { 549 mlx5_en_err(priv->ifp, 550 "Global pauseframes must be disabled before enabling PFC.\n"); 551 error = -EINVAL; 552 } else { 553 error = mlx5e_set_port_pause_and_pfc(priv); 554 } 555 return (error); 556 } 557 558 static int 559 mlx5e_media_change(struct ifnet *dev) 560 { 561 struct mlx5e_priv *priv = dev->if_softc; 562 struct mlx5_core_dev *mdev = priv->mdev; 563 u32 eth_proto_cap; 564 u32 link_mode; 565 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 566 int was_opened; 567 int locked; 568 int error; 569 bool ext; 570 571 locked = PRIV_LOCKED(priv); 572 if (!locked) 573 PRIV_LOCK(priv); 574 575 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) { 576 error = EINVAL; 577 goto done; 578 } 579 580 error = mlx5_query_port_ptys(mdev, out, sizeof(out), 581 MLX5_PTYS_EN, 1); 582 if (error != 0) { 583 mlx5_en_err(dev, "Query port media capability failed\n"); 584 goto done; 585 } 586 587 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet); 588 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext); 589 590 /* query supported capabilities */ 591 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 592 eth_proto_capability); 593 594 /* check for autoselect */ 595 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) { 596 link_mode = eth_proto_cap; 597 if (link_mode == 0) { 598 mlx5_en_err(dev, "Port media capability is zero\n"); 599 error = EINVAL; 600 goto done; 601 } 602 } else { 603 link_mode = link_mode & eth_proto_cap; 604 if (link_mode == 0) { 605 mlx5_en_err(dev, "Not supported link mode requested\n"); 606 error = EINVAL; 607 goto done; 608 } 609 } 610 if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) { 611 /* check if PFC is enabled */ 612 if (priv->params.rx_priority_flow_control || 613 priv->params.tx_priority_flow_control) { 614 mlx5_en_err(dev, "PFC must be disabled before enabling global pauseframes.\n"); 615 error = EINVAL; 616 goto done; 617 } 618 } 619 /* update pauseframe control bits */ 620 priv->params.rx_pauseframe_control = 621 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0; 622 priv->params.tx_pauseframe_control = 623 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0; 624 625 /* check if device is opened */ 626 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 627 628 /* reconfigure the hardware */ 629 mlx5_set_port_status(mdev, MLX5_PORT_DOWN); 630 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext); 631 error = -mlx5e_set_port_pause_and_pfc(priv); 632 if (was_opened) 633 mlx5_set_port_status(mdev, MLX5_PORT_UP); 634 635 done: 636 if (!locked) 637 PRIV_UNLOCK(priv); 638 return (error); 639 } 640 641 static void 642 mlx5e_update_carrier_work(struct work_struct *work) 643 { 644 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 645 update_carrier_work); 646 647 PRIV_LOCK(priv); 648 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) 649 mlx5e_update_carrier(priv); 650 PRIV_UNLOCK(priv); 651 } 652 653 #define MLX5E_PCIE_PERF_GET_64(a,b,c,d,e,f) \ 654 s_debug->c = MLX5_GET64(mpcnt_reg, out, counter_set.f.c); 655 656 #define MLX5E_PCIE_PERF_GET_32(a,b,c,d,e,f) \ 657 s_debug->c = MLX5_GET(mpcnt_reg, out, counter_set.f.c); 658 659 static void 660 mlx5e_update_pcie_counters(struct mlx5e_priv *priv) 661 { 662 struct mlx5_core_dev *mdev = priv->mdev; 663 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug; 664 const unsigned sz = MLX5_ST_SZ_BYTES(mpcnt_reg); 665 void *out; 666 void *in; 667 int err; 668 669 /* allocate firmware request structures */ 670 in = mlx5_vzalloc(sz); 671 out = mlx5_vzalloc(sz); 672 if (in == NULL || out == NULL) 673 goto free_out; 674 675 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP); 676 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 677 if (err != 0) 678 goto free_out; 679 680 MLX5E_PCIE_PERFORMANCE_COUNTERS_64(MLX5E_PCIE_PERF_GET_64) 681 MLX5E_PCIE_PERFORMANCE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 682 683 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP); 684 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 685 if (err != 0) 686 goto free_out; 687 688 MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 689 690 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_LANE_COUNTERS_GROUP); 691 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 692 if (err != 0) 693 goto free_out; 694 695 MLX5E_PCIE_LANE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 696 697 free_out: 698 /* free firmware request structures */ 699 kvfree(in); 700 kvfree(out); 701 } 702 703 /* 704 * This function reads the physical port counters from the firmware 705 * using a pre-defined layout defined by various MLX5E_PPORT_XXX() 706 * macros. The output is converted from big-endian 64-bit values into 707 * host endian ones and stored in the "priv->stats.pport" structure. 708 */ 709 static void 710 mlx5e_update_pport_counters(struct mlx5e_priv *priv) 711 { 712 struct mlx5_core_dev *mdev = priv->mdev; 713 struct mlx5e_pport_stats *s = &priv->stats.pport; 714 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug; 715 u32 *in; 716 u32 *out; 717 const u64 *ptr; 718 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 719 unsigned x; 720 unsigned y; 721 unsigned z; 722 723 /* allocate firmware request structures */ 724 in = mlx5_vzalloc(sz); 725 out = mlx5_vzalloc(sz); 726 if (in == NULL || out == NULL) 727 goto free_out; 728 729 /* 730 * Get pointer to the 64-bit counter set which is located at a 731 * fixed offset in the output firmware request structure: 732 */ 733 ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set); 734 735 MLX5_SET(ppcnt_reg, in, local_port, 1); 736 737 /* read IEEE802_3 counter group using predefined counter layout */ 738 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP); 739 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 740 for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM; 741 x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++) 742 s->arg[y] = be64toh(ptr[x]); 743 744 /* read RFC2819 counter group using predefined counter layout */ 745 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP); 746 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 747 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++) 748 s->arg[y] = be64toh(ptr[x]); 749 750 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM + 751 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++) 752 s_debug->arg[y] = be64toh(ptr[x]); 753 754 /* read RFC2863 counter group using predefined counter layout */ 755 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP); 756 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 757 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++) 758 s_debug->arg[y] = be64toh(ptr[x]); 759 760 /* read physical layer stats counter group using predefined counter layout */ 761 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP); 762 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 763 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++) 764 s_debug->arg[y] = be64toh(ptr[x]); 765 766 /* read Extended Ethernet counter group using predefined counter layout */ 767 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP); 768 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 769 for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++) 770 s_debug->arg[y] = be64toh(ptr[x]); 771 772 /* read Extended Statistical Group */ 773 if (MLX5_CAP_GEN(mdev, pcam_reg) && 774 MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) && 775 MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) { 776 /* read Extended Statistical counter group using predefined counter layout */ 777 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP); 778 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 779 780 for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++) 781 s_debug->arg[y] = be64toh(ptr[x]); 782 } 783 784 /* read PCIE counters */ 785 mlx5e_update_pcie_counters(priv); 786 787 /* read per-priority counters */ 788 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP); 789 790 /* iterate all the priorities */ 791 for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) { 792 MLX5_SET(ppcnt_reg, in, prio_tc, z); 793 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 794 795 /* read per priority stats counter group using predefined counter layout */ 796 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM / 797 MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++) 798 s->arg[y] = be64toh(ptr[x]); 799 } 800 801 free_out: 802 /* free firmware request structures */ 803 kvfree(in); 804 kvfree(out); 805 } 806 807 static void 808 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv) 809 { 810 u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {}; 811 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {}; 812 813 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard)) 814 return; 815 816 MLX5_SET(query_vnic_env_in, in, opcode, 817 MLX5_CMD_OP_QUERY_VNIC_ENV); 818 MLX5_SET(query_vnic_env_in, in, op_mod, 0); 819 MLX5_SET(query_vnic_env_in, in, other_vport, 0); 820 821 if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0) 822 return; 823 824 priv->stats.vport.rx_steer_missed_packets = 825 MLX5_GET64(query_vnic_env_out, out, 826 vport_env.nic_receive_steering_discard); 827 } 828 829 /* 830 * This function is called regularly to collect all statistics 831 * counters from the firmware. The values can be viewed through the 832 * sysctl interface. Execution is serialized using the priv's global 833 * configuration lock. 834 */ 835 static void 836 mlx5e_update_stats_locked(struct mlx5e_priv *priv) 837 { 838 struct mlx5_core_dev *mdev = priv->mdev; 839 struct mlx5e_vport_stats *s = &priv->stats.vport; 840 struct mlx5e_sq_stats *sq_stats; 841 struct buf_ring *sq_br; 842 #if (__FreeBSD_version < 1100000) 843 struct ifnet *ifp = priv->ifp; 844 #endif 845 846 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)]; 847 u32 *out; 848 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out); 849 u64 tso_packets = 0; 850 u64 tso_bytes = 0; 851 u64 tx_queue_dropped = 0; 852 u64 tx_defragged = 0; 853 u64 tx_offload_none = 0; 854 u64 lro_packets = 0; 855 u64 lro_bytes = 0; 856 u64 sw_lro_queued = 0; 857 u64 sw_lro_flushed = 0; 858 u64 rx_csum_none = 0; 859 u64 rx_wqe_err = 0; 860 u64 rx_packets = 0; 861 u64 rx_bytes = 0; 862 u32 rx_out_of_buffer = 0; 863 int error; 864 int i; 865 int j; 866 867 out = mlx5_vzalloc(outlen); 868 if (out == NULL) 869 goto free_out; 870 871 /* Collect firts the SW counters and then HW for consistency */ 872 for (i = 0; i < priv->params.num_channels; i++) { 873 struct mlx5e_channel *pch = priv->channel + i; 874 struct mlx5e_rq *rq = &pch->rq; 875 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats; 876 877 /* collect stats from LRO */ 878 rq_stats->sw_lro_queued = rq->lro.lro_queued; 879 rq_stats->sw_lro_flushed = rq->lro.lro_flushed; 880 sw_lro_queued += rq_stats->sw_lro_queued; 881 sw_lro_flushed += rq_stats->sw_lro_flushed; 882 lro_packets += rq_stats->lro_packets; 883 lro_bytes += rq_stats->lro_bytes; 884 rx_csum_none += rq_stats->csum_none; 885 rx_wqe_err += rq_stats->wqe_err; 886 rx_packets += rq_stats->packets; 887 rx_bytes += rq_stats->bytes; 888 889 for (j = 0; j < priv->num_tc; j++) { 890 sq_stats = &pch->sq[j].stats; 891 sq_br = pch->sq[j].br; 892 893 tso_packets += sq_stats->tso_packets; 894 tso_bytes += sq_stats->tso_bytes; 895 tx_queue_dropped += sq_stats->dropped; 896 if (sq_br != NULL) 897 tx_queue_dropped += sq_br->br_drops; 898 tx_defragged += sq_stats->defragged; 899 tx_offload_none += sq_stats->csum_offload_none; 900 } 901 } 902 903 /* update counters */ 904 s->tso_packets = tso_packets; 905 s->tso_bytes = tso_bytes; 906 s->tx_queue_dropped = tx_queue_dropped; 907 s->tx_defragged = tx_defragged; 908 s->lro_packets = lro_packets; 909 s->lro_bytes = lro_bytes; 910 s->sw_lro_queued = sw_lro_queued; 911 s->sw_lro_flushed = sw_lro_flushed; 912 s->rx_csum_none = rx_csum_none; 913 s->rx_wqe_err = rx_wqe_err; 914 s->rx_packets = rx_packets; 915 s->rx_bytes = rx_bytes; 916 917 mlx5e_grp_vnic_env_update_stats(priv); 918 919 /* HW counters */ 920 memset(in, 0, sizeof(in)); 921 922 MLX5_SET(query_vport_counter_in, in, opcode, 923 MLX5_CMD_OP_QUERY_VPORT_COUNTER); 924 MLX5_SET(query_vport_counter_in, in, op_mod, 0); 925 MLX5_SET(query_vport_counter_in, in, other_vport, 0); 926 927 memset(out, 0, outlen); 928 929 /* get number of out-of-buffer drops first */ 930 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 && 931 mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id, 932 &rx_out_of_buffer) == 0) { 933 s->rx_out_of_buffer = rx_out_of_buffer; 934 } 935 936 /* get port statistics */ 937 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) { 938 #define MLX5_GET_CTR(out, x) \ 939 MLX5_GET64(query_vport_counter_out, out, x) 940 941 s->rx_error_packets = 942 MLX5_GET_CTR(out, received_errors.packets); 943 s->rx_error_bytes = 944 MLX5_GET_CTR(out, received_errors.octets); 945 s->tx_error_packets = 946 MLX5_GET_CTR(out, transmit_errors.packets); 947 s->tx_error_bytes = 948 MLX5_GET_CTR(out, transmit_errors.octets); 949 950 s->rx_unicast_packets = 951 MLX5_GET_CTR(out, received_eth_unicast.packets); 952 s->rx_unicast_bytes = 953 MLX5_GET_CTR(out, received_eth_unicast.octets); 954 s->tx_unicast_packets = 955 MLX5_GET_CTR(out, transmitted_eth_unicast.packets); 956 s->tx_unicast_bytes = 957 MLX5_GET_CTR(out, transmitted_eth_unicast.octets); 958 959 s->rx_multicast_packets = 960 MLX5_GET_CTR(out, received_eth_multicast.packets); 961 s->rx_multicast_bytes = 962 MLX5_GET_CTR(out, received_eth_multicast.octets); 963 s->tx_multicast_packets = 964 MLX5_GET_CTR(out, transmitted_eth_multicast.packets); 965 s->tx_multicast_bytes = 966 MLX5_GET_CTR(out, transmitted_eth_multicast.octets); 967 968 s->rx_broadcast_packets = 969 MLX5_GET_CTR(out, received_eth_broadcast.packets); 970 s->rx_broadcast_bytes = 971 MLX5_GET_CTR(out, received_eth_broadcast.octets); 972 s->tx_broadcast_packets = 973 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets); 974 s->tx_broadcast_bytes = 975 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets); 976 977 s->tx_packets = s->tx_unicast_packets + 978 s->tx_multicast_packets + s->tx_broadcast_packets; 979 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes + 980 s->tx_broadcast_bytes; 981 982 /* Update calculated offload counters */ 983 s->tx_csum_offload = s->tx_packets - tx_offload_none; 984 s->rx_csum_good = s->rx_packets - s->rx_csum_none; 985 } 986 987 /* Get physical port counters */ 988 mlx5e_update_pport_counters(priv); 989 990 s->tx_jumbo_packets = 991 priv->stats.port_stats_debug.tx_stat_p1519to2047octets + 992 priv->stats.port_stats_debug.tx_stat_p2048to4095octets + 993 priv->stats.port_stats_debug.tx_stat_p4096to8191octets + 994 priv->stats.port_stats_debug.tx_stat_p8192to10239octets; 995 996 #if (__FreeBSD_version < 1100000) 997 /* no get_counters interface in fbsd 10 */ 998 ifp->if_ipackets = s->rx_packets; 999 ifp->if_ierrors = priv->stats.pport.in_range_len_errors + 1000 priv->stats.pport.out_of_range_len + 1001 priv->stats.pport.too_long_errors + 1002 priv->stats.pport.check_seq_err + 1003 priv->stats.pport.alignment_err; 1004 ifp->if_iqdrops = s->rx_out_of_buffer; 1005 ifp->if_opackets = s->tx_packets; 1006 ifp->if_oerrors = priv->stats.port_stats_debug.out_discards; 1007 ifp->if_snd.ifq_drops = s->tx_queue_dropped; 1008 ifp->if_ibytes = s->rx_bytes; 1009 ifp->if_obytes = s->tx_bytes; 1010 ifp->if_collisions = 1011 priv->stats.pport.collisions; 1012 #endif 1013 1014 free_out: 1015 kvfree(out); 1016 1017 /* Update diagnostics, if any */ 1018 if (priv->params_ethtool.diag_pci_enable || 1019 priv->params_ethtool.diag_general_enable) { 1020 error = mlx5_core_get_diagnostics_full(mdev, 1021 priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL, 1022 priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL); 1023 if (error != 0) 1024 mlx5_en_err(priv->ifp, 1025 "Failed reading diagnostics: %d\n", error); 1026 } 1027 1028 /* Update FEC, if any */ 1029 error = mlx5e_fec_update(priv); 1030 if (error != 0 && error != EOPNOTSUPP) { 1031 mlx5_en_err(priv->ifp, 1032 "Updating FEC failed: %d\n", error); 1033 } 1034 } 1035 1036 static void 1037 mlx5e_update_stats_work(struct work_struct *work) 1038 { 1039 struct mlx5e_priv *priv; 1040 1041 priv = container_of(work, struct mlx5e_priv, update_stats_work); 1042 PRIV_LOCK(priv); 1043 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 && 1044 !test_bit(MLX5_INTERFACE_STATE_TEARDOWN, &priv->mdev->intf_state)) 1045 mlx5e_update_stats_locked(priv); 1046 PRIV_UNLOCK(priv); 1047 } 1048 1049 static void 1050 mlx5e_update_stats(void *arg) 1051 { 1052 struct mlx5e_priv *priv = arg; 1053 1054 queue_work(priv->wq, &priv->update_stats_work); 1055 1056 callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv); 1057 } 1058 1059 static void 1060 mlx5e_async_event_sub(struct mlx5e_priv *priv, 1061 enum mlx5_dev_event event) 1062 { 1063 switch (event) { 1064 case MLX5_DEV_EVENT_PORT_UP: 1065 case MLX5_DEV_EVENT_PORT_DOWN: 1066 queue_work(priv->wq, &priv->update_carrier_work); 1067 break; 1068 1069 default: 1070 break; 1071 } 1072 } 1073 1074 static void 1075 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv, 1076 enum mlx5_dev_event event, unsigned long param) 1077 { 1078 struct mlx5e_priv *priv = vpriv; 1079 1080 mtx_lock(&priv->async_events_mtx); 1081 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state)) 1082 mlx5e_async_event_sub(priv, event); 1083 mtx_unlock(&priv->async_events_mtx); 1084 } 1085 1086 static void 1087 mlx5e_enable_async_events(struct mlx5e_priv *priv) 1088 { 1089 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 1090 } 1091 1092 static void 1093 mlx5e_disable_async_events(struct mlx5e_priv *priv) 1094 { 1095 mtx_lock(&priv->async_events_mtx); 1096 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 1097 mtx_unlock(&priv->async_events_mtx); 1098 } 1099 1100 static void mlx5e_calibration_callout(void *arg); 1101 static int mlx5e_calibration_duration = 20; 1102 static int mlx5e_fast_calibration = 1; 1103 static int mlx5e_normal_calibration = 30; 1104 1105 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW, 0, 1106 "MLX5 timestamp calibration parameteres"); 1107 1108 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN, 1109 &mlx5e_calibration_duration, 0, 1110 "Duration of initial calibration"); 1111 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN, 1112 &mlx5e_fast_calibration, 0, 1113 "Recalibration interval during initial calibration"); 1114 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN, 1115 &mlx5e_normal_calibration, 0, 1116 "Recalibration interval during normal operations"); 1117 1118 /* 1119 * Ignites the calibration process. 1120 */ 1121 static void 1122 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv) 1123 { 1124 1125 if (priv->clbr_done == 0) 1126 mlx5e_calibration_callout(priv); 1127 else 1128 callout_reset_curcpu(&priv->tstmp_clbr, (priv->clbr_done < 1129 mlx5e_calibration_duration ? mlx5e_fast_calibration : 1130 mlx5e_normal_calibration) * hz, mlx5e_calibration_callout, 1131 priv); 1132 } 1133 1134 static uint64_t 1135 mlx5e_timespec2usec(const struct timespec *ts) 1136 { 1137 1138 return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec); 1139 } 1140 1141 static uint64_t 1142 mlx5e_hw_clock(struct mlx5e_priv *priv) 1143 { 1144 struct mlx5_init_seg *iseg; 1145 uint32_t hw_h, hw_h1, hw_l; 1146 1147 iseg = priv->mdev->iseg; 1148 do { 1149 hw_h = ioread32be(&iseg->internal_timer_h); 1150 hw_l = ioread32be(&iseg->internal_timer_l); 1151 hw_h1 = ioread32be(&iseg->internal_timer_h); 1152 } while (hw_h1 != hw_h); 1153 return (((uint64_t)hw_h << 32) | hw_l); 1154 } 1155 1156 /* 1157 * The calibration callout, it runs either in the context of the 1158 * thread which enables calibration, or in callout. It takes the 1159 * snapshot of system and adapter clocks, then advances the pointers to 1160 * the calibration point to allow rx path to read the consistent data 1161 * lockless. 1162 */ 1163 static void 1164 mlx5e_calibration_callout(void *arg) 1165 { 1166 struct mlx5e_priv *priv; 1167 struct mlx5e_clbr_point *next, *curr; 1168 struct timespec ts; 1169 int clbr_curr_next; 1170 1171 priv = arg; 1172 curr = &priv->clbr_points[priv->clbr_curr]; 1173 clbr_curr_next = priv->clbr_curr + 1; 1174 if (clbr_curr_next >= nitems(priv->clbr_points)) 1175 clbr_curr_next = 0; 1176 next = &priv->clbr_points[clbr_curr_next]; 1177 1178 next->base_prev = curr->base_curr; 1179 next->clbr_hw_prev = curr->clbr_hw_curr; 1180 1181 next->clbr_hw_curr = mlx5e_hw_clock(priv); 1182 if (((next->clbr_hw_curr - curr->clbr_hw_curr) >> MLX5E_TSTMP_PREC) == 1183 0) { 1184 if (priv->clbr_done != 0) { 1185 mlx5_en_err(priv->ifp, 1186 "HW failed tstmp frozen %#jx %#jx, disabling\n", 1187 next->clbr_hw_curr, curr->clbr_hw_prev); 1188 priv->clbr_done = 0; 1189 } 1190 atomic_store_rel_int(&curr->clbr_gen, 0); 1191 return; 1192 } 1193 1194 nanouptime(&ts); 1195 next->base_curr = mlx5e_timespec2usec(&ts); 1196 1197 curr->clbr_gen = 0; 1198 atomic_thread_fence_rel(); 1199 priv->clbr_curr = clbr_curr_next; 1200 atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen)); 1201 1202 if (priv->clbr_done < mlx5e_calibration_duration) 1203 priv->clbr_done++; 1204 mlx5e_reset_calibration_callout(priv); 1205 } 1206 1207 static const char *mlx5e_rq_stats_desc[] = { 1208 MLX5E_RQ_STATS(MLX5E_STATS_DESC) 1209 }; 1210 1211 static int 1212 mlx5e_create_rq(struct mlx5e_channel *c, 1213 struct mlx5e_rq_param *param, 1214 struct mlx5e_rq *rq) 1215 { 1216 struct mlx5e_priv *priv = c->priv; 1217 struct mlx5_core_dev *mdev = priv->mdev; 1218 char buffer[16]; 1219 void *rqc = param->rqc; 1220 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); 1221 int wq_sz; 1222 int err; 1223 int i; 1224 u32 nsegs, wqe_sz; 1225 1226 err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs); 1227 if (err != 0) 1228 goto done; 1229 1230 /* Create DMA descriptor TAG */ 1231 if ((err = -bus_dma_tag_create( 1232 bus_get_dma_tag(mdev->pdev->dev.bsddev), 1233 1, /* any alignment */ 1234 0, /* no boundary */ 1235 BUS_SPACE_MAXADDR, /* lowaddr */ 1236 BUS_SPACE_MAXADDR, /* highaddr */ 1237 NULL, NULL, /* filter, filterarg */ 1238 nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */ 1239 nsegs, /* nsegments */ 1240 nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */ 1241 0, /* flags */ 1242 NULL, NULL, /* lockfunc, lockfuncarg */ 1243 &rq->dma_tag))) 1244 goto done; 1245 1246 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, 1247 &rq->wq_ctrl); 1248 if (err) 1249 goto err_free_dma_tag; 1250 1251 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR]; 1252 1253 err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs); 1254 if (err != 0) 1255 goto err_rq_wq_destroy; 1256 1257 wq_sz = mlx5_wq_ll_get_size(&rq->wq); 1258 1259 err = -tcp_lro_init_args(&rq->lro, priv->ifp, TCP_LRO_ENTRIES, wq_sz); 1260 if (err) 1261 goto err_rq_wq_destroy; 1262 1263 rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO); 1264 for (i = 0; i != wq_sz; i++) { 1265 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i); 1266 int j; 1267 1268 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map); 1269 if (err != 0) { 1270 while (i--) 1271 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 1272 goto err_rq_mbuf_free; 1273 } 1274 1275 /* set value for constant fields */ 1276 for (j = 0; j < rq->nsegs; j++) 1277 wqe->data[j].lkey = cpu_to_be32(priv->mr.key); 1278 } 1279 1280 INIT_WORK(&rq->dim.work, mlx5e_dim_work); 1281 if (priv->params.rx_cq_moderation_mode < 2) { 1282 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 1283 } else { 1284 void *cqc = container_of(param, 1285 struct mlx5e_channel_param, rq)->rx_cq.cqc; 1286 1287 switch (MLX5_GET(cqc, cqc, cq_period_mode)) { 1288 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE: 1289 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; 1290 break; 1291 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE: 1292 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE; 1293 break; 1294 default: 1295 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 1296 break; 1297 } 1298 } 1299 1300 rq->ifp = priv->ifp; 1301 rq->channel = c; 1302 rq->ix = c->ix; 1303 1304 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix); 1305 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 1306 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM, 1307 rq->stats.arg); 1308 return (0); 1309 1310 err_rq_mbuf_free: 1311 free(rq->mbuf, M_MLX5EN); 1312 tcp_lro_free(&rq->lro); 1313 err_rq_wq_destroy: 1314 mlx5_wq_destroy(&rq->wq_ctrl); 1315 err_free_dma_tag: 1316 bus_dma_tag_destroy(rq->dma_tag); 1317 done: 1318 return (err); 1319 } 1320 1321 static void 1322 mlx5e_destroy_rq(struct mlx5e_rq *rq) 1323 { 1324 int wq_sz; 1325 int i; 1326 1327 /* destroy all sysctl nodes */ 1328 sysctl_ctx_free(&rq->stats.ctx); 1329 1330 /* free leftover LRO packets, if any */ 1331 tcp_lro_free(&rq->lro); 1332 1333 wq_sz = mlx5_wq_ll_get_size(&rq->wq); 1334 for (i = 0; i != wq_sz; i++) { 1335 if (rq->mbuf[i].mbuf != NULL) { 1336 bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map); 1337 m_freem(rq->mbuf[i].mbuf); 1338 } 1339 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 1340 } 1341 free(rq->mbuf, M_MLX5EN); 1342 mlx5_wq_destroy(&rq->wq_ctrl); 1343 bus_dma_tag_destroy(rq->dma_tag); 1344 } 1345 1346 static int 1347 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param) 1348 { 1349 struct mlx5e_channel *c = rq->channel; 1350 struct mlx5e_priv *priv = c->priv; 1351 struct mlx5_core_dev *mdev = priv->mdev; 1352 1353 void *in; 1354 void *rqc; 1355 void *wq; 1356 int inlen; 1357 int err; 1358 1359 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 1360 sizeof(u64) * rq->wq_ctrl.buf.npages; 1361 in = mlx5_vzalloc(inlen); 1362 if (in == NULL) 1363 return (-ENOMEM); 1364 1365 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1366 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1367 1368 memcpy(rqc, param->rqc, sizeof(param->rqc)); 1369 1370 MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn); 1371 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1372 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1373 if (priv->counter_set_id >= 0) 1374 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id); 1375 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - 1376 PAGE_SHIFT); 1377 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); 1378 1379 mlx5_fill_page_array(&rq->wq_ctrl.buf, 1380 (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 1381 1382 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); 1383 1384 kvfree(in); 1385 1386 return (err); 1387 } 1388 1389 static int 1390 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state) 1391 { 1392 struct mlx5e_channel *c = rq->channel; 1393 struct mlx5e_priv *priv = c->priv; 1394 struct mlx5_core_dev *mdev = priv->mdev; 1395 1396 void *in; 1397 void *rqc; 1398 int inlen; 1399 int err; 1400 1401 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 1402 in = mlx5_vzalloc(inlen); 1403 if (in == NULL) 1404 return (-ENOMEM); 1405 1406 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1407 1408 MLX5_SET(modify_rq_in, in, rqn, rq->rqn); 1409 MLX5_SET(modify_rq_in, in, rq_state, curr_state); 1410 MLX5_SET(rqc, rqc, state, next_state); 1411 1412 err = mlx5_core_modify_rq(mdev, in, inlen); 1413 1414 kvfree(in); 1415 1416 return (err); 1417 } 1418 1419 static void 1420 mlx5e_disable_rq(struct mlx5e_rq *rq) 1421 { 1422 struct mlx5e_channel *c = rq->channel; 1423 struct mlx5e_priv *priv = c->priv; 1424 struct mlx5_core_dev *mdev = priv->mdev; 1425 1426 mlx5_core_destroy_rq(mdev, rq->rqn); 1427 } 1428 1429 static int 1430 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq) 1431 { 1432 struct mlx5e_channel *c = rq->channel; 1433 struct mlx5e_priv *priv = c->priv; 1434 struct mlx5_wq_ll *wq = &rq->wq; 1435 int i; 1436 1437 for (i = 0; i < 1000; i++) { 1438 if (wq->cur_sz >= priv->params.min_rx_wqes) 1439 return (0); 1440 1441 msleep(4); 1442 } 1443 return (-ETIMEDOUT); 1444 } 1445 1446 static int 1447 mlx5e_open_rq(struct mlx5e_channel *c, 1448 struct mlx5e_rq_param *param, 1449 struct mlx5e_rq *rq) 1450 { 1451 int err; 1452 1453 err = mlx5e_create_rq(c, param, rq); 1454 if (err) 1455 return (err); 1456 1457 err = mlx5e_enable_rq(rq, param); 1458 if (err) 1459 goto err_destroy_rq; 1460 1461 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 1462 if (err) 1463 goto err_disable_rq; 1464 1465 c->rq.enabled = 1; 1466 1467 return (0); 1468 1469 err_disable_rq: 1470 mlx5e_disable_rq(rq); 1471 err_destroy_rq: 1472 mlx5e_destroy_rq(rq); 1473 1474 return (err); 1475 } 1476 1477 static void 1478 mlx5e_close_rq(struct mlx5e_rq *rq) 1479 { 1480 mtx_lock(&rq->mtx); 1481 rq->enabled = 0; 1482 callout_stop(&rq->watchdog); 1483 mtx_unlock(&rq->mtx); 1484 1485 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 1486 } 1487 1488 static void 1489 mlx5e_close_rq_wait(struct mlx5e_rq *rq) 1490 { 1491 1492 mlx5e_disable_rq(rq); 1493 mlx5e_close_cq(&rq->cq); 1494 cancel_work_sync(&rq->dim.work); 1495 mlx5e_destroy_rq(rq); 1496 } 1497 1498 void 1499 mlx5e_free_sq_db(struct mlx5e_sq *sq) 1500 { 1501 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1502 int x; 1503 1504 for (x = 0; x != wq_sz; x++) { 1505 if (sq->mbuf[x].mbuf != NULL) { 1506 bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map); 1507 m_freem(sq->mbuf[x].mbuf); 1508 } 1509 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 1510 } 1511 free(sq->mbuf, M_MLX5EN); 1512 } 1513 1514 int 1515 mlx5e_alloc_sq_db(struct mlx5e_sq *sq) 1516 { 1517 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1518 int err; 1519 int x; 1520 1521 sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO); 1522 1523 /* Create DMA descriptor MAPs */ 1524 for (x = 0; x != wq_sz; x++) { 1525 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map); 1526 if (err != 0) { 1527 while (x--) 1528 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 1529 free(sq->mbuf, M_MLX5EN); 1530 return (err); 1531 } 1532 } 1533 return (0); 1534 } 1535 1536 static const char *mlx5e_sq_stats_desc[] = { 1537 MLX5E_SQ_STATS(MLX5E_STATS_DESC) 1538 }; 1539 1540 void 1541 mlx5e_update_sq_inline(struct mlx5e_sq *sq) 1542 { 1543 sq->max_inline = sq->priv->params.tx_max_inline; 1544 sq->min_inline_mode = sq->priv->params.tx_min_inline_mode; 1545 1546 /* 1547 * Check if trust state is DSCP or if inline mode is NONE which 1548 * indicates CX-5 or newer hardware. 1549 */ 1550 if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP || 1551 sq->min_inline_mode == MLX5_INLINE_MODE_NONE) { 1552 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert)) 1553 sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN; 1554 else 1555 sq->min_insert_caps = MLX5E_INSERT_NON_VLAN; 1556 } else { 1557 sq->min_insert_caps = 0; 1558 } 1559 } 1560 1561 static void 1562 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c) 1563 { 1564 int i; 1565 1566 for (i = 0; i != priv->num_tc; i++) { 1567 mtx_lock(&c->sq[i].lock); 1568 mlx5e_update_sq_inline(&c->sq[i]); 1569 mtx_unlock(&c->sq[i].lock); 1570 } 1571 } 1572 1573 void 1574 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv) 1575 { 1576 int i; 1577 1578 /* check if channels are closed */ 1579 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 1580 return; 1581 1582 for (i = 0; i < priv->params.num_channels; i++) 1583 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]); 1584 } 1585 1586 static int 1587 mlx5e_create_sq(struct mlx5e_channel *c, 1588 int tc, 1589 struct mlx5e_sq_param *param, 1590 struct mlx5e_sq *sq) 1591 { 1592 struct mlx5e_priv *priv = c->priv; 1593 struct mlx5_core_dev *mdev = priv->mdev; 1594 char buffer[16]; 1595 void *sqc = param->sqc; 1596 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq); 1597 int err; 1598 1599 /* Create DMA descriptor TAG */ 1600 if ((err = -bus_dma_tag_create( 1601 bus_get_dma_tag(mdev->pdev->dev.bsddev), 1602 1, /* any alignment */ 1603 0, /* no boundary */ 1604 BUS_SPACE_MAXADDR, /* lowaddr */ 1605 BUS_SPACE_MAXADDR, /* highaddr */ 1606 NULL, NULL, /* filter, filterarg */ 1607 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */ 1608 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */ 1609 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */ 1610 0, /* flags */ 1611 NULL, NULL, /* lockfunc, lockfuncarg */ 1612 &sq->dma_tag))) 1613 goto done; 1614 1615 err = mlx5_alloc_map_uar(mdev, &sq->uar); 1616 if (err) 1617 goto err_free_dma_tag; 1618 1619 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, 1620 &sq->wq_ctrl); 1621 if (err) 1622 goto err_unmap_free_uar; 1623 1624 sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; 1625 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2; 1626 1627 err = mlx5e_alloc_sq_db(sq); 1628 if (err) 1629 goto err_sq_wq_destroy; 1630 1631 sq->mkey_be = cpu_to_be32(priv->mr.key); 1632 sq->ifp = priv->ifp; 1633 sq->priv = priv; 1634 sq->tc = tc; 1635 1636 mlx5e_update_sq_inline(sq); 1637 1638 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc); 1639 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 1640 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM, 1641 sq->stats.arg); 1642 1643 return (0); 1644 1645 err_sq_wq_destroy: 1646 mlx5_wq_destroy(&sq->wq_ctrl); 1647 1648 err_unmap_free_uar: 1649 mlx5_unmap_free_uar(mdev, &sq->uar); 1650 1651 err_free_dma_tag: 1652 bus_dma_tag_destroy(sq->dma_tag); 1653 done: 1654 return (err); 1655 } 1656 1657 static void 1658 mlx5e_destroy_sq(struct mlx5e_sq *sq) 1659 { 1660 /* destroy all sysctl nodes */ 1661 sysctl_ctx_free(&sq->stats.ctx); 1662 1663 mlx5e_free_sq_db(sq); 1664 mlx5_wq_destroy(&sq->wq_ctrl); 1665 mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar); 1666 bus_dma_tag_destroy(sq->dma_tag); 1667 } 1668 1669 int 1670 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param, 1671 int tis_num) 1672 { 1673 void *in; 1674 void *sqc; 1675 void *wq; 1676 int inlen; 1677 int err; 1678 1679 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1680 sizeof(u64) * sq->wq_ctrl.buf.npages; 1681 in = mlx5_vzalloc(inlen); 1682 if (in == NULL) 1683 return (-ENOMEM); 1684 1685 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1686 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1687 1688 memcpy(sqc, param->sqc, sizeof(param->sqc)); 1689 1690 MLX5_SET(sqc, sqc, tis_num_0, tis_num); 1691 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn); 1692 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1693 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1694 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1695 1696 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1697 MLX5_SET(wq, wq, uar_page, sq->uar.index); 1698 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift - 1699 PAGE_SHIFT); 1700 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma); 1701 1702 mlx5_fill_page_array(&sq->wq_ctrl.buf, 1703 (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 1704 1705 err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn); 1706 1707 kvfree(in); 1708 1709 return (err); 1710 } 1711 1712 int 1713 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state) 1714 { 1715 void *in; 1716 void *sqc; 1717 int inlen; 1718 int err; 1719 1720 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 1721 in = mlx5_vzalloc(inlen); 1722 if (in == NULL) 1723 return (-ENOMEM); 1724 1725 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1726 1727 MLX5_SET(modify_sq_in, in, sqn, sq->sqn); 1728 MLX5_SET(modify_sq_in, in, sq_state, curr_state); 1729 MLX5_SET(sqc, sqc, state, next_state); 1730 1731 err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen); 1732 1733 kvfree(in); 1734 1735 return (err); 1736 } 1737 1738 void 1739 mlx5e_disable_sq(struct mlx5e_sq *sq) 1740 { 1741 1742 mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn); 1743 } 1744 1745 static int 1746 mlx5e_open_sq(struct mlx5e_channel *c, 1747 int tc, 1748 struct mlx5e_sq_param *param, 1749 struct mlx5e_sq *sq) 1750 { 1751 int err; 1752 1753 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact; 1754 1755 /* ensure the TX completion event factor is not zero */ 1756 if (sq->cev_factor == 0) 1757 sq->cev_factor = 1; 1758 1759 err = mlx5e_create_sq(c, tc, param, sq); 1760 if (err) 1761 return (err); 1762 1763 err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]); 1764 if (err) 1765 goto err_destroy_sq; 1766 1767 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY); 1768 if (err) 1769 goto err_disable_sq; 1770 1771 WRITE_ONCE(sq->running, 1); 1772 1773 return (0); 1774 1775 err_disable_sq: 1776 mlx5e_disable_sq(sq); 1777 err_destroy_sq: 1778 mlx5e_destroy_sq(sq); 1779 1780 return (err); 1781 } 1782 1783 static void 1784 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep) 1785 { 1786 /* fill up remainder with NOPs */ 1787 while (sq->cev_counter != 0) { 1788 while (!mlx5e_sq_has_room_for(sq, 1)) { 1789 if (can_sleep != 0) { 1790 mtx_unlock(&sq->lock); 1791 msleep(4); 1792 mtx_lock(&sq->lock); 1793 } else { 1794 goto done; 1795 } 1796 } 1797 /* send a single NOP */ 1798 mlx5e_send_nop(sq, 1); 1799 atomic_thread_fence_rel(); 1800 } 1801 done: 1802 /* Check if we need to write the doorbell */ 1803 if (likely(sq->doorbell.d64 != 0)) { 1804 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0); 1805 sq->doorbell.d64 = 0; 1806 } 1807 } 1808 1809 void 1810 mlx5e_sq_cev_timeout(void *arg) 1811 { 1812 struct mlx5e_sq *sq = arg; 1813 1814 mtx_assert(&sq->lock, MA_OWNED); 1815 1816 /* check next state */ 1817 switch (sq->cev_next_state) { 1818 case MLX5E_CEV_STATE_SEND_NOPS: 1819 /* fill TX ring with NOPs, if any */ 1820 mlx5e_sq_send_nops_locked(sq, 0); 1821 1822 /* check if completed */ 1823 if (sq->cev_counter == 0) { 1824 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL; 1825 return; 1826 } 1827 break; 1828 default: 1829 /* send NOPs on next timeout */ 1830 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS; 1831 break; 1832 } 1833 1834 /* restart timer */ 1835 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq); 1836 } 1837 1838 void 1839 mlx5e_drain_sq(struct mlx5e_sq *sq) 1840 { 1841 int error; 1842 struct mlx5_core_dev *mdev= sq->priv->mdev; 1843 1844 /* 1845 * Check if already stopped. 1846 * 1847 * NOTE: Serialization of this function is managed by the 1848 * caller ensuring the priv's state lock is locked or in case 1849 * of rate limit support, a single thread manages drain and 1850 * resume of SQs. The "running" variable can therefore safely 1851 * be read without any locks. 1852 */ 1853 if (READ_ONCE(sq->running) == 0) 1854 return; 1855 1856 /* don't put more packets into the SQ */ 1857 WRITE_ONCE(sq->running, 0); 1858 1859 /* serialize access to DMA rings */ 1860 mtx_lock(&sq->lock); 1861 1862 /* teardown event factor timer, if any */ 1863 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS; 1864 callout_stop(&sq->cev_callout); 1865 1866 /* send dummy NOPs in order to flush the transmit ring */ 1867 mlx5e_sq_send_nops_locked(sq, 1); 1868 mtx_unlock(&sq->lock); 1869 1870 /* wait till SQ is empty or link is down */ 1871 mtx_lock(&sq->lock); 1872 while (sq->cc != sq->pc && 1873 (sq->priv->media_status_last & IFM_ACTIVE) != 0 && 1874 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1875 mtx_unlock(&sq->lock); 1876 msleep(1); 1877 sq->cq.mcq.comp(&sq->cq.mcq); 1878 mtx_lock(&sq->lock); 1879 } 1880 mtx_unlock(&sq->lock); 1881 1882 /* error out remaining requests */ 1883 error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR); 1884 if (error != 0) { 1885 mlx5_en_err(sq->ifp, 1886 "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error); 1887 } 1888 1889 /* wait till SQ is empty */ 1890 mtx_lock(&sq->lock); 1891 while (sq->cc != sq->pc && 1892 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1893 mtx_unlock(&sq->lock); 1894 msleep(1); 1895 sq->cq.mcq.comp(&sq->cq.mcq); 1896 mtx_lock(&sq->lock); 1897 } 1898 mtx_unlock(&sq->lock); 1899 } 1900 1901 static void 1902 mlx5e_close_sq_wait(struct mlx5e_sq *sq) 1903 { 1904 1905 mlx5e_drain_sq(sq); 1906 mlx5e_disable_sq(sq); 1907 mlx5e_destroy_sq(sq); 1908 } 1909 1910 static int 1911 mlx5e_create_cq(struct mlx5e_priv *priv, 1912 struct mlx5e_cq_param *param, 1913 struct mlx5e_cq *cq, 1914 mlx5e_cq_comp_t *comp, 1915 int eq_ix) 1916 { 1917 struct mlx5_core_dev *mdev = priv->mdev; 1918 struct mlx5_core_cq *mcq = &cq->mcq; 1919 int eqn_not_used; 1920 int irqn; 1921 int err; 1922 u32 i; 1923 1924 param->wq.buf_numa_node = 0; 1925 param->wq.db_numa_node = 0; 1926 1927 err = mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn); 1928 if (err) 1929 return (err); 1930 1931 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, 1932 &cq->wq_ctrl); 1933 if (err) 1934 return (err); 1935 1936 mcq->cqe_sz = 64; 1937 mcq->set_ci_db = cq->wq_ctrl.db.db; 1938 mcq->arm_db = cq->wq_ctrl.db.db + 1; 1939 *mcq->set_ci_db = 0; 1940 *mcq->arm_db = 0; 1941 mcq->vector = eq_ix; 1942 mcq->comp = comp; 1943 mcq->event = mlx5e_cq_error_event; 1944 mcq->irqn = irqn; 1945 mcq->uar = &priv->cq_uar; 1946 1947 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { 1948 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); 1949 1950 cqe->op_own = 0xf1; 1951 } 1952 1953 cq->priv = priv; 1954 1955 return (0); 1956 } 1957 1958 static void 1959 mlx5e_destroy_cq(struct mlx5e_cq *cq) 1960 { 1961 mlx5_wq_destroy(&cq->wq_ctrl); 1962 } 1963 1964 static int 1965 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix) 1966 { 1967 struct mlx5_core_cq *mcq = &cq->mcq; 1968 void *in; 1969 void *cqc; 1970 int inlen; 1971 int irqn_not_used; 1972 int eqn; 1973 int err; 1974 1975 inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 1976 sizeof(u64) * cq->wq_ctrl.buf.npages; 1977 in = mlx5_vzalloc(inlen); 1978 if (in == NULL) 1979 return (-ENOMEM); 1980 1981 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1982 1983 memcpy(cqc, param->cqc, sizeof(param->cqc)); 1984 1985 mlx5_fill_page_array(&cq->wq_ctrl.buf, 1986 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas)); 1987 1988 mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used); 1989 1990 MLX5_SET(cqc, cqc, c_eqn, eqn); 1991 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index); 1992 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - 1993 PAGE_SHIFT); 1994 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); 1995 1996 err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen); 1997 1998 kvfree(in); 1999 2000 if (err) 2001 return (err); 2002 2003 mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock)); 2004 2005 return (0); 2006 } 2007 2008 static void 2009 mlx5e_disable_cq(struct mlx5e_cq *cq) 2010 { 2011 2012 mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq); 2013 } 2014 2015 int 2016 mlx5e_open_cq(struct mlx5e_priv *priv, 2017 struct mlx5e_cq_param *param, 2018 struct mlx5e_cq *cq, 2019 mlx5e_cq_comp_t *comp, 2020 int eq_ix) 2021 { 2022 int err; 2023 2024 err = mlx5e_create_cq(priv, param, cq, comp, eq_ix); 2025 if (err) 2026 return (err); 2027 2028 err = mlx5e_enable_cq(cq, param, eq_ix); 2029 if (err) 2030 goto err_destroy_cq; 2031 2032 return (0); 2033 2034 err_destroy_cq: 2035 mlx5e_destroy_cq(cq); 2036 2037 return (err); 2038 } 2039 2040 void 2041 mlx5e_close_cq(struct mlx5e_cq *cq) 2042 { 2043 mlx5e_disable_cq(cq); 2044 mlx5e_destroy_cq(cq); 2045 } 2046 2047 static int 2048 mlx5e_open_tx_cqs(struct mlx5e_channel *c, 2049 struct mlx5e_channel_param *cparam) 2050 { 2051 int err; 2052 int tc; 2053 2054 for (tc = 0; tc < c->priv->num_tc; tc++) { 2055 /* open completion queue */ 2056 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq, 2057 &mlx5e_tx_cq_comp, c->ix); 2058 if (err) 2059 goto err_close_tx_cqs; 2060 } 2061 return (0); 2062 2063 err_close_tx_cqs: 2064 for (tc--; tc >= 0; tc--) 2065 mlx5e_close_cq(&c->sq[tc].cq); 2066 2067 return (err); 2068 } 2069 2070 static void 2071 mlx5e_close_tx_cqs(struct mlx5e_channel *c) 2072 { 2073 int tc; 2074 2075 for (tc = 0; tc < c->priv->num_tc; tc++) 2076 mlx5e_close_cq(&c->sq[tc].cq); 2077 } 2078 2079 static int 2080 mlx5e_open_sqs(struct mlx5e_channel *c, 2081 struct mlx5e_channel_param *cparam) 2082 { 2083 int err; 2084 int tc; 2085 2086 for (tc = 0; tc < c->priv->num_tc; tc++) { 2087 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]); 2088 if (err) 2089 goto err_close_sqs; 2090 } 2091 2092 return (0); 2093 2094 err_close_sqs: 2095 for (tc--; tc >= 0; tc--) 2096 mlx5e_close_sq_wait(&c->sq[tc]); 2097 2098 return (err); 2099 } 2100 2101 static void 2102 mlx5e_close_sqs_wait(struct mlx5e_channel *c) 2103 { 2104 int tc; 2105 2106 for (tc = 0; tc < c->priv->num_tc; tc++) 2107 mlx5e_close_sq_wait(&c->sq[tc]); 2108 } 2109 2110 static void 2111 mlx5e_chan_static_init(struct mlx5e_priv *priv, struct mlx5e_channel *c, int ix) 2112 { 2113 int tc; 2114 2115 /* setup priv and channel number */ 2116 c->priv = priv; 2117 c->ix = ix; 2118 2119 /* setup send tag */ 2120 c->tag.type = IF_SND_TAG_TYPE_UNLIMITED; 2121 m_snd_tag_init(&c->tag.m_snd_tag, c->priv->ifp); 2122 2123 init_completion(&c->completion); 2124 2125 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF); 2126 2127 callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0); 2128 2129 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) { 2130 struct mlx5e_sq *sq = c->sq + tc; 2131 2132 mtx_init(&sq->lock, "mlx5tx", 2133 MTX_NETWORK_LOCK " TX", MTX_DEF); 2134 mtx_init(&sq->comp_lock, "mlx5comp", 2135 MTX_NETWORK_LOCK " TX", MTX_DEF); 2136 2137 callout_init_mtx(&sq->cev_callout, &sq->lock, 0); 2138 } 2139 } 2140 2141 static void 2142 mlx5e_chan_wait_for_completion(struct mlx5e_channel *c) 2143 { 2144 2145 m_snd_tag_rele(&c->tag.m_snd_tag); 2146 wait_for_completion(&c->completion); 2147 } 2148 2149 static void 2150 mlx5e_priv_wait_for_completion(struct mlx5e_priv *priv, const uint32_t channels) 2151 { 2152 uint32_t x; 2153 2154 for (x = 0; x != channels; x++) 2155 mlx5e_chan_wait_for_completion(&priv->channel[x]); 2156 } 2157 2158 static void 2159 mlx5e_chan_static_destroy(struct mlx5e_channel *c) 2160 { 2161 int tc; 2162 2163 callout_drain(&c->rq.watchdog); 2164 2165 mtx_destroy(&c->rq.mtx); 2166 2167 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) { 2168 callout_drain(&c->sq[tc].cev_callout); 2169 mtx_destroy(&c->sq[tc].lock); 2170 mtx_destroy(&c->sq[tc].comp_lock); 2171 } 2172 } 2173 2174 static int 2175 mlx5e_open_channel(struct mlx5e_priv *priv, 2176 struct mlx5e_channel_param *cparam, 2177 struct mlx5e_channel *c) 2178 { 2179 int i, err; 2180 2181 /* zero non-persistant data */ 2182 MLX5E_ZERO(&c->rq, mlx5e_rq_zero_start); 2183 for (i = 0; i != priv->num_tc; i++) 2184 MLX5E_ZERO(&c->sq[i], mlx5e_sq_zero_start); 2185 2186 /* open transmit completion queue */ 2187 err = mlx5e_open_tx_cqs(c, cparam); 2188 if (err) 2189 goto err_free; 2190 2191 /* open receive completion queue */ 2192 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq, 2193 &mlx5e_rx_cq_comp, c->ix); 2194 if (err) 2195 goto err_close_tx_cqs; 2196 2197 err = mlx5e_open_sqs(c, cparam); 2198 if (err) 2199 goto err_close_rx_cq; 2200 2201 err = mlx5e_open_rq(c, &cparam->rq, &c->rq); 2202 if (err) 2203 goto err_close_sqs; 2204 2205 /* poll receive queue initially */ 2206 c->rq.cq.mcq.comp(&c->rq.cq.mcq); 2207 2208 return (0); 2209 2210 err_close_sqs: 2211 mlx5e_close_sqs_wait(c); 2212 2213 err_close_rx_cq: 2214 mlx5e_close_cq(&c->rq.cq); 2215 2216 err_close_tx_cqs: 2217 mlx5e_close_tx_cqs(c); 2218 2219 err_free: 2220 return (err); 2221 } 2222 2223 static void 2224 mlx5e_close_channel(struct mlx5e_channel *c) 2225 { 2226 mlx5e_close_rq(&c->rq); 2227 } 2228 2229 static void 2230 mlx5e_close_channel_wait(struct mlx5e_channel *c) 2231 { 2232 mlx5e_close_rq_wait(&c->rq); 2233 mlx5e_close_sqs_wait(c); 2234 mlx5e_close_tx_cqs(c); 2235 } 2236 2237 static int 2238 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs) 2239 { 2240 u32 r, n; 2241 2242 r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz : 2243 MLX5E_SW2MB_MTU(priv->ifp->if_mtu); 2244 if (r > MJUM16BYTES) 2245 return (-ENOMEM); 2246 2247 if (r > MJUM9BYTES) 2248 r = MJUM16BYTES; 2249 else if (r > MJUMPAGESIZE) 2250 r = MJUM9BYTES; 2251 else if (r > MCLBYTES) 2252 r = MJUMPAGESIZE; 2253 else 2254 r = MCLBYTES; 2255 2256 /* 2257 * n + 1 must be a power of two, because stride size must be. 2258 * Stride size is 16 * (n + 1), as the first segment is 2259 * control. 2260 */ 2261 for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++) 2262 ; 2263 2264 if (n > MLX5E_MAX_BUSDMA_RX_SEGS) 2265 return (-ENOMEM); 2266 2267 *wqe_sz = r; 2268 *nsegs = n; 2269 return (0); 2270 } 2271 2272 static void 2273 mlx5e_build_rq_param(struct mlx5e_priv *priv, 2274 struct mlx5e_rq_param *param) 2275 { 2276 void *rqc = param->rqc; 2277 void *wq = MLX5_ADDR_OF(rqc, rqc, wq); 2278 u32 wqe_sz, nsegs; 2279 2280 mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs); 2281 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); 2282 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 2283 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) + 2284 nsegs * sizeof(struct mlx5_wqe_data_seg))); 2285 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size); 2286 MLX5_SET(wq, wq, pd, priv->pdn); 2287 2288 param->wq.buf_numa_node = 0; 2289 param->wq.db_numa_node = 0; 2290 param->wq.linear = 1; 2291 } 2292 2293 static void 2294 mlx5e_build_sq_param(struct mlx5e_priv *priv, 2295 struct mlx5e_sq_param *param) 2296 { 2297 void *sqc = param->sqc; 2298 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 2299 2300 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size); 2301 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 2302 MLX5_SET(wq, wq, pd, priv->pdn); 2303 2304 param->wq.buf_numa_node = 0; 2305 param->wq.db_numa_node = 0; 2306 param->wq.linear = 1; 2307 } 2308 2309 static void 2310 mlx5e_build_common_cq_param(struct mlx5e_priv *priv, 2311 struct mlx5e_cq_param *param) 2312 { 2313 void *cqc = param->cqc; 2314 2315 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index); 2316 } 2317 2318 static void 2319 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr) 2320 { 2321 2322 *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE); 2323 2324 /* apply LRO restrictions */ 2325 if (priv->params.hw_lro_en && 2326 ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) { 2327 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO; 2328 } 2329 } 2330 2331 static void 2332 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, 2333 struct mlx5e_cq_param *param) 2334 { 2335 struct net_dim_cq_moder curr; 2336 void *cqc = param->cqc; 2337 2338 /* 2339 * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE 2340 * format is more beneficial for FreeBSD use case. 2341 * 2342 * Adding support for MLX5_CQE_FORMAT_CSUM will require changes 2343 * in mlx5e_decompress_cqe. 2344 */ 2345 if (priv->params.cqe_zipping_en) { 2346 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH); 2347 MLX5_SET(cqc, cqc, cqe_compression_en, 1); 2348 } 2349 2350 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size); 2351 2352 switch (priv->params.rx_cq_moderation_mode) { 2353 case 0: 2354 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec); 2355 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts); 2356 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2357 break; 2358 case 1: 2359 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec); 2360 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts); 2361 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2362 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2363 else 2364 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2365 break; 2366 case 2: 2367 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr); 2368 MLX5_SET(cqc, cqc, cq_period, curr.usec); 2369 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts); 2370 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2371 break; 2372 case 3: 2373 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr); 2374 MLX5_SET(cqc, cqc, cq_period, curr.usec); 2375 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts); 2376 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2377 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2378 else 2379 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2380 break; 2381 default: 2382 break; 2383 } 2384 2385 mlx5e_dim_build_cq_param(priv, param); 2386 2387 mlx5e_build_common_cq_param(priv, param); 2388 } 2389 2390 static void 2391 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv, 2392 struct mlx5e_cq_param *param) 2393 { 2394 void *cqc = param->cqc; 2395 2396 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size); 2397 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec); 2398 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts); 2399 2400 switch (priv->params.tx_cq_moderation_mode) { 2401 case 0: 2402 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2403 break; 2404 default: 2405 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2406 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2407 else 2408 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2409 break; 2410 } 2411 2412 mlx5e_build_common_cq_param(priv, param); 2413 } 2414 2415 static void 2416 mlx5e_build_channel_param(struct mlx5e_priv *priv, 2417 struct mlx5e_channel_param *cparam) 2418 { 2419 memset(cparam, 0, sizeof(*cparam)); 2420 2421 mlx5e_build_rq_param(priv, &cparam->rq); 2422 mlx5e_build_sq_param(priv, &cparam->sq); 2423 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq); 2424 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq); 2425 } 2426 2427 static int 2428 mlx5e_open_channels(struct mlx5e_priv *priv) 2429 { 2430 struct mlx5e_channel_param *cparam; 2431 int err; 2432 int i; 2433 int j; 2434 2435 cparam = malloc(sizeof(*cparam), M_MLX5EN, M_WAITOK); 2436 2437 mlx5e_build_channel_param(priv, cparam); 2438 for (i = 0; i < priv->params.num_channels; i++) { 2439 err = mlx5e_open_channel(priv, cparam, &priv->channel[i]); 2440 if (err) 2441 goto err_close_channels; 2442 } 2443 2444 for (j = 0; j < priv->params.num_channels; j++) { 2445 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq); 2446 if (err) 2447 goto err_close_channels; 2448 } 2449 free(cparam, M_MLX5EN); 2450 return (0); 2451 2452 err_close_channels: 2453 while (i--) { 2454 mlx5e_close_channel(&priv->channel[i]); 2455 mlx5e_close_channel_wait(&priv->channel[i]); 2456 } 2457 free(cparam, M_MLX5EN); 2458 return (err); 2459 } 2460 2461 static void 2462 mlx5e_close_channels(struct mlx5e_priv *priv) 2463 { 2464 int i; 2465 2466 for (i = 0; i < priv->params.num_channels; i++) 2467 mlx5e_close_channel(&priv->channel[i]); 2468 for (i = 0; i < priv->params.num_channels; i++) 2469 mlx5e_close_channel_wait(&priv->channel[i]); 2470 } 2471 2472 static int 2473 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq) 2474 { 2475 2476 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) { 2477 uint8_t cq_mode; 2478 2479 switch (priv->params.tx_cq_moderation_mode) { 2480 case 0: 2481 case 2: 2482 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 2483 break; 2484 default: 2485 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE; 2486 break; 2487 } 2488 2489 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq, 2490 priv->params.tx_cq_moderation_usec, 2491 priv->params.tx_cq_moderation_pkts, 2492 cq_mode)); 2493 } 2494 2495 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq, 2496 priv->params.tx_cq_moderation_usec, 2497 priv->params.tx_cq_moderation_pkts)); 2498 } 2499 2500 static int 2501 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq) 2502 { 2503 2504 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) { 2505 uint8_t cq_mode; 2506 uint8_t dim_mode; 2507 int retval; 2508 2509 switch (priv->params.rx_cq_moderation_mode) { 2510 case 0: 2511 case 2: 2512 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 2513 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; 2514 break; 2515 default: 2516 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE; 2517 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE; 2518 break; 2519 } 2520 2521 /* tear down dynamic interrupt moderation */ 2522 mtx_lock(&rq->mtx); 2523 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 2524 mtx_unlock(&rq->mtx); 2525 2526 /* wait for dynamic interrupt moderation work task, if any */ 2527 cancel_work_sync(&rq->dim.work); 2528 2529 if (priv->params.rx_cq_moderation_mode >= 2) { 2530 struct net_dim_cq_moder curr; 2531 2532 mlx5e_get_default_profile(priv, dim_mode, &curr); 2533 2534 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq, 2535 curr.usec, curr.pkts, cq_mode); 2536 2537 /* set dynamic interrupt moderation mode and zero defaults */ 2538 mtx_lock(&rq->mtx); 2539 rq->dim.mode = dim_mode; 2540 rq->dim.state = 0; 2541 rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE; 2542 mtx_unlock(&rq->mtx); 2543 } else { 2544 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq, 2545 priv->params.rx_cq_moderation_usec, 2546 priv->params.rx_cq_moderation_pkts, 2547 cq_mode); 2548 } 2549 return (retval); 2550 } 2551 2552 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq, 2553 priv->params.rx_cq_moderation_usec, 2554 priv->params.rx_cq_moderation_pkts)); 2555 } 2556 2557 static int 2558 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c) 2559 { 2560 int err; 2561 int i; 2562 2563 err = mlx5e_refresh_rq_params(priv, &c->rq); 2564 if (err) 2565 goto done; 2566 2567 for (i = 0; i != priv->num_tc; i++) { 2568 err = mlx5e_refresh_sq_params(priv, &c->sq[i]); 2569 if (err) 2570 goto done; 2571 } 2572 done: 2573 return (err); 2574 } 2575 2576 int 2577 mlx5e_refresh_channel_params(struct mlx5e_priv *priv) 2578 { 2579 int i; 2580 2581 /* check if channels are closed */ 2582 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 2583 return (EINVAL); 2584 2585 for (i = 0; i < priv->params.num_channels; i++) { 2586 int err; 2587 2588 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]); 2589 if (err) 2590 return (err); 2591 } 2592 return (0); 2593 } 2594 2595 static int 2596 mlx5e_open_tis(struct mlx5e_priv *priv, int tc) 2597 { 2598 struct mlx5_core_dev *mdev = priv->mdev; 2599 u32 in[MLX5_ST_SZ_DW(create_tis_in)]; 2600 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 2601 2602 memset(in, 0, sizeof(in)); 2603 2604 MLX5_SET(tisc, tisc, prio, tc); 2605 MLX5_SET(tisc, tisc, transport_domain, priv->tdn); 2606 2607 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc])); 2608 } 2609 2610 static void 2611 mlx5e_close_tis(struct mlx5e_priv *priv, int tc) 2612 { 2613 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]); 2614 } 2615 2616 static int 2617 mlx5e_open_tises(struct mlx5e_priv *priv) 2618 { 2619 int num_tc = priv->num_tc; 2620 int err; 2621 int tc; 2622 2623 for (tc = 0; tc < num_tc; tc++) { 2624 err = mlx5e_open_tis(priv, tc); 2625 if (err) 2626 goto err_close_tises; 2627 } 2628 2629 return (0); 2630 2631 err_close_tises: 2632 for (tc--; tc >= 0; tc--) 2633 mlx5e_close_tis(priv, tc); 2634 2635 return (err); 2636 } 2637 2638 static void 2639 mlx5e_close_tises(struct mlx5e_priv *priv) 2640 { 2641 int num_tc = priv->num_tc; 2642 int tc; 2643 2644 for (tc = 0; tc < num_tc; tc++) 2645 mlx5e_close_tis(priv, tc); 2646 } 2647 2648 static int 2649 mlx5e_open_rqt(struct mlx5e_priv *priv) 2650 { 2651 struct mlx5_core_dev *mdev = priv->mdev; 2652 u32 *in; 2653 u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 2654 void *rqtc; 2655 int inlen; 2656 int err; 2657 int sz; 2658 int i; 2659 2660 sz = 1 << priv->params.rx_hash_log_tbl_sz; 2661 2662 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 2663 in = mlx5_vzalloc(inlen); 2664 if (in == NULL) 2665 return (-ENOMEM); 2666 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 2667 2668 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 2669 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 2670 2671 for (i = 0; i < sz; i++) { 2672 int ix = i; 2673 #ifdef RSS 2674 ix = rss_get_indirection_to_bucket(ix); 2675 #endif 2676 /* ensure we don't overflow */ 2677 ix %= priv->params.num_channels; 2678 2679 /* apply receive side scaling stride, if any */ 2680 ix -= ix % (int)priv->params.channels_rsss; 2681 2682 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn); 2683 } 2684 2685 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 2686 2687 err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out)); 2688 if (!err) 2689 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn); 2690 2691 kvfree(in); 2692 2693 return (err); 2694 } 2695 2696 static void 2697 mlx5e_close_rqt(struct mlx5e_priv *priv) 2698 { 2699 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0}; 2700 u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0}; 2701 2702 MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT); 2703 MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn); 2704 2705 mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)); 2706 } 2707 2708 static void 2709 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt) 2710 { 2711 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 2712 __be32 *hkey; 2713 2714 MLX5_SET(tirc, tirc, transport_domain, priv->tdn); 2715 2716 #define ROUGH_MAX_L2_L3_HDR_SZ 256 2717 2718 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2719 MLX5_HASH_FIELD_SEL_DST_IP) 2720 2721 #define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2722 MLX5_HASH_FIELD_SEL_DST_IP |\ 2723 MLX5_HASH_FIELD_SEL_L4_SPORT |\ 2724 MLX5_HASH_FIELD_SEL_L4_DPORT) 2725 2726 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2727 MLX5_HASH_FIELD_SEL_DST_IP |\ 2728 MLX5_HASH_FIELD_SEL_IPSEC_SPI) 2729 2730 if (priv->params.hw_lro_en) { 2731 MLX5_SET(tirc, tirc, lro_enable_mask, 2732 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | 2733 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO); 2734 MLX5_SET(tirc, tirc, lro_max_msg_sz, 2735 (priv->params.lro_wqe_sz - 2736 ROUGH_MAX_L2_L3_HDR_SZ) >> 8); 2737 /* TODO: add the option to choose timer value dynamically */ 2738 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, 2739 MLX5_CAP_ETH(priv->mdev, 2740 lro_timer_supported_periods[2])); 2741 } 2742 2743 /* setup parameters for hashing TIR type, if any */ 2744 switch (tt) { 2745 case MLX5E_TT_ANY: 2746 MLX5_SET(tirc, tirc, disp_type, 2747 MLX5_TIRC_DISP_TYPE_DIRECT); 2748 MLX5_SET(tirc, tirc, inline_rqn, 2749 priv->channel[0].rq.rqn); 2750 break; 2751 default: 2752 MLX5_SET(tirc, tirc, disp_type, 2753 MLX5_TIRC_DISP_TYPE_INDIRECT); 2754 MLX5_SET(tirc, tirc, indirect_table, 2755 priv->rqtn); 2756 MLX5_SET(tirc, tirc, rx_hash_fn, 2757 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ); 2758 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 2759 #ifdef RSS 2760 /* 2761 * The FreeBSD RSS implementation does currently not 2762 * support symmetric Toeplitz hashes: 2763 */ 2764 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0); 2765 rss_getkey((uint8_t *)hkey); 2766 #else 2767 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 2768 hkey[0] = cpu_to_be32(0xD181C62C); 2769 hkey[1] = cpu_to_be32(0xF7F4DB5B); 2770 hkey[2] = cpu_to_be32(0x1983A2FC); 2771 hkey[3] = cpu_to_be32(0x943E1ADB); 2772 hkey[4] = cpu_to_be32(0xD9389E6B); 2773 hkey[5] = cpu_to_be32(0xD1039C2C); 2774 hkey[6] = cpu_to_be32(0xA74499AD); 2775 hkey[7] = cpu_to_be32(0x593D56D9); 2776 hkey[8] = cpu_to_be32(0xF3253C06); 2777 hkey[9] = cpu_to_be32(0x2ADC1FFC); 2778 #endif 2779 break; 2780 } 2781 2782 switch (tt) { 2783 case MLX5E_TT_IPV4_TCP: 2784 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2785 MLX5_L3_PROT_TYPE_IPV4); 2786 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2787 MLX5_L4_PROT_TYPE_TCP); 2788 #ifdef RSS 2789 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) { 2790 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2791 MLX5_HASH_IP); 2792 } else 2793 #endif 2794 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2795 MLX5_HASH_ALL); 2796 break; 2797 2798 case MLX5E_TT_IPV6_TCP: 2799 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2800 MLX5_L3_PROT_TYPE_IPV6); 2801 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2802 MLX5_L4_PROT_TYPE_TCP); 2803 #ifdef RSS 2804 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) { 2805 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2806 MLX5_HASH_IP); 2807 } else 2808 #endif 2809 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2810 MLX5_HASH_ALL); 2811 break; 2812 2813 case MLX5E_TT_IPV4_UDP: 2814 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2815 MLX5_L3_PROT_TYPE_IPV4); 2816 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2817 MLX5_L4_PROT_TYPE_UDP); 2818 #ifdef RSS 2819 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) { 2820 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2821 MLX5_HASH_IP); 2822 } else 2823 #endif 2824 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2825 MLX5_HASH_ALL); 2826 break; 2827 2828 case MLX5E_TT_IPV6_UDP: 2829 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2830 MLX5_L3_PROT_TYPE_IPV6); 2831 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2832 MLX5_L4_PROT_TYPE_UDP); 2833 #ifdef RSS 2834 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) { 2835 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2836 MLX5_HASH_IP); 2837 } else 2838 #endif 2839 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2840 MLX5_HASH_ALL); 2841 break; 2842 2843 case MLX5E_TT_IPV4_IPSEC_AH: 2844 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2845 MLX5_L3_PROT_TYPE_IPV4); 2846 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2847 MLX5_HASH_IP_IPSEC_SPI); 2848 break; 2849 2850 case MLX5E_TT_IPV6_IPSEC_AH: 2851 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2852 MLX5_L3_PROT_TYPE_IPV6); 2853 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2854 MLX5_HASH_IP_IPSEC_SPI); 2855 break; 2856 2857 case MLX5E_TT_IPV4_IPSEC_ESP: 2858 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2859 MLX5_L3_PROT_TYPE_IPV4); 2860 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2861 MLX5_HASH_IP_IPSEC_SPI); 2862 break; 2863 2864 case MLX5E_TT_IPV6_IPSEC_ESP: 2865 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2866 MLX5_L3_PROT_TYPE_IPV6); 2867 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2868 MLX5_HASH_IP_IPSEC_SPI); 2869 break; 2870 2871 case MLX5E_TT_IPV4: 2872 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2873 MLX5_L3_PROT_TYPE_IPV4); 2874 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2875 MLX5_HASH_IP); 2876 break; 2877 2878 case MLX5E_TT_IPV6: 2879 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2880 MLX5_L3_PROT_TYPE_IPV6); 2881 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2882 MLX5_HASH_IP); 2883 break; 2884 2885 default: 2886 break; 2887 } 2888 } 2889 2890 static int 2891 mlx5e_open_tir(struct mlx5e_priv *priv, int tt) 2892 { 2893 struct mlx5_core_dev *mdev = priv->mdev; 2894 u32 *in; 2895 void *tirc; 2896 int inlen; 2897 int err; 2898 2899 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 2900 in = mlx5_vzalloc(inlen); 2901 if (in == NULL) 2902 return (-ENOMEM); 2903 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context); 2904 2905 mlx5e_build_tir_ctx(priv, tirc, tt); 2906 2907 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]); 2908 2909 kvfree(in); 2910 2911 return (err); 2912 } 2913 2914 static void 2915 mlx5e_close_tir(struct mlx5e_priv *priv, int tt) 2916 { 2917 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]); 2918 } 2919 2920 static int 2921 mlx5e_open_tirs(struct mlx5e_priv *priv) 2922 { 2923 int err; 2924 int i; 2925 2926 for (i = 0; i < MLX5E_NUM_TT; i++) { 2927 err = mlx5e_open_tir(priv, i); 2928 if (err) 2929 goto err_close_tirs; 2930 } 2931 2932 return (0); 2933 2934 err_close_tirs: 2935 for (i--; i >= 0; i--) 2936 mlx5e_close_tir(priv, i); 2937 2938 return (err); 2939 } 2940 2941 static void 2942 mlx5e_close_tirs(struct mlx5e_priv *priv) 2943 { 2944 int i; 2945 2946 for (i = 0; i < MLX5E_NUM_TT; i++) 2947 mlx5e_close_tir(priv, i); 2948 } 2949 2950 /* 2951 * SW MTU does not include headers, 2952 * HW MTU includes all headers and checksums. 2953 */ 2954 static int 2955 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu) 2956 { 2957 struct mlx5e_priv *priv = ifp->if_softc; 2958 struct mlx5_core_dev *mdev = priv->mdev; 2959 int hw_mtu; 2960 int err; 2961 2962 hw_mtu = MLX5E_SW2HW_MTU(sw_mtu); 2963 2964 err = mlx5_set_port_mtu(mdev, hw_mtu); 2965 if (err) { 2966 mlx5_en_err(ifp, "mlx5_set_port_mtu failed setting %d, err=%d\n", 2967 sw_mtu, err); 2968 return (err); 2969 } 2970 2971 /* Update vport context MTU */ 2972 err = mlx5_set_vport_mtu(mdev, hw_mtu); 2973 if (err) { 2974 mlx5_en_err(ifp, 2975 "Failed updating vport context with MTU size, err=%d\n", 2976 err); 2977 } 2978 2979 ifp->if_mtu = sw_mtu; 2980 2981 err = mlx5_query_vport_mtu(mdev, &hw_mtu); 2982 if (err || !hw_mtu) { 2983 /* fallback to port oper mtu */ 2984 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu); 2985 } 2986 if (err) { 2987 mlx5_en_err(ifp, 2988 "Query port MTU, after setting new MTU value, failed\n"); 2989 return (err); 2990 } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) { 2991 err = -E2BIG, 2992 mlx5_en_err(ifp, 2993 "Port MTU %d is smaller than ifp mtu %d\n", 2994 hw_mtu, sw_mtu); 2995 } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) { 2996 err = -EINVAL; 2997 mlx5_en_err(ifp, 2998 "Port MTU %d is bigger than ifp mtu %d\n", 2999 hw_mtu, sw_mtu); 3000 } 3001 priv->params_ethtool.hw_mtu = hw_mtu; 3002 3003 return (err); 3004 } 3005 3006 int 3007 mlx5e_open_locked(struct ifnet *ifp) 3008 { 3009 struct mlx5e_priv *priv = ifp->if_softc; 3010 int err; 3011 u16 set_id; 3012 3013 /* check if already opened */ 3014 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 3015 return (0); 3016 3017 #ifdef RSS 3018 if (rss_getnumbuckets() > priv->params.num_channels) { 3019 mlx5_en_info(ifp, 3020 "NOTE: There are more RSS buckets(%u) than channels(%u) available\n", 3021 rss_getnumbuckets(), priv->params.num_channels); 3022 } 3023 #endif 3024 err = mlx5e_open_tises(priv); 3025 if (err) { 3026 mlx5_en_err(ifp, "mlx5e_open_tises failed, %d\n", err); 3027 return (err); 3028 } 3029 err = mlx5_vport_alloc_q_counter(priv->mdev, 3030 MLX5_INTERFACE_PROTOCOL_ETH, &set_id); 3031 if (err) { 3032 mlx5_en_err(priv->ifp, 3033 "mlx5_vport_alloc_q_counter failed: %d\n", err); 3034 goto err_close_tises; 3035 } 3036 /* store counter set ID */ 3037 priv->counter_set_id = set_id; 3038 3039 err = mlx5e_open_channels(priv); 3040 if (err) { 3041 mlx5_en_err(ifp, 3042 "mlx5e_open_channels failed, %d\n", err); 3043 goto err_dalloc_q_counter; 3044 } 3045 err = mlx5e_open_rqt(priv); 3046 if (err) { 3047 mlx5_en_err(ifp, "mlx5e_open_rqt failed, %d\n", err); 3048 goto err_close_channels; 3049 } 3050 err = mlx5e_open_tirs(priv); 3051 if (err) { 3052 mlx5_en_err(ifp, "mlx5e_open_tir failed, %d\n", err); 3053 goto err_close_rqls; 3054 } 3055 err = mlx5e_open_flow_table(priv); 3056 if (err) { 3057 mlx5_en_err(ifp, 3058 "mlx5e_open_flow_table failed, %d\n", err); 3059 goto err_close_tirs; 3060 } 3061 err = mlx5e_add_all_vlan_rules(priv); 3062 if (err) { 3063 mlx5_en_err(ifp, 3064 "mlx5e_add_all_vlan_rules failed, %d\n", err); 3065 goto err_close_flow_table; 3066 } 3067 set_bit(MLX5E_STATE_OPENED, &priv->state); 3068 3069 mlx5e_update_carrier(priv); 3070 mlx5e_set_rx_mode_core(priv); 3071 3072 return (0); 3073 3074 err_close_flow_table: 3075 mlx5e_close_flow_table(priv); 3076 3077 err_close_tirs: 3078 mlx5e_close_tirs(priv); 3079 3080 err_close_rqls: 3081 mlx5e_close_rqt(priv); 3082 3083 err_close_channels: 3084 mlx5e_close_channels(priv); 3085 3086 err_dalloc_q_counter: 3087 mlx5_vport_dealloc_q_counter(priv->mdev, 3088 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 3089 3090 err_close_tises: 3091 mlx5e_close_tises(priv); 3092 3093 return (err); 3094 } 3095 3096 static void 3097 mlx5e_open(void *arg) 3098 { 3099 struct mlx5e_priv *priv = arg; 3100 3101 PRIV_LOCK(priv); 3102 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP)) 3103 mlx5_en_err(priv->ifp, 3104 "Setting port status to up failed\n"); 3105 3106 mlx5e_open_locked(priv->ifp); 3107 priv->ifp->if_drv_flags |= IFF_DRV_RUNNING; 3108 PRIV_UNLOCK(priv); 3109 } 3110 3111 int 3112 mlx5e_close_locked(struct ifnet *ifp) 3113 { 3114 struct mlx5e_priv *priv = ifp->if_softc; 3115 3116 /* check if already closed */ 3117 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3118 return (0); 3119 3120 clear_bit(MLX5E_STATE_OPENED, &priv->state); 3121 3122 mlx5e_set_rx_mode_core(priv); 3123 mlx5e_del_all_vlan_rules(priv); 3124 if_link_state_change(priv->ifp, LINK_STATE_DOWN); 3125 mlx5e_close_flow_table(priv); 3126 mlx5e_close_tirs(priv); 3127 mlx5e_close_rqt(priv); 3128 mlx5e_close_channels(priv); 3129 mlx5_vport_dealloc_q_counter(priv->mdev, 3130 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 3131 mlx5e_close_tises(priv); 3132 3133 return (0); 3134 } 3135 3136 #if (__FreeBSD_version >= 1100000) 3137 static uint64_t 3138 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt) 3139 { 3140 struct mlx5e_priv *priv = ifp->if_softc; 3141 u64 retval; 3142 3143 /* PRIV_LOCK(priv); XXX not allowed */ 3144 switch (cnt) { 3145 case IFCOUNTER_IPACKETS: 3146 retval = priv->stats.vport.rx_packets; 3147 break; 3148 case IFCOUNTER_IERRORS: 3149 retval = priv->stats.pport.in_range_len_errors + 3150 priv->stats.pport.out_of_range_len + 3151 priv->stats.pport.too_long_errors + 3152 priv->stats.pport.check_seq_err + 3153 priv->stats.pport.alignment_err; 3154 break; 3155 case IFCOUNTER_IQDROPS: 3156 retval = priv->stats.vport.rx_out_of_buffer; 3157 break; 3158 case IFCOUNTER_OPACKETS: 3159 retval = priv->stats.vport.tx_packets; 3160 break; 3161 case IFCOUNTER_OERRORS: 3162 retval = priv->stats.port_stats_debug.out_discards; 3163 break; 3164 case IFCOUNTER_IBYTES: 3165 retval = priv->stats.vport.rx_bytes; 3166 break; 3167 case IFCOUNTER_OBYTES: 3168 retval = priv->stats.vport.tx_bytes; 3169 break; 3170 case IFCOUNTER_IMCASTS: 3171 retval = priv->stats.vport.rx_multicast_packets; 3172 break; 3173 case IFCOUNTER_OMCASTS: 3174 retval = priv->stats.vport.tx_multicast_packets; 3175 break; 3176 case IFCOUNTER_OQDROPS: 3177 retval = priv->stats.vport.tx_queue_dropped; 3178 break; 3179 case IFCOUNTER_COLLISIONS: 3180 retval = priv->stats.pport.collisions; 3181 break; 3182 default: 3183 retval = if_get_counter_default(ifp, cnt); 3184 break; 3185 } 3186 /* PRIV_UNLOCK(priv); XXX not allowed */ 3187 return (retval); 3188 } 3189 #endif 3190 3191 static void 3192 mlx5e_set_rx_mode(struct ifnet *ifp) 3193 { 3194 struct mlx5e_priv *priv = ifp->if_softc; 3195 3196 queue_work(priv->wq, &priv->set_rx_mode_work); 3197 } 3198 3199 static int 3200 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3201 { 3202 struct mlx5e_priv *priv; 3203 struct ifreq *ifr; 3204 struct ifi2creq i2c; 3205 int error = 0; 3206 int mask = 0; 3207 int size_read = 0; 3208 int module_status; 3209 int module_num; 3210 int max_mtu; 3211 uint8_t read_addr; 3212 3213 priv = ifp->if_softc; 3214 3215 /* check if detaching */ 3216 if (priv == NULL || priv->gone != 0) 3217 return (ENXIO); 3218 3219 switch (command) { 3220 case SIOCSIFMTU: 3221 ifr = (struct ifreq *)data; 3222 3223 PRIV_LOCK(priv); 3224 mlx5_query_port_max_mtu(priv->mdev, &max_mtu); 3225 3226 if (ifr->ifr_mtu >= MLX5E_MTU_MIN && 3227 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) { 3228 int was_opened; 3229 3230 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 3231 if (was_opened) 3232 mlx5e_close_locked(ifp); 3233 3234 /* set new MTU */ 3235 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu); 3236 3237 if (was_opened) 3238 mlx5e_open_locked(ifp); 3239 } else { 3240 error = EINVAL; 3241 mlx5_en_err(ifp, 3242 "Invalid MTU value. Min val: %d, Max val: %d\n", 3243 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu)); 3244 } 3245 PRIV_UNLOCK(priv); 3246 break; 3247 case SIOCSIFFLAGS: 3248 if ((ifp->if_flags & IFF_UP) && 3249 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3250 mlx5e_set_rx_mode(ifp); 3251 break; 3252 } 3253 PRIV_LOCK(priv); 3254 if (ifp->if_flags & IFF_UP) { 3255 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3256 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3257 mlx5e_open_locked(ifp); 3258 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3259 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP); 3260 } 3261 } else { 3262 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3263 mlx5_set_port_status(priv->mdev, 3264 MLX5_PORT_DOWN); 3265 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 3266 mlx5e_close_locked(ifp); 3267 mlx5e_update_carrier(priv); 3268 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3269 } 3270 } 3271 PRIV_UNLOCK(priv); 3272 break; 3273 case SIOCADDMULTI: 3274 case SIOCDELMULTI: 3275 mlx5e_set_rx_mode(ifp); 3276 break; 3277 case SIOCSIFMEDIA: 3278 case SIOCGIFMEDIA: 3279 case SIOCGIFXMEDIA: 3280 ifr = (struct ifreq *)data; 3281 error = ifmedia_ioctl(ifp, ifr, &priv->media, command); 3282 break; 3283 case SIOCSIFCAP: 3284 ifr = (struct ifreq *)data; 3285 PRIV_LOCK(priv); 3286 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3287 3288 if (mask & IFCAP_TXCSUM) { 3289 ifp->if_capenable ^= IFCAP_TXCSUM; 3290 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 3291 3292 if (IFCAP_TSO4 & ifp->if_capenable && 3293 !(IFCAP_TXCSUM & ifp->if_capenable)) { 3294 ifp->if_capenable &= ~IFCAP_TSO4; 3295 ifp->if_hwassist &= ~CSUM_IP_TSO; 3296 mlx5_en_err(ifp, 3297 "tso4 disabled due to -txcsum.\n"); 3298 } 3299 } 3300 if (mask & IFCAP_TXCSUM_IPV6) { 3301 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 3302 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 3303 3304 if (IFCAP_TSO6 & ifp->if_capenable && 3305 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 3306 ifp->if_capenable &= ~IFCAP_TSO6; 3307 ifp->if_hwassist &= ~CSUM_IP6_TSO; 3308 mlx5_en_err(ifp, 3309 "tso6 disabled due to -txcsum6.\n"); 3310 } 3311 } 3312 if (mask & IFCAP_NOMAP) 3313 ifp->if_capenable ^= IFCAP_NOMAP; 3314 if (mask & IFCAP_RXCSUM) 3315 ifp->if_capenable ^= IFCAP_RXCSUM; 3316 if (mask & IFCAP_RXCSUM_IPV6) 3317 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 3318 if (mask & IFCAP_TSO4) { 3319 if (!(IFCAP_TSO4 & ifp->if_capenable) && 3320 !(IFCAP_TXCSUM & ifp->if_capenable)) { 3321 mlx5_en_err(ifp, "enable txcsum first.\n"); 3322 error = EAGAIN; 3323 goto out; 3324 } 3325 ifp->if_capenable ^= IFCAP_TSO4; 3326 ifp->if_hwassist ^= CSUM_IP_TSO; 3327 } 3328 if (mask & IFCAP_TSO6) { 3329 if (!(IFCAP_TSO6 & ifp->if_capenable) && 3330 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 3331 mlx5_en_err(ifp, "enable txcsum6 first.\n"); 3332 error = EAGAIN; 3333 goto out; 3334 } 3335 ifp->if_capenable ^= IFCAP_TSO6; 3336 ifp->if_hwassist ^= CSUM_IP6_TSO; 3337 } 3338 if (mask & IFCAP_VLAN_HWFILTER) { 3339 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) 3340 mlx5e_disable_vlan_filter(priv); 3341 else 3342 mlx5e_enable_vlan_filter(priv); 3343 3344 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER; 3345 } 3346 if (mask & IFCAP_VLAN_HWTAGGING) 3347 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3348 if (mask & IFCAP_WOL_MAGIC) 3349 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3350 3351 VLAN_CAPABILITIES(ifp); 3352 /* turn off LRO means also turn of HW LRO - if it's on */ 3353 if (mask & IFCAP_LRO) { 3354 int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 3355 bool need_restart = false; 3356 3357 ifp->if_capenable ^= IFCAP_LRO; 3358 3359 /* figure out if updating HW LRO is needed */ 3360 if (!(ifp->if_capenable & IFCAP_LRO)) { 3361 if (priv->params.hw_lro_en) { 3362 priv->params.hw_lro_en = false; 3363 need_restart = true; 3364 } 3365 } else { 3366 if (priv->params.hw_lro_en == false && 3367 priv->params_ethtool.hw_lro != 0) { 3368 priv->params.hw_lro_en = true; 3369 need_restart = true; 3370 } 3371 } 3372 if (was_opened && need_restart) { 3373 mlx5e_close_locked(ifp); 3374 mlx5e_open_locked(ifp); 3375 } 3376 } 3377 if (mask & IFCAP_HWRXTSTMP) { 3378 ifp->if_capenable ^= IFCAP_HWRXTSTMP; 3379 if (ifp->if_capenable & IFCAP_HWRXTSTMP) { 3380 if (priv->clbr_done == 0) 3381 mlx5e_reset_calibration_callout(priv); 3382 } else { 3383 callout_drain(&priv->tstmp_clbr); 3384 priv->clbr_done = 0; 3385 } 3386 } 3387 out: 3388 PRIV_UNLOCK(priv); 3389 break; 3390 3391 case SIOCGI2C: 3392 ifr = (struct ifreq *)data; 3393 3394 /* 3395 * Copy from the user-space address ifr_data to the 3396 * kernel-space address i2c 3397 */ 3398 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 3399 if (error) 3400 break; 3401 3402 if (i2c.len > sizeof(i2c.data)) { 3403 error = EINVAL; 3404 break; 3405 } 3406 3407 PRIV_LOCK(priv); 3408 /* Get module_num which is required for the query_eeprom */ 3409 error = mlx5_query_module_num(priv->mdev, &module_num); 3410 if (error) { 3411 mlx5_en_err(ifp, 3412 "Query module num failed, eeprom reading is not supported\n"); 3413 error = EINVAL; 3414 goto err_i2c; 3415 } 3416 /* Check if module is present before doing an access */ 3417 module_status = mlx5_query_module_status(priv->mdev, module_num); 3418 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED) { 3419 error = EINVAL; 3420 goto err_i2c; 3421 } 3422 /* 3423 * Currently 0XA0 and 0xA2 are the only addresses permitted. 3424 * The internal conversion is as follows: 3425 */ 3426 if (i2c.dev_addr == 0xA0) 3427 read_addr = MLX5_I2C_ADDR_LOW; 3428 else if (i2c.dev_addr == 0xA2) 3429 read_addr = MLX5_I2C_ADDR_HIGH; 3430 else { 3431 mlx5_en_err(ifp, 3432 "Query eeprom failed, Invalid Address: %X\n", 3433 i2c.dev_addr); 3434 error = EINVAL; 3435 goto err_i2c; 3436 } 3437 error = mlx5_query_eeprom(priv->mdev, 3438 read_addr, MLX5_EEPROM_LOW_PAGE, 3439 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num, 3440 (uint32_t *)i2c.data, &size_read); 3441 if (error) { 3442 mlx5_en_err(ifp, 3443 "Query eeprom failed, eeprom reading is not supported\n"); 3444 error = EINVAL; 3445 goto err_i2c; 3446 } 3447 3448 if (i2c.len > MLX5_EEPROM_MAX_BYTES) { 3449 error = mlx5_query_eeprom(priv->mdev, 3450 read_addr, MLX5_EEPROM_LOW_PAGE, 3451 (uint32_t)(i2c.offset + size_read), 3452 (uint32_t)(i2c.len - size_read), module_num, 3453 (uint32_t *)(i2c.data + size_read), &size_read); 3454 } 3455 if (error) { 3456 mlx5_en_err(ifp, 3457 "Query eeprom failed, eeprom reading is not supported\n"); 3458 error = EINVAL; 3459 goto err_i2c; 3460 } 3461 3462 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 3463 err_i2c: 3464 PRIV_UNLOCK(priv); 3465 break; 3466 3467 default: 3468 error = ether_ioctl(ifp, command, data); 3469 break; 3470 } 3471 return (error); 3472 } 3473 3474 static int 3475 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev) 3476 { 3477 /* 3478 * TODO: uncoment once FW really sets all these bits if 3479 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap || 3480 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap || 3481 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return 3482 * -ENOTSUPP; 3483 */ 3484 3485 /* TODO: add more must-to-have features */ 3486 3487 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) 3488 return (-ENODEV); 3489 3490 return (0); 3491 } 3492 3493 static u16 3494 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev) 3495 { 3496 uint32_t bf_buf_size = (1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U; 3497 3498 bf_buf_size -= sizeof(struct mlx5e_tx_wqe) - 2; 3499 3500 /* verify against driver hardware limit */ 3501 if (bf_buf_size > MLX5E_MAX_TX_INLINE) 3502 bf_buf_size = MLX5E_MAX_TX_INLINE; 3503 3504 return (bf_buf_size); 3505 } 3506 3507 static int 3508 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev, 3509 struct mlx5e_priv *priv, 3510 int num_comp_vectors) 3511 { 3512 int err; 3513 3514 /* 3515 * TODO: Consider link speed for setting "log_sq_size", 3516 * "log_rq_size" and "cq_moderation_xxx": 3517 */ 3518 priv->params.log_sq_size = 3519 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; 3520 priv->params.log_rq_size = 3521 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; 3522 priv->params.rx_cq_moderation_usec = 3523 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 3524 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE : 3525 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; 3526 priv->params.rx_cq_moderation_mode = 3527 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0; 3528 priv->params.rx_cq_moderation_pkts = 3529 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; 3530 priv->params.tx_cq_moderation_usec = 3531 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; 3532 priv->params.tx_cq_moderation_pkts = 3533 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; 3534 priv->params.min_rx_wqes = 3535 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES; 3536 priv->params.rx_hash_log_tbl_sz = 3537 (order_base_2(num_comp_vectors) > 3538 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ? 3539 order_base_2(num_comp_vectors) : 3540 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ; 3541 priv->params.num_tc = 1; 3542 priv->params.default_vlan_prio = 0; 3543 priv->counter_set_id = -1; 3544 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev); 3545 3546 err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode); 3547 if (err) 3548 return (err); 3549 3550 /* 3551 * hw lro is currently defaulted to off. when it won't anymore we 3552 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)" 3553 */ 3554 priv->params.hw_lro_en = false; 3555 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; 3556 3557 /* 3558 * CQE zipping is currently defaulted to off. when it won't 3559 * anymore we will consider the HW capability: 3560 * "!!MLX5_CAP_GEN(mdev, cqe_compression)" 3561 */ 3562 priv->params.cqe_zipping_en = false; 3563 3564 priv->mdev = mdev; 3565 priv->params.num_channels = num_comp_vectors; 3566 priv->params.channels_rsss = 1; 3567 priv->order_base_2_num_channels = order_base_2(num_comp_vectors); 3568 priv->queue_mapping_channel_mask = 3569 roundup_pow_of_two(num_comp_vectors) - 1; 3570 priv->num_tc = priv->params.num_tc; 3571 priv->default_vlan_prio = priv->params.default_vlan_prio; 3572 3573 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work); 3574 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); 3575 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); 3576 3577 return (0); 3578 } 3579 3580 static int 3581 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn, 3582 struct mlx5_core_mr *mkey) 3583 { 3584 struct ifnet *ifp = priv->ifp; 3585 struct mlx5_core_dev *mdev = priv->mdev; 3586 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 3587 void *mkc; 3588 u32 *in; 3589 int err; 3590 3591 in = mlx5_vzalloc(inlen); 3592 if (in == NULL) { 3593 mlx5_en_err(ifp, "failed to allocate inbox\n"); 3594 return (-ENOMEM); 3595 } 3596 3597 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 3598 MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA); 3599 MLX5_SET(mkc, mkc, lw, 1); 3600 MLX5_SET(mkc, mkc, lr, 1); 3601 3602 MLX5_SET(mkc, mkc, pd, pdn); 3603 MLX5_SET(mkc, mkc, length64, 1); 3604 MLX5_SET(mkc, mkc, qpn, 0xffffff); 3605 3606 err = mlx5_core_create_mkey(mdev, mkey, in, inlen); 3607 if (err) 3608 mlx5_en_err(ifp, "mlx5_core_create_mkey failed, %d\n", 3609 err); 3610 3611 kvfree(in); 3612 return (err); 3613 } 3614 3615 static const char *mlx5e_vport_stats_desc[] = { 3616 MLX5E_VPORT_STATS(MLX5E_STATS_DESC) 3617 }; 3618 3619 static const char *mlx5e_pport_stats_desc[] = { 3620 MLX5E_PPORT_STATS(MLX5E_STATS_DESC) 3621 }; 3622 3623 static void 3624 mlx5e_priv_static_init(struct mlx5e_priv *priv, const uint32_t channels) 3625 { 3626 uint32_t x; 3627 3628 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF); 3629 sx_init(&priv->state_lock, "mlx5state"); 3630 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0); 3631 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock); 3632 for (x = 0; x != channels; x++) 3633 mlx5e_chan_static_init(priv, &priv->channel[x], x); 3634 } 3635 3636 static void 3637 mlx5e_priv_static_destroy(struct mlx5e_priv *priv, const uint32_t channels) 3638 { 3639 uint32_t x; 3640 3641 for (x = 0; x != channels; x++) 3642 mlx5e_chan_static_destroy(&priv->channel[x]); 3643 callout_drain(&priv->watchdog); 3644 mtx_destroy(&priv->async_events_mtx); 3645 sx_destroy(&priv->state_lock); 3646 } 3647 3648 static int 3649 sysctl_firmware(SYSCTL_HANDLER_ARGS) 3650 { 3651 /* 3652 * %d.%d%.d the string format. 3653 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536. 3654 * We need at most 5 chars to store that. 3655 * It also has: two "." and NULL at the end, which means we need 18 3656 * (5*3 + 3) chars at most. 3657 */ 3658 char fw[18]; 3659 struct mlx5e_priv *priv = arg1; 3660 int error; 3661 3662 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev), 3663 fw_rev_sub(priv->mdev)); 3664 error = sysctl_handle_string(oidp, fw, sizeof(fw), req); 3665 return (error); 3666 } 3667 3668 static void 3669 mlx5e_disable_tx_dma(struct mlx5e_channel *ch) 3670 { 3671 int i; 3672 3673 for (i = 0; i < ch->priv->num_tc; i++) 3674 mlx5e_drain_sq(&ch->sq[i]); 3675 } 3676 3677 static void 3678 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq) 3679 { 3680 3681 sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP); 3682 sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8); 3683 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0); 3684 sq->doorbell.d64 = 0; 3685 } 3686 3687 void 3688 mlx5e_resume_sq(struct mlx5e_sq *sq) 3689 { 3690 int err; 3691 3692 /* check if already enabled */ 3693 if (READ_ONCE(sq->running) != 0) 3694 return; 3695 3696 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR, 3697 MLX5_SQC_STATE_RST); 3698 if (err != 0) { 3699 mlx5_en_err(sq->ifp, 3700 "mlx5e_modify_sq() from ERR to RST failed: %d\n", err); 3701 } 3702 3703 sq->cc = 0; 3704 sq->pc = 0; 3705 3706 /* reset doorbell prior to moving from RST to RDY */ 3707 mlx5e_reset_sq_doorbell_record(sq); 3708 3709 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, 3710 MLX5_SQC_STATE_RDY); 3711 if (err != 0) { 3712 mlx5_en_err(sq->ifp, 3713 "mlx5e_modify_sq() from RST to RDY failed: %d\n", err); 3714 } 3715 3716 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL; 3717 WRITE_ONCE(sq->running, 1); 3718 } 3719 3720 static void 3721 mlx5e_enable_tx_dma(struct mlx5e_channel *ch) 3722 { 3723 int i; 3724 3725 for (i = 0; i < ch->priv->num_tc; i++) 3726 mlx5e_resume_sq(&ch->sq[i]); 3727 } 3728 3729 static void 3730 mlx5e_disable_rx_dma(struct mlx5e_channel *ch) 3731 { 3732 struct mlx5e_rq *rq = &ch->rq; 3733 int err; 3734 3735 mtx_lock(&rq->mtx); 3736 rq->enabled = 0; 3737 callout_stop(&rq->watchdog); 3738 mtx_unlock(&rq->mtx); 3739 3740 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 3741 if (err != 0) { 3742 mlx5_en_err(rq->ifp, 3743 "mlx5e_modify_rq() from RDY to RST failed: %d\n", err); 3744 } 3745 3746 while (!mlx5_wq_ll_is_empty(&rq->wq)) { 3747 msleep(1); 3748 rq->cq.mcq.comp(&rq->cq.mcq); 3749 } 3750 3751 /* 3752 * Transitioning into RST state will allow the FW to track less ERR state queues, 3753 * thus reducing the recv queue flushing time 3754 */ 3755 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST); 3756 if (err != 0) { 3757 mlx5_en_err(rq->ifp, 3758 "mlx5e_modify_rq() from ERR to RST failed: %d\n", err); 3759 } 3760 } 3761 3762 static void 3763 mlx5e_enable_rx_dma(struct mlx5e_channel *ch) 3764 { 3765 struct mlx5e_rq *rq = &ch->rq; 3766 int err; 3767 3768 rq->wq.wqe_ctr = 0; 3769 mlx5_wq_ll_update_db_record(&rq->wq); 3770 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 3771 if (err != 0) { 3772 mlx5_en_err(rq->ifp, 3773 "mlx5e_modify_rq() from RST to RDY failed: %d\n", err); 3774 } 3775 3776 rq->enabled = 1; 3777 3778 rq->cq.mcq.comp(&rq->cq.mcq); 3779 } 3780 3781 void 3782 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value) 3783 { 3784 int i; 3785 3786 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3787 return; 3788 3789 for (i = 0; i < priv->params.num_channels; i++) { 3790 if (value) 3791 mlx5e_disable_tx_dma(&priv->channel[i]); 3792 else 3793 mlx5e_enable_tx_dma(&priv->channel[i]); 3794 } 3795 } 3796 3797 void 3798 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value) 3799 { 3800 int i; 3801 3802 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3803 return; 3804 3805 for (i = 0; i < priv->params.num_channels; i++) { 3806 if (value) 3807 mlx5e_disable_rx_dma(&priv->channel[i]); 3808 else 3809 mlx5e_enable_rx_dma(&priv->channel[i]); 3810 } 3811 } 3812 3813 static void 3814 mlx5e_add_hw_stats(struct mlx5e_priv *priv) 3815 { 3816 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 3817 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0, 3818 sysctl_firmware, "A", "HCA firmware version"); 3819 3820 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 3821 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0, 3822 "Board ID"); 3823 } 3824 3825 static int 3826 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS) 3827 { 3828 struct mlx5e_priv *priv = arg1; 3829 uint8_t temp[MLX5E_MAX_PRIORITY]; 3830 uint32_t tx_pfc; 3831 int err; 3832 int i; 3833 3834 PRIV_LOCK(priv); 3835 3836 tx_pfc = priv->params.tx_priority_flow_control; 3837 3838 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) 3839 temp[i] = (tx_pfc >> i) & 1; 3840 3841 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY); 3842 if (err || !req->newptr) 3843 goto done; 3844 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY); 3845 if (err) 3846 goto done; 3847 3848 priv->params.tx_priority_flow_control = 0; 3849 3850 /* range check input value */ 3851 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) { 3852 if (temp[i] > 1) { 3853 err = ERANGE; 3854 goto done; 3855 } 3856 priv->params.tx_priority_flow_control |= (temp[i] << i); 3857 } 3858 3859 /* check if update is required */ 3860 if (tx_pfc != priv->params.tx_priority_flow_control) 3861 err = -mlx5e_set_port_pfc(priv); 3862 done: 3863 if (err != 0) 3864 priv->params.tx_priority_flow_control= tx_pfc; 3865 PRIV_UNLOCK(priv); 3866 3867 return (err); 3868 } 3869 3870 static int 3871 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS) 3872 { 3873 struct mlx5e_priv *priv = arg1; 3874 uint8_t temp[MLX5E_MAX_PRIORITY]; 3875 uint32_t rx_pfc; 3876 int err; 3877 int i; 3878 3879 PRIV_LOCK(priv); 3880 3881 rx_pfc = priv->params.rx_priority_flow_control; 3882 3883 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) 3884 temp[i] = (rx_pfc >> i) & 1; 3885 3886 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY); 3887 if (err || !req->newptr) 3888 goto done; 3889 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY); 3890 if (err) 3891 goto done; 3892 3893 priv->params.rx_priority_flow_control = 0; 3894 3895 /* range check input value */ 3896 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) { 3897 if (temp[i] > 1) { 3898 err = ERANGE; 3899 goto done; 3900 } 3901 priv->params.rx_priority_flow_control |= (temp[i] << i); 3902 } 3903 3904 /* check if update is required */ 3905 if (rx_pfc != priv->params.rx_priority_flow_control) { 3906 err = -mlx5e_set_port_pfc(priv); 3907 if (err == 0 && priv->sw_is_port_buf_owner) 3908 err = mlx5e_update_buf_lossy(priv); 3909 } 3910 done: 3911 if (err != 0) 3912 priv->params.rx_priority_flow_control= rx_pfc; 3913 PRIV_UNLOCK(priv); 3914 3915 return (err); 3916 } 3917 3918 static void 3919 mlx5e_setup_pauseframes(struct mlx5e_priv *priv) 3920 { 3921 #if (__FreeBSD_version < 1100000) 3922 char path[96]; 3923 #endif 3924 int error; 3925 3926 /* enable pauseframes by default */ 3927 priv->params.tx_pauseframe_control = 1; 3928 priv->params.rx_pauseframe_control = 1; 3929 3930 /* disable ports flow control, PFC, by default */ 3931 priv->params.tx_priority_flow_control = 0; 3932 priv->params.rx_priority_flow_control = 0; 3933 3934 #if (__FreeBSD_version < 1100000) 3935 /* compute path for sysctl */ 3936 snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control", 3937 device_get_unit(priv->mdev->pdev->dev.bsddev)); 3938 3939 /* try to fetch tunable, if any */ 3940 TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control); 3941 3942 /* compute path for sysctl */ 3943 snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control", 3944 device_get_unit(priv->mdev->pdev->dev.bsddev)); 3945 3946 /* try to fetch tunable, if any */ 3947 TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control); 3948 #endif 3949 3950 /* register pauseframe SYSCTLs */ 3951 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 3952 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN, 3953 &priv->params.tx_pauseframe_control, 0, 3954 "Set to enable TX pause frames. Clear to disable."); 3955 3956 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 3957 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN, 3958 &priv->params.rx_pauseframe_control, 0, 3959 "Set to enable RX pause frames. Clear to disable."); 3960 3961 /* register priority flow control, PFC, SYSCTLs */ 3962 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 3963 OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN | 3964 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU", 3965 "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable."); 3966 3967 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 3968 OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN | 3969 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU", 3970 "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable."); 3971 3972 PRIV_LOCK(priv); 3973 3974 /* range check */ 3975 priv->params.tx_pauseframe_control = 3976 priv->params.tx_pauseframe_control ? 1 : 0; 3977 priv->params.rx_pauseframe_control = 3978 priv->params.rx_pauseframe_control ? 1 : 0; 3979 3980 /* update firmware */ 3981 error = mlx5e_set_port_pause_and_pfc(priv); 3982 if (error == -EINVAL) { 3983 mlx5_en_err(priv->ifp, 3984 "Global pauseframes must be disabled before enabling PFC.\n"); 3985 priv->params.rx_priority_flow_control = 0; 3986 priv->params.tx_priority_flow_control = 0; 3987 3988 /* update firmware */ 3989 (void) mlx5e_set_port_pause_and_pfc(priv); 3990 } 3991 PRIV_UNLOCK(priv); 3992 } 3993 3994 static int 3995 mlx5e_ul_snd_tag_alloc(struct ifnet *ifp, 3996 union if_snd_tag_alloc_params *params, 3997 struct m_snd_tag **ppmt) 3998 { 3999 struct mlx5e_priv *priv; 4000 struct mlx5e_channel *pch; 4001 4002 priv = ifp->if_softc; 4003 4004 if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) { 4005 return (EOPNOTSUPP); 4006 } else { 4007 /* keep this code synced with mlx5e_select_queue() */ 4008 u32 ch = priv->params.num_channels; 4009 #ifdef RSS 4010 u32 temp; 4011 4012 if (rss_hash2bucket(params->hdr.flowid, 4013 params->hdr.flowtype, &temp) == 0) 4014 ch = temp % ch; 4015 else 4016 #endif 4017 ch = (params->hdr.flowid % 128) % ch; 4018 4019 /* 4020 * NOTE: The channels array is only freed at detach 4021 * and it safe to return a pointer to the send tag 4022 * inside the channels structure as long as we 4023 * reference the priv. 4024 */ 4025 pch = priv->channel + ch; 4026 4027 /* check if send queue is not running */ 4028 if (unlikely(pch->sq[0].running == 0)) 4029 return (ENXIO); 4030 m_snd_tag_ref(&pch->tag.m_snd_tag); 4031 *ppmt = &pch->tag.m_snd_tag; 4032 return (0); 4033 } 4034 } 4035 4036 static int 4037 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params) 4038 { 4039 struct mlx5e_channel *pch = 4040 container_of(pmt, struct mlx5e_channel, tag.m_snd_tag); 4041 4042 params->unlimited.max_rate = -1ULL; 4043 params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]); 4044 return (0); 4045 } 4046 4047 static void 4048 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt) 4049 { 4050 struct mlx5e_channel *pch = 4051 container_of(pmt, struct mlx5e_channel, tag.m_snd_tag); 4052 4053 complete(&pch->completion); 4054 } 4055 4056 static int 4057 mlx5e_snd_tag_alloc(struct ifnet *ifp, 4058 union if_snd_tag_alloc_params *params, 4059 struct m_snd_tag **ppmt) 4060 { 4061 4062 switch (params->hdr.type) { 4063 #ifdef RATELIMIT 4064 case IF_SND_TAG_TYPE_RATE_LIMIT: 4065 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt)); 4066 #endif 4067 case IF_SND_TAG_TYPE_UNLIMITED: 4068 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt)); 4069 default: 4070 return (EOPNOTSUPP); 4071 } 4072 } 4073 4074 static int 4075 mlx5e_snd_tag_modify(struct m_snd_tag *pmt, union if_snd_tag_modify_params *params) 4076 { 4077 struct mlx5e_snd_tag *tag = 4078 container_of(pmt, struct mlx5e_snd_tag, m_snd_tag); 4079 4080 switch (tag->type) { 4081 #ifdef RATELIMIT 4082 case IF_SND_TAG_TYPE_RATE_LIMIT: 4083 return (mlx5e_rl_snd_tag_modify(pmt, params)); 4084 #endif 4085 case IF_SND_TAG_TYPE_UNLIMITED: 4086 default: 4087 return (EOPNOTSUPP); 4088 } 4089 } 4090 4091 static int 4092 mlx5e_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params) 4093 { 4094 struct mlx5e_snd_tag *tag = 4095 container_of(pmt, struct mlx5e_snd_tag, m_snd_tag); 4096 4097 switch (tag->type) { 4098 #ifdef RATELIMIT 4099 case IF_SND_TAG_TYPE_RATE_LIMIT: 4100 return (mlx5e_rl_snd_tag_query(pmt, params)); 4101 #endif 4102 case IF_SND_TAG_TYPE_UNLIMITED: 4103 return (mlx5e_ul_snd_tag_query(pmt, params)); 4104 default: 4105 return (EOPNOTSUPP); 4106 } 4107 } 4108 4109 #ifdef RATELIMIT 4110 #define NUM_HDWR_RATES_MLX 13 4111 static const uint64_t adapter_rates_mlx[NUM_HDWR_RATES_MLX] = { 4112 135375, /* 1,083,000 */ 4113 180500, /* 1,444,000 */ 4114 270750, /* 2,166,000 */ 4115 361000, /* 2,888,000 */ 4116 541500, /* 4,332,000 */ 4117 721875, /* 5,775,000 */ 4118 1082875, /* 8,663,000 */ 4119 1443875, /* 11,551,000 */ 4120 2165750, /* 17,326,000 */ 4121 2887750, /* 23,102,000 */ 4122 4331625, /* 34,653,000 */ 4123 5775500, /* 46,204,000 */ 4124 8663125 /* 69,305,000 */ 4125 }; 4126 4127 static void 4128 mlx5e_ratelimit_query(struct ifnet *ifp __unused, struct if_ratelimit_query_results *q) 4129 { 4130 /* 4131 * This function needs updating by the driver maintainer! 4132 * For the MLX card there are currently (ConectX-4?) 13 4133 * pre-set rates and others i.e. ConnectX-5, 6, 7?? 4134 * 4135 * This will change based on later adapters 4136 * and this code should be updated to look at ifp 4137 * and figure out the specific adapter type 4138 * settings i.e. how many rates as well 4139 * as if they are fixed (as is shown here) or 4140 * if they are dynamic (example chelsio t4). Also if there 4141 * is a maximum number of flows that the adapter 4142 * can handle that too needs to be updated in 4143 * the max_flows field. 4144 */ 4145 q->rate_table = adapter_rates_mlx; 4146 q->flags = RT_IS_FIXED_TABLE; 4147 q->max_flows = 0; /* mlx has no limit */ 4148 q->number_of_rates = NUM_HDWR_RATES_MLX; 4149 q->min_segment_burst = 1; 4150 } 4151 #endif 4152 4153 static void 4154 mlx5e_snd_tag_free(struct m_snd_tag *pmt) 4155 { 4156 struct mlx5e_snd_tag *tag = 4157 container_of(pmt, struct mlx5e_snd_tag, m_snd_tag); 4158 4159 switch (tag->type) { 4160 #ifdef RATELIMIT 4161 case IF_SND_TAG_TYPE_RATE_LIMIT: 4162 mlx5e_rl_snd_tag_free(pmt); 4163 break; 4164 #endif 4165 case IF_SND_TAG_TYPE_UNLIMITED: 4166 mlx5e_ul_snd_tag_free(pmt); 4167 break; 4168 default: 4169 break; 4170 } 4171 } 4172 4173 static void * 4174 mlx5e_create_ifp(struct mlx5_core_dev *mdev) 4175 { 4176 struct ifnet *ifp; 4177 struct mlx5e_priv *priv; 4178 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4); 4179 u8 connector_type; 4180 struct sysctl_oid_list *child; 4181 int ncv = mdev->priv.eq_table.num_comp_vectors; 4182 char unit[16]; 4183 struct pfil_head_args pa; 4184 int err; 4185 int i,j; 4186 u32 eth_proto_cap; 4187 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 4188 bool ext = 0; 4189 u32 speeds_num; 4190 struct media media_entry = {}; 4191 4192 if (mlx5e_check_required_hca_cap(mdev)) { 4193 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n"); 4194 return (NULL); 4195 } 4196 /* 4197 * Try to allocate the priv and make room for worst-case 4198 * number of channel structures: 4199 */ 4200 priv = malloc(sizeof(*priv) + 4201 (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors), 4202 M_MLX5EN, M_WAITOK | M_ZERO); 4203 4204 ifp = priv->ifp = if_alloc_dev(IFT_ETHER, mdev->pdev->dev.bsddev); 4205 if (ifp == NULL) { 4206 mlx5_core_err(mdev, "if_alloc() failed\n"); 4207 goto err_free_priv; 4208 } 4209 /* setup all static fields */ 4210 mlx5e_priv_static_init(priv, mdev->priv.eq_table.num_comp_vectors); 4211 4212 ifp->if_softc = priv; 4213 if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev)); 4214 ifp->if_mtu = ETHERMTU; 4215 ifp->if_init = mlx5e_open; 4216 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 4217 ifp->if_ioctl = mlx5e_ioctl; 4218 ifp->if_transmit = mlx5e_xmit; 4219 ifp->if_qflush = if_qflush; 4220 #if (__FreeBSD_version >= 1100000) 4221 ifp->if_get_counter = mlx5e_get_counter; 4222 #endif 4223 ifp->if_snd.ifq_maxlen = ifqmaxlen; 4224 /* 4225 * Set driver features 4226 */ 4227 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6; 4228 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 4229 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER; 4230 ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU; 4231 ifp->if_capabilities |= IFCAP_LRO; 4232 ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO; 4233 ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP; 4234 ifp->if_capabilities |= IFCAP_NOMAP; 4235 ifp->if_capabilities |= IFCAP_TXRTLMT; 4236 ifp->if_snd_tag_alloc = mlx5e_snd_tag_alloc; 4237 ifp->if_snd_tag_free = mlx5e_snd_tag_free; 4238 ifp->if_snd_tag_modify = mlx5e_snd_tag_modify; 4239 ifp->if_snd_tag_query = mlx5e_snd_tag_query; 4240 #ifdef RATELIMIT 4241 ifp->if_ratelimit_query = mlx5e_ratelimit_query; 4242 #endif 4243 /* set TSO limits so that we don't have to drop TX packets */ 4244 ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 4245 ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */; 4246 ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE; 4247 4248 ifp->if_capenable = ifp->if_capabilities; 4249 ifp->if_hwassist = 0; 4250 if (ifp->if_capenable & IFCAP_TSO) 4251 ifp->if_hwassist |= CSUM_TSO; 4252 if (ifp->if_capenable & IFCAP_TXCSUM) 4253 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP); 4254 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6) 4255 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 4256 4257 /* ifnet sysctl tree */ 4258 sysctl_ctx_init(&priv->sysctl_ctx); 4259 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev), 4260 OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name"); 4261 if (priv->sysctl_ifnet == NULL) { 4262 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4263 goto err_free_sysctl; 4264 } 4265 snprintf(unit, sizeof(unit), "%d", ifp->if_dunit); 4266 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4267 OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit"); 4268 if (priv->sysctl_ifnet == NULL) { 4269 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4270 goto err_free_sysctl; 4271 } 4272 4273 /* HW sysctl tree */ 4274 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev)); 4275 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child, 4276 OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw"); 4277 if (priv->sysctl_hw == NULL) { 4278 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4279 goto err_free_sysctl; 4280 } 4281 4282 err = mlx5e_build_ifp_priv(mdev, priv, ncv); 4283 if (err) { 4284 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err); 4285 goto err_free_sysctl; 4286 } 4287 4288 /* reuse mlx5core's watchdog workqueue */ 4289 priv->wq = mdev->priv.health.wq_watchdog; 4290 4291 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar); 4292 if (err) { 4293 mlx5_en_err(ifp, "mlx5_alloc_map_uar failed, %d\n", err); 4294 goto err_free_wq; 4295 } 4296 err = mlx5_core_alloc_pd(mdev, &priv->pdn); 4297 if (err) { 4298 mlx5_en_err(ifp, "mlx5_core_alloc_pd failed, %d\n", err); 4299 goto err_unmap_free_uar; 4300 } 4301 err = mlx5_alloc_transport_domain(mdev, &priv->tdn); 4302 if (err) { 4303 mlx5_en_err(ifp, 4304 "mlx5_alloc_transport_domain failed, %d\n", err); 4305 goto err_dealloc_pd; 4306 } 4307 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr); 4308 if (err) { 4309 mlx5_en_err(ifp, "mlx5e_create_mkey failed, %d\n", err); 4310 goto err_dealloc_transport_domain; 4311 } 4312 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr); 4313 4314 /* check if we should generate a random MAC address */ 4315 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 && 4316 is_zero_ether_addr(dev_addr)) { 4317 random_ether_addr(dev_addr); 4318 mlx5_en_err(ifp, "Assigned random MAC address\n"); 4319 } 4320 #ifdef RATELIMIT 4321 err = mlx5e_rl_init(priv); 4322 if (err) { 4323 mlx5_en_err(ifp, "mlx5e_rl_init failed, %d\n", err); 4324 goto err_create_mkey; 4325 } 4326 #endif 4327 4328 /* set default MTU */ 4329 mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu); 4330 4331 /* Set default media status */ 4332 priv->media_status_last = IFM_AVALID; 4333 priv->media_active_last = IFM_ETHER | IFM_AUTO | 4334 IFM_ETH_RXPAUSE | IFM_FDX; 4335 4336 /* setup default pauseframes configuration */ 4337 mlx5e_setup_pauseframes(priv); 4338 4339 /* Setup supported medias */ 4340 //TODO: If we failed to query ptys is it ok to proceed?? 4341 if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) { 4342 ext = MLX5_CAP_PCAM_FEATURE(mdev, 4343 ptys_extended_ethernet); 4344 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 4345 eth_proto_capability); 4346 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type)) 4347 connector_type = MLX5_GET(ptys_reg, out, 4348 connector_type); 4349 } else { 4350 eth_proto_cap = 0; 4351 mlx5_en_err(ifp, "Query port media capability failed, %d\n", err); 4352 } 4353 4354 ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK, 4355 mlx5e_media_change, mlx5e_media_status); 4356 4357 speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER : MLX5E_LINK_SPEEDS_NUMBER; 4358 for (i = 0; i != speeds_num; i++) { 4359 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) { 4360 media_entry = ext ? mlx5e_ext_mode_table[i][j] : 4361 mlx5e_mode_table[i][j]; 4362 if (media_entry.baudrate == 0) 4363 continue; 4364 if (MLX5E_PROT_MASK(i) & eth_proto_cap) { 4365 ifmedia_add(&priv->media, 4366 media_entry.subtype | 4367 IFM_ETHER, 0, NULL); 4368 ifmedia_add(&priv->media, 4369 media_entry.subtype | 4370 IFM_ETHER | IFM_FDX | 4371 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 4372 } 4373 } 4374 } 4375 4376 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL); 4377 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX | 4378 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 4379 4380 /* Set autoselect by default */ 4381 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX | 4382 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE); 4383 ether_ifattach(ifp, dev_addr); 4384 4385 /* Register for VLAN events */ 4386 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config, 4387 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST); 4388 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig, 4389 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST); 4390 4391 /* Link is down by default */ 4392 if_link_state_change(ifp, LINK_STATE_DOWN); 4393 4394 mlx5e_enable_async_events(priv); 4395 4396 mlx5e_add_hw_stats(priv); 4397 4398 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4399 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM, 4400 priv->stats.vport.arg); 4401 4402 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4403 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM, 4404 priv->stats.pport.arg); 4405 4406 mlx5e_create_ethtool(priv); 4407 4408 mtx_lock(&priv->async_events_mtx); 4409 mlx5e_update_stats(priv); 4410 mtx_unlock(&priv->async_events_mtx); 4411 4412 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4413 OID_AUTO, "rx_clbr_done", CTLFLAG_RD, 4414 &priv->clbr_done, 0, 4415 "RX timestamps calibration state"); 4416 callout_init(&priv->tstmp_clbr, CALLOUT_DIRECT); 4417 mlx5e_reset_calibration_callout(priv); 4418 4419 pa.pa_version = PFIL_VERSION; 4420 pa.pa_flags = PFIL_IN; 4421 pa.pa_type = PFIL_TYPE_ETHERNET; 4422 pa.pa_headname = ifp->if_xname; 4423 priv->pfil = pfil_head_register(&pa); 4424 4425 return (priv); 4426 4427 #ifdef RATELIMIT 4428 err_create_mkey: 4429 mlx5_core_destroy_mkey(priv->mdev, &priv->mr); 4430 #endif 4431 err_dealloc_transport_domain: 4432 mlx5_dealloc_transport_domain(mdev, priv->tdn); 4433 4434 err_dealloc_pd: 4435 mlx5_core_dealloc_pd(mdev, priv->pdn); 4436 4437 err_unmap_free_uar: 4438 mlx5_unmap_free_uar(mdev, &priv->cq_uar); 4439 4440 err_free_wq: 4441 flush_workqueue(priv->wq); 4442 4443 err_free_sysctl: 4444 sysctl_ctx_free(&priv->sysctl_ctx); 4445 if (priv->sysctl_debug) 4446 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx); 4447 mlx5e_priv_static_destroy(priv, mdev->priv.eq_table.num_comp_vectors); 4448 if_free(ifp); 4449 4450 err_free_priv: 4451 free(priv, M_MLX5EN); 4452 return (NULL); 4453 } 4454 4455 static void 4456 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv) 4457 { 4458 struct mlx5e_priv *priv = vpriv; 4459 struct ifnet *ifp = priv->ifp; 4460 4461 /* don't allow more IOCTLs */ 4462 priv->gone = 1; 4463 4464 /* XXX wait a bit to allow IOCTL handlers to complete */ 4465 pause("W", hz); 4466 4467 #ifdef RATELIMIT 4468 /* 4469 * The kernel can have reference(s) via the m_snd_tag's into 4470 * the ratelimit channels, and these must go away before 4471 * detaching: 4472 */ 4473 while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) { 4474 mlx5_en_err(priv->ifp, 4475 "Waiting for all ratelimit connections to terminate\n"); 4476 pause("W", hz); 4477 } 4478 #endif 4479 /* wait for all unlimited send tags to complete */ 4480 mlx5e_priv_wait_for_completion(priv, mdev->priv.eq_table.num_comp_vectors); 4481 4482 /* stop watchdog timer */ 4483 callout_drain(&priv->watchdog); 4484 4485 callout_drain(&priv->tstmp_clbr); 4486 4487 if (priv->vlan_attach != NULL) 4488 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach); 4489 if (priv->vlan_detach != NULL) 4490 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach); 4491 4492 /* make sure device gets closed */ 4493 PRIV_LOCK(priv); 4494 mlx5e_close_locked(ifp); 4495 PRIV_UNLOCK(priv); 4496 4497 /* deregister pfil */ 4498 if (priv->pfil != NULL) { 4499 pfil_head_unregister(priv->pfil); 4500 priv->pfil = NULL; 4501 } 4502 4503 /* unregister device */ 4504 ifmedia_removeall(&priv->media); 4505 ether_ifdetach(ifp); 4506 4507 #ifdef RATELIMIT 4508 mlx5e_rl_cleanup(priv); 4509 #endif 4510 /* destroy all remaining sysctl nodes */ 4511 sysctl_ctx_free(&priv->stats.vport.ctx); 4512 sysctl_ctx_free(&priv->stats.pport.ctx); 4513 if (priv->sysctl_debug) 4514 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx); 4515 sysctl_ctx_free(&priv->sysctl_ctx); 4516 4517 mlx5_core_destroy_mkey(priv->mdev, &priv->mr); 4518 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn); 4519 mlx5_core_dealloc_pd(priv->mdev, priv->pdn); 4520 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar); 4521 mlx5e_disable_async_events(priv); 4522 flush_workqueue(priv->wq); 4523 mlx5e_priv_static_destroy(priv, mdev->priv.eq_table.num_comp_vectors); 4524 if_free(ifp); 4525 free(priv, M_MLX5EN); 4526 } 4527 4528 static void * 4529 mlx5e_get_ifp(void *vpriv) 4530 { 4531 struct mlx5e_priv *priv = vpriv; 4532 4533 return (priv->ifp); 4534 } 4535 4536 static struct mlx5_interface mlx5e_interface = { 4537 .add = mlx5e_create_ifp, 4538 .remove = mlx5e_destroy_ifp, 4539 .event = mlx5e_async_event, 4540 .protocol = MLX5_INTERFACE_PROTOCOL_ETH, 4541 .get_dev = mlx5e_get_ifp, 4542 }; 4543 4544 void 4545 mlx5e_init(void) 4546 { 4547 mlx5_register_interface(&mlx5e_interface); 4548 } 4549 4550 void 4551 mlx5e_cleanup(void) 4552 { 4553 mlx5_unregister_interface(&mlx5e_interface); 4554 } 4555 4556 static void 4557 mlx5e_show_version(void __unused *arg) 4558 { 4559 4560 printf("%s", mlx5e_version); 4561 } 4562 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL); 4563 4564 module_init_order(mlx5e_init, SI_ORDER_THIRD); 4565 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD); 4566 4567 #if (__FreeBSD_version >= 1100000) 4568 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1); 4569 #endif 4570 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1); 4571 MODULE_VERSION(mlx5en, 1); 4572