1 /*- 2 * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include "opt_kern_tls.h" 29 30 #include "en.h" 31 32 #include <sys/eventhandler.h> 33 #include <sys/sockio.h> 34 #include <machine/atomic.h> 35 36 #include <net/debugnet.h> 37 38 #ifndef ETH_DRIVER_VERSION 39 #define ETH_DRIVER_VERSION "3.6.0" 40 #endif 41 #define DRIVER_RELDATE "December 2020" 42 43 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver " 44 ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n"; 45 46 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs); 47 48 struct mlx5e_channel_param { 49 struct mlx5e_rq_param rq; 50 struct mlx5e_sq_param sq; 51 struct mlx5e_cq_param rx_cq; 52 struct mlx5e_cq_param tx_cq; 53 }; 54 55 struct media { 56 u32 subtype; 57 u64 baudrate; 58 }; 59 60 static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = { 61 62 [MLX5E_1000BASE_CX_SGMII][MLX5E_SGMII] = { 63 .subtype = IFM_1000_CX_SGMII, 64 .baudrate = IF_Mbps(1000ULL), 65 }, 66 [MLX5E_1000BASE_KX][MLX5E_KX] = { 67 .subtype = IFM_1000_KX, 68 .baudrate = IF_Mbps(1000ULL), 69 }, 70 [MLX5E_10GBASE_CX4][MLX5E_CX4] = { 71 .subtype = IFM_10G_CX4, 72 .baudrate = IF_Gbps(10ULL), 73 }, 74 [MLX5E_10GBASE_KX4][MLX5E_KX4] = { 75 .subtype = IFM_10G_KX4, 76 .baudrate = IF_Gbps(10ULL), 77 }, 78 [MLX5E_10GBASE_KR][MLX5E_KR] = { 79 .subtype = IFM_10G_KR, 80 .baudrate = IF_Gbps(10ULL), 81 }, 82 [MLX5E_20GBASE_KR2][MLX5E_KR2] = { 83 .subtype = IFM_20G_KR2, 84 .baudrate = IF_Gbps(20ULL), 85 }, 86 [MLX5E_40GBASE_CR4][MLX5E_CR4] = { 87 .subtype = IFM_40G_CR4, 88 .baudrate = IF_Gbps(40ULL), 89 }, 90 [MLX5E_40GBASE_KR4][MLX5E_KR4] = { 91 .subtype = IFM_40G_KR4, 92 .baudrate = IF_Gbps(40ULL), 93 }, 94 [MLX5E_56GBASE_R4][MLX5E_R] = { 95 .subtype = IFM_56G_R4, 96 .baudrate = IF_Gbps(56ULL), 97 }, 98 [MLX5E_10GBASE_CR][MLX5E_CR1] = { 99 .subtype = IFM_10G_CR1, 100 .baudrate = IF_Gbps(10ULL), 101 }, 102 [MLX5E_10GBASE_SR][MLX5E_SR] = { 103 .subtype = IFM_10G_SR, 104 .baudrate = IF_Gbps(10ULL), 105 }, 106 [MLX5E_10GBASE_ER_LR][MLX5E_ER] = { 107 .subtype = IFM_10G_ER, 108 .baudrate = IF_Gbps(10ULL), 109 }, 110 [MLX5E_10GBASE_ER_LR][MLX5E_LR] = { 111 .subtype = IFM_10G_LR, 112 .baudrate = IF_Gbps(10ULL), 113 }, 114 [MLX5E_40GBASE_SR4][MLX5E_SR4] = { 115 .subtype = IFM_40G_SR4, 116 .baudrate = IF_Gbps(40ULL), 117 }, 118 [MLX5E_40GBASE_LR4_ER4][MLX5E_LR4] = { 119 .subtype = IFM_40G_LR4, 120 .baudrate = IF_Gbps(40ULL), 121 }, 122 [MLX5E_40GBASE_LR4_ER4][MLX5E_ER4] = { 123 .subtype = IFM_40G_ER4, 124 .baudrate = IF_Gbps(40ULL), 125 }, 126 [MLX5E_100GBASE_CR4][MLX5E_CR4] = { 127 .subtype = IFM_100G_CR4, 128 .baudrate = IF_Gbps(100ULL), 129 }, 130 [MLX5E_100GBASE_SR4][MLX5E_SR4] = { 131 .subtype = IFM_100G_SR4, 132 .baudrate = IF_Gbps(100ULL), 133 }, 134 [MLX5E_100GBASE_KR4][MLX5E_KR4] = { 135 .subtype = IFM_100G_KR4, 136 .baudrate = IF_Gbps(100ULL), 137 }, 138 [MLX5E_100GBASE_LR4][MLX5E_LR4] = { 139 .subtype = IFM_100G_LR4, 140 .baudrate = IF_Gbps(100ULL), 141 }, 142 [MLX5E_100BASE_TX][MLX5E_TX] = { 143 .subtype = IFM_100_TX, 144 .baudrate = IF_Mbps(100ULL), 145 }, 146 [MLX5E_1000BASE_T][MLX5E_T] = { 147 .subtype = IFM_1000_T, 148 .baudrate = IF_Mbps(1000ULL), 149 }, 150 [MLX5E_10GBASE_T][MLX5E_T] = { 151 .subtype = IFM_10G_T, 152 .baudrate = IF_Gbps(10ULL), 153 }, 154 [MLX5E_25GBASE_CR][MLX5E_CR] = { 155 .subtype = IFM_25G_CR, 156 .baudrate = IF_Gbps(25ULL), 157 }, 158 [MLX5E_25GBASE_KR][MLX5E_KR] = { 159 .subtype = IFM_25G_KR, 160 .baudrate = IF_Gbps(25ULL), 161 }, 162 [MLX5E_25GBASE_SR][MLX5E_SR] = { 163 .subtype = IFM_25G_SR, 164 .baudrate = IF_Gbps(25ULL), 165 }, 166 [MLX5E_50GBASE_CR2][MLX5E_CR2] = { 167 .subtype = IFM_50G_CR2, 168 .baudrate = IF_Gbps(50ULL), 169 }, 170 [MLX5E_50GBASE_KR2][MLX5E_KR2] = { 171 .subtype = IFM_50G_KR2, 172 .baudrate = IF_Gbps(50ULL), 173 }, 174 [MLX5E_50GBASE_KR4][MLX5E_KR4] = { 175 .subtype = IFM_50G_KR4, 176 .baudrate = IF_Gbps(50ULL), 177 }, 178 }; 179 180 static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = { 181 [MLX5E_SGMII_100M][MLX5E_SGMII] = { 182 .subtype = IFM_100_SGMII, 183 .baudrate = IF_Mbps(100), 184 }, 185 [MLX5E_1000BASE_X_SGMII][MLX5E_KX] = { 186 .subtype = IFM_1000_KX, 187 .baudrate = IF_Mbps(1000), 188 }, 189 [MLX5E_1000BASE_X_SGMII][MLX5E_CX_SGMII] = { 190 .subtype = IFM_1000_CX_SGMII, 191 .baudrate = IF_Mbps(1000), 192 }, 193 [MLX5E_1000BASE_X_SGMII][MLX5E_CX] = { 194 .subtype = IFM_1000_CX, 195 .baudrate = IF_Mbps(1000), 196 }, 197 [MLX5E_1000BASE_X_SGMII][MLX5E_LX] = { 198 .subtype = IFM_1000_LX, 199 .baudrate = IF_Mbps(1000), 200 }, 201 [MLX5E_1000BASE_X_SGMII][MLX5E_SX] = { 202 .subtype = IFM_1000_SX, 203 .baudrate = IF_Mbps(1000), 204 }, 205 [MLX5E_1000BASE_X_SGMII][MLX5E_T] = { 206 .subtype = IFM_1000_T, 207 .baudrate = IF_Mbps(1000), 208 }, 209 [MLX5E_5GBASE_R][MLX5E_T] = { 210 .subtype = IFM_5000_T, 211 .baudrate = IF_Mbps(5000), 212 }, 213 [MLX5E_5GBASE_R][MLX5E_KR] = { 214 .subtype = IFM_5000_KR, 215 .baudrate = IF_Mbps(5000), 216 }, 217 [MLX5E_5GBASE_R][MLX5E_KR1] = { 218 .subtype = IFM_5000_KR1, 219 .baudrate = IF_Mbps(5000), 220 }, 221 [MLX5E_5GBASE_R][MLX5E_KR_S] = { 222 .subtype = IFM_5000_KR_S, 223 .baudrate = IF_Mbps(5000), 224 }, 225 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_ER] = { 226 .subtype = IFM_10G_ER, 227 .baudrate = IF_Gbps(10ULL), 228 }, 229 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_KR] = { 230 .subtype = IFM_10G_KR, 231 .baudrate = IF_Gbps(10ULL), 232 }, 233 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_LR] = { 234 .subtype = IFM_10G_LR, 235 .baudrate = IF_Gbps(10ULL), 236 }, 237 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_SR] = { 238 .subtype = IFM_10G_SR, 239 .baudrate = IF_Gbps(10ULL), 240 }, 241 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_T] = { 242 .subtype = IFM_10G_T, 243 .baudrate = IF_Gbps(10ULL), 244 }, 245 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_AOC] = { 246 .subtype = IFM_10G_AOC, 247 .baudrate = IF_Gbps(10ULL), 248 }, 249 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CR1] = { 250 .subtype = IFM_10G_CR1, 251 .baudrate = IF_Gbps(10ULL), 252 }, 253 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CR4] = { 254 .subtype = IFM_40G_CR4, 255 .baudrate = IF_Gbps(40ULL), 256 }, 257 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_KR4] = { 258 .subtype = IFM_40G_KR4, 259 .baudrate = IF_Gbps(40ULL), 260 }, 261 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_LR4] = { 262 .subtype = IFM_40G_LR4, 263 .baudrate = IF_Gbps(40ULL), 264 }, 265 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_SR4] = { 266 .subtype = IFM_40G_SR4, 267 .baudrate = IF_Gbps(40ULL), 268 }, 269 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_ER4] = { 270 .subtype = IFM_40G_ER4, 271 .baudrate = IF_Gbps(40ULL), 272 }, 273 274 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR] = { 275 .subtype = IFM_25G_CR, 276 .baudrate = IF_Gbps(25ULL), 277 }, 278 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR] = { 279 .subtype = IFM_25G_KR, 280 .baudrate = IF_Gbps(25ULL), 281 }, 282 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_SR] = { 283 .subtype = IFM_25G_SR, 284 .baudrate = IF_Gbps(25ULL), 285 }, 286 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_ACC] = { 287 .subtype = IFM_25G_ACC, 288 .baudrate = IF_Gbps(25ULL), 289 }, 290 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_AOC] = { 291 .subtype = IFM_25G_AOC, 292 .baudrate = IF_Gbps(25ULL), 293 }, 294 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR1] = { 295 .subtype = IFM_25G_CR1, 296 .baudrate = IF_Gbps(25ULL), 297 }, 298 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR_S] = { 299 .subtype = IFM_25G_CR_S, 300 .baudrate = IF_Gbps(25ULL), 301 }, 302 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR1] = { 303 .subtype = IFM_5000_KR1, 304 .baudrate = IF_Gbps(25ULL), 305 }, 306 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR_S] = { 307 .subtype = IFM_25G_KR_S, 308 .baudrate = IF_Gbps(25ULL), 309 }, 310 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_LR] = { 311 .subtype = IFM_25G_LR, 312 .baudrate = IF_Gbps(25ULL), 313 }, 314 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_T] = { 315 .subtype = IFM_25G_T, 316 .baudrate = IF_Gbps(25ULL), 317 }, 318 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CR2] = { 319 .subtype = IFM_50G_CR2, 320 .baudrate = IF_Gbps(50ULL), 321 }, 322 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_KR2] = { 323 .subtype = IFM_50G_KR2, 324 .baudrate = IF_Gbps(50ULL), 325 }, 326 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_KR4] = { 327 .subtype = IFM_50G_KR4, 328 .baudrate = IF_Gbps(50ULL), 329 }, 330 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_SR2] = { 331 .subtype = IFM_50G_SR2, 332 .baudrate = IF_Gbps(50ULL), 333 }, 334 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_LR2] = { 335 .subtype = IFM_50G_LR2, 336 .baudrate = IF_Gbps(50ULL), 337 }, 338 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_LR] = { 339 .subtype = IFM_50G_LR, 340 .baudrate = IF_Gbps(50ULL), 341 }, 342 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_SR] = { 343 .subtype = IFM_50G_SR, 344 .baudrate = IF_Gbps(50ULL), 345 }, 346 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CP] = { 347 .subtype = IFM_50G_CP, 348 .baudrate = IF_Gbps(50ULL), 349 }, 350 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_FR] = { 351 .subtype = IFM_50G_FR, 352 .baudrate = IF_Gbps(50ULL), 353 }, 354 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_KR_PAM4] = { 355 .subtype = IFM_50G_KR_PAM4, 356 .baudrate = IF_Gbps(50ULL), 357 }, 358 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CR4] = { 359 .subtype = IFM_100G_CR4, 360 .baudrate = IF_Gbps(100ULL), 361 }, 362 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_KR4] = { 363 .subtype = IFM_100G_KR4, 364 .baudrate = IF_Gbps(100ULL), 365 }, 366 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_LR4] = { 367 .subtype = IFM_100G_LR4, 368 .baudrate = IF_Gbps(100ULL), 369 }, 370 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_SR4] = { 371 .subtype = IFM_100G_SR4, 372 .baudrate = IF_Gbps(100ULL), 373 }, 374 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_SR2] = { 375 .subtype = IFM_100G_SR2, 376 .baudrate = IF_Gbps(100ULL), 377 }, 378 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CP2] = { 379 .subtype = IFM_100G_CP2, 380 .baudrate = IF_Gbps(100ULL), 381 }, 382 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_KR2_PAM4] = { 383 .subtype = IFM_100G_KR2_PAM4, 384 .baudrate = IF_Gbps(100ULL), 385 }, 386 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_DR4] = { 387 .subtype = IFM_200G_DR4, 388 .baudrate = IF_Gbps(200ULL), 389 }, 390 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_LR4] = { 391 .subtype = IFM_200G_LR4, 392 .baudrate = IF_Gbps(200ULL), 393 }, 394 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_SR4] = { 395 .subtype = IFM_200G_SR4, 396 .baudrate = IF_Gbps(200ULL), 397 }, 398 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_FR4] = { 399 .subtype = IFM_200G_FR4, 400 .baudrate = IF_Gbps(200ULL), 401 }, 402 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CR4_PAM4] = { 403 .subtype = IFM_200G_CR4_PAM4, 404 .baudrate = IF_Gbps(200ULL), 405 }, 406 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_KR4_PAM4] = { 407 .subtype = IFM_200G_KR4_PAM4, 408 .baudrate = IF_Gbps(200ULL), 409 }, 410 }; 411 412 DEBUGNET_DEFINE(mlx5_en); 413 414 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet"); 415 416 static void 417 mlx5e_update_carrier(struct mlx5e_priv *priv) 418 { 419 struct mlx5_core_dev *mdev = priv->mdev; 420 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 421 u32 eth_proto_oper; 422 int error; 423 u8 port_state; 424 u8 is_er_type; 425 u8 i, j; 426 bool ext; 427 struct media media_entry = {}; 428 429 port_state = mlx5_query_vport_state(mdev, 430 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0); 431 432 if (port_state == VPORT_STATE_UP) { 433 priv->media_status_last |= IFM_ACTIVE; 434 } else { 435 priv->media_status_last &= ~IFM_ACTIVE; 436 priv->media_active_last = IFM_ETHER; 437 if_link_state_change(priv->ifp, LINK_STATE_DOWN); 438 return; 439 } 440 441 error = mlx5_query_port_ptys(mdev, out, sizeof(out), 442 MLX5_PTYS_EN, 1); 443 if (error) { 444 priv->media_active_last = IFM_ETHER; 445 priv->ifp->if_baudrate = 1; 446 mlx5_en_err(priv->ifp, "query port ptys failed: 0x%x\n", 447 error); 448 return; 449 } 450 451 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet); 452 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 453 eth_proto_oper); 454 455 i = ilog2(eth_proto_oper); 456 457 for (j = 0; j != MLX5E_LINK_MODES_NUMBER; j++) { 458 media_entry = ext ? mlx5e_ext_mode_table[i][j] : 459 mlx5e_mode_table[i][j]; 460 if (media_entry.baudrate != 0) 461 break; 462 } 463 464 if (media_entry.subtype == 0) { 465 mlx5_en_err(priv->ifp, 466 "Could not find operational media subtype\n"); 467 return; 468 } 469 470 switch (media_entry.subtype) { 471 case IFM_10G_ER: 472 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type); 473 if (error != 0) { 474 mlx5_en_err(priv->ifp, 475 "query port pddr failed: %d\n", error); 476 } 477 if (error != 0 || is_er_type == 0) 478 media_entry.subtype = IFM_10G_LR; 479 break; 480 case IFM_40G_LR4: 481 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type); 482 if (error != 0) { 483 mlx5_en_err(priv->ifp, 484 "query port pddr failed: %d\n", error); 485 } 486 if (error == 0 && is_er_type != 0) 487 media_entry.subtype = IFM_40G_ER4; 488 break; 489 } 490 priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX; 491 priv->ifp->if_baudrate = media_entry.baudrate; 492 493 if_link_state_change(priv->ifp, LINK_STATE_UP); 494 } 495 496 static void 497 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr) 498 { 499 struct mlx5e_priv *priv = dev->if_softc; 500 501 ifmr->ifm_status = priv->media_status_last; 502 ifmr->ifm_current = ifmr->ifm_active = priv->media_active_last | 503 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) | 504 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0); 505 506 } 507 508 static u32 509 mlx5e_find_link_mode(u32 subtype, bool ext) 510 { 511 u32 i; 512 u32 j; 513 u32 link_mode = 0; 514 u32 speeds_num = 0; 515 struct media media_entry = {}; 516 517 switch (subtype) { 518 case IFM_10G_LR: 519 subtype = IFM_10G_ER; 520 break; 521 case IFM_40G_ER4: 522 subtype = IFM_40G_LR4; 523 break; 524 } 525 526 speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER : 527 MLX5E_LINK_SPEEDS_NUMBER; 528 529 for (i = 0; i != speeds_num; i++) { 530 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) { 531 media_entry = ext ? mlx5e_ext_mode_table[i][j] : 532 mlx5e_mode_table[i][j]; 533 if (media_entry.baudrate == 0) 534 continue; 535 if (media_entry.subtype == subtype) { 536 link_mode |= MLX5E_PROT_MASK(i); 537 } 538 } 539 } 540 541 return (link_mode); 542 } 543 544 static int 545 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv) 546 { 547 return (mlx5_set_port_pause_and_pfc(priv->mdev, 1, 548 priv->params.rx_pauseframe_control, 549 priv->params.tx_pauseframe_control, 550 priv->params.rx_priority_flow_control, 551 priv->params.tx_priority_flow_control)); 552 } 553 554 static int 555 mlx5e_set_port_pfc(struct mlx5e_priv *priv) 556 { 557 int error; 558 559 if (priv->gone != 0) { 560 error = -ENXIO; 561 } else if (priv->params.rx_pauseframe_control || 562 priv->params.tx_pauseframe_control) { 563 mlx5_en_err(priv->ifp, 564 "Global pauseframes must be disabled before enabling PFC.\n"); 565 error = -EINVAL; 566 } else { 567 error = mlx5e_set_port_pause_and_pfc(priv); 568 } 569 return (error); 570 } 571 572 static int 573 mlx5e_media_change(struct ifnet *dev) 574 { 575 struct mlx5e_priv *priv = dev->if_softc; 576 struct mlx5_core_dev *mdev = priv->mdev; 577 u32 eth_proto_cap; 578 u32 link_mode; 579 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 580 int was_opened; 581 int locked; 582 int error; 583 bool ext; 584 585 locked = PRIV_LOCKED(priv); 586 if (!locked) 587 PRIV_LOCK(priv); 588 589 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) { 590 error = EINVAL; 591 goto done; 592 } 593 594 error = mlx5_query_port_ptys(mdev, out, sizeof(out), 595 MLX5_PTYS_EN, 1); 596 if (error != 0) { 597 mlx5_en_err(dev, "Query port media capability failed\n"); 598 goto done; 599 } 600 601 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet); 602 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext); 603 604 /* query supported capabilities */ 605 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 606 eth_proto_capability); 607 608 /* check for autoselect */ 609 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) { 610 link_mode = eth_proto_cap; 611 if (link_mode == 0) { 612 mlx5_en_err(dev, "Port media capability is zero\n"); 613 error = EINVAL; 614 goto done; 615 } 616 } else { 617 link_mode = link_mode & eth_proto_cap; 618 if (link_mode == 0) { 619 mlx5_en_err(dev, "Not supported link mode requested\n"); 620 error = EINVAL; 621 goto done; 622 } 623 } 624 if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) { 625 /* check if PFC is enabled */ 626 if (priv->params.rx_priority_flow_control || 627 priv->params.tx_priority_flow_control) { 628 mlx5_en_err(dev, "PFC must be disabled before enabling global pauseframes.\n"); 629 error = EINVAL; 630 goto done; 631 } 632 } 633 /* update pauseframe control bits */ 634 priv->params.rx_pauseframe_control = 635 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0; 636 priv->params.tx_pauseframe_control = 637 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0; 638 639 /* check if device is opened */ 640 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 641 642 /* reconfigure the hardware */ 643 mlx5_set_port_status(mdev, MLX5_PORT_DOWN); 644 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext); 645 error = -mlx5e_set_port_pause_and_pfc(priv); 646 if (was_opened) 647 mlx5_set_port_status(mdev, MLX5_PORT_UP); 648 649 done: 650 if (!locked) 651 PRIV_UNLOCK(priv); 652 return (error); 653 } 654 655 static void 656 mlx5e_update_carrier_work(struct work_struct *work) 657 { 658 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 659 update_carrier_work); 660 661 PRIV_LOCK(priv); 662 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) 663 mlx5e_update_carrier(priv); 664 PRIV_UNLOCK(priv); 665 } 666 667 #define MLX5E_PCIE_PERF_GET_64(a,b,c,d,e,f) \ 668 s_debug->c = MLX5_GET64(mpcnt_reg, out, counter_set.f.c); 669 670 #define MLX5E_PCIE_PERF_GET_32(a,b,c,d,e,f) \ 671 s_debug->c = MLX5_GET(mpcnt_reg, out, counter_set.f.c); 672 673 static void 674 mlx5e_update_pcie_counters(struct mlx5e_priv *priv) 675 { 676 struct mlx5_core_dev *mdev = priv->mdev; 677 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug; 678 const unsigned sz = MLX5_ST_SZ_BYTES(mpcnt_reg); 679 void *out; 680 void *in; 681 int err; 682 683 /* allocate firmware request structures */ 684 in = mlx5_vzalloc(sz); 685 out = mlx5_vzalloc(sz); 686 if (in == NULL || out == NULL) 687 goto free_out; 688 689 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP); 690 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 691 if (err != 0) 692 goto free_out; 693 694 MLX5E_PCIE_PERFORMANCE_COUNTERS_64(MLX5E_PCIE_PERF_GET_64) 695 MLX5E_PCIE_PERFORMANCE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 696 697 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP); 698 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 699 if (err != 0) 700 goto free_out; 701 702 MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 703 704 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_LANE_COUNTERS_GROUP); 705 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); 706 if (err != 0) 707 goto free_out; 708 709 MLX5E_PCIE_LANE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32) 710 711 free_out: 712 /* free firmware request structures */ 713 kvfree(in); 714 kvfree(out); 715 } 716 717 /* 718 * This function reads the physical port counters from the firmware 719 * using a pre-defined layout defined by various MLX5E_PPORT_XXX() 720 * macros. The output is converted from big-endian 64-bit values into 721 * host endian ones and stored in the "priv->stats.pport" structure. 722 */ 723 static void 724 mlx5e_update_pport_counters(struct mlx5e_priv *priv) 725 { 726 struct mlx5_core_dev *mdev = priv->mdev; 727 struct mlx5e_pport_stats *s = &priv->stats.pport; 728 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug; 729 u32 *in; 730 u32 *out; 731 const u64 *ptr; 732 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg); 733 unsigned x; 734 unsigned y; 735 unsigned z; 736 737 /* allocate firmware request structures */ 738 in = mlx5_vzalloc(sz); 739 out = mlx5_vzalloc(sz); 740 if (in == NULL || out == NULL) 741 goto free_out; 742 743 /* 744 * Get pointer to the 64-bit counter set which is located at a 745 * fixed offset in the output firmware request structure: 746 */ 747 ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set); 748 749 MLX5_SET(ppcnt_reg, in, local_port, 1); 750 751 /* read IEEE802_3 counter group using predefined counter layout */ 752 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP); 753 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 754 for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM; 755 x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++) 756 s->arg[y] = be64toh(ptr[x]); 757 758 /* read RFC2819 counter group using predefined counter layout */ 759 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP); 760 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 761 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++) 762 s->arg[y] = be64toh(ptr[x]); 763 764 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM + 765 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++) 766 s_debug->arg[y] = be64toh(ptr[x]); 767 768 /* read RFC2863 counter group using predefined counter layout */ 769 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP); 770 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 771 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++) 772 s_debug->arg[y] = be64toh(ptr[x]); 773 774 /* read physical layer stats counter group using predefined counter layout */ 775 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP); 776 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 777 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++) 778 s_debug->arg[y] = be64toh(ptr[x]); 779 780 /* read Extended Ethernet counter group using predefined counter layout */ 781 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP); 782 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 783 for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++) 784 s_debug->arg[y] = be64toh(ptr[x]); 785 786 /* read Extended Statistical Group */ 787 if (MLX5_CAP_GEN(mdev, pcam_reg) && 788 MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) && 789 MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) { 790 /* read Extended Statistical counter group using predefined counter layout */ 791 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP); 792 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 793 794 for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++) 795 s_debug->arg[y] = be64toh(ptr[x]); 796 } 797 798 /* read PCIE counters */ 799 mlx5e_update_pcie_counters(priv); 800 801 /* read per-priority counters */ 802 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP); 803 804 /* iterate all the priorities */ 805 for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) { 806 MLX5_SET(ppcnt_reg, in, prio_tc, z); 807 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); 808 809 /* read per priority stats counter group using predefined counter layout */ 810 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM / 811 MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++) 812 s->arg[y] = be64toh(ptr[x]); 813 } 814 815 free_out: 816 /* free firmware request structures */ 817 kvfree(in); 818 kvfree(out); 819 } 820 821 static void 822 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv) 823 { 824 u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {}; 825 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {}; 826 827 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard)) 828 return; 829 830 MLX5_SET(query_vnic_env_in, in, opcode, 831 MLX5_CMD_OP_QUERY_VNIC_ENV); 832 MLX5_SET(query_vnic_env_in, in, op_mod, 0); 833 MLX5_SET(query_vnic_env_in, in, other_vport, 0); 834 835 if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0) 836 return; 837 838 priv->stats.vport.rx_steer_missed_packets = 839 MLX5_GET64(query_vnic_env_out, out, 840 vport_env.nic_receive_steering_discard); 841 } 842 843 /* 844 * This function is called regularly to collect all statistics 845 * counters from the firmware. The values can be viewed through the 846 * sysctl interface. Execution is serialized using the priv's global 847 * configuration lock. 848 */ 849 static void 850 mlx5e_update_stats_locked(struct mlx5e_priv *priv) 851 { 852 struct mlx5_core_dev *mdev = priv->mdev; 853 struct mlx5e_vport_stats *s = &priv->stats.vport; 854 struct mlx5e_sq_stats *sq_stats; 855 #if (__FreeBSD_version < 1100000) 856 struct ifnet *ifp = priv->ifp; 857 #endif 858 859 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)]; 860 u32 *out; 861 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out); 862 u64 tso_packets = 0; 863 u64 tso_bytes = 0; 864 u64 tx_queue_dropped = 0; 865 u64 tx_defragged = 0; 866 u64 tx_offload_none = 0; 867 u64 lro_packets = 0; 868 u64 lro_bytes = 0; 869 u64 sw_lro_queued = 0; 870 u64 sw_lro_flushed = 0; 871 u64 rx_csum_none = 0; 872 u64 rx_wqe_err = 0; 873 u64 rx_packets = 0; 874 u64 rx_bytes = 0; 875 u32 rx_out_of_buffer = 0; 876 int error; 877 int i; 878 int j; 879 880 out = mlx5_vzalloc(outlen); 881 if (out == NULL) 882 goto free_out; 883 884 /* Collect firts the SW counters and then HW for consistency */ 885 for (i = 0; i < priv->params.num_channels; i++) { 886 struct mlx5e_channel *pch = priv->channel + i; 887 struct mlx5e_rq *rq = &pch->rq; 888 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats; 889 890 /* collect stats from LRO */ 891 rq_stats->sw_lro_queued = rq->lro.lro_queued; 892 rq_stats->sw_lro_flushed = rq->lro.lro_flushed; 893 sw_lro_queued += rq_stats->sw_lro_queued; 894 sw_lro_flushed += rq_stats->sw_lro_flushed; 895 lro_packets += rq_stats->lro_packets; 896 lro_bytes += rq_stats->lro_bytes; 897 rx_csum_none += rq_stats->csum_none; 898 rx_wqe_err += rq_stats->wqe_err; 899 rx_packets += rq_stats->packets; 900 rx_bytes += rq_stats->bytes; 901 902 for (j = 0; j < priv->num_tc; j++) { 903 sq_stats = &pch->sq[j].stats; 904 905 tso_packets += sq_stats->tso_packets; 906 tso_bytes += sq_stats->tso_bytes; 907 tx_queue_dropped += sq_stats->dropped; 908 tx_queue_dropped += sq_stats->enobuf; 909 tx_defragged += sq_stats->defragged; 910 tx_offload_none += sq_stats->csum_offload_none; 911 } 912 } 913 914 #ifdef RATELIMIT 915 /* Collect statistics from all rate-limit queues */ 916 for (j = 0; j < priv->rl.param.tx_worker_threads_def; j++) { 917 struct mlx5e_rl_worker *rlw = priv->rl.workers + j; 918 919 for (i = 0; i < priv->rl.param.tx_channels_per_worker_def; i++) { 920 struct mlx5e_rl_channel *channel = rlw->channels + i; 921 struct mlx5e_sq *sq = channel->sq; 922 923 if (sq == NULL) 924 continue; 925 926 sq_stats = &sq->stats; 927 928 tso_packets += sq_stats->tso_packets; 929 tso_bytes += sq_stats->tso_bytes; 930 tx_queue_dropped += sq_stats->dropped; 931 tx_queue_dropped += sq_stats->enobuf; 932 tx_defragged += sq_stats->defragged; 933 tx_offload_none += sq_stats->csum_offload_none; 934 } 935 } 936 #endif 937 938 /* update counters */ 939 s->tso_packets = tso_packets; 940 s->tso_bytes = tso_bytes; 941 s->tx_queue_dropped = tx_queue_dropped; 942 s->tx_defragged = tx_defragged; 943 s->lro_packets = lro_packets; 944 s->lro_bytes = lro_bytes; 945 s->sw_lro_queued = sw_lro_queued; 946 s->sw_lro_flushed = sw_lro_flushed; 947 s->rx_csum_none = rx_csum_none; 948 s->rx_wqe_err = rx_wqe_err; 949 s->rx_packets = rx_packets; 950 s->rx_bytes = rx_bytes; 951 952 mlx5e_grp_vnic_env_update_stats(priv); 953 954 /* HW counters */ 955 memset(in, 0, sizeof(in)); 956 957 MLX5_SET(query_vport_counter_in, in, opcode, 958 MLX5_CMD_OP_QUERY_VPORT_COUNTER); 959 MLX5_SET(query_vport_counter_in, in, op_mod, 0); 960 MLX5_SET(query_vport_counter_in, in, other_vport, 0); 961 962 memset(out, 0, outlen); 963 964 /* get number of out-of-buffer drops first */ 965 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 && 966 mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id, 967 &rx_out_of_buffer) == 0) { 968 s->rx_out_of_buffer = rx_out_of_buffer; 969 } 970 971 /* get port statistics */ 972 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) { 973 #define MLX5_GET_CTR(out, x) \ 974 MLX5_GET64(query_vport_counter_out, out, x) 975 976 s->rx_error_packets = 977 MLX5_GET_CTR(out, received_errors.packets); 978 s->rx_error_bytes = 979 MLX5_GET_CTR(out, received_errors.octets); 980 s->tx_error_packets = 981 MLX5_GET_CTR(out, transmit_errors.packets); 982 s->tx_error_bytes = 983 MLX5_GET_CTR(out, transmit_errors.octets); 984 985 s->rx_unicast_packets = 986 MLX5_GET_CTR(out, received_eth_unicast.packets); 987 s->rx_unicast_bytes = 988 MLX5_GET_CTR(out, received_eth_unicast.octets); 989 s->tx_unicast_packets = 990 MLX5_GET_CTR(out, transmitted_eth_unicast.packets); 991 s->tx_unicast_bytes = 992 MLX5_GET_CTR(out, transmitted_eth_unicast.octets); 993 994 s->rx_multicast_packets = 995 MLX5_GET_CTR(out, received_eth_multicast.packets); 996 s->rx_multicast_bytes = 997 MLX5_GET_CTR(out, received_eth_multicast.octets); 998 s->tx_multicast_packets = 999 MLX5_GET_CTR(out, transmitted_eth_multicast.packets); 1000 s->tx_multicast_bytes = 1001 MLX5_GET_CTR(out, transmitted_eth_multicast.octets); 1002 1003 s->rx_broadcast_packets = 1004 MLX5_GET_CTR(out, received_eth_broadcast.packets); 1005 s->rx_broadcast_bytes = 1006 MLX5_GET_CTR(out, received_eth_broadcast.octets); 1007 s->tx_broadcast_packets = 1008 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets); 1009 s->tx_broadcast_bytes = 1010 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets); 1011 1012 s->tx_packets = s->tx_unicast_packets + 1013 s->tx_multicast_packets + s->tx_broadcast_packets; 1014 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes + 1015 s->tx_broadcast_bytes; 1016 1017 /* Update calculated offload counters */ 1018 s->tx_csum_offload = s->tx_packets - tx_offload_none; 1019 s->rx_csum_good = s->rx_packets - s->rx_csum_none; 1020 } 1021 1022 /* Get physical port counters */ 1023 mlx5e_update_pport_counters(priv); 1024 1025 s->tx_jumbo_packets = 1026 priv->stats.port_stats_debug.tx_stat_p1519to2047octets + 1027 priv->stats.port_stats_debug.tx_stat_p2048to4095octets + 1028 priv->stats.port_stats_debug.tx_stat_p4096to8191octets + 1029 priv->stats.port_stats_debug.tx_stat_p8192to10239octets; 1030 1031 #if (__FreeBSD_version < 1100000) 1032 /* no get_counters interface in fbsd 10 */ 1033 ifp->if_ipackets = s->rx_packets; 1034 ifp->if_ierrors = priv->stats.pport.in_range_len_errors + 1035 priv->stats.pport.out_of_range_len + 1036 priv->stats.pport.too_long_errors + 1037 priv->stats.pport.check_seq_err + 1038 priv->stats.pport.alignment_err; 1039 ifp->if_iqdrops = s->rx_out_of_buffer; 1040 ifp->if_opackets = s->tx_packets; 1041 ifp->if_oerrors = priv->stats.port_stats_debug.out_discards; 1042 ifp->if_snd.ifq_drops = s->tx_queue_dropped; 1043 ifp->if_ibytes = s->rx_bytes; 1044 ifp->if_obytes = s->tx_bytes; 1045 ifp->if_collisions = 1046 priv->stats.pport.collisions; 1047 #endif 1048 1049 free_out: 1050 kvfree(out); 1051 1052 /* Update diagnostics, if any */ 1053 if (priv->params_ethtool.diag_pci_enable || 1054 priv->params_ethtool.diag_general_enable) { 1055 error = mlx5_core_get_diagnostics_full(mdev, 1056 priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL, 1057 priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL); 1058 if (error != 0) 1059 mlx5_en_err(priv->ifp, 1060 "Failed reading diagnostics: %d\n", error); 1061 } 1062 1063 /* Update FEC, if any */ 1064 error = mlx5e_fec_update(priv); 1065 if (error != 0 && error != EOPNOTSUPP) { 1066 mlx5_en_err(priv->ifp, 1067 "Updating FEC failed: %d\n", error); 1068 } 1069 1070 /* Update temperature, if any */ 1071 if (priv->params_ethtool.hw_num_temp != 0) { 1072 error = mlx5e_hw_temperature_update(priv); 1073 if (error != 0 && error != EOPNOTSUPP) { 1074 mlx5_en_err(priv->ifp, 1075 "Updating temperature failed: %d\n", error); 1076 } 1077 } 1078 } 1079 1080 static void 1081 mlx5e_update_stats_work(struct work_struct *work) 1082 { 1083 struct mlx5e_priv *priv; 1084 1085 priv = container_of(work, struct mlx5e_priv, update_stats_work); 1086 PRIV_LOCK(priv); 1087 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 && 1088 !test_bit(MLX5_INTERFACE_STATE_TEARDOWN, &priv->mdev->intf_state)) 1089 mlx5e_update_stats_locked(priv); 1090 PRIV_UNLOCK(priv); 1091 } 1092 1093 static void 1094 mlx5e_update_stats(void *arg) 1095 { 1096 struct mlx5e_priv *priv = arg; 1097 1098 queue_work(priv->wq, &priv->update_stats_work); 1099 1100 callout_reset(&priv->watchdog, hz / 4, &mlx5e_update_stats, priv); 1101 } 1102 1103 static void 1104 mlx5e_async_event_sub(struct mlx5e_priv *priv, 1105 enum mlx5_dev_event event) 1106 { 1107 switch (event) { 1108 case MLX5_DEV_EVENT_PORT_UP: 1109 case MLX5_DEV_EVENT_PORT_DOWN: 1110 queue_work(priv->wq, &priv->update_carrier_work); 1111 break; 1112 1113 default: 1114 break; 1115 } 1116 } 1117 1118 static void 1119 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv, 1120 enum mlx5_dev_event event, unsigned long param) 1121 { 1122 struct mlx5e_priv *priv = vpriv; 1123 1124 mtx_lock(&priv->async_events_mtx); 1125 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state)) 1126 mlx5e_async_event_sub(priv, event); 1127 mtx_unlock(&priv->async_events_mtx); 1128 } 1129 1130 static void 1131 mlx5e_enable_async_events(struct mlx5e_priv *priv) 1132 { 1133 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 1134 } 1135 1136 static void 1137 mlx5e_disable_async_events(struct mlx5e_priv *priv) 1138 { 1139 mtx_lock(&priv->async_events_mtx); 1140 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); 1141 mtx_unlock(&priv->async_events_mtx); 1142 } 1143 1144 static void mlx5e_calibration_callout(void *arg); 1145 static int mlx5e_calibration_duration = 20; 1146 static int mlx5e_fast_calibration = 1; 1147 static int mlx5e_normal_calibration = 30; 1148 1149 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 1150 "MLX5 timestamp calibration parameteres"); 1151 1152 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN, 1153 &mlx5e_calibration_duration, 0, 1154 "Duration of initial calibration"); 1155 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN, 1156 &mlx5e_fast_calibration, 0, 1157 "Recalibration interval during initial calibration"); 1158 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN, 1159 &mlx5e_normal_calibration, 0, 1160 "Recalibration interval during normal operations"); 1161 1162 /* 1163 * Ignites the calibration process. 1164 */ 1165 static void 1166 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv) 1167 { 1168 1169 if (priv->clbr_done == 0) 1170 mlx5e_calibration_callout(priv); 1171 else 1172 callout_reset_curcpu(&priv->tstmp_clbr, (priv->clbr_done < 1173 mlx5e_calibration_duration ? mlx5e_fast_calibration : 1174 mlx5e_normal_calibration) * hz, mlx5e_calibration_callout, 1175 priv); 1176 } 1177 1178 static uint64_t 1179 mlx5e_timespec2usec(const struct timespec *ts) 1180 { 1181 1182 return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec); 1183 } 1184 1185 static uint64_t 1186 mlx5e_hw_clock(struct mlx5e_priv *priv) 1187 { 1188 struct mlx5_init_seg *iseg; 1189 uint32_t hw_h, hw_h1, hw_l; 1190 1191 iseg = priv->mdev->iseg; 1192 do { 1193 hw_h = ioread32be(&iseg->internal_timer_h); 1194 hw_l = ioread32be(&iseg->internal_timer_l); 1195 hw_h1 = ioread32be(&iseg->internal_timer_h); 1196 } while (hw_h1 != hw_h); 1197 return (((uint64_t)hw_h << 32) | hw_l); 1198 } 1199 1200 /* 1201 * The calibration callout, it runs either in the context of the 1202 * thread which enables calibration, or in callout. It takes the 1203 * snapshot of system and adapter clocks, then advances the pointers to 1204 * the calibration point to allow rx path to read the consistent data 1205 * lockless. 1206 */ 1207 static void 1208 mlx5e_calibration_callout(void *arg) 1209 { 1210 struct mlx5e_priv *priv; 1211 struct mlx5e_clbr_point *next, *curr; 1212 struct timespec ts; 1213 int clbr_curr_next; 1214 1215 priv = arg; 1216 curr = &priv->clbr_points[priv->clbr_curr]; 1217 clbr_curr_next = priv->clbr_curr + 1; 1218 if (clbr_curr_next >= nitems(priv->clbr_points)) 1219 clbr_curr_next = 0; 1220 next = &priv->clbr_points[clbr_curr_next]; 1221 1222 next->base_prev = curr->base_curr; 1223 next->clbr_hw_prev = curr->clbr_hw_curr; 1224 1225 next->clbr_hw_curr = mlx5e_hw_clock(priv); 1226 if (((next->clbr_hw_curr - curr->clbr_hw_curr) >> MLX5E_TSTMP_PREC) == 1227 0) { 1228 if (priv->clbr_done != 0) { 1229 mlx5_en_err(priv->ifp, 1230 "HW failed tstmp frozen %#jx %#jx, disabling\n", 1231 next->clbr_hw_curr, curr->clbr_hw_prev); 1232 priv->clbr_done = 0; 1233 } 1234 atomic_store_rel_int(&curr->clbr_gen, 0); 1235 return; 1236 } 1237 1238 nanouptime(&ts); 1239 next->base_curr = mlx5e_timespec2usec(&ts); 1240 1241 curr->clbr_gen = 0; 1242 atomic_thread_fence_rel(); 1243 priv->clbr_curr = clbr_curr_next; 1244 atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen)); 1245 1246 if (priv->clbr_done < mlx5e_calibration_duration) 1247 priv->clbr_done++; 1248 mlx5e_reset_calibration_callout(priv); 1249 } 1250 1251 static const char *mlx5e_rq_stats_desc[] = { 1252 MLX5E_RQ_STATS(MLX5E_STATS_DESC) 1253 }; 1254 1255 static int 1256 mlx5e_create_rq(struct mlx5e_channel *c, 1257 struct mlx5e_rq_param *param, 1258 struct mlx5e_rq *rq) 1259 { 1260 struct mlx5e_priv *priv = c->priv; 1261 struct mlx5_core_dev *mdev = priv->mdev; 1262 char buffer[16]; 1263 void *rqc = param->rqc; 1264 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); 1265 int wq_sz; 1266 int err; 1267 int i; 1268 u32 nsegs, wqe_sz; 1269 1270 err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs); 1271 if (err != 0) 1272 goto done; 1273 1274 /* Create DMA descriptor TAG */ 1275 if ((err = -bus_dma_tag_create( 1276 bus_get_dma_tag(mdev->pdev->dev.bsddev), 1277 1, /* any alignment */ 1278 0, /* no boundary */ 1279 BUS_SPACE_MAXADDR, /* lowaddr */ 1280 BUS_SPACE_MAXADDR, /* highaddr */ 1281 NULL, NULL, /* filter, filterarg */ 1282 nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */ 1283 nsegs, /* nsegments */ 1284 nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */ 1285 0, /* flags */ 1286 NULL, NULL, /* lockfunc, lockfuncarg */ 1287 &rq->dma_tag))) 1288 goto done; 1289 1290 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, 1291 &rq->wq_ctrl); 1292 if (err) 1293 goto err_free_dma_tag; 1294 1295 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR]; 1296 1297 err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs); 1298 if (err != 0) 1299 goto err_rq_wq_destroy; 1300 1301 wq_sz = mlx5_wq_ll_get_size(&rq->wq); 1302 1303 err = -tcp_lro_init_args(&rq->lro, priv->ifp, TCP_LRO_ENTRIES, wq_sz); 1304 if (err) 1305 goto err_rq_wq_destroy; 1306 1307 rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO); 1308 for (i = 0; i != wq_sz; i++) { 1309 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i); 1310 int j; 1311 1312 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map); 1313 if (err != 0) { 1314 while (i--) 1315 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 1316 goto err_rq_mbuf_free; 1317 } 1318 1319 /* set value for constant fields */ 1320 for (j = 0; j < rq->nsegs; j++) 1321 wqe->data[j].lkey = cpu_to_be32(priv->mr.key); 1322 } 1323 1324 INIT_WORK(&rq->dim.work, mlx5e_dim_work); 1325 if (priv->params.rx_cq_moderation_mode < 2) { 1326 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 1327 } else { 1328 void *cqc = container_of(param, 1329 struct mlx5e_channel_param, rq)->rx_cq.cqc; 1330 1331 switch (MLX5_GET(cqc, cqc, cq_period_mode)) { 1332 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE: 1333 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; 1334 break; 1335 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE: 1336 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE; 1337 break; 1338 default: 1339 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 1340 break; 1341 } 1342 } 1343 1344 rq->ifp = priv->ifp; 1345 rq->channel = c; 1346 rq->ix = c->ix; 1347 1348 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix); 1349 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 1350 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM, 1351 rq->stats.arg); 1352 return (0); 1353 1354 err_rq_mbuf_free: 1355 free(rq->mbuf, M_MLX5EN); 1356 tcp_lro_free(&rq->lro); 1357 err_rq_wq_destroy: 1358 mlx5_wq_destroy(&rq->wq_ctrl); 1359 err_free_dma_tag: 1360 bus_dma_tag_destroy(rq->dma_tag); 1361 done: 1362 return (err); 1363 } 1364 1365 static void 1366 mlx5e_destroy_rq(struct mlx5e_rq *rq) 1367 { 1368 int wq_sz; 1369 int i; 1370 1371 /* destroy all sysctl nodes */ 1372 sysctl_ctx_free(&rq->stats.ctx); 1373 1374 /* free leftover LRO packets, if any */ 1375 tcp_lro_free(&rq->lro); 1376 1377 wq_sz = mlx5_wq_ll_get_size(&rq->wq); 1378 for (i = 0; i != wq_sz; i++) { 1379 if (rq->mbuf[i].mbuf != NULL) { 1380 bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map); 1381 m_freem(rq->mbuf[i].mbuf); 1382 } 1383 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map); 1384 } 1385 free(rq->mbuf, M_MLX5EN); 1386 mlx5_wq_destroy(&rq->wq_ctrl); 1387 bus_dma_tag_destroy(rq->dma_tag); 1388 } 1389 1390 static int 1391 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param) 1392 { 1393 struct mlx5e_channel *c = rq->channel; 1394 struct mlx5e_priv *priv = c->priv; 1395 struct mlx5_core_dev *mdev = priv->mdev; 1396 1397 void *in; 1398 void *rqc; 1399 void *wq; 1400 int inlen; 1401 int err; 1402 1403 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 1404 sizeof(u64) * rq->wq_ctrl.buf.npages; 1405 in = mlx5_vzalloc(inlen); 1406 if (in == NULL) 1407 return (-ENOMEM); 1408 1409 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1410 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1411 1412 memcpy(rqc, param->rqc, sizeof(param->rqc)); 1413 1414 MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn); 1415 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1416 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1417 if (priv->counter_set_id >= 0) 1418 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id); 1419 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - 1420 PAGE_SHIFT); 1421 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); 1422 1423 mlx5_fill_page_array(&rq->wq_ctrl.buf, 1424 (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 1425 1426 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); 1427 1428 kvfree(in); 1429 1430 return (err); 1431 } 1432 1433 static int 1434 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state) 1435 { 1436 struct mlx5e_channel *c = rq->channel; 1437 struct mlx5e_priv *priv = c->priv; 1438 struct mlx5_core_dev *mdev = priv->mdev; 1439 1440 void *in; 1441 void *rqc; 1442 int inlen; 1443 int err; 1444 1445 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 1446 in = mlx5_vzalloc(inlen); 1447 if (in == NULL) 1448 return (-ENOMEM); 1449 1450 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1451 1452 MLX5_SET(modify_rq_in, in, rqn, rq->rqn); 1453 MLX5_SET(modify_rq_in, in, rq_state, curr_state); 1454 MLX5_SET(rqc, rqc, state, next_state); 1455 1456 err = mlx5_core_modify_rq(mdev, in, inlen); 1457 1458 kvfree(in); 1459 1460 return (err); 1461 } 1462 1463 static void 1464 mlx5e_disable_rq(struct mlx5e_rq *rq) 1465 { 1466 struct mlx5e_channel *c = rq->channel; 1467 struct mlx5e_priv *priv = c->priv; 1468 struct mlx5_core_dev *mdev = priv->mdev; 1469 1470 mlx5_core_destroy_rq(mdev, rq->rqn); 1471 } 1472 1473 static int 1474 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq) 1475 { 1476 struct mlx5e_channel *c = rq->channel; 1477 struct mlx5e_priv *priv = c->priv; 1478 struct mlx5_wq_ll *wq = &rq->wq; 1479 int i; 1480 1481 for (i = 0; i < 1000; i++) { 1482 if (wq->cur_sz >= priv->params.min_rx_wqes) 1483 return (0); 1484 1485 msleep(4); 1486 } 1487 return (-ETIMEDOUT); 1488 } 1489 1490 static int 1491 mlx5e_open_rq(struct mlx5e_channel *c, 1492 struct mlx5e_rq_param *param, 1493 struct mlx5e_rq *rq) 1494 { 1495 int err; 1496 1497 err = mlx5e_create_rq(c, param, rq); 1498 if (err) 1499 return (err); 1500 1501 err = mlx5e_enable_rq(rq, param); 1502 if (err) 1503 goto err_destroy_rq; 1504 1505 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 1506 if (err) 1507 goto err_disable_rq; 1508 1509 c->rq.enabled = 1; 1510 1511 return (0); 1512 1513 err_disable_rq: 1514 mlx5e_disable_rq(rq); 1515 err_destroy_rq: 1516 mlx5e_destroy_rq(rq); 1517 1518 return (err); 1519 } 1520 1521 static void 1522 mlx5e_close_rq(struct mlx5e_rq *rq) 1523 { 1524 mtx_lock(&rq->mtx); 1525 rq->enabled = 0; 1526 callout_stop(&rq->watchdog); 1527 mtx_unlock(&rq->mtx); 1528 1529 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 1530 } 1531 1532 static void 1533 mlx5e_close_rq_wait(struct mlx5e_rq *rq) 1534 { 1535 1536 mlx5e_disable_rq(rq); 1537 mlx5e_close_cq(&rq->cq); 1538 cancel_work_sync(&rq->dim.work); 1539 mlx5e_destroy_rq(rq); 1540 } 1541 1542 void 1543 mlx5e_free_sq_db(struct mlx5e_sq *sq) 1544 { 1545 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1546 int x; 1547 1548 for (x = 0; x != wq_sz; x++) { 1549 if (unlikely(sq->mbuf[x].p_refcount != NULL)) { 1550 atomic_add_int(sq->mbuf[x].p_refcount, -1); 1551 sq->mbuf[x].p_refcount = NULL; 1552 } 1553 if (sq->mbuf[x].mbuf != NULL) { 1554 bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map); 1555 m_freem(sq->mbuf[x].mbuf); 1556 } 1557 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 1558 } 1559 free(sq->mbuf, M_MLX5EN); 1560 } 1561 1562 int 1563 mlx5e_alloc_sq_db(struct mlx5e_sq *sq) 1564 { 1565 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1566 int err; 1567 int x; 1568 1569 sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO); 1570 1571 /* Create DMA descriptor MAPs */ 1572 for (x = 0; x != wq_sz; x++) { 1573 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map); 1574 if (err != 0) { 1575 while (x--) 1576 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map); 1577 free(sq->mbuf, M_MLX5EN); 1578 return (err); 1579 } 1580 } 1581 return (0); 1582 } 1583 1584 static const char *mlx5e_sq_stats_desc[] = { 1585 MLX5E_SQ_STATS(MLX5E_STATS_DESC) 1586 }; 1587 1588 void 1589 mlx5e_update_sq_inline(struct mlx5e_sq *sq) 1590 { 1591 sq->max_inline = sq->priv->params.tx_max_inline; 1592 sq->min_inline_mode = sq->priv->params.tx_min_inline_mode; 1593 1594 /* 1595 * Check if trust state is DSCP or if inline mode is NONE which 1596 * indicates CX-5 or newer hardware. 1597 */ 1598 if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP || 1599 sq->min_inline_mode == MLX5_INLINE_MODE_NONE) { 1600 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert)) 1601 sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN; 1602 else 1603 sq->min_insert_caps = MLX5E_INSERT_NON_VLAN; 1604 } else { 1605 sq->min_insert_caps = 0; 1606 } 1607 } 1608 1609 static void 1610 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c) 1611 { 1612 int i; 1613 1614 for (i = 0; i != priv->num_tc; i++) { 1615 mtx_lock(&c->sq[i].lock); 1616 mlx5e_update_sq_inline(&c->sq[i]); 1617 mtx_unlock(&c->sq[i].lock); 1618 } 1619 } 1620 1621 void 1622 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv) 1623 { 1624 int i; 1625 1626 /* check if channels are closed */ 1627 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 1628 return; 1629 1630 for (i = 0; i < priv->params.num_channels; i++) 1631 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]); 1632 } 1633 1634 static int 1635 mlx5e_create_sq(struct mlx5e_channel *c, 1636 int tc, 1637 struct mlx5e_sq_param *param, 1638 struct mlx5e_sq *sq) 1639 { 1640 struct mlx5e_priv *priv = c->priv; 1641 struct mlx5_core_dev *mdev = priv->mdev; 1642 char buffer[16]; 1643 void *sqc = param->sqc; 1644 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq); 1645 int err; 1646 1647 /* Create DMA descriptor TAG */ 1648 if ((err = -bus_dma_tag_create( 1649 bus_get_dma_tag(mdev->pdev->dev.bsddev), 1650 1, /* any alignment */ 1651 0, /* no boundary */ 1652 BUS_SPACE_MAXADDR, /* lowaddr */ 1653 BUS_SPACE_MAXADDR, /* highaddr */ 1654 NULL, NULL, /* filter, filterarg */ 1655 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */ 1656 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */ 1657 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */ 1658 0, /* flags */ 1659 NULL, NULL, /* lockfunc, lockfuncarg */ 1660 &sq->dma_tag))) 1661 goto done; 1662 1663 sq->uar_map = priv->bfreg.map; 1664 1665 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, 1666 &sq->wq_ctrl); 1667 if (err) 1668 goto err_free_dma_tag; 1669 1670 sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; 1671 1672 err = mlx5e_alloc_sq_db(sq); 1673 if (err) 1674 goto err_sq_wq_destroy; 1675 1676 sq->mkey_be = cpu_to_be32(priv->mr.key); 1677 sq->ifp = priv->ifp; 1678 sq->priv = priv; 1679 sq->tc = tc; 1680 1681 mlx5e_update_sq_inline(sq); 1682 1683 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc); 1684 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 1685 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM, 1686 sq->stats.arg); 1687 1688 return (0); 1689 1690 err_sq_wq_destroy: 1691 mlx5_wq_destroy(&sq->wq_ctrl); 1692 1693 err_free_dma_tag: 1694 bus_dma_tag_destroy(sq->dma_tag); 1695 done: 1696 return (err); 1697 } 1698 1699 static void 1700 mlx5e_destroy_sq(struct mlx5e_sq *sq) 1701 { 1702 /* destroy all sysctl nodes */ 1703 sysctl_ctx_free(&sq->stats.ctx); 1704 1705 mlx5e_free_sq_db(sq); 1706 mlx5_wq_destroy(&sq->wq_ctrl); 1707 bus_dma_tag_destroy(sq->dma_tag); 1708 } 1709 1710 int 1711 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param, 1712 int tis_num) 1713 { 1714 void *in; 1715 void *sqc; 1716 void *wq; 1717 int inlen; 1718 int err; 1719 1720 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1721 sizeof(u64) * sq->wq_ctrl.buf.npages; 1722 in = mlx5_vzalloc(inlen); 1723 if (in == NULL) 1724 return (-ENOMEM); 1725 1726 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1727 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1728 1729 memcpy(sqc, param->sqc, sizeof(param->sqc)); 1730 1731 MLX5_SET(sqc, sqc, tis_num_0, tis_num); 1732 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn); 1733 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1734 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1735 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1736 1737 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1738 MLX5_SET(wq, wq, uar_page, sq->priv->bfreg.index); 1739 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift - 1740 PAGE_SHIFT); 1741 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma); 1742 1743 mlx5_fill_page_array(&sq->wq_ctrl.buf, 1744 (__be64 *) MLX5_ADDR_OF(wq, wq, pas)); 1745 1746 err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn); 1747 1748 kvfree(in); 1749 1750 return (err); 1751 } 1752 1753 int 1754 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state) 1755 { 1756 void *in; 1757 void *sqc; 1758 int inlen; 1759 int err; 1760 1761 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 1762 in = mlx5_vzalloc(inlen); 1763 if (in == NULL) 1764 return (-ENOMEM); 1765 1766 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1767 1768 MLX5_SET(modify_sq_in, in, sqn, sq->sqn); 1769 MLX5_SET(modify_sq_in, in, sq_state, curr_state); 1770 MLX5_SET(sqc, sqc, state, next_state); 1771 1772 err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen); 1773 1774 kvfree(in); 1775 1776 return (err); 1777 } 1778 1779 void 1780 mlx5e_disable_sq(struct mlx5e_sq *sq) 1781 { 1782 1783 mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn); 1784 } 1785 1786 static int 1787 mlx5e_open_sq(struct mlx5e_channel *c, 1788 int tc, 1789 struct mlx5e_sq_param *param, 1790 struct mlx5e_sq *sq) 1791 { 1792 int err; 1793 1794 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact; 1795 1796 /* ensure the TX completion event factor is not zero */ 1797 if (sq->cev_factor == 0) 1798 sq->cev_factor = 1; 1799 1800 err = mlx5e_create_sq(c, tc, param, sq); 1801 if (err) 1802 return (err); 1803 1804 err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]); 1805 if (err) 1806 goto err_destroy_sq; 1807 1808 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY); 1809 if (err) 1810 goto err_disable_sq; 1811 1812 WRITE_ONCE(sq->running, 1); 1813 1814 return (0); 1815 1816 err_disable_sq: 1817 mlx5e_disable_sq(sq); 1818 err_destroy_sq: 1819 mlx5e_destroy_sq(sq); 1820 1821 return (err); 1822 } 1823 1824 static void 1825 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep) 1826 { 1827 /* fill up remainder with NOPs */ 1828 while (sq->cev_counter != 0) { 1829 while (!mlx5e_sq_has_room_for(sq, 1)) { 1830 if (can_sleep != 0) { 1831 mtx_unlock(&sq->lock); 1832 msleep(4); 1833 mtx_lock(&sq->lock); 1834 } else { 1835 goto done; 1836 } 1837 } 1838 /* send a single NOP */ 1839 mlx5e_send_nop(sq, 1); 1840 atomic_thread_fence_rel(); 1841 } 1842 done: 1843 /* Check if we need to write the doorbell */ 1844 if (likely(sq->doorbell.d64 != 0)) { 1845 mlx5e_tx_notify_hw(sq, sq->doorbell.d32); 1846 sq->doorbell.d64 = 0; 1847 } 1848 } 1849 1850 void 1851 mlx5e_sq_cev_timeout(void *arg) 1852 { 1853 struct mlx5e_sq *sq = arg; 1854 1855 mtx_assert(&sq->lock, MA_OWNED); 1856 1857 /* check next state */ 1858 switch (sq->cev_next_state) { 1859 case MLX5E_CEV_STATE_SEND_NOPS: 1860 /* fill TX ring with NOPs, if any */ 1861 mlx5e_sq_send_nops_locked(sq, 0); 1862 1863 /* check if completed */ 1864 if (sq->cev_counter == 0) { 1865 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL; 1866 return; 1867 } 1868 break; 1869 default: 1870 /* send NOPs on next timeout */ 1871 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS; 1872 break; 1873 } 1874 1875 /* restart timer */ 1876 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq); 1877 } 1878 1879 void 1880 mlx5e_drain_sq(struct mlx5e_sq *sq) 1881 { 1882 int error; 1883 struct mlx5_core_dev *mdev= sq->priv->mdev; 1884 1885 /* 1886 * Check if already stopped. 1887 * 1888 * NOTE: Serialization of this function is managed by the 1889 * caller ensuring the priv's state lock is locked or in case 1890 * of rate limit support, a single thread manages drain and 1891 * resume of SQs. The "running" variable can therefore safely 1892 * be read without any locks. 1893 */ 1894 if (READ_ONCE(sq->running) == 0) 1895 return; 1896 1897 /* don't put more packets into the SQ */ 1898 WRITE_ONCE(sq->running, 0); 1899 1900 /* serialize access to DMA rings */ 1901 mtx_lock(&sq->lock); 1902 1903 /* teardown event factor timer, if any */ 1904 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS; 1905 callout_stop(&sq->cev_callout); 1906 1907 /* send dummy NOPs in order to flush the transmit ring */ 1908 mlx5e_sq_send_nops_locked(sq, 1); 1909 mtx_unlock(&sq->lock); 1910 1911 /* wait till SQ is empty or link is down */ 1912 mtx_lock(&sq->lock); 1913 while (sq->cc != sq->pc && 1914 (sq->priv->media_status_last & IFM_ACTIVE) != 0 && 1915 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1916 mtx_unlock(&sq->lock); 1917 msleep(1); 1918 sq->cq.mcq.comp(&sq->cq.mcq, NULL); 1919 mtx_lock(&sq->lock); 1920 } 1921 mtx_unlock(&sq->lock); 1922 1923 /* error out remaining requests */ 1924 error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR); 1925 if (error != 0) { 1926 mlx5_en_err(sq->ifp, 1927 "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error); 1928 } 1929 1930 /* wait till SQ is empty */ 1931 mtx_lock(&sq->lock); 1932 while (sq->cc != sq->pc && 1933 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1934 mtx_unlock(&sq->lock); 1935 msleep(1); 1936 sq->cq.mcq.comp(&sq->cq.mcq, NULL); 1937 mtx_lock(&sq->lock); 1938 } 1939 mtx_unlock(&sq->lock); 1940 } 1941 1942 static void 1943 mlx5e_close_sq_wait(struct mlx5e_sq *sq) 1944 { 1945 1946 mlx5e_drain_sq(sq); 1947 mlx5e_disable_sq(sq); 1948 mlx5e_destroy_sq(sq); 1949 } 1950 1951 static int 1952 mlx5e_create_cq(struct mlx5e_priv *priv, 1953 struct mlx5e_cq_param *param, 1954 struct mlx5e_cq *cq, 1955 mlx5e_cq_comp_t *comp, 1956 int eq_ix) 1957 { 1958 struct mlx5_core_dev *mdev = priv->mdev; 1959 struct mlx5_core_cq *mcq = &cq->mcq; 1960 int eqn_not_used; 1961 int irqn; 1962 int err; 1963 u32 i; 1964 1965 param->wq.buf_numa_node = 0; 1966 param->wq.db_numa_node = 0; 1967 1968 err = mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn); 1969 if (err) 1970 return (err); 1971 1972 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, 1973 &cq->wq_ctrl); 1974 if (err) 1975 return (err); 1976 1977 mcq->cqe_sz = 64; 1978 mcq->set_ci_db = cq->wq_ctrl.db.db; 1979 mcq->arm_db = cq->wq_ctrl.db.db + 1; 1980 *mcq->set_ci_db = 0; 1981 *mcq->arm_db = 0; 1982 mcq->vector = eq_ix; 1983 mcq->comp = comp; 1984 mcq->event = mlx5e_cq_error_event; 1985 mcq->irqn = irqn; 1986 1987 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { 1988 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); 1989 1990 cqe->op_own = 0xf1; 1991 } 1992 1993 cq->priv = priv; 1994 1995 return (0); 1996 } 1997 1998 static void 1999 mlx5e_destroy_cq(struct mlx5e_cq *cq) 2000 { 2001 mlx5_wq_destroy(&cq->wq_ctrl); 2002 } 2003 2004 static int 2005 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix) 2006 { 2007 struct mlx5_core_cq *mcq = &cq->mcq; 2008 u32 out[MLX5_ST_SZ_DW(create_cq_out)]; 2009 void *in; 2010 void *cqc; 2011 int inlen; 2012 int irqn_not_used; 2013 int eqn; 2014 int err; 2015 2016 inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 2017 sizeof(u64) * cq->wq_ctrl.buf.npages; 2018 in = mlx5_vzalloc(inlen); 2019 if (in == NULL) 2020 return (-ENOMEM); 2021 2022 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); 2023 2024 memcpy(cqc, param->cqc, sizeof(param->cqc)); 2025 2026 mlx5_fill_page_array(&cq->wq_ctrl.buf, 2027 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas)); 2028 2029 mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used); 2030 2031 MLX5_SET(cqc, cqc, c_eqn, eqn); 2032 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - 2033 PAGE_SHIFT); 2034 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); 2035 2036 err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen, out, sizeof(out)); 2037 2038 kvfree(in); 2039 2040 if (err) 2041 return (err); 2042 2043 mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock)); 2044 2045 return (0); 2046 } 2047 2048 static void 2049 mlx5e_disable_cq(struct mlx5e_cq *cq) 2050 { 2051 2052 mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq); 2053 } 2054 2055 int 2056 mlx5e_open_cq(struct mlx5e_priv *priv, 2057 struct mlx5e_cq_param *param, 2058 struct mlx5e_cq *cq, 2059 mlx5e_cq_comp_t *comp, 2060 int eq_ix) 2061 { 2062 int err; 2063 2064 err = mlx5e_create_cq(priv, param, cq, comp, eq_ix); 2065 if (err) 2066 return (err); 2067 2068 err = mlx5e_enable_cq(cq, param, eq_ix); 2069 if (err) 2070 goto err_destroy_cq; 2071 2072 return (0); 2073 2074 err_destroy_cq: 2075 mlx5e_destroy_cq(cq); 2076 2077 return (err); 2078 } 2079 2080 void 2081 mlx5e_close_cq(struct mlx5e_cq *cq) 2082 { 2083 mlx5e_disable_cq(cq); 2084 mlx5e_destroy_cq(cq); 2085 } 2086 2087 static int 2088 mlx5e_open_tx_cqs(struct mlx5e_channel *c, 2089 struct mlx5e_channel_param *cparam) 2090 { 2091 int err; 2092 int tc; 2093 2094 for (tc = 0; tc < c->priv->num_tc; tc++) { 2095 /* open completion queue */ 2096 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq, 2097 &mlx5e_tx_cq_comp, c->ix); 2098 if (err) 2099 goto err_close_tx_cqs; 2100 } 2101 return (0); 2102 2103 err_close_tx_cqs: 2104 for (tc--; tc >= 0; tc--) 2105 mlx5e_close_cq(&c->sq[tc].cq); 2106 2107 return (err); 2108 } 2109 2110 static void 2111 mlx5e_close_tx_cqs(struct mlx5e_channel *c) 2112 { 2113 int tc; 2114 2115 for (tc = 0; tc < c->priv->num_tc; tc++) 2116 mlx5e_close_cq(&c->sq[tc].cq); 2117 } 2118 2119 static int 2120 mlx5e_open_sqs(struct mlx5e_channel *c, 2121 struct mlx5e_channel_param *cparam) 2122 { 2123 int err; 2124 int tc; 2125 2126 for (tc = 0; tc < c->priv->num_tc; tc++) { 2127 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]); 2128 if (err) 2129 goto err_close_sqs; 2130 } 2131 2132 return (0); 2133 2134 err_close_sqs: 2135 for (tc--; tc >= 0; tc--) 2136 mlx5e_close_sq_wait(&c->sq[tc]); 2137 2138 return (err); 2139 } 2140 2141 static void 2142 mlx5e_close_sqs_wait(struct mlx5e_channel *c) 2143 { 2144 int tc; 2145 2146 for (tc = 0; tc < c->priv->num_tc; tc++) 2147 mlx5e_close_sq_wait(&c->sq[tc]); 2148 } 2149 2150 static void 2151 mlx5e_chan_static_init(struct mlx5e_priv *priv, struct mlx5e_channel *c, int ix) 2152 { 2153 int tc; 2154 2155 /* setup priv and channel number */ 2156 c->priv = priv; 2157 c->ix = ix; 2158 2159 /* setup send tag */ 2160 m_snd_tag_init(&c->tag, c->priv->ifp, IF_SND_TAG_TYPE_UNLIMITED); 2161 2162 init_completion(&c->completion); 2163 2164 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF); 2165 2166 callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0); 2167 2168 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) { 2169 struct mlx5e_sq *sq = c->sq + tc; 2170 2171 mtx_init(&sq->lock, "mlx5tx", 2172 MTX_NETWORK_LOCK " TX", MTX_DEF); 2173 mtx_init(&sq->comp_lock, "mlx5comp", 2174 MTX_NETWORK_LOCK " TX", MTX_DEF); 2175 2176 callout_init_mtx(&sq->cev_callout, &sq->lock, 0); 2177 } 2178 } 2179 2180 static void 2181 mlx5e_chan_wait_for_completion(struct mlx5e_channel *c) 2182 { 2183 2184 m_snd_tag_rele(&c->tag); 2185 wait_for_completion(&c->completion); 2186 } 2187 2188 static void 2189 mlx5e_priv_wait_for_completion(struct mlx5e_priv *priv, const uint32_t channels) 2190 { 2191 uint32_t x; 2192 2193 for (x = 0; x != channels; x++) 2194 mlx5e_chan_wait_for_completion(&priv->channel[x]); 2195 } 2196 2197 static void 2198 mlx5e_chan_static_destroy(struct mlx5e_channel *c) 2199 { 2200 int tc; 2201 2202 callout_drain(&c->rq.watchdog); 2203 2204 mtx_destroy(&c->rq.mtx); 2205 2206 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) { 2207 callout_drain(&c->sq[tc].cev_callout); 2208 mtx_destroy(&c->sq[tc].lock); 2209 mtx_destroy(&c->sq[tc].comp_lock); 2210 } 2211 } 2212 2213 static int 2214 mlx5e_open_channel(struct mlx5e_priv *priv, 2215 struct mlx5e_channel_param *cparam, 2216 struct mlx5e_channel *c) 2217 { 2218 struct epoch_tracker et; 2219 int i, err; 2220 2221 /* zero non-persistant data */ 2222 MLX5E_ZERO(&c->rq, mlx5e_rq_zero_start); 2223 for (i = 0; i != priv->num_tc; i++) 2224 MLX5E_ZERO(&c->sq[i], mlx5e_sq_zero_start); 2225 2226 /* open transmit completion queue */ 2227 err = mlx5e_open_tx_cqs(c, cparam); 2228 if (err) 2229 goto err_free; 2230 2231 /* open receive completion queue */ 2232 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq, 2233 &mlx5e_rx_cq_comp, c->ix); 2234 if (err) 2235 goto err_close_tx_cqs; 2236 2237 err = mlx5e_open_sqs(c, cparam); 2238 if (err) 2239 goto err_close_rx_cq; 2240 2241 err = mlx5e_open_rq(c, &cparam->rq, &c->rq); 2242 if (err) 2243 goto err_close_sqs; 2244 2245 /* poll receive queue initially */ 2246 NET_EPOCH_ENTER(et); 2247 c->rq.cq.mcq.comp(&c->rq.cq.mcq, NULL); 2248 NET_EPOCH_EXIT(et); 2249 2250 return (0); 2251 2252 err_close_sqs: 2253 mlx5e_close_sqs_wait(c); 2254 2255 err_close_rx_cq: 2256 mlx5e_close_cq(&c->rq.cq); 2257 2258 err_close_tx_cqs: 2259 mlx5e_close_tx_cqs(c); 2260 2261 err_free: 2262 return (err); 2263 } 2264 2265 static void 2266 mlx5e_close_channel(struct mlx5e_channel *c) 2267 { 2268 mlx5e_close_rq(&c->rq); 2269 } 2270 2271 static void 2272 mlx5e_close_channel_wait(struct mlx5e_channel *c) 2273 { 2274 mlx5e_close_rq_wait(&c->rq); 2275 mlx5e_close_sqs_wait(c); 2276 mlx5e_close_tx_cqs(c); 2277 } 2278 2279 static int 2280 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs) 2281 { 2282 u32 r, n; 2283 2284 r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz : 2285 MLX5E_SW2MB_MTU(priv->ifp->if_mtu); 2286 if (r > MJUM16BYTES) 2287 return (-ENOMEM); 2288 2289 if (r > MJUM9BYTES) 2290 r = MJUM16BYTES; 2291 else if (r > MJUMPAGESIZE) 2292 r = MJUM9BYTES; 2293 else if (r > MCLBYTES) 2294 r = MJUMPAGESIZE; 2295 else 2296 r = MCLBYTES; 2297 2298 /* 2299 * n + 1 must be a power of two, because stride size must be. 2300 * Stride size is 16 * (n + 1), as the first segment is 2301 * control. 2302 */ 2303 for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++) 2304 ; 2305 2306 if (n > MLX5E_MAX_BUSDMA_RX_SEGS) 2307 return (-ENOMEM); 2308 2309 *wqe_sz = r; 2310 *nsegs = n; 2311 return (0); 2312 } 2313 2314 static void 2315 mlx5e_build_rq_param(struct mlx5e_priv *priv, 2316 struct mlx5e_rq_param *param) 2317 { 2318 void *rqc = param->rqc; 2319 void *wq = MLX5_ADDR_OF(rqc, rqc, wq); 2320 u32 wqe_sz, nsegs; 2321 2322 mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs); 2323 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); 2324 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 2325 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) + 2326 nsegs * sizeof(struct mlx5_wqe_data_seg))); 2327 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size); 2328 MLX5_SET(wq, wq, pd, priv->pdn); 2329 2330 param->wq.buf_numa_node = 0; 2331 param->wq.db_numa_node = 0; 2332 param->wq.linear = 1; 2333 } 2334 2335 static void 2336 mlx5e_build_sq_param(struct mlx5e_priv *priv, 2337 struct mlx5e_sq_param *param) 2338 { 2339 void *sqc = param->sqc; 2340 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 2341 2342 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size); 2343 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 2344 MLX5_SET(wq, wq, pd, priv->pdn); 2345 2346 param->wq.buf_numa_node = 0; 2347 param->wq.db_numa_node = 0; 2348 param->wq.linear = 1; 2349 } 2350 2351 static void 2352 mlx5e_build_common_cq_param(struct mlx5e_priv *priv, 2353 struct mlx5e_cq_param *param) 2354 { 2355 void *cqc = param->cqc; 2356 2357 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index); 2358 } 2359 2360 static void 2361 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr) 2362 { 2363 2364 *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE); 2365 2366 /* apply LRO restrictions */ 2367 if (priv->params.hw_lro_en && 2368 ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) { 2369 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO; 2370 } 2371 } 2372 2373 static void 2374 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, 2375 struct mlx5e_cq_param *param) 2376 { 2377 struct net_dim_cq_moder curr; 2378 void *cqc = param->cqc; 2379 2380 /* 2381 * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE 2382 * format is more beneficial for FreeBSD use case. 2383 * 2384 * Adding support for MLX5_CQE_FORMAT_CSUM will require changes 2385 * in mlx5e_decompress_cqe. 2386 */ 2387 if (priv->params.cqe_zipping_en) { 2388 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH); 2389 MLX5_SET(cqc, cqc, cqe_compression_en, 1); 2390 } 2391 2392 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size); 2393 2394 switch (priv->params.rx_cq_moderation_mode) { 2395 case 0: 2396 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec); 2397 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts); 2398 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2399 break; 2400 case 1: 2401 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec); 2402 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts); 2403 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2404 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2405 else 2406 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2407 break; 2408 case 2: 2409 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr); 2410 MLX5_SET(cqc, cqc, cq_period, curr.usec); 2411 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts); 2412 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2413 break; 2414 case 3: 2415 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr); 2416 MLX5_SET(cqc, cqc, cq_period, curr.usec); 2417 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts); 2418 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2419 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2420 else 2421 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2422 break; 2423 default: 2424 break; 2425 } 2426 2427 mlx5e_dim_build_cq_param(priv, param); 2428 2429 mlx5e_build_common_cq_param(priv, param); 2430 } 2431 2432 static void 2433 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv, 2434 struct mlx5e_cq_param *param) 2435 { 2436 void *cqc = param->cqc; 2437 2438 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size); 2439 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec); 2440 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts); 2441 2442 switch (priv->params.tx_cq_moderation_mode) { 2443 case 0: 2444 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2445 break; 2446 default: 2447 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2448 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 2449 else 2450 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 2451 break; 2452 } 2453 2454 mlx5e_build_common_cq_param(priv, param); 2455 } 2456 2457 static void 2458 mlx5e_build_channel_param(struct mlx5e_priv *priv, 2459 struct mlx5e_channel_param *cparam) 2460 { 2461 memset(cparam, 0, sizeof(*cparam)); 2462 2463 mlx5e_build_rq_param(priv, &cparam->rq); 2464 mlx5e_build_sq_param(priv, &cparam->sq); 2465 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq); 2466 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq); 2467 } 2468 2469 static int 2470 mlx5e_open_channels(struct mlx5e_priv *priv) 2471 { 2472 struct mlx5e_channel_param *cparam; 2473 int err; 2474 int i; 2475 int j; 2476 2477 cparam = malloc(sizeof(*cparam), M_MLX5EN, M_WAITOK); 2478 2479 mlx5e_build_channel_param(priv, cparam); 2480 for (i = 0; i < priv->params.num_channels; i++) { 2481 err = mlx5e_open_channel(priv, cparam, &priv->channel[i]); 2482 if (err) 2483 goto err_close_channels; 2484 } 2485 2486 for (j = 0; j < priv->params.num_channels; j++) { 2487 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq); 2488 if (err) 2489 goto err_close_channels; 2490 } 2491 free(cparam, M_MLX5EN); 2492 return (0); 2493 2494 err_close_channels: 2495 while (i--) { 2496 mlx5e_close_channel(&priv->channel[i]); 2497 mlx5e_close_channel_wait(&priv->channel[i]); 2498 } 2499 free(cparam, M_MLX5EN); 2500 return (err); 2501 } 2502 2503 static void 2504 mlx5e_close_channels(struct mlx5e_priv *priv) 2505 { 2506 int i; 2507 2508 for (i = 0; i < priv->params.num_channels; i++) 2509 mlx5e_close_channel(&priv->channel[i]); 2510 for (i = 0; i < priv->params.num_channels; i++) 2511 mlx5e_close_channel_wait(&priv->channel[i]); 2512 } 2513 2514 static int 2515 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq) 2516 { 2517 2518 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) { 2519 uint8_t cq_mode; 2520 2521 switch (priv->params.tx_cq_moderation_mode) { 2522 case 0: 2523 case 2: 2524 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 2525 break; 2526 default: 2527 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE; 2528 break; 2529 } 2530 2531 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq, 2532 priv->params.tx_cq_moderation_usec, 2533 priv->params.tx_cq_moderation_pkts, 2534 cq_mode)); 2535 } 2536 2537 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq, 2538 priv->params.tx_cq_moderation_usec, 2539 priv->params.tx_cq_moderation_pkts)); 2540 } 2541 2542 static int 2543 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq) 2544 { 2545 2546 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) { 2547 uint8_t cq_mode; 2548 uint8_t dim_mode; 2549 int retval; 2550 2551 switch (priv->params.rx_cq_moderation_mode) { 2552 case 0: 2553 case 2: 2554 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 2555 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE; 2556 break; 2557 default: 2558 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE; 2559 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE; 2560 break; 2561 } 2562 2563 /* tear down dynamic interrupt moderation */ 2564 mtx_lock(&rq->mtx); 2565 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED; 2566 mtx_unlock(&rq->mtx); 2567 2568 /* wait for dynamic interrupt moderation work task, if any */ 2569 cancel_work_sync(&rq->dim.work); 2570 2571 if (priv->params.rx_cq_moderation_mode >= 2) { 2572 struct net_dim_cq_moder curr; 2573 2574 mlx5e_get_default_profile(priv, dim_mode, &curr); 2575 2576 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq, 2577 curr.usec, curr.pkts, cq_mode); 2578 2579 /* set dynamic interrupt moderation mode and zero defaults */ 2580 mtx_lock(&rq->mtx); 2581 rq->dim.mode = dim_mode; 2582 rq->dim.state = 0; 2583 rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE; 2584 mtx_unlock(&rq->mtx); 2585 } else { 2586 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq, 2587 priv->params.rx_cq_moderation_usec, 2588 priv->params.rx_cq_moderation_pkts, 2589 cq_mode); 2590 } 2591 return (retval); 2592 } 2593 2594 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq, 2595 priv->params.rx_cq_moderation_usec, 2596 priv->params.rx_cq_moderation_pkts)); 2597 } 2598 2599 static int 2600 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c) 2601 { 2602 int err; 2603 int i; 2604 2605 err = mlx5e_refresh_rq_params(priv, &c->rq); 2606 if (err) 2607 goto done; 2608 2609 for (i = 0; i != priv->num_tc; i++) { 2610 err = mlx5e_refresh_sq_params(priv, &c->sq[i]); 2611 if (err) 2612 goto done; 2613 } 2614 done: 2615 return (err); 2616 } 2617 2618 int 2619 mlx5e_refresh_channel_params(struct mlx5e_priv *priv) 2620 { 2621 int i; 2622 2623 /* check if channels are closed */ 2624 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 2625 return (EINVAL); 2626 2627 for (i = 0; i < priv->params.num_channels; i++) { 2628 int err; 2629 2630 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]); 2631 if (err) 2632 return (err); 2633 } 2634 return (0); 2635 } 2636 2637 static int 2638 mlx5e_open_tis(struct mlx5e_priv *priv, int tc) 2639 { 2640 struct mlx5_core_dev *mdev = priv->mdev; 2641 u32 in[MLX5_ST_SZ_DW(create_tis_in)]; 2642 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 2643 2644 memset(in, 0, sizeof(in)); 2645 2646 MLX5_SET(tisc, tisc, prio, tc); 2647 MLX5_SET(tisc, tisc, transport_domain, priv->tdn); 2648 2649 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc])); 2650 } 2651 2652 static void 2653 mlx5e_close_tis(struct mlx5e_priv *priv, int tc) 2654 { 2655 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]); 2656 } 2657 2658 static int 2659 mlx5e_open_tises(struct mlx5e_priv *priv) 2660 { 2661 int num_tc = priv->num_tc; 2662 int err; 2663 int tc; 2664 2665 for (tc = 0; tc < num_tc; tc++) { 2666 err = mlx5e_open_tis(priv, tc); 2667 if (err) 2668 goto err_close_tises; 2669 } 2670 2671 return (0); 2672 2673 err_close_tises: 2674 for (tc--; tc >= 0; tc--) 2675 mlx5e_close_tis(priv, tc); 2676 2677 return (err); 2678 } 2679 2680 static void 2681 mlx5e_close_tises(struct mlx5e_priv *priv) 2682 { 2683 int num_tc = priv->num_tc; 2684 int tc; 2685 2686 for (tc = 0; tc < num_tc; tc++) 2687 mlx5e_close_tis(priv, tc); 2688 } 2689 2690 static int 2691 mlx5e_open_rqt(struct mlx5e_priv *priv) 2692 { 2693 struct mlx5_core_dev *mdev = priv->mdev; 2694 u32 *in; 2695 u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 2696 void *rqtc; 2697 int inlen; 2698 int err; 2699 int sz; 2700 int i; 2701 2702 sz = 1 << priv->params.rx_hash_log_tbl_sz; 2703 2704 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 2705 in = mlx5_vzalloc(inlen); 2706 if (in == NULL) 2707 return (-ENOMEM); 2708 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 2709 2710 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 2711 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 2712 2713 for (i = 0; i < sz; i++) { 2714 int ix = i; 2715 #ifdef RSS 2716 ix = rss_get_indirection_to_bucket(ix); 2717 #endif 2718 /* ensure we don't overflow */ 2719 ix %= priv->params.num_channels; 2720 2721 /* apply receive side scaling stride, if any */ 2722 ix -= ix % (int)priv->params.channels_rsss; 2723 2724 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn); 2725 } 2726 2727 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 2728 2729 err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out)); 2730 if (!err) 2731 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn); 2732 2733 kvfree(in); 2734 2735 return (err); 2736 } 2737 2738 static void 2739 mlx5e_close_rqt(struct mlx5e_priv *priv) 2740 { 2741 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0}; 2742 u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0}; 2743 2744 MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT); 2745 MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn); 2746 2747 mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)); 2748 } 2749 2750 #define MLX5E_RSS_KEY_SIZE (10 * 4) /* bytes */ 2751 2752 static void 2753 mlx5e_get_rss_key(void *key_ptr) 2754 { 2755 #ifdef RSS 2756 rss_getkey(key_ptr); 2757 #else 2758 static const u32 rsskey[] = { 2759 cpu_to_be32(0xD181C62C), 2760 cpu_to_be32(0xF7F4DB5B), 2761 cpu_to_be32(0x1983A2FC), 2762 cpu_to_be32(0x943E1ADB), 2763 cpu_to_be32(0xD9389E6B), 2764 cpu_to_be32(0xD1039C2C), 2765 cpu_to_be32(0xA74499AD), 2766 cpu_to_be32(0x593D56D9), 2767 cpu_to_be32(0xF3253C06), 2768 cpu_to_be32(0x2ADC1FFC), 2769 }; 2770 CTASSERT(sizeof(rsskey) == MLX5E_RSS_KEY_SIZE); 2771 memcpy(key_ptr, rsskey, MLX5E_RSS_KEY_SIZE); 2772 #endif 2773 } 2774 2775 static void 2776 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt) 2777 { 2778 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 2779 __be32 *hkey; 2780 2781 MLX5_SET(tirc, tirc, transport_domain, priv->tdn); 2782 2783 #define ROUGH_MAX_L2_L3_HDR_SZ 256 2784 2785 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2786 MLX5_HASH_FIELD_SEL_DST_IP) 2787 2788 #define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2789 MLX5_HASH_FIELD_SEL_DST_IP |\ 2790 MLX5_HASH_FIELD_SEL_L4_SPORT |\ 2791 MLX5_HASH_FIELD_SEL_L4_DPORT) 2792 2793 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\ 2794 MLX5_HASH_FIELD_SEL_DST_IP |\ 2795 MLX5_HASH_FIELD_SEL_IPSEC_SPI) 2796 2797 if (priv->params.hw_lro_en) { 2798 MLX5_SET(tirc, tirc, lro_enable_mask, 2799 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | 2800 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO); 2801 MLX5_SET(tirc, tirc, lro_max_msg_sz, 2802 (priv->params.lro_wqe_sz - 2803 ROUGH_MAX_L2_L3_HDR_SZ) >> 8); 2804 /* TODO: add the option to choose timer value dynamically */ 2805 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, 2806 MLX5_CAP_ETH(priv->mdev, 2807 lro_timer_supported_periods[2])); 2808 } 2809 2810 /* setup parameters for hashing TIR type, if any */ 2811 switch (tt) { 2812 case MLX5E_TT_ANY: 2813 MLX5_SET(tirc, tirc, disp_type, 2814 MLX5_TIRC_DISP_TYPE_DIRECT); 2815 MLX5_SET(tirc, tirc, inline_rqn, 2816 priv->channel[0].rq.rqn); 2817 break; 2818 default: 2819 MLX5_SET(tirc, tirc, disp_type, 2820 MLX5_TIRC_DISP_TYPE_INDIRECT); 2821 MLX5_SET(tirc, tirc, indirect_table, 2822 priv->rqtn); 2823 MLX5_SET(tirc, tirc, rx_hash_fn, 2824 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ); 2825 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 2826 2827 CTASSERT(MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key) >= 2828 MLX5E_RSS_KEY_SIZE); 2829 #ifdef RSS 2830 /* 2831 * The FreeBSD RSS implementation does currently not 2832 * support symmetric Toeplitz hashes: 2833 */ 2834 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0); 2835 #else 2836 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 2837 #endif 2838 mlx5e_get_rss_key(hkey); 2839 break; 2840 } 2841 2842 switch (tt) { 2843 case MLX5E_TT_IPV4_TCP: 2844 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2845 MLX5_L3_PROT_TYPE_IPV4); 2846 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2847 MLX5_L4_PROT_TYPE_TCP); 2848 #ifdef RSS 2849 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) { 2850 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2851 MLX5_HASH_IP); 2852 } else 2853 #endif 2854 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2855 MLX5_HASH_ALL); 2856 break; 2857 2858 case MLX5E_TT_IPV6_TCP: 2859 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2860 MLX5_L3_PROT_TYPE_IPV6); 2861 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2862 MLX5_L4_PROT_TYPE_TCP); 2863 #ifdef RSS 2864 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) { 2865 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2866 MLX5_HASH_IP); 2867 } else 2868 #endif 2869 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2870 MLX5_HASH_ALL); 2871 break; 2872 2873 case MLX5E_TT_IPV4_UDP: 2874 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2875 MLX5_L3_PROT_TYPE_IPV4); 2876 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2877 MLX5_L4_PROT_TYPE_UDP); 2878 #ifdef RSS 2879 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) { 2880 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2881 MLX5_HASH_IP); 2882 } else 2883 #endif 2884 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2885 MLX5_HASH_ALL); 2886 break; 2887 2888 case MLX5E_TT_IPV6_UDP: 2889 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2890 MLX5_L3_PROT_TYPE_IPV6); 2891 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2892 MLX5_L4_PROT_TYPE_UDP); 2893 #ifdef RSS 2894 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) { 2895 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2896 MLX5_HASH_IP); 2897 } else 2898 #endif 2899 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2900 MLX5_HASH_ALL); 2901 break; 2902 2903 case MLX5E_TT_IPV4_IPSEC_AH: 2904 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2905 MLX5_L3_PROT_TYPE_IPV4); 2906 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2907 MLX5_HASH_IP_IPSEC_SPI); 2908 break; 2909 2910 case MLX5E_TT_IPV6_IPSEC_AH: 2911 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2912 MLX5_L3_PROT_TYPE_IPV6); 2913 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2914 MLX5_HASH_IP_IPSEC_SPI); 2915 break; 2916 2917 case MLX5E_TT_IPV4_IPSEC_ESP: 2918 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2919 MLX5_L3_PROT_TYPE_IPV4); 2920 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2921 MLX5_HASH_IP_IPSEC_SPI); 2922 break; 2923 2924 case MLX5E_TT_IPV6_IPSEC_ESP: 2925 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2926 MLX5_L3_PROT_TYPE_IPV6); 2927 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2928 MLX5_HASH_IP_IPSEC_SPI); 2929 break; 2930 2931 case MLX5E_TT_IPV4: 2932 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2933 MLX5_L3_PROT_TYPE_IPV4); 2934 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2935 MLX5_HASH_IP); 2936 break; 2937 2938 case MLX5E_TT_IPV6: 2939 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2940 MLX5_L3_PROT_TYPE_IPV6); 2941 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2942 MLX5_HASH_IP); 2943 break; 2944 2945 default: 2946 break; 2947 } 2948 } 2949 2950 static int 2951 mlx5e_open_tir(struct mlx5e_priv *priv, int tt) 2952 { 2953 struct mlx5_core_dev *mdev = priv->mdev; 2954 u32 *in; 2955 void *tirc; 2956 int inlen; 2957 int err; 2958 2959 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 2960 in = mlx5_vzalloc(inlen); 2961 if (in == NULL) 2962 return (-ENOMEM); 2963 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context); 2964 2965 mlx5e_build_tir_ctx(priv, tirc, tt); 2966 2967 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]); 2968 2969 kvfree(in); 2970 2971 return (err); 2972 } 2973 2974 static void 2975 mlx5e_close_tir(struct mlx5e_priv *priv, int tt) 2976 { 2977 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]); 2978 } 2979 2980 static int 2981 mlx5e_open_tirs(struct mlx5e_priv *priv) 2982 { 2983 int err; 2984 int i; 2985 2986 for (i = 0; i < MLX5E_NUM_TT; i++) { 2987 err = mlx5e_open_tir(priv, i); 2988 if (err) 2989 goto err_close_tirs; 2990 } 2991 2992 return (0); 2993 2994 err_close_tirs: 2995 for (i--; i >= 0; i--) 2996 mlx5e_close_tir(priv, i); 2997 2998 return (err); 2999 } 3000 3001 static void 3002 mlx5e_close_tirs(struct mlx5e_priv *priv) 3003 { 3004 int i; 3005 3006 for (i = 0; i < MLX5E_NUM_TT; i++) 3007 mlx5e_close_tir(priv, i); 3008 } 3009 3010 /* 3011 * SW MTU does not include headers, 3012 * HW MTU includes all headers and checksums. 3013 */ 3014 static int 3015 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu) 3016 { 3017 struct mlx5e_priv *priv = ifp->if_softc; 3018 struct mlx5_core_dev *mdev = priv->mdev; 3019 int hw_mtu; 3020 int err; 3021 3022 hw_mtu = MLX5E_SW2HW_MTU(sw_mtu); 3023 3024 err = mlx5_set_port_mtu(mdev, hw_mtu); 3025 if (err) { 3026 mlx5_en_err(ifp, "mlx5_set_port_mtu failed setting %d, err=%d\n", 3027 sw_mtu, err); 3028 return (err); 3029 } 3030 3031 /* Update vport context MTU */ 3032 err = mlx5_set_vport_mtu(mdev, hw_mtu); 3033 if (err) { 3034 mlx5_en_err(ifp, 3035 "Failed updating vport context with MTU size, err=%d\n", 3036 err); 3037 } 3038 3039 ifp->if_mtu = sw_mtu; 3040 3041 err = mlx5_query_vport_mtu(mdev, &hw_mtu); 3042 if (err || !hw_mtu) { 3043 /* fallback to port oper mtu */ 3044 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu); 3045 } 3046 if (err) { 3047 mlx5_en_err(ifp, 3048 "Query port MTU, after setting new MTU value, failed\n"); 3049 return (err); 3050 } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) { 3051 err = -E2BIG, 3052 mlx5_en_err(ifp, 3053 "Port MTU %d is smaller than ifp mtu %d\n", 3054 hw_mtu, sw_mtu); 3055 } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) { 3056 err = -EINVAL; 3057 mlx5_en_err(ifp, 3058 "Port MTU %d is bigger than ifp mtu %d\n", 3059 hw_mtu, sw_mtu); 3060 } 3061 priv->params_ethtool.hw_mtu = hw_mtu; 3062 3063 /* compute MSB */ 3064 while (hw_mtu & (hw_mtu - 1)) 3065 hw_mtu &= (hw_mtu - 1); 3066 priv->params_ethtool.hw_mtu_msb = hw_mtu; 3067 3068 return (err); 3069 } 3070 3071 int 3072 mlx5e_open_locked(struct ifnet *ifp) 3073 { 3074 struct mlx5e_priv *priv = ifp->if_softc; 3075 int err; 3076 u16 set_id; 3077 3078 /* check if already opened */ 3079 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 3080 return (0); 3081 3082 #ifdef RSS 3083 if (rss_getnumbuckets() > priv->params.num_channels) { 3084 mlx5_en_info(ifp, 3085 "NOTE: There are more RSS buckets(%u) than channels(%u) available\n", 3086 rss_getnumbuckets(), priv->params.num_channels); 3087 } 3088 #endif 3089 err = mlx5e_open_tises(priv); 3090 if (err) { 3091 mlx5_en_err(ifp, "mlx5e_open_tises failed, %d\n", err); 3092 return (err); 3093 } 3094 err = mlx5_vport_alloc_q_counter(priv->mdev, 3095 MLX5_INTERFACE_PROTOCOL_ETH, &set_id); 3096 if (err) { 3097 mlx5_en_err(priv->ifp, 3098 "mlx5_vport_alloc_q_counter failed: %d\n", err); 3099 goto err_close_tises; 3100 } 3101 /* store counter set ID */ 3102 priv->counter_set_id = set_id; 3103 3104 err = mlx5e_open_channels(priv); 3105 if (err) { 3106 mlx5_en_err(ifp, 3107 "mlx5e_open_channels failed, %d\n", err); 3108 goto err_dalloc_q_counter; 3109 } 3110 err = mlx5e_open_rqt(priv); 3111 if (err) { 3112 mlx5_en_err(ifp, "mlx5e_open_rqt failed, %d\n", err); 3113 goto err_close_channels; 3114 } 3115 err = mlx5e_open_tirs(priv); 3116 if (err) { 3117 mlx5_en_err(ifp, "mlx5e_open_tir failed, %d\n", err); 3118 goto err_close_rqls; 3119 } 3120 err = mlx5e_open_flow_table(priv); 3121 if (err) { 3122 mlx5_en_err(ifp, 3123 "mlx5e_open_flow_table failed, %d\n", err); 3124 goto err_close_tirs; 3125 } 3126 err = mlx5e_add_all_vlan_rules(priv); 3127 if (err) { 3128 mlx5_en_err(ifp, 3129 "mlx5e_add_all_vlan_rules failed, %d\n", err); 3130 goto err_close_flow_table; 3131 } 3132 set_bit(MLX5E_STATE_OPENED, &priv->state); 3133 3134 mlx5e_update_carrier(priv); 3135 mlx5e_set_rx_mode_core(priv); 3136 3137 return (0); 3138 3139 err_close_flow_table: 3140 mlx5e_close_flow_table(priv); 3141 3142 err_close_tirs: 3143 mlx5e_close_tirs(priv); 3144 3145 err_close_rqls: 3146 mlx5e_close_rqt(priv); 3147 3148 err_close_channels: 3149 mlx5e_close_channels(priv); 3150 3151 err_dalloc_q_counter: 3152 mlx5_vport_dealloc_q_counter(priv->mdev, 3153 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 3154 3155 err_close_tises: 3156 mlx5e_close_tises(priv); 3157 3158 return (err); 3159 } 3160 3161 static void 3162 mlx5e_open(void *arg) 3163 { 3164 struct mlx5e_priv *priv = arg; 3165 3166 PRIV_LOCK(priv); 3167 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP)) 3168 mlx5_en_err(priv->ifp, 3169 "Setting port status to up failed\n"); 3170 3171 mlx5e_open_locked(priv->ifp); 3172 priv->ifp->if_drv_flags |= IFF_DRV_RUNNING; 3173 PRIV_UNLOCK(priv); 3174 } 3175 3176 int 3177 mlx5e_close_locked(struct ifnet *ifp) 3178 { 3179 struct mlx5e_priv *priv = ifp->if_softc; 3180 3181 /* check if already closed */ 3182 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3183 return (0); 3184 3185 clear_bit(MLX5E_STATE_OPENED, &priv->state); 3186 3187 mlx5e_set_rx_mode_core(priv); 3188 mlx5e_del_all_vlan_rules(priv); 3189 if_link_state_change(priv->ifp, LINK_STATE_DOWN); 3190 mlx5e_close_flow_table(priv); 3191 mlx5e_close_tirs(priv); 3192 mlx5e_close_rqt(priv); 3193 mlx5e_close_channels(priv); 3194 mlx5_vport_dealloc_q_counter(priv->mdev, 3195 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id); 3196 mlx5e_close_tises(priv); 3197 3198 return (0); 3199 } 3200 3201 #if (__FreeBSD_version >= 1100000) 3202 static uint64_t 3203 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt) 3204 { 3205 struct mlx5e_priv *priv = ifp->if_softc; 3206 u64 retval; 3207 3208 /* PRIV_LOCK(priv); XXX not allowed */ 3209 switch (cnt) { 3210 case IFCOUNTER_IPACKETS: 3211 retval = priv->stats.vport.rx_packets; 3212 break; 3213 case IFCOUNTER_IERRORS: 3214 retval = priv->stats.pport.in_range_len_errors + 3215 priv->stats.pport.out_of_range_len + 3216 priv->stats.pport.too_long_errors + 3217 priv->stats.pport.check_seq_err + 3218 priv->stats.pport.alignment_err; 3219 break; 3220 case IFCOUNTER_IQDROPS: 3221 retval = priv->stats.vport.rx_out_of_buffer; 3222 break; 3223 case IFCOUNTER_OPACKETS: 3224 retval = priv->stats.vport.tx_packets; 3225 break; 3226 case IFCOUNTER_OERRORS: 3227 retval = priv->stats.port_stats_debug.out_discards; 3228 break; 3229 case IFCOUNTER_IBYTES: 3230 retval = priv->stats.vport.rx_bytes; 3231 break; 3232 case IFCOUNTER_OBYTES: 3233 retval = priv->stats.vport.tx_bytes; 3234 break; 3235 case IFCOUNTER_IMCASTS: 3236 retval = priv->stats.vport.rx_multicast_packets; 3237 break; 3238 case IFCOUNTER_OMCASTS: 3239 retval = priv->stats.vport.tx_multicast_packets; 3240 break; 3241 case IFCOUNTER_OQDROPS: 3242 retval = priv->stats.vport.tx_queue_dropped; 3243 break; 3244 case IFCOUNTER_COLLISIONS: 3245 retval = priv->stats.pport.collisions; 3246 break; 3247 default: 3248 retval = if_get_counter_default(ifp, cnt); 3249 break; 3250 } 3251 /* PRIV_UNLOCK(priv); XXX not allowed */ 3252 return (retval); 3253 } 3254 #endif 3255 3256 static void 3257 mlx5e_set_rx_mode(struct ifnet *ifp) 3258 { 3259 struct mlx5e_priv *priv = ifp->if_softc; 3260 3261 queue_work(priv->wq, &priv->set_rx_mode_work); 3262 } 3263 3264 static int 3265 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3266 { 3267 struct mlx5e_priv *priv; 3268 struct ifreq *ifr; 3269 struct ifdownreason *ifdr; 3270 struct ifi2creq i2c; 3271 struct ifrsskey *ifrk; 3272 struct ifrsshash *ifrh; 3273 int error = 0; 3274 int mask = 0; 3275 int size_read = 0; 3276 int module_status; 3277 int module_num; 3278 int max_mtu; 3279 uint8_t read_addr; 3280 3281 priv = ifp->if_softc; 3282 3283 /* check if detaching */ 3284 if (priv == NULL || priv->gone != 0) 3285 return (ENXIO); 3286 3287 switch (command) { 3288 case SIOCSIFMTU: 3289 ifr = (struct ifreq *)data; 3290 3291 PRIV_LOCK(priv); 3292 mlx5_query_port_max_mtu(priv->mdev, &max_mtu); 3293 3294 if (ifr->ifr_mtu >= MLX5E_MTU_MIN && 3295 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) { 3296 int was_opened; 3297 3298 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 3299 if (was_opened) 3300 mlx5e_close_locked(ifp); 3301 3302 /* set new MTU */ 3303 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu); 3304 3305 if (was_opened) 3306 mlx5e_open_locked(ifp); 3307 } else { 3308 error = EINVAL; 3309 mlx5_en_err(ifp, 3310 "Invalid MTU value. Min val: %d, Max val: %d\n", 3311 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu)); 3312 } 3313 PRIV_UNLOCK(priv); 3314 break; 3315 case SIOCSIFFLAGS: 3316 if ((ifp->if_flags & IFF_UP) && 3317 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3318 mlx5e_set_rx_mode(ifp); 3319 break; 3320 } 3321 PRIV_LOCK(priv); 3322 if (ifp->if_flags & IFF_UP) { 3323 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3324 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3325 mlx5e_open_locked(ifp); 3326 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3327 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP); 3328 } 3329 } else { 3330 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3331 mlx5_set_port_status(priv->mdev, 3332 MLX5_PORT_DOWN); 3333 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0) 3334 mlx5e_close_locked(ifp); 3335 mlx5e_update_carrier(priv); 3336 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3337 } 3338 } 3339 PRIV_UNLOCK(priv); 3340 break; 3341 case SIOCADDMULTI: 3342 case SIOCDELMULTI: 3343 mlx5e_set_rx_mode(ifp); 3344 break; 3345 case SIOCSIFMEDIA: 3346 case SIOCGIFMEDIA: 3347 case SIOCGIFXMEDIA: 3348 ifr = (struct ifreq *)data; 3349 error = ifmedia_ioctl(ifp, ifr, &priv->media, command); 3350 break; 3351 case SIOCSIFCAP: 3352 ifr = (struct ifreq *)data; 3353 PRIV_LOCK(priv); 3354 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3355 3356 if (mask & IFCAP_TXCSUM) { 3357 ifp->if_capenable ^= IFCAP_TXCSUM; 3358 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 3359 3360 if (IFCAP_TSO4 & ifp->if_capenable && 3361 !(IFCAP_TXCSUM & ifp->if_capenable)) { 3362 mask &= ~IFCAP_TSO4; 3363 ifp->if_capenable &= ~IFCAP_TSO4; 3364 ifp->if_hwassist &= ~CSUM_IP_TSO; 3365 mlx5_en_err(ifp, 3366 "tso4 disabled due to -txcsum.\n"); 3367 } 3368 } 3369 if (mask & IFCAP_TXCSUM_IPV6) { 3370 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 3371 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 3372 3373 if (IFCAP_TSO6 & ifp->if_capenable && 3374 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 3375 mask &= ~IFCAP_TSO6; 3376 ifp->if_capenable &= ~IFCAP_TSO6; 3377 ifp->if_hwassist &= ~CSUM_IP6_TSO; 3378 mlx5_en_err(ifp, 3379 "tso6 disabled due to -txcsum6.\n"); 3380 } 3381 } 3382 if (mask & IFCAP_NOMAP) 3383 ifp->if_capenable ^= IFCAP_NOMAP; 3384 if (mask & IFCAP_TXTLS4) 3385 ifp->if_capenable ^= IFCAP_TXTLS4; 3386 if (mask & IFCAP_TXTLS6) 3387 ifp->if_capenable ^= IFCAP_TXTLS6; 3388 #ifdef RATELIMIT 3389 if (mask & IFCAP_TXTLS_RTLMT) 3390 ifp->if_capenable ^= IFCAP_TXTLS_RTLMT; 3391 #endif 3392 if (mask & IFCAP_RXCSUM) 3393 ifp->if_capenable ^= IFCAP_RXCSUM; 3394 if (mask & IFCAP_RXCSUM_IPV6) 3395 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 3396 if (mask & IFCAP_TSO4) { 3397 if (!(IFCAP_TSO4 & ifp->if_capenable) && 3398 !(IFCAP_TXCSUM & ifp->if_capenable)) { 3399 mlx5_en_err(ifp, "enable txcsum first.\n"); 3400 error = EAGAIN; 3401 goto out; 3402 } 3403 ifp->if_capenable ^= IFCAP_TSO4; 3404 ifp->if_hwassist ^= CSUM_IP_TSO; 3405 } 3406 if (mask & IFCAP_TSO6) { 3407 if (!(IFCAP_TSO6 & ifp->if_capenable) && 3408 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 3409 mlx5_en_err(ifp, "enable txcsum6 first.\n"); 3410 error = EAGAIN; 3411 goto out; 3412 } 3413 ifp->if_capenable ^= IFCAP_TSO6; 3414 ifp->if_hwassist ^= CSUM_IP6_TSO; 3415 } 3416 if (mask & IFCAP_VLAN_HWFILTER) { 3417 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) 3418 mlx5e_disable_vlan_filter(priv); 3419 else 3420 mlx5e_enable_vlan_filter(priv); 3421 3422 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER; 3423 } 3424 if (mask & IFCAP_VLAN_HWTAGGING) 3425 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3426 if (mask & IFCAP_WOL_MAGIC) 3427 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3428 3429 VLAN_CAPABILITIES(ifp); 3430 /* turn off LRO means also turn of HW LRO - if it's on */ 3431 if (mask & IFCAP_LRO) { 3432 int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 3433 bool need_restart = false; 3434 3435 ifp->if_capenable ^= IFCAP_LRO; 3436 3437 /* figure out if updating HW LRO is needed */ 3438 if (!(ifp->if_capenable & IFCAP_LRO)) { 3439 if (priv->params.hw_lro_en) { 3440 priv->params.hw_lro_en = false; 3441 need_restart = true; 3442 } 3443 } else { 3444 if (priv->params.hw_lro_en == false && 3445 priv->params_ethtool.hw_lro != 0) { 3446 priv->params.hw_lro_en = true; 3447 need_restart = true; 3448 } 3449 } 3450 if (was_opened && need_restart) { 3451 mlx5e_close_locked(ifp); 3452 mlx5e_open_locked(ifp); 3453 } 3454 } 3455 if (mask & IFCAP_HWRXTSTMP) { 3456 ifp->if_capenable ^= IFCAP_HWRXTSTMP; 3457 if (ifp->if_capenable & IFCAP_HWRXTSTMP) { 3458 if (priv->clbr_done == 0) 3459 mlx5e_reset_calibration_callout(priv); 3460 } else { 3461 callout_drain(&priv->tstmp_clbr); 3462 priv->clbr_done = 0; 3463 } 3464 } 3465 out: 3466 PRIV_UNLOCK(priv); 3467 break; 3468 3469 case SIOCGI2C: 3470 ifr = (struct ifreq *)data; 3471 3472 /* 3473 * Copy from the user-space address ifr_data to the 3474 * kernel-space address i2c 3475 */ 3476 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 3477 if (error) 3478 break; 3479 3480 if (i2c.len > sizeof(i2c.data)) { 3481 error = EINVAL; 3482 break; 3483 } 3484 3485 PRIV_LOCK(priv); 3486 /* Get module_num which is required for the query_eeprom */ 3487 error = mlx5_query_module_num(priv->mdev, &module_num); 3488 if (error) { 3489 mlx5_en_err(ifp, 3490 "Query module num failed, eeprom reading is not supported\n"); 3491 error = EINVAL; 3492 goto err_i2c; 3493 } 3494 /* Check if module is present before doing an access */ 3495 module_status = mlx5_query_module_status(priv->mdev, module_num); 3496 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED) { 3497 error = EINVAL; 3498 goto err_i2c; 3499 } 3500 /* 3501 * Currently 0XA0 and 0xA2 are the only addresses permitted. 3502 * The internal conversion is as follows: 3503 */ 3504 if (i2c.dev_addr == 0xA0) 3505 read_addr = MLX5_I2C_ADDR_LOW; 3506 else if (i2c.dev_addr == 0xA2) 3507 read_addr = MLX5_I2C_ADDR_HIGH; 3508 else { 3509 mlx5_en_err(ifp, 3510 "Query eeprom failed, Invalid Address: %X\n", 3511 i2c.dev_addr); 3512 error = EINVAL; 3513 goto err_i2c; 3514 } 3515 error = mlx5_query_eeprom(priv->mdev, 3516 read_addr, MLX5_EEPROM_LOW_PAGE, 3517 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num, 3518 (uint32_t *)i2c.data, &size_read); 3519 if (error) { 3520 mlx5_en_err(ifp, 3521 "Query eeprom failed, eeprom reading is not supported\n"); 3522 error = EINVAL; 3523 goto err_i2c; 3524 } 3525 3526 if (i2c.len > MLX5_EEPROM_MAX_BYTES) { 3527 error = mlx5_query_eeprom(priv->mdev, 3528 read_addr, MLX5_EEPROM_LOW_PAGE, 3529 (uint32_t)(i2c.offset + size_read), 3530 (uint32_t)(i2c.len - size_read), module_num, 3531 (uint32_t *)(i2c.data + size_read), &size_read); 3532 } 3533 if (error) { 3534 mlx5_en_err(ifp, 3535 "Query eeprom failed, eeprom reading is not supported\n"); 3536 error = EINVAL; 3537 goto err_i2c; 3538 } 3539 3540 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 3541 err_i2c: 3542 PRIV_UNLOCK(priv); 3543 break; 3544 case SIOCGIFDOWNREASON: 3545 ifdr = (struct ifdownreason *)data; 3546 bzero(ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg)); 3547 PRIV_LOCK(priv); 3548 error = -mlx5_query_pddr_troubleshooting_info(priv->mdev, NULL, 3549 ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg)); 3550 PRIV_UNLOCK(priv); 3551 if (error == 0) 3552 ifdr->ifdr_reason = IFDR_REASON_MSG; 3553 break; 3554 3555 case SIOCGIFRSSKEY: 3556 ifrk = (struct ifrsskey *)data; 3557 ifrk->ifrk_func = RSS_FUNC_TOEPLITZ; 3558 ifrk->ifrk_keylen = MLX5E_RSS_KEY_SIZE; 3559 CTASSERT(sizeof(ifrk->ifrk_key) >= MLX5E_RSS_KEY_SIZE); 3560 mlx5e_get_rss_key(ifrk->ifrk_key); 3561 break; 3562 3563 case SIOCGIFRSSHASH: 3564 ifrh = (struct ifrsshash *)data; 3565 ifrh->ifrh_func = RSS_FUNC_TOEPLITZ; 3566 ifrh->ifrh_types = 3567 RSS_TYPE_IPV4 | 3568 RSS_TYPE_TCP_IPV4 | 3569 RSS_TYPE_UDP_IPV4 | 3570 RSS_TYPE_IPV6 | 3571 RSS_TYPE_TCP_IPV6 | 3572 RSS_TYPE_UDP_IPV6; 3573 break; 3574 3575 default: 3576 error = ether_ioctl(ifp, command, data); 3577 break; 3578 } 3579 return (error); 3580 } 3581 3582 static int 3583 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev) 3584 { 3585 /* 3586 * TODO: uncoment once FW really sets all these bits if 3587 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap || 3588 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap || 3589 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return 3590 * -ENOTSUPP; 3591 */ 3592 3593 /* TODO: add more must-to-have features */ 3594 3595 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) 3596 return (-ENODEV); 3597 3598 return (0); 3599 } 3600 3601 static u16 3602 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev) 3603 { 3604 const int min_size = ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN; 3605 const int max_size = MLX5E_MAX_TX_INLINE; 3606 const int bf_buf_size = 3607 ((1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U) - 3608 (sizeof(struct mlx5e_tx_wqe) - 2); 3609 3610 /* verify against driver limits */ 3611 if (bf_buf_size > max_size) 3612 return (max_size); 3613 else if (bf_buf_size < min_size) 3614 return (min_size); 3615 else 3616 return (bf_buf_size); 3617 } 3618 3619 static int 3620 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev, 3621 struct mlx5e_priv *priv, 3622 int num_comp_vectors) 3623 { 3624 int err; 3625 3626 /* 3627 * TODO: Consider link speed for setting "log_sq_size", 3628 * "log_rq_size" and "cq_moderation_xxx": 3629 */ 3630 priv->params.log_sq_size = 3631 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; 3632 priv->params.log_rq_size = 3633 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; 3634 priv->params.rx_cq_moderation_usec = 3635 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 3636 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE : 3637 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; 3638 priv->params.rx_cq_moderation_mode = 3639 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0; 3640 priv->params.rx_cq_moderation_pkts = 3641 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; 3642 priv->params.tx_cq_moderation_usec = 3643 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; 3644 priv->params.tx_cq_moderation_pkts = 3645 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; 3646 priv->params.min_rx_wqes = 3647 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES; 3648 priv->params.rx_hash_log_tbl_sz = 3649 (order_base_2(num_comp_vectors) > 3650 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ? 3651 order_base_2(num_comp_vectors) : 3652 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ; 3653 priv->params.num_tc = 1; 3654 priv->params.default_vlan_prio = 0; 3655 priv->counter_set_id = -1; 3656 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev); 3657 3658 err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode); 3659 if (err) 3660 return (err); 3661 3662 /* 3663 * hw lro is currently defaulted to off. when it won't anymore we 3664 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)" 3665 */ 3666 priv->params.hw_lro_en = false; 3667 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; 3668 3669 /* 3670 * CQE zipping is currently defaulted to off. when it won't 3671 * anymore we will consider the HW capability: 3672 * "!!MLX5_CAP_GEN(mdev, cqe_compression)" 3673 */ 3674 priv->params.cqe_zipping_en = false; 3675 3676 priv->mdev = mdev; 3677 priv->params.num_channels = num_comp_vectors; 3678 priv->params.channels_rsss = 1; 3679 priv->order_base_2_num_channels = order_base_2(num_comp_vectors); 3680 priv->queue_mapping_channel_mask = 3681 roundup_pow_of_two(num_comp_vectors) - 1; 3682 priv->num_tc = priv->params.num_tc; 3683 priv->default_vlan_prio = priv->params.default_vlan_prio; 3684 3685 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work); 3686 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); 3687 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); 3688 3689 return (0); 3690 } 3691 3692 static int 3693 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn, 3694 struct mlx5_core_mr *mkey) 3695 { 3696 struct ifnet *ifp = priv->ifp; 3697 struct mlx5_core_dev *mdev = priv->mdev; 3698 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 3699 void *mkc; 3700 u32 *in; 3701 int err; 3702 3703 in = mlx5_vzalloc(inlen); 3704 if (in == NULL) { 3705 mlx5_en_err(ifp, "failed to allocate inbox\n"); 3706 return (-ENOMEM); 3707 } 3708 3709 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 3710 MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA); 3711 MLX5_SET(mkc, mkc, umr_en, 1); /* used by HW TLS */ 3712 MLX5_SET(mkc, mkc, lw, 1); 3713 MLX5_SET(mkc, mkc, lr, 1); 3714 3715 MLX5_SET(mkc, mkc, pd, pdn); 3716 MLX5_SET(mkc, mkc, length64, 1); 3717 MLX5_SET(mkc, mkc, qpn, 0xffffff); 3718 3719 err = mlx5_core_create_mkey(mdev, mkey, in, inlen); 3720 if (err) 3721 mlx5_en_err(ifp, "mlx5_core_create_mkey failed, %d\n", 3722 err); 3723 3724 kvfree(in); 3725 return (err); 3726 } 3727 3728 static const char *mlx5e_vport_stats_desc[] = { 3729 MLX5E_VPORT_STATS(MLX5E_STATS_DESC) 3730 }; 3731 3732 static const char *mlx5e_pport_stats_desc[] = { 3733 MLX5E_PPORT_STATS(MLX5E_STATS_DESC) 3734 }; 3735 3736 static void 3737 mlx5e_priv_static_init(struct mlx5e_priv *priv, const uint32_t channels) 3738 { 3739 uint32_t x; 3740 3741 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF); 3742 sx_init(&priv->state_lock, "mlx5state"); 3743 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0); 3744 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock); 3745 for (x = 0; x != channels; x++) 3746 mlx5e_chan_static_init(priv, &priv->channel[x], x); 3747 } 3748 3749 static void 3750 mlx5e_priv_static_destroy(struct mlx5e_priv *priv, const uint32_t channels) 3751 { 3752 uint32_t x; 3753 3754 for (x = 0; x != channels; x++) 3755 mlx5e_chan_static_destroy(&priv->channel[x]); 3756 callout_drain(&priv->watchdog); 3757 mtx_destroy(&priv->async_events_mtx); 3758 sx_destroy(&priv->state_lock); 3759 } 3760 3761 static int 3762 sysctl_firmware(SYSCTL_HANDLER_ARGS) 3763 { 3764 /* 3765 * %d.%d%.d the string format. 3766 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536. 3767 * We need at most 5 chars to store that. 3768 * It also has: two "." and NULL at the end, which means we need 18 3769 * (5*3 + 3) chars at most. 3770 */ 3771 char fw[18]; 3772 struct mlx5e_priv *priv = arg1; 3773 int error; 3774 3775 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev), 3776 fw_rev_sub(priv->mdev)); 3777 error = sysctl_handle_string(oidp, fw, sizeof(fw), req); 3778 return (error); 3779 } 3780 3781 static void 3782 mlx5e_disable_tx_dma(struct mlx5e_channel *ch) 3783 { 3784 int i; 3785 3786 for (i = 0; i < ch->priv->num_tc; i++) 3787 mlx5e_drain_sq(&ch->sq[i]); 3788 } 3789 3790 static void 3791 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq) 3792 { 3793 3794 sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP); 3795 sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8); 3796 mlx5e_tx_notify_hw(sq, sq->doorbell.d32); 3797 sq->doorbell.d64 = 0; 3798 } 3799 3800 void 3801 mlx5e_resume_sq(struct mlx5e_sq *sq) 3802 { 3803 int err; 3804 3805 /* check if already enabled */ 3806 if (READ_ONCE(sq->running) != 0) 3807 return; 3808 3809 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR, 3810 MLX5_SQC_STATE_RST); 3811 if (err != 0) { 3812 mlx5_en_err(sq->ifp, 3813 "mlx5e_modify_sq() from ERR to RST failed: %d\n", err); 3814 } 3815 3816 sq->cc = 0; 3817 sq->pc = 0; 3818 3819 /* reset doorbell prior to moving from RST to RDY */ 3820 mlx5e_reset_sq_doorbell_record(sq); 3821 3822 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, 3823 MLX5_SQC_STATE_RDY); 3824 if (err != 0) { 3825 mlx5_en_err(sq->ifp, 3826 "mlx5e_modify_sq() from RST to RDY failed: %d\n", err); 3827 } 3828 3829 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL; 3830 WRITE_ONCE(sq->running, 1); 3831 } 3832 3833 static void 3834 mlx5e_enable_tx_dma(struct mlx5e_channel *ch) 3835 { 3836 int i; 3837 3838 for (i = 0; i < ch->priv->num_tc; i++) 3839 mlx5e_resume_sq(&ch->sq[i]); 3840 } 3841 3842 static void 3843 mlx5e_disable_rx_dma(struct mlx5e_channel *ch) 3844 { 3845 struct mlx5e_rq *rq = &ch->rq; 3846 struct epoch_tracker et; 3847 int err; 3848 3849 mtx_lock(&rq->mtx); 3850 rq->enabled = 0; 3851 callout_stop(&rq->watchdog); 3852 mtx_unlock(&rq->mtx); 3853 3854 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); 3855 if (err != 0) { 3856 mlx5_en_err(rq->ifp, 3857 "mlx5e_modify_rq() from RDY to RST failed: %d\n", err); 3858 } 3859 3860 while (!mlx5_wq_ll_is_empty(&rq->wq)) { 3861 msleep(1); 3862 NET_EPOCH_ENTER(et); 3863 rq->cq.mcq.comp(&rq->cq.mcq, NULL); 3864 NET_EPOCH_EXIT(et); 3865 } 3866 3867 /* 3868 * Transitioning into RST state will allow the FW to track less ERR state queues, 3869 * thus reducing the recv queue flushing time 3870 */ 3871 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST); 3872 if (err != 0) { 3873 mlx5_en_err(rq->ifp, 3874 "mlx5e_modify_rq() from ERR to RST failed: %d\n", err); 3875 } 3876 } 3877 3878 static void 3879 mlx5e_enable_rx_dma(struct mlx5e_channel *ch) 3880 { 3881 struct mlx5e_rq *rq = &ch->rq; 3882 struct epoch_tracker et; 3883 int err; 3884 3885 rq->wq.wqe_ctr = 0; 3886 mlx5_wq_ll_update_db_record(&rq->wq); 3887 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 3888 if (err != 0) { 3889 mlx5_en_err(rq->ifp, 3890 "mlx5e_modify_rq() from RST to RDY failed: %d\n", err); 3891 } 3892 3893 rq->enabled = 1; 3894 3895 NET_EPOCH_ENTER(et); 3896 rq->cq.mcq.comp(&rq->cq.mcq, NULL); 3897 NET_EPOCH_EXIT(et); 3898 } 3899 3900 void 3901 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value) 3902 { 3903 int i; 3904 3905 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3906 return; 3907 3908 for (i = 0; i < priv->params.num_channels; i++) { 3909 if (value) 3910 mlx5e_disable_tx_dma(&priv->channel[i]); 3911 else 3912 mlx5e_enable_tx_dma(&priv->channel[i]); 3913 } 3914 } 3915 3916 void 3917 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value) 3918 { 3919 int i; 3920 3921 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0) 3922 return; 3923 3924 for (i = 0; i < priv->params.num_channels; i++) { 3925 if (value) 3926 mlx5e_disable_rx_dma(&priv->channel[i]); 3927 else 3928 mlx5e_enable_rx_dma(&priv->channel[i]); 3929 } 3930 } 3931 3932 static void 3933 mlx5e_add_hw_stats(struct mlx5e_priv *priv) 3934 { 3935 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 3936 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 3937 priv, 0, sysctl_firmware, "A", "HCA firmware version"); 3938 3939 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw), 3940 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0, 3941 "Board ID"); 3942 } 3943 3944 static int 3945 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS) 3946 { 3947 struct mlx5e_priv *priv = arg1; 3948 uint8_t temp[MLX5E_MAX_PRIORITY]; 3949 uint32_t tx_pfc; 3950 int err; 3951 int i; 3952 3953 PRIV_LOCK(priv); 3954 3955 tx_pfc = priv->params.tx_priority_flow_control; 3956 3957 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) 3958 temp[i] = (tx_pfc >> i) & 1; 3959 3960 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY); 3961 if (err || !req->newptr) 3962 goto done; 3963 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY); 3964 if (err) 3965 goto done; 3966 3967 priv->params.tx_priority_flow_control = 0; 3968 3969 /* range check input value */ 3970 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) { 3971 if (temp[i] > 1) { 3972 err = ERANGE; 3973 goto done; 3974 } 3975 priv->params.tx_priority_flow_control |= (temp[i] << i); 3976 } 3977 3978 /* check if update is required */ 3979 if (tx_pfc != priv->params.tx_priority_flow_control) 3980 err = -mlx5e_set_port_pfc(priv); 3981 done: 3982 if (err != 0) 3983 priv->params.tx_priority_flow_control= tx_pfc; 3984 PRIV_UNLOCK(priv); 3985 3986 return (err); 3987 } 3988 3989 static int 3990 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS) 3991 { 3992 struct mlx5e_priv *priv = arg1; 3993 uint8_t temp[MLX5E_MAX_PRIORITY]; 3994 uint32_t rx_pfc; 3995 int err; 3996 int i; 3997 3998 PRIV_LOCK(priv); 3999 4000 rx_pfc = priv->params.rx_priority_flow_control; 4001 4002 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) 4003 temp[i] = (rx_pfc >> i) & 1; 4004 4005 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY); 4006 if (err || !req->newptr) 4007 goto done; 4008 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY); 4009 if (err) 4010 goto done; 4011 4012 priv->params.rx_priority_flow_control = 0; 4013 4014 /* range check input value */ 4015 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) { 4016 if (temp[i] > 1) { 4017 err = ERANGE; 4018 goto done; 4019 } 4020 priv->params.rx_priority_flow_control |= (temp[i] << i); 4021 } 4022 4023 /* check if update is required */ 4024 if (rx_pfc != priv->params.rx_priority_flow_control) { 4025 err = -mlx5e_set_port_pfc(priv); 4026 if (err == 0 && priv->sw_is_port_buf_owner) 4027 err = mlx5e_update_buf_lossy(priv); 4028 } 4029 done: 4030 if (err != 0) 4031 priv->params.rx_priority_flow_control= rx_pfc; 4032 PRIV_UNLOCK(priv); 4033 4034 return (err); 4035 } 4036 4037 static void 4038 mlx5e_setup_pauseframes(struct mlx5e_priv *priv) 4039 { 4040 #if (__FreeBSD_version < 1100000) 4041 char path[96]; 4042 #endif 4043 int error; 4044 4045 /* enable pauseframes by default */ 4046 priv->params.tx_pauseframe_control = 1; 4047 priv->params.rx_pauseframe_control = 1; 4048 4049 /* disable ports flow control, PFC, by default */ 4050 priv->params.tx_priority_flow_control = 0; 4051 priv->params.rx_priority_flow_control = 0; 4052 4053 #if (__FreeBSD_version < 1100000) 4054 /* compute path for sysctl */ 4055 snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control", 4056 device_get_unit(priv->mdev->pdev->dev.bsddev)); 4057 4058 /* try to fetch tunable, if any */ 4059 TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control); 4060 4061 /* compute path for sysctl */ 4062 snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control", 4063 device_get_unit(priv->mdev->pdev->dev.bsddev)); 4064 4065 /* try to fetch tunable, if any */ 4066 TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control); 4067 #endif 4068 4069 /* register pauseframe SYSCTLs */ 4070 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4071 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN, 4072 &priv->params.tx_pauseframe_control, 0, 4073 "Set to enable TX pause frames. Clear to disable."); 4074 4075 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4076 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN, 4077 &priv->params.rx_pauseframe_control, 0, 4078 "Set to enable RX pause frames. Clear to disable."); 4079 4080 /* register priority flow control, PFC, SYSCTLs */ 4081 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4082 OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN | 4083 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU", 4084 "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable."); 4085 4086 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4087 OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN | 4088 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU", 4089 "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable."); 4090 4091 PRIV_LOCK(priv); 4092 4093 /* range check */ 4094 priv->params.tx_pauseframe_control = 4095 priv->params.tx_pauseframe_control ? 1 : 0; 4096 priv->params.rx_pauseframe_control = 4097 priv->params.rx_pauseframe_control ? 1 : 0; 4098 4099 /* update firmware */ 4100 error = mlx5e_set_port_pause_and_pfc(priv); 4101 if (error == -EINVAL) { 4102 mlx5_en_err(priv->ifp, 4103 "Global pauseframes must be disabled before enabling PFC.\n"); 4104 priv->params.rx_priority_flow_control = 0; 4105 priv->params.tx_priority_flow_control = 0; 4106 4107 /* update firmware */ 4108 (void) mlx5e_set_port_pause_and_pfc(priv); 4109 } 4110 PRIV_UNLOCK(priv); 4111 } 4112 4113 int 4114 mlx5e_ul_snd_tag_alloc(struct ifnet *ifp, 4115 union if_snd_tag_alloc_params *params, 4116 struct m_snd_tag **ppmt) 4117 { 4118 struct mlx5e_priv *priv; 4119 struct mlx5e_channel *pch; 4120 4121 priv = ifp->if_softc; 4122 4123 if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) { 4124 return (EOPNOTSUPP); 4125 } else { 4126 /* keep this code synced with mlx5e_select_queue() */ 4127 u32 ch = priv->params.num_channels; 4128 #ifdef RSS 4129 u32 temp; 4130 4131 if (rss_hash2bucket(params->hdr.flowid, 4132 params->hdr.flowtype, &temp) == 0) 4133 ch = temp % ch; 4134 else 4135 #endif 4136 ch = (params->hdr.flowid % 128) % ch; 4137 4138 /* 4139 * NOTE: The channels array is only freed at detach 4140 * and it safe to return a pointer to the send tag 4141 * inside the channels structure as long as we 4142 * reference the priv. 4143 */ 4144 pch = priv->channel + ch; 4145 4146 /* check if send queue is not running */ 4147 if (unlikely(pch->sq[0].running == 0)) 4148 return (ENXIO); 4149 m_snd_tag_ref(&pch->tag); 4150 *ppmt = &pch->tag; 4151 return (0); 4152 } 4153 } 4154 4155 int 4156 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params) 4157 { 4158 struct mlx5e_channel *pch = 4159 container_of(pmt, struct mlx5e_channel, tag); 4160 4161 params->unlimited.max_rate = -1ULL; 4162 params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]); 4163 return (0); 4164 } 4165 4166 void 4167 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt) 4168 { 4169 struct mlx5e_channel *pch = 4170 container_of(pmt, struct mlx5e_channel, tag); 4171 4172 complete(&pch->completion); 4173 } 4174 4175 static int 4176 mlx5e_snd_tag_alloc(struct ifnet *ifp, 4177 union if_snd_tag_alloc_params *params, 4178 struct m_snd_tag **ppmt) 4179 { 4180 4181 switch (params->hdr.type) { 4182 #ifdef RATELIMIT 4183 case IF_SND_TAG_TYPE_RATE_LIMIT: 4184 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt)); 4185 #ifdef KERN_TLS 4186 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT: 4187 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt)); 4188 #endif 4189 #endif 4190 case IF_SND_TAG_TYPE_UNLIMITED: 4191 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt)); 4192 #ifdef KERN_TLS 4193 case IF_SND_TAG_TYPE_TLS: 4194 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt)); 4195 #endif 4196 default: 4197 return (EOPNOTSUPP); 4198 } 4199 } 4200 4201 static int 4202 mlx5e_snd_tag_modify(struct m_snd_tag *pmt, union if_snd_tag_modify_params *params) 4203 { 4204 4205 switch (pmt->type) { 4206 #ifdef RATELIMIT 4207 case IF_SND_TAG_TYPE_RATE_LIMIT: 4208 return (mlx5e_rl_snd_tag_modify(pmt, params)); 4209 #ifdef KERN_TLS 4210 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT: 4211 return (mlx5e_tls_snd_tag_modify(pmt, params)); 4212 #endif 4213 #endif 4214 case IF_SND_TAG_TYPE_UNLIMITED: 4215 #ifdef KERN_TLS 4216 case IF_SND_TAG_TYPE_TLS: 4217 #endif 4218 default: 4219 return (EOPNOTSUPP); 4220 } 4221 } 4222 4223 static int 4224 mlx5e_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params) 4225 { 4226 4227 switch (pmt->type) { 4228 #ifdef RATELIMIT 4229 case IF_SND_TAG_TYPE_RATE_LIMIT: 4230 return (mlx5e_rl_snd_tag_query(pmt, params)); 4231 #ifdef KERN_TLS 4232 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT: 4233 return (mlx5e_tls_snd_tag_query(pmt, params)); 4234 #endif 4235 #endif 4236 case IF_SND_TAG_TYPE_UNLIMITED: 4237 return (mlx5e_ul_snd_tag_query(pmt, params)); 4238 #ifdef KERN_TLS 4239 case IF_SND_TAG_TYPE_TLS: 4240 return (mlx5e_tls_snd_tag_query(pmt, params)); 4241 #endif 4242 default: 4243 return (EOPNOTSUPP); 4244 } 4245 } 4246 4247 #ifdef RATELIMIT 4248 #define NUM_HDWR_RATES_MLX 13 4249 static const uint64_t adapter_rates_mlx[NUM_HDWR_RATES_MLX] = { 4250 135375, /* 1,083,000 */ 4251 180500, /* 1,444,000 */ 4252 270750, /* 2,166,000 */ 4253 361000, /* 2,888,000 */ 4254 541500, /* 4,332,000 */ 4255 721875, /* 5,775,000 */ 4256 1082875, /* 8,663,000 */ 4257 1443875, /* 11,551,000 */ 4258 2165750, /* 17,326,000 */ 4259 2887750, /* 23,102,000 */ 4260 4331625, /* 34,653,000 */ 4261 5775500, /* 46,204,000 */ 4262 8663125 /* 69,305,000 */ 4263 }; 4264 4265 static void 4266 mlx5e_ratelimit_query(struct ifnet *ifp __unused, struct if_ratelimit_query_results *q) 4267 { 4268 /* 4269 * This function needs updating by the driver maintainer! 4270 * For the MLX card there are currently (ConectX-4?) 13 4271 * pre-set rates and others i.e. ConnectX-5, 6, 7?? 4272 * 4273 * This will change based on later adapters 4274 * and this code should be updated to look at ifp 4275 * and figure out the specific adapter type 4276 * settings i.e. how many rates as well 4277 * as if they are fixed (as is shown here) or 4278 * if they are dynamic (example chelsio t4). Also if there 4279 * is a maximum number of flows that the adapter 4280 * can handle that too needs to be updated in 4281 * the max_flows field. 4282 */ 4283 q->rate_table = adapter_rates_mlx; 4284 q->flags = RT_IS_FIXED_TABLE; 4285 q->max_flows = 0; /* mlx has no limit */ 4286 q->number_of_rates = NUM_HDWR_RATES_MLX; 4287 q->min_segment_burst = 1; 4288 } 4289 #endif 4290 4291 static void 4292 mlx5e_snd_tag_free(struct m_snd_tag *pmt) 4293 { 4294 4295 switch (pmt->type) { 4296 #ifdef RATELIMIT 4297 case IF_SND_TAG_TYPE_RATE_LIMIT: 4298 mlx5e_rl_snd_tag_free(pmt); 4299 break; 4300 #ifdef KERN_TLS 4301 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT: 4302 mlx5e_tls_snd_tag_free(pmt); 4303 break; 4304 #endif 4305 #endif 4306 case IF_SND_TAG_TYPE_UNLIMITED: 4307 mlx5e_ul_snd_tag_free(pmt); 4308 break; 4309 #ifdef KERN_TLS 4310 case IF_SND_TAG_TYPE_TLS: 4311 mlx5e_tls_snd_tag_free(pmt); 4312 break; 4313 #endif 4314 default: 4315 break; 4316 } 4317 } 4318 4319 static void 4320 mlx5e_ifm_add(struct mlx5e_priv *priv, int type) 4321 { 4322 ifmedia_add(&priv->media, type | IFM_ETHER, 0, NULL); 4323 ifmedia_add(&priv->media, type | IFM_ETHER | 4324 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 4325 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_RXPAUSE, 0, NULL); 4326 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_TXPAUSE, 0, NULL); 4327 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX, 0, NULL); 4328 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX | 4329 IFM_ETH_RXPAUSE, 0, NULL); 4330 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX | 4331 IFM_ETH_TXPAUSE, 0, NULL); 4332 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX | 4333 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL); 4334 } 4335 4336 static void * 4337 mlx5e_create_ifp(struct mlx5_core_dev *mdev) 4338 { 4339 struct ifnet *ifp; 4340 struct mlx5e_priv *priv; 4341 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4); 4342 u8 connector_type; 4343 struct sysctl_oid_list *child; 4344 int ncv = mdev->priv.eq_table.num_comp_vectors; 4345 char unit[16]; 4346 struct pfil_head_args pa; 4347 int err; 4348 int i,j; 4349 u32 eth_proto_cap; 4350 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; 4351 bool ext = 0; 4352 u32 speeds_num; 4353 struct media media_entry = {}; 4354 4355 if (mlx5e_check_required_hca_cap(mdev)) { 4356 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n"); 4357 return (NULL); 4358 } 4359 /* 4360 * Try to allocate the priv and make room for worst-case 4361 * number of channel structures: 4362 */ 4363 priv = malloc(sizeof(*priv) + 4364 (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors), 4365 M_MLX5EN, M_WAITOK | M_ZERO); 4366 4367 ifp = priv->ifp = if_alloc_dev(IFT_ETHER, mdev->pdev->dev.bsddev); 4368 if (ifp == NULL) { 4369 mlx5_core_err(mdev, "if_alloc() failed\n"); 4370 goto err_free_priv; 4371 } 4372 /* setup all static fields */ 4373 mlx5e_priv_static_init(priv, mdev->priv.eq_table.num_comp_vectors); 4374 4375 ifp->if_softc = priv; 4376 if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev)); 4377 ifp->if_mtu = ETHERMTU; 4378 ifp->if_init = mlx5e_open; 4379 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 4380 IFF_KNOWSEPOCH; 4381 ifp->if_ioctl = mlx5e_ioctl; 4382 ifp->if_transmit = mlx5e_xmit; 4383 ifp->if_qflush = if_qflush; 4384 #if (__FreeBSD_version >= 1100000) 4385 ifp->if_get_counter = mlx5e_get_counter; 4386 #endif 4387 ifp->if_snd.ifq_maxlen = ifqmaxlen; 4388 /* 4389 * Set driver features 4390 */ 4391 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6; 4392 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 4393 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER; 4394 ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU; 4395 ifp->if_capabilities |= IFCAP_LRO; 4396 ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO; 4397 ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP; 4398 ifp->if_capabilities |= IFCAP_NOMAP; 4399 ifp->if_capabilities |= IFCAP_TXTLS4 | IFCAP_TXTLS6; 4400 #ifdef RATELIMIT 4401 ifp->if_capabilities |= IFCAP_TXRTLMT | IFCAP_TXTLS_RTLMT; 4402 #endif 4403 ifp->if_snd_tag_alloc = mlx5e_snd_tag_alloc; 4404 ifp->if_snd_tag_free = mlx5e_snd_tag_free; 4405 ifp->if_snd_tag_modify = mlx5e_snd_tag_modify; 4406 ifp->if_snd_tag_query = mlx5e_snd_tag_query; 4407 #ifdef RATELIMIT 4408 ifp->if_ratelimit_query = mlx5e_ratelimit_query; 4409 #endif 4410 /* set TSO limits so that we don't have to drop TX packets */ 4411 ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 4412 ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */; 4413 ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE; 4414 4415 ifp->if_capenable = ifp->if_capabilities; 4416 ifp->if_hwassist = 0; 4417 if (ifp->if_capenable & IFCAP_TSO) 4418 ifp->if_hwassist |= CSUM_TSO; 4419 if (ifp->if_capenable & IFCAP_TXCSUM) 4420 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP); 4421 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6) 4422 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 4423 4424 /* ifnet sysctl tree */ 4425 sysctl_ctx_init(&priv->sysctl_ctx); 4426 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev), 4427 OID_AUTO, ifp->if_dname, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 4428 "MLX5 ethernet - interface name"); 4429 if (priv->sysctl_ifnet == NULL) { 4430 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4431 goto err_free_sysctl; 4432 } 4433 snprintf(unit, sizeof(unit), "%d", ifp->if_dunit); 4434 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4435 OID_AUTO, unit, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 4436 "MLX5 ethernet - interface unit"); 4437 if (priv->sysctl_ifnet == NULL) { 4438 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4439 goto err_free_sysctl; 4440 } 4441 4442 /* HW sysctl tree */ 4443 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev)); 4444 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child, 4445 OID_AUTO, "hw", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 4446 "MLX5 ethernet dev hw"); 4447 if (priv->sysctl_hw == NULL) { 4448 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n"); 4449 goto err_free_sysctl; 4450 } 4451 4452 err = mlx5e_build_ifp_priv(mdev, priv, ncv); 4453 if (err) { 4454 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err); 4455 goto err_free_sysctl; 4456 } 4457 4458 /* reuse mlx5core's watchdog workqueue */ 4459 priv->wq = mdev->priv.health.wq_watchdog; 4460 4461 err = mlx5_core_alloc_pd(mdev, &priv->pdn); 4462 if (err) { 4463 mlx5_en_err(ifp, "mlx5_core_alloc_pd failed, %d\n", err); 4464 goto err_free_wq; 4465 } 4466 err = mlx5_alloc_transport_domain(mdev, &priv->tdn); 4467 if (err) { 4468 mlx5_en_err(ifp, 4469 "mlx5_alloc_transport_domain failed, %d\n", err); 4470 goto err_dealloc_pd; 4471 } 4472 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr); 4473 if (err) { 4474 mlx5_en_err(ifp, "mlx5e_create_mkey failed, %d\n", err); 4475 goto err_dealloc_transport_domain; 4476 } 4477 err = mlx5_alloc_bfreg(mdev, &priv->bfreg, false, false); 4478 if (err) { 4479 mlx5_en_err(ifp, "alloc bfreg failed, %d\n", err); 4480 goto err_create_mkey; 4481 } 4482 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr); 4483 4484 /* check if we should generate a random MAC address */ 4485 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 && 4486 is_zero_ether_addr(dev_addr)) { 4487 random_ether_addr(dev_addr); 4488 mlx5_en_err(ifp, "Assigned random MAC address\n"); 4489 } 4490 4491 err = mlx5e_rl_init(priv); 4492 if (err) { 4493 mlx5_en_err(ifp, "mlx5e_rl_init failed, %d\n", err); 4494 goto err_alloc_bfreg; 4495 } 4496 4497 err = mlx5e_tls_init(priv); 4498 if (err) { 4499 if_printf(ifp, "%s: mlx5e_tls_init failed\n", __func__); 4500 goto err_rl_init; 4501 } 4502 4503 /* set default MTU */ 4504 mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu); 4505 4506 /* Set default media status */ 4507 priv->media_status_last = IFM_AVALID; 4508 priv->media_active_last = IFM_ETHER | IFM_AUTO | IFM_FDX; 4509 4510 /* setup default pauseframes configuration */ 4511 mlx5e_setup_pauseframes(priv); 4512 4513 /* Setup supported medias */ 4514 //TODO: If we failed to query ptys is it ok to proceed?? 4515 if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) { 4516 ext = MLX5_CAP_PCAM_FEATURE(mdev, 4517 ptys_extended_ethernet); 4518 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 4519 eth_proto_capability); 4520 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type)) 4521 connector_type = MLX5_GET(ptys_reg, out, 4522 connector_type); 4523 } else { 4524 eth_proto_cap = 0; 4525 mlx5_en_err(ifp, "Query port media capability failed, %d\n", err); 4526 } 4527 4528 ifmedia_init(&priv->media, IFM_IMASK, 4529 mlx5e_media_change, mlx5e_media_status); 4530 4531 speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER : MLX5E_LINK_SPEEDS_NUMBER; 4532 for (i = 0; i != speeds_num; i++) { 4533 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) { 4534 media_entry = ext ? mlx5e_ext_mode_table[i][j] : 4535 mlx5e_mode_table[i][j]; 4536 if (media_entry.baudrate == 0) 4537 continue; 4538 if (MLX5E_PROT_MASK(i) & eth_proto_cap) 4539 mlx5e_ifm_add(priv, media_entry.subtype); 4540 } 4541 } 4542 4543 mlx5e_ifm_add(priv, IFM_AUTO); 4544 4545 /* Set autoselect by default */ 4546 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX | 4547 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE); 4548 4549 DEBUGNET_SET(ifp, mlx5_en); 4550 4551 ether_ifattach(ifp, dev_addr); 4552 4553 /* Register for VLAN events */ 4554 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config, 4555 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST); 4556 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig, 4557 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST); 4558 4559 /* Link is down by default */ 4560 if_link_state_change(ifp, LINK_STATE_DOWN); 4561 4562 mlx5e_enable_async_events(priv); 4563 4564 mlx5e_add_hw_stats(priv); 4565 4566 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4567 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM, 4568 priv->stats.vport.arg); 4569 4570 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4571 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM, 4572 priv->stats.pport.arg); 4573 4574 mlx5e_create_ethtool(priv); 4575 4576 mtx_lock(&priv->async_events_mtx); 4577 mlx5e_update_stats(priv); 4578 mtx_unlock(&priv->async_events_mtx); 4579 4580 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet), 4581 OID_AUTO, "rx_clbr_done", CTLFLAG_RD, 4582 &priv->clbr_done, 0, 4583 "RX timestamps calibration state"); 4584 callout_init(&priv->tstmp_clbr, CALLOUT_DIRECT); 4585 mlx5e_reset_calibration_callout(priv); 4586 4587 pa.pa_version = PFIL_VERSION; 4588 pa.pa_flags = PFIL_IN; 4589 pa.pa_type = PFIL_TYPE_ETHERNET; 4590 pa.pa_headname = ifp->if_xname; 4591 priv->pfil = pfil_head_register(&pa); 4592 4593 return (priv); 4594 4595 err_rl_init: 4596 mlx5e_rl_cleanup(priv); 4597 4598 err_alloc_bfreg: 4599 mlx5_free_bfreg(mdev, &priv->bfreg); 4600 4601 err_create_mkey: 4602 mlx5_core_destroy_mkey(priv->mdev, &priv->mr); 4603 4604 err_dealloc_transport_domain: 4605 mlx5_dealloc_transport_domain(mdev, priv->tdn); 4606 4607 err_dealloc_pd: 4608 mlx5_core_dealloc_pd(mdev, priv->pdn); 4609 4610 err_free_wq: 4611 flush_workqueue(priv->wq); 4612 4613 err_free_sysctl: 4614 sysctl_ctx_free(&priv->sysctl_ctx); 4615 if (priv->sysctl_debug) 4616 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx); 4617 mlx5e_priv_static_destroy(priv, mdev->priv.eq_table.num_comp_vectors); 4618 if_free(ifp); 4619 4620 err_free_priv: 4621 free(priv, M_MLX5EN); 4622 return (NULL); 4623 } 4624 4625 static void 4626 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv) 4627 { 4628 struct mlx5e_priv *priv = vpriv; 4629 struct ifnet *ifp = priv->ifp; 4630 4631 /* don't allow more IOCTLs */ 4632 priv->gone = 1; 4633 4634 /* XXX wait a bit to allow IOCTL handlers to complete */ 4635 pause("W", hz); 4636 4637 #ifdef RATELIMIT 4638 /* 4639 * The kernel can have reference(s) via the m_snd_tag's into 4640 * the ratelimit channels, and these must go away before 4641 * detaching: 4642 */ 4643 while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) { 4644 mlx5_en_err(priv->ifp, 4645 "Waiting for all ratelimit connections to terminate\n"); 4646 pause("W", hz); 4647 } 4648 #endif 4649 /* wait for all unlimited send tags to complete */ 4650 mlx5e_priv_wait_for_completion(priv, mdev->priv.eq_table.num_comp_vectors); 4651 4652 /* stop watchdog timer */ 4653 callout_drain(&priv->watchdog); 4654 4655 callout_drain(&priv->tstmp_clbr); 4656 4657 if (priv->vlan_attach != NULL) 4658 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach); 4659 if (priv->vlan_detach != NULL) 4660 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach); 4661 4662 /* make sure device gets closed */ 4663 PRIV_LOCK(priv); 4664 mlx5e_close_locked(ifp); 4665 PRIV_UNLOCK(priv); 4666 4667 /* deregister pfil */ 4668 if (priv->pfil != NULL) { 4669 pfil_head_unregister(priv->pfil); 4670 priv->pfil = NULL; 4671 } 4672 4673 /* unregister device */ 4674 ifmedia_removeall(&priv->media); 4675 ether_ifdetach(ifp); 4676 4677 mlx5e_tls_cleanup(priv); 4678 mlx5e_rl_cleanup(priv); 4679 4680 /* destroy all remaining sysctl nodes */ 4681 sysctl_ctx_free(&priv->stats.vport.ctx); 4682 sysctl_ctx_free(&priv->stats.pport.ctx); 4683 if (priv->sysctl_debug) 4684 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx); 4685 sysctl_ctx_free(&priv->sysctl_ctx); 4686 4687 mlx5_free_bfreg(priv->mdev, &priv->bfreg); 4688 mlx5_core_destroy_mkey(priv->mdev, &priv->mr); 4689 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn); 4690 mlx5_core_dealloc_pd(priv->mdev, priv->pdn); 4691 mlx5e_disable_async_events(priv); 4692 flush_workqueue(priv->wq); 4693 mlx5e_priv_static_destroy(priv, mdev->priv.eq_table.num_comp_vectors); 4694 if_free(ifp); 4695 free(priv, M_MLX5EN); 4696 } 4697 4698 #ifdef DEBUGNET 4699 static void 4700 mlx5_en_debugnet_init(struct ifnet *dev, int *nrxr, int *ncl, int *clsize) 4701 { 4702 struct mlx5e_priv *priv = if_getsoftc(dev); 4703 4704 PRIV_LOCK(priv); 4705 *nrxr = priv->params.num_channels; 4706 *ncl = DEBUGNET_MAX_IN_FLIGHT; 4707 *clsize = MLX5E_MAX_RX_BYTES; 4708 PRIV_UNLOCK(priv); 4709 } 4710 4711 static void 4712 mlx5_en_debugnet_event(struct ifnet *dev, enum debugnet_ev event) 4713 { 4714 } 4715 4716 static int 4717 mlx5_en_debugnet_transmit(struct ifnet *dev, struct mbuf *m) 4718 { 4719 struct mlx5e_priv *priv = if_getsoftc(dev); 4720 struct mlx5e_sq *sq; 4721 int err; 4722 4723 if ((if_getdrvflags(dev) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4724 IFF_DRV_RUNNING || (priv->media_status_last & IFM_ACTIVE) == 0) 4725 return (ENOENT); 4726 4727 sq = &priv->channel[0].sq[0]; 4728 4729 if (sq->running == 0) { 4730 m_freem(m); 4731 return (ENOENT); 4732 } 4733 4734 if (mlx5e_sq_xmit(sq, &m) != 0) { 4735 m_freem(m); 4736 err = ENOBUFS; 4737 } else { 4738 err = 0; 4739 } 4740 4741 if (likely(sq->doorbell.d64 != 0)) { 4742 mlx5e_tx_notify_hw(sq, sq->doorbell.d32); 4743 sq->doorbell.d64 = 0; 4744 } 4745 return (err); 4746 } 4747 4748 static int 4749 mlx5_en_debugnet_poll(struct ifnet *dev, int count) 4750 { 4751 struct mlx5e_priv *priv = if_getsoftc(dev); 4752 4753 if ((if_getdrvflags(dev) & IFF_DRV_RUNNING) == 0 || 4754 (priv->media_status_last & IFM_ACTIVE) == 0) 4755 return (ENOENT); 4756 4757 mlx5_poll_interrupts(priv->mdev); 4758 4759 return (0); 4760 } 4761 #endif /* DEBUGNET */ 4762 4763 static void * 4764 mlx5e_get_ifp(void *vpriv) 4765 { 4766 struct mlx5e_priv *priv = vpriv; 4767 4768 return (priv->ifp); 4769 } 4770 4771 static struct mlx5_interface mlx5e_interface = { 4772 .add = mlx5e_create_ifp, 4773 .remove = mlx5e_destroy_ifp, 4774 .event = mlx5e_async_event, 4775 .protocol = MLX5_INTERFACE_PROTOCOL_ETH, 4776 .get_dev = mlx5e_get_ifp, 4777 }; 4778 4779 void 4780 mlx5e_init(void) 4781 { 4782 mlx5_register_interface(&mlx5e_interface); 4783 } 4784 4785 void 4786 mlx5e_cleanup(void) 4787 { 4788 mlx5_unregister_interface(&mlx5e_interface); 4789 } 4790 4791 static void 4792 mlx5e_show_version(void __unused *arg) 4793 { 4794 4795 printf("%s", mlx5e_version); 4796 } 4797 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL); 4798 4799 module_init_order(mlx5e_init, SI_ORDER_SIXTH); 4800 module_exit_order(mlx5e_cleanup, SI_ORDER_SIXTH); 4801 4802 #if (__FreeBSD_version >= 1100000) 4803 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1); 4804 #endif 4805 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1); 4806 MODULE_VERSION(mlx5en, 1); 4807