1 /*- 2 * Copyright (c) 2015-2021 Mellanox Technologies. All rights reserved. 3 * Copyright (c) 2022 NVIDIA corporation & affiliates. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #ifndef _MLX5_EN_H_ 28 #define _MLX5_EN_H_ 29 30 #include <linux/kmod.h> 31 #include <linux/page.h> 32 #include <linux/slab.h> 33 #include <linux/if_vlan.h> 34 #include <linux/if_ether.h> 35 #include <linux/vmalloc.h> 36 #include <linux/moduleparam.h> 37 #include <linux/delay.h> 38 #include <linux/etherdevice.h> 39 #include <linux/ktime.h> 40 #include <linux/net_dim.h> 41 42 #include <netinet/in_systm.h> 43 #include <netinet/in.h> 44 #include <netinet/if_ether.h> 45 #include <netinet/ip.h> 46 #include <netinet/ip6.h> 47 #include <netinet/tcp.h> 48 #include <netinet/tcp_lro.h> 49 #include <netinet/udp.h> 50 #include <net/ethernet.h> 51 #include <net/pfil.h> 52 #include <sys/buf_ring.h> 53 #include <sys/kthread.h> 54 #include <sys/counter.h> 55 56 #ifdef RSS 57 #include <net/rss_config.h> 58 #include <netinet/in_rss.h> 59 #endif 60 61 #include <machine/bus.h> 62 63 #include <dev/mlx5/driver.h> 64 #include <dev/mlx5/qp.h> 65 #include <dev/mlx5/cq.h> 66 #include <dev/mlx5/port.h> 67 #include <dev/mlx5/vport.h> 68 #include <dev/mlx5/diagnostics.h> 69 70 #include <dev/mlx5/mlx5_core/wq.h> 71 #include <dev/mlx5/mlx5_core/transobj.h> 72 #include <dev/mlx5/mlx5_core/mlx5_core.h> 73 74 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v) 75 76 #define MLX5E_MAX_PRIORITY 8 77 78 #define MLX5E_MAX_FEC_10X_25X 4 79 #define MLX5E_MAX_FEC_50X 4 80 81 /* IEEE 802.1Qaz standard supported values */ 82 #define IEEE_8021QAZ_MAX_TCS 8 83 84 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x7 85 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa 86 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xe 87 88 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x7 89 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa 90 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xe 91 92 #define MLX5E_MAX_BUSDMA_RX_SEGS 31 93 94 #ifndef MLX5E_MAX_RX_BYTES 95 #define MLX5E_MAX_RX_BYTES MCLBYTES 96 #endif 97 98 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ 65535 99 100 #define MLX5E_DIM_DEFAULT_PROFILE 3 101 #define MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO 16 102 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 103 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 104 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 105 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 106 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 107 #define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ 0x7 108 #define MLX5E_CACHELINE_SIZE CACHE_LINE_SIZE 109 #define MLX5E_HW2SW_MTU(hwmtu) \ 110 ((hwmtu) - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 111 #define MLX5E_SW2HW_MTU(swmtu) \ 112 ((swmtu) + (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 113 #define MLX5E_SW2MB_MTU(swmtu) \ 114 (MLX5E_SW2HW_MTU(swmtu) + MLX5E_NET_IP_ALIGN) 115 #define MLX5E_MTU_MIN 72 /* Min MTU allowed by the kernel */ 116 #define MLX5E_MTU_MAX MIN(ETHERMTU_JUMBO, MJUM16BYTES) /* Max MTU of Ethernet 117 * jumbo frames */ 118 119 #define MLX5E_BUDGET_MAX 8192 /* RX and TX */ 120 #define MLX5E_RX_BUDGET_MAX 256 121 #define MLX5E_SQ_BF_BUDGET 16 122 #define MLX5E_SQ_TX_QUEUE_SIZE 4096 /* SQ drbr queue size */ 123 124 #define MLX5E_MAX_TX_NUM_TC 8 /* units */ 125 #define MLX5E_MAX_TX_HEADER 192 /* bytes */ 126 #define MLX5E_MAX_TX_PAYLOAD_SIZE 65536 /* bytes */ 127 #define MLX5E_MAX_TX_MBUF_SIZE 65536 /* bytes */ 128 #define MLX5E_MAX_TX_MBUF_FRAGS \ 129 ((MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS) - \ 130 (MLX5E_MAX_TX_HEADER / MLX5_SEND_WQE_DS) - \ 131 1 /* the maximum value of the DS counter is 0x3F and not 0x40 */) /* units */ 132 #define MLX5E_MAX_TX_INLINE \ 133 (MLX5E_MAX_TX_HEADER - sizeof(struct mlx5e_tx_wqe) + \ 134 sizeof(((struct mlx5e_tx_wqe *)0)->eth.inline_hdr_start)) /* bytes */ 135 136 #define MLX5E_100MB (100000) 137 #define MLX5E_1GB (1000000) 138 139 #define MLX5E_ZERO(ptr, field) \ 140 memset(&(ptr)->field, 0, \ 141 sizeof(*(ptr)) - __offsetof(__typeof(*(ptr)), field)) 142 143 MALLOC_DECLARE(M_MLX5EN); 144 145 struct mlx5_core_dev; 146 struct mlx5e_cq; 147 148 typedef void (mlx5e_cq_comp_t)(struct mlx5_core_cq *, struct mlx5_eqe *); 149 150 #define mlx5_en_err(_dev, format, ...) \ 151 if_printf(_dev, "ERR: ""%s:%d:(pid %d): " format, \ 152 __func__, __LINE__, curthread->td_proc->p_pid, \ 153 ##__VA_ARGS__) 154 155 #define mlx5_en_warn(_dev, format, ...) \ 156 if_printf(_dev, "WARN: ""%s:%d:(pid %d): " format, \ 157 __func__, __LINE__, curthread->td_proc->p_pid, \ 158 ##__VA_ARGS__) 159 160 #define mlx5_en_info(_dev, format, ...) \ 161 if_printf(_dev, "INFO: ""%s:%d:(pid %d): " format, \ 162 __func__, __LINE__, curthread->td_proc->p_pid, \ 163 ##__VA_ARGS__) 164 165 #define MLX5E_STATS_COUNT(a, ...) a 166 #define MLX5E_STATS_VAR(a, b, c, ...) b c; 167 #define MLX5E_STATS_COUNTER(a, b, c, ...) counter_##b##_t c; 168 #define MLX5E_STATS_DESC(a, b, c, d, e, ...) d, e, 169 170 #define MLX5E_VPORT_STATS(m) \ 171 /* HW counters */ \ 172 m(+1, u64, rx_packets, "rx_packets", "Received packets") \ 173 m(+1, u64, rx_bytes, "rx_bytes", "Received bytes") \ 174 m(+1, u64, tx_packets, "tx_packets", "Transmitted packets") \ 175 m(+1, u64, tx_bytes, "tx_bytes", "Transmitted bytes") \ 176 m(+1, u64, rx_error_packets, "rx_error_packets", "Received error packets") \ 177 m(+1, u64, rx_error_bytes, "rx_error_bytes", "Received error bytes") \ 178 m(+1, u64, tx_error_packets, "tx_error_packets", "Transmitted error packets") \ 179 m(+1, u64, tx_error_bytes, "tx_error_bytes", "Transmitted error bytes") \ 180 m(+1, u64, rx_unicast_packets, "rx_unicast_packets", "Received unicast packets") \ 181 m(+1, u64, rx_unicast_bytes, "rx_unicast_bytes", "Received unicast bytes") \ 182 m(+1, u64, tx_unicast_packets, "tx_unicast_packets", "Transmitted unicast packets") \ 183 m(+1, u64, tx_unicast_bytes, "tx_unicast_bytes", "Transmitted unicast bytes") \ 184 m(+1, u64, rx_multicast_packets, "rx_multicast_packets", "Received multicast packets") \ 185 m(+1, u64, rx_multicast_bytes, "rx_multicast_bytes", "Received multicast bytes") \ 186 m(+1, u64, tx_multicast_packets, "tx_multicast_packets", "Transmitted multicast packets") \ 187 m(+1, u64, tx_multicast_bytes, "tx_multicast_bytes", "Transmitted multicast bytes") \ 188 m(+1, u64, rx_broadcast_packets, "rx_broadcast_packets", "Received broadcast packets") \ 189 m(+1, u64, rx_broadcast_bytes, "rx_broadcast_bytes", "Received broadcast bytes") \ 190 m(+1, u64, tx_broadcast_packets, "tx_broadcast_packets", "Transmitted broadcast packets") \ 191 m(+1, u64, tx_broadcast_bytes, "tx_broadcast_bytes", "Transmitted broadcast bytes") \ 192 m(+1, u64, rx_out_of_buffer, "rx_out_of_buffer", "Receive out of buffer, no recv wqes events") \ 193 /* SW counters */ \ 194 m(+1, u64, tso_packets, "tso_packets", "Transmitted TSO packets") \ 195 m(+1, u64, tso_bytes, "tso_bytes", "Transmitted TSO bytes") \ 196 m(+1, u64, lro_packets, "lro_packets", "Received LRO packets") \ 197 m(+1, u64, lro_bytes, "lro_bytes", "Received LRO bytes") \ 198 m(+1, u64, sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 199 m(+1, u64, sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 200 m(+1, u64, rx_csum_good, "rx_csum_good", "Received checksum valid packets") \ 201 m(+1, u64, rx_csum_none, "rx_csum_none", "Received no checksum packets") \ 202 m(+1, u64, tx_csum_offload, "tx_csum_offload", "Transmit checksum offload packets") \ 203 m(+1, u64, tx_queue_dropped, "tx_queue_dropped", "Transmit queue dropped") \ 204 m(+1, u64, tx_defragged, "tx_defragged", "Transmit queue defragged") \ 205 m(+1, u64, rx_wqe_err, "rx_wqe_err", "Receive WQE errors") \ 206 m(+1, u64, tx_jumbo_packets, "tx_jumbo_packets", "TX packets greater than 1518 octets") \ 207 m(+1, u64, rx_steer_missed_packets, "rx_steer_missed_packets", "RX packets dropped by steering rule(s)") \ 208 m(+1, u64, rx_decrypted_ok_packets, "rx_decrypted_ok_packets", "RX packets successfully decrypted by steering rule(s)") \ 209 m(+1, u64, rx_decrypted_error_packets, "rx_decrypted_error_packets", "RX packets not decrypted by steering rule(s)") 210 211 #define MLX5E_VPORT_STATS_NUM (0 MLX5E_VPORT_STATS(MLX5E_STATS_COUNT)) 212 213 struct mlx5e_vport_stats { 214 struct sysctl_ctx_list ctx; 215 u64 arg [0]; 216 MLX5E_VPORT_STATS(MLX5E_STATS_VAR) 217 }; 218 219 #define MLX5E_PPORT_IEEE802_3_STATS(m) \ 220 m(+1, u64, frames_tx, "frames_tx", "Frames transmitted") \ 221 m(+1, u64, frames_rx, "frames_rx", "Frames received") \ 222 m(+1, u64, check_seq_err, "check_seq_err", "Sequence errors") \ 223 m(+1, u64, alignment_err, "alignment_err", "Alignment errors") \ 224 m(+1, u64, octets_tx, "octets_tx", "Bytes transmitted") \ 225 m(+1, u64, octets_received, "octets_received", "Bytes received") \ 226 m(+1, u64, multicast_xmitted, "multicast_xmitted", "Multicast transmitted") \ 227 m(+1, u64, broadcast_xmitted, "broadcast_xmitted", "Broadcast transmitted") \ 228 m(+1, u64, multicast_rx, "multicast_rx", "Multicast received") \ 229 m(+1, u64, broadcast_rx, "broadcast_rx", "Broadcast received") \ 230 m(+1, u64, in_range_len_errors, "in_range_len_errors", "In range length errors") \ 231 m(+1, u64, out_of_range_len, "out_of_range_len", "Out of range length errors") \ 232 m(+1, u64, too_long_errors, "too_long_errors", "Too long errors") \ 233 m(+1, u64, symbol_err, "symbol_err", "Symbol errors") \ 234 m(+1, u64, mac_control_tx, "mac_control_tx", "MAC control transmitted") \ 235 m(+1, u64, mac_control_rx, "mac_control_rx", "MAC control received") \ 236 m(+1, u64, unsupported_op_rx, "unsupported_op_rx", "Unsupported operation received") \ 237 m(+1, u64, pause_ctrl_rx, "pause_ctrl_rx", "Pause control received") \ 238 m(+1, u64, pause_ctrl_tx, "pause_ctrl_tx", "Pause control transmitted") 239 240 #define MLX5E_PPORT_RFC2819_STATS(m) \ 241 m(+1, u64, drop_events, "drop_events", "Dropped events") \ 242 m(+1, u64, octets, "octets", "Octets") \ 243 m(+1, u64, pkts, "pkts", "Packets") \ 244 m(+1, u64, broadcast_pkts, "broadcast_pkts", "Broadcast packets") \ 245 m(+1, u64, multicast_pkts, "multicast_pkts", "Multicast packets") \ 246 m(+1, u64, crc_align_errors, "crc_align_errors", "CRC alignment errors") \ 247 m(+1, u64, undersize_pkts, "undersize_pkts", "Undersized packets") \ 248 m(+1, u64, oversize_pkts, "oversize_pkts", "Oversized packets") \ 249 m(+1, u64, fragments, "fragments", "Fragments") \ 250 m(+1, u64, jabbers, "jabbers", "Jabbers") \ 251 m(+1, u64, collisions, "collisions", "Collisions") 252 253 #define MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 254 m(+1, u64, p64octets, "p64octets", "Bytes") \ 255 m(+1, u64, p65to127octets, "p65to127octets", "Bytes") \ 256 m(+1, u64, p128to255octets, "p128to255octets", "Bytes") \ 257 m(+1, u64, p256to511octets, "p256to511octets", "Bytes") \ 258 m(+1, u64, p512to1023octets, "p512to1023octets", "Bytes") \ 259 m(+1, u64, p1024to1518octets, "p1024to1518octets", "Bytes") \ 260 m(+1, u64, p1519to2047octets, "p1519to2047octets", "Bytes") \ 261 m(+1, u64, p2048to4095octets, "p2048to4095octets", "Bytes") \ 262 m(+1, u64, p4096to8191octets, "p4096to8191octets", "Bytes") \ 263 m(+1, u64, p8192to10239octets, "p8192to10239octets", "Bytes") 264 265 #define MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 266 m(+1, u64, in_octets, "in_octets", "In octets") \ 267 m(+1, u64, in_ucast_pkts, "in_ucast_pkts", "In unicast packets") \ 268 m(+1, u64, in_discards, "in_discards", "In discards") \ 269 m(+1, u64, in_errors, "in_errors", "In errors") \ 270 m(+1, u64, in_unknown_protos, "in_unknown_protos", "In unknown protocols") \ 271 m(+1, u64, out_octets, "out_octets", "Out octets") \ 272 m(+1, u64, out_ucast_pkts, "out_ucast_pkts", "Out unicast packets") \ 273 m(+1, u64, out_discards, "out_discards", "Out discards") \ 274 m(+1, u64, out_errors, "out_errors", "Out errors") \ 275 m(+1, u64, in_multicast_pkts, "in_multicast_pkts", "In multicast packets") \ 276 m(+1, u64, in_broadcast_pkts, "in_broadcast_pkts", "In broadcast packets") \ 277 m(+1, u64, out_multicast_pkts, "out_multicast_pkts", "Out multicast packets") \ 278 m(+1, u64, out_broadcast_pkts, "out_broadcast_pkts", "Out broadcast packets") 279 280 #define MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(m) \ 281 m(+1, u64, port_transmit_wait, "port_transmit_wait", "Port transmit wait") \ 282 m(+1, u64, ecn_marked, "ecn_marked", "ECN marked") \ 283 m(+1, u64, no_buffer_discard_mc, "no_buffer_discard_mc", "No buffer discard mc") \ 284 m(+1, u64, rx_ebp, "rx_ebp", "RX EBP") \ 285 m(+1, u64, tx_ebp, "tx_ebp", "TX EBP") \ 286 m(+1, u64, rx_buffer_almost_full, "rx_buffer_almost_full", "RX buffer almost full") \ 287 m(+1, u64, rx_buffer_full, "rx_buffer_full", "RX buffer full") \ 288 m(+1, u64, rx_icrc_encapsulated, "rx_icrc_encapsulated", "RX ICRC encapsulated") \ 289 m(+1, u64, ex_reserved_0, "ex_reserved_0", "Reserved") \ 290 m(+1, u64, ex_reserved_1, "ex_reserved_1", "Reserved") \ 291 m(+1, u64, tx_stat_p64octets, "tx_stat_p64octets", "Bytes") \ 292 m(+1, u64, tx_stat_p65to127octets, "tx_stat_p65to127octets", "Bytes") \ 293 m(+1, u64, tx_stat_p128to255octets, "tx_stat_p128to255octets", "Bytes") \ 294 m(+1, u64, tx_stat_p256to511octets, "tx_stat_p256to511octets", "Bytes") \ 295 m(+1, u64, tx_stat_p512to1023octets, "tx_stat_p512to1023octets", "Bytes") \ 296 m(+1, u64, tx_stat_p1024to1518octets, "tx_stat_p1024to1518octets", "Bytes") \ 297 m(+1, u64, tx_stat_p1519to2047octets, "tx_stat_p1519to2047octets", "Bytes") \ 298 m(+1, u64, tx_stat_p2048to4095octets, "tx_stat_p2048to4095octets", "Bytes") \ 299 m(+1, u64, tx_stat_p4096to8191octets, "tx_stat_p4096to8191octets", "Bytes") \ 300 m(+1, u64, tx_stat_p8192to10239octets, "tx_stat_p8192to10239octets", "Bytes") 301 302 #define MLX5E_PPORT_STATISTICAL_DEBUG(m) \ 303 m(+1, u64, phy_time_since_last_clear, "phy_time_since_last_clear", \ 304 "Time since last clear in milliseconds") \ 305 m(+1, u64, phy_received_bits, "phy_received_bits", \ 306 "Total amount of traffic received in bits before error correction") \ 307 m(+1, u64, phy_symbol_errors, "phy_symbol_errors", \ 308 "Total number of symbol errors before error correction") \ 309 m(+1, u64, phy_corrected_bits, "phy_corrected_bits", \ 310 "Total number of corrected bits ") \ 311 m(+1, u64, phy_corrected_bits_lane0, "phy_corrected_bits_lane0", \ 312 "Total number of corrected bits for lane 0") \ 313 m(+1, u64, phy_corrected_bits_lane1, "phy_corrected_bits_lane1", \ 314 "Total number of corrected bits for lane 1") \ 315 m(+1, u64, phy_corrected_bits_lane2, "phy_corrected_bits_lane2", \ 316 "Total number of corrected bits for lane 2") \ 317 m(+1, u64, phy_corrected_bits_lane3, "phy_corrected_bits_lane3", \ 318 "Total number of corrected bits for lane 3") 319 320 #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \ 321 m(+1, u64, time_since_last_clear, "time_since_last_clear", \ 322 "Time since the last counters clear event (msec)") \ 323 m(+1, u64, symbol_errors, "symbol_errors", "Symbol errors") \ 324 m(+1, u64, sync_headers_errors, "sync_headers_errors", \ 325 "Sync header error counter") \ 326 m(+1, u64, bip_errors_lane0, "edpl_bip_errors_lane0", \ 327 "Indicates the number of PRBS errors on lane 0") \ 328 m(+1, u64, bip_errors_lane1, "edpl_bip_errors_lane1", \ 329 "Indicates the number of PRBS errors on lane 1") \ 330 m(+1, u64, bip_errors_lane2, "edpl_bip_errors_lane2", \ 331 "Indicates the number of PRBS errors on lane 2") \ 332 m(+1, u64, bip_errors_lane3, "edpl_bip_errors_lane3", \ 333 "Indicates the number of PRBS errors on lane 3") \ 334 m(+1, u64, fc_corrected_blocks_lane0, "fc_corrected_blocks_lane0", \ 335 "FEC correctable block counter lane 0") \ 336 m(+1, u64, fc_corrected_blocks_lane1, "fc_corrected_blocks_lane1", \ 337 "FEC correctable block counter lane 1") \ 338 m(+1, u64, fc_corrected_blocks_lane2, "fc_corrected_blocks_lane2", \ 339 "FEC correctable block counter lane 2") \ 340 m(+1, u64, fc_corrected_blocks_lane3, "fc_corrected_blocks_lane3", \ 341 "FEC correctable block counter lane 3") \ 342 m(+1, u64, rs_corrected_blocks, "rs_corrected_blocks", \ 343 "FEC correcable block counter") \ 344 m(+1, u64, rs_uncorrectable_blocks, "rs_uncorrectable_blocks", \ 345 "FEC uncorrecable block counter") \ 346 m(+1, u64, rs_no_errors_blocks, "rs_no_errors_blocks", \ 347 "The number of RS-FEC blocks received that had no errors") \ 348 m(+1, u64, rs_single_error_blocks, "rs_single_error_blocks", \ 349 "The number of corrected RS-FEC blocks received that had" \ 350 "exactly 1 error symbol") \ 351 m(+1, u64, rs_corrected_symbols_total, "rs_corrected_symbols_total", \ 352 "Port FEC corrected symbol counter") \ 353 m(+1, u64, rs_corrected_symbols_lane0, "rs_corrected_symbols_lane0", \ 354 "FEC corrected symbol counter lane 0") \ 355 m(+1, u64, rs_corrected_symbols_lane1, "rs_corrected_symbols_lane1", \ 356 "FEC corrected symbol counter lane 1") \ 357 m(+1, u64, rs_corrected_symbols_lane2, "rs_corrected_symbols_lane2", \ 358 "FEC corrected symbol counter lane 2") \ 359 m(+1, u64, rs_corrected_symbols_lane3, "rs_corrected_symbols_lane3", \ 360 "FEC corrected symbol counter lane 3") 361 362 /* Per priority statistics for PFC */ 363 #define MLX5E_PPORT_PER_PRIO_STATS_SUB(m,n,p) \ 364 m(n, p, +1, u64, rx_octets, "rx_octets", "Received octets") \ 365 m(n, p, +1, u64, rx_uc_frames, "rx_uc_frames", "Received unicast frames") \ 366 m(n, p, +1, u64, rx_mc_frames, "rx_mc_frames", "Received multicast frames") \ 367 m(n, p, +1, u64, rx_bc_frames, "rx_bc_frames", "Received broadcast frames") \ 368 m(n, p, +1, u64, rx_frames, "rx_frames", "Received frames") \ 369 m(n, p, +1, u64, tx_octets, "tx_octets", "Transmitted octets") \ 370 m(n, p, +1, u64, tx_uc_frames, "tx_uc_frames", "Transmitted unicast frames") \ 371 m(n, p, +1, u64, tx_mc_frames, "tx_mc_frames", "Transmitted multicast frames") \ 372 m(n, p, +1, u64, tx_bc_frames, "tx_bc_frames", "Transmitted broadcast frames") \ 373 m(n, p, +1, u64, tx_frames, "tx_frames", "Transmitted frames") \ 374 m(n, p, +1, u64, rx_pause, "rx_pause", "Received pause frames") \ 375 m(n, p, +1, u64, rx_pause_duration, "rx_pause_duration", \ 376 "Received pause duration") \ 377 m(n, p, +1, u64, tx_pause, "tx_pause", "Transmitted pause frames") \ 378 m(n, p, +1, u64, tx_pause_duration, "tx_pause_duration", \ 379 "Transmitted pause duration") \ 380 m(n, p, +1, u64, rx_pause_transition, "rx_pause_transition", \ 381 "Received pause transitions") \ 382 m(n, p, +1, u64, rx_discards, "rx_discards", "Discarded received frames") \ 383 m(n, p, +1, u64, device_stall_minor_watermark, \ 384 "device_stall_minor_watermark", "Device stall minor watermark") \ 385 m(n, p, +1, u64, device_stall_critical_watermark, \ 386 "device_stall_critical_watermark", "Device stall critical watermark") 387 388 #define MLX5E_PPORT_PER_PRIO_STATS_PREFIX(m,p,c,t,f,s,d) \ 389 m(c, t, pri_##p##_##f, "prio" #p "_" s, "Priority " #p " - " d) 390 391 #define MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO 8 392 393 #define MLX5E_PPORT_PER_PRIO_STATS(m) \ 394 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,0) \ 395 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,1) \ 396 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,2) \ 397 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,3) \ 398 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,4) \ 399 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,5) \ 400 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,6) \ 401 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,7) 402 403 #define MLX5E_PCIE_PERFORMANCE_COUNTERS_64(m) \ 404 m(+1, u64, life_time_counter_high, "life_time_counter", \ 405 "Life time counter.", pcie_perf_counters) \ 406 m(+1, u64, tx_overflow_buffer_pkt, "tx_overflow_buffer_pkt", \ 407 "The number of packets dropped due to lack of PCIe buffers " \ 408 "in receive path from NIC port toward the hosts.", \ 409 pcie_perf_counters) \ 410 m(+1, u64, tx_overflow_buffer_marked_pkt, \ 411 "tx_overflow_buffer_marked_pkt", \ 412 "The number of packets marked due to lack of PCIe buffers " \ 413 "in receive path from NIC port toward the hosts.", \ 414 pcie_perf_counters) 415 416 #define MLX5E_PCIE_PERFORMANCE_COUNTERS_32(m) \ 417 m(+1, u64, rx_errors, "rx_errors", \ 418 "Number of transitions to recovery due to Framing " \ 419 "errors and CRC errors.", pcie_perf_counters) \ 420 m(+1, u64, tx_errors, "tx_errors", "Number of transitions " \ 421 "to recovery due to EIEOS and TS errors.", pcie_perf_counters) \ 422 m(+1, u64, l0_to_recovery_eieos, "l0_to_recovery_eieos", "Number of " \ 423 "transitions to recovery due to getting EIEOS.", pcie_perf_counters)\ 424 m(+1, u64, l0_to_recovery_ts, "l0_to_recovery_ts", "Number of " \ 425 "transitions to recovery due to getting TS.", pcie_perf_counters) \ 426 m(+1, u64, l0_to_recovery_framing, "l0_to_recovery_framing", "Number "\ 427 "of transitions to recovery due to identifying framing " \ 428 "errors at gen3/4.", pcie_perf_counters) \ 429 m(+1, u64, l0_to_recovery_retrain, "l0_to_recovery_retrain", \ 430 "Number of transitions to recovery due to link retrain request " \ 431 "from data link.", pcie_perf_counters) \ 432 m(+1, u64, crc_error_dllp, "crc_error_dllp", "Number of transitions " \ 433 "to recovery due to identifying CRC DLLP errors.", \ 434 pcie_perf_counters) \ 435 m(+1, u64, crc_error_tlp, "crc_error_tlp", "Number of transitions to "\ 436 "recovery due to identifying CRC TLP errors.", pcie_perf_counters) \ 437 m(+1, u64, outbound_stalled_reads, "outbound_stalled_reads", \ 438 "The percentage of time within the last second that the NIC had " \ 439 "outbound non-posted read requests but could not perform the " \ 440 "operation due to insufficient non-posted credits.", \ 441 pcie_perf_counters) \ 442 m(+1, u64, outbound_stalled_writes, "outbound_stalled_writes", \ 443 "The percentage of time within the last second that the NIC had " \ 444 "outbound posted writes requests but could not perform the " \ 445 "operation due to insufficient posted credits.", \ 446 pcie_perf_counters) \ 447 m(+1, u64, outbound_stalled_reads_events, \ 448 "outbound_stalled_reads_events", "The number of events where " \ 449 "outbound_stalled_reads was above a threshold.", \ 450 pcie_perf_counters) \ 451 m(+1, u64, outbound_stalled_writes_events, \ 452 "outbound_stalled_writes_events", \ 453 "The number of events where outbound_stalled_writes was above " \ 454 "a threshold.", pcie_perf_counters) 455 456 #define MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(m) \ 457 m(+1, u64, time_to_boot_image_start, "time_to_boot_image_start", \ 458 "Time from start until FW boot image starts running in usec.", \ 459 pcie_timers_states) \ 460 m(+1, u64, time_to_link_image, "time_to_link_image", \ 461 "Time from start until FW pci_link image starts running in usec.", \ 462 pcie_timers_states) \ 463 m(+1, u64, calibration_time, "calibration_time", \ 464 "Time it took FW to do calibration in usec.", \ 465 pcie_timers_states) \ 466 m(+1, u64, time_to_first_perst, "time_to_first_perst", \ 467 "Time form start until FW handle first perst. in usec.", \ 468 pcie_timers_states) \ 469 m(+1, u64, time_to_detect_state, "time_to_detect_state", \ 470 "Time from start until first transition to LTSSM.Detect_Q in usec", \ 471 pcie_timers_states) \ 472 m(+1, u64, time_to_l0, "time_to_l0", \ 473 "Time from start until first transition to LTSSM.L0 in usec", \ 474 pcie_timers_states) \ 475 m(+1, u64, time_to_crs_en, "time_to_crs_en", \ 476 "Time from start until crs is enabled in usec", \ 477 pcie_timers_states) \ 478 m(+1, u64, time_to_plastic_image_start, "time_to_plastic_image_start",\ 479 "Time form start until FW plastic image starts running in usec.", \ 480 pcie_timers_states) \ 481 m(+1, u64, time_to_iron_image_start, "time_to_iron_image_start", \ 482 "Time form start until FW iron image starts running in usec.", \ 483 pcie_timers_states) \ 484 m(+1, u64, perst_handler, "perst_handler", \ 485 "Number of persts arrived.", pcie_timers_states) \ 486 m(+1, u64, times_in_l1, "times_in_l1", \ 487 "Number of times LTSSM entered L1 flow.", pcie_timers_states) \ 488 m(+1, u64, times_in_l23, "times_in_l23", \ 489 "Number of times LTSSM entered L23 flow.", pcie_timers_states) \ 490 m(+1, u64, dl_down, "dl_down", \ 491 "Number of moves for DL_active to DL_down.", pcie_timers_states) \ 492 m(+1, u64, config_cycle1usec, "config_cycle1usec", \ 493 "Number of configuration requests that firmware " \ 494 "handled in less than 1 usec.", pcie_timers_states) \ 495 m(+1, u64, config_cycle2to7usec, "config_cycle2to7usec", \ 496 "Number of configuration requests that firmware " \ 497 "handled within 2 to 7 usec.", pcie_timers_states) \ 498 m(+1, u64, config_cycle8to15usec, "config_cycle8to15usec", \ 499 "Number of configuration requests that firmware " \ 500 "handled within 8 to 15 usec.", pcie_timers_states) \ 501 m(+1, u64, config_cycle16to63usec, "config_cycle16to63usec", \ 502 "Number of configuration requests that firmware " \ 503 "handled within 16 to 63 usec.", pcie_timers_states) \ 504 m(+1, u64, config_cycle64usec, "config_cycle64usec", \ 505 "Number of configuration requests that firmware " \ 506 "handled took more than 64 usec.", pcie_timers_states) \ 507 m(+1, u64, correctable_err_msg_sent, "correctable_err_msg_sent", \ 508 "Number of correctable error messages sent.", pcie_timers_states) \ 509 m(+1, u64, non_fatal_err_msg_sent, "non_fatal_err_msg_sent", \ 510 "Number of non-Fatal error msg sent.", pcie_timers_states) \ 511 m(+1, u64, fatal_err_msg_sent, "fatal_err_msg_sent", \ 512 "Number of fatal error msg sent.", pcie_timers_states) 513 514 #define MLX5E_PCIE_LANE_COUNTERS_32(m) \ 515 m(+1, u64, error_counter_lane0, "error_counter_lane0", \ 516 "Error counter for PCI lane 0", pcie_lanes_counters) \ 517 m(+1, u64, error_counter_lane1, "error_counter_lane1", \ 518 "Error counter for PCI lane 1", pcie_lanes_counters) \ 519 m(+1, u64, error_counter_lane2, "error_counter_lane2", \ 520 "Error counter for PCI lane 2", pcie_lanes_counters) \ 521 m(+1, u64, error_counter_lane3, "error_counter_lane3", \ 522 "Error counter for PCI lane 3", pcie_lanes_counters) \ 523 m(+1, u64, error_counter_lane4, "error_counter_lane4", \ 524 "Error counter for PCI lane 4", pcie_lanes_counters) \ 525 m(+1, u64, error_counter_lane5, "error_counter_lane5", \ 526 "Error counter for PCI lane 5", pcie_lanes_counters) \ 527 m(+1, u64, error_counter_lane6, "error_counter_lane6", \ 528 "Error counter for PCI lane 6", pcie_lanes_counters) \ 529 m(+1, u64, error_counter_lane7, "error_counter_lane7", \ 530 "Error counter for PCI lane 7", pcie_lanes_counters) \ 531 m(+1, u64, error_counter_lane8, "error_counter_lane8", \ 532 "Error counter for PCI lane 8", pcie_lanes_counters) \ 533 m(+1, u64, error_counter_lane9, "error_counter_lane9", \ 534 "Error counter for PCI lane 9", pcie_lanes_counters) \ 535 m(+1, u64, error_counter_lane10, "error_counter_lane10", \ 536 "Error counter for PCI lane 10", pcie_lanes_counters) \ 537 m(+1, u64, error_counter_lane11, "error_counter_lane11", \ 538 "Error counter for PCI lane 11", pcie_lanes_counters) \ 539 m(+1, u64, error_counter_lane12, "error_counter_lane12", \ 540 "Error counter for PCI lane 12", pcie_lanes_counters) \ 541 m(+1, u64, error_counter_lane13, "error_counter_lane13", \ 542 "Error counter for PCI lane 13", pcie_lanes_counters) \ 543 m(+1, u64, error_counter_lane14, "error_counter_lane14", \ 544 "Error counter for PCI lane 14", pcie_lanes_counters) \ 545 m(+1, u64, error_counter_lane15, "error_counter_lane15", \ 546 "Error counter for PCI lane 15", pcie_lanes_counters) 547 548 /* 549 * Make sure to update mlx5e_update_pport_counters() 550 * when adding a new MLX5E_PPORT_STATS block 551 */ 552 #define MLX5E_PPORT_STATS(m) \ 553 MLX5E_PPORT_PER_PRIO_STATS(m) \ 554 MLX5E_PPORT_IEEE802_3_STATS(m) \ 555 MLX5E_PPORT_RFC2819_STATS(m) 556 557 #define MLX5E_PORT_STATS_DEBUG(m) \ 558 MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 559 MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 560 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \ 561 MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(m) \ 562 MLX5E_PPORT_STATISTICAL_DEBUG(m) \ 563 MLX5E_PCIE_PERFORMANCE_COUNTERS_64(m) \ 564 MLX5E_PCIE_PERFORMANCE_COUNTERS_32(m) \ 565 MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(m) \ 566 MLX5E_PCIE_LANE_COUNTERS_32(m) 567 568 #define MLX5E_PPORT_IEEE802_3_STATS_NUM \ 569 (0 MLX5E_PPORT_IEEE802_3_STATS(MLX5E_STATS_COUNT)) 570 #define MLX5E_PPORT_RFC2819_STATS_NUM \ 571 (0 MLX5E_PPORT_RFC2819_STATS(MLX5E_STATS_COUNT)) 572 #define MLX5E_PPORT_STATS_NUM \ 573 (0 MLX5E_PPORT_STATS(MLX5E_STATS_COUNT)) 574 575 #define MLX5E_PPORT_PER_PRIO_STATS_NUM \ 576 (0 MLX5E_PPORT_PER_PRIO_STATS(MLX5E_STATS_COUNT)) 577 #define MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM \ 578 (0 MLX5E_PPORT_RFC2819_STATS_DEBUG(MLX5E_STATS_COUNT)) 579 #define MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM \ 580 (0 MLX5E_PPORT_RFC2863_STATS_DEBUG(MLX5E_STATS_COUNT)) 581 #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM \ 582 (0 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(MLX5E_STATS_COUNT)) 583 #define MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM \ 584 (0 MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(MLX5E_STATS_COUNT)) 585 #define MLX5E_PPORT_STATISTICAL_DEBUG_NUM \ 586 (0 MLX5E_PPORT_STATISTICAL_DEBUG(MLX5E_STATS_COUNT)) 587 #define MLX5E_PORT_STATS_DEBUG_NUM \ 588 (0 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_COUNT)) 589 590 struct mlx5e_pport_stats { 591 struct sysctl_ctx_list ctx; 592 u64 arg [0]; 593 MLX5E_PPORT_STATS(MLX5E_STATS_VAR) 594 }; 595 596 struct mlx5e_port_stats_debug { 597 struct sysctl_ctx_list ctx; 598 u64 arg [0]; 599 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_VAR) 600 }; 601 602 #define MLX5E_RQ_STATS(m) \ 603 m(+1, u64, packets, "packets", "Received packets") \ 604 m(+1, u64, bytes, "bytes", "Received bytes") \ 605 m(+1, u64, csum_none, "csum_none", "Received packets") \ 606 m(+1, u64, lro_packets, "lro_packets", "Received LRO packets") \ 607 m(+1, u64, lro_bytes, "lro_bytes", "Received LRO bytes") \ 608 m(+1, u64, sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 609 m(+1, u64, sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 610 m(+1, u64, wqe_err, "wqe_err", "Received packets") \ 611 m(+1, u64, decrypted_ok_packets, "decrypted_ok_packets", "Received packets successfully decrypted by steering rule(s)") \ 612 m(+1, u64, decrypted_error_packets, "decrypted_error_packets", "Received packets not decrypted by steering rule(s)") 613 614 #define MLX5E_RQ_STATS_NUM (0 MLX5E_RQ_STATS(MLX5E_STATS_COUNT)) 615 616 struct mlx5e_rq_stats { 617 struct sysctl_ctx_list ctx; 618 u64 arg [0]; 619 MLX5E_RQ_STATS(MLX5E_STATS_VAR) 620 }; 621 622 #define MLX5E_SQ_STATS(m) \ 623 m(+1, u64, packets, "packets", "Transmitted packets") \ 624 m(+1, u64, bytes, "bytes", "Transmitted bytes") \ 625 m(+1, u64, tso_packets, "tso_packets", "Transmitted packets") \ 626 m(+1, u64, tso_bytes, "tso_bytes", "Transmitted bytes") \ 627 m(+1, u64, csum_offload_none, "csum_offload_none", "Transmitted packets") \ 628 m(+1, u64, defragged, "defragged", "Transmitted packets") \ 629 m(+1, u64, dropped, "dropped", "Transmitted packets") \ 630 m(+1, u64, enobuf, "enobuf", "Transmitted packets") \ 631 m(+1, u64, cqe_err, "cqe_err", "Transmit CQE errors") \ 632 m(+1, u64, nop, "nop", "Transmitted packets") 633 634 #define MLX5E_SQ_STATS_NUM (0 MLX5E_SQ_STATS(MLX5E_STATS_COUNT)) 635 636 struct mlx5e_sq_stats { 637 struct sysctl_ctx_list ctx; 638 u64 arg [0]; 639 MLX5E_SQ_STATS(MLX5E_STATS_VAR) 640 }; 641 642 struct mlx5e_stats { 643 struct mlx5e_vport_stats vport; 644 struct mlx5e_pport_stats pport; 645 struct mlx5e_port_stats_debug port_stats_debug; 646 }; 647 648 struct mlx5e_rq_param { 649 u32 rqc [MLX5_ST_SZ_DW(rqc)]; 650 struct mlx5_wq_param wq; 651 }; 652 653 struct mlx5e_sq_param { 654 u32 sqc [MLX5_ST_SZ_DW(sqc)]; 655 struct mlx5_wq_param wq; 656 }; 657 658 struct mlx5e_cq_param { 659 u32 cqc [MLX5_ST_SZ_DW(cqc)]; 660 struct mlx5_wq_param wq; 661 }; 662 663 struct mlx5e_params { 664 u8 log_sq_size; 665 u8 log_rq_size; 666 u16 num_channels; 667 u8 default_vlan_prio; 668 u8 num_tc; 669 u8 rx_cq_moderation_mode; 670 u8 tx_cq_moderation_mode; 671 u16 rx_cq_moderation_usec; 672 u16 rx_cq_moderation_pkts; 673 u16 tx_cq_moderation_usec; 674 u16 tx_cq_moderation_pkts; 675 bool hw_lro_en; 676 bool cqe_zipping_en; 677 u32 lro_wqe_sz; 678 u16 rx_hash_log_tbl_sz; 679 u32 tx_pauseframe_control __aligned(4); 680 u32 rx_pauseframe_control __aligned(4); 681 u16 tx_max_inline; 682 u8 tx_min_inline_mode; 683 u8 tx_priority_flow_control; 684 u8 rx_priority_flow_control; 685 u8 channels_rsss; 686 }; 687 688 #define MLX5E_PARAMS(m) \ 689 m(+1, u64, tx_queue_size_max, "tx_queue_size_max", "Max send queue size") \ 690 m(+1, u64, rx_queue_size_max, "rx_queue_size_max", "Max receive queue size") \ 691 m(+1, u64, tx_queue_size, "tx_queue_size", "Default send queue size") \ 692 m(+1, u64, rx_queue_size, "rx_queue_size", "Default receive queue size") \ 693 m(+1, u64, channels, "channels", "Default number of channels") \ 694 m(+1, u64, channels_rsss, "channels_rsss", "Default channels receive side scaling stride") \ 695 m(+1, u64, coalesce_usecs_max, "coalesce_usecs_max", "Maximum usecs for joining packets") \ 696 m(+1, u64, coalesce_pkts_max, "coalesce_pkts_max", "Maximum packets to join") \ 697 m(+1, u64, rx_coalesce_usecs, "rx_coalesce_usecs", "Limit in usec for joining rx packets") \ 698 m(+1, u64, rx_coalesce_pkts, "rx_coalesce_pkts", "Maximum number of rx packets to join") \ 699 m(+1, u64, rx_coalesce_mode, "rx_coalesce_mode", "0: EQE fixed mode 1: CQE fixed mode 2: EQE auto mode 3: CQE auto mode") \ 700 m(+1, u64, tx_coalesce_usecs, "tx_coalesce_usecs", "Limit in usec for joining tx packets") \ 701 m(+1, u64, tx_coalesce_pkts, "tx_coalesce_pkts", "Maximum number of tx packets to join") \ 702 m(+1, u64, tx_coalesce_mode, "tx_coalesce_mode", "0: EQE mode 1: CQE mode") \ 703 m(+1, u64, tx_completion_fact, "tx_completion_fact", "1..MAX: Completion event ratio") \ 704 m(+1, u64, tx_completion_fact_max, "tx_completion_fact_max", "Maximum completion event ratio") \ 705 m(+1, u64, hw_lro, "hw_lro", "set to enable hw_lro") \ 706 m(+1, u64, cqe_zipping, "cqe_zipping", "0 : CQE zipping disabled") \ 707 m(+1, u64, modify_tx_dma, "modify_tx_dma", "0: Enable TX 1: Disable TX") \ 708 m(+1, u64, modify_rx_dma, "modify_rx_dma", "0: Enable RX 1: Disable RX") \ 709 m(+1, u64, diag_pci_enable, "diag_pci_enable", "0: Disabled 1: Enabled") \ 710 m(+1, u64, diag_general_enable, "diag_general_enable", "0: Disabled 1: Enabled") \ 711 m(+1, u64, hw_mtu, "hw_mtu", "Current hardware MTU value") \ 712 m(+1, u64, mc_local_lb, "mc_local_lb", "0: Local multicast loopback enabled 1: Disabled") \ 713 m(+1, u64, uc_local_lb, "uc_local_lb", "0: Local unicast loopback enabled 1: Disabled") \ 714 m(+1, s64, irq_cpu_base, "irq_cpu_base", "-1: Don't bind IRQ 0..NCPU-1: select this base CPU when binding IRQs") \ 715 m(+1, s64, irq_cpu_stride, "irq_cpu_stride", "0..NCPU-1: Distance between IRQ vectors when binding them") 716 717 #define MLX5E_PARAMS_NUM (0 MLX5E_PARAMS(MLX5E_STATS_COUNT)) 718 719 struct mlx5e_params_ethtool { 720 u64 arg [0]; 721 MLX5E_PARAMS(MLX5E_STATS_VAR) 722 u64 max_bw_value[IEEE_8021QAZ_MAX_TCS]; 723 u8 max_bw_share[IEEE_8021QAZ_MAX_TCS]; 724 u8 prio_tc[MLX5E_MAX_PRIORITY]; 725 u8 dscp2prio[MLX5_MAX_SUPPORTED_DSCP]; 726 u8 trust_state; 727 u8 fec_mask_10x_25x[MLX5E_MAX_FEC_10X_25X]; 728 u16 fec_mask_50x[MLX5E_MAX_FEC_50X]; 729 u8 fec_avail_10x_25x[MLX5E_MAX_FEC_10X_25X]; 730 u16 fec_avail_50x[MLX5E_MAX_FEC_50X]; 731 u32 fec_mode_active; 732 u32 hw_mtu_msb; 733 s32 hw_val_temp[MLX5_MAX_TEMPERATURE]; 734 u32 hw_num_temp; 735 }; 736 737 struct mlx5e_cq { 738 /* data path - accessed per cqe */ 739 struct mlx5_cqwq wq; 740 741 /* data path - accessed per HW polling */ 742 struct mlx5_core_cq mcq; 743 744 /* control */ 745 struct mlx5e_priv *priv; 746 struct mlx5_wq_ctrl wq_ctrl; 747 } __aligned(MLX5E_CACHELINE_SIZE); 748 749 struct ipsec_accel_in_tag; 750 751 struct mlx5e_rq_mbuf { 752 bus_dmamap_t dma_map; 753 caddr_t data; 754 struct mbuf *mbuf; 755 struct ipsec_accel_in_tag *ipsec_mtag; 756 }; 757 758 struct mlx5e_rq { 759 /* persistent fields */ 760 struct mtx mtx; 761 struct mlx5e_rq_stats stats; 762 struct callout watchdog; 763 764 /* data path */ 765 #define mlx5e_rq_zero_start wq 766 struct mlx5_wq_ll wq; 767 bus_dma_tag_t dma_tag; 768 u32 wqe_sz; 769 u32 nsegs; 770 struct mlx5e_rq_mbuf *mbuf; 771 if_t ifp; 772 struct mlx5e_cq cq; 773 struct lro_ctrl lro; 774 volatile int enabled; 775 int processing; 776 int ix; 777 778 /* Dynamic Interrupt Moderation */ 779 struct net_dim dim; 780 781 /* control */ 782 struct mlx5_wq_ctrl wq_ctrl; 783 u32 rqn; 784 struct mlx5e_channel *channel; 785 } __aligned(MLX5E_CACHELINE_SIZE); 786 787 typedef void (mlx5e_iq_callback_t)(void *arg); 788 789 struct mlx5e_iq_data { 790 bus_dmamap_t dma_map; 791 mlx5e_iq_callback_t *callback; 792 void *arg; 793 volatile s32 *p_refcount; /* in use refcount, if any */ 794 u32 num_wqebbs; 795 u32 dma_sync; 796 }; 797 798 struct mlx5e_iq { 799 /* persistant fields */ 800 struct mtx lock; 801 struct mtx comp_lock; 802 int db_inhibit; 803 804 /* data path */ 805 #define mlx5e_iq_zero_start dma_tag 806 bus_dma_tag_t dma_tag; 807 808 u16 cc; /* consumer counter */ 809 u16 pc __aligned(MLX5E_CACHELINE_SIZE); 810 u16 running; 811 812 union { 813 u32 d32[2]; 814 u64 d64; 815 } doorbell; 816 817 struct mlx5e_cq cq; 818 819 /* pointers to per request info: write@xmit, read@completion */ 820 struct mlx5e_iq_data *data; 821 822 /* read only */ 823 struct mlx5_wq_cyc wq; 824 void __iomem *uar_map; 825 u32 sqn; 826 u32 mkey_be; 827 828 /* control path */ 829 struct mlx5_wq_ctrl wq_ctrl; 830 struct mlx5e_priv *priv; 831 }; 832 833 struct mlx5e_sq_mbuf { 834 bus_dmamap_t dma_map; 835 struct mbuf *mbuf; 836 struct m_snd_tag *mst; /* if set, unref this send tag on completion */ 837 u32 num_bytes; 838 u32 num_wqebbs; 839 }; 840 841 enum { 842 MLX5E_SQ_READY, 843 MLX5E_SQ_FULL 844 }; 845 846 struct mlx5e_sq { 847 /* persistent fields */ 848 struct mtx lock; 849 struct mtx comp_lock; 850 struct mlx5e_sq_stats stats; 851 struct callout cev_callout; 852 int db_inhibit; 853 854 /* data path */ 855 #define mlx5e_sq_zero_start dma_tag 856 bus_dma_tag_t dma_tag; 857 858 /* dirtied @completion */ 859 u16 cc; 860 861 /* dirtied @xmit */ 862 u16 pc __aligned(MLX5E_CACHELINE_SIZE); 863 u16 cev_counter; /* completion event counter */ 864 u16 cev_factor; /* completion event factor */ 865 u16 cev_next_state; /* next completion event state */ 866 #define MLX5E_CEV_STATE_INITIAL 0 /* timer not started */ 867 #define MLX5E_CEV_STATE_SEND_NOPS 1 /* send NOPs */ 868 #define MLX5E_CEV_STATE_HOLD_NOPS 2 /* don't send NOPs yet */ 869 u16 running; /* set if SQ is running */ 870 union { 871 u32 d32[2]; 872 u64 d64; 873 } doorbell; 874 875 struct mlx5e_cq cq; 876 877 /* pointers to per packet info: write@xmit, read@completion */ 878 struct mlx5e_sq_mbuf *mbuf; 879 880 /* read only */ 881 struct mlx5_wq_cyc wq; 882 void __iomem *uar_map; 883 struct ifnet *ifp; 884 u32 sqn; 885 u32 mkey_be; 886 u16 max_inline; 887 u8 min_inline_mode; 888 u8 min_insert_caps; 889 u32 queue_handle; /* SQ remap support */ 890 #define MLX5E_INSERT_VLAN 1 891 #define MLX5E_INSERT_NON_VLAN 2 892 893 /* control path */ 894 struct mlx5_wq_ctrl wq_ctrl; 895 struct mlx5e_priv *priv; 896 int tc; 897 } __aligned(MLX5E_CACHELINE_SIZE); 898 899 static inline bool 900 mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) 901 { 902 u16 cc = sq->cc; 903 u16 pc = sq->pc; 904 905 return ((sq->wq.sz_m1 & (cc - pc)) >= n || cc == pc); 906 } 907 908 static inline u32 909 mlx5e_sq_queue_level(struct mlx5e_sq *sq) 910 { 911 u16 cc; 912 u16 pc; 913 914 if (sq == NULL) 915 return (0); 916 917 cc = sq->cc; 918 pc = sq->pc; 919 920 return (((sq->wq.sz_m1 & (pc - cc)) * 921 IF_SND_QUEUE_LEVEL_MAX) / sq->wq.sz_m1); 922 } 923 924 struct mlx5e_channel { 925 struct mlx5e_rq rq; 926 struct m_snd_tag tag; 927 struct mlx5_sq_bfreg bfreg; 928 struct mlx5e_sq sq[MLX5E_MAX_TX_NUM_TC]; 929 struct mlx5e_iq iq; 930 struct mlx5e_priv *priv; 931 struct completion completion; 932 int ix; 933 u32 rqtn; 934 } __aligned(MLX5E_CACHELINE_SIZE); 935 936 enum mlx5e_traffic_types { 937 MLX5E_TT_IPV4_TCP, 938 MLX5E_TT_IPV6_TCP, 939 MLX5E_TT_IPV4_UDP, 940 MLX5E_TT_IPV6_UDP, 941 MLX5E_TT_IPV4_IPSEC_AH, 942 MLX5E_TT_IPV6_IPSEC_AH, 943 MLX5E_TT_IPV4_IPSEC_ESP, 944 MLX5E_TT_IPV6_IPSEC_ESP, 945 MLX5E_TT_IPV4, 946 MLX5E_TT_IPV6, 947 MLX5E_TT_ANY, 948 MLX5E_NUM_TT, 949 }; 950 951 enum { 952 MLX5E_RQT_SPREADING = 0, 953 MLX5E_RQT_DEFAULT_RQ = 1, 954 MLX5E_NUM_RQT = 2, 955 }; 956 957 struct mlx5_flow_rule; 958 959 struct mlx5e_eth_addr_info { 960 u8 addr [ETH_ALEN + 2]; 961 /* flow table rule per traffic type */ 962 struct mlx5_flow_handle *ft_rule[MLX5E_NUM_TT]; 963 }; 964 965 #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE) 966 967 struct mlx5e_eth_addr_hash_node; 968 969 struct mlx5e_eth_addr_hash_head { 970 struct mlx5e_eth_addr_hash_node *lh_first; 971 }; 972 973 struct mlx5e_eth_addr_db { 974 struct mlx5e_eth_addr_hash_head if_uc[MLX5E_ETH_ADDR_HASH_SIZE]; 975 struct mlx5e_eth_addr_hash_head if_mc[MLX5E_ETH_ADDR_HASH_SIZE]; 976 struct mlx5e_eth_addr_info broadcast; 977 struct mlx5e_eth_addr_info allmulti; 978 struct mlx5e_eth_addr_info promisc; 979 bool broadcast_enabled; 980 bool allmulti_enabled; 981 bool promisc_enabled; 982 }; 983 984 enum { 985 MLX5E_STATE_ASYNC_EVENTS_ENABLE, 986 MLX5E_STATE_OPENED, 987 MLX5E_STATE_FLOW_RULES_READY, 988 }; 989 990 enum { 991 MLX5_BW_NO_LIMIT = 0, 992 MLX5_100_MBPS_UNIT = 3, 993 MLX5_GBPS_UNIT = 4, 994 }; 995 996 struct mlx5e_vlan_db { 997 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 998 struct mlx5_flow_handle *active_vlans_ft_rule[VLAN_N_VID]; 999 struct mlx5_flow_handle *untagged_ft_rule; 1000 struct mlx5_flow_handle *any_cvlan_ft_rule; 1001 struct mlx5_flow_handle *any_svlan_ft_rule; 1002 bool filter_disabled; 1003 }; 1004 1005 struct mlx5e_vxlan_db_el { 1006 u_int refcount; 1007 u_int proto; 1008 u_int port; 1009 bool installed; 1010 struct mlx5_flow_handle *vxlan_ft_rule; 1011 TAILQ_ENTRY(mlx5e_vxlan_db_el) link; 1012 }; 1013 1014 struct mlx5e_vxlan_db { 1015 TAILQ_HEAD(, mlx5e_vxlan_db_el) head; 1016 }; 1017 1018 struct mlx5e_flow_table { 1019 int num_groups; 1020 struct mlx5_flow_table *t; 1021 struct mlx5_flow_group **g; 1022 }; 1023 1024 enum accel_fs_tcp_type { 1025 MLX5E_ACCEL_FS_IPV4_TCP, 1026 MLX5E_ACCEL_FS_IPV6_TCP, 1027 MLX5E_ACCEL_FS_TCP_NUM_TYPES, 1028 }; 1029 1030 struct mlx5e_accel_fs_tcp { 1031 struct mlx5_flow_namespace *ns; 1032 struct mlx5e_flow_table tables[MLX5E_ACCEL_FS_TCP_NUM_TYPES]; 1033 struct mlx5_flow_handle *default_rules[MLX5E_ACCEL_FS_TCP_NUM_TYPES]; 1034 }; 1035 1036 struct mlx5e_flow_tables { 1037 struct mlx5_flow_namespace *ns; 1038 struct mlx5e_flow_table vlan; 1039 struct mlx5e_flow_table vxlan; 1040 struct mlx5_flow_handle *vxlan_catchall_ft_rule; 1041 struct mlx5e_flow_table main; 1042 struct mlx5e_flow_table main_vxlan; 1043 struct mlx5_flow_handle *main_vxlan_rule[MLX5E_NUM_TT]; 1044 struct mlx5e_flow_table inner_rss; 1045 struct mlx5e_accel_fs_tcp accel_tcp; 1046 struct mlx5_flow_table *ipsec_ft; 1047 }; 1048 1049 struct mlx5e_xmit_args { 1050 struct m_snd_tag *mst; 1051 u32 tisn; 1052 u16 ihs; 1053 }; 1054 1055 #include <dev/mlx5/mlx5_en/en_rl.h> 1056 #include <dev/mlx5/mlx5_en/en_hw_tls.h> 1057 #include <dev/mlx5/mlx5_en/en_hw_tls_rx.h> 1058 1059 #define MLX5E_TSTMP_PREC 10 1060 1061 struct mlx5e_clbr_point { 1062 uint64_t base_curr; 1063 uint64_t base_prev; 1064 uint64_t clbr_hw_prev; 1065 uint64_t clbr_hw_curr; 1066 u_int clbr_gen; 1067 }; 1068 1069 struct mlx5e_dcbx { 1070 u32 cable_len; 1071 u32 xoff; 1072 }; 1073 1074 struct mlx5e_ipsec; 1075 struct mlx5e_priv { 1076 struct mlx5_core_dev *mdev; /* must be first */ 1077 1078 /* priv data path fields - start */ 1079 int order_base_2_num_channels; 1080 int queue_mapping_channel_mask; 1081 int num_tc; 1082 int default_vlan_prio; 1083 /* priv data path fields - end */ 1084 1085 unsigned long state; 1086 int gone; 1087 #define PRIV_LOCK(priv) sx_xlock(&(priv)->state_lock) 1088 #define PRIV_UNLOCK(priv) sx_xunlock(&(priv)->state_lock) 1089 #define PRIV_LOCKED(priv) sx_xlocked(&(priv)->state_lock) 1090 #define PRIV_ASSERT_LOCKED(priv) sx_assert(&(priv)->state_lock, SA_XLOCKED) 1091 struct sx state_lock; /* Protects Interface state */ 1092 struct mlx5e_rq drop_rq; 1093 u32 pdn; 1094 u32 tdn; 1095 struct mlx5_core_mkey mr; 1096 1097 u32 tisn[MLX5E_MAX_TX_NUM_TC]; 1098 u32 rqtn; 1099 u32 tirn[MLX5E_NUM_TT]; 1100 u32 tirn_inner_vxlan[MLX5E_NUM_TT]; 1101 1102 struct mlx5e_flow_tables fts; 1103 struct mlx5e_eth_addr_db eth_addr; 1104 struct mlx5e_vlan_db vlan; 1105 struct mlx5e_vxlan_db vxlan; 1106 1107 struct mlx5e_params params; 1108 struct mlx5e_params_ethtool params_ethtool; 1109 union mlx5_core_pci_diagnostics params_pci; 1110 union mlx5_core_general_diagnostics params_general; 1111 struct mtx async_events_mtx; /* sync hw events */ 1112 struct work_struct update_stats_work; 1113 struct work_struct update_carrier_work; 1114 struct work_struct set_rx_mode_work; 1115 MLX5_DECLARE_DOORBELL_LOCK(doorbell_lock) 1116 1117 if_t ifp; 1118 struct sysctl_ctx_list sysctl_ctx; 1119 struct sysctl_oid *sysctl_ifnet; 1120 struct sysctl_oid *sysctl_hw; 1121 int sysctl_debug; 1122 struct mlx5e_stats stats; 1123 int counter_set_id; 1124 1125 struct workqueue_struct *wq; 1126 1127 eventhandler_tag vlan_detach; 1128 eventhandler_tag vlan_attach; 1129 struct ifmedia media; 1130 int media_status_last; 1131 int media_active_last; 1132 eventhandler_tag vxlan_start; 1133 eventhandler_tag vxlan_stop; 1134 1135 struct callout watchdog; 1136 1137 struct mlx5e_rl_priv_data rl; 1138 1139 struct mlx5e_tls tls; 1140 struct mlx5e_tls_rx tls_rx; 1141 1142 struct callout tstmp_clbr; 1143 int clbr_done; 1144 int clbr_curr; 1145 struct mlx5e_clbr_point clbr_points[2]; 1146 u_int clbr_gen; 1147 uint64_t cclk; 1148 1149 struct mlx5e_dcbx dcbx; 1150 bool sw_is_port_buf_owner; 1151 1152 struct pfil_head *pfil; 1153 struct mlx5e_ipsec *ipsec; 1154 struct mlx5e_channel channel[]; 1155 }; 1156 1157 #define MLX5E_NET_IP_ALIGN 2 1158 1159 struct mlx5e_tx_wqe { 1160 struct mlx5_wqe_ctrl_seg ctrl; 1161 struct mlx5_wqe_eth_seg eth; 1162 }; 1163 1164 struct mlx5e_tx_umr_wqe { 1165 struct mlx5_wqe_ctrl_seg ctrl; 1166 struct mlx5_wqe_umr_ctrl_seg umr; 1167 uint8_t mkc[64]; 1168 }; 1169 1170 struct mlx5e_tx_psv_wqe { 1171 struct mlx5_wqe_ctrl_seg ctrl; 1172 struct mlx5_seg_set_psv psv; 1173 }; 1174 1175 struct mlx5e_tx_qos_remap_wqe { 1176 struct mlx5_wqe_ctrl_seg ctrl; 1177 struct mlx5_wqe_qos_remap_seg qos_remap; 1178 }; 1179 1180 struct mlx5e_rx_wqe { 1181 struct mlx5_wqe_srq_next_seg next; 1182 struct mlx5_wqe_data_seg data[]; 1183 }; 1184 1185 /* the size of the structure above must be power of two */ 1186 CTASSERT(powerof2(sizeof(struct mlx5e_rx_wqe))); 1187 1188 struct mlx5e_eeprom { 1189 int lock_bit; 1190 int i2c_addr; 1191 int page_num; 1192 int device_addr; 1193 int module_num; 1194 int len; 1195 int type; 1196 int page_valid; 1197 u32 *data; 1198 }; 1199 1200 #define MLX5E_FLD_MAX(typ, fld) ((1ULL << __mlx5_bit_sz(typ, fld)) - 1ULL) 1201 1202 bool mlx5e_do_send_cqe(struct mlx5e_sq *); 1203 int mlx5e_get_full_header_size(const struct mbuf *, const struct tcphdr **); 1204 int mlx5e_xmit(if_t, struct mbuf *); 1205 1206 int mlx5e_open_locked(if_t); 1207 int mlx5e_close_locked(if_t); 1208 1209 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, int event); 1210 void mlx5e_dump_err_cqe(struct mlx5e_cq *, u32, const struct mlx5_err_cqe *); 1211 1212 mlx5e_cq_comp_t mlx5e_rx_cq_comp; 1213 mlx5e_cq_comp_t mlx5e_tx_cq_comp; 1214 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); 1215 1216 void mlx5e_dim_work(struct work_struct *); 1217 void mlx5e_dim_build_cq_param(struct mlx5e_priv *, struct mlx5e_cq_param *); 1218 1219 int mlx5e_open_flow_tables(struct mlx5e_priv *priv); 1220 void mlx5e_close_flow_tables(struct mlx5e_priv *priv); 1221 int mlx5e_open_flow_rules(struct mlx5e_priv *priv); 1222 void mlx5e_close_flow_rules(struct mlx5e_priv *priv); 1223 void mlx5e_set_rx_mode_work(struct work_struct *work); 1224 1225 void mlx5e_vlan_rx_add_vid(void *, if_t, u16); 1226 void mlx5e_vlan_rx_kill_vid(void *, if_t, u16); 1227 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); 1228 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); 1229 1230 void mlx5e_vxlan_start(void *arg, if_t ifp, sa_family_t family, 1231 u_int port); 1232 void mlx5e_vxlan_stop(void *arg, if_t ifp, sa_family_t family, 1233 u_int port); 1234 int mlx5e_add_all_vxlan_rules(struct mlx5e_priv *priv); 1235 void mlx5e_del_all_vxlan_rules(struct mlx5e_priv *priv); 1236 1237 static inline void 1238 mlx5e_tx_notify_hw(struct mlx5e_sq *sq, bool force) 1239 { 1240 if (unlikely((force == false && sq->db_inhibit != 0) || sq->doorbell.d64 == 0)) { 1241 /* skip writing the doorbell record */ 1242 return; 1243 } 1244 1245 /* ensure wqe is visible to device before updating doorbell record */ 1246 wmb(); 1247 1248 *sq->wq.db = cpu_to_be32(sq->pc); 1249 1250 /* 1251 * Ensure the doorbell record is visible to device before ringing 1252 * the doorbell: 1253 */ 1254 wmb(); 1255 1256 mlx5_write64(sq->doorbell.d32, sq->uar_map, 1257 MLX5_GET_DOORBELL_LOCK(&sq->priv->doorbell_lock)); 1258 1259 sq->doorbell.d64 = 0; 1260 } 1261 1262 static inline void 1263 mlx5e_cq_arm(struct mlx5e_cq *cq, spinlock_t *dblock) 1264 { 1265 struct mlx5_core_cq *mcq; 1266 1267 mcq = &cq->mcq; 1268 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, dblock, cq->wq.cc); 1269 } 1270 1271 #define mlx5e_dbg(_IGN, _priv, ...) mlx5_core_dbg((_priv)->mdev, __VA_ARGS__) 1272 1273 extern const struct ethtool_ops mlx5e_ethtool_ops; 1274 void mlx5e_create_ethtool(struct mlx5e_priv *); 1275 void mlx5e_create_stats(struct sysctl_ctx_list *, 1276 struct sysctl_oid_list *, const char *, 1277 const char **, unsigned, u64 *); 1278 void mlx5e_create_counter_stats(struct sysctl_ctx_list *, 1279 struct sysctl_oid_list *, const char *, 1280 const char **, unsigned, counter_u64_t *); 1281 void mlx5e_send_nop(struct mlx5e_sq *, u32); 1282 int mlx5e_sq_dump_xmit(struct mlx5e_sq *, struct mlx5e_xmit_args *, struct mbuf **); 1283 int mlx5e_sq_xmit(struct mlx5e_sq *, struct mbuf **); 1284 void mlx5e_sq_cev_timeout(void *); 1285 int mlx5e_refresh_channel_params(struct mlx5e_priv *); 1286 int mlx5e_open_cq(struct mlx5e_priv *, struct mlx5e_cq_param *, 1287 struct mlx5e_cq *, mlx5e_cq_comp_t *, int eq_ix); 1288 void mlx5e_close_cq(struct mlx5e_cq *); 1289 void mlx5e_free_sq_db(struct mlx5e_sq *); 1290 int mlx5e_alloc_sq_db(struct mlx5e_sq *); 1291 int mlx5e_enable_sq(struct mlx5e_sq *, struct mlx5e_sq_param *, 1292 const struct mlx5_sq_bfreg *, int tis_num); 1293 int mlx5e_modify_sq(struct mlx5e_sq *, int curr_state, int next_state); 1294 void mlx5e_disable_sq(struct mlx5e_sq *); 1295 void mlx5e_drain_sq(struct mlx5e_sq *); 1296 void mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value); 1297 void mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value); 1298 void mlx5e_resume_sq(struct mlx5e_sq *sq); 1299 void mlx5e_update_sq_inline(struct mlx5e_sq *sq); 1300 void mlx5e_refresh_sq_inline(struct mlx5e_priv *priv); 1301 int mlx5e_update_buf_lossy(struct mlx5e_priv *priv); 1302 int mlx5e_fec_update(struct mlx5e_priv *priv); 1303 int mlx5e_hw_temperature_update(struct mlx5e_priv *priv); 1304 int mlx5e_hw_lro_update_tirs(struct mlx5e_priv *priv); 1305 1306 /* Internal Queue, IQ, API functions */ 1307 void mlx5e_iq_send_nop(struct mlx5e_iq *, u32); 1308 int mlx5e_iq_open(struct mlx5e_channel *, struct mlx5e_sq_param *, struct mlx5e_cq_param *, struct mlx5e_iq *); 1309 void mlx5e_iq_close(struct mlx5e_iq *); 1310 void mlx5e_iq_static_init(struct mlx5e_iq *); 1311 void mlx5e_iq_static_destroy(struct mlx5e_iq *); 1312 void mlx5e_iq_notify_hw(struct mlx5e_iq *); 1313 int mlx5e_iq_get_producer_index(struct mlx5e_iq *); 1314 void mlx5e_iq_load_memory_single(struct mlx5e_iq *, u16, void *, size_t, u64 *, u32); 1315 1316 #endif /* _MLX5_EN_H_ */ 1317