xref: /freebsd/sys/dev/mlx5/mlx5_en/en.h (revision f061a2215f9bf0bea98ac601a34750f89428db67)
1 /*-
2  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  * 1. Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  *
13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23  * SUCH DAMAGE.
24  *
25  * $FreeBSD$
26  */
27 
28 #ifndef _MLX5_EN_H_
29 #define	_MLX5_EN_H_
30 
31 #include <linux/kmod.h>
32 #include <linux/page.h>
33 #include <linux/slab.h>
34 #include <linux/if_vlan.h>
35 #include <linux/if_ether.h>
36 #include <linux/vmalloc.h>
37 #include <linux/moduleparam.h>
38 #include <linux/delay.h>
39 #include <linux/netdevice.h>
40 #include <linux/etherdevice.h>
41 
42 #include <netinet/in_systm.h>
43 #include <netinet/in.h>
44 #include <netinet/if_ether.h>
45 #include <netinet/ip.h>
46 #include <netinet/ip6.h>
47 #include <netinet/tcp.h>
48 #include <netinet/tcp_lro.h>
49 #include <netinet/udp.h>
50 #include <net/ethernet.h>
51 #include <sys/buf_ring.h>
52 
53 #include "opt_rss.h"
54 
55 #ifdef	RSS
56 #include <net/rss_config.h>
57 #include <netinet/in_rss.h>
58 #endif
59 
60 #include <machine/bus.h>
61 
62 #ifdef HAVE_TURBO_LRO
63 #include "tcp_tlro.h"
64 #endif
65 
66 #include <dev/mlx5/driver.h>
67 #include <dev/mlx5/qp.h>
68 #include <dev/mlx5/cq.h>
69 #include <dev/mlx5/vport.h>
70 
71 #include <dev/mlx5/mlx5_core/wq.h>
72 #include <dev/mlx5/mlx5_core/transobj.h>
73 #include <dev/mlx5/mlx5_core/mlx5_core.h>
74 
75 #define	MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE                0x7
76 #define	MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE                0xa
77 #define	MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE                0xd
78 
79 #define	MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE                0x7
80 #define	MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE                0xa
81 #define	MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE                0xd
82 
83 /* freeBSD HW LRO is limited by 16KB - the size of max mbuf */
84 #define	MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ                 MJUM16BYTES
85 #define	MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC      0x10
86 #define	MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE	0x3
87 #define	MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS      0x20
88 #define	MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC      0x10
89 #define	MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS      0x20
90 #define	MLX5E_PARAMS_DEFAULT_MIN_RX_WQES                0x80
91 #define	MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ         0x7
92 #define	MLX5E_CACHELINE_SIZE CACHE_LINE_SIZE
93 #define	MLX5E_HW2SW_MTU(hwmtu) \
94     ((hwmtu) - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN))
95 #define	MLX5E_SW2HW_MTU(swmtu) \
96     ((swmtu) + (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN))
97 #define	MLX5E_SW2MB_MTU(swmtu) \
98     (MLX5E_SW2HW_MTU(swmtu) + MLX5E_NET_IP_ALIGN)
99 #define	MLX5E_MTU_MIN		72	/* Min MTU allowed by the kernel */
100 #define	MLX5E_MTU_MAX		MIN(ETHERMTU_JUMBO, MJUM16BYTES)	/* Max MTU of Ethernet
101 									 * jumbo frames */
102 
103 #define	MLX5E_BUDGET_MAX	8192	/* RX and TX */
104 #define	MLX5E_RX_BUDGET_MAX	256
105 #define	MLX5E_SQ_BF_BUDGET	16
106 #define	MLX5E_SQ_TX_QUEUE_SIZE	4096	/* SQ drbr queue size */
107 
108 #define	MLX5E_MAX_TX_NUM_TC	8	/* units */
109 #define	MLX5E_MAX_TX_HEADER	128	/* bytes */
110 #define	MLX5E_MAX_TX_PAYLOAD_SIZE	65536	/* bytes */
111 #define	MLX5E_MAX_TX_MBUF_SIZE	65536	/* bytes */
112 #define	MLX5E_MAX_TX_MBUF_FRAGS	\
113     ((MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS) - \
114     (MLX5E_MAX_TX_HEADER / MLX5_SEND_WQE_DS))	/* units */
115 #define	MLX5E_MAX_TX_INLINE \
116   (MLX5E_MAX_TX_HEADER - sizeof(struct mlx5e_tx_wqe) + \
117   sizeof(((struct mlx5e_tx_wqe *)0)->eth.inline_hdr_start))	/* bytes */
118 
119 MALLOC_DECLARE(M_MLX5EN);
120 
121 struct mlx5_core_dev;
122 struct mlx5e_cq;
123 
124 typedef void (mlx5e_cq_comp_t)(struct mlx5_core_cq *);
125 
126 #define	MLX5E_STATS_COUNT(a,b,c,d) a
127 #define	MLX5E_STATS_VAR(a,b,c,d) b;
128 #define	MLX5E_STATS_DESC(a,b,c,d) c, d,
129 
130 #define	MLX5E_VPORT_STATS(m)						\
131   /* HW counters */							\
132   m(+1, u64 rx_packets, "rx_packets", "Received packets")		\
133   m(+1, u64 rx_bytes, "rx_bytes", "Received bytes")			\
134   m(+1, u64 tx_packets, "tx_packets", "Transmitted packets")		\
135   m(+1, u64 tx_bytes, "tx_bytes", "Transmitted bytes")			\
136   m(+1, u64 rx_error_packets, "rx_error_packets", "Received error packets") \
137   m(+1, u64 rx_error_bytes, "rx_error_bytes", "Received error bytes")	\
138   m(+1, u64 tx_error_packets, "tx_error_packets", "Transmitted error packets") \
139   m(+1, u64 tx_error_bytes, "tx_error_bytes", "Transmitted error bytes") \
140   m(+1, u64 rx_unicast_packets, "rx_unicast_packets", "Received unicast packets") \
141   m(+1, u64 rx_unicast_bytes, "rx_unicast_bytes", "Received unicast bytes") \
142   m(+1, u64 tx_unicast_packets, "tx_unicast_packets", "Transmitted unicast packets") \
143   m(+1, u64 tx_unicast_bytes, "tx_unicast_bytes", "Transmitted unicast bytes") \
144   m(+1, u64 rx_multicast_packets, "rx_multicast_packets", "Received multicast packets") \
145   m(+1, u64 rx_multicast_bytes, "rx_multicast_bytes", "Received multicast bytes") \
146   m(+1, u64 tx_multicast_packets, "tx_multicast_packets", "Transmitted multicast packets") \
147   m(+1, u64 tx_multicast_bytes, "tx_multicast_bytes", "Transmitted multicast bytes") \
148   m(+1, u64 rx_broadcast_packets, "rx_broadcast_packets", "Received broadcast packets") \
149   m(+1, u64 rx_broadcast_bytes, "rx_broadcast_bytes", "Received broadcast bytes") \
150   m(+1, u64 tx_broadcast_packets, "tx_broadcast_packets", "Transmitted broadcast packets") \
151   m(+1, u64 tx_broadcast_bytes, "tx_broadcast_bytes", "Transmitted broadcast bytes") \
152   m(+1, u64 rx_out_of_buffer, "rx_out_of_buffer", "Receive out of buffer, no recv wqes events") \
153   /* SW counters */							\
154   m(+1, u64 tso_packets, "tso_packets", "Transmitted TSO packets")	\
155   m(+1, u64 tso_bytes, "tso_bytes", "Transmitted TSO bytes")		\
156   m(+1, u64 lro_packets, "lro_packets", "Received LRO packets")		\
157   m(+1, u64 lro_bytes, "lro_bytes", "Received LRO bytes")		\
158   m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO")	\
159   m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO")	\
160   m(+1, u64 rx_csum_good, "rx_csum_good", "Received checksum valid packets") \
161   m(+1, u64 rx_csum_none, "rx_csum_none", "Received no checksum packets") \
162   m(+1, u64 tx_csum_offload, "tx_csum_offload", "Transmit checksum offload packets") \
163   m(+1, u64 tx_queue_dropped, "tx_queue_dropped", "Transmit queue dropped") \
164   m(+1, u64 tx_defragged, "tx_defragged", "Transmit queue defragged") \
165   m(+1, u64 rx_wqe_err, "rx_wqe_err", "Receive WQE errors")
166 
167 #define	MLX5E_VPORT_STATS_NUM (0 MLX5E_VPORT_STATS(MLX5E_STATS_COUNT))
168 
169 struct mlx5e_vport_stats {
170 	struct	sysctl_ctx_list ctx;
171 	u64	arg [0];
172 	MLX5E_VPORT_STATS(MLX5E_STATS_VAR)
173 	u32	rx_out_of_buffer_prev;
174 };
175 
176 #define	MLX5E_PPORT_IEEE802_3_STATS(m)					\
177   m(+1, u64 frames_tx, "frames_tx", "Frames transmitted")		\
178   m(+1, u64 frames_rx, "frames_rx", "Frames received")			\
179   m(+1, u64 check_seq_err, "check_seq_err", "Sequence errors")		\
180   m(+1, u64 alignment_err, "alignment_err", "Alignment errors")	\
181   m(+1, u64 octets_tx, "octets_tx", "Bytes transmitted")		\
182   m(+1, u64 octets_received, "octets_received", "Bytes received")	\
183   m(+1, u64 multicast_xmitted, "multicast_xmitted", "Multicast transmitted") \
184   m(+1, u64 broadcast_xmitted, "broadcast_xmitted", "Broadcast transmitted") \
185   m(+1, u64 multicast_rx, "multicast_rx", "Multicast received")	\
186   m(+1, u64 broadcast_rx, "broadcast_rx", "Broadcast received")	\
187   m(+1, u64 in_range_len_errors, "in_range_len_errors", "In range length errors") \
188   m(+1, u64 out_of_range_len, "out_of_range_len", "Out of range length errors") \
189   m(+1, u64 too_long_errors, "too_long_errors", "Too long errors")	\
190   m(+1, u64 symbol_err, "symbol_err", "Symbol errors")			\
191   m(+1, u64 mac_control_tx, "mac_control_tx", "MAC control transmitted") \
192   m(+1, u64 mac_control_rx, "mac_control_rx", "MAC control received")	\
193   m(+1, u64 unsupported_op_rx, "unsupported_op_rx", "Unsupported operation received") \
194   m(+1, u64 pause_ctrl_rx, "pause_ctrl_rx", "Pause control received")	\
195   m(+1, u64 pause_ctrl_tx, "pause_ctrl_tx", "Pause control transmitted")
196 
197 #define	MLX5E_PPORT_RFC2819_STATS(m)					\
198   m(+1, u64 drop_events, "drop_events", "Dropped events")		\
199   m(+1, u64 octets, "octets", "Octets")					\
200   m(+1, u64 pkts, "pkts", "Packets")					\
201   m(+1, u64 broadcast_pkts, "broadcast_pkts", "Broadcast packets")	\
202   m(+1, u64 multicast_pkts, "multicast_pkts", "Multicast packets")	\
203   m(+1, u64 crc_align_errors, "crc_align_errors", "CRC alignment errors") \
204   m(+1, u64 undersize_pkts, "undersize_pkts", "Undersized packets")	\
205   m(+1, u64 oversize_pkts, "oversize_pkts", "Oversized packets")	\
206   m(+1, u64 fragments, "fragments", "Fragments")			\
207   m(+1, u64 jabbers, "jabbers", "Jabbers")				\
208   m(+1, u64 collisions, "collisions", "Collisions")
209 
210 #define	MLX5E_PPORT_RFC2819_STATS_DEBUG(m)				\
211   m(+1, u64 p64octets, "p64octets", "Bytes")				\
212   m(+1, u64 p65to127octets, "p65to127octets", "Bytes")			\
213   m(+1, u64 p128to255octets, "p128to255octets", "Bytes")		\
214   m(+1, u64 p256to511octets, "p256to511octets", "Bytes")		\
215   m(+1, u64 p512to1023octets, "p512to1023octets", "Bytes")		\
216   m(+1, u64 p1024to1518octets, "p1024to1518octets", "Bytes")		\
217   m(+1, u64 p1519to2047octets, "p1519to2047octets", "Bytes")		\
218   m(+1, u64 p2048to4095octets, "p2048to4095octets", "Bytes")		\
219   m(+1, u64 p4096to8191octets, "p4096to8191octets", "Bytes")		\
220   m(+1, u64 p8192to10239octets, "p8192to10239octets", "Bytes")
221 
222 #define	MLX5E_PPORT_RFC2863_STATS_DEBUG(m)				\
223   m(+1, u64 in_octets, "in_octets", "In octets")			\
224   m(+1, u64 in_ucast_pkts, "in_ucast_pkts", "In unicast packets")	\
225   m(+1, u64 in_discards, "in_discards", "In discards")			\
226   m(+1, u64 in_errors, "in_errors", "In errors")			\
227   m(+1, u64 in_unknown_protos, "in_unknown_protos", "In unknown protocols") \
228   m(+1, u64 out_octets, "out_octets", "Out octets")			\
229   m(+1, u64 out_ucast_pkts, "out_ucast_pkts", "Out unicast packets")	\
230   m(+1, u64 out_discards, "out_discards", "Out discards")		\
231   m(+1, u64 out_errors, "out_errors", "Out errors")			\
232   m(+1, u64 in_multicast_pkts, "in_multicast_pkts", "In multicast packets") \
233   m(+1, u64 in_broadcast_pkts, "in_broadcast_pkts", "In broadcast packets") \
234   m(+1, u64 out_multicast_pkts, "out_multicast_pkts", "Out multicast packets") \
235   m(+1, u64 out_broadcast_pkts, "out_broadcast_pkts", "Out broadcast packets")
236 
237 #define	MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m)                                    		\
238   m(+1, u64 time_since_last_clear, "time_since_last_clear",				\
239 			"Time since the last counters clear event (msec)")		\
240   m(+1, u64 symbol_errors, "symbol_errors", "Symbol errors")				\
241   m(+1, u64 sync_headers_errors, "sync_headers_errors", "Sync header error counter")	\
242   m(+1, u64 bip_errors_lane0, "edpl_bip_errors_lane0",					\
243 			"Indicates the number of PRBS errors on lane 0")		\
244   m(+1, u64 bip_errors_lane1, "edpl_bip_errors_lane1",					\
245 			"Indicates the number of PRBS errors on lane 1")		\
246   m(+1, u64 bip_errors_lane2, "edpl_bip_errors_lane2",					\
247 			"Indicates the number of PRBS errors on lane 2")		\
248   m(+1, u64 bip_errors_lane3, "edpl_bip_errors_lane3",					\
249 			"Indicates the number of PRBS errors on lane 3")		\
250   m(+1, u64 fc_corrected_blocks_lane0, "fc_corrected_blocks_lane0",			\
251 			"FEC correctable block counter lane 0")				\
252   m(+1, u64 fc_corrected_blocks_lane1, "fc_corrected_blocks_lane1",			\
253 			"FEC correctable block counter lane 1")				\
254   m(+1, u64 fc_corrected_blocks_lane2, "fc_corrected_blocks_lane2",			\
255 			"FEC correctable block counter lane 2")				\
256   m(+1, u64 fc_corrected_blocks_lane3, "fc_corrected_blocks_lane3",			\
257 			"FEC correctable block counter lane 3")				\
258   m(+1, u64 rs_corrected_blocks, "rs_corrected_blocks",					\
259 			"FEC correcable block counter")					\
260   m(+1, u64 rs_uncorrectable_blocks, "rs_uncorrectable_blocks",				\
261 			"FEC uncorrecable block counter")				\
262   m(+1, u64 rs_no_errors_blocks, "rs_no_errors_blocks",					\
263 			"The number of RS-FEC blocks received that had no errors")	\
264   m(+1, u64 rs_single_error_blocks, "rs_single_error_blocks",				\
265 			"The number of corrected RS-FEC blocks received that had"	\
266 			"exactly 1 error symbol")					\
267   m(+1, u64 rs_corrected_symbols_total, "rs_corrected_symbols_total",			\
268 			"Port FEC corrected symbol counter")				\
269   m(+1, u64 rs_corrected_symbols_lane0, "rs_corrected_symbols_lane0",			\
270 			"FEC corrected symbol counter lane 0")				\
271   m(+1, u64 rs_corrected_symbols_lane1, "rs_corrected_symbols_lane1",			\
272 			"FEC corrected symbol counter lane 1")				\
273   m(+1, u64 rs_corrected_symbols_lane2, "rs_corrected_symbols_lane2",			\
274 			"FEC corrected symbol counter lane 2")				\
275   m(+1, u64 rs_corrected_symbols_lane3, "rs_corrected_symbols_lane3",			\
276 			"FEC corrected symbol counter lane 3")				\
277 
278 /*
279  * Make sure to update mlx5e_update_pport_counters()
280  * when adding a new MLX5E_PPORT_STATS block
281  */
282 #define	MLX5E_PPORT_STATS(m)			\
283   MLX5E_PPORT_IEEE802_3_STATS(m)		\
284   MLX5E_PPORT_RFC2819_STATS(m)
285 
286 #define	MLX5E_PORT_STATS_DEBUG(m)		\
287   MLX5E_PPORT_RFC2819_STATS_DEBUG(m)		\
288   MLX5E_PPORT_RFC2863_STATS_DEBUG(m)		\
289   MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m)
290 
291 #define	MLX5E_PPORT_IEEE802_3_STATS_NUM \
292   (0 MLX5E_PPORT_IEEE802_3_STATS(MLX5E_STATS_COUNT))
293 #define	MLX5E_PPORT_RFC2819_STATS_NUM \
294   (0 MLX5E_PPORT_RFC2819_STATS(MLX5E_STATS_COUNT))
295 #define	MLX5E_PPORT_STATS_NUM \
296   (0 MLX5E_PPORT_STATS(MLX5E_STATS_COUNT))
297 
298 #define	MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM \
299   (0 MLX5E_PPORT_RFC2819_STATS_DEBUG(MLX5E_STATS_COUNT))
300 #define	MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM \
301   (0 MLX5E_PPORT_RFC2863_STATS_DEBUG(MLX5E_STATS_COUNT))
302 #define	MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM \
303   (0 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(MLX5E_STATS_COUNT))
304 #define	MLX5E_PORT_STATS_DEBUG_NUM \
305   (0 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_COUNT))
306 
307 struct mlx5e_pport_stats {
308 	struct	sysctl_ctx_list ctx;
309 	u64	arg [0];
310 	MLX5E_PPORT_STATS(MLX5E_STATS_VAR)
311 };
312 
313 struct mlx5e_port_stats_debug {
314 	struct	sysctl_ctx_list ctx;
315 	u64	arg [0];
316 	MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_VAR)
317 };
318 
319 #define	MLX5E_RQ_STATS(m)					\
320   m(+1, u64 packets, "packets", "Received packets")		\
321   m(+1, u64 csum_none, "csum_none", "Received packets")		\
322   m(+1, u64 lro_packets, "lro_packets", "Received packets")	\
323   m(+1, u64 lro_bytes, "lro_bytes", "Received packets")		\
324   m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO")	\
325   m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO")	\
326   m(+1, u64 wqe_err, "wqe_err", "Received packets")
327 
328 #define	MLX5E_RQ_STATS_NUM (0 MLX5E_RQ_STATS(MLX5E_STATS_COUNT))
329 
330 struct mlx5e_rq_stats {
331 	struct	sysctl_ctx_list ctx;
332 	u64	arg [0];
333 	MLX5E_RQ_STATS(MLX5E_STATS_VAR)
334 };
335 
336 #define	MLX5E_SQ_STATS(m)						\
337   m(+1, u64 packets, "packets", "Transmitted packets")			\
338   m(+1, u64 tso_packets, "tso_packets", "Transmitted packets")		\
339   m(+1, u64 tso_bytes, "tso_bytes", "Transmitted bytes")		\
340   m(+1, u64 csum_offload_none, "csum_offload_none", "Transmitted packets")	\
341   m(+1, u64 defragged, "defragged", "Transmitted packets")		\
342   m(+1, u64 dropped, "dropped", "Transmitted packets")			\
343   m(+1, u64 nop, "nop", "Transmitted packets")
344 
345 #define	MLX5E_SQ_STATS_NUM (0 MLX5E_SQ_STATS(MLX5E_STATS_COUNT))
346 
347 struct mlx5e_sq_stats {
348 	struct	sysctl_ctx_list ctx;
349 	u64	arg [0];
350 	MLX5E_SQ_STATS(MLX5E_STATS_VAR)
351 };
352 
353 struct mlx5e_stats {
354 	struct mlx5e_vport_stats vport;
355 	struct mlx5e_pport_stats pport;
356 	struct mlx5e_port_stats_debug port_stats_debug;
357 };
358 
359 struct mlx5e_params {
360 	u8	log_sq_size;
361 	u8	log_rq_size;
362 	u16	num_channels;
363 	u8	default_vlan_prio;
364 	u8	num_tc;
365 	u8	rx_cq_moderation_mode;
366 	u8	tx_cq_moderation_mode;
367 	u16	rx_cq_moderation_usec;
368 	u16	rx_cq_moderation_pkts;
369 	u16	tx_cq_moderation_usec;
370 	u16	tx_cq_moderation_pkts;
371 	u16	min_rx_wqes;
372 	bool	hw_lro_en;
373 	bool	cqe_zipping_en;
374 	u32	lro_wqe_sz;
375 	u16	rx_hash_log_tbl_sz;
376 	u32	tx_pauseframe_control;
377 	u32	rx_pauseframe_control;
378 };
379 
380 #define	MLX5E_PARAMS(m)							\
381   m(+1, u64 tx_queue_size_max, "tx_queue_size_max", "Max send queue size") \
382   m(+1, u64 rx_queue_size_max, "rx_queue_size_max", "Max receive queue size") \
383   m(+1, u64 tx_queue_size, "tx_queue_size", "Default send queue size")	\
384   m(+1, u64 rx_queue_size, "rx_queue_size", "Default receive queue size") \
385   m(+1, u64 channels, "channels", "Default number of channels")		\
386   m(+1, u64 coalesce_usecs_max, "coalesce_usecs_max", "Maximum usecs for joining packets") \
387   m(+1, u64 coalesce_pkts_max, "coalesce_pkts_max", "Maximum packets to join") \
388   m(+1, u64 rx_coalesce_usecs, "rx_coalesce_usecs", "Limit in usec for joining rx packets") \
389   m(+1, u64 rx_coalesce_pkts, "rx_coalesce_pkts", "Maximum number of rx packets to join") \
390   m(+1, u64 rx_coalesce_mode, "rx_coalesce_mode", "0: EQE mode 1: CQE mode") \
391   m(+1, u64 tx_coalesce_usecs, "tx_coalesce_usecs", "Limit in usec for joining tx packets") \
392   m(+1, u64 tx_coalesce_pkts, "tx_coalesce_pkts", "Maximum number of tx packets to join") \
393   m(+1, u64 tx_coalesce_mode, "tx_coalesce_mode", "0: EQE mode 1: CQE mode") \
394   m(+1, u64 tx_completion_fact, "tx_completion_fact", "1..MAX: Completion event ratio") \
395   m(+1, u64 tx_completion_fact_max, "tx_completion_fact_max", "Maximum completion event ratio") \
396   m(+1, u64 hw_lro, "hw_lro", "set to enable hw_lro") \
397   m(+1, u64 cqe_zipping, "cqe_zipping", "0 : CQE zipping disabled")
398 
399 #define	MLX5E_PARAMS_NUM (0 MLX5E_PARAMS(MLX5E_STATS_COUNT))
400 
401 struct mlx5e_params_ethtool {
402 	u64	arg [0];
403 	MLX5E_PARAMS(MLX5E_STATS_VAR)
404 };
405 
406 /* EEPROM Standards for plug in modules */
407 #ifndef MLX5E_ETH_MODULE_SFF_8472
408 #define	MLX5E_ETH_MODULE_SFF_8472	0x1
409 #define	MLX5E_ETH_MODULE_SFF_8472_LEN	128
410 #endif
411 
412 #ifndef MLX5E_ETH_MODULE_SFF_8636
413 #define	MLX5E_ETH_MODULE_SFF_8636	0x2
414 #define	MLX5E_ETH_MODULE_SFF_8636_LEN	256
415 #endif
416 
417 #ifndef MLX5E_ETH_MODULE_SFF_8436
418 #define	MLX5E_ETH_MODULE_SFF_8436	0x3
419 #define	MLX5E_ETH_MODULE_SFF_8436_LEN	256
420 #endif
421 
422 /* EEPROM I2C Addresses */
423 #define	MLX5E_I2C_ADDR_LOW		0x50
424 #define	MLX5E_I2C_ADDR_HIGH		0x51
425 
426 #define	MLX5E_EEPROM_LOW_PAGE		0x0
427 #define	MLX5E_EEPROM_HIGH_PAGE		0x3
428 
429 #define	MLX5E_EEPROM_HIGH_PAGE_OFFSET	128
430 #define	MLX5E_EEPROM_PAGE_LENGTH	256
431 
432 #define	MLX5E_EEPROM_INFO_BYTES		0x3
433 
434 struct mlx5e_cq {
435 	/* data path - accessed per cqe */
436 	struct mlx5_cqwq wq;
437 
438 	/* data path - accessed per HW polling */
439 	struct mlx5_core_cq mcq;
440 	struct mlx5e_channel *channel;
441 
442 	/* control */
443 	struct mlx5_wq_ctrl wq_ctrl;
444 } __aligned(MLX5E_CACHELINE_SIZE);
445 
446 struct mlx5e_rq_mbuf {
447 	bus_dmamap_t	dma_map;
448 	caddr_t		data;
449 	struct mbuf	*mbuf;
450 };
451 
452 struct mlx5e_rq {
453 	/* data path */
454 	struct mlx5_wq_ll wq;
455 	struct mtx mtx;
456 	bus_dma_tag_t dma_tag;
457 	u32	wqe_sz;
458 	struct mlx5e_rq_mbuf *mbuf;
459 	struct device *pdev;
460 	struct ifnet *ifp;
461 	struct mlx5e_rq_stats stats;
462 	struct mlx5e_cq cq;
463 #ifdef HAVE_TURBO_LRO
464 	struct tlro_ctrl lro;
465 #else
466 	struct lro_ctrl lro;
467 #endif
468 	volatile int enabled;
469 	int	ix;
470 
471 	/* control */
472 	struct mlx5_wq_ctrl wq_ctrl;
473 	u32	rqn;
474 	struct mlx5e_channel *channel;
475 } __aligned(MLX5E_CACHELINE_SIZE);
476 
477 struct mlx5e_sq_mbuf {
478 	bus_dmamap_t dma_map;
479 	struct mbuf *mbuf;
480 	u32	num_bytes;
481 	u32	num_wqebbs;
482 };
483 
484 enum {
485 	MLX5E_SQ_READY,
486 	MLX5E_SQ_FULL
487 };
488 
489 struct mlx5e_sq {
490 	/* data path */
491 	struct	mtx lock;
492 	bus_dma_tag_t dma_tag;
493 	struct	mtx comp_lock;
494 
495 	/* dirtied @completion */
496 	u16	cc;
497 
498 	/* dirtied @xmit */
499 	u16	pc __aligned(MLX5E_CACHELINE_SIZE);
500 	u16	bf_offset;
501 	u16	cev_counter;		/* completion event counter */
502 	u16	cev_factor;		/* completion event factor */
503 	u32	cev_next_state;		/* next completion event state */
504 #define	MLX5E_CEV_STATE_INITIAL 0	/* timer not started */
505 #define	MLX5E_CEV_STATE_SEND_NOPS 1	/* send NOPs */
506 #define	MLX5E_CEV_STATE_HOLD_NOPS 2	/* don't send NOPs yet */
507 	struct callout cev_callout;
508 	union {
509 		u32	d32[2];
510 		u64	d64;
511 	} doorbell;
512 	struct	mlx5e_sq_stats stats;
513 
514 	struct	mlx5e_cq cq;
515 	struct	task sq_task;
516 	struct	taskqueue *sq_tq;
517 
518 	/* pointers to per packet info: write@xmit, read@completion */
519 	struct	mlx5e_sq_mbuf *mbuf;
520 	struct	buf_ring *br;
521 
522 	/* read only */
523 	struct	mlx5_wq_cyc wq;
524 	void	__iomem *uar_map;
525 	void	__iomem *uar_bf_map;
526 	u32	sqn;
527 	u32	bf_buf_size;
528 	struct  device *pdev;
529 	u32	mkey_be;
530 
531 	/* control path */
532 	struct	mlx5_wq_ctrl wq_ctrl;
533 	struct	mlx5_uar uar;
534 	struct	mlx5e_channel *channel;
535 	int	tc;
536 	unsigned int queue_state;
537 } __aligned(MLX5E_CACHELINE_SIZE);
538 
539 static inline bool
540 mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
541 {
542 	return ((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n ||
543 	    sq->cc == sq->pc);
544 }
545 
546 struct mlx5e_channel {
547 	/* data path */
548 	struct mlx5e_rq rq;
549 	struct mlx5e_sq sq[MLX5E_MAX_TX_NUM_TC];
550 	struct device *pdev;
551 	struct ifnet *ifp;
552 	u32	mkey_be;
553 	u8	num_tc;
554 
555 	/* control */
556 	struct mlx5e_priv *priv;
557 	int	ix;
558 	int	cpu;
559 } __aligned(MLX5E_CACHELINE_SIZE);
560 
561 enum mlx5e_traffic_types {
562 	MLX5E_TT_IPV4_TCP,
563 	MLX5E_TT_IPV6_TCP,
564 	MLX5E_TT_IPV4_UDP,
565 	MLX5E_TT_IPV6_UDP,
566 	MLX5E_TT_IPV4_IPSEC_AH,
567 	MLX5E_TT_IPV6_IPSEC_AH,
568 	MLX5E_TT_IPV4_IPSEC_ESP,
569 	MLX5E_TT_IPV6_IPSEC_ESP,
570 	MLX5E_TT_IPV4,
571 	MLX5E_TT_IPV6,
572 	MLX5E_TT_ANY,
573 	MLX5E_NUM_TT,
574 };
575 
576 enum {
577 	MLX5E_RQT_SPREADING = 0,
578 	MLX5E_RQT_DEFAULT_RQ = 1,
579 	MLX5E_NUM_RQT = 2,
580 };
581 
582 struct mlx5e_eth_addr_info {
583 	u8	addr [ETH_ALEN + 2];
584 	u32	tt_vec;
585 	u32	ft_ix[MLX5E_NUM_TT];	/* flow table index per traffic type */
586 };
587 
588 #define	MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE)
589 
590 struct mlx5e_eth_addr_hash_node;
591 
592 struct mlx5e_eth_addr_hash_head {
593 	struct mlx5e_eth_addr_hash_node *lh_first;
594 };
595 
596 struct mlx5e_eth_addr_db {
597 	struct mlx5e_eth_addr_hash_head if_uc[MLX5E_ETH_ADDR_HASH_SIZE];
598 	struct mlx5e_eth_addr_hash_head if_mc[MLX5E_ETH_ADDR_HASH_SIZE];
599 	struct mlx5e_eth_addr_info broadcast;
600 	struct mlx5e_eth_addr_info allmulti;
601 	struct mlx5e_eth_addr_info promisc;
602 	bool	broadcast_enabled;
603 	bool	allmulti_enabled;
604 	bool	promisc_enabled;
605 };
606 
607 enum {
608 	MLX5E_STATE_ASYNC_EVENTS_ENABLE,
609 	MLX5E_STATE_OPENED,
610 };
611 
612 struct mlx5e_vlan_db {
613 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
614 	u32	active_vlans_ft_ix[VLAN_N_VID];
615 	u32	untagged_rule_ft_ix;
616 	u32	any_vlan_rule_ft_ix;
617 	bool	filter_disabled;
618 };
619 
620 struct mlx5e_flow_table {
621 	void   *vlan;
622 	void   *main;
623 };
624 
625 struct mlx5e_priv {
626 	/* priv data path fields - start */
627 	int	order_base_2_num_channels;
628 	int	queue_mapping_channel_mask;
629 	int	num_tc;
630 	int	default_vlan_prio;
631 	/* priv data path fields - end */
632 
633 	unsigned long state;
634 	int	gone;
635 #define	PRIV_LOCK(priv) sx_xlock(&(priv)->state_lock)
636 #define	PRIV_UNLOCK(priv) sx_xunlock(&(priv)->state_lock)
637 #define	PRIV_LOCKED(priv) sx_xlocked(&(priv)->state_lock)
638 	struct sx state_lock;		/* Protects Interface state */
639 	struct mlx5_uar cq_uar;
640 	u32	pdn;
641 	u32	tdn;
642 	struct mlx5_core_mr mr;
643 
644 	struct mlx5e_channel *volatile *channel;
645 	u32	tisn[MLX5E_MAX_TX_NUM_TC];
646 	u32	rqtn;
647 	u32	tirn[MLX5E_NUM_TT];
648 
649 	struct mlx5e_flow_table ft;
650 	struct mlx5e_eth_addr_db eth_addr;
651 	struct mlx5e_vlan_db vlan;
652 
653 	struct mlx5e_params params;
654 	struct mlx5e_params_ethtool params_ethtool;
655 	struct mtx async_events_mtx;	/* sync hw events */
656 	struct work_struct update_stats_work;
657 	struct work_struct update_carrier_work;
658 	struct work_struct set_rx_mode_work;
659 
660 	struct mlx5_core_dev *mdev;
661 	struct ifnet *ifp;
662 	struct sysctl_ctx_list sysctl_ctx;
663 	struct sysctl_oid *sysctl_ifnet;
664 	struct sysctl_oid *sysctl_hw;
665 	int	sysctl_debug;
666 	struct mlx5e_stats stats;
667 	int	counter_set_id;
668 
669 	eventhandler_tag vlan_detach;
670 	eventhandler_tag vlan_attach;
671 	struct ifmedia media;
672 	int	media_status_last;
673 	int	media_active_last;
674 
675 	struct callout watchdog;
676 };
677 
678 #define	MLX5E_NET_IP_ALIGN 2
679 
680 struct mlx5e_tx_wqe {
681 	struct mlx5_wqe_ctrl_seg ctrl;
682 	struct mlx5_wqe_eth_seg eth;
683 };
684 
685 struct mlx5e_rx_wqe {
686 	struct mlx5_wqe_srq_next_seg next;
687 	struct mlx5_wqe_data_seg data;
688 };
689 
690 struct mlx5e_eeprom {
691 	int	lock_bit;
692 	int	i2c_addr;
693 	int	page_num;
694 	int	device_addr;
695 	int	module_num;
696 	int	len;
697 	int	type;
698 	int	page_valid;
699 	u32	*data;
700 };
701 
702 enum mlx5e_link_mode {
703 	MLX5E_1000BASE_CX_SGMII = 0,
704 	MLX5E_1000BASE_KX = 1,
705 	MLX5E_10GBASE_CX4 = 2,
706 	MLX5E_10GBASE_KX4 = 3,
707 	MLX5E_10GBASE_KR = 4,
708 	MLX5E_20GBASE_KR2 = 5,
709 	MLX5E_40GBASE_CR4 = 6,
710 	MLX5E_40GBASE_KR4 = 7,
711 	MLX5E_56GBASE_R4 = 8,
712 	MLX5E_10GBASE_CR = 12,
713 	MLX5E_10GBASE_SR = 13,
714 	MLX5E_10GBASE_LR = 14,
715 	MLX5E_40GBASE_SR4 = 15,
716 	MLX5E_40GBASE_LR4 = 16,
717 	MLX5E_100GBASE_CR4 = 20,
718 	MLX5E_100GBASE_SR4 = 21,
719 	MLX5E_100GBASE_KR4 = 22,
720 	MLX5E_100GBASE_LR4 = 23,
721 	MLX5E_100BASE_TX = 24,
722 	MLX5E_100BASE_T = 25,
723 	MLX5E_10GBASE_T = 26,
724 	MLX5E_25GBASE_CR = 27,
725 	MLX5E_25GBASE_KR = 28,
726 	MLX5E_25GBASE_SR = 29,
727 	MLX5E_50GBASE_CR2 = 30,
728 	MLX5E_50GBASE_KR2 = 31,
729 	MLX5E_LINK_MODES_NUMBER,
730 };
731 
732 #define	MLX5E_PROT_MASK(link_mode) (1 << (link_mode))
733 #define	MLX5E_FLD_MAX(typ, fld) ((1ULL << __mlx5_bit_sz(typ, fld)) - 1ULL)
734 
735 int	mlx5e_xmit(struct ifnet *, struct mbuf *);
736 
737 int	mlx5e_open_locked(struct ifnet *);
738 int	mlx5e_close_locked(struct ifnet *);
739 
740 void	mlx5e_cq_error_event(struct mlx5_core_cq *mcq, int event);
741 void	mlx5e_rx_cq_comp(struct mlx5_core_cq *);
742 void	mlx5e_tx_cq_comp(struct mlx5_core_cq *);
743 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
744 void	mlx5e_tx_que(void *context, int pending);
745 
746 int	mlx5e_open_flow_table(struct mlx5e_priv *priv);
747 void	mlx5e_close_flow_table(struct mlx5e_priv *priv);
748 void	mlx5e_set_rx_mode_core(struct mlx5e_priv *priv);
749 void	mlx5e_set_rx_mode_work(struct work_struct *work);
750 
751 void	mlx5e_vlan_rx_add_vid(void *, struct ifnet *, u16);
752 void	mlx5e_vlan_rx_kill_vid(void *, struct ifnet *, u16);
753 void	mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
754 void	mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
755 int	mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv);
756 void	mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv);
757 
758 static inline void
759 mlx5e_tx_notify_hw(struct mlx5e_sq *sq, u32 *wqe, int bf_sz)
760 {
761 	u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
762 
763 	/* ensure wqe is visible to device before updating doorbell record */
764 	wmb();
765 
766 	*sq->wq.db = cpu_to_be32(sq->pc);
767 
768 	/*
769 	 * Ensure the doorbell record is visible to device before ringing
770 	 * the doorbell:
771 	 */
772 	wmb();
773 
774 	if (bf_sz) {
775 		__iowrite64_copy(sq->uar_bf_map + ofst, wqe, bf_sz);
776 
777 		/* flush the write-combining mapped buffer */
778 		wmb();
779 
780 	} else {
781 		mlx5_write64(wqe, sq->uar_map + ofst, NULL);
782 	}
783 
784 	sq->bf_offset ^= sq->bf_buf_size;
785 }
786 
787 static inline void
788 mlx5e_cq_arm(struct mlx5e_cq *cq)
789 {
790 	struct mlx5_core_cq *mcq;
791 
792 	mcq = &cq->mcq;
793 	mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
794 }
795 
796 extern const struct ethtool_ops mlx5e_ethtool_ops;
797 void	mlx5e_create_ethtool(struct mlx5e_priv *);
798 void	mlx5e_create_stats(struct sysctl_ctx_list *,
799     struct sysctl_oid_list *, const char *,
800     const char **, unsigned, u64 *);
801 void	mlx5e_send_nop(struct mlx5e_sq *, u32);
802 void	mlx5e_sq_cev_timeout(void *);
803 int	mlx5e_refresh_channel_params(struct mlx5e_priv *);
804 
805 #endif					/* _MLX5_EN_H_ */
806