1 /*- 2 * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef _MLX5_EN_H_ 29 #define _MLX5_EN_H_ 30 31 #include <linux/kmod.h> 32 #include <linux/page.h> 33 #include <linux/slab.h> 34 #include <linux/if_vlan.h> 35 #include <linux/if_ether.h> 36 #include <linux/vmalloc.h> 37 #include <linux/moduleparam.h> 38 #include <linux/delay.h> 39 #include <linux/netdevice.h> 40 #include <linux/etherdevice.h> 41 #include <linux/ktime.h> 42 #include <linux/net_dim.h> 43 44 #include <netinet/in_systm.h> 45 #include <netinet/in.h> 46 #include <netinet/if_ether.h> 47 #include <netinet/ip.h> 48 #include <netinet/ip6.h> 49 #include <netinet/tcp.h> 50 #include <netinet/tcp_lro.h> 51 #include <netinet/udp.h> 52 #include <net/ethernet.h> 53 #include <net/pfil.h> 54 #include <sys/buf_ring.h> 55 #include <sys/kthread.h> 56 57 #include "opt_rss.h" 58 59 #ifdef RSS 60 #include <net/rss_config.h> 61 #include <netinet/in_rss.h> 62 #endif 63 64 #include <machine/bus.h> 65 66 #include <dev/mlx5/driver.h> 67 #include <dev/mlx5/qp.h> 68 #include <dev/mlx5/cq.h> 69 #include <dev/mlx5/port.h> 70 #include <dev/mlx5/vport.h> 71 #include <dev/mlx5/diagnostics.h> 72 73 #include <dev/mlx5/mlx5_core/wq.h> 74 #include <dev/mlx5/mlx5_core/transobj.h> 75 #include <dev/mlx5/mlx5_core/mlx5_core.h> 76 77 #define MLX5E_MAX_PRIORITY 8 78 79 /* IEEE 802.1Qaz standard supported values */ 80 #define IEEE_8021QAZ_MAX_TCS 8 81 82 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x7 83 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa 84 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xe 85 86 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x7 87 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa 88 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xe 89 90 #define MLX5E_MAX_RX_SEGS 7 91 92 #ifndef MLX5E_MAX_RX_BYTES 93 #define MLX5E_MAX_RX_BYTES MCLBYTES 94 #endif 95 96 #if (MLX5E_MAX_RX_SEGS == 1) 97 /* FreeBSD HW LRO is limited by 16KB - the size of max mbuf */ 98 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ MJUM16BYTES 99 #else 100 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ \ 101 MIN(65535, MLX5E_MAX_RX_SEGS * MLX5E_MAX_RX_BYTES) 102 #endif 103 #define MLX5E_DIM_DEFAULT_PROFILE 3 104 #define MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO 16 105 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 106 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 107 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 108 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 109 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 110 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 111 #define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ 0x7 112 #define MLX5E_CACHELINE_SIZE CACHE_LINE_SIZE 113 #define MLX5E_HW2SW_MTU(hwmtu) \ 114 ((hwmtu) - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 115 #define MLX5E_SW2HW_MTU(swmtu) \ 116 ((swmtu) + (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN)) 117 #define MLX5E_SW2MB_MTU(swmtu) \ 118 (MLX5E_SW2HW_MTU(swmtu) + MLX5E_NET_IP_ALIGN) 119 #define MLX5E_MTU_MIN 72 /* Min MTU allowed by the kernel */ 120 #define MLX5E_MTU_MAX MIN(ETHERMTU_JUMBO, MJUM16BYTES) /* Max MTU of Ethernet 121 * jumbo frames */ 122 123 #define MLX5E_BUDGET_MAX 8192 /* RX and TX */ 124 #define MLX5E_RX_BUDGET_MAX 256 125 #define MLX5E_SQ_BF_BUDGET 16 126 #define MLX5E_SQ_TX_QUEUE_SIZE 4096 /* SQ drbr queue size */ 127 128 #define MLX5E_MAX_TX_NUM_TC 8 /* units */ 129 #define MLX5E_MAX_TX_HEADER 128 /* bytes */ 130 #define MLX5E_MAX_TX_PAYLOAD_SIZE 65536 /* bytes */ 131 #define MLX5E_MAX_TX_MBUF_SIZE 65536 /* bytes */ 132 #define MLX5E_MAX_TX_MBUF_FRAGS \ 133 ((MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS) - \ 134 (MLX5E_MAX_TX_HEADER / MLX5_SEND_WQE_DS) - \ 135 1 /* the maximum value of the DS counter is 0x3F and not 0x40 */) /* units */ 136 #define MLX5E_MAX_TX_INLINE \ 137 (MLX5E_MAX_TX_HEADER - sizeof(struct mlx5e_tx_wqe) + \ 138 sizeof(((struct mlx5e_tx_wqe *)0)->eth.inline_hdr_start)) /* bytes */ 139 140 #define MLX5E_100MB (100000) 141 #define MLX5E_1GB (1000000) 142 143 MALLOC_DECLARE(M_MLX5EN); 144 145 struct mlx5_core_dev; 146 struct mlx5e_cq; 147 148 typedef void (mlx5e_cq_comp_t)(struct mlx5_core_cq *); 149 150 #define MLX5E_STATS_COUNT(a,b,c,d) a 151 #define MLX5E_STATS_VAR(a,b,c,d) b; 152 #define MLX5E_STATS_DESC(a,b,c,d) c, d, 153 154 #define MLX5E_VPORT_STATS(m) \ 155 /* HW counters */ \ 156 m(+1, u64 rx_packets, "rx_packets", "Received packets") \ 157 m(+1, u64 rx_bytes, "rx_bytes", "Received bytes") \ 158 m(+1, u64 tx_packets, "tx_packets", "Transmitted packets") \ 159 m(+1, u64 tx_bytes, "tx_bytes", "Transmitted bytes") \ 160 m(+1, u64 rx_error_packets, "rx_error_packets", "Received error packets") \ 161 m(+1, u64 rx_error_bytes, "rx_error_bytes", "Received error bytes") \ 162 m(+1, u64 tx_error_packets, "tx_error_packets", "Transmitted error packets") \ 163 m(+1, u64 tx_error_bytes, "tx_error_bytes", "Transmitted error bytes") \ 164 m(+1, u64 rx_unicast_packets, "rx_unicast_packets", "Received unicast packets") \ 165 m(+1, u64 rx_unicast_bytes, "rx_unicast_bytes", "Received unicast bytes") \ 166 m(+1, u64 tx_unicast_packets, "tx_unicast_packets", "Transmitted unicast packets") \ 167 m(+1, u64 tx_unicast_bytes, "tx_unicast_bytes", "Transmitted unicast bytes") \ 168 m(+1, u64 rx_multicast_packets, "rx_multicast_packets", "Received multicast packets") \ 169 m(+1, u64 rx_multicast_bytes, "rx_multicast_bytes", "Received multicast bytes") \ 170 m(+1, u64 tx_multicast_packets, "tx_multicast_packets", "Transmitted multicast packets") \ 171 m(+1, u64 tx_multicast_bytes, "tx_multicast_bytes", "Transmitted multicast bytes") \ 172 m(+1, u64 rx_broadcast_packets, "rx_broadcast_packets", "Received broadcast packets") \ 173 m(+1, u64 rx_broadcast_bytes, "rx_broadcast_bytes", "Received broadcast bytes") \ 174 m(+1, u64 tx_broadcast_packets, "tx_broadcast_packets", "Transmitted broadcast packets") \ 175 m(+1, u64 tx_broadcast_bytes, "tx_broadcast_bytes", "Transmitted broadcast bytes") \ 176 m(+1, u64 rx_out_of_buffer, "rx_out_of_buffer", "Receive out of buffer, no recv wqes events") \ 177 /* SW counters */ \ 178 m(+1, u64 tso_packets, "tso_packets", "Transmitted TSO packets") \ 179 m(+1, u64 tso_bytes, "tso_bytes", "Transmitted TSO bytes") \ 180 m(+1, u64 lro_packets, "lro_packets", "Received LRO packets") \ 181 m(+1, u64 lro_bytes, "lro_bytes", "Received LRO bytes") \ 182 m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 183 m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 184 m(+1, u64 rx_csum_good, "rx_csum_good", "Received checksum valid packets") \ 185 m(+1, u64 rx_csum_none, "rx_csum_none", "Received no checksum packets") \ 186 m(+1, u64 tx_csum_offload, "tx_csum_offload", "Transmit checksum offload packets") \ 187 m(+1, u64 tx_queue_dropped, "tx_queue_dropped", "Transmit queue dropped") \ 188 m(+1, u64 tx_defragged, "tx_defragged", "Transmit queue defragged") \ 189 m(+1, u64 rx_wqe_err, "rx_wqe_err", "Receive WQE errors") \ 190 m(+1, u64 tx_jumbo_packets, "tx_jumbo_packets", "TX packets greater than 1518 octets") \ 191 m(+1, u64 rx_steer_missed_packets, "rx_steer_missed_packets", "RX packets dropped by steering rule(s)") 192 193 #define MLX5E_VPORT_STATS_NUM (0 MLX5E_VPORT_STATS(MLX5E_STATS_COUNT)) 194 195 struct mlx5e_vport_stats { 196 struct sysctl_ctx_list ctx; 197 u64 arg [0]; 198 MLX5E_VPORT_STATS(MLX5E_STATS_VAR) 199 }; 200 201 #define MLX5E_PPORT_IEEE802_3_STATS(m) \ 202 m(+1, u64 frames_tx, "frames_tx", "Frames transmitted") \ 203 m(+1, u64 frames_rx, "frames_rx", "Frames received") \ 204 m(+1, u64 check_seq_err, "check_seq_err", "Sequence errors") \ 205 m(+1, u64 alignment_err, "alignment_err", "Alignment errors") \ 206 m(+1, u64 octets_tx, "octets_tx", "Bytes transmitted") \ 207 m(+1, u64 octets_received, "octets_received", "Bytes received") \ 208 m(+1, u64 multicast_xmitted, "multicast_xmitted", "Multicast transmitted") \ 209 m(+1, u64 broadcast_xmitted, "broadcast_xmitted", "Broadcast transmitted") \ 210 m(+1, u64 multicast_rx, "multicast_rx", "Multicast received") \ 211 m(+1, u64 broadcast_rx, "broadcast_rx", "Broadcast received") \ 212 m(+1, u64 in_range_len_errors, "in_range_len_errors", "In range length errors") \ 213 m(+1, u64 out_of_range_len, "out_of_range_len", "Out of range length errors") \ 214 m(+1, u64 too_long_errors, "too_long_errors", "Too long errors") \ 215 m(+1, u64 symbol_err, "symbol_err", "Symbol errors") \ 216 m(+1, u64 mac_control_tx, "mac_control_tx", "MAC control transmitted") \ 217 m(+1, u64 mac_control_rx, "mac_control_rx", "MAC control received") \ 218 m(+1, u64 unsupported_op_rx, "unsupported_op_rx", "Unsupported operation received") \ 219 m(+1, u64 pause_ctrl_rx, "pause_ctrl_rx", "Pause control received") \ 220 m(+1, u64 pause_ctrl_tx, "pause_ctrl_tx", "Pause control transmitted") 221 222 #define MLX5E_PPORT_RFC2819_STATS(m) \ 223 m(+1, u64 drop_events, "drop_events", "Dropped events") \ 224 m(+1, u64 octets, "octets", "Octets") \ 225 m(+1, u64 pkts, "pkts", "Packets") \ 226 m(+1, u64 broadcast_pkts, "broadcast_pkts", "Broadcast packets") \ 227 m(+1, u64 multicast_pkts, "multicast_pkts", "Multicast packets") \ 228 m(+1, u64 crc_align_errors, "crc_align_errors", "CRC alignment errors") \ 229 m(+1, u64 undersize_pkts, "undersize_pkts", "Undersized packets") \ 230 m(+1, u64 oversize_pkts, "oversize_pkts", "Oversized packets") \ 231 m(+1, u64 fragments, "fragments", "Fragments") \ 232 m(+1, u64 jabbers, "jabbers", "Jabbers") \ 233 m(+1, u64 collisions, "collisions", "Collisions") 234 235 #define MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 236 m(+1, u64 p64octets, "p64octets", "Bytes") \ 237 m(+1, u64 p65to127octets, "p65to127octets", "Bytes") \ 238 m(+1, u64 p128to255octets, "p128to255octets", "Bytes") \ 239 m(+1, u64 p256to511octets, "p256to511octets", "Bytes") \ 240 m(+1, u64 p512to1023octets, "p512to1023octets", "Bytes") \ 241 m(+1, u64 p1024to1518octets, "p1024to1518octets", "Bytes") \ 242 m(+1, u64 p1519to2047octets, "p1519to2047octets", "Bytes") \ 243 m(+1, u64 p2048to4095octets, "p2048to4095octets", "Bytes") \ 244 m(+1, u64 p4096to8191octets, "p4096to8191octets", "Bytes") \ 245 m(+1, u64 p8192to10239octets, "p8192to10239octets", "Bytes") 246 247 #define MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 248 m(+1, u64 in_octets, "in_octets", "In octets") \ 249 m(+1, u64 in_ucast_pkts, "in_ucast_pkts", "In unicast packets") \ 250 m(+1, u64 in_discards, "in_discards", "In discards") \ 251 m(+1, u64 in_errors, "in_errors", "In errors") \ 252 m(+1, u64 in_unknown_protos, "in_unknown_protos", "In unknown protocols") \ 253 m(+1, u64 out_octets, "out_octets", "Out octets") \ 254 m(+1, u64 out_ucast_pkts, "out_ucast_pkts", "Out unicast packets") \ 255 m(+1, u64 out_discards, "out_discards", "Out discards") \ 256 m(+1, u64 out_errors, "out_errors", "Out errors") \ 257 m(+1, u64 in_multicast_pkts, "in_multicast_pkts", "In multicast packets") \ 258 m(+1, u64 in_broadcast_pkts, "in_broadcast_pkts", "In broadcast packets") \ 259 m(+1, u64 out_multicast_pkts, "out_multicast_pkts", "Out multicast packets") \ 260 m(+1, u64 out_broadcast_pkts, "out_broadcast_pkts", "Out broadcast packets") 261 262 #define MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(m) \ 263 m(+1, u64 port_transmit_wait_high, "port_transmit_wait_high", "Port transmit wait high") \ 264 m(+1, u64 ecn_marked, "ecn_marked", "ECN marked") \ 265 m(+1, u64 no_buffer_discard_mc, "no_buffer_discard_mc", "No buffer discard mc") \ 266 m(+1, u64 rx_ebp, "rx_ebp", "RX EBP") \ 267 m(+1, u64 tx_ebp, "tx_ebp", "TX EBP") \ 268 m(+1, u64 rx_buffer_almost_full, "rx_buffer_almost_full", "RX buffer almost full") \ 269 m(+1, u64 rx_buffer_full, "rx_buffer_full", "RX buffer full") \ 270 m(+1, u64 rx_icrc_encapsulated, "rx_icrc_encapsulated", "RX ICRC encapsulated") \ 271 m(+1, u64 ex_reserved_0, "ex_reserved_0", "Reserved") \ 272 m(+1, u64 ex_reserved_1, "ex_reserved_1", "Reserved") \ 273 m(+1, u64 tx_stat_p64octets, "tx_stat_p64octets", "Bytes") \ 274 m(+1, u64 tx_stat_p65to127octets, "tx_stat_p65to127octets", "Bytes") \ 275 m(+1, u64 tx_stat_p128to255octets, "tx_stat_p128to255octets", "Bytes") \ 276 m(+1, u64 tx_stat_p256to511octets, "tx_stat_p256to511octets", "Bytes") \ 277 m(+1, u64 tx_stat_p512to1023octets, "tx_stat_p512to1023octets", "Bytes") \ 278 m(+1, u64 tx_stat_p1024to1518octets, "tx_stat_p1024to1518octets", "Bytes") \ 279 m(+1, u64 tx_stat_p1519to2047octets, "tx_stat_p1519to2047octets", "Bytes") \ 280 m(+1, u64 tx_stat_p2048to4095octets, "tx_stat_p2048to4095octets", "Bytes") \ 281 m(+1, u64 tx_stat_p4096to8191octets, "tx_stat_p4096to8191octets", "Bytes") \ 282 m(+1, u64 tx_stat_p8192to10239octets, "tx_stat_p8192to10239octets", "Bytes") 283 284 #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \ 285 m(+1, u64 time_since_last_clear, "time_since_last_clear", \ 286 "Time since the last counters clear event (msec)") \ 287 m(+1, u64 symbol_errors, "symbol_errors", "Symbol errors") \ 288 m(+1, u64 sync_headers_errors, "sync_headers_errors", "Sync header error counter") \ 289 m(+1, u64 bip_errors_lane0, "edpl_bip_errors_lane0", \ 290 "Indicates the number of PRBS errors on lane 0") \ 291 m(+1, u64 bip_errors_lane1, "edpl_bip_errors_lane1", \ 292 "Indicates the number of PRBS errors on lane 1") \ 293 m(+1, u64 bip_errors_lane2, "edpl_bip_errors_lane2", \ 294 "Indicates the number of PRBS errors on lane 2") \ 295 m(+1, u64 bip_errors_lane3, "edpl_bip_errors_lane3", \ 296 "Indicates the number of PRBS errors on lane 3") \ 297 m(+1, u64 fc_corrected_blocks_lane0, "fc_corrected_blocks_lane0", \ 298 "FEC correctable block counter lane 0") \ 299 m(+1, u64 fc_corrected_blocks_lane1, "fc_corrected_blocks_lane1", \ 300 "FEC correctable block counter lane 1") \ 301 m(+1, u64 fc_corrected_blocks_lane2, "fc_corrected_blocks_lane2", \ 302 "FEC correctable block counter lane 2") \ 303 m(+1, u64 fc_corrected_blocks_lane3, "fc_corrected_blocks_lane3", \ 304 "FEC correctable block counter lane 3") \ 305 m(+1, u64 rs_corrected_blocks, "rs_corrected_blocks", \ 306 "FEC correcable block counter") \ 307 m(+1, u64 rs_uncorrectable_blocks, "rs_uncorrectable_blocks", \ 308 "FEC uncorrecable block counter") \ 309 m(+1, u64 rs_no_errors_blocks, "rs_no_errors_blocks", \ 310 "The number of RS-FEC blocks received that had no errors") \ 311 m(+1, u64 rs_single_error_blocks, "rs_single_error_blocks", \ 312 "The number of corrected RS-FEC blocks received that had" \ 313 "exactly 1 error symbol") \ 314 m(+1, u64 rs_corrected_symbols_total, "rs_corrected_symbols_total", \ 315 "Port FEC corrected symbol counter") \ 316 m(+1, u64 rs_corrected_symbols_lane0, "rs_corrected_symbols_lane0", \ 317 "FEC corrected symbol counter lane 0") \ 318 m(+1, u64 rs_corrected_symbols_lane1, "rs_corrected_symbols_lane1", \ 319 "FEC corrected symbol counter lane 1") \ 320 m(+1, u64 rs_corrected_symbols_lane2, "rs_corrected_symbols_lane2", \ 321 "FEC corrected symbol counter lane 2") \ 322 m(+1, u64 rs_corrected_symbols_lane3, "rs_corrected_symbols_lane3", \ 323 "FEC corrected symbol counter lane 3") 324 325 /* Per priority statistics for PFC */ 326 #define MLX5E_PPORT_PER_PRIO_STATS_SUB(m,n,p) \ 327 m(n, p, +1, u64, rx_octets, "rx_octets", "Received octets") \ 328 m(n, p, +1, u64, reserved_0, "reserved_0", "Reserved") \ 329 m(n, p, +1, u64, reserved_1, "reserved_1", "Reserved") \ 330 m(n, p, +1, u64, reserved_2, "reserved_2", "Reserved") \ 331 m(n, p, +1, u64, rx_frames, "rx_frames", "Received frames") \ 332 m(n, p, +1, u64, tx_octets, "tx_octets", "Transmitted octets") \ 333 m(n, p, +1, u64, reserved_3, "reserved_3", "Reserved") \ 334 m(n, p, +1, u64, reserved_4, "reserved_4", "Reserved") \ 335 m(n, p, +1, u64, reserved_5, "reserved_5", "Reserved") \ 336 m(n, p, +1, u64, tx_frames, "tx_frames", "Transmitted frames") \ 337 m(n, p, +1, u64, rx_pause, "rx_pause", "Received pause frames") \ 338 m(n, p, +1, u64, rx_pause_duration, "rx_pause_duration", \ 339 "Received pause duration") \ 340 m(n, p, +1, u64, tx_pause, "tx_pause", "Transmitted pause frames") \ 341 m(n, p, +1, u64, tx_pause_duration, "tx_pause_duration", \ 342 "Transmitted pause duration") \ 343 m(n, p, +1, u64, rx_pause_transition, "rx_pause_transition", \ 344 "Received pause transitions") \ 345 m(n, p, +1, u64, rx_discards, "rx_discards", "Discarded received frames") \ 346 m(n, p, +1, u64, device_stall_minor_watermark, \ 347 "device_stall_minor_watermark", "Device stall minor watermark") \ 348 m(n, p, +1, u64, device_stall_critical_watermark, \ 349 "device_stall_critical_watermark", "Device stall critical watermark") 350 351 #define MLX5E_PPORT_PER_PRIO_STATS_PREFIX(m,p,c,t,f,s,d) \ 352 m(c, t pri_##p##_##f, "prio" #p "_" s, "Priority " #p " - " d) 353 354 #define MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO 8 355 356 #define MLX5E_PPORT_PER_PRIO_STATS(m) \ 357 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,0) \ 358 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,1) \ 359 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,2) \ 360 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,3) \ 361 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,4) \ 362 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,5) \ 363 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,6) \ 364 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,7) 365 366 /* 367 * Make sure to update mlx5e_update_pport_counters() 368 * when adding a new MLX5E_PPORT_STATS block 369 */ 370 #define MLX5E_PPORT_STATS(m) \ 371 MLX5E_PPORT_PER_PRIO_STATS(m) \ 372 MLX5E_PPORT_IEEE802_3_STATS(m) \ 373 MLX5E_PPORT_RFC2819_STATS(m) 374 375 #define MLX5E_PORT_STATS_DEBUG(m) \ 376 MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \ 377 MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \ 378 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \ 379 MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(m) 380 381 #define MLX5E_PPORT_IEEE802_3_STATS_NUM \ 382 (0 MLX5E_PPORT_IEEE802_3_STATS(MLX5E_STATS_COUNT)) 383 #define MLX5E_PPORT_RFC2819_STATS_NUM \ 384 (0 MLX5E_PPORT_RFC2819_STATS(MLX5E_STATS_COUNT)) 385 #define MLX5E_PPORT_STATS_NUM \ 386 (0 MLX5E_PPORT_STATS(MLX5E_STATS_COUNT)) 387 388 #define MLX5E_PPORT_PER_PRIO_STATS_NUM \ 389 (0 MLX5E_PPORT_PER_PRIO_STATS(MLX5E_STATS_COUNT)) 390 #define MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM \ 391 (0 MLX5E_PPORT_RFC2819_STATS_DEBUG(MLX5E_STATS_COUNT)) 392 #define MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM \ 393 (0 MLX5E_PPORT_RFC2863_STATS_DEBUG(MLX5E_STATS_COUNT)) 394 #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM \ 395 (0 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(MLX5E_STATS_COUNT)) 396 #define MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM \ 397 (0 MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(MLX5E_STATS_COUNT)) 398 #define MLX5E_PORT_STATS_DEBUG_NUM \ 399 (0 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_COUNT)) 400 401 struct mlx5e_pport_stats { 402 struct sysctl_ctx_list ctx; 403 u64 arg [0]; 404 MLX5E_PPORT_STATS(MLX5E_STATS_VAR) 405 }; 406 407 struct mlx5e_port_stats_debug { 408 struct sysctl_ctx_list ctx; 409 u64 arg [0]; 410 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_VAR) 411 }; 412 413 #define MLX5E_RQ_STATS(m) \ 414 m(+1, u64 packets, "packets", "Received packets") \ 415 m(+1, u64 bytes, "bytes", "Received bytes") \ 416 m(+1, u64 csum_none, "csum_none", "Received packets") \ 417 m(+1, u64 lro_packets, "lro_packets", "Received LRO packets") \ 418 m(+1, u64 lro_bytes, "lro_bytes", "Received LRO bytes") \ 419 m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \ 420 m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \ 421 m(+1, u64 wqe_err, "wqe_err", "Received packets") 422 423 #define MLX5E_RQ_STATS_NUM (0 MLX5E_RQ_STATS(MLX5E_STATS_COUNT)) 424 425 struct mlx5e_rq_stats { 426 struct sysctl_ctx_list ctx; 427 u64 arg [0]; 428 MLX5E_RQ_STATS(MLX5E_STATS_VAR) 429 }; 430 431 #define MLX5E_SQ_STATS(m) \ 432 m(+1, u64 packets, "packets", "Transmitted packets") \ 433 m(+1, u64 bytes, "bytes", "Transmitted bytes") \ 434 m(+1, u64 tso_packets, "tso_packets", "Transmitted packets") \ 435 m(+1, u64 tso_bytes, "tso_bytes", "Transmitted bytes") \ 436 m(+1, u64 csum_offload_none, "csum_offload_none", "Transmitted packets") \ 437 m(+1, u64 defragged, "defragged", "Transmitted packets") \ 438 m(+1, u64 dropped, "dropped", "Transmitted packets") \ 439 m(+1, u64 nop, "nop", "Transmitted packets") 440 441 #define MLX5E_SQ_STATS_NUM (0 MLX5E_SQ_STATS(MLX5E_STATS_COUNT)) 442 443 struct mlx5e_sq_stats { 444 struct sysctl_ctx_list ctx; 445 u64 arg [0]; 446 MLX5E_SQ_STATS(MLX5E_STATS_VAR) 447 }; 448 449 struct mlx5e_stats { 450 struct mlx5e_vport_stats vport; 451 struct mlx5e_pport_stats pport; 452 struct mlx5e_port_stats_debug port_stats_debug; 453 }; 454 455 struct mlx5e_rq_param { 456 u32 rqc [MLX5_ST_SZ_DW(rqc)]; 457 struct mlx5_wq_param wq; 458 }; 459 460 struct mlx5e_sq_param { 461 u32 sqc [MLX5_ST_SZ_DW(sqc)]; 462 struct mlx5_wq_param wq; 463 }; 464 465 struct mlx5e_cq_param { 466 u32 cqc [MLX5_ST_SZ_DW(cqc)]; 467 struct mlx5_wq_param wq; 468 }; 469 470 struct mlx5e_params { 471 u8 log_sq_size; 472 u8 log_rq_size; 473 u16 num_channels; 474 u8 default_vlan_prio; 475 u8 num_tc; 476 u8 rx_cq_moderation_mode; 477 u8 tx_cq_moderation_mode; 478 u16 rx_cq_moderation_usec; 479 u16 rx_cq_moderation_pkts; 480 u16 tx_cq_moderation_usec; 481 u16 tx_cq_moderation_pkts; 482 u16 min_rx_wqes; 483 bool hw_lro_en; 484 bool cqe_zipping_en; 485 u32 lro_wqe_sz; 486 u16 rx_hash_log_tbl_sz; 487 u32 tx_pauseframe_control __aligned(4); 488 u32 rx_pauseframe_control __aligned(4); 489 u16 tx_max_inline; 490 u8 tx_min_inline_mode; 491 u8 tx_priority_flow_control; 492 u8 rx_priority_flow_control; 493 u8 channels_rsss; 494 }; 495 496 #define MLX5E_PARAMS(m) \ 497 m(+1, u64 tx_queue_size_max, "tx_queue_size_max", "Max send queue size") \ 498 m(+1, u64 rx_queue_size_max, "rx_queue_size_max", "Max receive queue size") \ 499 m(+1, u64 tx_queue_size, "tx_queue_size", "Default send queue size") \ 500 m(+1, u64 rx_queue_size, "rx_queue_size", "Default receive queue size") \ 501 m(+1, u64 channels, "channels", "Default number of channels") \ 502 m(+1, u64 channels_rsss, "channels_rsss", "Default channels receive side scaling stride") \ 503 m(+1, u64 coalesce_usecs_max, "coalesce_usecs_max", "Maximum usecs for joining packets") \ 504 m(+1, u64 coalesce_pkts_max, "coalesce_pkts_max", "Maximum packets to join") \ 505 m(+1, u64 rx_coalesce_usecs, "rx_coalesce_usecs", "Limit in usec for joining rx packets") \ 506 m(+1, u64 rx_coalesce_pkts, "rx_coalesce_pkts", "Maximum number of rx packets to join") \ 507 m(+1, u64 rx_coalesce_mode, "rx_coalesce_mode", "0: EQE fixed mode 1: CQE fixed mode 2: EQE auto mode 3: CQE auto mode") \ 508 m(+1, u64 tx_coalesce_usecs, "tx_coalesce_usecs", "Limit in usec for joining tx packets") \ 509 m(+1, u64 tx_coalesce_pkts, "tx_coalesce_pkts", "Maximum number of tx packets to join") \ 510 m(+1, u64 tx_coalesce_mode, "tx_coalesce_mode", "0: EQE mode 1: CQE mode") \ 511 m(+1, u64 tx_completion_fact, "tx_completion_fact", "1..MAX: Completion event ratio") \ 512 m(+1, u64 tx_completion_fact_max, "tx_completion_fact_max", "Maximum completion event ratio") \ 513 m(+1, u64 hw_lro, "hw_lro", "set to enable hw_lro") \ 514 m(+1, u64 cqe_zipping, "cqe_zipping", "0 : CQE zipping disabled") \ 515 m(+1, u64 modify_tx_dma, "modify_tx_dma", "0: Enable TX 1: Disable TX") \ 516 m(+1, u64 modify_rx_dma, "modify_rx_dma", "0: Enable RX 1: Disable RX") \ 517 m(+1, u64 diag_pci_enable, "diag_pci_enable", "0: Disabled 1: Enabled") \ 518 m(+1, u64 diag_general_enable, "diag_general_enable", "0: Disabled 1: Enabled") \ 519 m(+1, u64 hw_mtu, "hw_mtu", "Current hardware MTU value") \ 520 m(+1, u64 mc_local_lb, "mc_local_lb", "0: Local multicast loopback enabled 1: Disabled") \ 521 m(+1, u64 uc_local_lb, "uc_local_lb", "0: Local unicast loopback enabled 1: Disabled") 522 523 524 #define MLX5E_PARAMS_NUM (0 MLX5E_PARAMS(MLX5E_STATS_COUNT)) 525 526 struct mlx5e_params_ethtool { 527 u64 arg [0]; 528 MLX5E_PARAMS(MLX5E_STATS_VAR) 529 u64 max_bw_value[IEEE_8021QAZ_MAX_TCS]; 530 u8 max_bw_share[IEEE_8021QAZ_MAX_TCS]; 531 u8 prio_tc[MLX5E_MAX_PRIORITY]; 532 u8 dscp2prio[MLX5_MAX_SUPPORTED_DSCP]; 533 u8 trust_state; 534 }; 535 536 /* EEPROM Standards for plug in modules */ 537 #ifndef MLX5E_ETH_MODULE_SFF_8472 538 #define MLX5E_ETH_MODULE_SFF_8472 0x1 539 #define MLX5E_ETH_MODULE_SFF_8472_LEN 128 540 #endif 541 542 #ifndef MLX5E_ETH_MODULE_SFF_8636 543 #define MLX5E_ETH_MODULE_SFF_8636 0x2 544 #define MLX5E_ETH_MODULE_SFF_8636_LEN 256 545 #endif 546 547 #ifndef MLX5E_ETH_MODULE_SFF_8436 548 #define MLX5E_ETH_MODULE_SFF_8436 0x3 549 #define MLX5E_ETH_MODULE_SFF_8436_LEN 256 550 #endif 551 552 /* EEPROM I2C Addresses */ 553 #define MLX5E_I2C_ADDR_LOW 0x50 554 #define MLX5E_I2C_ADDR_HIGH 0x51 555 556 #define MLX5E_EEPROM_LOW_PAGE 0x0 557 #define MLX5E_EEPROM_HIGH_PAGE 0x3 558 559 #define MLX5E_EEPROM_HIGH_PAGE_OFFSET 128 560 #define MLX5E_EEPROM_PAGE_LENGTH 256 561 562 #define MLX5E_EEPROM_INFO_BYTES 0x3 563 564 struct mlx5e_cq { 565 /* data path - accessed per cqe */ 566 struct mlx5_cqwq wq; 567 568 /* data path - accessed per HW polling */ 569 struct mlx5_core_cq mcq; 570 571 /* control */ 572 struct mlx5e_priv *priv; 573 struct mlx5_wq_ctrl wq_ctrl; 574 } __aligned(MLX5E_CACHELINE_SIZE); 575 576 struct mlx5e_rq_mbuf { 577 bus_dmamap_t dma_map; 578 caddr_t data; 579 struct mbuf *mbuf; 580 }; 581 582 struct mlx5e_rq { 583 /* data path */ 584 struct mlx5_wq_ll wq; 585 struct mtx mtx; 586 bus_dma_tag_t dma_tag; 587 u32 wqe_sz; 588 u32 nsegs; 589 struct mlx5e_rq_mbuf *mbuf; 590 struct ifnet *ifp; 591 struct mlx5e_rq_stats stats; 592 struct mlx5e_cq cq; 593 struct lro_ctrl lro; 594 volatile int enabled; 595 int ix; 596 597 /* Dynamic Interrupt Moderation */ 598 struct net_dim dim; 599 600 /* control */ 601 struct mlx5_wq_ctrl wq_ctrl; 602 u32 rqn; 603 struct mlx5e_channel *channel; 604 struct callout watchdog; 605 } __aligned(MLX5E_CACHELINE_SIZE); 606 607 struct mlx5e_sq_mbuf { 608 bus_dmamap_t dma_map; 609 struct mbuf *mbuf; 610 u32 num_bytes; 611 u32 num_wqebbs; 612 }; 613 614 enum { 615 MLX5E_SQ_READY, 616 MLX5E_SQ_FULL 617 }; 618 619 struct mlx5e_snd_tag { 620 struct m_snd_tag m_snd_tag; /* send tag */ 621 u32 type; /* tag type */ 622 }; 623 624 struct mlx5e_sq { 625 /* data path */ 626 struct mtx lock; 627 bus_dma_tag_t dma_tag; 628 struct mtx comp_lock; 629 630 /* dirtied @completion */ 631 u16 cc; 632 633 /* dirtied @xmit */ 634 u16 pc __aligned(MLX5E_CACHELINE_SIZE); 635 u16 bf_offset; 636 u16 cev_counter; /* completion event counter */ 637 u16 cev_factor; /* completion event factor */ 638 u16 cev_next_state; /* next completion event state */ 639 #define MLX5E_CEV_STATE_INITIAL 0 /* timer not started */ 640 #define MLX5E_CEV_STATE_SEND_NOPS 1 /* send NOPs */ 641 #define MLX5E_CEV_STATE_HOLD_NOPS 2 /* don't send NOPs yet */ 642 u16 running; /* set if SQ is running */ 643 struct callout cev_callout; 644 union { 645 u32 d32[2]; 646 u64 d64; 647 } doorbell; 648 struct mlx5e_sq_stats stats; 649 650 struct mlx5e_cq cq; 651 652 /* pointers to per packet info: write@xmit, read@completion */ 653 struct mlx5e_sq_mbuf *mbuf; 654 struct buf_ring *br; 655 656 /* read only */ 657 struct mlx5_wq_cyc wq; 658 struct mlx5_uar uar; 659 struct ifnet *ifp; 660 u32 sqn; 661 u32 bf_buf_size; 662 u32 mkey_be; 663 u16 max_inline; 664 u8 min_inline_mode; 665 u8 min_insert_caps; 666 #define MLX5E_INSERT_VLAN 1 667 #define MLX5E_INSERT_NON_VLAN 2 668 669 /* control path */ 670 struct mlx5_wq_ctrl wq_ctrl; 671 struct mlx5e_priv *priv; 672 int tc; 673 } __aligned(MLX5E_CACHELINE_SIZE); 674 675 static inline bool 676 mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) 677 { 678 u16 cc = sq->cc; 679 u16 pc = sq->pc; 680 681 return ((sq->wq.sz_m1 & (cc - pc)) >= n || cc == pc); 682 } 683 684 static inline u32 685 mlx5e_sq_queue_level(struct mlx5e_sq *sq) 686 { 687 u16 cc; 688 u16 pc; 689 690 if (sq == NULL) 691 return (0); 692 693 cc = sq->cc; 694 pc = sq->pc; 695 696 return (((sq->wq.sz_m1 & (pc - cc)) * 697 IF_SND_QUEUE_LEVEL_MAX) / sq->wq.sz_m1); 698 } 699 700 struct mlx5e_channel { 701 /* data path */ 702 struct mlx5e_rq rq; 703 struct mlx5e_snd_tag tag; 704 struct mlx5e_sq sq[MLX5E_MAX_TX_NUM_TC]; 705 u32 mkey_be; 706 u8 num_tc; 707 708 /* control */ 709 struct mlx5e_priv *priv; 710 int ix; 711 int cpu; 712 } __aligned(MLX5E_CACHELINE_SIZE); 713 714 enum mlx5e_traffic_types { 715 MLX5E_TT_IPV4_TCP, 716 MLX5E_TT_IPV6_TCP, 717 MLX5E_TT_IPV4_UDP, 718 MLX5E_TT_IPV6_UDP, 719 MLX5E_TT_IPV4_IPSEC_AH, 720 MLX5E_TT_IPV6_IPSEC_AH, 721 MLX5E_TT_IPV4_IPSEC_ESP, 722 MLX5E_TT_IPV6_IPSEC_ESP, 723 MLX5E_TT_IPV4, 724 MLX5E_TT_IPV6, 725 MLX5E_TT_ANY, 726 MLX5E_NUM_TT, 727 }; 728 729 enum { 730 MLX5E_RQT_SPREADING = 0, 731 MLX5E_RQT_DEFAULT_RQ = 1, 732 MLX5E_NUM_RQT = 2, 733 }; 734 735 struct mlx5_flow_rule; 736 737 struct mlx5e_eth_addr_info { 738 u8 addr [ETH_ALEN + 2]; 739 u32 tt_vec; 740 /* flow table rule per traffic type */ 741 struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT]; 742 }; 743 744 #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE) 745 746 struct mlx5e_eth_addr_hash_node; 747 748 struct mlx5e_eth_addr_hash_head { 749 struct mlx5e_eth_addr_hash_node *lh_first; 750 }; 751 752 struct mlx5e_eth_addr_db { 753 struct mlx5e_eth_addr_hash_head if_uc[MLX5E_ETH_ADDR_HASH_SIZE]; 754 struct mlx5e_eth_addr_hash_head if_mc[MLX5E_ETH_ADDR_HASH_SIZE]; 755 struct mlx5e_eth_addr_info broadcast; 756 struct mlx5e_eth_addr_info allmulti; 757 struct mlx5e_eth_addr_info promisc; 758 bool broadcast_enabled; 759 bool allmulti_enabled; 760 bool promisc_enabled; 761 }; 762 763 enum { 764 MLX5E_STATE_ASYNC_EVENTS_ENABLE, 765 MLX5E_STATE_OPENED, 766 }; 767 768 enum { 769 MLX5_BW_NO_LIMIT = 0, 770 MLX5_100_MBPS_UNIT = 3, 771 MLX5_GBPS_UNIT = 4, 772 }; 773 774 struct mlx5e_vlan_db { 775 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 776 struct mlx5_flow_rule *active_vlans_ft_rule[VLAN_N_VID]; 777 struct mlx5_flow_rule *untagged_ft_rule; 778 struct mlx5_flow_rule *any_cvlan_ft_rule; 779 struct mlx5_flow_rule *any_svlan_ft_rule; 780 bool filter_disabled; 781 }; 782 783 struct mlx5e_flow_table { 784 int num_groups; 785 struct mlx5_flow_table *t; 786 struct mlx5_flow_group **g; 787 }; 788 789 struct mlx5e_flow_tables { 790 struct mlx5_flow_namespace *ns; 791 struct mlx5e_flow_table vlan; 792 struct mlx5e_flow_table main; 793 struct mlx5e_flow_table inner_rss; 794 }; 795 796 #ifdef RATELIMIT 797 #include "en_rl.h" 798 #endif 799 800 #define MLX5E_TSTMP_PREC 10 801 802 struct mlx5e_clbr_point { 803 uint64_t base_curr; 804 uint64_t base_prev; 805 uint64_t clbr_hw_prev; 806 uint64_t clbr_hw_curr; 807 u_int clbr_gen; 808 }; 809 810 struct mlx5e_priv { 811 struct mlx5_core_dev *mdev; /* must be first */ 812 813 /* priv data path fields - start */ 814 int order_base_2_num_channels; 815 int queue_mapping_channel_mask; 816 int num_tc; 817 int default_vlan_prio; 818 /* priv data path fields - end */ 819 820 unsigned long state; 821 int gone; 822 #define PRIV_LOCK(priv) sx_xlock(&(priv)->state_lock) 823 #define PRIV_UNLOCK(priv) sx_xunlock(&(priv)->state_lock) 824 #define PRIV_LOCKED(priv) sx_xlocked(&(priv)->state_lock) 825 struct sx state_lock; /* Protects Interface state */ 826 struct mlx5_uar cq_uar; 827 u32 pdn; 828 u32 tdn; 829 struct mlx5_core_mr mr; 830 volatile unsigned int channel_refs; 831 832 u32 tisn[MLX5E_MAX_TX_NUM_TC]; 833 u32 rqtn; 834 u32 tirn[MLX5E_NUM_TT]; 835 836 struct mlx5e_flow_tables fts; 837 struct mlx5e_eth_addr_db eth_addr; 838 struct mlx5e_vlan_db vlan; 839 840 struct mlx5e_params params; 841 struct mlx5e_params_ethtool params_ethtool; 842 union mlx5_core_pci_diagnostics params_pci; 843 union mlx5_core_general_diagnostics params_general; 844 struct mtx async_events_mtx; /* sync hw events */ 845 struct work_struct update_stats_work; 846 struct work_struct update_carrier_work; 847 struct work_struct set_rx_mode_work; 848 MLX5_DECLARE_DOORBELL_LOCK(doorbell_lock) 849 850 struct ifnet *ifp; 851 struct sysctl_ctx_list sysctl_ctx; 852 struct sysctl_oid *sysctl_ifnet; 853 struct sysctl_oid *sysctl_hw; 854 int sysctl_debug; 855 struct mlx5e_stats stats; 856 int counter_set_id; 857 858 struct workqueue_struct *wq; 859 860 eventhandler_tag vlan_detach; 861 eventhandler_tag vlan_attach; 862 struct ifmedia media; 863 int media_status_last; 864 int media_active_last; 865 866 struct callout watchdog; 867 #ifdef RATELIMIT 868 struct mlx5e_rl_priv_data rl; 869 #endif 870 871 struct callout tstmp_clbr; 872 int clbr_done; 873 int clbr_curr; 874 struct mlx5e_clbr_point clbr_points[2]; 875 u_int clbr_gen; 876 877 struct pfil_head *pfil; 878 struct mlx5e_channel channel[]; 879 }; 880 881 #define MLX5E_NET_IP_ALIGN 2 882 883 struct mlx5e_tx_wqe { 884 struct mlx5_wqe_ctrl_seg ctrl; 885 struct mlx5_wqe_eth_seg eth; 886 }; 887 888 struct mlx5e_rx_wqe { 889 struct mlx5_wqe_srq_next_seg next; 890 struct mlx5_wqe_data_seg data[]; 891 }; 892 893 /* the size of the structure above must be power of two */ 894 CTASSERT(powerof2(sizeof(struct mlx5e_rx_wqe))); 895 896 struct mlx5e_eeprom { 897 int lock_bit; 898 int i2c_addr; 899 int page_num; 900 int device_addr; 901 int module_num; 902 int len; 903 int type; 904 int page_valid; 905 u32 *data; 906 }; 907 908 #define MLX5E_FLD_MAX(typ, fld) ((1ULL << __mlx5_bit_sz(typ, fld)) - 1ULL) 909 910 int mlx5e_xmit(struct ifnet *, struct mbuf *); 911 912 int mlx5e_open_locked(struct ifnet *); 913 int mlx5e_close_locked(struct ifnet *); 914 915 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, int event); 916 void mlx5e_rx_cq_comp(struct mlx5_core_cq *); 917 void mlx5e_tx_cq_comp(struct mlx5_core_cq *); 918 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); 919 920 void mlx5e_dim_work(struct work_struct *); 921 void mlx5e_dim_build_cq_param(struct mlx5e_priv *, struct mlx5e_cq_param *); 922 923 int mlx5e_open_flow_table(struct mlx5e_priv *priv); 924 void mlx5e_close_flow_table(struct mlx5e_priv *priv); 925 void mlx5e_set_rx_mode_core(struct mlx5e_priv *priv); 926 void mlx5e_set_rx_mode_work(struct work_struct *work); 927 928 void mlx5e_vlan_rx_add_vid(void *, struct ifnet *, u16); 929 void mlx5e_vlan_rx_kill_vid(void *, struct ifnet *, u16); 930 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); 931 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); 932 int mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv); 933 void mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv); 934 935 static inline void 936 mlx5e_tx_notify_hw(struct mlx5e_sq *sq, u32 *wqe, int bf_sz) 937 { 938 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; 939 940 /* ensure wqe is visible to device before updating doorbell record */ 941 wmb(); 942 943 *sq->wq.db = cpu_to_be32(sq->pc); 944 945 /* 946 * Ensure the doorbell record is visible to device before ringing 947 * the doorbell: 948 */ 949 wmb(); 950 951 if (bf_sz) { 952 __iowrite64_copy(sq->uar.bf_map + ofst, wqe, bf_sz); 953 954 /* flush the write-combining mapped buffer */ 955 wmb(); 956 957 } else { 958 mlx5_write64(wqe, sq->uar.map + ofst, 959 MLX5_GET_DOORBELL_LOCK(&sq->priv->doorbell_lock)); 960 } 961 962 sq->bf_offset ^= sq->bf_buf_size; 963 } 964 965 static inline void 966 mlx5e_cq_arm(struct mlx5e_cq *cq, spinlock_t *dblock) 967 { 968 struct mlx5_core_cq *mcq; 969 970 mcq = &cq->mcq; 971 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, dblock, cq->wq.cc); 972 } 973 974 static inline void 975 mlx5e_ref_channel(struct mlx5e_priv *priv) 976 { 977 978 KASSERT(priv->channel_refs < INT_MAX, 979 ("Channel refs will overflow")); 980 atomic_fetchadd_int(&priv->channel_refs, 1); 981 } 982 983 static inline void 984 mlx5e_unref_channel(struct mlx5e_priv *priv) 985 { 986 987 KASSERT(priv->channel_refs > 0, 988 ("Channel refs is not greater than zero")); 989 atomic_fetchadd_int(&priv->channel_refs, -1); 990 } 991 992 extern const struct ethtool_ops mlx5e_ethtool_ops; 993 void mlx5e_create_ethtool(struct mlx5e_priv *); 994 void mlx5e_create_stats(struct sysctl_ctx_list *, 995 struct sysctl_oid_list *, const char *, 996 const char **, unsigned, u64 *); 997 void mlx5e_send_nop(struct mlx5e_sq *, u32); 998 void mlx5e_sq_cev_timeout(void *); 999 int mlx5e_refresh_channel_params(struct mlx5e_priv *); 1000 int mlx5e_open_cq(struct mlx5e_priv *, struct mlx5e_cq_param *, 1001 struct mlx5e_cq *, mlx5e_cq_comp_t *, int eq_ix); 1002 void mlx5e_close_cq(struct mlx5e_cq *); 1003 void mlx5e_free_sq_db(struct mlx5e_sq *); 1004 int mlx5e_alloc_sq_db(struct mlx5e_sq *); 1005 int mlx5e_enable_sq(struct mlx5e_sq *, struct mlx5e_sq_param *, int tis_num); 1006 int mlx5e_modify_sq(struct mlx5e_sq *, int curr_state, int next_state); 1007 void mlx5e_disable_sq(struct mlx5e_sq *); 1008 void mlx5e_drain_sq(struct mlx5e_sq *); 1009 void mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value); 1010 void mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value); 1011 void mlx5e_resume_sq(struct mlx5e_sq *sq); 1012 void mlx5e_update_sq_inline(struct mlx5e_sq *sq); 1013 void mlx5e_refresh_sq_inline(struct mlx5e_priv *priv); 1014 1015 #endif /* _MLX5_EN_H_ */ 1016